BT136X_SERIES_D [ETC]
Triacs logic level ; 三端双向可控硅逻辑电平\n
| 型号： | BT136X_SERIES_D |
| 厂家： | 
ETC |
| 描述： | Triacs logic level
|
| 文件： | 总6页 (文件大小：44K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
Triacs
logic level
BT136X series D
GENERAL DESCRIPTION
QUICK REFERENCE DATA
Passivated, sensitive gate triacs in a full
pack plastic envelope, intended for use
SYMBOL
PARAMETER
MAX. UNIT
in
switching
applications.These devicesareintended
general
purpose
bidirectional
BT136X- 600D
and phase
control
VDRM
IT(RMS)
ITSM
Repetitive peak off-state voltages
RMS on-state current
Non-repetitive peak on-state current
600
4
V
A
A
to
be
interfaced directly
to
25
microcontrollers, logic integrated circuits
and other low power gate trigger circuits.
PINNING - SOT186A
PIN CONFIGURATION
SYMBOL
PIN
1
DESCRIPTION
main terminal 1
case
T2
T1
2
main terminal 2
gate
3
G
1
2 3
case isolated
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134).
SYMBOL PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
V
-600
600
VDRM
Repetitive peak off-state
voltages
-
-
IT(RMS)
ITSM
RMS on-state current
Non-repetitive peak
on-state current
full sine wave; Ths ≤ 92 ˚C
full sine wave; Tj = 25 ˚C prior to
surge
4
A
t = 20 ms
-
-
-
25
27
3.1
A
A
t = 16.7 ms
I2t
dIT/dt
I2t for fusing
Repetitive rate of rise of
on-state current after
triggering
t = 10 ms
A2s
ITM = 6 A; IG = 0.2 A;
dIG/dt = 0.2 A/µs
T2+ G+
-
50
50
50
10
2
5
5
0.5
150
125
A/µs
A/µs
A/µs
A/µs
A
T2+ G-
-
T2- G-
-
T2- G+
-
IGM
Peak gate current
Peak gate voltage
Peak gate power
Average gate power
Storage temperature
Operating junction
temperature
-
VGM
PGM
PG(AV)
Tstg
Tj
-
V
-
-
W
over any 20 ms period
W
-40
-
˚C
˚C
June 2001
1
Rev 1.400
Philips Semiconductors
Product specification
Triacs
logic level
BT136X series D
ISOLATION LIMITING VALUE & CHARACTERISTIC
Ths = 25 ˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Visol
Cisol
R.M.S. isolation voltage from all f = 50-60 Hz; sinusoidal
-
-
2500
V
three terminals to external
heatsink
waveform;
R.H. ≤ 65% ; clean and dustfree
Capacitance from T2 to external f = 1 MHz
heatsink
-
10
-
pF
THERMAL RESISTANCES
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Rth j-hs
Rth j-a
Thermal resistance
junction to heatsink
full or half cycle
with heatsink compound
without heatsink compound
in free air
-
-
-
-
-
55
5.5
7.2
-
K/W
K/W
K/W
Thermal resistance
junction to ambient
STATIC CHARACTERISTICS
Tj = 25 ˚C unless otherwise stated
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
IGT
Gate trigger current
VD = 12 V; IT = 0.1 A
T2+ G+
T2+ G-
T2- G-
T2- G+
-
-
-
-
2.0
2.5
2.5
5.0
5
5
mA
mA
mA
mA
5
10
IL
Latching current
VD = 12 V; IGT = 0.1 A
T2+ G+
T2+ G-
T2- G-
T2- G+
-
1.6
4.5
1.2
2.2
1.2
1.4
0.7
0.4
0.1
10
15
mA
mA
mA
mA
mA
V
-
-
10
-
15
IH
VT
VGT
Holding current
On-state voltage
Gate trigger voltage
VD = 12 V; IGT = 0.1 A
IT = 5 A
-
10
-
1.70
1.5
-
VD = 12 V; IT = 0.1 A
-
0.25
-
V
VD = 400 V; IT = 0.1 A; Tj = 125 ˚C
V
ID
Off-state leakage current VD = VDRM(max); Tj = 125 ˚C
0.5
mA
DYNAMIC CHARACTERISTICS
Tj = 25 ˚C unless otherwise stated
SYMBOL PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
dVD/dt
Critical rate of rise of
off-state voltage
Gate controlled turn-on
time
VDM = 67% VDRM(max); Tj = 125 ˚C;
exponential waveform; RGK = 1 kΩ
ITM = 6 A; VD = VDRM(max); IG = 0.1 A;
dIG/dt = 5 A/µs
-
5
-
V/µs
tgt
-
2
-
µs
June 2001
2
Rev 1.400
Philips Semiconductors
Product specification
Triacs
logic level
BT136X series D
Ptot / W
8
Ths(max) / C
IT(RMS) / A
5
4
3
2
1
0
81
86.5
92
7
92 C
= 180
120
1
6
97.5
5
4
3
2
1
0
90
60
103
30
108.5
114
119.5
125
0
1
2
3
4
5
-50
0
50
100
150
IT(RMS) / A
Ths / C
Fig.1. Maximum on-state dissipation, Ptot, versus rms
on-state current, IT(RMS), where α = conduction angle.
Fig.4. Maximum permissible rms current IT(RMS)
versus heatsink temperature Ths.
,
IT(RMS) / A
12
ITSM / A
1000
I
TSM
time
I
T
10
8
T
Tj initial = 25 C max
100
6
dIT/dt limit
4
T2- G+ quadrant
2
10
10us
0
100us
1ms
T / s
10ms
100ms
0.01
0.1
surge duration / s
1
10
Fig.2. Maximum permissible non-repetitive peak
on-state current ITSM, versus pulse width tp, for
sinusoidal currents, tp ≤ 20ms.
Fig.5. Maximum permissible repetitive rms on-state
current IT(RMS), versus surge duration, for sinusoidal
currents, f = 50 Hz; Ths ≤ 92˚C.
VGT(Tj)
VGT(25 C)
ITSM / A
30
25
20
15
10
5
1.6
I
TSM
time
I
T
1.4
1.2
1
T
Tj initial = 25 C max
0.8
0.6
0.4
0
1
10
100
1000
-50
0
50
Tj / C
100
150
Number of cycles at 50Hz
Fig.3. Maximum permissible non-repetitive peak
on-state current ITSM, versus number of cycles, for
sinusoidal currents, f = 50 Hz.
Fig.6. Normalised gate trigger voltage
VGT(Tj)/ VGT(25˚C), versus junction temperature Tj.
June 2001
3
Rev 1.400
Philips Semiconductors
Product specification
Triacs
logic level
BT136X series D
IGT(Tj)
IGT(25 C)
IT / A
12
10
8
Tj = 125 C
Tj = 25 C
3
T2+ G+
T2+ G-
T2- G-
T2- G+
typ
max
2.5
2
Vo = 1.27 V
Rs = 0.091 ohms
6
1.5
1
4
2
0.5
0
0
0
0.5
1
1.5
VT / V
2
2.5
3
-50
0
50
Tj / C
100
150
Fig.7. Normalised gate trigger current
IGT(Tj)/ IGT(25˚C), versus junction temperature Tj.
Fig.10. Typical and maximum on-state characteristic.
Zth j-hs (K/W)
10
IL(Tj)
IL(25 C)
with heatsink compound
3
without heatsink compound
2.5
2
unidirectional
1
bidirectional
1.5
1
t
P
D
0.1
p
t
0.5
0
0.01
10us
0.1ms
1ms
10ms
tp / s
0.1s
1s
10s
-50
0
50
Tj / C
100
150
Fig.8. Normalised latching current IL(Tj)/ IL(25˚C),
Fig.11. Transient thermal impedance Zth j-hs, versus
pulse width tp.
versus junction temperature Tj.
dVD/dt (V/us)
1000
IH(Tj)
IH(25C)
3
2.5
2
100
10
1
1.5
1
0.5
0
-50
0
50
100
150
0
50
100
150
Tj / C
Tj / C
Fig.9. Normalised holding current IH(Tj)/ IH(25˚C),
Fig.12. Typical, critical rate of rise of off-state voltage,
dVD/dt versus junction temperature Tj.
versus junction temperature Tj.
June 2001
4
Rev 1.400
Philips Semiconductors
Product specification
Triacs
logic level
BT136X series D
MECHANICAL DATA
Dimensions in mm
Net Mass: 2 g
10.3
max
4.6
max
3.2
3.0
2.9 max
2.8
Recesses (2x)
6.4
2.5
0.8 max. depth
15.8
max
seating
plane
15.8
max.
19
max.
3 max.
not tinned
3
2.5
13.5
min.
1
2
3
M
0.4
1.0 (2x)
0.6
2.5
0.9
0.7
2.54
0.5
5.08
1.3
Fig.13. SOT186A; The seating plane is electrically isolated from all terminals.
Notes
1. Refer to mounting instructions for F-pack envelopes.
2. Epoxy meets UL94 V0 at 1/8".
June 2001
5
Rev 1.400
Philips Semiconductors
Product specification
Triacs
logic level
BT136X series D
DEFINITIONS
DATA SHEET STATUS
DATA SHEET
STATUS1
PRODUCT
DEFINITIONS
STATUS2
Objective data
Development
This data sheet contains data from the objective specification for
product development. Philips Semiconductors reserves the right to
change the specification in any manner without notice
Preliminary data
Qualification
Production
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in ordere to improve the design and supply the best possible
product
Product data
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in
order to improve the design, manufacturing and supply. Changes will
be communicated according to the Customer Product/Process
Change Notification (CPCN) procedure SNW-SQ-650A
Limiting values
Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and
operation of the device at these or at any other conditions above those given in the Characteristics sections of
this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
Philips Electronics N.V. 2001
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the
copyright owner.
The information presented in this document does not form part of any quotation or contract, it is believed to be
accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under patent or other
industrial or intellectual property rights.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these
products can be reasonably expected to result in personal injury. Philips customers using or selling these products
for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting
from such improper use or sale.
1 Please consult the most recently issued datasheet before initiating or completing a design.
2 The product status of the device(s) described in this datasheet may have changed since this datasheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
June 2001
6
Rev 1.400
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