AT93C86-10PI-2.7 [ETC]
Microwire Serial EEPROM ; Microwire串行EEPROM\n
| 型号： | AT93C86-10PI-2.7 |
| 厂家： | 
ETC |
| 描述： | Microwire Serial EEPROM
|
| 文件： | 总11页 (文件大小：165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Low-voltage and Standard-voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
• User Selectable Internal Organization
– 16K: 2048 x 8 or 1024 x 16
• 3-wire Serial Interface
• Sequential Read Operation
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• 2 MHz Clock Rate (5V) Compatibility
• Self-timed Write Cycle (10 ms max)
• High Reliability
3-wire Serial
EEPROM
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
– ESD Protection: >4000V
16K (2048 x 8 or 1024 x 16)
• Automotive Grade and Extended Temperature Devices Available
• 8-pin PDIP, 8-pin JEDEC SOIC, and 8-pin TSSOP Packages
Description
AT93C86
The AT93C86 provides 16384 bits of serial electrically erasable programmable read
only memory (EEPROM) organized as 1024 words of 16 bits each when the ORG Pin
is connected to VCC and 2048 words of 8 bits each when it is tied to ground. The
device is optimized for use in many industrial and commercial applications where low
power and low voltage operations are essential. The AT93C86 is available in space
saving 8-pin PDIP, 8-pin JEDEC SOIC and 8-pin TSSOP packages.
(continued)
Pin Configurations
Pin Name Function
8-pin PDIP
CS
Chip Select
CS
SK
DI
1
2
3
4
8
7
6
5
VCC
DC
SK
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
ORG
GND
DI
DO
DO
GND
VCC
ORG
DC
Power Supply
8-pin SOIC
Internal Organization
Don’t Connect
CS
1
2
3
4
8
7
6
5
VCC
SK
DI
DC
ORG
GND
DO
8-pin TSSOP
CS
1
2
3
4
8
7
6
5
VCC
DC
SK
DI
ORG
GND
Rev. 1237B–06/01
DO
The AT93C86 is enabled through the Chip Select pin (CS),
and accessed via a 3-wire serial interface consisting of
Data Input (DI), Data Output (DO), and Shift Clock (SK).
Upon receiving a READ instruction at DI, the address is
decoded and the data is clocked out serially on the data
output pin DO. The WRITE cycle is completely self-timed
and no separate ERASE cycle is required before WRITE.
The WRITE cycle is only enabled when the part is in the
ERASE/WRITE ENABLE state. When CS is brought “high”
following the initiation of a WRITE cycle, the DO pin out-
puts the READY/BUSY status of the part.
The AT93C86 is available in 4.5V to 5.5V and 2.7V to 5.5V
versions.
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Operating Temperature.................................. -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on any Pin
with Respect to Ground.....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Block Diagram
Vcc
GND
MEMORY ARRAY
ADDRESS
DECODER
2048 x 8
OR
ORG
1024 x 16
DATA
REGISTER
OUTPUT
BUFFER
DI
MODE
DECODE
LOGIC
CS
CLOCK
GENERATOR
DO
SK
Note:
1. When the ORG pin is connected to Vcc, the x 16 organization is selected. When it is connected to ground, the x 8 organiza-
tion is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the
internal 1 Meg ohm pullup, then the x 16 organization is selected. This feature is not available on the 1.8V devices.
2
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
Symbol
COUT
CIN
Test Conditions
Max
5
Units
pF
Conditions
VOUT = 0V
VIN = 0V
Output Capacitance (DO)
Input Capacitance (CS, SK, DI)
5
pF
Note:
1. This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +2.7V to +5.5V,
TAC = 0°C to +70°C, VCC = +2.7V to +5.5V (unless otherwise noted).
Symbol
VCC1
Parameter
Test Condition
Min
2.7
4.5
Typ
Max
5.5
Unit
V
Supply Voltage
Supply Voltage
VCC2
5.5
V
READ at 1.0 MHz
WRITE at 1.0 MHz
CS = 0V
0.5
0.5
6.0
17
2.0
mA
mA
µA
µA
µA
µA
ICC
Supply Current
VCC = 5.0V
2.0
ISB1
ISB2
IIL
Standby Current
Standby Current
Input Leakage
VCC = 2.7V
10.0
30
VCC = 5.0V
CS = 0V
VIN = 0V to VCC
VIN = 0V to VCC
0.1
0.1
1.0
IOL
Output Leakage
1.0
(1)
VIL1
VIH1
Input Low Voltage
Input High Voltage
-0.6
CC x 0.7
VCC x 0.3
4.5V ≤ VCC ≤ 5.5V
VCC ≤ 2.7V
V
V
(1)
V
VCC + 1
(1)
VIL2
VIH2
Input Low Voltage
Input High Voltage
-0.6
VCC x 0.3
(1)
VCC x 0.7
2.4
VCC + 1
0.4
IOL = 2.1 mA
V
V
V
V
VOL1
VOH1
Output Low Voltage
Output High Voltage
4.5V ≤ VCC ≤ 5.5V
VCC ≤ 2.7V
IOH = -0.4 mA
IOL = 0.15 mA
IOH = -100 µA
0.2
VOL2
VOH2
Output Low Voltage
Output High Voltage
VCC - 0.2
Note:
1. VIL min and VIH max are reference only and are not tested.
3
AC Characteristics
Applicable over recommended operating range from TA = -40°C to + 85°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol
Parameter
Test Condition
Min
Typ
Max
Units
SK Clock
Frequency
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
0
0
2
1
fSK
MHz
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
tSKH
tSKL
tCS
SK High Time
SK Low Time
ns
ns
ns
ns
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
Minimum CS
Low Time
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
50
50
tCSS
CS Setup Time
Relative to SK
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
100
100
tDIS
tCSH
tDIH
DI Setup Time
CS Hold Time
DI Hold Time
Relative to SK
Relative to SK
Relative to SK
ns
ns
ns
0
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
100
100
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
tPD1
tPD0
tSV
Output Delay to ‘1’
Output Delay to ‘0’
CS to Status Valid
AC Test
AC Test
AC Test
ns
ns
ns
ns
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
250
250
CS to DO in High
Impedance
AC Test
CS = VIL
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
100
100
tDF
0.1
1M
10
ms
ms
tWP
Write Cycle Time
4.5V ≤ VCC ≤ 5.5V
4
Endurance(1)
5.0V, 25°C, Page Mode
Write Cycles
Note:
1. This parameter is characterized and is not 100% tested.
Instruction Set for the AT93C86
Address
Data
Instruction
SB
Op Code
x 8
x 16
x 8
x 16
Comments
READ
1
10
A
10 - A0
A9 - A0
Reads data stored in memory,
at specified address.
EWEN
1
00
11XXXXXXXX
11XXXXXXXX
Write enable must precede all
programming modes.
ERASE
WRITE
1
1
11
01
A10 - A0
A10 - A0
A9 - A0
A9 - A0
Erases memory location An - A0.
D7 - D0
D15 - D0 Writes memory location An - A0.
4
Instruction Set for the AT93C86
Address
Data
Instruction
SB
Op Code
x 8
x 16
x 8
x 16
Comments
ERAL
1
00
10XXXXXXXX
10XXXXXXXX
Erases all memory locations.
Valid only at VCC = 4.5V to 5.5V.
WRAL
EWDS
1
1
00
00
01XXXXXXXX
01XXXXXXXX
00XXXXXXXX
D7 - D0
D15 - D0 Writes all memory locations.
Valid when VCC = 4.5V to 5.5V and
Disable Register cleared.
00XXXXXXXX
Disables all programming instructions.
Functional Description
The AT93C86 is accessed via a simple and versatile 3-wire
serial communication interface. Device operation is con-
trolled by seven instructions issued by the host processor.
A valid instruction starts with a rising edge of CS and
consists of a Start Bit (logic “1”) followed by the appropriate
Op Code and the desired memory Address location.
WRITE (WRITE): The Write (WRITE) instruction contains
the 8 or 16 bits of data to be written into the specified mem-
ory location. The self-timed programming cycle, tWP, starts
after the last bit of data is received at serial data input pin
DI. The DO pin outputs the READY/BUSY status of the part
if CS is brought high after being kept low for a minimum of
250 ns (tCS). A logic “0” at DO indicates that programming
is still in progress. A logic “1” indicates that the memory
location at the specified address has been written with the
data pattern contained in the instruction and the part is
ready for further instructions. A READY/BUSY status can-
not be obtained if the CS is brought high after the end
READ (READ): The Read (READ) instruction contains
the Address code for the memory location to be read. After
the instruction and address are decoded, data from the
selected memory location is available at the serial output
pin DO. Output data changes are synchronized with the ris-
ing edges of serial clock SK. It should be noted that a
dummy bit (logic “0”) precedes the 8- or 16-bit data output
string.
of the self-timed programming cycle, tWP
.
ERASE ALL (ERAL): The Erase All (ERAL) instruction
programs every bit in the memory array to the logic “1”
state and is primarily used for testing purposes. The DO pin
outputs the READY/BUSY status of the part if CS is
brought high after being kept low for a minimum of 250 ns
(tCS). The ERAL instruction is valid only at VCC = 5.0V
10%.
ERASE/WRITE (EWEN): To assure data integrity, the
part automatically goes into the Erase/Write Disable
(EWDS) state when power is first applied. An Erase/Write
Enable (EWEN) instruction must be executed first before
any programming instructions can be carried out. Please
note that once in the Erase/Write Enable state, program-
ming remains enabled until an Erase/Write Disable
(EWDS) instruction is executed or VCC power is removed
from the part.
WRITE ALL (WRAL): The Write All (WRAL) instruction
programs all memory locations with the data patterns spec-
ified in the instruction. The DO pin outputs the
READY/BUSY status of the part if CS is brought high after
being kept low for a minimum of 250 ns (tCS). The WRAL
instruction is valid only at VCC = 5.0V 10%.
ERASE (ERASE): The Erase (ERASE) instruction pro-
grams all bits in the specified memory location to the logical
“1” state. The self-timed erase cycle starts once the
ERASE instruction and address are decoded. The DO pin
outputs the READY/BUSY status of the part if CS is
brought high after being kept low for a minimum of 250 ns
(tCS). A logic “1” at pin DO indicates that the selected mem-
ory location has been erased, and the part is ready for
another instruction.
ERASE/WRITE DISABLE (EWDS): To protect against
accidental data disturb, the Erase/Write Disable (EWDS)
instruction disables all programming modes and should be
executed after all programming operations. The operation
of the READ instruction is independent of both the EWEN
and EWDS instructions and can be executed at any time.
5
Timing Diagrams
Synchronous Data Timing
Note:
1. This is the minimum SK period.
Organization Key for Timing Diagrams
AT93C86 (16K)
I/O
AN
DN
x 8
A10
D7
x 16
A9
D15
READ Timing
6
EWEN Timing
EWDS Timing
WRITE Timing
tCS
CS
SK
DI
...
1
0
0
1
1
tCS
CS
SK
DI
...
0
0
0
1
0
tCS
CS
SK
DI
...
...
AN
DN
1
0
1
A0
D0
HIGH IMPEDANCE
BUSY
READY
DO
tWP
WRAL Timing(1)
tCS
CS
SK
DI
1
0
0
0
1
...
DN ... D0
BUSY
HIGH IMPEDANCE
DO
READY
tWP
Note:
1. Valid only at VCC = 4.5V to 5.5V.
7
ERASE Timing
tCS
CS
STANDBY
CHECK
STATUS
SK
DI
A0
1
1
1
AN
...
AN-1 AN-2
tDF
tSV
HIGH IMPEDANCE
HIGH IMPEDANCE
BUSY
DO
READY
tWP
ERAL Timing(1)
tCS
CS
STANDBY
CHECK
STATUS
SK
DI
1
0
0
1
0
tDF
tSV
BUSY
HIGH IMPEDANCE
HIGH IMPEDANCE
DO
READY
tWP
Note:
1. Valid only at VCC = 4.5V to 5.5V.
8
AT93C86 Ordering Information
tWP (max)
ICC (max)
ISB (max)
fMAX
(ms)
(µA)
(µA)
(kHz)
Ordering Code
Package
Operation Range
10
2000
30.0
30.0
10.0
10.0
2000
2000
1000
1000
AT93C86-10PC
AT93C86-10SC
AT93C86-10TC
8P3
8S1
8T
Commercial
(0°C to 70°C)
AT93C86-10PI
AT93C86-10SI
AT93C86-10TI
8P3
8S1
8T
Industrial
(-40°C to 85°C)
10
800
AT93C86-10PC-2.7
AT93C86-10SC-2.7
AT93C86-10TC-2.7
8P3
8S1
8T
Commercial
(0°C to 70°C)
AT93C86-10PI-2.7
AT93C86-10SI-2.7
AT93C86-10TI-2.7
8P3
8S1
8T
Industrial
(-40°C to 85°C)
Package Type
8P3
8S1
8T
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
Blank
-2.7
Standard Operation (4.5V to 5.5V)
Low Voltage (2.7V to 5.5V)
9
Packaging Information
8P3, 8-Lead, 0.300" Wide, Plastic Dual Inline
Package (PDIP)
8S1, 8-Lead, 0.150" Wide, Plastic Gull Wing Small
Outline (JEDEC SOIC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-001 BA
Dimensions in Inches and (Millimeters)
.020 (.508)
.013 (.330)
.400 (10.16)
.355 (9.02)
PIN
1
.244 (6.20)
.228 (5.79)
.157 (3.99)
.150 (3.81)
.280 (7.11)
.240 (6.10)
PIN 1
.037 (.940)
.027 (.690)
.300 (7.62) REF
.210 (5.33) MAX
.050 (1.27) BSC
.100 (2.54) BSC
SEATING
PLANE
.196 (4.98)
.189 (4.80)
.068 (1.73)
.053 (1.35)
.015 (.380) MIN
.150 (3.81)
.115 (2.92)
.022 (.559)
.014 (.356)
.070 (1.78)
.045 (1.14)
.010 (.254)
.004 (.102)
.325 (8.26)
.300 (7.62)
0
0
8
REF
15
REF
.010 (.254)
.007 (.203)
.012 (.305)
.008 (.203)
.430 (10.9) MAX
.050 (1.27)
.016 (.406)
8T, 8-Lead, 0.170" Wide Thin Shrink Small Outline
Package (TSSOP)
Dimensions in Millimeters and (Inches)*
PIN 1
6.50 (.256)
6.25 (.246)
0.30 (.012)
0.19 (.008)
3.10 (.122)
2.90 (.114)
1.05 (.041)
0.80 (.033)
1.20 (.047) MAX
.65 (.026) BSC
0.15 (.006)
0.05 (.002)
4.5 (.177)
4.3 (.169)
0.20 (.008)
0.09 (.004)
0.75 (.030)
0.45 (.018)
0
8
REF
*Controlling dimension: millimeters
10
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© Atmel Corporation 1999.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-
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®
™
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Printed on recycled paper.
1237B–06/01/xM
相关型号：
AT93C86A-10PQ-2.7
EEPROM, 1KX16, Serial, CMOS, PDIP8, 0.300 INCH, LEAD AND HALOGEN FREE, PLASTIC, MS-001BA, DIP-8
ATMEL
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