AT88SC153-09HT-XX-2.7 [ETC]
EEPROM ; EEPROM\n
| 型号： | AT88SC153-09HT-XX-2.7 |
| 厂家： | 
ETC |
| 描述： | EEPROM
|
| 文件： | 总21页 (文件大小：426K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• One 64 x 8 (512 bit) Configuration Zone
• Three 64 x 8 (512 bit) User Zones
• Programmable Chip Select
• Low-voltage Operation: 2.7V to 5.5V
• Two-wire Serial Interface
• 8-byte Page Write Mode
• Self-timed Write Cycle (10 ms max)
• ISO 7816-3 Synchronous Protocol
• Answer-to-Reset Register
• High-security Memory Including Anti-wire Tapping
– 64-bit Authentication Protocol*
– Secure Checksum
3 x 64 x 8
Secure Memory
with
– Configurable Authentication Attempts Counter
– Two Sets of Two 24-bit Passwords
– Specific Passwords for Read and Write
– Four Password Attempts Counters
– Selectable Access Rights by Zone
• ISO Compliant Packaging
Authentication
• High Reliability
– Endurance: 100,000 Cycles
– Data Retention: 100 Years
– ESD Protection: 4,000V min
• Low-Power CMOS
AT88SC153
Description
The AT88SC153 provides 2,048 bits of serial EEPROM memory organized as one
configuration zone of 64 bytes and three user zones of 64 bytes each. This device is
optimized as a “secure memory” for multi-application smart card markets, secure
identification for electronic data transfer or for components in a system without the
requirement of an internal microprocessor.
The embedded authentication protocol allows the memory and the host to
authenticate each other. When this device is used with a host which incorporates a
microcontroller, e.g., AT89C51, AT89C2051, AT90S1200, the system provides an
“anti-wire tapping” configuration. The device and the host exchange “challenges”
issued from a random generator and verify their values through a specific
cryptographic function included in each part. When both agree on the same result, the
access to the memory is permitted.
Security Methodology
Rev. 1016B–11/99
*Under exclusive patent license from ELVA
Memory Access
Depending on the device configuration, the host might
carry out the authentication protocol, and/or present
different passwords for each operation: read or write. Each
user zone may be configured for free access for read and
write, or for password restricted access. To insure security
between the different user zones (multi-application card),
each zone can use a different set of passwords. A specific
attempts counter for each password and for the
authentication provides protection against “systematic
attacks”. When the memory is unlocked, the two-wire serial
protocol is effective, using SDA and SCL. The memory
includes a specific register providing a 32-bit data stream
conforming to the ISO 7816-3 synchronous Answer-to-
Reset.
Block Diagram
VCC
Pin Descriptions
capacitance loading the SDA bus will determine the rise
time of SDA. This rise time will determine the maximum
frequency during Read operations. Low value pull-up
resistors will allow higher frequency operations while
drawing higher average power supply current.
Supply Voltage (VCC)
The VCC input is a 2.7V to 5.5V positive voltage supplied
by the host.
Serial Clock (SCL)
The SCL input is used to positive edge clock data into the
device and negative edge clock data out of the device.
Reset (RST)
When the RST input is pulsed high, the device will output
the data programmed into the 32-bit answer-to-reset
register. All password and authentication access will be
reset. Following a reset, device authentication and
password verification sequences must be presented to re-
establish user access.
Serial Data (SDA)
The SDA pin is bi-directional for serial data transfer. This
pin is open-drain driven, and may be wire-ORed with any
number of other open drain or open collector devices. An
external pull up resistor should be connected between SDA
and VCC. The value of this resistor and the system
AT88SC153
2
AT88SC153
Memory Mapping
The 2,048 bits of the memory are divided in four zones of 64 bytes each:
Zone
$0
$1
$2
$3
$4
$5
$6
$7
@
$00
-
64 bytes
64 bytes
64 bytes
64 bytes
User 0
zz = 00
-
$38
$00
-
User 1
zz = 01
$38
$00
-
User 2
zz = 10
-
$38
$00
Configuration
zz = 11
$38
The last 64 bytes of the memory is a configuration zone with specific system data, access rights and read/write commands;
it is divided in four subzones(1).
Configuration
$0
$1
Answer-to-Reset
Fab Code
$2
$3
$4
$5
$6
$7
@
Lot History Code
$00
$08
$10
$18
$20
$28
$30
$38
Fabrication
CMC
AR0
AR1
AR2
MTZ
Issuer Code
Identification
DCR
Identification Number (Nc)
Cryptogram (Ci)
Secret Seed (Gc)
PAC
AAC(2)
Secret
PAC
PAC
Write 0
Read 0
Read 1
Passwords
Secure Code/Write 1
PAC
Notes: 1. CMC: Card Manufacturer Code.
AR0-2: Access Register for User Zone 0 to 2.
MTZ: Memory Test Zone.
DCR: Device Configuration Register.
AAC: Authentication Attempts Counter.
PAC: Password Attempts Counter.
zz: Zone number
2. Address $20 also serves as the virtual address of the Checksum Authentication Register (CAR) during checksum mode.
3
Fuses
• FAB, CMA and PER are nonvolatile fuses blown at the
end of each card life step. Once blown, these EEPROM
fuses can not be reset.
• The CMA fuse is blown by the card manufacturer prior to
shipping cards to the issuer.
• The PER fuse is blown by the issuer prior to shipping
• The FAB fuse is blown by Atmel prior to shipping wafers
to the card manufacturer.
cards to the end user.
The device responds to a Read Fuse command with “fuse byte”.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
PER
CMA
FAB
When the fuses are all 1’s, read and write are allowed in the entire memory. Before blowing the FAB fuse, Atmel writes the
entire memory to “1”, and programs the fabrication subzone (except CMC and AR) and the secure code.
Zone
Access
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
FAB = 0
Free
CMA = 0
Free
PER = 0
Free
Fabrication
(Except CMC, MTZ and AR)
Forbidden
Free
Forbidden
Free
Forbidden
Free
Card Manufacturer
Code
Secure Code
Free
Forbidden
Free
Forbidden
Free
Access Registers
Memory Test Zone
Identification
Secret
Secure Code
Free
Secure Code
Free
Forbidden
Free
Free
Free
Free
Free
Free
Free
Secure Code
Secure Code
Secure Code
Secure Code
Secure Code
Free
Secure Code
Secure Code
Secure Code
Secure Code
Secure Code
Free
Forbidden
Forbidden
Forbidden
Write PW
Write PW
Free
Passwords
PAC
Secure Code
AR
Secure Code
AR
Write PW
AR
User Zones
AR
AR
AR
Note:
CMC: Card Manufacturer Code.
AR: Access Rights as defined by the Access Registers.
PW: Password.
AT88SC153
4
AT88SC153
user zone. Read access to this zone is allowed without
authentication. This bit is ignored if ATE is enabled.
Configuration Zone
Answer-to-Reset
32-bit register defined by Atmel.
PWS - Password Select
This bit defines which of the two password sets must be
presented to allow access to the user zone. Each access
register may point to a unique password set, or access reg-
isters for multiple zones may point to the same password
set. In this case, verification of a single password will open
several zones, combining the zones into a single larger
zone.
Lot History Code
32-bit register defined by Atmel.
Fab Code
16-bit register defined by Atmel.
Card Manufacturer Code
16-bit register defined by the card manufacturer.
WLM - Write Lock Mode
Issuer Code
64-bit register defined by the card issuer.
If enabled (WLM = “0”), the eight bits of the first byte of
each user zone page will define the locked/unlocked status
for each byte in the page. Write access is forbidden to a
byte if its associated bit in byte 0 is set to “0”. Bit 7 controls
byte 7, bit 6 controls byte 6, etc.
Access Registers
Three 8-bit access registers defined by the issuer, one for
each user zone. (Active low)
MDF - Modify Forbidden
If enabled (MDF = “0”), no write access is allowed in the
zone at any time. The user zone must be written before the
PER is blown.
Bit 7
Bit 6
Bit 5
ATE
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPE RPE
AOW PWS WLM MDF PGO
PGO - Program Only
WPE - Write Password Enable
If enabled (PGO = “0”), data within the zone may be
changed from “1” to “0”, but never from “0” to “1”.
If enabled (WPE = “0”), the user is required to verify the
Write Password to allow write operations in the user zone.
If disabled (WPE = “1”), all write operations are allowed
within the zone. Verification of the Write password also
allows the Read and Write passwords to be changed.
Identification Number (Nc)
An identification number with up to 56-bits is defined by the
issuer and should be unique for each device.
RPE - Read Password Enable
Cryptogram (Ci)
If enabled (RPE = “0”), the user is required to verify either
the Read Password or Write Password to allow read
operations in the user zone. Read operations initiated
without a verified password will return $00 (or the status of
the fuse bits, if either CMA or PER are still intact).
Verification of the Write password will always allow read
access to the zone. RPE = “0” and WPE = “1” is allowed,
but is not recommended.
The 56-bit cryptogram is generated by the internal random
generator and modified after each successful verification of
the cryptogram by the chip, on host request. The initial
value, defined by the issuer, is diversified as a function of
the identification number. The 64 bits used in the Authenti-
cation protocol consist of the 56-bit cryptogram and the 8-
bit Authentication Attempts counter. Note that any change
in the AAC status will change Ci for the next authentication
attempt.
ATE - Authentication Enable
If enabled (ATE = “0”), a valid Authentication sequence is
required for both Read and Write and must be completed
before access is allowed to the user zone. If disabled (ATE
= “1”), authentication is not required for access.
Secret Seed (Gc)
The 64-bit secret seed, defined by the issuer, is diversified
as a function of the identification number.
AOW - Authentication Only for Write
Memory Test Zone
8-bit free access zone for memory and protocol test.
If enabled (AOW = “0”), a valid Authentication sequence
must be completed before write access is allowed to the
5
UAT - Unlimited Authentication Trials
Password Set
Two sets of two 24-bit passwords for read and write
operations, defined by the issuer. The Write Password
allows modification of the Read and Write passwords of the
same set. By default, Password 1 is selected for all user
zones.
If enabled (UAT = “0”), the Authentication Attempts Counter
(AAC) is disabled, allowing an unlimited number of
authentication attempts. The Password Attempts Counters
(PAC) are not affected by the UAT bit.
UCR - Unlimited Checksum Reads
If enabled (UCR = “0”), the device will allow an unlimited
number of checksums without requiring a new
Authentication.
Secure Code
24-bit password, defined by Atmel, is different for each card
manufacturer. The Write Password 1 is used as the Secure
Code until the personalization is over (PER = 0).
SME - Supervisor Mode Enable
If enabled (SME = “0”), verification of the Write 1 Password
will allow the user to write and read the entire Passwords
zone (including the PACs).
Attempts Counters
Four 8-bit attempts counters, one for each password
(PAC), and one other 8-bit Attempts Counter for the
authentication protocol (AAC). The attempts counters limit
the number of consecutive incorrect code presentations
allowed (currently 4).
Checksum Authentication Register
After a valid authentication has been completed, the
internal pseudo-random generator (PRG) will compute a
secure checksum after one write command or several
consecutive write commands. This checksum certifies that
the data sent by the host during the write commands were
received and therefore written in the memory. For every
Write command, the device clocks the data bytes into the
PRG and its output is the Checksum Authentication
Register (CAR), which is a function of Ci, Gc, Q and the
data bytes written.
Device Configuration Register
This 8-bit register allows the issuer to select the following
device configuration options (active-low).
Bit 7
Bit 6
Bit 5
UAT
Bit 4
ETA
Bit 3
CS3
Bit 2
CS2
Bit 1
CS1
Bit 0
CS0
SME UCR
After a valid authentication, any write command will enable
the checksum mode, and cause AAC to become the virtual
location of the eight byte CAR. When all data have been
transmitted, the host may perform a “Read CAR”
command, by sending a Read command with the AAC
address ($20). The first eight bytes transmitted by the
device form the secure checksum.
CS0 - CS3 - Programmable Chip Select
The four most significant bits (b4 - b7) of every command
comprise the Chip Select Address. All AT88SC153 devices
will respond to the default Chip Select Address of $B
(1011). Each device will also respond to a second Chip
Select Address programmed into CS0 - CS3 of the Device
Configuration Register. By programming each device to a
unique Chip Select Address, it is possible to connect up to
15 devices on the same Serial Data bus. Write EEPROM
and Verify Password commands can be used globally to all
devices sharing the bus by using the default Chip Select
Address $B.
The checksum mode allows only a single “Read CAR”
operation for each valid Authentication. The checksum
mode is disabled at the end of the “Read CAR” command,
whatever the number of bytes transmitted, or by a read
command with any other address. The checksum mode
can only be enabled once for a given authentication.
Note: During the “Read CAR” command, the internal address
counter is incremented just as in a normal read command.
Once eight bytes have been transmitted, the checksum
mode is automatically disabled, and if the host continues to
request data, the device responds as to a normal Read
command, from the address $28.
ETA - Eight Trials Allowed
If enabled (ETA = “0”), extends the trials limit to 8 incorrect
presentations allowed (passwords or authentication). If
disabled (ETA = “1”), the Password Attempts Counter
(PAC) and Authentication Attempts Counter (AAC) will
allow only four incorrect attempts.
AT88SC153
6
AT88SC153
AT88SC153 requires that the Verify Password command be
transmitted twice in sequence to successfully verify a Write
or Read password(1). The first Verify Password command
can be considered an initialization command. It will write a
new bit (“0”) in the corresponding password attempts
counter. The data bits in this initialization command are
ignored. The second Verify password command will
compare the 3-byte password data presented with the
corresponding password value stored in memory. If the
comparison is valid, the password attempts counter will be
cleared. A successful password verification will allow
authorized operations to be carried out as long as the chip
is powered. The current password is memorized and active
until power is turned off, a new password is presented or
RST becomes active. Only one password is active at a
time. If a new user zone is selected which points to a
different password set, the new password must be verified
and the old password becomes invalid.
User Zones
Three zones are dedicated to the user data. The access
rights of each zone are programmable separately via the
access registers. If several zones share the same
password set, this set will be entered only once (after the
part is powered up), so several zones might be combined
in one larger zone.
Security Operations
Write Lock
If a user zone is configured in the write lock mode (Access
Register bit 2), the lowest address byte of a page
constitutes a write access byte for the bytes of that page.
$0 - WLB
$1
$2
$3
$4
$5
$6
$7
@
x x
x x
x x
1101100
1
x x
x x
x x
x x
$00
Lock Lock
Lock
Note:
1. This two-pass method of password verification was
implemented in the AT88SC153 to protect the device
from attacks on the password security system.
Example: the write lock byte at $00 controls the bytes
from $00 to $07.
Authentication Protocol
The access to an user zone may be protected by an
authentication protocol in addition to password dependent
rights.
The Write Lock byte (WLB) can also lock itself by writing its
least significant (right most) bit to “0”.The Write Lock byte
can only be programmed, that is, bits written to “0” cannot
return to “1”.
The authentication success is memorized and active, as
long as the chip is powered, unless a new authentication is
initialized or RST becomes active. If the new authentication
request is not validated, the card has lost its previous
authentication and it should be presented again. Only the
last request is memorized.
In the write lock configuration, only one byte of the page
can be written at a time. Even if several bytes are received,
only the first byte will be taken into account by the device.
Password Verification
Compare the operation password presented with the stored
one, and write a new bit in the corresponding attempts
counter for each wrong attempt. A valid attempt erases the
attempts counter, and allows the operation to be carried out
as long as the chip is powered.
The Authentication Verification protocol requires the host to
perform an Initialize authentication command, followed by a
verify authentication command.
Note: The password and authentication may be presented
at any time and in any order. If the trials limit has been
reached, i.e. the 8 bits of the attempts counter have been
written, the password verification or authentication
process will not be taken into account.
The current password is memorized and active until power
is turned off, unless a new password is presented or RST
becomes active. Only one password is active at a time. The
7
AT88SC153 Command Definitions and Protocols
The ISO compliant interface is based on the popular two-wire serial interface. Note that the MOST significant bit is transmit-
ted first.
Command
Chip Select
Instruction
Description
b7
b6
b5
b4
b3
z
b2
b1
0
b0
0
CS3
CS3
CS3
CS3
CS3
CS3
CS3
CS2
CS2
CS2
CS2
CS2
CS2
CS2
CS1
CS1
CS1
CS1
CS1
CS1
CS1
CS0
CS0
CS0
CS0
CS0
CS0
CS0
z
z
p
0
1
0
1
Write EEPROM
Read EEPROM
Verify Password
Initialize Authentication
Verify Authentication
Write fuse
z
0
1
r
1
1
0
0
1
1
1
0
1
0
1
0
1
0
Read fuse
Read EEPROM
Note:
*don’t care bit
zz: Zone number
r : Read/Write password
p : Password set
The data byte address is internally incremented following
the transmission of each data byte. During a read operation
the address “roll over” is from the last byte of the current
zone, to the first byte of the same zone. If the host is not
allowed to read at the specified address, the device will
transmit the corresponding data byte with all bits equal to
“0”.
AT88SC153
8
AT88SC153
Write EEPROM
Note:
*don’t care bit
zz: Zone number
The data byte address lower three bits are internally
incremented following the receipt of each data byte. The
higher data byte address bits are not incremented,
retaining the 8-byte write page address. Each data byte
within a page must only be loaded once. Once a stop
condition is issued to indicate the end of the host’s write
operation, the device initiates the internal nonvolatile write
cycle. An ACK polling sequence can be initiated
immediately. After a write command, if the host is not
allowed to write at some address locations, a nonvolatile
write cycle will still be initiated, but the device will only
modify data at the allowed addresses. When Write Lock
Mode is enabled (WLM = “0”), the write cycle is initiated
automatically after the first data byte has been transmitted.
Read Fuses
0
Note:
Fx = 1 : fuse is not blown
Fx = 0 : fuse is blown
The read fuses operation is always allowed. The
AT88SC153 will continuously transmit the fuse byte if the
host continues to transmit an ACK. The command is
terminated when the host transmits a NACK and STOP bit.
9
Write Fuses
S
T
A
R
T
S
T
O
P
Note:
nnn = 001 : Blow FAB
nnn = 010 : Blow CMA
nnn = 100 : Blow PER
The write fuses operation is only allowed under secure
code control, no data byte is transmitted by the host. The
fuses are blown sequentially: CMA is blown if FAB is equal
to “0”, and PER is blown if CMA is equal to “0”. If the fuses
are all 0’s, the operation is canceled and the device waits
for a new command.
Once a stop condition is issued to indicate the end of the
host’s write operation, the device initiates the internal
nonvolatile write cycle. An ACK polling sequence can be
initiated immediately.
AT88SC153
10
AT88SC153
Answer-to-Reset
If RST is high during SCL clock pulse, the reset operation
occurs according to the ISO 7816-3 synchronous Answer-
to-Reset. The 4 bytes of the Answer-to-Reset register are
transmitted LEAST significant bit first, on the 32 clock
pulses provided on SCL.
The values programmed by Atmel are:
$AA
$2C
$A1
$55
Verify Password
Notes: 1. Pw: Password, 3 bytes.
2. The two bits “rp” indicate the password to compare:
r = 0: Write password,
r = 1: Read password,
p: Password set number.
rp = 01 for the secure code.
This command must be transmitted twice in sequence to
successfully verify a Write or Read password. The first
Verify Password command can be considered an
initialization command. It will write a new bit (“0”) in the
password attempts counter corresponding to the “r” and “p”
bits. The data bits in this initialization command are
ignored. The second Verify password command will
compare the 3-byte password data presented with the
corresponding password value stored in memory. If the
comparison is valid, the password attempts counter will be
cleared. For both commands, once the command
sequence is completed and a stop condition is issued, a
nonvolatile write cycle is initiated to update the associated
attempts counter. After the stop condition is issued, an
ACK polling sequence with the specific command byte of
$BD will indicate the end of the write cycle, and will read
the attempts counter in the configuration zone. The
initialization command will result in a “0” bit in the PAC. The
second Verify Password command will read $FF in the
PAC if the verification was successful.
11
Initialize Authentication
Note: Q: Host random number, 8 bytes.
The initialize authentication command sets up the random
generator with the cryptogram (Ci), the secret seed (Gc)
and the host random number (Q). Once the sequence is
completed and a stop condition is issued, there is a
nonvolatile write cycle to clear a new bit of the
authentication attempts counter. In order to complete the
authentication protocol, the device requires the host to
perform an ACK polling sequence with the specific
command byte of $B6, corresponding to the verify
authentication command.
Verify Authentication
Ch(0)
Ch(1)
Ch(7)
1
Note: Ch: Host challenge, 8 bytes.
If Ch is equal to Ci+1, then the device writes Ci+2 in
memory in place of Ci; this must be preceded by the
initialize authentication command. Once the sequence is
completed and a stop condition is issued, there is a
nonvolatile write cycle to update the associated attempts
counter. In order to know whether or not the authentication
was correct, the device requires the host to perform an
ACK polling sequence with the specific command byte of
$BD, to read the corresponding attempts counter in the
configuration zone.
AT88SC153
12
AT88SC153
Pin Description
Name
VCC
GND
SCL
Description
ISO Module Contact
Standard Package Pin
Supply Voltage
Ground
C1
C5
C3
C7
C2
8
1
6
3
7
Serial Clock Input
Serial Data Input/Output
Reset Input
SDA
RST
Card Module Contact
8-pin SOIC, PDIP, EIAJ or LAP
GND
NC
1
2
3
4
8
7
6
5
VCC
RST
SCL
NC
VCC
SDA
NC
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is
normally pulled high with an external device. Data on the
SDA pin may change only during SCL low time periods
(refer to Data Validity timing diagram). Data changes during
SCL high periods will indicate a start or stop condition as
defined below.
transmitted to and from the device in 8 bit words. The device
sends a zero to acknowledge that it has received each byte.
This happens during the ninth clock cycle.
STANDBY MODE: The AT88SC153 features a low power
standby mode which is enabled: (a) upon power-up and (b)
after the receipt of the STOP bit and the completion of any
internal operations.
ACKNOWLEDGE POLLING: Once the internally-timed
write cycle has started and the device inputs are disabled,
acknowledge polling can be initiated. This involves sending
a start condition followed by the command byte
representative of the operation desired. Only if the internal
write cycle has completed will the device respond with a
zero, allowing the sequence to continue.
START CONDITION: A high-to-low transition of SDA with
SCL high is a start condition which must precede any other
command (refer to Start and Stop Definition timing
diagram).
STOP CONDITION: A low-to-high transition of SDA with
SCL high is a stop condition. After a read sequence, the
stop command will place the device in a standby power
mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data are serially
13
Start and Stop Definition
Note: The SCL input should be LOW when the device is idle. Therefore, SCL is LOW before a start condition and after a stop condition.
Data Validity
SDA
SCL
DATA STABLE
DATA STABLE
DATA
CHANGE
Output Acknowledge
1
8
9
SCL
DATA IN
DATA OUT
START
ACKNOWLEDGE
Note:
To transmit a NACK (no acknowledge), hold data (SDA) high during the entire 9th clock cycle.
AT88SC153
14
AT88SC153
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Operating Temperature ........................-55°C to +125°C
Storage Temperature............................-65°C to +150°C
Voltage on Any Pin
with Respect to Ground................... -0.7V to VCC + 0.7V
Maximum Operating Voltage .................................6.25V
DC Output Current ............................................. 5.0 mA
DC Characteristics
Applicable over recommended operating range from: VCC = +2.7V to 5.5V, TAC = 0°C to +70°C (unless otherwise noted).
Symbol
Parameter
Test Condition
Min
Typ
Max
5.5
Units
V
(1)
VCC
Supply Voltage
2.7
ICC
ICC
Supply Current (VCC = 5.0V)
Supply Current (VCC = 5.0V)
Standby Current (VCC = 2.7V)
Standby Current (VCC = 5.0V)
Input Leakage Current
Output Leakage Current
Input Low Level (3)
READ at 1 MHz(2)
WRITE at 1 MHz
VIN = VCC or GND
VIN = VCC or GND
VIN = VCC or GND
VOUT = VCC or GND
5.0
mA
mA
µA
µA
µA
µA
V
5.0
(1)
ISB1
1.0
ISB2
ILI
5.0
1.0
ILO
1.0
VIL
-0.3
VCC x 0.3
VCC + 0.5
0.4
VIH
VOL2
Input High Level (3)
VCC x 0.7
V
Output Low Level (VCC = 2.7V)
IOL = 2.1 mA
V
Notes: 1. This parameter is preliminary and Atmel may change the specifications upon further characterization.
2. Output not loaded.
3. VIL min and VIH max are reference only and are not tested.
15
AC Characteristics
Applicable over recommended operating range from TA = 0°C to +70°C, VCC = +2.7V to +5.5V, CL = 1 TTL Gate and 100
pF (unless otherwise noted).
5.0 Volt
Parameter
Symbol
fSCL
Min
Max
Units
MHz
ns
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Clock Low to Data Out Valid
Start Hold Time
1.0
tLOW
400
400
tHIGH
tAA
ns
550
ns
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
200
200
0
ns
Start Set-up Time
ns
Data In Hold Time
Data In Set-up Time
Inputs Rise Time (1,2)
Inputs Fall Time (1,2)
Stop Set-up Time
ns
100
ns
300
100
ns
tF
ns
tSU.STO
tDH
200
0
ns
Data Out Hold Time
Write Cycle Time
ns
tWR
10
ms
ns
tRST
Reset Width High
600
50
tSU.RST
tHD.RST
Reset Set-up Time
Reset Hold Time
ns
50
ns
Period of time the bus must be free before a new
command can start (1)
tBUF
500
ns
Notes: 1. This parameter is characterized and is not 100% tested.
2. Input rise and fall transitions must be monotonic.
Pin Capacitance
Applicable at recommended operating condition TA = 25°C, f = 1.0 MHz, VCC = +2.7V.
Symbol
CI/O
Test Condition
Max
8
Units
Conditions
VI/O = 0V
VIN = 0V
Input/Output Capacitance (SDA)(1)
Input Capacitance (RST, SCL)(1)
pF
pF
CIN
6
Note:
1. This parameter is characterized and is not 100% tested.
AT88SC153
16
AT88SC153
Bus Timing SCL: Serial Clock SDA: Serial Data I/O
Synchronous Answer-to-Reset Timing
Write Cycle Timing SCL: Serial Clock SDA: Serial Data I/O
SCL
SDA
ACK
8th BIT
WORD n
tWR
STOP
CONDITION
START
CONDITION
Note:
Note: The write cycle Time tWR is the time from valid stop condition of a write sequence to the end of the internal clear/write
cycle.
17
Ordering Information
Ordering Code(1)
Package(2)
Voltage Range
Temperature Range
AT88SC153 - 09AT - xx - 2.7
AT88SC153 - 09BT - xx - 2.7
AT88SC153 - 09CT - xx - 2.7
AT88SC153 - 09DT - xx - 2.7
AT88SC153 - 09ET - xx - 2.7
AT88SC153 - 09GT - xx - 2.7
AT88SC153 - 09HT - xx - 2.7
AT88SC153 - 10SC - xx - 2.7
AT88SC153 - 10WC - xx - 2.7
AT88SC153 - 10PC - xx - 2.7
AT88SC153 - 10CC - xx - 2.7
M2 - A Module
M2 - B Module
M4 - C Module
M4 - D Module
M2 - E Module
M3 - G Module
M3 - H Module
8S1
Commercial
2.7V to 3.3V
0°C to 70°C
8S2
8P3
8C
AT88SC153 - 09AT - xx
AT88SC153 - 09BT - xx
AT88SC153 - 09CT - xx
AT88SC153 - 09DT - xx
AT88SC153 - 09ET - xx
AT88SC153 - 09GT - xx
AT88SC153 - 09HT - xx
AT88SC153 -10SC - xx
AT88SC153 - 10WC - xx
AT88SC153 -10PC - xx
AT88SC153 - 10CC - xx
M2 - A Module
M2 - B Module
M4 - C Module
M4 - D Module
M2 - E Module
M3 - G Module
M3 - H Module
8S1
Commercial
4.5V to 5.5V
0°C to 70°C
8S2
8P3
8C
Package Type(2)
M2 ISO 7816 Smart Card Module
M2 - A Module
M2 - B Module
M4 - C Module
M4 - D Module
M2 - E Module
M3 - G Module
M3 - H Module
8S1
M2 ISO 7816 Smart Card Module with Atmel Logo
M4 ISO 7816 Smart Card Module
M4 ISO 7816 Smart Card Module with Atmel Logo
M2 ISO 7816 Smart Card Module
M3 ISO 7816 Smart Card Module
M3 ISO 7816 Smart Card Module with Atmel Logo
8-Lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8-Lead, 0.200” Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
8-Lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)
8S2
8P3
8C
8-Lead, 0.230” Wide, Leadless Array Package (LAP)
Notes: 1. “xx” must be replaced by a security code. Contact an Atmel Sales Office for the security code.
2. Formal drawings may be obtained from an Atmel Sales Office.
AT88SC153
18
AT88SC153
Smart Card Modules
M2 - A Module - Ordering Code: 09AT
M2 - E Module - Ordering Code: 09ET
Module Size: M2
Module Size: M2
Dimension(1): 12.6 x 11.4 mm
Glob Top: Black, Square: 8.6 x 8.6 mm
Thickness: 0.58 mm max.
Pitch: 14.25 mm
Dimension(1): 12.6 x 11.4 mm
Glob Top: Clear, Round: Ø 7.5 mm max.
Thickness: 0.58 mm max.
Pitch: 14.25 mm
M2 - B Module - Ordering Code: 09BT
M3 - G Module - Ordering Code: 09GT
Module Size: M3
Module Size: M2
Dimension(1): 10.6 x 8.0 mm
Glob Top: Clear, Round: Ø 6.5 mm max.
Thickness: 0.58 mm max.
Pitch: 9.5 mm
Dimension(1): 12.6 x 11.4 mm
Glob Top: Black, Square: 8.6 x 8.6 mm
Thickness: 0.58 mm max.
Pitch: 14.25 mm
M3 - H Module - Ordering Code: 09HT
M4 - C Module - Ordering Code: 09CT
Module Size: M3
Dimension(1): 10.6 x 8.0 mm
Glob Top: Clear, Round: Ø 6.5 mm max.
Thickness: 0.58 mm max.
Pitch: 9.5 mm
Module Size: M4
Dimension(1): 12.6 x 12.6 mm
Glob Top: Black, Square: 8.6 x 8.6 mm
Thickness: 0.58 mm
Pitch: 14.25 mm
Note:
1. The module dimensions listed refer to the
dimensions of the exposed metal contact area.
The actual dimensions of the module after excise or
punching from the carrier tape are generally 0.4 mm
greater in both directions (i.e. a punched M2 module
will yield 13.0 x 11.8 mm).
M4 - D Module - Ordering Code: 09DT
Module Size: M4
Dimension(1): 12.6 x 12.6 mm
Glob Top: Black, Square: 8.6 x 8.6 mm
Thickness: 0.58 mm max.
Pitch: 14.25 mm
19
Packaging Information
8S1, 8-lead, 0.150” Wide, Plastic Gull Wing Small
Outline (JEDEC SOIC)
8S2, 8-lead, 0.210” Wide, Plastic Gull Wing Small
Outline (EIAJ SOIC)
Dimensions in Inches and (Millimeters)
Dimensions in Inches and (Millimeters)
.020 (.508)
.012 (.305)
.020 (.508)
.013 (.330)
.213 (5.41) .330 (8.38)
.205 (5.21) .300 (7.62)
.244 (6.20)
.228 (5.79)
.157 (3.99)
.150 (3.81)
PIN 1
PIN 1
.050 (1.27) BSC
.050 (1.27) BSC
.212 (5.38)
.203 (5.16)
.080 (2.03)
.070 (1.78)
.196 (4.98)
.189 (4.80)
.068 (1.73)
.053 (1.35)
.013 (.330)
.004 (.102)
.010 (.254)
.004 (.102)
0
8
0
8
REF
.010 (.254)
.007 (.178)
REF
.010 (.254)
.007 (.203)
.035 (.889)
.020 (.508)
.050 (1.27)
.016 (.406)
8P3, 8-lead, 0.300” Wide, Plastic Dual Inline
Package (PDIP)
8C, 8-lead, 0.300” Wide, Leadless Array Package
(LAP)
Dimensions in Inches and (Millimeters)
Dimensions in Inches and (Millimeters)
.400 (10.16)
.355 (9.02)
SIDE
TOP VIEW
VIEW
PIN
1
.280 (7.11)
.240 (6.10)
5.03 (0.198)
4.83 (0.190)
.037 (.940)
.027 (.690)
.300 (7.62) REF
.210 (5.33) MAX
1.14 (0.045)
0.94 (0.037)
6.09 (0.240)
5.89 (0.232)
.100 (2.54) BSC
0.38 (0.015)
0.30 (0.012)
SEATING
PLANE
BOTTOM VIEW
1
1.32 (0.052)
1.19 (0.047)
1.09 (0.043)
.015 (.380) MIN
1.22 (0.048)
.150 (3.81)
.115 (2.92)
8
7
6
5
.022 (.559)
.014 (.356)
.070 (1.78)
.045 (1.14)
0.61 (0.024)
2
3
4
3.86 (0.152)
3.76 (0.148)
0.51 (0.020)
.325 (8.26)
.300 (7.62)
0
REF
15
0.89 (0.035)
0.79 (0.031)
.012 (.305)
.008 (.203)
0.60 (0.024)
0.50 (0.020)
.430 (10.9) MAX
AT88SC153
20
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Atmel Operations
Corporate Headquarters
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San Jose, CA 95131
TEL (408) 441-0311
FAX (408) 487-2600
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FAX (81) 3-3523-7581
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International:
1-(408) 441-0732
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
BBS
1-(408) 436-4309
© Atmel Corporation 1999.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-
ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for
any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
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