AT52BR1662T-90CI [ETC]
MIXED MEMORY|SRAM+EEPROM|HYBRID|BGA|66PIN|PLASTIC ; 混合内存| SRAM + EEPROM |混合| BGA | 66PIN |塑料\n
| 型号： | AT52BR1662T-90CI |
| 厂家： | 
ETC |
| 描述： | MIXED MEMORY|SRAM+EEPROM|HYBRID|BGA|66PIN|PLASTIC
|
| 文件： | 总40页 (文件大小：563K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• 16-megabit (x16) Flash and 2-megabit/4-megabit SRAM
• 2.7V to 3.3V Operating Voltage
• Low Operating Power
– 40 mA Operating Current (Maximum)
– 50 µA Standby Current (Maximum)
• Industrial Temperature Range
Flash
• 2.7V to 3.3V Read/Write
16-megabit
Flash +
2-megabit/
4-megabit
SRAM Stack
Memory
• Access Time – 70 ns
• Sector Erase Architecture
– Thirty-one 32K Word (64K Byte) Sectors with Individual Write Lockout
– Eight 4K Word (8K Byte) Sectors with Individual Write Lockout
• Fast Word Program Time – 20 µs
• Fast Sector Erase Time – 300 ms
• Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming from Any Sector by Suspending Erase of a
Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
• Low-power Operation
– 30 mA Active
– 10 µA Standby
• Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
• VPP Pin for Write Protection and Accelerated Program/Erase Operations
• RESET Input for Device Initialization
• Sector Lockdown Support
• Top Boot Block Configuration
• 128-bit Protection Register
AT52BR1662T
AT52BR1664T
SRAM
• 2-megabit (128K x 16)/4-megabit (256K x 16)
• 2.7V to 3.3V VCC Operating Voltage
• 70 ns Access Time
• Fully Static Operation and Tri-state Output
• 1.2V (Min) Data Retention
Flash Boot
Location
Flash Plane
Architecture
SRAM
Configuration
Device Number
AT52BR1662T
AT52BR1664T
16M
16M
Top
Top
128K x 16
256K x 16
Rev. 2212A–11/01
CBGA Top View
1
3
4
5
6
7
8
9
10 11
12
2
A
B
C
D
E
F
NC
NC
NC
NC
NC
A16
WE
A11
A8
A15
A10
A14
A9
A13
A12
SWE
I/O6
GND
I/O14
I/O4
SVcc
I/O2
I/O0
A1
NC
I/O7
I/O5
Vcc
I/O15
I/O13
I/O12
RDY BUSY
RESET
Vpp
SGND
NC
SCS2
I/O10
I/O8
A19
SOE
A7
I/O11
I/O3
I/O1
SCS1
NC
SLB
A18
NC
SUB
I/O9
A3
G
H
A17
A6
A0
A2
NC
NC
NC
NC
A5
A4
CE
GND
OE
Pin
Pin Name
A0 - A15
A0 - A16
A17 - A19
CE
Function
Configurations
Flash/SRAM Common Address Input for 2M SRAM
Flash/SRAM Common Address Input for 4M SRAM
Flash Address Input
Flash Chip Enable
OE/SOE
WE/SWE
VCC
Flash/SRAM, Output Enable
Flash/SRAM, Write Enable
Flash Power Supply
VPP
Optional Flash Power Supply for Faster Program/Erase Operations
Data Inputs/Outputs
I/O0-I/O15
SCS1, SCS2
RDY/BUSY
SVCC
SRAM Chip Select
Flash Ready/Busy Output
SRAM Power Supply
GND/SGND
SUB
Flash/SRAM GND
SRAM Upper Byte
SLB
SRAM Lower Byte
NC
No Connect
RESET
Flash Reset
2
AT52BR1662T/1664T
2212A–11/01
AT52BR1662T/1664T
Description
The AT52BR1662T combines a single plane 16-megabit Flash and a 2-megabit SRAM in a stacked 66-ball CBGA package;
while the AT52BR1664T combines a single plane 16-megabit Flash and a 4-megabit SRAM in a stacked 66-ball CBGA
package. Both devices operate at 2.7V to 3.3 in the industrial temperature range.
Block Diagram
ADDRESS
OE WE
SOE SWE
RESET
CE
FLASH
SRAM
SCS1
RDY/BUSY
DATA
Absolute Maximum Ratings
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature under Bias .................................. -40°C to +85°C
Storage Temperature..................................... -55°C to +150°C
All Input Voltages
except VPP and RESET
(including NC Pins)
with Respect to Ground.....................................-0.2V to +3.3V
Voltage on VPP
with Respect to Ground..................................-0.2V to + 6.25V
Voltage on RESET
with Respect to Ground...................................-0.2V to +13.5V
All Output Voltages
with Respect to Ground.....................................-0.2V to +0.2V
DC and AC Operating Range
AT52BR1662T/1664T-70, -90
-40°C - 85°C
Operating Temperature (Case)
CC Power Supply
Industrial
V
2.7V to 3.3V
3
2212A–11/01
16-megabit Flash Memory Block Diagram
I/O0 - I/O15
OUTPUT
BUFFER
INPUT
BUFFER
IDENTIFIER
REGISTER
INPUT
A0 - A19
BUFFER
STATUS
CE
REGISTER
WE
COMMAND
REGISTER
OE
RESET
BYTE
ADDRESS
LATCH
DATA
RDY/BUSY
VPP
COMPARATOR
WRITE STATE
MACHINE
PROGRAM/ERASE
VOLTAGE SWITCH
Y-DECODER
X-DECODER
Y-GATING
VCC
GND
MAIN
MEMORY
4
AT52BR1662T/1664T
2212A–11/01
AT52BR1662T/1664T
16-megabit
Flash
Description
The 16-megabit Flash memory is organized as 1,048,576 words of 16 bits each. The x16 data
appears on I/O0 - I/O15. The memory is divided into 39 sectors for erase operations. The
device has CE and OE control signals to avoid any bus contention. This device can be read or
reprogrammed using a single 2.7V power supply, making it ideally suited for in-system
programming.
The device powers on in the read mode. Command sequences are used to place the device in
other operation modes such as program and erase. The device has the capability to protect
the data in any sector. (See “Sector Lockdown” section.)
To increase the flexibility of the device, it contains an Erase Suspend and Program Suspend
feature. This feature will put the Erase or Program on hold for any amount of time and let the
user read data from or program data to any of the remaining sectors within the memory. The
end of a program or an erase cycle is detected by the Ready/Busy pin, Data Polling or by the
toggle bit.
The VPP pin provides data protection and faster programming. When the VPP input is below
0.8V, the program and erase functions are inhibited. When VPP is at 1.65V or above, normal
program and erase operations can be performed. With VPP at 5.0V or 12.0V, the program and
erase operations are accelerated.
A six-byte command (Enter Single Pulse Program Mode) sequence to remove the requirement
of entering the three-byte program sequence is offered to further improve programming time.
After entering the six-byte code, only single pulses on the write control lines are required for
writing into the device. This mode (Single Pulse Word Program) is exited by powering down
the device, or by pulsing the RESET pin low for a minimum of 500 ns and then bringing it back
to VCC. Erase, Erase Suspend/Resume, and Program Suspend/Resume commands will not
work while in this mode; if entered, they will result in data being programmed into the device. It
is not recommended that the six-byte code reside in the software of the final product but only
exist in external programming code.
Device
Operation
READ: The 16-megabit Flash is accessed like an EPROM. When CE and OE are low and WE
is high, the data stored at the memory location determined by the address pins are asserted
on the outputs. The outputs are put in the high-impedance state whenever CE or OE is high.
This dual-line control gives designers flexibility in preventing bus contention.
COMMAND SEQUENCES: When the device is first powered on, it will be reset to the read or
standby mode, depending upon the state of the control line inputs. In order to perform other
device functions, a series of command sequences are entered into the device. The command
sequences are shown in the “Command Definition in Hex” table on page 13 (I/O8 - I/O15 are
don’t care inputs for the command codes). The command sequences are written by applying a
low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address
is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the
first rising edge of CE or WE. Standard microprocessor write timings are used. The address
locations used in the command sequences are not affected by entering the command
sequences.
RESET: A RESET input pin is provided to ease some system applications. When RESET is at
a logic high level, the device is in its standard operating mode. A low level on the RESET input
halts the present device operation and puts the outputs of the device in a high-impedance
state. When a high level is reasserted on the RESET pin, the device returns to the read or
standby mode, depending upon the state of the control inputs.
ERASURE: Before a word can be reprogrammed, it must be erased. The erased state of
memory bits is a logical “1”. The entire device can be erased by using the Chip Erase com-
mand or individual sectors can be erased by using the Sector Erase command.
5
2212A–11/01
CHIP ERASE: The entire device can be erased at one time by using the six-byte chip erase
software code. After the chip erase has been initiated, the device will internally time the erase
operation so that no external clocks are required. The maximum time to erase the chip is tEC
.
If the sector lockdown has been enabled, the chip erase will not erase the data in the sector
that has been locked out; it will erase only the unprotected sectors. After the chip erase, the
device will return to the read or standby mode.
SECTOR ERASE: As an alternative to a full chip erase, the device is organized into 39 sec-
tors (SA0 - SA38) that can be individually erased. The Sector Erase command is a six-bus
cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while
the 30H data input command is latched on the rising edge of WE. The sector erase starts after
the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will
automatically time to completion. The maximum time to erase a sector is tSEC. When the sec-
tor programming lockdown feature is not enabled, the sector will erase (from the same Sector
Erase command). An attempt to erase a sector that has been protected will result in the oper-
ation terminating in 2 µs.
WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logical “0”)
on a word-by-word basis. Programming is accomplished via the internal device command reg-
ister and is a four-bus cycle operation. The device will automatically generate the required
internal program pulses.
Any commands written to the chip during the embedded programming cycle will be ignored. If
a hardware reset happens during programming, the data at the location being programmed
will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase
operations can convert “0”s to “1”s. Programming is completed after the specified tBP cycle
time. The Data Polling feature or the Toggle Bit feature may be used to indicate the end of a
program cycle. If the erase/program status bit is a “1”, the device was not able to verify that the
erase or program operation was performed successfully.
VPP PIN: The circuitry of the 16-megabit Flash is designed so that the device can be pro-
grammed or erased from the VCC power supply or from the VPP input pin. When VPP is greater
than 1.65V and less than or equal to the VCC pin, the device selects the VCC supply for pro-
gramming and erase operations. When the VPP pin is greater than the VCC supply, the device
will select the VPP input as the power supply for programming and erase operations. The
device will allow for some variations between the VPP input and the VCC power supply in its
selection of VCC or VPP for program or erase operations. If the VPP pin is within 0.3V of VCC for
2.7V < VCC < 3.6V, then the program or erase operations will use VCC and disregard the VPP
input signal. When the VPP signal is used for program and erase operations, the VPP must be
in the 5V 0.5V or 12V 0.5V range to ensure proper operation. The Vpp pin cannot be left
floating.
PROGRAM/ERASE STATUS: The device provides several bits to determine the status of a
program or erase operation: I/O2, I/O3, I/O5, I/O6 and I/O7. The “Status Bit Table” on page 12
and the following four sections describe the function of these bits. To provide greater flexibility
for system designers, the 16-megabit Flash contains a programmable configuration register.
The configuration register allows the user to specify the status bit operation. The configuration
register can be set to one of two different values, “00” or “01”. If the configuration register is set
to “00”, the part will automatically return to the read mode after a successful program or erase
operation. If the configuration register is set to a “01”, a Product ID Exit command must be
given after a successful program or erase operation before the part will return to the read
mode. It is important to note that whether the configuration register is set to a “00” or to a “01”,
any unsuccessful program or erase operation requires using the Product ID Exit command to
return the device to read mode. The default value (after power-up) for the configuration regis-
ter is “00”. Using the four-bus cycle Set Configuration Register command as shown in the
“Command Definition in Hex” table on page 13, the value of the configuration register can be
6
AT52BR1662T/1664T
2212A–11/01
AT52BR1662T/1664T
changed. Voltages applied to the RESET pin will not alter the value of the configuration regis-
ter. The value of the configuration register will affect the operation of the I/O7 status bit as
described below.
DATA POLLING: The 16-megabit features Data Polling to indicate the end of a program cycle.
If the status configuration register is set to a “00”, during a program cycle an attempted read of
the last word loaded will result in the complement of the loaded data on I/O7. Once the pro-
gram cycle has been completed, true data is valid on all outputs and the next cycle may begin.
During a chip or sector erase operation, an attempt to read the device will give a “0” on I/O7.
Once the program or erase cycle has completed, true data will be read from the device. Data
Polling may begin at any time during the program cycle. Please see “Status Bit Table” on page
12 for more details.
If the status bit configuration register is set to a “01”, the I/O7 status bit will be low while the
device is actively programming or erasing data. I/O7 will go high when the device has com-
pleted a program or erase operation. Once I/O7 has gone high, status information on the other
pins can be checked.
The Data Polling status bit must be used in conjunction with the erase/program and VPP status
bit as shown in the algorithm in Figures 1 and 2 on page 10.
TOGGLE BIT: In addition to Data Polling, the 16-megabit Flash provides another method for
determining the end of a program or erase cycle. During a program or erase operation, suc-
cessive attempts to read data from the memory will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be
read. Examining the toggle bit may begin at any time during a program cycle. Please see “Sta-
tus Bit Table” on page 12 for more details.
The toggle bit status bit should be used in conjunction with the erase/program and VPP status
bit as shown in the algorithm in Figures 3 and 4 on page 11.
ERASE/PROGRAM STATUS BIT: The device offers a status bit on I/O5, which indicates
whether the program or erase operation has exceeded a specified internal pulse count limit. If
the status bit is a “1”, the device is unable to verify that an erase or a word program operation
has been successfully performed. The device may also output a “1” on I/O5 if the system tries
to program a “1” to a location that was previously programmed to a “0”. Only an erase opera-
tion can change a “0” back to a “1”. If a program (Sector Erase) command is issued to a
protected sector, the protected sector will not be programmed (erased). The device will go to a
status read mode and the I/O5 status bit will be set high, indicating the program (erase) opera-
tion did not complete as requested. Once the erase/program status bit has been set to a “1”,
the system must write the Product ID Exit command to return to the read mode. The
erase/program status bit is a “0” while the erase or program operation is still in progress.
Please see “Status Bit Table” on page 12 for more details.
VPP STATUS BIT: The 16-megabit Flash provides a status bit on I/O3, which provides infor-
mation regarding the voltage level of the VPP pin. During a program or erase operation, if the
voltage on the VPP pin is not high enough to perform the desired operation successfully, the
I/O3 status bit will be a “1”. Once the VPP status bit has been set to a “1”, the system must
write the Product ID Exit command to return to the read mode. On the other hand, if the volt-
age level is high enough to perform a program or erase operation successfully, the VPP status
bit will output a “0”. Please see “Status Bit Table” on page 12 for more details.
SECTOR LOCKDOWN: Each sector has a programming lockdown feature. This feature pre-
vents programming of data in the designated sectors once the feature has been enabled.
These sectors can contain secure code that is used to bring up the system. Enabling the lock-
down feature will allow the boot code to stay in the device while data in the rest of the device is
updated. This feature does not have to be activated; any sector’s usage as a write-protected
region is optional to the user.
7
2212A–11/01
At power-up or reset, all sectors are unlocked. To activate the lockdown for a specific sector,
the six-bus cycle Sector Lockdown command must be issued. Once a sector has been locked
down, the contents of the sector is read-only and cannot be erased or programmed.
SECTOR LOCKDOWN DETECTION: A software method is available to determine if program-
ming of a sector is locked down. When the device is in the software product identification
mode (see “Software Product Identification Entry/Exit” sections on page 23), a read from
address location 00002H within a sector will show if programming the sector is locked down. If
the data on I/O0 is low, the sector can be programmed; if the data on I/O0 is high, the program
lockdown feature has been enabled and the sector cannot be programmed. The software
product identification exit code should be used to return to standard operation.
SECTOR LOCKDOWN OVERRIDE: The only way to unlock a sector that is locked down is
through reset or power-up cycles. After power-up or reset, the content of a sector that is
locked down can be erased and reprogrammed.
ERASE SUSPEND/ERASE RESUME: The Erase Suspend command allows the system to
interrupt a sector erase or chip erase operation and then program or read data from a different
sector within the memory. After the Erase Suspend command is given, the device requires a
maximum time of 15 µs to suspend the erase operation. After the erase operation has been
suspended, the system can then read data or program data to any other sector within the
device. An address is not required during the Erase Suspend command. During a sector erase
suspend, another sector cannot be erased. To resume the sector erase operation, the system
must write the Erase Resume command. The Erase Resume command is a one-bus cycle
command. The device also supports an erase suspend during a complete chip erase. While
the chip erase is suspended, the user can read from any sector within the memory that is pro-
tected. The command sequence for a chip erase suspend and a sector erase suspend are the
same.
PROGRAM SUSPEND/PROGRAM RESUME: The Program Suspend command allows the
system to interrupt a programming operation and then read data from a different word within
the memory. After the Program Suspend command is given, the device requires a maximum
of 15 µs to suspend the programming operation. After the programming operation has been
suspended, the system can then read data from any other word within the device. An address
is not required during the program suspend operation. To resume the programming operation,
the system must write the Program Resume command. The program suspend and resume are
one-bus cycle commands. The command sequence for the erase suspend and program sus-
pend are the same, and the command sequence for the erase resume and program resume
are the same.
PRODUCT IDENTIFICATION: The product identification mode identifies the device and man-
ufacturer as Atmel. It may be accessed by hardware or software operation. The hardware
operation mode can be used by an external programmer to identify the correct programming
algorithm for the Atmel product.
For details, see “Operating Modes” on page 16 (for hardware operation) or “Software Product
Identification Entry/Exit” on page 23. The manufacturer and device codes are the same for
both modes.
128-BIT PROTECTION REGISTER: The 16-megabit Flash contains a 128-bit register that
can be used for security purposes in system design. The protection register is divided into two
64-bit blocks. The two blocks are designated as block A and block B. The data in block A is
non-changeable and is programmed at the factory with a unique number. The data in block B
is programmed by the user and can be locked out such that data in the block cannot be repro-
grammed. To program block B in the protection register, the four-bus cycle Program
Protection Register command must be used as shown in the “Command Definition in Hex”
table on page 13. To lock out block B, the four-bus cycle Lock Protection Register command
8
AT52BR1662T/1664T
2212A–11/01
AT52BR1662T/1664T
must be used as shown in the “Command Definition in Hex” table on page 13. Data bit D1
must be zero during the fourth bus cycle. All other data bits during the fourth bus cycle are
don’t cares. To determine whether block B is locked out, the Product ID Entry command is
given followed by a read operation from address 80H. If data bit D1 is zero, block B is locked.
If data bit D1 is one, block B can be reprogrammed. Please see the “Protection Register
Addressing Table” on page 14 for the address locations in the protection register. To read the
protection register, the Product ID Entry command is given followed by a normal read opera-
tion from an address within the protection register. After determining whether block B is
protected or not, or reading the protection register, the Product ID Exit command must be
given prior to performing any other operation.
RDY/BUSY: An open-drain READY/BUSY output pin provides another method of detecting
the end of a program or erase operation. RDY/BUSY is actively pulled low during the internal
program and erase cycles and is released at the completion of the cycle. The open-drain con-
nection allows for OR-tying of several devices to the same RDY/BUSY line. Please see
“Status Bit Table” on page 12 for more details.
HARDWARE DATA PROTECTION: The Hardware Data Protection feature protects against
inadvertent programs to the 16-megabit Flash in the following ways: (a) VCC sense: if VCC is
below 1.8V (typical), the program function is inhibited. (b) VCC power-on delay: once VCC has
reached the VCC sense level, the device will automatically time out 10 ms (typical) before pro-
gramming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits
program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will
not initiate a program cycle. (e) Program inhibit: VPP is less than VILPP. (f) VPP power-on delay:
once VPP has reached 1.65V, program and erase operations can occur after 100 ns.
INPUT LEVELS: While operating with a 2.7V to 3.6V power supply, the address inputs and
control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the
operation of the device. The I/O lines can only be driven from 0 to VCC + 0.6V.
OUTPUT LEVELS: For the Flash, output high levels (VOH) are equal to VCCQ - 0.2V (not VCC).
For 2.7V - 3.6V output levels, VCCQ must be tied to VCC. For 1.8V - 2.2V output levels, VCCQ
must be regulated to 2.0V 10%, while VCC must be regulated to 2.7V - 3.0V (for minimum
power).
9
2212A–11/01
Figure 1. Data Polling Algorithm
Figure 2. Data Polling Algorithm
(Configuration Register = 00)
(Configuration Register = 01)
START
START
Read I/O7 - I/O0
Addr = VA
Read I/O7 - I/O0
Addr = VA
NO
I/O7 = 1?
YES
I/O7 = Data?
NO
YES
NO
I/O3, I/O5 = 1?
NO
I/O3, I/O5 = 1?
YES
YES
Program/Erase
Operation
Successful,
Write Product ID
Exit Command
Program/Erase
Operation Not
Successful, Write
Product ID
Read I/O7 - I/O0
Addr = VA
Exit Command
Note:
1. VA = Valid address for programming. During a sec-
YES
I/O7 = Data?
NO
tor erase operation, a valid address is any sector
address within the sector being erased. During
chip erase, a valid address is any non-protected
sector address.
Program/Erase
Operation Not
Successful, Write
Product ID
Program/Erase
Operation
Successful,
Device in
Exit Command
Read Mode
Notes: 1. VA = Valid address for programming. During a sec-
tor erase operation, a valid address is any sector
address within the sector being erased. During
chip erase, a valid address is any non-protected
sector address.
2. I/O7 should be rechecked even if I/O5 = “1”
because I/O7 may change simultaneously with
I/O5.
10
AT52BR1662T/1664T
2212A–11/01
AT52BR1662T/1664T
Figure 3. Toggle Bit Algorithm
Figure 4. Toggle Bit Algorithm
(Configuration Register = 00)
(Configuration Register = 01)
START
START
Read I/O7 - I/O0
Read I/O7 - I/O0
Read I/O7 - I/O0
Read I/O7 - I/O0
NO
NO
Toggle Bit =
Toggle?
Toggle Bit =
Toggle?
YES
YES
NO
NO
I/O3, I/O5 = 1?
I/O3, I/O5 = 1?
YES
YES
Read I/O7 - I/O0
Twice
Read I/O7 - I/O0
Twice
Toggle Bit =
Toggle?
Toggle Bit =
Toggle?
NO
NO
YES
YES
Program/Erase
Operation Not
Successful, Write
Product ID
Program/Erase
Operation
Successful,
Write Product ID
Exit Command
Program/Erase
Operation Not
Successful, Write
Product ID
Program/Erase
Operation
Successful
Exit Command
Exit Command
Note:
1. The system should recheck the toggle bit even if
I/O5 = “1” because the toggle bit may stop toggling
as I/O5 changes to “1”.
Note:
1. The system should recheck the toggle bit even if
I/O5 = “1” because the toggle bit may stop toggling
as I/O5 changes to “1”.
11
2212A–11/01
Status Bit Table
Status Bit
I/O7
00
I/O7
0
I/O7
01
0
I/O6
00/01
I/O5(1)
I/O3(2)
I/O2
00/01
RDY/BUSY
Configuration Register:
Programming
00/01
00/01
00/01
TOGGLE
TOGGLE
1
0
0
0
0
0
0
1
0
0
1
Erasing
0
TOGGLE
TOGGLE
Erase Suspended & Read
Erasing Sector
1
1
Erase Suspended & Read
Non-erasing Sector
DATA
I/O7
DATA
0
DATA
DATA
0
DATA
0
DATA
1
0
Erase Suspended &
TOGGLE
TOGGLE
Program Non-erasing Sector
Notes: 1. I/O5 switches to a “1” when a program or an erase operation has exceeded the maximum time limits or when a program or
sector erase operation is performed on a protected sector.
2. I/O3 switches to a “1” when the VPP level is not high enough to successfully perform program and erase operations.
12
AT52BR1662T/1664T
2212A–11/01
AT52BR1662T/1664T
Command Definition in Hex(1)
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Command
Sequence
Bus
Cycles
Addr
Addr
555
Data
DOUT
AA
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Read
1
6
6
4
Chip Erase
Sector Erase
Word Program
AAA(2)
AAA
55
55
55
555
555
555
80
80
A0
555
555
AA
AA
DIN
AAA
AAA
55
55
555
SA(3)(4)
10
30
555
AA
555
AA
AAA
Addr
Enter Single Pulse
Program Mode
6
555
AA
AAA
55
555
80
555
AA
AAA
AAA
55
55
555
A0
60
Single Pulse Word
Program
1
6
1
Addr
555
DIN
AA
B0
Sector Lockdown
AAA
55
555
80
555
AA
SA(3)(4)
Erase/Program
Suspend
XXX
Erase/Program
Resume
1
XXX
30
Product ID Entry
Product ID Exit(5)
Product ID Exit(5)
3
3
1
555
555
AA
AA
F0
AAA
AAA
55
55
555
555
90
F0
XXX
Program Protection
Register
4
4
4
4
555
555
555
555
AA
AA
AA
AA
AAA
AAA
AAA
AAA
55
55
55
55
555
555
555
555
C0
C0
90
Addr
080
80
DIN
X0
Lock Protection
Register - Block B
Status of Block B
Protection
(6)
DOUT
Set Configuration
Register
D0
XXX
00/01(7)
Notes: 1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). In word operation I/O15 - I/O8 are Don’t Care.
The ADDRESS FORMAT shown for each bus cycle is as follows: A11 - A0 (Hex). Address A19 through A11 are Don’t Care.
2. Since A11 is a Don’t Care, AAA can be replaced with 2AA.
3. SA = sector address. Any word address within a sector can be used to designate the sector address (see page 15 for
details).
4. Once a sector is in the lockdown mode, data in the protected sector cannot be changed unless the chip is reset or power
cycled.
5. Either one of the Product ID Exit commands can be used.
6. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed.
7. The default state (after power-up) of the configuration register is “00”.
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature under Bias ................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on OE and VPP
with Respect to Ground...................................-0.6V to +13.0V
13
2212A–11/01
Protection Register Addressing Table
Word
Use
Factory
Factory
Factory
Factory
User
Block
A7
A6
0
A5
0
A4
0
A3
0
A2
0
A1
0
A0
1
0
1
2
3
4
5
6
7
A
A
A
A
B
B
B
B
1
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
1
0
0
0
0
1
0
1
User
1
0
0
0
0
1
1
0
User
1
0
0
0
0
1
1
1
User
1
0
0
0
1
0
0
0
Note:
1. All address lines not specified in the above table must be “0” when accessing the protection register, i.e., A19 - A8 = 0.
14
AT52BR1662T/1664T
2212A–11/01
AT52BR1662T/1664T
Top Boot 16-megabit Flash – Sector Address Table
x16
Sector
SA0
Size (Words)
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
4K
Address Range (A19 - A0)
00000 - 07FFF
08000 - 0FFFF
10000 - 17FFF
18000 - 1FFFF
20000 - 27FFF
28000 - 2FFFF
30000 - 37FFF
38000 - 3FFFF
40000 - 47FFF
48000 - 4FFFF
50000 - 57FFF
58000 - 5FFFF
60000 - 67FFF
68000 - 6FFFF
70000 - 77FFF
78000 - 7FFFF
80000 - 87FFF
88000 - 8FFFF
90000 - 97FFF
98000 - 9FFFF
A0000 - A7FFF
A8000 - AFFFF
B0000 - B7FFF
B8000 - BFFFF
C0000 - C7FFF
C8000 - CFFFF
D0000 - D7FFF
D8000 - DFFFF
E0000 - E7FFF
E8000 - EFFFF
F0000 - F7FFF
F8000 - F8FFF
F9000 - F9FFF
FA000 - FAFFF
FB000 - FBFFF
FC000 - FCFFF
FD000 - FDFFF
FE000 - FEFFF
FF000 - FFFFF
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
4K
4K
4K
4K
4K
4K
4K
15
2212A–11/01
DC and AC Operating Range
AT52BR1662T/1664T-70
-40°C - 85°C
AT52BR1662T/1664T-90
-40°C - 85°C
Operating Temperature (Case)
CC Power Supply
Ind.
V
2.7V to 3.3V
2.7V to 3.3V
Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
WE
VIH
VIL
X
RESET
VIH
VPP
Ai
Ai
Ai
X
I/O
Read
VIL
VIH
X(1)
X
X
DOUT
(6)
Program/Erase(2)
Standby/Program Inhibit
VIH
VIHPP
DIN
VIH
X
X
X
High-Z
VIH
X
VIH
Program Inhibit
X
VIL
X
VIH
(7)
X
X
VIH
VILPP
Output Disable
Reset
X
VIH
X
X
VIH
X
X
High-Z
High-Z
X
X
VIL
X
Product Identification
A1 - A19 = VIL, A9 = VH(3), A0 = VIL
A1 - A19 = VIL, A9 = VH(3), A0 = VIH
A0 = VIL, A1 - A19 = VIL
Manufacturer Code(4)
Device Code(4)
Hardware
VIL
VIL
VIH
VIH
VIH
Manufacturer Code(4)
Device Code(4)
Software(5)
A0 = VIH, A1 - A19 = VIL
Notes: 1. X can be VIL or VIH.
2. Refer to AC programming waveforms on page 22.
3. VH = 12.0V 0.5V.
4. Manufacturer Code: 001FH, Device Code: 00C2H.
5. See details under “Software Product Identification Entry/Exit” on page 23.
6. VIHPP (min) = 1.65V; VIHPP (max) = 3.6V. For faster erase/program operations, VPP can be set to 5.0V 0.5V or 12V 0.5V.
7. VILPP (max) = 0.8V.
16
AT52BR1662T/1664T
2212A–11/01
AT52BR1662T/1664T
DC Characteristics
Symbol
Parameter
Condition
Min
Max
10
10
10
1
Units
µA
µA
µA
mA
µA
mA
mA
µA
µA
mA
mA
mA
mA
V
ILI
Input Load Current
VIN = 0V to VCC
ILO
Output Leakage Current
VCC Standby Current CMOS
VCC Standby Current TTL
VCC Standby Current TTL
VCC Active Read Current
VCC Programming Current (VPP = VCC
VI/O = 0V to VCC
ISB1
ISB2
ISB3
CE = VCC - 0.3V to VCC
CE = 2.0V to VCC
CE = 2.0V to VCC, VCC = 2.85V
f = 5 MHz; IOUT = 0 mA, 3.3V≤ VCC
10
30
45
10
10
40
5
(1)(2)
ICC
ICC1
)
V
PP = 0V, VCC = 3.0V
IPP1
VPP Input Load Current
VPP = VCC = 3.0V
ICC2
IPP2
ICC3
IPP3
VIL
VCC Programming Current (VPP = 5.0V 0.5V)
VPP Programming Current (VPP = 5.0V 0.5V)
VCC Programming Current (VPP = 12.0V 0.5V)
VPP Programming Current (VPP = 12.0V 0.5V)
Input Low Voltage
40
6
0.6
VIH
Input High Voltage
2.0
V
VOL1
VOL2
Output Low Voltage
IOL = 2.1 mA
IOL = 1.0 mA
0.45
0.20
V
Output Low Voltage
V
V
V
V
IOH = -400 µA
VCCQ < 2.6V
VCCQ - 0.2
2.4
VOH1
Output High Voltage
Output High Voltage
I
OH = -400 µA
VCCQ ≥ 2.6V
V
V
V
IOH = -100 µA
OH = -100 µA
VCCQ < 2.6V
VCCQ - 0.1
2.5
VOH2
I
VCCQ ≥ 2.6V
Notes: 1. In the erase mode, ICC is 50 mA.
2. For 3.3V < VCC < 3.6V, ICC (max) = 35 mA
17
2212A–11/01
.
AC Read Characteristics
AT52BR1662T/1664T-70
AT52BR1662T/1664T-90
Symbol
tRC
Parameter
Min
Max
70
Min
Max
90
Units
ns
Read Cycle Time
tACC
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
70
90
ns
(1)
tCE
70
90
ns
(2)
tOE
0
0
35
0
0
40
ns
(3)(4)
tDF
25
25
ns
Output Hold from OE, CE or Address, whichever occurred
first
tOH
tRO
0
0
ns
ns
RESET to Output Delay
100
100
AC Read Waveforms(1)(2)(3)(4)
tRC
ADDRESS
CE
ADDRESS VALID
tCE
tOE
OE
tDF
tOH
tACC
tRO
RESET
HIGH Z
OUTPUT
VALID
OUTPUT
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
18
AT52BR1662T/1664T
2212A–11/01
AT52BR1662T/1664T
Input Test Waveforms and Measurement Level
Output Test Load
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
Typ
4
Max
6
Units
Conditions
VIN = 0V
pF
pF
COUT
8
12
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested
19
2212A–11/01
.
AC Word Load Characteristics
Symbol
Parameter
Min
0
Max
Units
ns
t
AS, tOES
Address, OE Setup Time
Address Hold Time
tAH
tCS
tCH
tWP
tDS
40
0
ns
Chip Select Setup Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Setup Time
ns
0
ns
40
30
0
ns
ns
t
DH, tOEH
Data, OE Hold Time
Write Pulse Width High
ns
tWPH
30
ns
AC Word Load Waveforms
WE Controlled
CE Controlled
20
AT52BR1662T/1664T
2212A–11/01
AT52BR1662T/1664T
Program Cycle Characteristics
Symbol
Parameter
Min
Typ
20
Max
200
100
Units
µs
tBP
Word Programming Time (VIHPP < VPP < 4.5V)
Word Programming Time (VPP > 4.5V)
Address Setup Time
tBPVPP
tAS
10
µs
0
40
30
0
ns
tAH
Address Hold Time
ns
tDS
Data Setup Time
ns
tDH
Data Hold Time
ns
tWP
Write Pulse Width
40
30
70
500
50
ns
tWPH
tWC
Write Pulse Width High
ns
Write Cycle Time
ns
tRP
Reset Pulse Width
ns
tRH
Reset High Time before Read
Chip Erase Cycle Time (VPP < 4.5V)
Chip Erase Cycle Time (VPP > 4.5V)
Sector Erase Cycle Time (VPP < 4.5V)
Erase or Program Suspend Time
ns
tEC
12
6
seconds
seconds
ms
tECVPP
tSEC
tEPS
300
400
15
µs
Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
t
t
t
WP
BP
WPH
WE
t
t
t
DH
AS
AH
555
t
AAA
555
ADDRESS
555
A0 -A19
DATA
WC
t
DS
INPUT
DATA
AA
55
A0
AA
Sector or Chip Erase Cycle Waveforms
(1)
OE
CE
t
t
WP
WPH
WE
A0-A19
DATA
t
t
t
DH
AS
AH
555
t
AAA
555
555
AAA
Note
2
WC
t
t
EC
DS
AA
WORD
55
WORD
80
WORD
AA
WORD
55
WORD
Note 3
0
1
2
3
4
WORD 5
Notes: 1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased.
(See note 3 under Command Definitions.)
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
21
2212A–11/01
Data Polling Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
OE Hold Time
10
ns
OE to Output Delay(2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 18.
Data Polling Waveforms
Toggle Bit Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
tOEHP
tWR
OE Hold Time
10
ns
OE to Output Delay(2)
OE High Pulse
ns
50
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 18.
Toggle Bit Waveforms(1)(2)(3)
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.
The tOEHP specification must be met by the toggling input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
22
AT52BR1662T/1664T
2212A–11/01
AT52BR1662T/1664T
Software Product Identification Entry(1)
Sector Lockdown Enable Algorithm(1)
LOAD DATA AA
TO
LOAD DATA AA
TO
ADDRESS 555
ADDRESS 555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS AAA
ADDRESS AAA
LOAD DATA 80
TO
LOAD DATA 90
TO
ADDRESS 555
ADDRESS 555
ENTER PRODUCT
IDENTIFICATION
LOAD DATA AA
TO
(2)(3)(5)
MODE
ADDRESS 555
Software Product Identification Exit(1)(6)
LOAD DATA 55
TO
OR
LOAD DATA AA
TO
LOAD DATA F0
TO
ADDRESS AAA
ADDRESS 555
ANY ADDRESS
LOAD DATA 60
TO
EXIT PRODUCT
IDENTIFICATION
LOAD DATA 55
TO
SECTOR ADDRESS
(4)
MODE
ADDRESS AAA
LOAD DATA F0
TO
(2)
PAUSE 200 µs
ADDRESS 555
Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
Address Format: A11 - A0 (Hex) and A11 - A19 (Don’t
Care).
EXIT PRODUCT
IDENTIFICATION
(4)
MODE
2. Sector Lockdown feature enabled.
Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
Address Format: A11 - A0 (Hex) and A11 - A19 (Don’t Care).
2. A1 - A19 = VIL. Manufacturer Code is read for A0 = VIL;
Device Code is read for A0 = VIH. Additional Device Code is
read for address 0003H.
3. The device does not remain in identification mode if powered
down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 001FH.
Device Code: 00C2H.
Additional Device Code: 0008H.
6. Either one of the Product ID Exit commands can be used.
23
2212A–11/01
2-megabit
SRAM
Description
The 2-megabit SRAM is a high-speed, super low-power CMOS SRAM organized as 128K
words by 16 bits. The SRAM uses high-performance full CMOS process technology and is
designed for high-speed and low-power circuit technology. It is particularly well-suited for the
high-density low-power system application. This device has a data retention mode that guar-
antees data to remain valid at a minimum power supply voltage of 1.2V.
Features
• Fully Static Operation and Tri-state Output
• TTL Compatible Inputs and Outputs
• Battery Backup
– 1.2V (Min) Data Retention
Operation
Current/ICC (mA)
(Max)
Standby
Current (µA)
(Max)
Temperature
Voltage (V)
Speed (ns)
(°C)
2.7 - 3.3
70
10
10
-40 - 85
Block Diagram
ROW DECODER
A0
I/O0
I/O7
I/O8
MEMORY ARRAY
512K X 16
I/O15
A16
SCS1
SCS2
SOE
SLB
SUB
SWE
24
AT52BR1662T/1664T
2212A–11/01
AT52BR1662T/1664T
Absolute Maximum Ratings(1)
Symbol
VIN, VOUT
VCC
Parameter
Rating
-0.3 to 3.6
-0.3 to 4.6
-40 to 85
-55 to 150
1.0
Unit
V
Input/Output Voltage
Power Supply
V
TA
Operating Temperature
Storage Temperature
Power Dissipation
°C
°C
W
TSTG
PD
Note:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is
stress rating only and the functional operation of the device under these or any other conditions above those indicated in the
operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may
affect reliability.
Truth Table
I/O Pin
I/O8 - I/O15
SCS1
H(1)
X(1)
X
SCS2
SWE
SOE
SLB(2)
SUB(2)
Mode
I/O0 - I/O7
Power
X
L
X
X
X
X
Deselected
High-Z
High-Z
High-Z
Standby
X
H
L
H
H
L
L(1)
H
H
H
H
L
H
X
L
H
L
Output Disabled
Write
High-Z
Active
Active
Active
L
L
H
L
DIN
High-Z
DIN
High-Z
DIN
L
H
L
L
DIN
L
H
L
DOUT
High-Z
DOUT
High-Z
DOUT
DOUT
L
H
H
L
Read
L
Notes: 1. H = VIH, L = VIL, X = Don't Care (VIL or VIH)
2. SUB, SLB (Upper, Lower Byte Enable). These active LOW inputs allow individual bytes to be written or read. When SLB is
LOW, data is written or read to the lower byte, I/O0 - I/O8. When SUB is LOW, data is written or read to the upper byte, I/O9
- I/O16.
Recommended DC Operating Condition
Symbol
Parameter
Min
Typ
3.0
0
Max
3.3
Unit
V
VCC
Supply Voltage
Ground
2.3
VSS
0
0
V
VIH
Input High Voltage
Input Low Voltage
2.2
VCC + 0.3
0.4
V
VIL
-0.2(1)
V
(1)
Note:
1. Undershoot: VIL = -1.5V for pulse width less than 30 ns. Undershoot is sampled, not 100% tested.
25
2212A–11/01
DC Electrical Characteristics
TA = -40°C to 85°C
Symbol
ILI
Parameter
Test Condition
Min
-1
Typ(1)
Max
1
Unit
µA
Input Leakage Current
Output Leakage Current
VSS < VIN < VCC
ILO
VSS < VOUT < VCC
,
-1
1
µA
SCS1 = VIH or SCS2=VIL or
SOE = VIH or SWE = VIL or
SUB = VIH, SLB = VIH
ICC
Operating Power Supply Current
Average Operating Current
SCS1 = VIL, SCS2=VIH,
VIN = VIH or VIL, II/O = 0 mA
5
4
10
6
mA
mA
ICC1
Cycle Time = 1 µs
II/O = 0 mA,
SCS1 = 0.2V, SCS2 = VCC -0.2V,
VIN ≤ 0.2V or VIN ≥ VCC - 0.2V
Cycle Time = Min,
30
45
mA
100% Duty, II/O = 0 mA
SCS1 = VIL, SCS2 = VIH,
VIN = VIH or VIL
ISB
Standby Current (TTL Input)
Standby Current (CMOS Input)
SCS1 = VIH or SCS2 = VIL
0.5
10
mA
µA
ISB1
SCS1 ≥ VCC - 0.2V
or
LL
SL
0.4
2
µA
SCS2 ≤ VSS + 0.2V
IOL = 0.5 mA
VOL
VOH
Output Low
Output High
0.4
V
V
IOH = -0.5 mA
2.0
Note:
1. Typical values are at VCC = 3.0V, TA = 25°C. Typical values are not 100% tested.
Capacitance(1)
(Temp = 25°C, f = 1.0 MHz)
Symbol
Parameter
Condition
IN = 0 V
Max
Unit
CIN
Input Capacitance (Add, SCS1,
SCS2, SLB, SUB, SWE, SOE)
V
8
pF
COUT
Output Capacitance (I/O)
VI/O = 0 V
10
pF
Note:
1. These parameters are sampled and not 100% tested.
26
AT52BR1662T/1664T
2212A–11/01
AT52BR1662T/1664T
AC Characteristics
TA = -40°C to 85°C, Unless Otherwise Specified
70 ns
#
1
Symbol
tRC
Parameter
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
70
2
tAA
Address Access Time
70
70
35
35
3
tACS
tOE
Chip Select Access Time
Output Enable to Output Valid
SLB, SUB Access Time
4
5
tBA
6
tCLZ
tOLZ
tBLZ
tCHZ
tOHZ
tBHZ
tOH
Chip Select to Output in Low Z
Output Enable to Output in Low Z
SLB, SUB Enable to Output in Low Z
Chip Deselection to Output in High Z
Out Disable to Output in High Z
SLB, SUB Disable to Output in High Z
Output Hold from Address Change
Write Cycle Time
5
0
7
8
0
9
0
30
30
30
10
11
12
13
14
15
16
17
18
19
20
21
22
23
0
0
10
70
60
60
60
0
tWC
tCW
tAW
Chip Selection to End of Write
Address Valid to End of Write
SLB, SUB Valid to End of Write
Address Setup Time
tBW
tAS
tWP
tWR
tWHZ
tDW
Write Pulse Width
50
0
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
0
25
30
0
tDH
tOW
5
AC Test Conditions
TA = -40°C to 85°C, Unless Otherwise Specified
Parameter
Value
Input Pulse Level
0.4V to 2.2V
Input Rise and Fall Time
5 ns
Input and Output Timing Reference Level
1.5V
Output Load
CL = 5 pF + 1 TTL Load
CL = 30 pF + 1 TTL Load
CL = 5 pF + 1 TTL Load
CL = 30 pF + 1 TTL Load
27
2212A–11/01
Output Test Load
Timing Diagrams
Read Cycle 1(1),(4)
tRC
ADDRESS
tAA
tOH
tACS
SCS1
SCS2
SUB, SLB
SOE
(3)
tCHZ
tBA
(3)
tBHZ
tOE
(3)
tOLZ
(3)
tOHZ
(3)
tBLZ
(3)
tCLZ
HIGH-Z
DATA OUT
DATA VALID
Read Cycle 2(1) (2) (4)
,
,
tRC
ADDRESS
tAA
tOH
tOH
PREVIOUS DATA
DATA OUT
DATA VALID
Read Cycle 3(1) (2) (4)
,
,
SCS1
SUB, SLB
SCS2
tACS
(3)
tCHZ
(3)
tCLZ
DATA OUT
DATA VALID
Notes: 1. Read Cycle occurs whenever a high on the SWE and SOE is low, while SUB and/or SLB and SCS1 and SCS2 are in active
status.
2. SOE = VIL.
3. Transition is measured + 200 mV from steady state voltage. This parameter is sampled and not 100% tested.
4. SCS1 in high for the standby, low for active. SCS2 in low for the standby, high for active. SUB and SLB in high for the
standby, low for active.
28
AT52BR1662T/1664T
2212A–11/01
AT52BR1662T/1664T
Write Cycle 1 (SWE Controlled)(1),(4),(8)
tWC
ADDRESS
SCS1
(2)
tWR
tCW
SCS2
tAW
tBW
SUB, SLB
tWP
SWE
tAS
tDW
tDH
tAS
HIGH-Z
DATA IN
DATA VALID
(3)(7)
tOW
tWHZ
(5)
(5)
DATA OUT
Write Cycle 2 (SCS1, SCS2 Controlled)(1),(4),(8)
tWC
ADDRESS
(2)
tCW
tWR
tAS
SCS1
SCS2
tAW
tBW
SUB, SLB
SWE
tWP
tDW
tDH
HIGH-Z
DATA IN
DATA VALID
HIGH-Z
DATA OUT
Notes: 1. A write occurs during the overlap of a low SWE, a low SCS1, a high SCS2 and a low SUB and/or SLB.
2. tWR is measured from the earlier of SCS1, SLB, SUB, or SWE going high or SCS2 going low to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be
applied.
4. If the SCS1, SLB and SUB low transition and SCS2 high transition occur simultaneously with the SWE low transition or after
the SWE transition, outputs remain in a high impedance state.
5. Q (data out) is the same phase with the write data of this write cycle.
6. Q (data out) is the read data of the next address.
7. Transition is measured + 200 mV from steady state. This parameter is sampled and not 100% tested.
8. SCS1 in high for the standby, low for active SCS2 in low for the standby, high for active. SUB and SLB in high for the standby,
low for active.
29
2212A–11/01
Data Retention Electric Characteristic
TA = -40°C to 85°C
Symbol Parameter
Test Condition
Min
Typ
Max
Unit
VDR
VCC for Data Retention
SCS1 > VCC -0.2V,
1.2
3.3
V
SCS2 ≤ 0.2V or
VCC - 0.2V,
VSS ≤ VIN ≤ VCC
ICCDR
Data Retention Current
VCC = 3.0V,
SCS1 > VCC - 0.2V or
9.5
0.7
µA
SCS2 ≤ VSS + 0.2V or
VSS ≤ VIN ≤ VCC
0.4(1)
µA
ns
tCDR
tR
Chip Deselect to Data
Retention Time
0
See Data Retention Timing Diagram
(2)
Operating Recovery Time
tRC
ns
Notes: 1. Typical values are under the condition of TA = 25°C. Typical values are sampled and not 100% tested.
2. tRC is read cycle time.
Data Retention Timing Diagram 1
DATA RETENTION MODE
VCC
2.3V
tCDR
tR
IH
VDR
SCS1 > VCC - 0.2V
SCS1
VSS
Data Retention Timing Diagram 2
DATA RETENTION MODE
VCC
2.3V
tCDR
tR
SCS2
VDR
0.4V
VSS
SCS2 < 0.2V
30
AT52BR1662T/1664T
2212A–11/01
AT52BR1662T/1664T
4-megabit
SRAM
Description
The 4-megabit SRAM is a high-speed, super low-power CMOS SRAM organized as 256K
words by 16 bits. The SRAM uses high-performance full CMOS process technology and is
designed for high-speed and low-power circuit technology. It is particularly well-suited for the
high-density low-power system application. This device has a data retention mode that guar-
antees data to remain valid at a minimum power supply voltage of 1.2V.
Features
• Fully Static Operation and Tri-state Output
• TTL Compatible Inputs and Outputs
• Battery Backup
– 1.2V (Min) Data Retention
Operation
Current/ICC (mA)
(Max)
Standby Current
(µA)
Temperature
Voltage (V)
Speed (ns)
(Max)
(°C)
2.7 - 3.3
70
5
15
-40 - 85
Block Diagram
ROW DECODER
A0
I/O0
I/O7
I/O8
MEMORY ARRAY
256K X 16
I/O15
A17
SCS1
SCS2
SOE
SLB
SUB
SWE
31
2212A–11/01
Absolute Maximum Ratings(1)
Symbol
VIN, VOUT
VCC
Parameter
Rating
-0.3 to 3.6
-0.3 to 4.6
-40 to 85
-55 to 150
1.0
Unit
V
Input/Output Voltage
Power Supply
V
TA
Operating Temperature
Storage Temperature
Power Dissipation
°C
°C
W
TSTG
PD
Note:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is
stress rating only and the functional operation of the device under these or any other conditions above those indicated in the
operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may
affect reliability.
Truth Table
I/O Pin
I/O8 - I/O15
SCS1
H(1)
X(1)
X
SCS2
SWE
SOE
SLB(2)
SUB(2)
Mode
I/O0 - I/O7
Power
X
L
X
X
X
X
Deselected
High-Z
High-Z
High-Z
Standby
X
H
L
H
H
L
L(1)
H
H
H
L
H
X
H
L
Output Disabled
High-Z
Active
Active
L
L
H
L
DIN
High-Z
DIN
High-Z
DIN
H
L
Write
DIN
L
L
DIN
High-Z
High-Z
DOUT
DOUT
High-Z
L
H
L
DOUT
High-Z
DOUT
DOUT
H
L
H
H
L
Read
Active
L
L
Notes: 1. H = VIH, L = VIL, X = Don't Care (VIL or VIH)
2. SUB, SLB (Upper, Lower Byte Enable). These active LOW inputs allow individual bytes to be written or read. When SLB is
LOW, data is written or read to the lower byte, I/O0 - I/O7. When SUB is LOW, data is written or read to the upper byte, I/O8
- I/O15.
Recommended DC Operating Condition
Symbol
Parameter
Min
Typ
3.0
0
Max
3.3
Unit
V
VCC
Supply Voltage
Ground
2.7
VSS
0
0
V
VIH
Input High Voltage
Input Low Voltage
2.2
VCC + 0.3
0.6
V
VIL
-0.31(1)
V
(1)
Note:
1. Undershoot: VIL = -1.5V for pulse width less than 30 ns. Undershoot is sampled, not 100% tested.
32
AT52BR1662T/1664T
2212A–11/01
AT52BR1662T/1664T
DC Electrical Characteristics
TA = -40°C to 85°C
Symbol
ILI
Parameter
Test Condition
Min
-1
Max
1
Unit
µA
Input Leakage Current
Output Leakage Current
VSS < VIN < VCC
ILO
VSS < VOUT < VCC
,
-1
1
µA
SCS1 = VIH or SCS2=VIL or
SOE = VIH or SWE = VIL or
SUB = VIH, SLB = VIH
ICC
Operating Power Supply Current
Average Operating Current
SCS1 = VIL, SCS2=VIH,
VIN = VIH or VIL, II/O = 0 mA
5
mA
mA
ICC1
SCS1 = VIL, SCS2 = VIH,
35
VIN = VIH or VIL, Cycle Time = Min
100% Duty, II/O = 0 mA
SCS1 < 0.2V, SCS2 > VCC - 0.2V
5
mA
mA
VIN < 0.2V or VIN > VCC - 0.2V,
Cycle Time = 1 µs
100% Duty, II/O = 0 mA
ISB
Standby Current (TTL Input)
Standby Current (CMOS Input)
SCS1 = VIH or SCS2 = VIL or
SUB, SLB = VIH
0.5
VIN = VIH or VIL
ISB1
SCS1 > VCC - 0.2V or
SCS2 < VSS + 0.2V or
SUB, SLB > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < VSS + 0.2V
SL
LL
4
µA
µA
15
0.4
VOL
VOH
Output Low
Output High
IOL = 0.1 mA
IOH = -0.1 mA
V
V
2.4
Capacitance(1)
(Temp = 25°C, f = 1.0 MHz)
Symbol
Parameter
Condition
Max
Unit
CIN
Input Capacitance (Add, SCS1,
SCS2, SLB, SUB, SWE, SOE)
VIN = 0 V
8
pF
COUT
Output Capacitance (I/O)
VI/O = 0 V
10
pF
Note:
1. These parameters are sampled and not 100% tested.
33
2212A–11/01
AC Characteristics
TA = -40°C to 85°C, Unless Otherwise Specified
70 ns
#
1
Symbol
tRC
Parameter
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
70
2
tAA
Address Access Time
70
70
35
70
3
tACS
tOE
Chip Select Access Time
Output Enable to Output Valid
SLB, SUB Access Time
4
5
tBA
6
tCLZ
tOLZ
tBLZ
tCHZ
tOHZ
tBHZ
tOH
Chip Select to Output in Low Z
Output Enable to Output in Low Z
SLB, SUB Enable to Output in Low Z
Chip Deselection to Output in High Z
Out Disable to Output in High Z
SLB, SUB Disable to Output in High Z
Output Hold from Address Change
Write Cycle Time
10
5
7
8
10
0
9
30
30
30
10
11
12
13
14
15
16
17
18
19
20
21
22
23
0
0
10
70
60
60
60
0
tWC
tCW
tAW
Chip Selection to End of Write
Address Valid to End of Write
SLB, SUB Valid to End of Write
Address Setup Time
tBW
tAS
tWP
tWR
tWHZ
tDW
Write Pulse Width
50
0
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
0
20
30
0
tDH
tOW
5
AC Test Conditions
TA = -40°C to 85°C, Unless Otherwise Specified
Parameter
Value
Input Pulse Level
0.4V to 2.2V
5 ns
Input Rise and Fall Time
Input and Output Timing Reference Level
1.5V
Output Load
CL = 5 pF + 1 TTL Load
CL = 30 pF + 1 TTL Load
CL = 5 pF + 1 TTL Load
CL = 30 pF + 1 TTL Load
34
AT52BR1662T/1664T
2212A–11/01
AT52BR1662T/1664T
Output Test Load
Timing Diagrams
Read Cycle 1(1),(4)
tRC
ADDRESS
SCS1
tAA
tOH
tACS
SCS2
SUB, SLB
SOE
(3)
tCHZ
tBA
(3)
tBHZ
tOE
(3)
tOLZ
(3)
tOHZ
(3)
tBLZ
(3)
tCLZ
HIGH-Z
DATA OUT
DATA VALID
Read Cycle 2(1) (2) (4)
,
,
tRC
ADDRESS
tAA
tOH
tOH
PREVIOUS DATA
DATA OUT
DATA VALID
Read Cycle 3(1) (2) (4)
,
,
SCS1
SUB, SLB
SCS2
tACS
(3)
tCHZ
(3)
tCLZ
DATA OUT
DATA VALID
Notes: 1. Read Cycle occurs whenever a high on the SWE and SOE is low, while SUB and/or SLB and SCS1 and SCS2 are in active
status.
2. SOE = VIL.
3. Transition is measured + 200 mV from steady state voltage. This parameter is sampled and not 100% tested.
4. SCS1 in high for the standby, low for active. SCS2 in low for the standby, high for active. SUB and SLB in high for the
standby, low for active.
35
2212A–11/01
Write Cycle 1 (SWE Controlled)(1),(4),(8)
tWC
ADDRESS
SCS1
(2)
tWR
tCW
SCS2
tAW
tBW
SUB, SLB
tWP
SWE
tAS
tDW
tDH
tAS
HIGH-Z
DATA IN
DATA VALID
(3)(7)
tOW
tWHZ
(5)
(5)
DATA OUT
Write Cycle 2 (SCS1, SCS2 Controlled)(1),(4),(8)
tWC
ADDRESS
(2)
tCW
tWR
tAS
SCS1
SCS2
tAW
tBW
SUB, SLB
SWE
tWP
tDW
tDH
HIGH-Z
DATA IN
DATA VALID
HIGH-Z
DATA OUT
Notes: 1. A write occurs during the overlap of a low SWE, a low SCS1, a high SCS2 and a low SUB and/or SLB.
2. tWR is measured from the earlier of SCS1, SLB, SUB, or SWE going high or SCS2 going low to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be
applied.
4. If the SCS1, SLB and SUB low transition and SCS2 high transition occur simultaneously with the SWE low transition or after
the SWE transition, outputs remain in a high impedance state.
5. Q (data out) is the same phase with the write data of this write cycle.
6. Q (data out) is the read data of the next address.
7. Transition is measured + 200 mV from steady state. This parameter is sampled and not 100% tested.
8. SCS1 in high for the standby, low for active SCS2 in low for the standby, high for active. SUB and SLB in high for the standby,
low for active.
36
AT52BR1662T/1664T
2212A–11/01
AT52BR1662T/1664T
Data Retention Electric Characteristic
TA = -40°C to 85°C
Symbol
Parameter
Test Condition
Min
Typ(1)
Max
Unit
VDR
VCC for Data Retention
SCS1 > VCC - 0.2V or
SCS2 < VSS + 0.2V or
SUB, SLB > VCC - 0.2V
VIN > VCC - 0.2V or
1.2
3.3
V
VIN < VSS + 0.2V
ICCDR
Data Retention Current
Vcc=1.5V,
SL
LL
0.1
0.1
2
µA
µA
SCS1 > VCC - 0.2V or
SCS2 < VSS + 0.2V or
SUB, SLB > VCC - 0.2V
VIN > VCC - 0.2V or
10
VIN < VSS + 0.2V
tCDR
Chip Deselect to Data
Retention Time
0
ns
ns
See Data Retention Timing Diagram
(2)
tR
Note:
Operating Recovery Time
tRC
1. Typical values are under the condition of TA = 25°C. Typical values are sampled and not 100% tested.
2. tRC is read cycle time.
Data Retention Timing Diagram 1
DATA RETENTION MODE
VCC
2.7V
tCDR
tR
IH
VDR
SCS1 > VCC - 0.2V
SCS1
VSS
Data Retention Timing Diagram 2
DATA RETENTION MODE
VCC
2.7V
tCDR
tR
SCS2
VDR
0.4V
VSS
SCS2 < 0.2V
37
2212A–11/01
Ordering Information
tACC (ns)
Voltage Range
Ordering Code
Package
Operation Range
70
2.7V - 3.3V
AT52BR1662T-70CI
66C5
Industrial
(-40° to 85°C)
90
70
90
2.7V - 3.3V
2.7V - 3.3V
2.7V - 3.3V
AT52BR1662T-90CI
AT52BR1664T-70CI
AT52BR1664T-90CI
66C5
66C5
66C5
Industrial
(-40° to 85°C)
Industrial
(-40° to 85°C)
Industrial
(-40° to 85°C)
Package Type
66C5
66-ball, Plastic Chip-scale Ball Grid Array Package (CBGA)
38
AT52BR1662T/1664T
2212A–11/01
AT52BR1662T/1664T
Packaging Information
66C5 – CBGA
C
0.12
E
C
Seating Plane
Marked A1 identifier
D
Side View
A1
Top View
A
0.60 REF
E1
A1 Ball Corner
e
1.20 REF
A
B
C
D
E
F
D1
G
H
COMMON DIMENSIONS
(Unit of Measure = mm)
e
2
12 11 10
9
8
7
5
4
1
6
3
MIN
9.90
–
MAX
10.10
–
NOM
10.00
8.80
8.00
5.60
–
NOTE
SYMBOL
E
Øb
E1
D
Bottom View
7.90
–
8.10
–
D1
A
–
1.20
–
A1
e
0.25
–
0.80 BSC
0.40
b
–
–
09/19/01
DRAWING NO. REV.
66C5
TITLE
2325 Orchard Parkway
San Jose, CA 95131
66C5, 66-ball (12 x 8 Array), 10 x 8 x 1.2 mm Body, 0.8 mm Ball
Pitch Chip-scale Ball Grid Array Package (CBGA)
A
R
39
2212A–11/01
Atmel Headquarters
Atmel Product Operations
Corporate Headquarters
2325 Orchard Parkway
San Jose, CA 95131
TEL (408) 441-0311
FAX (408) 487-2600
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FAX (33) 4-7658-3480
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© Atmel Corporation 2001.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
ATMEL® is the registered trademark of Atmel.
Other terms and product names may be the trademarks of others.
Printed on recycled paper.
2212A–11/01/xM
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