AT52BR1664A-90CJ [MICROCHIP]
Memory Circuit, 1MX16, CMOS, PBGA66;
| 型号： | AT52BR1664A-90CJ |
| 厂家： | 
MICROCHIP |
| 描述： | Memory Circuit, 1MX16, CMOS, PBGA66 ATM 异步传输模式 静态存储器 内存集成电路 |
| 文件： | 总35页 (文件大小：495K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
•
•
•
16-Mbit (x16) Flash and 4-megabit SRAM
2.7V to 3.3V Operating Voltage
Low Operating Power
– 40 mA Operating Current (Maximum)
– 35 µA Standby Current (Maximum)
Industrial Temperature Range
•
Flash
16-megabit
Flash +
•
•
•
2.7V to 3.3V Read/Write
Access Time – 70 ns, 90 ns
Sector Erase Architecture
4-megabit
SRAM Stack
Memory
– Thirty-one 32K Word (64-Kbyte) Sectors with Individual Write Lockout
– Eight 4K Word (8-Kbyte) Sectors with Individual Write Lockout
Fast Word Program Time – 12 µs
•
•
Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming from Any Sector by Suspending Erase of a
Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
Low-power Operation
•
AT52BR1664A
AT52BR1664AT
– 12 mA Active
– 13 µA Standby
•
•
•
•
•
•
•
Data Polling, Toggle Bit, Ready/Busy for End of Program Detection
VPP Pin for Write Protection and Accelerated Program/Erase Operations
RESET Input for Device Initialization
Sector Lockdown Support
Not Recommended
for New Designs.
Top/Bottom Boot Block Configuration
128-bit Protection Register
Minimum 100,000 Erase Cycles
SRAM
•
•
•
•
•
4-megabit (256K x 16)
2.7V to 3.3V VCC Operating Voltage
70 ns Access Time
Fully Static Operation and Tri-state Output
1.2V (Min) Data Retention
Device Number
Flash Configuration
16M (1M x 16)
SRAM Configuration
AT52BR1664A(T)
4M (256K x 16)
3361D–STKD–1/07
1. CBGA Top View
1
3
4
5
6
7
8
9
10 11
12
2
A
B
C
D
E
F
NC
NC
NC
NC
NC
A16
WE
A11
A8
A15
A10
A14
A9
A13
A12
SWE
I/O6
GND
I/O14
I/O4
SVcc
I/O2
I/O0
A1
NC
I/O7
I/O5
Vcc
I/O15
I/O13
I/O12
RDY BUSY
RESET
Vpp
SGND
NC
SCS2
I/O10
I/O8
A19
SOE
A7
I/O11
I/O3
I/O1
SCS1
NC
SLB
A18
NC
SUB
I/O9
A3
G
H
A17
A6
A0
A2
NC
NC
NC
NC
A5
A4
CE
GND
OE
2. Pin Configurations
Function
Pin Name
A0 - A17
A18 - A19
CE
Flash/SRAM Common Address Input for 4M SRAM
Flash Address Input
Flash Chip Enable
OE/SOE
WE/SWE
VCC
Flash/SRAM, Output Enable
Flash/SRAM, Write Enable
Flash Power Supply
VPP
Optional Flash Power Supply for Faster Program/Erase Operations
Data Inputs/Outputs
I/O0-I/O15
SCS1, SCS2
RDY/BUSY
SVCC
SRAM Chip Select
Flash Ready/Busy Output
SRAM Power Supply
GND/SGND
SUB
Flash/SRAM GND
SRAM Upper Byte
SLB
SRAM Lower Byte
NC
No Connect
RESET
Flash Reset
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AT52BR1664A(T)
3. Description
The AT52BR1664A(T) combines a single plane 16-Mbit Flash and a 4-megabit SRAM in a stacked 66-ball CBGA package.
Both devices operate at 2.7V to 3.3V in the industrial temperature range.
4. Block Diagram
ADDRESS
OE WE
SOE SWE
RESET
CE
SCS1
SCS2
FLASH
SRAM
SUB
SLB
RDY/BUSY
DATA
5. Absolute Maximum Ratings
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Temperature under Bias ................................. -40°C to +85° C
Storage Temperature.................................... -55°C to +150° C
All Input Voltages
(including NC Pins)
with Respect to Ground.....................................-0.2V to +3.6V
Voltage on VPP
with Respect to Ground.....................................-0.2V to + 10V
All Output Voltages
with Respect to Ground.....................................-0.2V to +3.6V
6. DC and AC Operating Range
AT52BR1664A(T)-70, -90
-40°C - 85°C
Operating Temperature (Case)
VCC Power Supply
Industrial
2.7V to 3.3V
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7. 16-Mbit Flash Memory Block Diagram
I/O0 - I/O15
OUTPUT
BUFFER
INPUT
BUFFER
IDENTIFIER
REGISTER
INPUT
A0 - A19
BUFFER
STATUS
CE
REGISTER
WE
COMMAND
REGISTER
OE
RESET
ADDRESS
LATCH
DATA
RDY/BUSY
VPP
COMPARATOR
WRITE STATE
MACHINE
PROGRAM/ERASE
VOLTAGE SWITCH
Y-DECODER
X-DECODER
Y-GATING
VCC
GND
MAIN
MEMORY
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AT52BR1664A(T)
8. 16-Mbit Flash Description
The 16-Mbit Flash is organized as 1,048,576 words of 16 bits each. The x16 data appears on
I/O0 - I/O15. The memory is divided into 39 sectors for erase operations. The device has CE and
OE control signals to avoid any bus contention. This device can be read or reprogrammed using
a single power supply, making it ideally suited for in-system programming.
The device powers on in the read mode. Command sequences are used to place the device in
other operation modes such as program and erase. The device has the capability to protect the
data in any sector (see “Sector Lockdown” on page 8).
To increase the flexibility of the device, it contains an Erase Suspend and Program Suspend
feature. This feature will put the erase or program on hold for any amount of time and let the
user read data from or program data to any of the remaining sectors within the memory. The
end of a program or an erase cycle is detected by the READY/BUSY pin, Data Polling or by the
toggle bit.
The VPP pin provides data protection. When the VPP input is below 0.4V, the program and erase
functions are inhibited. When VPP is at 0.9V or above, normal program and erase operations can
be performed.
A six-byte command (Enter Single Pulse Program Mode) sequence to remove the requirement
of entering the three-byte program sequence is offered to further improve programming time.
After entering the six-byte code, only single pulses on the write control lines are required for writ-
ing into the device. This mode (Single Pulse Word Program) is exited by powering down the
device, or by pulsing the RESET pin low for a minimum of 500 ns and then bringing it back to
V
CC. Erase, Erase Suspend/Resume and Program Suspend/Resume commands will not work
while in this mode; if entered they will result in data being programmed into the device. It is not
recommended that the six-byte code reside in the software of the final product but only exist in
external programming code.
9. Device Operation
9.1
Read
The Flash is accessed like an EPROM. When CE and OE are low and WE is high, the data
stored at the memory location determined by the address pins are asserted on the outputs. The
outputs are put in the high impedance state whenever CE or OE is high. This dual-line control
gives designers flexibility in preventing bus contention.
9.2
Command Sequences
When the device is first powered on, it will be reset to the read or standby mode, depending
upon the state of the control line inputs. In order to perform other device functions, a series of
command sequences are entered into the device. The command sequences are shown in the
“Command Definition Table” on page 14 (I/O8 - I/O15 are don’t care inputs for the command
codes). The command sequences are written by applying a low pulse on the WE or CE input
with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE
or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Standard
microprocessor write timings are used. The address locations used in the command sequences
are not affected by entering the command sequences.
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9.3
Reset
A RESET input pin is provided to ease some system applications. When RESET is at a logic
high level, the device is in its standard operating mode. A low level on the RESET input halts the
present device operation and puts the outputs of the device in a high impedance state. When a
high level is reasserted on the RESET pin, the device returns to the read or standby mode,
depending upon the state of the control inputs.
9.4
Erasure
Before a word can be reprogrammed, it must be erased. The erased state of memory bits is a
logical “1”. The entire device can be erased by using the Chip Erase command or individual sec-
tors can be erased by using the Sector Erase command.
9.4.1
Chip Erase
The entire device can be erased at one time by using the six-byte chip erase software code.
After the chip erase has been initiated, the device will internally time the erase operation so that
no external clocks are required. The maximum time to erase the chip is tEC
.
If the sector lockdown has been enabled, the chip erase will not erase the data in the sector that
has been locked out; it will erase only the unprotected sectors. After the chip erase, the device
will return to the read or standby mode.
9.4.2
Sector Erase
As an alternative to a full chip erase, the device is organized into 39 sectors (SA0 - SA38) that
can be individually erased. The Sector Erase command is a six-bus cycle operation. The sector
address is latched on the falling WE edge of the sixth cycle while the 30H data input command is
latched on the rising edge of WE. The sector erase starts after the rising edge of WE of the sixth
cycle. The erase operation is internally controlled; it will automatically time to completion. The
maximum time to erase a sector is tSEC. When the sector programming lockdown feature is not
enabled, the sector will erase (from the same Sector Erase command). An attempt to erase a
sector that has been protected will result in the operation terminating immediately.
9.5
Word Programming
Once a memory block is erased, it is programmed (to a logical “0”) on a word-by-word basis.
Programming is accomplished via the internal device command register and is a four-bus cycle
operation. The device will automatically generate the required internal program pulses.
Any commands written to the chip during the embedded programming cycle will be ignored. If a
hardware reset happens during programming, the data at the location being programmed will be
corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase opera-
tions can convert “0”s to “1”s. Programming is completed after the specified tBP cycle time. The
Data Polling feature or the Toggle Bit feature may be used to indicate the end of a program
cycle. If the erase/program status bit is a “1”, the device was not able to verify that the erase or
program operation was performed successfully.
9.6
VPPPin
The circuitry of the device is designed so that it cannot be programmed or erased if the VPP volt-
age is less that 0.4V. When VPP is at 0.9V or above, normal program and erase operations can
be performed. The VPP pin cannot be left floating.
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AT52BR1664A(T)
9.7
Program/Erase Status
The device provides several bits to determine the status of a program or erase operation: I/O2,
I/O3, I/O5, I/O6 and I/O7. The “Status Bit Table” on page 13 and the following four sections
describe the function of these bits. To provide greater flexibility for system designers, the Flash
contains a programmable configuration register. The configuration register allows the user to
specify the status bit operation. The configuration register can be set to one of two different val-
ues, “00” or “01”. If the configuration register is set to “00”, the part will automatically return to the
read mode after a successful program or erase operation. If the configuration register is set to a
“01”, a Product ID Exit command must be given after a successful program or erase operation
before the part will return to the read mode. It is important to note that whether the configuration
register is set to a “00” or to a “01”, any unsuccessful program or erase operation requires using
the Product ID Exit command to return the device to read mode. The default value (after power-
up) for the configuration register is “00”. Using the four-bus cycle Set Configuration Register
command as shown in the “Command Definition Table” on page 14, the value of the configura-
tion register can be changed. Voltages applied to the RESET pin will not alter the value of the
configuration register. The value of the configuration register will affect the operation of the I/O7
status bit as described below.
9.8
Data Polling
The 16-Mbit Flash features Data Polling to indicate the end of a program cycle. If the status con-
figuration register is set to a “00”, during a program cycle an attempted read of the last word
loaded will result in the complement of the loaded data on I/O7. Once the program cycle has
been completed, true data is valid on all outputs and the next cycle may begin. During a chip or
sector erase operation, an attempt to read the device will give a “0” on I/O7. Once the program
or erase cycle has completed, true data will be read from the device. Data Polling may begin at
any time during the program cycle. Please see “Status Bit Table” on page 13 for more details.
If the status bit configuration register is set to a “01”, the I/O7 status bit will be low while the
device is actively programming or erasing data. I/O7 will go high when the device has completed
a program or erase operation. Once I/O7 has gone high, status information on the other pins can
be checked.
The Data Polling status bit must be used in conjunction with the erase/program and VPP status
bit as shown in the algorithm in Figures 9-1 and 9-2 on page 11.
9.9
Toggle Bit
In addition to Data Polling, the device provides another method for determining the end of a pro-
gram or erase cycle. During a program or erase operation, successive attempts to read data
from the memory will result in I/O6 toggling between one and zero. Once the program cycle has
completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin
at any time during a program cycle. Please see “Status Bit Table” on page 13 for more details.
The toggle bit status bit should be used in conjunction with the erase/program and VPP status bit
as shown in the algorithm in Figures 9-3 and 12 on page 12.
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9.10 Erase/Program Status Bit
The device offers a status bit on I/O5, which indicates whether the program or erase operation
has exceeded a specified internal pulse count limit. If the status bit is a “1”, the device is unable
to verify that an erase or a word program operation has been successfully performed. If a pro-
gram (Sector Erase) command is issued to a protected sector, the protected sector will not be
programmed (erased). The device will go to a status read mode and the I/O5 status bit will be
set high, indicating the program (erase) operation did not complete as requested. Once the
erase/program status bit has been set to a “1”, the system must write the Product ID Exit com-
mand to return to the read mode. The erase/program status bit is a “0” while the erase or
program operation is still in progress. Please see “Status Bit Table” on page 13 for more details.
9.10.1
VPP Status Bit
The device provides a status bit on I/O3, which provides information regarding the voltage level
of the VPP pin. During a program or erase operation, if the voltage on the VPP pin is not high
enough to perform the desired operation successfully, the I/O3 status bit will be a “1”. Once the
V
PP status bit has been set to a “1”, the system must write the Product ID Exit command to return
to the read mode. On the other hand, if the voltage level is high enough to perform a program or
erase operation successfully, the VPP status bit will output a “0”. Please see “Status Bit Table” on
page 13 for more details.
9.11 Sector Lockdown
Each sector has a programming lockdown feature. This feature prevents programming of data in
the designated sectors once the feature has been enabled. These sectors can contain secure
code that is used to bring up the system. Enabling the lockdown feature will allow the boot code
to stay in the device while data in the rest of the device is updated. This feature does not have to
be activated; any sector’s usage as a write-protected region is optional to the user.
At power-up or reset, all sectors are unlocked. To activate the lockdown for a specific sector, the
six-bus cycle Sector Lockdown command must be issued. Once a sector has been locked down,
the contents of the sector is read-only and cannot be erased or programmed.
9.11.1
Sector Lockdown Detection
A software method is available to determine if programming of a sector is locked down. When
the device is in the software product identification mode (see “Software Product Identification
Entry/Exit” sections on page 25), a read from address location 00002H within a sector will show
if programming the sector is locked down. If the data on I/O0 is low, the sector can be pro-
grammed; if the data on I/O0 is high, the program lockdown feature has been enabled and the
sector cannot be programmed. The software product identification exit code should be used to
return to standard operation.
9.11.2
Sector Lockdown Override
The only way to unlock a sector that is locked down is through reset or power-up cycles. After
power-up or reset, the content of a sector that is locked down can be erased and reprogrammed.
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AT52BR1664A(T)
9.12 Erase Suspend/Erase Resume
The Erase Suspend command allows the system to interrupt a sector or chip erase operation
and then program or read data from a different sector within the memory. After the Erase Sus-
pend command is given, the device requires a maximum time of 15 µs to suspend the erase
operation. After the erase operation has been suspended, the system can then read data or pro-
gram data to any other sector within the device. An address is not required during the Erase
Suspend command. During a sector erase suspend, another sector cannot be erased. To
resume the sector erase operation, the system must write the Erase Resume command. The
Erase Resume command is a one-bus cycle command. The device also supports an erase sus-
pend during a complete chip erase. While the chip erase is suspended, the user can read from
any sector within the memory that is protected. The command sequence for a chip erase sus-
pend and a sector erase suspend are the same.
9.13 Program Suspend/Program Resume
The Program Suspend command allows the system to interrupt a programming operation and
then read data from a different word within the memory. After the Program Suspend command is
given, the device requires a maximum of 20 µs to suspend the programming operation. After the
programming operation has been suspended, the system can then read data from any other
word that is not contained in the sector in which the programming operation was suspended. An
address is not required during the program suspend operation. To resume the programming
operation, the system must write the Program Resume command. The program suspend and
resume are one-bus cycle commands. The command sequence for the erase suspend and pro-
gram suspend are the same, and the command sequence for the erase resume and program
resume are the same.
9.14 Product Identification
The product identification mode identifies the device and manufacturer as Atmel. It may be
accessed by hardware or software operation. The hardware operation mode can be used by an
external programmer to identify the correct programming algorithm for the Atmel product.
For details, see “Operating Modes” on page 18 (for hardware operation) or “Software Product
Identification Entry/Exit” sections on page 25. The manufacturer and device codes are the same
for both modes.
9.15 128-bit Protection Register
The device contains a 128-bit register that can be used for security purposes in system design.
The protection register is divided into two 64-bit blocks. The two blocks are designated as block
A and block B. The data in block A is non-changeable and is programmed at the factory with a
unique number. The data in block B is programmed by the user and can be locked out such that
data in the block cannot be reprogrammed. To program block B in the protection register, the
four-bus cycle Program Protection Register command must be used as shown in the “Command
Definition Table” on page 14. To lock out block B, the four-bus cycle Lock Protection Register
command must be used as shown in the “Command Definition Table” on page 14. Data bit D1
must be zero during the fourth bus cycle. All other data bits during the fourth bus cycle are don’t
cares. To determine whether block B is locked out, the Product ID Entry command is given fol-
lowed by a read operation from address 80H. If data bit D1 is zero, block B is locked. If data bit
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D1 is one, block B can be reprogrammed. Please see the “Protection Register Addressing
Table” on page 15 for the address locations in the protection register. To read the protection reg-
ister, the Product ID Entry command is given followed by a normal read operation from an
address within the protection register. After determining whether block B is protected or not, or
reading the protection register, the Product ID Exit command must be given prior to performing
any other operation.
9.16 RDY/BUSY
For the 16-Mbit Flash, an open-drain READY/BUSY output pin provides another method of
detecting the end of a program or erase operation. RDY/BUSY is actively pulled low during the
internal program and erase cycles and is released at the completion of the cycle. The open-drain
connection allows for OR-tying of several devices to the same RDY/BUSY line. Please see “Sta-
tus Bit Table” on page 13 for more details.
9.17 Hardware Data Protection
The Hardware Data Protection feature protects against inadvertent programs to the device in the
following ways: (a) VCC sense: if VCC is below 1.8V (typical), the program function is inhibited. (b)
VCC power-on delay: once VCC has reached the VCC sense level, the device will automatically
time out 10 ms (typical) before programming. (c) Program inhibit: holding any one of OE low, CE
high or WE high inhibits program cycles. (d) Program inhibit: VPP is less than VILPP. (e) VPP
power-on delay: once VPP has reached 1.65V, program and erase operations are inhibited for
100 ns.
9.18 Input Levels
While operating with a 2.7V to 3.3V power supply, the address inputs and control inputs (OE, CE
and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device.
The I/O lines can only be driven from 0 to VCC + 0.6V.
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AT52BR1664A(T)
Figure 9-1. Data Polling Algorithm
Figure 9-2. Data Polling Algorithm
(Configuration Register = 00)
(Configuration Register = 01)
START
START
Read I/O7 - I/O0
Read I/O7 - I/O0
Read I/O7 - I/O0
Addr = VA
YES
I/O7 = Data?
NO
Toggle Bit =
Toggle?
NO
YES
NO
I/O3, I/O5 = 1?
NO
I/O3, I/O5 = 1?
YES
YES
Read I/O7 - I/O0
Addr = VA
Read I/O7 - I/O0
Twice
YES
I/O7 = Data?
Toggle Bit =
Toggle?
NO
NO
YES
Program/Erase
Operation Not
Successful, Write
Product ID
Program/Erase
Program/Erase
Operation
Successful,
Write Product
ID Exit Command
Program/Erase
Operation Not
Successful, Write
Product ID
Operation
Successful,
Device in
Exit Command
Read Mode
Exit Command
Note:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector
address within the sector being erased. During chip
erase, a valid address is any non-protected sector
address.
Notes: 1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector
address within the sector being erased. During chip
erase, a valid address is any non-protected sector
address.
2. I/O7 should be rechecked even if I/O5 = “1” because
I/O7 may change simultaneously with I/O5.
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Figure 9-3. Toggle Bit Algorithm
(Configuration Register = 00)
Figure 9-4. Toggle Bit Algorithm
(Configuration Register = 01)
START
START
Read I/O7 - I/O0
Read I/O7 - I/O0
Read I/O7 - I/O0
Read I/O7 - I/O0
NO
NO
Toggle Bit =
Toggle?
Toggle Bit =
Toggle?
YES
YES
NO
NO
I/O3, I/O5 = 1?
I/O3, I/O5 = 1?
YES
YES
Read I/O7 - I/O0
Twice
Read I/O7 - I/O0
Twice
Toggle Bit =
Toggle?
NO
Toggle Bit =
Toggle?
NO
YES
YES
Program/Erase
Operation Not
Successful, Write
Product ID
Program/Erase
Program/Erase
Operation Not
Successful, Write
Product ID
Program/Erase
Operation
Successful,
Write Product ID
Exit Command
Operation
Successful,
Device in
Exit Command
Read Mode
Exit Command
Note:
1. The system should recheck the toggle bit even if
I/O5 = “1” because the toggle bit may stop toggling
as I/O5 changes to “1”.
Note:
1. The system should recheck the toggle bit even if
I/O5 = “1” because the toggle bit may stop toggling
as I/O5 changes to “1”.
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10. Status Bit Table
Status Bit
I/O7
00
I/O7
01
0
I/O6
I/O5(1)
I/O3(2)
I/O2
00/01
1
RDY/BUSY
Configuration Register
Programming
00/01
00/01
00/01
00/01
I/O7
0
TOGGLE
TOGGLE
0
0
0
0
0
0
Erasing
0
TOGGLE
Erase Suspended & Read
Erasing Sector
1
1
DATA
0
1
0
DATA
0
0
DATA
0
TOGGLE
DATA
1
1
0
Erase Suspended & Read
Non-erasing Sector
DATA
I/O7
DATA
Erase Suspended &
Program Non-erasing Sector
TOGGLE
TOGGLE
Erase Suspended &
Program Suspended and
Reading from Non-
suspended Sectors
DATA
DATA
DATA
DATA
DATA
DATA
1
Program Suspended &
Read Programming Sector
I/O7
1
1
0
0
TOGGLE
DATA
1
1
Program Suspended &
Read Non-programming
Sector
DATA
DATA
DATA
DATA
DATA
Notes: 1. I/O5 switches to a “1” when a program or an erase operation has exceeded the maximum time limits or when a program or
sector erase operation is performed on a protected sector.
2. I/O3 switches to a “1” when the VPP level is not high enough to successfully perform program and erase operations.
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11. Command Definition Table
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Command
Sequence
Bus
Cycles
Addr
Addr
555
Data
DOUT
AA
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Read
1
6
6
4
Chip Erase
Sector Erase
Word Program
AAA(2)
AAA
55
55
55
555
555
555
80
80
A0
555
555
AA
AA
DIN
AAA
AAA
55
55
555
10
30
555
AA
SA(3)(4)
555
AA
AAA
Addr
Dual Word
Program(9)
5
6
555
555
AA
AA
AAA
AAA
55
55
555
555
E0
80
Addr1
555
DIN1
AA
Addr2
AAA
DIN2
55
Enter Single Pulse
Program Mode
555
A0
60
Single Pulse Word
Program
1
6
1
Addr
555
DIN
AA
B0
Sector Lockdown
AAA(2)
55
555
80
555
AA
AAA
55
SA(3)(4)
Erase/Program
Suspend
XXX
Erase/Program
Resume
1
XXX
30
Product ID Entry
Product ID Exit(5)
Product ID Exit(5)
3
3
1
555
555
AA
AA
AAA
AAA
55
55
555
555
90
F0(8)
XXX
F0(8)
Program Protection
Register
4
4
4
555
555
555
AA
AA
AA
AAA
AAA
AAA
AAA
55
55
55
55
555
555
555
555
C0
C0
90
Addr
080
80
DIN
X0
Lock Protection
Register - Block B
Status of Block B
Protection
(6)
DOUT
Set Configuration
Register
4
1
555
X55
AA
98
D0
XXX
00/01(7)
CFI Query
Notes: 1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). I/O15 - I/O8 are don’t care. The ADDRESS
FORMAT shown for each bus cycle is as follows: A11 - A0 (Hex). Address A19 through A11 are don’t care.
2. Since A11 is a Don’t Care, AAA can be replaced with 2AA.
3. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages 16 - 17 for
details).
4. Once a sector is in the lockdown mode, data in the protected sector cannot be changed unless the chip is reset or power
cycled.
5. Either one of the Product ID Exit commands can be used.
6. If data bit D1 is “0”, block B is locked. If data bit D1 is “1”, block B can be reprogrammed.
7. The default state (after power-up) of the configuration register is “00”.
8. Bytes of data other than F0 may be used to exit the Product ID mode. However, it is recommended that F0 be used.
9. This fast programming option enables the user to program two words in parallel only when VPP = 12V. The Addresses, Addr1
and Addr2, of the two words, DIN1 and DIN2, must only differ in address A0. This command should be used during manufac-
turing purposes only.
14
AT52BR1664A(T)
3361D–STKD–1/07
AT52BR1664A(T)
12. Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Temperature under Bias ................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground.............................-0.6V to VCC + 0.6V
Voltage on VPP
with Respect to Ground...................................-0.6V to +13.0V
13. Protection Register Addressing Table
Word
Use
Factory
Factory
Factory
Factory
User
Block
A7
A6
A5
0
A4
0
A3
0
A2
0
A1
0
A0
1
0
1
2
3
4
5
6
7
A
A
A
A
B
B
B
B
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
1
0
0
0
0
1
0
1
User
1
0
0
0
0
1
1
0
User
1
0
0
0
0
1
1
1
User
1
0
0
0
1
0
0
0
Note:
All address lines not specified in the above table must be “0” when accessing the protection register, i.e., A19 - A8 = 0.
15
3361D–STKD–1/07
14. AT52BR1664A – Sector Address Table
x16
Sector
SA0
Size (Words)
4K
Address Range (A19 - A0)
00000 - 00FFF
01000 - 01FFF
02000 - 02FFF
03000 - 03FFF
04000 - 04FFF
05000 - 05FFF
06000 - 06FFF
07000 - 07FFF
08000 - 0FFFF
10000 - 17FFF
18000 - 1FFFF
20000 - 27FFF
28000 - 2FFFF
30000 - 37FFF
38000 - 3FFFF
40000 - 47FFF
48000 - 4FFFF
50000 - 57FFF
58000 - 5FFFF
60000 - 67FFF
68000 - 6FFFF
70000 - 77FFF
78000 - 7FFFF
80000 - 87FFF
88000 - 8FFFF
90000 - 97FFF
98000 - 9FFFF
A0000 - A7FFF
A8000 - AFFFF
B0000 - B7FFF
B8000 - BFFFF
C0000 - C7FFF
C8000 - CFFFF
D0000 - D7FFF
D8000 - DFFFF
E0000 - E7FFF
E8000 - EFFFF
F0000 - F7FFF
F8000 - FFFFF
SA1
4K
SA2
4K
SA3
4K
SA4
4K
SA5
4K
SA6
4K
SA7
4K
SA8
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
16
AT52BR1664A(T)
3361D–STKD–1/07
AT52BR1664A(T)
15. AT52BR1664AT – Sector Address Table
x16
Sector
SA0
Size (Words)
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
32K
4K
Address Range (A19 - A0)
00000 - 07FFF
08000 - 0FFFF
10000 - 17FFF
18000 - 1FFFF
20000 - 27FFF
28000 - 2FFFF
30000 - 37FFF
38000 - 3FFFF
40000 - 47FFF
48000 - 4FFFF
50000 - 57FFF
58000 - 5FFFF
60000 - 67FFF
68000 - 6FFFF
70000 - 77FFF
78000 - 7FFFF
80000 - 87FFF
88000 - 8FFFF
90000 - 97FFF
98000 - 9FFFF
A0000 - A7FFF
A8000 - AFFFF
B0000 - B7FFF
B8000 - BFFFF
C0000 - C7FFF
C8000 - CFFFF
D0000 - D7FFF
D8000 - DFFFF
E0000 - E7FFF
E8000 - EFFFF
F0000 - F7FFF
F8000 - F8FFF
F9000 - F9FFF
FA000 - FAFFF
FB000 - FBFFF
FC000 - FCFFF
FD000 - FDFFF
FE000 - FEFFF
FF000 - FFFFF
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
4K
4K
4K
4K
4K
4K
4K
17
3361D–STKD–1/07
16. DC and AC Operating Range
16-Mbit Flash-70
-40°C - 85°C
16-Mbit Flash-90
-40°C - 85°C
Operating Temperature (Case)
CC Power Supply
Ind.
V
2.70V to 3.3V
2.70V to 3.3V
17. Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
VIL
VIH
X(1)
X
WE
VIH
VIL
X
RESET
VIH
VPP
Ai
Ai
Ai
X
I/O
Read
X
DOUT
DIN
Program/Erase(2)
Standby/Program Inhibit
VIH
VIHPP
(6)
VIH
X
X
X
High-Z
VIH
X
VIH
Program Inhibit
X
VIL
X
VIH
(7)
X
X
VIH
VILPP
X
Output Disable
Reset
X
VIH
X
X
VIH
High-Z
High-Z
X
X
VIL
X
X
Product Identification
A1 - A19 = VIL, A9 = VH(3), A0 = VIL
A1 - A19 = VIL, A9 = VH(3), A0 = VIH
A0 = VIL, A1 - A19 = VIL
Manufacturer Code(4)
Device Code(4)
Hardware
VIL
VIL
VIH
VIH
VIH
Manufacturer Code(4)
Device Code(4)
Software(5)
A0 = VIH, A1 - A19 = VIL
Notes: 1. X can be VIL or VIH.
2. Refer to AC programming waveforms on page 23.
3. VH = 12.0V 0.5V.
4. Manufacturer Code: 001FH, Device Code: 00C0H – Bottom Boot, 00C2H, Top Boot.
5. See details under “Software Product Identification Entry/Exit” on page 25.
6. VIHPP (min) = 0.9V; VIHPP (max) = 3.6V.
7. VILPP (max) = 0.4V.
18
AT52BR1664A(T)
3361D–STKD–1/07
AT52BR1664A(T)
18. DC Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
2
Units
µA
µA
µA
mA
mA
µA
V
ILI
Input Load Current
VIN = 0V to VCC
ILO
Output Leakage Current
VCC Standby Current CMOS
VCC Active Read Current
VCC Programming Current
VPP Input Load Current
Input Low Voltage
VI/O = 0V to VCC
10
25
25
40
5
ISB
CE = VCC - 0.3V to VCC
f = 5 MHz; IOUT = 0 mA
13
12
(1)
ICC
ICC1
IPP1
VIL
0.6
VIH
Input High Voltage
2.0
V
VOL1
VOL2
VOH1
VOH2
Output Low Voltage
Output Low Voltage
Output High Voltage
IOL = 2.1 mA
IOL = 1.0 mA
IOH = -400 µA
IOH = -100 µA
0.45
0.20
V
V
2.4
2.5
V
Output High Voltage
V
Note:
1. In the erase mode, ICC is 45 mA.
19
3361D–STKD–1/07
19. AC Read Characteristics
16-Mbit Flash-70
16-Mbit Flash-90
Symbol
tRC
Parameter
Min
Max
Min
Max
Units
ns
Read Cycle Time
70
70
70
20
25
90
90
90
20
25
tACC
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
ns
(1)
tCE
ns
(2)
tOE
0
0
0
0
ns
(3)(4)
tDF
ns
Output Hold from OE, CE or Address,
whichever occurred first
tOH
tRO
0
0
ns
ns
RESET to Output Delay
100
100
(1)(2)(3)(4)
20. AC Read Waveforms
tRC
ADDRESS
ADDRESS VALID
CE
OE
tCE
tOE
tDF
tOH
tACC
tRO
RESET
HIGH Z
OUTPUT
VALID
OUTPUT
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
20
AT52BR1664A(T)
3361D–STKD–1/07
AT52BR1664A(T)
21. Input Test Waveforms and Measurement Level
tR, tF < 5 ns
22. Output Test Load
2.8V = V
TM
1029 Ohm
CL(1)
1728 Ohm
23. Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
CIN
Typ
4
Max
6
Units
pF
Conditions
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
This parameter is characterized and is not 100% tested.
21
3361D–STKD–1/07
24. AC Word Load Characteristics
Symbol
tAS, tOES
tAH
Parameter
Min
0
Max
Units
ns
Address, OE Setup Time
Address Hold Time
35
0
ns
tCS
Chip Select Setup Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Setup Time
ns
tCH
0
ns
tWP
35
35
0
ns
tDS
ns
t
DH, tOEH
Data, OE Hold Time
Write Pulse Width High
ns
tWPH
35
ns
25. AC Word Load Waveforms
25.1 WE Controlled
25.2 CE Controlled
22
AT52BR1664A(T)
3361D–STKD–1/07
AT52BR1664A(T)
26. Program Cycle Characteristics
Symbol
Parameter
Min
Typ
12
6
Max
200
100
Units
tBP
Word Programming Time
Word Programming Time in Dual Programming Mode
Address Setup Time
µs
µs
tBPD
tAS
0
35
35
0
ns
tAH
Address Hold Time
ns
tDS
Data Setup Time
ns
tDH
Data Hold Time
ns
tWP
Write Pulse Width
35
35
70
500
ns
tWPH
tWC
Write Pulse Width High
Write Cycle Time
ns
ns
tRP
Reset Pulse Width
ns
tEC
Chip Erase Cycle Time
Sector Erase Cycle Time (4K Word Sectors)
Sector Erase Cycle Time (32K Word Sectors)
Erase Suspend Time
25
seconds
seconds
seconds
µs
tSEC1
tSEC2
tES
3.0
5.0
15
tPS
Program Suspend Time
10
µs
27. Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
t
t
BP
t
WP
WPH
WE
t
t
t
DH
AS
AH
555
AAA
555
ADDRESS
555
A0 - A19
DATA
t
WC
t
DS
INPUT
DATA
AA
55
A0
AA
28. Sector or Chip Erase Cycle Waveforms
(1)
OE
CE
t
t
WP
WPH
WE
A0-A19
DATA
t
t
t
DH
AS
AH
555
t
AAA
555
555
AAA
Note
2
WC
t
t
EC
DS
AA
WORD
55
WORD
80
WORD
AA
WORD
55
WORD
Note 3
0
1
2
3
4
WORD 5
Notes: 1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased.
(See note 3 under “Command Definitions in Hex” on page 14.)
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
23
3361D–STKD–1/07
29. Data Polling Characteristics
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
OE Hold Time
10
ns
OE to Output Delay(2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 20.
30. Data Polling Waveforms
WE
CE
tOEH
OE
tDH
tWR
tOE
HIGH Z
I/O7
An
An
An
An
An
A0-A19
31. Toggle Bit Characteristics
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
tOEHP
tWR
OE Hold Time
10
ns
OE to Output Delay(2)
OE High Pulse
ns
50
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 20.
32. Toggle Bit Waveforms(1)(2)(3)
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
24
AT52BR1664A(T)
3361D–STKD–1/07
AT52BR1664A(T)
33. Software Product Identification
Entry(1)
35. Sector Lockdown Enable
Algorithm(1)
LOAD DATA AA
TO
LOAD DATA AA
TO
ADDRESS 555
ADDRESS 555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS AAA
ADDRESS AAA
LOAD DATA 80
TO
LOAD DATA 90
TO
ADDRESS 555
ADDRESS 555
LOAD DATA AA
TO
ENTER PRODUCT
IDENTIFICATION
ADDRESS 555
(2)(3)(5)
MODE
LOAD DATA 55
TO
34. Software Product Identification
ADDRESS AAA
Exit(1)(6)
OR
LOAD DATA AA
LOAD DATA F0
TO
TO
LOAD DATA 60
TO
ADDRESS 555
ANY ADDRESS
SECTOR ADDRESS
EXIT PRODUCT
IDENTIFICATION
LOAD DATA 55
TO
(4)
MODE
ADDRESS AAA
(2)
PAUSE 200 µs
LOAD DATA F0
TO
Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
Address Format: A11 - A0 (Hex), and A11 - A19 (Don’t
Care).
ADDRESS 555
2. Sector Lockdown feature enabled.
EXIT PRODUCT
IDENTIFICATION
(4)
MODE
Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
Address Format: A11 - A0 (Hex), and A11 - A19 (Don’t
Care).
2. A1 - A19 = VIL. Manufacturer Code is read for A0 = VIL;
Device Code is read for A0 = VIH
.
3. The device does not remain in identification mode if pow-
ered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 001FH(x16)
Device Code:00C0H (x16) - Bottom Boot;
00C2H (x16) - Top Boot.
6. Either one of the Product ID Exit commands can be used.
25
3361D–STKD–1/07
36. 4-megabit SRAM Description
The 4-megabit SRAM is a high-speed, super low-power CMOS SRAM organized as 256K words
by 16 bits. The SRAM uses high-performance full CMOS process technology and is designed for
high-speed and low-power circuit technology. It is particularly well-suited for the high-density
low-power system application. This device has a data retention mode that guarantees data to
remain valid at a minimum power supply voltage of 1.2V.
37. Features
•
•
•
Fully Static Operation and Tri-state Output
TTL Compatible Inputs and Outputs
Battery Backup
– 1.2V (Min) Data Retention
Operation
Current/ICC (mA)
(Max)
Standby Current
(µA)
Temperature
Voltage (V)
Speed (ns)
(Max)
(°C)
2.7 - 3.3
70
3
10
-40 - 85
38. Block Diagram
ROW DECODER
A0
I/O0
I/O7
I/O8
MEMORY ARRAY
256K X 16
I/O15
A17
SCS1
SCS2
SOE
SLB
SUB
SWE
26
AT52BR1664A(T)
3361D–STKD–1/07
AT52BR1664A(T)
39. Absolute Maximum Ratings
Symbol
VIN, VOUT
VCC
Parameter
Rating
-0.3 to 3.6
-0.3 to 3.6
-40 to 85
-55 to 150
1.0
Unit
V
Input/Output Voltage
Power Supply
V
TA
Operating Temperature
Storage Temperature
Power Dissipation
°C
°C
W
TSTG
PD
Note:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is
stress rating only and the functional operation of the device under these or any other conditions above those indicated in the
operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may
affect reliability.
40. Truth Table
I/O Pin
I/O8 - I/O15
SCS1
H(1)
X(1)
X
SCS2
SWE
SOE
SLB(2)
SUB(2)
Mode
I/O0 - I/O7
Power
X
L
X
X
X
X
Deselected
High-Z
High-Z
High-Z
Standby
X
H
L
H
H
L
L(1)
H
H
H
L
H
X
H
L
Output Disabled
High-Z
Active
Active
L
L
H
L
DIN
High-Z
DIN
High-Z
DIN
H
L
Write
DIN
L
L
DIN
High-Z
High-Z
DOUT
DOUT
High-Z
L
H
L
DOUT
High-Z
DOUT
DOUT
H
L
H
H
L
Read
Active
L
L
Notes: 1. H = VIH, L = VIL, X = Don't Care (VIL or VIH)
2. SUB, SLB (Upper, Lower Byte Enable). These active LOW inputs allow individual bytes to be written or read. When SLB is
LOW, data is written or read to the lower byte, I/O0 - I/O7. When SUB is LOW, data is written or read to the upper byte, I/O8 -
I/O15.
41. Recommended DC Operating Condition
Symbol
Parameter
Min
Typ
3.0
0
Max
3.3
Unit
V
VCC
Supply Voltage
Ground
2.7
VSS
0
0
V
VIH
Input High Voltage
Input Low Voltage
2.2
VCC + 0.3
0.6
V
VIL
-0.3(1)
V
(1)
Note:
1. Undershoot: VIL = -1.5V for pulse width less than 30 ns. Undershoot is sampled, not 100% tested.
27
3361D–STKD–1/07
42. DC Electrical Characteristics
TA = -40° C to 85°C
Symbol
Parameter
Test Condition
Min
Max
Unit
ILI
Input Leakage Current
VSS < VIN < VCC
-1
1
µA
VSS < VOUT < VCC
,
SCS1 = VIH or SCS2=VIL or
SOE = VIH or SWE = VIL or
SUB = VIH, SLB = VIH
ILO
Output Leakage Current
-1
1
µA
SCS1 = VIL, SCS2=VIH,
VIN = VIH or VIL, II/O = 0 mA
ICC
Operating Power Supply Current
3
mA
mA
SCS1 = VIL, SCS2 = VIH,
VIN = VIH or VIL, Cycle Time = Min
100% Duty, II/O = 0 mA
15
ICC1
Average Operating Current
SCS1 < 0.2V, SCS2 > VCC - 0.2V
VIN < 0.2V or VIN > VCC - 0.2V,
Cycle Time = 1 µs
2
mA
mA
100% Duty, II/O = 0 mA
SCS1 = VIH or SCS2 = VIL or
SUB, SLB = VIH
VIN = VIH or VIL
ISB
Standby Current (TTL Input)
Standby Current (CMOS Input)
0.3
SCS1 > VCC - 0.2V or
SCS2 < VSS + 0.2V or
SUB, SLB > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < VSS + 0.2V
ISB1
LL
10
µA
VOL
VOH
Output Low
Output High
IOL = 2.1 mA
IOH = -1.0 mA
0.4
V
V
2.4
43. Capacitance(1)
(Temp = 25° C, f = 1.0 MHz)
Symbol
Parameter
Condition
VIN = 0 V
VI/O = 0 V
Max
Unit
pF
Input Capacitance (Add, SCS1,
SCS2, SLB, SUB, SWE, SOE)
CIN
8
COUT
Output Capacitance (I/O)
10
pF
Note:
1. These parameters are sampled and not 100% tested.
28
AT52BR1664A(T)
3361D–STKD–1/07
AT52BR1664A(T)
44. AC Characteristics
TA = -40° C to 85°C, Unless Otherwise Specified
70 ns
#
1
Symbol
tRC
Parameter
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
70
2
tAA
Address Access Time
70
70
35
70
3
tACS
tOE
Chip Select Access Time
Output Enable to Output Valid
SLB, SUB Access Time
4
5
tBA
6
tCLZ
tOLZ
tBLZ
tCHZ
tOHZ
tBHZ
tOH
Chip Select to Output in Low Z
Output Enable to Output in Low Z
SLB, SUB Enable to Output in Low Z
Chip Deselection to Output in High Z
Out Disable to Output in High Z
SLB, SUB Disable to Output in High Z
Output Hold from Address Change
Write Cycle Time
10
5
7
8
10
0
9
25
25
25
10
11
12
13
14
15
16
17
18
19
20
21
22
23
0
0
10
30
30
30
30
0
tWC
tCW
tAW
Chip Selection to End of Write
Address Valid to End of Write
SLB, SUB Valid to End of Write
Address Setup Time
tBW
tAS
tWP
Write Pulse Width
30
0
tWR
tWHZ
tDW
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
0
5
25
0
tDH
tOW
5
45. AC Test Conditions
TA = -40° C to 85°C, Unless Otherwise Specified
Parameter
Value
Input Pulse Level
0.4V to 2.2V
Input Rise and Fall Time
5 ns
Input and Output Timing Reference Level
1.5V
t
CLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ, tWHZ, tOW
CL = 5 pF + 1 TTL Load
CL = 30 pF + 1 TTL Load
Output Load
Others
29
3361D–STKD–1/07
46. Output Test Load
2.8V = V
TM
1029 Ohm
CL(1)
1728 Ohm
Note:
1. Including jig and scope capacitance.
47. Timing Diagrams
47.1 Read Cycle 1(1),(4)
tRC
ADDRESS
SCS1
tAA
tOH
tACS
SCS2
SUB, SLB
SOE
(3)
tCHZ
tBA
(3)
tBHZ
tOE
(3)
tOLZ
(3)
tOHZ
(3)
tBLZ
(3)
tCLZ
HIGH-Z
DATA OUT
DATA VALID
48. Read Cycle 2(1) (2) (4)
,
,
tRC
ADDRESS
DATA OUT
tAA
tOH
tOH
PREVIOUS DATA
DATA VALID
49. Read Cycle 3(1) (2) (4)
,
,
SCS1
SUB, SLB
SCS2
tACS
(3)
tCHZ
(3)
tCLZ
DATA OUT
DATA VALID
Notes: 1. Read Cycle occurs whenever a high on the SWE and SOE is low, while SUB and/or SLB and SCS1 and SCS2 are in active
status.
2. SOE = VIL.
3. Transition is measured 200 mV from steady state voltage. This parameter is sampled and not 100% tested.
4. SCS1 in high for the standby, low for active. SCS2 in low for the standby, high for active. SUB and SLB in high for the
standby, low for active.
30
AT52BR1664A(T)
3361D–STKD–1/07
AT52BR1664A(T)
49.1 Write Cycle 1 (SWE Controlled)(1),(4),(8)
tWC
ADDRESS
SCS1
(2)
tWR
tCW
SCS2
tAW
tBW
SUB, SLB
tWP
SWE
tAS
tDW
tDH
tAS
HIGH-Z
DATA IN
DATA VALID
(3)(7)
tOW
tWHZ
(5)
(5)
DATA OUT
49.2 Write Cycle 2 (SCS1, SCS2 Controlled)(1),(4),(8)
tWC
ADDRESS
(2)
tCW
tWR
tAS
SCS1
SCS2
tAW
tBW
SUB, SLB
tWP
SWE
tDW
tDH
HIGH-Z
DATA IN
DATA VALID
HIGH-Z
DATA OUT
Notes: 1. A write occurs during the overlap of a low SWE, a low SCS1, a high SCS2 and a low SUB and/or SLB.
2. tWR is measured from the earlier of SCS1, SLB, SUB, or SWE going high or SCS2 going low to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be
applied.
4. If the SCS1, SLB and SUB low transition and SCS2 high transition occur simultaneously with the SWE low transition or after
the SWE transition, outputs remain in a high impedance state.
5. Q (data out) is the same phase with the write data of this write cycle.
6. Q (data out) is the read data of the next address.
7. Transition is measured 200 mV from steady state. This parameter is sampled and not 100% tested.
8. SCS1 in high for the standby, low for active SCS2 in low for the standby, high for active. SUB and SLB in high for the standby,
low for active.
31
3361D–STKD–1/07
50. Data Retention Electric Characteristic
TA = -40° C to 85°C
Symbol
Parameter
Test Condition
Min
Typ(1)
Max
Unit
SCS1 > VCC - 0.2V or
SCS2 < VSS + 0.2V or
SUB, SLB > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < VSS + 0.2V
VDR
VCC for Data Retention
1.2
3.3
V
Vcc=1.5V,
SCS1 > VCC - 0.2V or
SCS2 < VSS + 0.2V or
SUB, SLB > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < VSS + 0.2V
ICCDR
Data Retention Current
0.2
6
µA
Chip Deselect to Data
Retention Time
tCDR
0
ns
ns
See Data Retention Timing Diagram
(2)
tR
Note:
Operating Recovery Time
tRC
1. Typical values are under the condition of TA = 25°C. Typical values are sampled and not 100% tested.
2. tRC is read cycle time.
50.1 Data Retention Timing Diagram 1
DATA RETENTION MODE
VCC
2.7V
tCDR
tR
IH
VDR
SCS1 > VCC - 0.2V
SCS1
VSS
50.2 Data Retention Timing Diagram 2
DATA RETENTION MODE
VCC
2.7V
tCDR
tR
SCS2
VDR
0.4V
VSS
SCS2 < 0.2V
32
AT52BR1664A(T)
3361D–STKD–1/07
AT52BR1664A(T)
51. Ordering Information
51.1 Standard Package
tACC (ns)
Voltage Range
Ordering Code
Boot Block
Package
Operation Range
70
AT52BR1664AT-70CI
Top
90
70
90
AT52BR1664AT-90CI
AT52BR1664A-70CI
AT52BR1664A-90CI
Top
Industrial
(-40° to 85°C)
2.7V - 3.3V
66C5
Bottom
Bottom
51.2 Green Package (Pb/Halide-free)
tACC (ns)
Voltage Range
Ordering Code
Boot Block
Package
Operation Range
70
AT52BR1664AT-70CU
Top
90
70
90
AT52BR1664AT-90CU
AT52BR1664A-70CU
AT52BR1664A-90CU
Top
Industrial
(-40° to 85°C)
2.7V - 3.3V
66C5
Bottom
Bottom
Package Type
66-ball, Plastic Chip-scale Ball Grid Array Package (CBGA)
66C5
33
3361D–STKD–1/07
52. Packaging Information
52.1 66C5 – CBGA
0.12
C
E
Seating Plane
C
Marked A1 Identifier
D
Side View
A1
A
Top View
0.60 REF
E1
A1 Ball Corner
1.20 REF
e
A
B
C
D
E
F
D1
COMMON DIMENSIONS
(Unit of Measure = mm)
G
H
MIN
9.90
–
MAX
10.10
–
NOM
10.00
8.80
8.00
5.60
–
NOTE
SYMBOL
e
E
2
12 11 10
9
8
7
5
4
1
6
3
E1
D
Øb
7.90
–
8.10
–
Bottom View
D1
A
–
1.20
–
A1
e
0.25
–
0.80 BSC
0.40
Øb
–
–
09/19/01
DRAWING NO. REV.
66C5
TITLE
2325 Orchard Parkway
San Jose, CA 95131
66C5, 66-ball (12 x 8 Array), 10 x 8 x 1.2 mm Body, 0.8 mm Ball
Pitch Chip-scale Ball Grid Array Package (CBGA)
A
R
34
AT52BR1664A(T)
3361D–STKD–1/07
Atmel Corporation
Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Memory
RF/Automotive
Theresienstrasse 2
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Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
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Regional Headquarters
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San Jose, CA 95131, USA
Tel: 1(408) 441-0311
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3361D–STKD–1/07
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