AS6VA5128-BC [ETC]
2.7V to 3.3V 512K X 8 Intelliwatt low-power CMOS SRAM; 2.7V至3.3V 512K ×8 Intelliwatt低功耗CMOS SRAM
| 型号： | AS6VA5128-BC |
| 厂家： | 
ETC |
| 描述： | 2.7V to 3.3V 512K X 8 Intelliwatt low-power CMOS SRAM |
| 文件： | 总9页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 2000
AS6VA5128
®
2.7V to 3.3V 512K × 8 Intelliwatt™ low-power CMOS SRAM
Features
• 1.2V data retention
• AS6VA5128
• Equal access and cycle times
• Intelliwatt™ active power circuitry
• Industrial and commercial temperature ranges available
• Organization: 524,288 words × 8 bits
• 2.7V to 3.3V at 55 ns
• Low power consumption: ACTIVE
- 132 mW at 3.3V and 55 ns
• Easy memory expansion with CS, OE inputs
• Smallest footprint packages
- 36(48)-ball FBGA
- 32-pin TSOP I and TSOP II packages are available on
Alliance AS6UB5128 product family (available January
2001)
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
• Low power consumption: STANDBY
- 66 µW max at 3.3V
48-CSP BGA Package (shading indicates no ball)
Logic block diagram
VCC
GND
1
2
3
4
5
6
Input buffer
A
B
C
D
E
A
A
A
NC
WE
NC
A
A
A
A
A
A
8
0
1
2
3
4
5
6
7
A0
I/O
I/O
I/O
I/O
5
6
1
2
A1
A2
A3
A4
A5
A6
A7
A8
I/O8
I/O1
512K × 8
Array
(4,194,304)
V
V
V
CC
SS
V
CC
SS
F
I/O
A
A
A
A
I/O
I/O
7
8
18
17
16
12
3
4
WE
OE
CS
Column decoder
Control
circuit
G
H
I/O
OE
CS
A
A
15
13
A
A
A
A
9
10
11
14
Selection guide
V
Range
Power Dissipation
Operating (I Standby (I
CC
2
)
)
SB1
Min
(V)
Typ
Max
(V)
Speed
(ns)
CC
Product
(V)
Max (mA)
2
Max (µA)
AS6VA5128
2.7
3.0
3.3
55
20
10/6/00
ALLIANCE SEMICONDUCTOR
1
Copyright ©2000 Alliance Semiconductor. All rights reserved.
AS6VA5128
®
Functional description
The AS6VA5128 is a low-power CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as
524,288 words × 8 bits. It is designed for memory applications where slow data access, low power, and simple interfacing
are desired.
Equal address access and cycle times (t , t , t ) of 55 ns are ideal for low-power applications. Active high and low chip
AA RC WC
selects (CS) permit easy memory expansion with multiple-bank memory systems.
When CS is high, the device enters standby mode: the AS6VA5128 is guaranteed not to exceed 66 µW power consumption
at 3.3V and 55ns. The device also returns data when V is reduced to 1.5V for even lower power consumption.
CC
A write cycle is accomplished by asserting write enable ( WE) and chip select (CS) low. Data on the input pins I/O1–I/O8 is
written on the rising edge of WE (write cycle 1) or CS (write cycle 2).To avoid bus contention, external devices should drive
I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE), chip select (CS), with write enable (WE) High. The chip
drives I/O pins with the data word referenced by the input address. When either chip select or output enable is inactive, or
write enable is active, output drivers stay in high-impedance mode.
All chip inputs and outputs are CMOS-compatible, and operation is from a single 2.7V to 3.3V supply. The device is
available in the JEDEC standard 36(48)-ball FBGA package.
Absolute maximum ratings
Parameter
Device
Symbol
Min
–0.5
–0.5
–
Max
V + 0.5
CC
Unit
V
Voltage on V relative to V
V
CC
SS
tIN
Voltage on any I/O pin relative to GND
Power dissipation
V
V
tI/O
P
1.0
+150
+125
20
W
D
Storage temperature (plastic)
T
–65
–55
–
°C
°C
mA
stg
Temperature with V applied
T
bias
CC
DC output current (low)
I
OUT
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CS
H
L
WE
X
OE
X
Supply Current
I/O1–I/O8
High Z
Mode
Standby (I
Standby (I
I
I
)
)
SB
SB
CC
CC
CC
SB
SB
X
X
High Z
L
H
H
I
I
I
High Z
Output disable (I
)
CC
L
H
L
D
Read (I
)
CC
OUT
L
L
X
D
Write (I
)
CC
IN
Key: X = Don’t care, L = Low, H = High.
2
ALLIANCE SEMICONDUCTOR
10/6/00
AS6VA5128
®
Recommended operating condition (over the operating range)
Parameter
Description
Test Conditions
Min
2.4
Max
0.4
Unit
V
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Load Current
I
= –2.1mA
= 2.1mA
OL
V
V
V
V
= 2.7V
= 2.7V
= 2.7V
= 2.7V
OH
OH
CC
CC
CC
CC
CC
V
I
V
OL
V
2.2
–0.5
–1
V
+ 0.5
CC
V
IH
V
0.8
+1
+1
V
IL
I
GND < V < V
µA
µA
IX
IN
I
I
GND < V < V ; Outputs High Z
–1
OZ
CC
O
CC
CS = V ,
IL
V
Operating Supply
Current
CC
I
= 0mA, f = 0,
V
V
= 3.3V
= 3.3V
2
5
mA
mA
mA
µA
µA
µA
OUT
CC
CC
V
= V or V
IN
IL IH
CS < 0.2V, V
0.2V,
<
IN
Average V Operating
CC
I
@
CC1
Supply Current at 1
MHz
1 MHz
or V > V – 0.2V,
IN
CC
f = 1 mS
Average V Operating CS ≠ V , V = V
IL
CC
IL
IN
I
V
= 3.3V (55 ns)
CC
40
100
20
2
CC2
Supply Current
or V , f = f
IH Max
CS Power Down
Current; TTL Inputs
CS > V , other inputs
IH
I
V
= 3.3V
= 3.3V
= 1.2V
SB
CC
CC
CC
= 0V – V
CC
CS > V – 0.2V,
other inputs = 0V –
CC
CS Power Down
Current; CMOS Inputs
I
V
V
SB1
V
, f = f
CC
Max
CS > V – 0.1V,
CC
f = 0
I
Data Retention
SBDR
Capacitance (f = 1 MHz, T = Room temperature, V = NOMINAL)2
a
CC
Signals
Parameter
Input capacitance
Symbol
Test conditions
= 0V
Max
Unit
C
A, CS, WE, OE
I/O
V
5
7
pF
pF
IN
IN
I/O capacitance
C
V
= V
= 0V
I/O
IN
OUT
10/6/00
ALLIANCE SEMICONDUCTOR
3
AS6VA5128
®
Read cycle (over the operating range)3,9
Parameter
Read cycle time
Symbol
Min
55
–
Max
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
t
RC
AA
Address access time
t
55
55
25
–
3
3
Chip select (CS) access time
Output enable (OE) access time
Output hold from address change
CS low to output in low Z
CS high to output in high Z
OE low to output in low Z
OE high to output in high Z
Power up time
t
–
ACS
t
–
OE
t
10
10
0
5
OH
t
–
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
CLZ
CHZ
OLZ
OHZ
t
t
20
–
5
t
0
20
–
t
t
0
PU
PD
Power down time
–
55
Key to switching waveforms
Rising input
Falling input
Undefined/don’t care
Read waveform 1 (address controlled)3,6,7,9
tRC
Address
tAA
tOH
tOH
DOUT
Previous data valid
Data valid
Read waveform 2 (CS, OE controlled)3,6,8,9
tRC1
CS
tOE
OE
tOLZ
tOHZ
tCHZ
tACE
DOUT
Data valid
tCLZ
tPD
50%
ICC
tPU
Supply
current
ISB
50%
4
ALLIANCE SEMICONDUCTOR
10/6/00
AS6VA5128
®
Write cycle (over the operating range)11
Parameter
Symbol
Min
55
40
40
0
Max
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
12
Write cycle time
t
WC
Chip select to write end
Address setup to write end
Address setup time
t
–
CW
t
–
AW
t
–
12
AS
WP
AH
DW
Write pulse width
t
t
35
0
–
Address hold from end of write
Data valid to write end
Data hold time
–
t
25
0
–
t
–
4, 5
4, 5
4, 5
DH
WZ
OW
Write enable to output in high Z
Output active from write end
t
0
20
–
t
5
Write waveform 1 (WE controlled)10,11
tWC
tAW
tAH
Address
tWP
WE
tAS
tDW
tDH
DIN
Data valid
tWZ
tOW
DOUT
Write waveform 2 (CS controlled)10,11
tWC
tAW
tAH
Address
tAS
tCW
CS
tWP
WE
tWZ
tDW
Data valid
tDH
DIN
DOUT
10/6/00
ALLIANCE SEMICONDUCTOR
5
AS6VA5128
®
Data retention characteristics (over the operating range)13,5
Parameter
Symbol
Test conditions
Min
1.2V
–
Max
3.3
4
Unit
V
V
for data retention
V
DR
CC
V
= 1.2V
CC
Data retention current
I
µA
ns
CS ≥ V – 0.1V or
CCDR
CC
V
≥ V – 0.1V or
Chip deselect to data retention time
Operation recovery time
t
0
–
IN
CC
CDR
V
≤ 0.1V
IN
t
t
–
ns
R
RC
Data retention waveform
Data retention mode
VCC
VCC
VCC
VDR ≥ 1.2V
tCDR
tR
VDR
VIH
VIH
CS
AC test loads and waveforms
Thevenin equivalent:
RTH
R1
R1
VCC
VCC
OUTPUT
V
OUTPUT
VCC Typ
OUTPUT
30 pF
5 pF
ALL INPUT PULSES
R2
R2
90%
10%
90%
10%
INCLUDING
JIG AND
INCLUDING
JIG AND
SCOPE
< 5 ns
(c)
GND
(a)
SCOPE
(b)
= 2.5V
Parameters
V
= 3.0V
V
V = 2.0V
CC
Unit
CC
CC
R1
R2
1105
16670
15294
Ohms
Ohms
Ohms
Volts
1550
645
15380
8000
1.2V
11300
6500
R
TH
V
1.75V
0.85V
TH
Notes
1
2
3
4
5
6
7
8
9
During VCC power-up, a pull-up resistor to VCC on CS is required to meet ISB specification.
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions.
t
CLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500 mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is HIGH for read cycle.
CS and OE are LOW for read cycle.
Address valid prior to or coincident with CS transition LOW.
All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CS or WE must be HIGH during address transitions. Either CS or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 N/A.
13 1.2V data retention applies to commercial and industrial temperature range operations.
14 C = 30pF, except at high Z and low Z parameters, where C = 5pF.
6
ALLIANCE SEMICONDUCTOR
10/6/00
AS6VA5128
®
Typical DC and AC characteristics
Normalized supply current
vs. supply voltage
1.4
Normalized access time
vs. supply voltage
Normalized standby current
vs. ambient temperature
1.0
3.0
2.5
2.0
1.2
1.0
0.8
VCC = VCC typ
VIN = VCC typ
0.75
0.5
1.5
1.0
0.5
TA = 25° C
VIN = VCC typ
TA = 25° C
0.6
0.4
0.2
0.0
0.0
0.25
0.0
–0.5
1.7
2.2
2.7
3.2
3.7
1.7
2.2
2.7
3.2
3.7
–55
25
105
Supply voltage (V)
Supply Voltage (V)
Ambient temperature (°C)
Normalized standby current
vs. supply voltage
Normalized ICC
vs. Cycle Time
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.5
1.0
ISB2
V
IN = 3.6V
TA = 25° C
0.50
0.10
VIN = VCC typ
TA = 25° C
1
5
10
15
2.8
1.9
Supply voltage (V)
1
3.7
Supply voltage (V)
10/6/00
ALLIANCE SEMICONDUCTOR
7
AS6VA5128
®
Package diagrams and dimensions
36(48)-ball FBGA
Top View
Bottom View
Ball #A1 index
6
5
4
3
2
1
Ball #A1
A
B
C
D
E
SRAM Die
C
C1
F
A
G
H
Elastomer
A
B
B1
Detail View
Side View
A
E2
D
E
Y
E2
E
Die
Die
E1
0.3/Typ
Minimum
Typical Maximum
A
–
6.90
–
0.75
7.00
3.75
11.00
5.25
0.35
–
–
7.10
–
Notes
B
B1
C
1. Bump counts: 36(48) (8 row × 6 column).
2. Pitch: (x,y) = 0.75 mm × 0.75 mm (typ).
3. Units: millimeters.
10.90
–
11.10
–
C1
D
4. All tolerances are ±0.050, unless otherwise specified.
5. Typ: typical.
0.30
–
0.40
1.20
–
E
6. Y is coplanarity: 0.08 (max).
E1
E2
Y
–
0.68
0.25
–
0.22
–
0.27
0.08
8
ALLIANCE SEMICONDUCTOR
10/6/00
AS6VA5128
®
Ordering codes
Speed (ns)
Ordering Code
AS6VA5128-BC
AS6VA5128-BI
Package Type
Operating Range
55
55
48-ball fine pitch BGA
48-ball fine pitch BGA
Commercial
Industrial
Part numbering system
AS6VA
5128
T, ST, HF, HR, B
C, I
Temperature range:
C: Commercial: 0° C to 70° C
I: Industrial: –40°C to 85° C
Package:
B: CSP BGA
SRAM Intelliwatt™ prefix
Device number
10/6/00
ALLIANCE SEMICONDUCTOR
9
Copyright © 2000. Alliance Semiconductor Corporation (Alliance)'s three-point logo, our name, and Intelliwatt™ are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks
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parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of
Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indem nify Alliance against all claims arising from such use.
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