AN-20 [ETC]
Transient Suppression Techniques for TOPSwitch Power Supplies ; 为TOPSwitch电源瞬态抑制技术\n
| 型号： | AN-20 |
| 厂家： | 
ETC |
| 描述： | Transient Suppression Techniques for TOPSwitch Power Supplies
|
| 文件： | 总8页 (文件大小：116K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
Transient Suppression Techniques
for TOPSwitch® Power Supplies
Application Note AN-20
U
1.0
0.9
Introduction
Front Time
= 1.67 x T = 1.2 µs ± 30%
T
1
AC power mains occasionally have transient surge voltages.
Lightning strikes and AC mains load switching are just two
examplesofmanypossibleconditionscausingtransientvoltages.
Consequently, all off-line power supplies must provide some
Time To Half Value
= 50 µs ± 20%
T
2
0.5
T
2
0.3
0.1
0.0
level of protection to suppress the effects of such transient
t
T
voltages.
T
1
PI-1709-120595
Thisapplicationnotepresentsdesigntechniqueswhichimprove
TOPSwitch power supply operation through most AC mains
transient surge voltages. Properly designed transformers, PC
boards, and EMI filters not only suppress the effects from
transient voltages but also reduce both conducted and radiated
EMI emissions as well. These techniques can also be used in
applications with DC input voltages such as Telecom and
Television Cable Communication (or Cablecom).
Figure 1. Waveshape of Open Circuit Voltage (1.2/50 µS)
From IEC-1000-4-5.
V
peak
0.9 V
peak
T = 10 µs (f = 100 kHz)
The ST202A Reference Design Board using the TOP202YAI
TOPSwitch will be used as an example throughout this
application note. Refer to the ST202A data sheet as well as
AN-14 and AN-15 for additional information.
0.1 V
peak
0.5 µs
Typical Transient Test Voltages
Figure 1 shows a typical surge voltage waveform specified by
IEC 1000-4-5 (formerly IEC 801-4-5). Peak test voltages (U)
of 3kV are common but in some applications higher peak
voltagesarespecified. Thesurgevoltagewaveformhasa1.2µS
front time T1 and 50µS time to half value T2 as shown.
60% OF V
peak
PI-1710-120595
Figure 2. 0.5 µs-100 kHz Ring Wave (Open-Circuit Voltage)
From IEEE-587.
Figure 2 shows a typical ring wave voltage waveform specified
byIEEE-587. Peaktest voltages(Vpeak) of 3kV are commonbut
in some applications higher voltages are specified. The open
circuit ring wave voltage waveform has a 0.5µS rise time to
90% of peak value and exponentially decays while oscillating
at 100 kHz with each peak being 60% of the preceding peak.
voltage first to one AC mains conductor and then the other with
respect to earth ground. The TOPSwitch power supply output
should be connected either directly to earth ground or AC
coupled through a capacitor to earth ground. This transient test
voltage causes high peak transient ringing currents to flow
between the TOPSwitch power supply primary and secondary.
Without proper attention to EMI filter design, transformer
design, and PC layout design, transient currents couple into
signal traces and generate voltage spikes capable of setting the
TOPSwitch shutdown latch.
Thetransienttestvoltagemaybeappliedbothincommonmode
and differential mode configurations. The common mode
configuration shown in Figure 3 applies the transient test
June 1996
AN-20
TRANSIENT
GENERATOR
R = 10 Ω
C = 9 µF
R
C
DECOUPLING NETWORK
L = 20 mH
L
AC (DC)
UNIT
UNDER
TEST
POWER
SUPPLY
NETWORK
N
PE
GROUND REFERENCE
PI-1711-120595
Figure 3. Typical Test Set-Up for Capacitive Coupling on AC Lines; Common Mode or Line to Ground Coupling.
TRANSIENT
GENERATOR
DECOUPLING NETWORK
C = 18 µF
L = 20 mH
L
AC (DC)
UNIT
UNDER
TEST
POWER
SUPPLY
NETWORK
N
PE
GROUND REFERENCE
PI-1712-120595
Figure 4. Typical Test Set-up for Capacitive Coupling on AC Lines; Differential Mode or Line to Line Coupling.
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AN-20
Circuit Countermeasures
+1
0
V
o
The following circuit countermeasures have been shown to
improve TOPSwitch power supply operation under transient
spike or surge voltage conditions. TOPSwitch ST202A power
supplieshavebeendemonstratedtosuccessfullyoperatethrough
both ring wave and 1.2µS/50µS surge voltages with peak
voltages up to 3 kV with the following circuit modifications.
All common mode countermeasures apply to differential mode
transient test conditions as well.
V
DIODE (ENVELOPE)
+10
0
-1
-10
-20
160V
450V
-30
-40
Common Mode Countermeasures
Eliminate all PC Board arcing! Dim the lights and closely
examinethePCboardduringtestingforsignsofarcingbetween
PC traces or conductors. Change the PC layout temporarily
with trace cuts and jumpers to increase the spacing and make
permanent changes on the PC board artwork. Slots in the PC
board can be used to increase effective clearance.
PI-1716-120595
Figure 5. Output Voltage and Envelope of Diode Voltage Waveform
During Normal Mode Transient Surge.
The differential mode configuration shown in Figure 4 applies
thetransienttestvoltageacrossbothACmainsconductors. The
TOPSwitch power supply output should be connected either
directly to earth ground or AC coupled through a capacitor to
earthground. Thistransienttestvoltagecauseshighdifferential
modetransientcurrentswhichcanoverchargethepowersupply
bulk energy storage capacitor (C1 in Figure 7) or high voltage
DC bus (V+) to a high value. During transient testing, directly
measuring the V+ high voltage DC bus is dangerous and can
lead to equipment damage. Fortunately, the V+ high voltage
DC bus can be measured indirectly on the secondary side of the
power supply. Figure 5 shows the ST202A power supply
output voltage and the envelope of the output rectifier (D2 in
Figure 7) anode voltage during a differential mode test. The
anode voltage is useful because the envelope above reference is
proportionaltopowersupplyoutputvoltageVO andtheenvelope
below reference is proportional to the V+ high voltage DC bus.
During the transient test, input capacitor C1 and the V+ high
voltage DC bus is charged from 160 VDC up to 450 VDC but
the TOPSwitch simply operates through with just a minor
output voltage correction.
Replacecommonmodechokewithwiderbandwidthstyle. One
example of a wide bandwidth common mode choke is shown in
Figure 6. Note that each common mode inductor is wound in
two series connected sections to reduce capacitance. Two
section construction also divides or splits the transient test
voltage to reduce voltage stress and prevent arcing between
commonmodechokewindings. Use10mH to33mHcommon
mode chokes such as the Panasonic ELF-18D290X series for
output power under 20 Watts and ELF-18D2XX series for
output power over 20 Watts. (Toroidal common mode chokes
are not recommended.)
Some differential mode transient test voltages are capable of
charging input capacitor C1 up to a voltage sufficient to cause
the bridge rectifier diodes to enter avalanche breakdown which
essentially clamps the high voltage DC bus (V+). Sometimes
the fuse opens, sometimes the bridge rectifier fails and then the
fuse opens. In the worst case scenario, the transient test voltage
charges up input capacitor C1 to a sufficiently high DC bus
voltage (V+) that TOPSwitch Drain voltage rating is exceeded.
0.8
10.0±0.5
16.0±1.0
13.0±0.5
21.0±1.0
PI-1635-111695
Figure 6. Spool Wound Common Mode Choke (Dimensions in mm).
A
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AN-20
Figure 7 shows a typical 2-wire input TOPSwitch ST202A
power supply modified with Y2-safety capacitors C7, C8, and
C11. TheschematicisdrawntoemphasizethatC7,C8,andC11
should connect directly to the transformer pins. This capacitor
connectionkeepspeaktransientcurrentsflowingthroughknown
paths and out of sensitive PC traces. Note that C11 connects to
the high voltage DC bus (V+), C7 connects to the high voltage
DC bus return (V-), and C8 connects directly to secondary
return. C7, C8, and C11 must have very short leads and be
connected with short, wide traces.
T1
T1202
C11
2.2 nF
Y2
D2
UG8BT
L1
3.3 µH
8
7.5 V
V+
R1
39 Ω
1
R2
68 Ω
C3
VR1
120 µF
25 V
P6KE150
C2
680 µF
25 V NEC2501-H
U2
C8
2.2 nF
Y2
D1
UF4005
VR2
1N5995B
6.2 V
BR1
400 V
2
C1
33 µF
400 V
RTN
L2
22 mH
7
3
D3
IN4148
C6
0.1 µF
X2
C5
47µF
C7
2.2 nF
Y2
C4
0.1 µF
4
F1
3.15 A
DRAIN
SOURCE
CONTROL
L
R6
270 Ω to 620 Ω
U1
TOP202YAI
V-
N
J1
PI-1706-120495
Figure 7. Modified ST202A Power Supply, 2-Wire Input.
A
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AN-20
Figure 8 shows a typical 3-wire modification to the ST202A
TOPSwitch power supply. The earth ground wire is threaded
through a ferrite bead or toroid to damp power cord resonances
(see AN-15). Because of the connection to earth ground, C8 no
longer needs to be a Y-capacitor but can be replaced with a
simple, general purpose and low cost ceramic 0.1 uF capacitor.
C7, C8, and C11 must have very short leads and be connected
with short, wide traces.
T1
T1202
C11
2.2 nF
Y2
D2
UG8BT
L1
3.3 µH
BEAD
OR
8
7.5 V
TOROID
V+
R1
39 Ω
1
R2
68 Ω
C3
VR1
120 µF
25 V
P6KE150
C2
680 µF
U2
25 V NEC2501-H
D1
UF4005
C8
0.1µF
VR2
1N5995B
6.2 V
BR1
400 V
2
C1
33 µF
400 V
L2
22 mH
RTN
7
3
D3
IN4148
C6
0.1 µF
C5
47µF
X2
C7
2.2 nF
Y2
C4
0.1 µF
4
F1
3.15 A
DRAIN
SOURCE
CONTROL
L
R6
270 Ω to 620 Ω
U1
TOP202YAI
V-
N
J1
PI-1708-120495
Figure 8. Modified ST202A Power Supply, 3-Wire Input.
A
6/96
5
AN-20
Figure9shows atypical3-wireinputpowersupplywithcascaded
LC EMI filters. The sum of common mode inductance L2 and
L3 should be 10 mH or less and L3 should be at least twice the
valueofL2topreventsuperpositionoffilterresonantfrequencies.
L2 will tend to have higher bandwidth and effectively filters
higherfrequencycommonmodecurrentsclosetotheinputpower
connection.
T1
T1202
C11
2.2 nF
Y2
D2
UG8BT
L1
3.3 µH
BEAD
OR
8
7.5 V
TOROID
V+
R1
39 Ω
1
R2
C12
0.1 µF
68 Ω
C3
120 µF
25 V
VR1
P6KE150
X2
L3
6.8 mH
C2
680 µF
U2
25 V NEC2501-H
D1
UF4005
C8
0.1µF
VR2
1N5995B
6.2 V
BR1
400 V
2
C1
33 µF
400 V
L2
3.3 mH
RTN
7
3
D3
IN4148
C6
0.1 µF
X2
C5
47µF
C7
2.2 nF
Y2
C4
0.1 µF
4
F1
3.15 A
DRAIN
SOURCE
CONTROL
L
R6
270 Ω to 620 Ω
U1
TOP202YAI
V-
N
J1
PI-1707-120495
Figure 9. Modified ST202A Power Supply, 3-Wire Input with Two Cascaded LC EMI Filters.
A
6/96
6
AN-20
The primary bias winding should be connected directly with a
single trace to the TOPSwitch Source pin as shown in Figures
7, 8, and 9. Bias filter capacitor C4 should also connect directly
to the TOPSwitch Source pin with a single trace.
Figure 12 shows a split sandwich primary transformer. The
"noisy" or TOPSwitch connected half of the primary is
wound followed by 1 or 2 tape layers and the bias winding.
To reduce transformer capacitance, 3 to 5 tape layers are
placed followed by the secondary. 3 to 5 more tape layers
are placed before winding the "quiet" or V+ connected half
of the primary.
Auto-restart capacitor C5 should be connected directly across
TOPSwitchControlandSourcepinstoreducenoisevoltageson
the Control pin.
Reducing transformer capacitance reduces the peak transient
currents. To reduce transformer capacitance, the primary must
be properly located relative to the other windings. 3 to 5 layers
of 2 mil thick polyester film tape should also be used between
the secondary and all primary referenced windings. Three
typical transformer design examples are given below:
Outer Insulation
Quiet Primary Half
3 to 5 Layers Tape
Secondary
3 to 5 Layers Tape
Primary Bias
Figure 10 shows a transformer with single primary
layer, single tape layer and bias winding layer. To reduce
capacitance,3to5tapelayersareaddedbeforethesecondary
is wound.
1 to 2 Layers Tape
Noisy Primary Half
PI-1715-120595
Figure 12. Split Sandwich Primary Transformer Cross Section.
When using triple insulated wire secondaries, the number of
tape layers can be reduced to 1 or 2 layers due to the inherent
spacing and reduced capacitance provided by the insulated
wire.
Outer Insulation
Secondary
3 to 5 Layers Tape
Primary Bias
Basic Insulation
Primary
PI-1713-120595
The highest transformer secondary resistance (smallest wire
diameter) should be used which is still consistent with power
supply efficiency requirements. Slightly higher secondary
resistance helps limit peak transient currents.
Figure 10. Single Layer Primary Transformer Cross Section.
Heat sinks should be either connected only to TOPSwitchtab or
completelyisolatedfrombothTOPSwitchtabandcircuit. Ifthe
heat sink is connected elsewhere in circuit but isolated from
TOPSwitch tab, capacitance between TOPSwitch tab and heat
sinkcanresonatewithcircuitinductancecausinghighfrequency
ringingcurrentswhichmaytriggerTOPSwitch shutdownlatch.
Figure 11 shows a two layer primary transformer with the
"noisy" or TOPSwitch connected half of the primary buried
or shielded beneath the "quiet" or V+ connected half of the
primary. To reduce transformer capacitance, 3 to 5 tape
layers are placed before the secondary is wound. 3 to 5 more
tape layers are placed over the secondary before the
primary bias winding is wound.
Additional Countermeasures for Differential Mode
Add resistor R6 (approximately 270 to 620 Ohms) in series
with the optocoupler (U2) phototransistor emitter as shown in
Figures 7, 8, and 9. R6 limits peak current flow below the
latchedshutdowntriggercurrentthresholdduringoutputvoltage
and control loop overshoot.
Outer Insulation
Primary Bias
3 to 5 Layers Tape
Select larger input capacitor C1 to control the final DC bus
voltage.
Secondary
3 to 5 Layers Tape
Quiet Primary Half
Carefully select bridge rectifier BR1 (or discrete diodes) for
avalanche and voltage clamping capability.
Basic Insulation
Noisy Primary Half
PI-1714-120595
Select a common mode choke to withstand some excessive
normal mode current levels (occurring when bridge diodes
Figure 11. Two-Layer Primary Transformer Cross Section.
A
6/96
7
AN-20
V+
F1
L2
L
BR1
N
C6
0.1 µF
X2
VR3
MOV
COMMON
MODE
CHOKE
TO
POWER
SUPPLY
V-
PI-1717-120595
Figure 13. MOV VR3 Position Relative to X-Capacitor C6, Common Mode Choke L2 and Bridge Rectifier BR1.
avalanche and clamp the V+ high voltage DC bus) without
causing sufficient coil magnetostriction to stress and crack the
ferrite core.
Select MOV or metal-oxide-varistor transient suppressor to
“clip” the peak off the higher transient test voltages. Connect
varistor VR3 between fuse F1 and common mode choke L2 as
shown in Figure 13. Long term reliability of VR3 should be
high because VR3 absorbs only a portion of the energy
associated with the highest peak transient test voltages. Lower
peak transient test voltages can be safely tolerated without VR3
absorbing significant energy.
For lower power 100 to 115 VAC applications, use higher
voltageTOP2XXTOPSwitchforimprovedvoltagebreakdown
margin relative to peak DC bus voltage V+ (across C1) which
occurs following application of the transient test voltage.
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability.
Power Integrations does not assume any liability arising from the use of any device or circuit described herein, nor does it
convey any license under its patent rights or the rights of others.
PI Logo and TOPSwitch are registered trademarks of Power Integrations, Inc.
©Copyright 1994, Power Integrations, Inc. 477 N. Mathilda Avenue, Sunnyvale, CA 94086
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