AMDATHLONXP_技术文档

Preliminary Information

TM

AMD Athlon XP

Processor Model 8

Data Sheet

Publication # 25175 Rev. H

Issue Date: March 2003

Preliminary Information

The contents of this document are provided in connection with Advanced

Micro Devices, Inc. (“AMD”) products. AMD makes no representations or war-

ranties with respect to the accuracy or completeness of the contents of this

publication and reserves the right to make changes to specifications and prod-

uct descriptions at any time without notice. No license, whether express,

implied, arising by estoppel or otherwise, to any intellectual property rights is

granted by this publication. Except as set forth in AMD’s Standard Terms and

Conditions of Sale, AMD assumes no liability whatsoever, and disclaims any

express or implied warranty, relating to its products including, but not limited

to, the implied warranty of merchantability, fitness for a particular purpose,

or infringement of any intellectual property right.

AMD’s products are not designed, intended, authorized or warranted for use

as components in systems intended for surgical implant into the body, or in

other applications intended to support or sustain life, or in any other applica-

tion in which the failure of AMD’s product could create a situation where per-

sonal injury, death, or severe property or environmental damage may occur.

AMD reserves the right to discontinue or make changes to its products at any

time without notice.

Trademarks

AMD, the AMD Arrow logo, AMD Athlon, AMD Duron, and combinations thereof, QuantiSpeed, and 3DNow!

are trademarks of Advanced Micro Devices, Inc.

HyperTransport is a licensed trademark of the HyperTransport Technology Consortium.

MMX is a trademark of Intel Corporation.

Windows is a registered trademark of Microsoft Corporation.

Other product names used in this publication are for identification purposes only and may be trademarks of

their respective companies.

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

Contents

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1

QuantiSpeed™ Architecture Summary. . . . . . . . . . . . . . . . . . . 2

2

Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1

2.2

2.3

2.4

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Signaling Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Push-Pull (PP) Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

AMD Athlon™ System Bus Signals . . . . . . . . . . . . . . . . . . . . . . 6

3

4

Logic Symbol Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.1

Power Management States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Working State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Stop Grant States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Probe State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Connect and Disconnect Protocol . . . . . . . . . . . . . . . . . . . . . . 12

Connect Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Connect State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Clock Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4.2

4.3

5

6

CPUID Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Advanced 266 Front-Side Bus AMD Athlon™ XP

Processor Model 8 Specifications. . . . . . . . . . . . . . . . . . . . . . . 21

6.1

Part-Specific Electrical and Thermal Specifications

for Advanced 266 FSB AMD Athlon XP Processors

Model 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Advanced 266 FSB AMD Athlon XP Processor Model 8

SYSCLK and SYSCLK# AC Characteristics . . . . . . . . . . . . . . 24

Advanced 266 FSB AMD Athlon System Bus

6.2

6.3

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7

Advanced 333 Front-Side Bus AMD Athlon™ XP

Processor Model 8 Specifications. . . . . . . . . . . . . . . . . . . . . . . 27

7.1

7.2

7.3

Electrical and Thermal Specifications for the Advanced

333 FSB AMD Athlon XP Processor Model 8 . . . . . . . . . . . . . 27

Advanced 333 FSB AMD Athlon XP Processor Model 8

SYSCLK and SYSCLK# AC Characteristics . . . . . . . . . . . . . . 28

Advanced 333 FSB AMD Athlon System Bus

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table of Contents

3

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

8

Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

8.1

8.2

8.3

8.4

8.5

8.6

8.7

8.8

8.9

Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Interface Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Voltage Identification (VID[4:0]) . . . . . . . . . . . . . . . . . . . . . . 33

Frequency Identification (FID[3:0]) . . . . . . . . . . . . . . . . . . . . 33

VCCA AC and DC Characteristics. . . . . . . . . . . . . . . . . . . . . . 33

Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

V_{CC_CORE}Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

SYSCLK and SYSCLK# DC Characteristics . . . . . . . . . . . . . . 37

8.10 AMD Athlon System Bus DC Characteristics . . . . . . . . . . . . . 38

8.11 General AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . 39

8.12 Open-Drain Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

8.13 Thermal Diode Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42

Thermal Diode Electrical Characteristics. . . . . . . . . . . . . 42

Thermal Protection Characterization . . . . . . . . . . . . . . . . 43

8.14 APIC Pins AC and DC Characteristics . . . . . . . . . . . . . . . . . . 44

9

Signal and Power-Up Requirements . . . . . . . . . . . . . . . . . . . . 45

9.1

9.2

Power-Up Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Signal Sequence and Timing Description . . . . . . . . . . . . . 45

Clock Multiplier Selection (FID[3:0]) . . . . . . . . . . . . . . . . 48

Processor Warm Reset Requirements. . . . . . . . . . . . . . . . . . . 48

Northbridge Reset Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

10

Mechanical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10.1 Die Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

10.2 Part Number 27291 OPGA Package Dimensions for

AMD Athlon XP Processors Model 8 with a

CPUID of 680 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

10.3 Part Number 27291 OPGA Package Dimensions for

AMD Athlon XP Processors Model 8 with a

CPUID of 681 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

10.4 Part Number 27648 OPGA Package Dimensions for

AMD Athlon XP Processors Model 8 with a

CPUID of 681 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

11

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

11.1 Pin Diagram and Pin Name Abbreviations. . . . . . . . . . . . . . . 55

11.2 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

11.3 Detailed Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

A20M# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

AMD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

AMD Athlon System Bus Pins . . . . . . . . . . . . . . . . . . . . . . 74

Analog Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

APIC Pins, PICCLK, PICD[1:0]# . . . . . . . . . . . . . . . . . . . . 74

CLKFWDRST Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4

Table of Contents

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

CLKIN, RSTCLK (SYSCLK) Pins. . . . . . . . . . . . . . . . . . . . 74

CONNECT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

COREFB and COREFB# Pins. . . . . . . . . . . . . . . . . . . . . . . 75

CPU_PRESENCE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

DBRDY and DBREQ# Pins . . . . . . . . . . . . . . . . . . . . . . . . . 75

FERR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

FID[3:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

FSB_Sense[1:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

FLUSH# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

IGNNE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

INIT# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

INTR Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

JTAG Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

K7CLKOUT and K7CLKOUT# Pins. . . . . . . . . . . . . . . . . . 78

Key Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

NC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

NMI Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

PGA Orientation Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

PLL Bypass and Test Pins. . . . . . . . . . . . . . . . . . . . . . . . . . 78

PWROK Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

SADDIN[1:0]# and SADDOUT[1:0]# Pins. . . . . . . . . . . . . 79

Scan Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

SMI# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

STPCLK# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

SYSCLK and SYSCLK#. . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

THERMDA and THERMDC Pins. . . . . . . . . . . . . . . . . . . . 79

VCCA Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

VID[4:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

VREFSYS Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

ZN and ZP Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

12

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Standard AMD Athlon XP Processor Model 8 Products . . . . . . . . . . 81

Appendix A Thermal Diode Calculations . . . . . . . . . . . . . . . . . . . . . 83

Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Ideal Diode Equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Temperature Offset Correction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Appendix B Conventions and Abbreviations . . . . . . . . . . . . . . . . . . 87

Signals and Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Data Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Abbreviations and Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Related Publications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table of Contents

5

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

6

Table of Contents

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

List of Figures

Figure 1. Typical AMD Athlon™ XP Processor Model 8 System

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 2. Logic Symbol Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. AMD Athlon XP Processor Model 8 Power Management

States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 4. AMD Athlon System Bus Disconnect Sequence in the

Stop Grant State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 5. Exiting the Stop Grant State and Bus Connect Sequence . . . . 15

Figure 6. Northbridge Connect State Diagram . . . . . . . . . . . . . . . . . . . . . 16

Figure 7. Processor Connect State Diagram . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 8. SYSCLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 9. SYSCLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 10. V_{CC_CORE}Voltage Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 11. SYSCLK and SYSCLK# Differential Clock Signals . . . . . . . . . 37

Figure 12. General ATE Open-Drain Test Circuit. . . . . . . . . . . . . . . . . . . . 41

Figure 13. Signal Relationship Requirements During Power-Up

Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 14. AMD Athlon XP Processor Model 8 Part Number

27291 OPGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 15. AMD Athlon XP Processor Model 8 Part Number

27648 OPGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 16. AMD Athlon XP Processor Model 8 Pin Diagram

—Topside View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 17. AMD Athlon XP Processor Model 8 Pin Diagram

—Bottomside View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 18. OPN Example for the AMD Athlon XP Processor

Model 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

List of Figures

7

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

8

List of Figures

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

List of Tables

Table 1.

Electrical and Thermal Specifications for Processors

with a CPUID of 680. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 2.

Electrical and Thermal Specifications for Processors

with a CPUID of 681. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

SYSCLK and SYSCLK# AC Characteristics . . . . . . . . . . . . . . . 24

AMD Athlon™ System Bus AC Characteristics . . . . . . . . . . . . 25

Electrical and Thermal Specifications. . . . . . . . . . . . . . . . . . . . 27

SYSCLK and SYSCLK# AC Characteristics . . . . . . . . . . . . . . . 28

AMD Athlon System Bus AC Characteristics . . . . . . . . . . . . . . 29

Interface Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

VID[4:0] DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 10. FID[3:0] DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 11. VCCA AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 33

Table 12.

V_{CC_CORE}AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . 34

Table 13. Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 14. SYSCLK and SYSCLK# DC Characteristics . . . . . . . . . . . . . . . 37

Table 15. AMD Athlon System Bus DC Characteristics . . . . . . . . . . . . . . 38

Table 16. General AC and DC Characteristics. . . . . . . . . . . . . . . . . . . . . . 39

Table 17. Thermal Diode Electrical Characteristics . . . . . . . . . . . . . . . . . 42

Table 18. Guidelines for Platform Thermal Protection of the

Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 19. APIC Pin AC and DC Characteristics. . . . . . . . . . . . . . . . . . . . . 44

Table 20. Mechanical Loading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 21. Part Number 27291 OPGA Package Dimensions

for AMD Athlon XP Processors Model 8 with a

CPUID of 680 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 22. Part Number 27291 OPGA Package Dimensions

for AMD Athlon XP Processors Model 8 with a

CPUID of 681 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 23. Part Number 27648 OPGA Package Dimensions

for AMD Athlon XP Processors Model 8 with a

CPUID of 681 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 24. Pin Name Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 25. Cross-Reference by Pin Location . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 26. FID[3:0] Clock Multiplier Encodings . . . . . . . . . . . . . . . . . . . . . 76

Table 27. Front-Side Bus Sense Truth Table . . . . . . . . . . . . . . . . . . . . . . . 77

List of Tables

9

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

Table 28. VID[4:0] Code to Voltage Definition . . . . . . . . . . . . . . . . . . . . . 80

Table 29. Constants and Variables for the Ideal Diode Equation . . . . . . 83

Table 30. Constants and Variables Used in Temperature Offset

Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table 31. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Table 32. Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

10

List of Tables

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

Revision History

Date

Rev

Description

Public revision H of the AMD Athlon™ XP Processor Model 8 Data Sheet includes the following

changes:

■

In Chapter 6, revised Table 2, “Electrical and Thermal Specifications for Processors with a

CPUID of 681,” on page 23.

March 2003

H

■

In Chapter 12, revised Figure 18, “OPN Example for the AMD Athlon™ XP Processor Model 8,”

on page 81.

Public revision G of the AMD Athlon™ XP Processor Model 8 Data Sheet includes the following

changes:

■

In Chapter 6, revised Table 2, “Electrical and Thermal Specifications for Processors with a

CPUID of 681,” on page 23.

■

In Chapter 7, revised Table 6, “SYSCLK and SYSCLK# AC Characteristics,” on page 28.

In Chapter 10, renamed Table 21, “Part Number 27291 OPGA Package Dimensions for

AMD Athlon™ XP Processors Model 8 with a CPUID of 680,” on page 50, renamed Table 22,

“Part Number 27291 OPGA Package Dimensions for AMD Athlon™ XP Processors Model 8

with a CPUID of 681,” on page 51, added Table 23, “Part Number 27648 OPGA Package

Dimensions for AMD Athlon™ XP Processors Model 8 with a CPUID of 681,” on page 53,

renamed Figure 14, “AMD Athlon™ XP Processor Model 8 Part Number 27291 OPGA

Package,” on page 52, and added Figure 15, “AMD Athlon™ XP Processor Model 8 Part

Number 27648 OPGA Package,” on page 54.

March 2003

G

■

In Chapter 12, revised Figure 18, “OPN Example for the AMD Athlon™ XP Processor Model 8,”

on page 81.

Public revision F of the AMD Athlon™ XP Processor Model 8 Data Sheet includes the following

changes:

■

In Chapter 6, revised Table 2, “Electrical and Thermal Specifications for Processors with a

CPUID of 681,” on page 23.

December 2002

F

E

■

In Chapter 8, revised Table 16, “General AC and DC Characteristics,” on page 39 and

Figure 12, “General ATE Open-Drain Test Circuit,” on page 41.

Public revision E of the AMD Athlon™ XP Processor Model 8 Data Sheet includes the following

changes:

■

In Chapter 6, revised Table 2, “Electrical and Thermal Specifications for Processors with a

CPUID of 681,” on page 23.

■

In Chapter 3, revised Figure 2, “Logic Symbol Diagram,” on page 7.

In Chapter 7, revised Table 5, “Electrical and Thermal Specifications,” on page 27.

In Chapter 8, revised Table 9, “VID[4:0] DC Characteristics,” on page 33.

November 2002

In Chapter 12, revised Figure 18, “OPN Example for the AMD Athlon™ XP Processor Model 8,”

on page 81.

Revision History

11

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

Date

Rev

Description

Public revision D of the AMD Athlon™ XP Processor Model 8 Data Sheet includes the following

changes:

■

In Chapter 1, revised wording in Overview.

In Chapter 6, revised Table 2, “Electrical and Thermal Specifications for Processors with a

CPUID of 681,” on page 23, added Table 3, “SYSCLK and SYSCLK# AC Characteristics,” on

page 24, Figure 8, “SYSCLK Waveform,” on page 24, and Table 4, “AMD Athlon™ System

Bus AC Characteristics,” on page 25.

■

Added Chapter 7, “Advanced 333 Front-Side Bus AMD Athlon™ XP Processor Model 8

Specifications” on page 27, Table 5, “Electrical and Thermal Specifications,” on page 27,

Table 6, “SYSCLK and SYSCLK# AC Characteristics,” on page 28, Figure 9, “SYSCLK

Waveform,” on page 28, and Table 7, “AMD Athlon™ System Bus AC Characteristics,” on

page 29.

October 2002

D

■

In Chapter 8, revised Table 8, “Interface Signal Groupings,” on page 31, Table 9, “VID[4:0]

DC Characteristics,” on page 33, Table 10, “FID[3:0] DC Characteristics,” on page 33, and

Table 19, “APIC Pin AC and DC Characteristics,” on page 44.

In Chapter 10, revised Table 21, “Part Number 27291 OPGA Package Dimensions for

AMD Athlon™ XP Processors Model 8 with a CPUID of 680,” on page 50 and Table 22, “Part

Number 27291 OPGA Package Dimensions for AMD Athlon™ XP Processors Model 8 with a

CPUID of 681,” on page 51.

■

In Chapter 12, revised Figure 18, “OPN Example for the AMD Athlon™ XP Processor Model

8,” on page 81.

Public revision C of the AMD Athlon™ XP Processor Model 8 Data Sheet includes the following

changes:

■

In Chapter 3, revised Figure 2, “Logic Symbol Diagram,” on page 7.

In Chapter 6, added Table 1, “Electrical and Thermal Specifications for Processors with a

CPUID of 680,” on page 22 and Table 2, “Electrical and Thermal Specifications for

Processors with a CPUID of 681,” on page 23.

■

In Chapter 8, revised Table 8, “Interface Signal Groupings,” on page 31.

In Chapter 10, added Table 21, “Part Number 27291 OPGA Package Dimensions for

AMD Athlon™ XP Processors Model 8 with a CPUID of 680,” on page 50 and Table 22, “Part

Number 27291 OPGA Package Dimensions for AMD Athlon™ XP Processors Model 8 with a

CPUID of 681,” on page 51.

August 2002

C

■

In Chapter 11, revised Figure 16, “AMD Athlon™ XP Processor Model 8 Pin Diagram—

Topside View,” on page 56, Figure 17, “AMD Athlon™ XP Processor Model 8 Pin Diagram—

Bottomside View,” on page 57, Table 24, “Pin Name Abbreviations,” on page 58, Table 25,

“Cross-Reference by Pin Location,” on page 66, and added “FSB_Sense[1:0] Pins” on page

77, and Table 27, “Front-Side Bus Sense Truth Table,” on page 77.

■

In Chapter 12, revised Figure 18, “OPN Example for the AMD Athlon™ XP Processor Model

8,” on page 81.

June 2002

B

First public release of the AMD Athlon™ XP Processor Model 8 Data Sheet

12

Revision History

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

1

Overview

The AMD Athlon™ XP processor model 8 with QuantiSpeed™

architecture powers the next generation in computing platforms,

®

delivering extreme performance for Windows XP.

The AMD Athlon™ XP processor model 8, based on leading-

edge 0.13 micron technology, integrates the innovative design

and manufacturing expertise of AMD to deliver improved

performance, lower power, and smaller die size while

maintaining the stable and compatible Socket A infrastructure

of the AMD Athlon processor.

Delivered in an OPGA package, the AMD Athlon XP processor

model 8 delivers the integer, floating-point, and 3D multimedia

performance for highly demanding applications running on x86

system platforms. The AMD Athlon XP processor model 8

delivers compelling performance for cutting-edge software

applications that include high-speed Internet capability, digital

content creation, digital photo editing, digital video, image

compression, video encoding for streaming over the Internet,

soft DVD, commercial 3D modeling, workstation-class

computer-aided design (CAD), commercial desktop publishing,

and speech recognition. The AMD Athlon XP processor model 8

also offers the scalability and reliability that IT managers and

business users require for enterprise computing.

The AMD Athlon XP processor model 8 features a

seventh-generation microarchitecture with an integrated,

exclusive L2 cache, which supports the growing processor and

system bandwidth requirements of emerging software,

graphics, I/O, and memory technologies. The high-speed

execution core of the AMD Athlon XP processor model 8

includes multiple x86 instruction decoders, a dual-ported

128-Kbyte split level-one (L1) cache, an exclusive 256-Kbyte L2

cache, three independent integer pipelines, three address

calculation pipelines, and a superscalar, fully pipelined,

out-of-order, three-way floating-point engine. The floating-point

engine is capable of delivering outstanding performance on

numerically complex applications.

Chapter 1

Overview

1

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

The features of the AMD Athlon XP processor model 8 are

QuantiSpeed™ architecture, a high-performance full-speed cache,

an advanced 333 front-side Bus (FSB) with a 2.7-Gigabyte per

second system bus, or an advanced 266 FSB with a 2.1-Gigabyte per

second system bus, and 3DNow!™ Professional technology. The

AMD Athlon system bus combines the latest technological

advances, such as point-to-point topology, source-synchronous

packet-based transfers, and low-voltage signaling to provide an

extremely powerful, scalable bus for an x86 processor.

The AMD Athlon XP processor model 8 is binary-compatible with

existing x86 software and backwards compatible with applications

optimized for MMX™, SSE, and 3DNow! technology. Using a data

format and single-instruction multiple-data (SIMD) operations

based on the MMX instruction model, the AMD Athlon XP

processor model 8 can produce as many as four, 32-bit,

single-precision floating-point results per clock cycle. The 3DNow!

Professional technology implemented in the AMD Athlon XP

processor model 8 includes new integer multimedia instructions

and software-directed data movement instructions for optimizing

such applications as digital content creation and streaming video

for the internet, as well as new instructions for digital signal

processing (DSP) and communications applications.

1.1

QuantiSpeed™ Architecture Summary

The following features summarize the AMD Athlon XP

processor model 8 QuantiSpeed architecture:

■

Advanced 333 FSB technology available

An advanced nine-issue, superpipelined, superscalar x86

processor microarchitecture designed for increased instructions

per cycle (IPC) and high clock frequencies

■

Fully pipelined floating-point unit that executes all x87

(floating-point), MMX, SSE and 3DNow! instructions

Hardware data pre-fetch that increases and optimizes

performance on high-end software applications utilizing high-

bandwidth system capabilities

■

Advanced two-level translation look-aside buffer (TLB)

structures for both enhanced data and instruction address

translation. The AMD Athlon XP processor model 8 with

QuantiSpeed

architecture

incorporates

three

TLB

optimizations: the L1 DTLB increases from 32 to 40 entries, the

L2 ITLB and L2 DTLB both use exclusive architecture, and the

TLB entries can be speculatively loaded.

2

Overview

Chapter 1

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

The AMD Athlon XP processor model 8 delivers excellent

system performance in a cost-effective, industry-standard form

factor. The AMD Athlon XP processor model 8 is compatible

with motherboards based on Socket A.

Figure 1 shows a typical AMD Athlon XP processor model 8

system block diagram.

Thermal Monitor

AMD Athlon™ XP

Processor Model 8

AMD Athlon System Bus

AGP

AGP Bus

Memory Bus

System Controller

(Northbridge)

SDRAM or DDR

PCI Bus

Peripheral Bus

Controller

(Southbridge)

LAN

SCSI

Modem / Audio

LPC Bus

USB

Dual EIDE

BIOS

Figure 1. Typical AMD Athlon™ XP Processor Model 8 System Block Diagram

Chapter 1

Overview

3

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

4

Overview

Chapter 1

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

2

Interface Signals

This section describes the interface signals utilized by the

AMD Athlon™ XP processor model 8.

2.1

Overview

The AMD Athlon™ system bus architecture is designed to

deliver excellent data movement bandwidth for next-

generation x86 platforms as well as the high-performance

required by enterprise-class application software. The system

bus architecture consists of three high-speed channels (a

unidirectional processor request channel, a unidirectional

probe channel, and a 64-bit bidirectional data channel),

source-synchronous clocking, and a packet-based protocol. In

addition, the system bus supports several control, clock, and

legacy signals. The interface signals use an impedance

controlled push-pull, low-voltage, swing-signaling technology

contained within the Socket A socket.

For more information, see “AMD Athlon™ System Bus Signals”

on page 6, Chapter 11, “Pin Descriptions” on page 55, and the

AMD Athlon™ System Bus Specification, order# 21902.

2.2

Signaling Technology

The AMD Athlon system bus uses a low-voltage, swing-signaling

technology, that has been enhanced to provide larger noise

margins, reduced ringing, and variable voltage levels. The

signals are push-pull and impedance compensated. The signal

inputs use differential receivers that require a reference

voltage (V

). The reference signal is used by the receivers to

REF

determine if a signal is asserted or deasserted by the source.

Termination resistors are not needed because the driver is

impedance-matched to the motherboard and a high impedance

reflection is used at the receiver to bring the signal past the

input threshold.

For more information about pins and signals, see Chapter 11,

“Pin Descriptions” on page 55.

Chapter 2

Interface Signals

5

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

2.3

Push-Pull (PP) Drivers

The AMD Athlon XP processor model 8 supports push-pull (PP)

drivers. The system logic configures the processor with the

configuration parameter called SysPushPull (1=PP). The

impedance of the PP drivers is set to match the impedance of

the motherboard by two external resistors connected to the ZN

and ZP pins.

See “ZN and ZP Pins” on page 80 for more information.

2.4

AMD Athlon™ System Bus Signals

The AMD Athlon system bus is a clock-forwarded, point-to-

point interface with the following three point-to-point channels:

■ A 13-bit unidirectional output address/command channel

■ A 13-bit unidirectional input address/command channel

■ A 72-bit bidirectional data channel

For more information, see Chapter 8, “Electrical Data” on page

31 and the AMD Athlon™ System Bus Specification, order#

21902.

6

Interface Signals

Chapter 2

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

3

Logic Symbol Diagram

Figure 2 is the logic symbol diagram of the processor. This

diagram shows the logical grouping of the input and output

signals.

Clock

SYSCLK

SYSCLK#

VID[4:0]

COREFB

COREFB#

PWROK

SDATA[63:0]#

{

SDATAINCLK[3:0]#

SDATAOUTCLK[3:0]#

SDATAINVALID#

SDATAOUTVALID#

SFILLVALID#

Voltage

Control

Data

{

Frequency

Control

FID[3:0]

Front-Side Bus

Autodetect

FSB_SENSE[1:0]

SADDIN[14:2]#

SADDINCLK#

Probe/SysCMD

{

FERR

IGNNE#

INIT#

INTR

NMI

A20M#

SMI#

FLUSH#

AMD Athlon™ XP

Processor Model 8

{

SADDOUT[14:2]#

SADDOUTCLK#

Request

Legacy

PROCRDY

CLKFWDRST

CONNECT

STPCLK#

RESET#

Power

Management

and Initialization

{

Thermal

Diode

THERMDA

THERMDC

{

PICCLK

PICD[1:0]

APIC

Figure 2. Logic Symbol Diagram

Chapter 3

Logic Symbol Diagram

7

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

8

Logic Symbol Diagram

Chapter 3

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

4

Power Management

This chapter describes the power management control system

of the AMD Athlon™ XP processor model 8. The power

management features of the processor are compliant with the

ACPI 1.0b and ACPI 2.0 specifications.

4.1

Power Management States

The AMD Athlon XP processor model 8 supports low-power

Halt and Stop Grant states. These states are used by advanced

configuration and power interface (ACPI) enabled operating

systems for processor power management.

Figure 3 shows the power management states of the processor.

The figure includes the ACPI “Cx” naming convention for these

states.

Execute HLT

C1

Halt

C0

Working⁴

SMI#, INTR, NMI, INIT#, RESET#

S1

Incoming Probe

Probe Serviced

C2

Probe

State¹

Stop Grant

Cache Not Snoopable

Sleep

Stop Grant

Cache Snoopable

Legend

Hardware transitions

Software transitions

Note:

The AMD Athlon^TMSystem Bus is connected during the following states:

1) The Probe state

2) During transitions between the Halt state and the C2 Stop Grant state

3) During transitions between the C2 Stop Grant state and the Halt state

4) C0 Working state

Figure 3. AMD Athlon™ XP Processor Model 8 Power Management States

Chapter 4 Power Management

9

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

The following sections provide an overview of the power

management states. For more details, refer to the

AMD Athlon™ System Bus Specification, order# 21902.

Note: In all power management states that the processor is

powered, the system must not stop the system clock

(SYSCLK/SYSCLK#) to the processor.

Working State

Halt State

The Working state is the state in which the processor is

executing instructions.

When the processor executes the HLT instruction, the processor

enters the Halt state and issues a Halt special cycle to the

AMD Athlon system bus. The processor only enters the low

power state dictated by the CLK_Ctl MSR if the system

controller (Northbridge) disconnects the AMD Athlon system

bus in response to the Halt special cycle.

If STPCLK# is asserted, the processor will exit the Halt state

and enter the Stop Grant state. The processor will initiate a

system bus connect, if it is disconnected, then issue a Stop

Grant special cycle. When STPCLK# is deasserted, the

processor will exit the Stop Grant state and re-enter the Halt

state. The processor will issue a Halt special cycle when

re-entering the Halt state.

The Halt state is exited when the processor detects the

assertion of INIT#, RESET#, SMI#, or an interrupt via the INTR

or NMI pins, or via a local APIC interrupt message. When the

Halt state is exited, the processor will initiate an AMD Athlon

system bus connect if it is disconnected.

Stop Grant States

The processor enters the Stop Grant state upon recognition of

assertion of STPCLK# input. After entering the Stop Grant

state, the processor issues a Stop Grant special bus cycle on the

AMD Athlon system bus. The processor is not in a low-power

state at this time, because the AMD Athlon system bus is still

connected. After the Northbridge disconnects the AMD Athlon

system bus in response to the Stop Grant special bus cycle, the

processor enters a low-power state dictated by the CLK_Ctl

MSR. If the Northbridge needs to probe the processor during

the Stop Grant state while the system bus is disconnected, it

must first connect the system bus. Connecting the system bus

10

Power Management

Chapter 4

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

places the processor into the higher power probe state. After

the Northbridge has completed all probes of the processor, the

Northbridge must disconnect the AMD Athlon system bus

again so that the processor can return to the low-power state.

During the Stop Grant states, the processor latches INIT#,

INTR, NMI, SMI#, or a local APIC interrupt message, if they are

asserted.

The Stop Grant state is exited upon the deassertion of

STPCLK# or the assertion of RESET#. When STPCLK# is

deasserted, the processor initiates a connect of the

AMD Athlon system bus if it is disconnected. After the

processor enters the Working state, any pending interrupts are

recognized and serviced and the processor resumes execution

at the instruction boundary where STPCLK# was initially

recognized. If RESET# is sampled asserted during the Stop

Grant state, the processor exits the Stop Grant state and the

reset process begins.

There are two mechanisms for asserting STPCLK#—hardware

and software.

The Southbridge can force STPCLK# assertion for throttling to

protect the processor from exceeding its maximum case

temperature. This is accomplished by asserting the THERM#

input to the Southbridge. Throttling asserts STPCLK# for a

percentage of a predefined throttling period: STPCLK# is

repetitively asserted and deasserted until THERM# is

deasserted.

Software can force the processor into the Stop Grant state by

accessing ACPI-defined registers typically located in the

Southbridge.

The operating system places the processor into the C2 Stop

Grant state by reading the P_LVL2 register in the Southbridge.

If an ACPI Thermal Zone is defined for the processor, the

operating system can initiate throttling with STPCLK# using

the ACPI defined P_CNT register in the Southbridge. The

Northbridge connects the AMD Athlon system bus, and the

processor enters the Probe state to service cache snoops during

Stop Grant for C2 or throttling.

In C2, probes are allowed, as shown in Figure 3 on page 9

Chapter 4

Power Management

11

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

The Stop Grant state is also entered for the S1, Powered On

Suspend, system sleep state based on a write to the SLP_TYP

and SLP_EN fields in the ACPI-defined Power Management 1

control register in the Southbridge. During the S1 Sleep state,

system software ensures no bus master or probe activity occurs.

The Southbridge deasserts STPCLK# and brings the processor

out of the S1 Stop Grant state when any enabled resume event

occurs.

Probe State

The Probe state is entered when the Northbridge connects the

AMD Athlon system bus to probe the processor (for example, to

snoop the processor caches) when the processor is in the Halt or

Stop Grant state. When in the Probe state, the processor

responds to a probe cycle in the same manner as when it is in

the Working state. When the probe has been serviced, the

processor returns to the same state as when it entered the

Probe state (Halt or Stop Grant state). When probe activity is

completed the processor only returns to a low-power state after

the Northbridge disconnects the AMD Athlon system bus again.

4.2

Connect and Disconnect Protocol

Significant power savings of the processor only occur if the

processor is disconnected from the system bus by the

Northbridge while in the Halt or Stop Grant state. The

Northbridge can optionally initiate a bus disconnect upon the

receipt of a Halt or Stop Grant special cycle. The option of

disconnecting is controlled by an enable bit in the Northbridge.

If the Northbridge requires the processor to service a probe

after the system bus has been disconnected, it must first

initiate a system bus connect.

Connect Protocol

In addition to the legacy STPCLK# signal and the Halt and Stop

Grant special cycles, the AMD Athlon system bus connect

protocol includes the CONNECT, PROCRDY, and CLKFWDRST

signals and a Connect special cycle.

AMD Athlon system bus disconnects are initiated by the

Northbridge in response to the receipt of a Halt or Stop Grant.

Reconnect is initiated by the processor in response to an

interrupt for Halt or STPCLK# deassertion. Reconnect is

initiated by the Northbridge to probe the processor.

12

Power Management

Chapter 4

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

The Northbridge contains BIOS programmable registers to

enable the system bus disconnect in response to Halt and Stop

Grant special cycles. When the Northbridge receives the Halt or

Stop Grant special cycle from the processor and, if there are no

outstanding probes or data movements, the Northbridge

deasserts CONNECT a minimum of eight SYSCLK periods after

the last command sent to the processor. The processor detects

the deassertion of CONNECT on a rising edge of SYSCLK and

deasserts PROCRDY to the Northbridge. In return, the

Northbridge asserts CLKFWDRST in anticipation of

reestablishing a connection at some later point.

Note: The Northbridge must disconnect the processor from the

AMD Athlon system bus before issuing the Stop Grant

special cycle to the PCI bus or passing the Stop Grant special

cycle to the Southbridge for systems that connect to the

Southbridge with HyperTransport™ technology.

This note applies to current chipset implementation—

alternate chipset implementations that do not require this

are possible.

Note: In response to Halt special cycles, the Northbridge passes the

Halt special cycle to the PCI bus or Southbridge

immediately.

The processor can receive an interrupt after it sends a Halt

special cycle, or STPCLK# deassertion after it sends a Stop

Grant special cycle to the Northbridge but before the

disconnect actually occurs. In this case, the processor sends the

Connect special cycle to the Northbridge, rather than

continuing with the disconnect sequence. In response to the

Connect special cycle, the Northbridge cancels the disconnect

request.

The system is required to assert the CONNECT signal before

returning the C-bit for the connect special cycle (assuming

CONNECT has been deasserted).

For more information, see the AMD Athlon™ System Bus

Specification, order# 21902 for the definition of the C-bit and

the Connect special cycle.

Chapter 4

Power Management

13

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

Figure 4 shows STPCLK# assertion resulting in the processor in

the Stop Grant state and the AMD Athlon system bus

disconnected.

STPCLK#

AMD Athlon™

System Bus

Stop Grant

CONNECT

PROCRDY

CLKFWDRST

PCI Bus

Stop Grant

Figure 4. AMD Athlon™ System Bus Disconnect Sequence in the Stop Grant State

An example of the AMD Athlon system bus disconnect

sequence is as follows:

1. The peripheral controller (Southbridge) asserts STPCLK#

to place the processor in the Stop Grant state.

2. When the processor recognizes STPCLK# asserted, it enters

the Stop Grant state and then issues a Stop Grant special

cycle.

3. When the special cycle is received by the Northbridge, it

deasserts CONNECT, assuming no probes are pending,

initiating a bus disconnect to the processor.

4. The processor responds to the Northbridge by deasserting

PROCRDY.

5. The Northbridge asserts CLKFWDRST to complete the bus

disconnect sequence.

6. After the processor is disconnected from the bus, the

processor enters a low-power state. The Northbridge passes

the Stop Grant special cycle along to the Southbridge.

14

Power Management

Chapter 4

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

Figure 5 shows the signal sequence of events that takes the

processor out of the Stop Grant state, connects the processor to

the AMD Athlon system bus, and puts the processor into the

Working state.

STPCLK#

PROCRDY

CONNECT

CLKFWDRST

Figure 5. Exiting the Stop Grant State and Bus Connect Sequence

The following sequence of events removes the processor from

the Stop Grant state and connects it to the system bus:

1. The Southbridge deasserts STPCLK#, informing the

processor of a wake event.

2. When the processor recognizes STPCLK# deassertion, it

exits the low-power state and asserts PROCRDY, notifying

the Northbridge to connect to the bus.

3. The Northbridge asserts CONNECT.

4. The Northbridge deasserts CLKFWDRST, synchronizing the

forwarded clocks between the processor and the

Northbridge.

5. The processor issues a Connect special cycle on the system

bus and resumes operating system and application code

execution.

Chapter 4

Power Management

15

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

Connect State

Diagram

Figure 6 below and Figure 7 on page 17 show the Northbridge

and processor connect state diagrams, respectively.

4/A

1

2/A

Disconnect

Pending

Disconnect

Requested

Connect

3/C

3

5/B

8

Reconnect

Pending

Probe

Pending 2

Disconnect

7/D,C

6/C

7/D

Probe

Pending 1

Condition

Action

1 A disconnect is requested and probes are still pending.

2 A disconnect is requested and no probes are pending.

3 A Connect special cycle from the processor.

4 No probes are pending.

Deassert CONNECT eight SYSCLK periods

after last SysDC sent.

A

B Assert CLKFWDRST.

C Assert CONNECT.

D Deassert CLKFWDRST.

5 PROCRDY is deasserted.

6 A probe needs service.

7 PROCRDY is asserted.

Three SYSCLK periods after CLKFWDRST is deasserted.

Although reconnected to the system interface, the

8

Northbridge must not issue any non-NOP SysDC

commands for a minimum of four SYSCLK periods after

deasserting CLKFWDRST.

Figure 6. Northbridge Connect State Diagram

16 Power Management

Chapter 4

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

Connect

6/B

1

2/B

Connect

Pending 2

Disconnect

Pending

5

Connect

Pending 1

3/A

Disconnect

4/C

Condition

Action

CONNECT is deasserted by the Northbridge (for a

previously sent Halt or Stop Grant special cycle).

A CLKFWDRST is asserted by the Northbridge.

B Issue a Connect special cycle.*

1

2

Processor receives a wake-up event and must cancel

the disconnect request.

Return internal clocks to full speed and assert

C

PROCRDY.

3 Deassert PROCRDY and slow down internal clocks.

Note:

*

The Connect special cycle is only issued after a

processor wake-up event (interrupt or STPCLK#

deassertion) occurs. If the AMD Athlon™ system

bus is connected so the Northbridge can probe the

processor, a Connect special cycle is not issued at

that time (it is only issued after a subsequent

processor wake-up event).

Processor wake-up event or CONNECT asserted by

Northbridge.

4

5 CLKFWDRST is deasserted by the Northbridge.

Forward clocks start three SYSCLK periods after

CLKFWDRST is deasserted.

6

Figure 7. Processor Connect State Diagram

Chapter 4

Power Management

17

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

4.3

Clock Control

The processor implements a Clock Control (CLK_Ctl) MSR

(address C001_001Bh) that determines the internal clock

divisor when the AMD Athlon system bus is disconnected.

Refer to the AMD Athlon™ and AMD Duron™ Processors BIOS,

Software, and Debug Developers Guide, order# 21656, for more

details on the CLK_Ctl register.

18

Power Management

Chapter 4

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

5

CPUID Support

AMD Athlon™ XP processor model 8 version and feature set

recognition can be performed through the use of the CPUID

instruction, that provides complete information about the

processor—vendor, type, name, etc., and its capabilities.

Software can make use of this information to accurately tune

the system for maximum performance and benefit to users.

For information on the use of the CPUID instruction see the

following documents:

■ AMD Processor Recognition Application Note, order# 20734

■ AMD Athlon™ Processor Recognition Application Note

Addendum, order# 21922

■ AMD Athlon™ and AMD Duron™ Processors BIOS, Software,

and Debug Developers Guide, order# 21656

Chapter 5

CPUID Support

19

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

20

CPUID Support

Chapter 5

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

6

Advanced 266 Front-Side Bus AMD Athlon™ XP

Processor Model 8 Specifications

This chapter describes the electrical specifications that are

unique to the advanced 266 front-side bus (FSB) AMD Athlon™

XP processor model 8.

6.1

Part-Specific Electrical and Thermal Specifications for

Advanced 266 FSB AMD Athlon™ XP Processors Model 8

This section provides part-specific electrical and thermal

information for each type of the Advanced 266 FSB

AMD Athlon XP processors model 8 in Table 1 on page 22 and

Table 2 on page 23.

Chapter 6

Advanced 266 Front-Side Bus AMD Athlon™ XP Processor Model 8 Specifications

21

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

Table 1 shows the part-specific electrical and thermal

specifications in the C0 working state and the S1 Stop Grant

state for processors with a CPUID = 680.

Table 1. Electrical and Thermal Specifications for Processors with a CPUID of 680

I

_CC(Processor Current)

Working State C0

Maximum Typical Maximum Typical Maximum Typical

V_{CC_CORE}

(Core

Voltage)

Thermal Power⁵

Frequency in MHz

(Model Number)

Maximum Die

Temperature

Stop Grant S1^{1, 2, 3, 4}

32.9 A

34.0 A

35.0 A

29.9 A

30.9 A

31.8 A

49.4 W

51.0 W

52.5 W

44.9 W

46.3 W

47.7 W

1467 (1700+)

1533 (1800+)

1600 (1900+)

1.50 V

5.87 A

3.7 A

90°C

85°C

1.60 V

1.65 V

37.7 A

36.5 A

34.2 A

33.2 A

7.68 A

8.85 A

4.7 A

5.4 A

60.3 W

54.7 W

1667 (2000+)

1733 (2100+)

1.60 V

1.65 V

38.8 A

41.2 A

35.2 A

37.4 A

7.68 A

8.85 A

4.7 A

5.4 A

62.1 W

67.9 W

56.4 W

61.7 W

1800 (2200+)

Notes:

1. See Figure 3, "AMD Athlon™ XP Processor Model 8 Power Management States" on page 9.

2. The maximum Stop Grant currents are absolute worst case currents for parts that may yield from the worst case corner of the

process and are not representative of the typical Stop Grant current that is currently about one-third of the maximum specified

current.

3. These currents occur when the AMD Athlon™ system bus is disconnected and has a low power ratio of 1/8 for Stop Grant

disconnect and a low power ratio of 1/8 Halt disconnect applied to the core clock grid of the processor as dictated by a value of

6003_1223h programmed into the Clock Control (CLK_Ctl) MSR. For more information, refer to the AMD Athlon™ and

AMD Duron™ Processors BIOS, Software, and Debug Developers Guide, order# 21656.

4. The Stop Grant current consumption is characterized at 50°C and not tested.

5. Thermal design power represents the maximum sustained power dissipated while executing publicly-available software or

instruction sequences under normal system operation at nominal V

. Thermal solutions must monitor the temperature of

CC_CORE

the processor to prevent the processor from exceeding its maximum die temperature.

22

Advanced 266 Front-Side Bus AMD Athlon™ XP Processor Model 8 Specifications

Chapter 6

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

6.2

Advanced 266 FSB AMD Athlon™ XP Processor Model 8

SYSCLK and SYSCLK# AC Characteristics

Table 3 shows the SYSCLK/SYSCLK# differential clock AC

characteristics of this processor.

.

Table 3. SYSCLK and SYSCLK# AC Characteristics

Symbol

Parameter Description

Clock Frequency

Minimum

Maximum

Units

Notes

50

30%

7.5

133

MHz

1

Duty Cycle

70%

t₁

t₂

t₃

t₄

t₅

Period

ns

ps

2, 3

High Time

Low Time

Fall Time

1.05

2

Rise Time

Period Stability

± 300

Notes:

1. The AMD Athlon™ system bus operates at twice this clock frequency.

2. Circuitry driving the AMD Athlon system bus clock inputs must exhibit a suitably low closed-loop jitter bandwidth to allow the PLL

to track the jitter. The –20dB attenuation point, as measured into a 20- or 30-pF load must be less than 500 kHz.

3. Circuitry driving the AMD Athlon system bus clock inputs may purposely alter the AMD Athlon system bus clock frequency (spread

spectrum clock generators). In no cases can the AMD Athlon system bus period violate the minimum specification above.

AMD Athlon system bus clock inputs can vary from 100% of the specified frequency to 99% of the specified frequency at a

maximum rate of 100 kHz.

Figure 8 shows a sample waveform of the SYSCLK signal.

t₂

V_Threshold-AC

V_CROSS

t₃

t₄

t₅

t₁

Figure 8. SYSCLK Waveform

24 Advanced 266 Front-Side Bus AMD Athlon™ XP Processor Model 8 Specifications

Chapter 6

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

6.3

Advanced 266 FSB AMD Athlon™ System Bus

AC Characteristics

The AC characteristics for the AMD Athlon system bus of this

processor are shown in Table 4. The parameters are grouped

based on the source or destination of the signals involved.

Table 4. AMD Athlon™ System Bus AC Characteristics

Group

Symbol

Parameter

Output Rise Slew Rate

Output Fall Slew Rate

Min

1

Max

Units Notes

T_RISE

T_FALL

3

V/ns

1

All Signals

1

Output skew with respect to

the same clock edge

T_{SKEW-SAMEEDGE}

T_{SKEW-DIFFEDGE}

–

385

770

ps

2

Output skew with respect to a

different clock edge

Forward

Clocks

T_SU

Input Data Setup Time

Input Data Hold Time

Capacitance on input Clocks

Capacitance on output Clocks

RSTCLK to Output Valid

Setup to RSTCLK

300

4

ps

pF

ps

3

T_HD

C_IN

25

12

C_OUT

T_VAL

T_SU

4

250

500

1000

2000

4, 5

4, 6

Sync

T_HD

Hold from RSTCLK

Notes:

1. Rise and fall time ranges are guidelines over which the I/O has been characterized.

2. T is the maximum skew within a clock forwarded group between any two signals or between any signal and its

SKEW-SAMEEDGE

forward clock, as measured at the package, with respect to the same clock edge.

is the maximum skew within a clock forwarded group between any two signals or between any signal and its

T

SKEW-DIFFEDGE

forward clock, as measured at the package, with respect to different clock edges.

3. Input SU and HD times are with respect to the appropriate Clock Forward Group input clock.

4. The synchronous signals include PROCRDY, CONNECT, and CLKFWDRST.

5. T is RSTCLK rising edge to output valid for PROCRDY. Test Load is 25 pF.

VAL

6. T is setup of CONNECT/CLKFWDRST to rising edge of RSTCLK. T is hold of CONNECT/CLKFWDRST from rising edge of

SU

HD

RSTCLK.

Chapter 6

Advanced 266 Front-Side Bus AMD Athlon™ XP Processor Model 8 Specifications

25

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

26

Advanced 266 Front-Side Bus AMD Athlon™ XP Processor Model 8 Specifications

Chapter 6

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

7

Advanced 333 Front-Side Bus AMD Athlon™ XP

Processor Model 8 Specifications

This chapter describes the electrical specifications that are

unique to the advanced 333 front-side bus (FSB) AMD Athlon™

XP processor model 8.

7.1

Electrical and Thermal Specifications for the Advanced 333 FSB

AMD Athlon™ XP Processor Model 8

Table 5 shows the electrical and thermal specifications for this

processor in the C0 working state and the S1 Stop Grant state.

Table 5. Electrical and Thermal Specifications

I

_CC(Processor Current)

V_{CC_CORE}

(Core

Voltage)

Thermal Power⁵

Frequency in MHz

(Model Number)

Maximum Die

Temperature

Stop Grant S1^{1, 2, 3, 4}

Working State C0

Maximum Typical Maximum Typical Maximum Typical

2083 (2600+)

1.65 V

41.4 A 37.6 A 8.9 A 5.9 A 68.3 W 62.0 W

85°C

2167 (2700+)

Notes:

1. See Figure 3, "AMD Athlon™ XP Processor Model 8 Power Management States" on page 9.

2. The maximum Stop Grant currents are absolute worst case currents for parts that may yield from the worst case corner of the

process and are not representative of the typical Stop Grant current that is currently about one-third of the maximum specified

current.

3. These currents occur when the AMD Athlon™ system bus is disconnected and has a low power ratio of 1/8 for Stop Grant

disconnect and a low power ratio of 1/8 Halt disconnect applied to the core clock grid of the processor as dictated by a value of

2003_1223h programmed into the Clock Control (CLK_Ctl) MSR. For more information, refer to the AMD Athlon™ and

AMD Duron™ Processors BIOS, Software, and Debug Developers Guide, order# 21656.

4. The Stop Grant current consumption is characterized at 50°C and not tested.

5. Thermal design power represents the maximum sustained power dissipated while executing publicly-available software or

instruction sequences under normal system operation at nominal V

. Thermal solutions must monitor the temperature of

CC_CORE

the processor to prevent the processor from exceeding its maximum die temperature.

Chapter 7

Advanced 333 Front-Side Bus AMD Athlon™ XP Processor Model 8 Specifications

27

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

7.2

Advanced 333 FSB AMD Athlon™ XP Processor Model 8

SYSCLK and SYSCLK# AC Characteristics

Table 6 shows the SYSCLK/SYSCLK# differential clock AC

characteristics of this processor.

Table 6. SYSCLK and SYSCLK# AC Characteristics

Symbol

Parameter Description

Clock Frequency

Minimum

Maximum

Units

Notes

50

30%

6

166

MHz

1

Duty Cycle

70%

t₁

t₂

t₃

t₄

t₅

Period

ns

ps

2, 3

High Time

Low Time

Fall Time

1.0

2

Rise Time

Period Stability

± 300

Notes:

1. The AMD Athlon™ system bus operates at twice this clock frequency.

2. Circuitry driving the AMD Athlon system bus clock inputs must exhibit a suitably low closed-loop jitter bandwidth to allow the PLL

to track the jitter. The –20dB attenuation point, as measured into a 20- or 30-pF load must be less than 500 kHz.

3. Circuitry driving the AMD Athlon system bus clock inputs may purposely alter the AMD Athlon system bus clock frequency (spread

spectrum clock generators). In no cases can the AMD Athlon system bus period violate the minimum specification above.

AMD Athlon system bus clock inputs can vary from 100% of the specified frequency to 99% of the specified frequency at a

maximum rate of 100 kHz.

Figure 9 shows a sample waveform of the SYSCLK signal.

t₂

V_Threshold-AC

V_CROSS

t₃

t₄

t₅

t₁

Figure 9. SYSCLK Waveform

28 Advanced 333 Front-Side Bus AMD Athlon™ XP Processor Model 8 Specifications

Chapter 7

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

7.3

Advanced 333 FSB AMD Athlon™ System Bus

AC Characteristics

The AC characteristics of the AMD Athlon system bus of this

processor are shown in Table 7. The parameters are grouped

based on the source or destination of the signals involved.

Table 7. AMD Athlon™ System Bus AC Characteristics

Group

Symbol

Parameter

Output Rise Slew Rate

Output Fall Slew Rate

Min

1

Max

Units Notes

T_RISE

T_FALL

3

V/ns

1

All Signals

1

Output skew with respect to a

different clock edge

T_{SKEW-DIFFEDGE}

–

770

ps

2

T_SU

Input Data Setup Time

Input Data Hold Time

Capacitance on input Clocks

Capacitance on output Clocks

RSTCLK to Output Valid

Setup to RSTCLK

300

4

ps

pF

ps

3

Forward

Clocks

T_HD

C_IN

25

12

C_OUT

T_VAL

T_SU

4

800

500

2000

4, 5

4, 6

Sync

T_HD

Hold from RSTCLK

Notes:

1. Rise and fall time ranges are guidelines over which the I/O has been characterized.

2. T is the maximum skew within a clock forwarded group between any two signals or between any signal and its

SKEW-DIFFEDGE

forward clock, as measured at the package, with respect to different clock edges.

3. Input SU and HD times are with respect to the appropriate Clock Forward Group input clock.

4. The synchronous signals include PROCRDY, CONNECT, and CLKFWDRST.

5. T is RSTCLK rising edge to output valid for PROCRDY. Test Load is 25 pF.

VAL

6. T is setup of CONNECT/CLKFWDRST to rising edge of RSTCLK. T is hold of CONNECT/CLKFWDRST from rising edge of

SU

HD

RSTCLK.

Chapter 7

Advanced 333 Front-Side Bus AMD Athlon™ XP Processor Model 8 Specifications

29

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

30

Advanced 333 Front-Side Bus AMD Athlon™ XP Processor Model 8 Specifications

Chapter 7

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

8

Electrical Data

This chapter describes the electrical characteristics that apply

to all desktop AMD Athlon™ XP processors model 8.

8.1

Conventions

The conventions used in this chapter are as follows:

■ Current specified as being sourced by the processor is

negative.

■ Current specified as being sunk by the processor is positive.

8.2

Interface Signal Groupings

The electrical data in this chapter is presented separately for

each signal group.

Table 8 defines each group and the signals contained in each

group.

Table 8. Interface Signal Groupings

Signal Group

Signals

Notes

See “Advanced 266 FSB

AMD Athlon™ System Bus AC

SADDIN[14:2]#, SADDOUT[14:2]#, SADDINCLK#, SADDOUTCLK#, Characteristics” on page 25,

AMD Athlon™ SFILLVAL#, SDATAINVAL#, SDATAOUTVAL#, SDATA[63:0]#, “Advanced 333 FSB AMD Athlon™

SDATAINCLK[3:0]#, SDATAOUTCLK[3:0]#, CLKFWDRST, PROCRDY, System Bus AC Characteristics” on

System Bus

APIC

CONNECT

page 29, “AMD Athlon™ System

Bus DC Characteristics” on page 36,

and “CLKFWDRST Pin” on page 73.

See “APIC Pins AC and DC

Characteristics” on page 44, and

“APIC Pins, PICCLK, PICD[1:0]#” on

page 73.

PICD[1:0]#, PICCLK

See “Frequency Identification

(FID[3:0])” on page 33, “FID[3:0]

Pins” on page 75, and

Frequency

JTAG

FID[3:0], FSB_Sense[1:0]

“FSB_Sense[1:0] Pins” on page 76.

See “General AC and DC

Characteristics” on page 39.

TMS, TCK, TRST#, TDI, TDO

Chapter 8

Electrical Data

31

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

Table 8. Interface Signal Groupings (continued)

Signal Group

Signals

Notes

See “Voltage Identification

(VID[4:0])” on page 33, “VID[4:0]

Pins” on page 78,“VCCA AC and DC

Characteristics” on page 33,

VID[4:0], VCCA, V_{CC_CORE}, COREFB, COREFB#

Power

“V_{CC_CORE}Characteristics” on page

34,“VCCA Pin” on page 78, and

“COREFB and COREFB# Pins” on

page 74.

See “General AC and DC

Characteristics” on page 39, “INTR

Pin” on page 76, “NMI Pin” on page

77, “SMI# Pin” on page 78, “INIT#

Pin” on page 76, “A20M# Pin” on

page 73, “FERR Pin” on page

74,“IGNNE# Pin” on page 76,

“STPCLK# Pin” on page 79, and

“FLUSH# Pin” on page 77.

RESET#, INTR, NMI, SMI#, INIT#, A20M#, FERR, IGNNE#,

STPCLK#, FLUSH#

Southbridge

See “Advanced 266 FSB

AMD Athlon™ XP Processor Model

8 SYSCLK and SYSCLK# AC

Characteristics” on page 24,

“Advanced 333 FSB AMD Athlon™

SYSCLK, SYSCLK# (Tied to CLKIN/CLKIN# and RSTCLK/RSTCLK#), XP Processor Model 8 SYSCLK and

System Clocks

PLLBYPASSCLK#, PLLBYPASSCLK

SYSCLK# AC Characteristics” on

page 28, Table 14, “SYSCLK and

SYSCLK# DC Characteristics,” on

page 37, “SYSCLK and SYSCLK#”

on page 78, and “PLL Bypass and

Test Pins” on page 77.

See “General AC and DC

Characteristics” on page 39, “PLL

Bypass and Test Pins” on page 77,

“Scan Pins” on page 78, “Analog

Pin” on page 73.

PLLBYPASS#, PLLTEST#, PLLMON1, PLLMON2, SCANCLK1,

SCANCLK2, SCANSHIFTEN, SCANINTEVAL, ANALOG

Test

Table 17, “Thermal Diode Electrical

Characteristics,” on page 42, and

“THERMDA and THERMDC Pins”

on page 78.

Thermal

THERMDA, THERMDC

See “General AC and DC

Characteristics” on page 39,

“DBRDY and DBREQ# Pins” on

page 74, “PWROK Pin” on page 77.

Miscellaneous DBREQ#, DBRDY, PWROK

32

Electrical Data

Chapter 8

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

8.3

Voltage Identification (VID[4:0])

Table 9 shows the VID[4:0] DC Characteristics. For more infor-

mation on VID[4:0] DC Characteristics, see “VID[4:0] Pins” on

page 78.

Table 9. VID[4:0] DC Characteristics

Parameter

Description

Output Current Low

Output High Voltage

Min

6 mA

–

Max

I_OL

V_OH

5.25 V *

Note:

*

The VID pins are either open circuit or pulled to ground. It is recommended that these pins

are not pulled above 5.25 V, which is 5.0 V + 5%.

8.4

Frequency Identification (FID[3:0])

Table 10 shows the FID[3:0] DC characteristics. For more

information, see “FID[3:0] Pins” on page 75.

Table 10. FID[3:0] DC Characteristics

Parameter

Description

Output Current Low

Output High Voltage

Min

6 mA

–

Max

I_OL

V_OH

2.625 V *

Note:

*

The FID pins must not be pulled above this voltage by an external pullup resistor.

8.5

VCCA AC and DC Characteristics

Table 11 shows the AC and DC characteristics for VCCA. For

more information, see “VCCA Pin” on page 78.

Table 11. VCCA AC and DC Characteristics

Symbol

V_VCCA

Parameter

VCCA Pin Voltage

VCCA Pin Current

Min

2.25

0

Nominal

Max

2.75

50

Units

V

Notes

2.5

1

2

I_VCCA

mA/GHz

Notes:

1. Minimum and Maximum voltages are absolute. No transients below minimum nor above maximum voltages are permitted.

2. Measured at 2.5 V.

Chapter 8

Electrical Data

33

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

8.6

Decoupling

See the AMD Athlon™ Processor-Based Motherboard Design

Guide, order# 24363, or contact your local AMD office for

information about the decoupling required on the motherboard

for use with the AMD Athlon™ XP processor model 8.

8.7

V

Characteristics

CC_CORE

Table 12 shows the AC and DC characteristics for V

.

CC_CORE

See Figure 10 on page 35 for a graphical representation of the

V

waveform.

CC_CORE

Table 12. V

Symbol

AC and DC Characteristics

CC_CORE

Parameter

Limit in Working State

Units

*

V_{CC_CORE_DC_MAX}

V_{CC_CORE_DC_MIN}

V_{CC_CORE_AC_MAX}

Maximum static voltage above V_{CC_CORE_NOM}

50

mV

Maximum static voltage below V_{CC_CORE_NOM}

–50

150

mV

*

Maximum excursion above V_{CC_CORE_NOM}

*

V_{CC_CORE_AC_MIN}

Maximum excursion below V_{CC_CORE_NOM}

–100

10

mV

µs

t_{MAX_AC}

Maximum excursion time for AC transients

Negative excursion time for AC transients

t_{MIN_AC}

5

Note:

*

All voltage measurements are taken differentially at the COREFB/COREFB# pins.

34

Electrical Data

Chapter 8

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

Figure 10 shows the processor core voltage (V

)

CC_CORE

waveform response to perturbation. The t

(negative AC

min_AC

transient excursion time) and t

(positive AC transient

max_AC

excursion time) represent the maximum allowable time below

or above the DC tolerance thresholds.

t_{MAX_AC}

V_{CC_CORE_AC_MAX}

V_{CC_CORE_DC_MAX}

V_{CC_CORE_NOM}

V_{CC_CORE_DC_MIN}

V_{CC_CORE_AC_MIN}

t_{MIN_AC}

I_{CORE_MAX}

dI /dt

I_{CORE_MIN}

Figure 10. V

Voltage Waveform

CC_CORE

Chapter 8

Electrical Data

35

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

8.8

Absolute Ratings

The AMD Athlon XP processor model 8 should not be subjected

to conditions exceeding the absolute ratings, as such conditions

can adversely affect long-term reliability or result in functional

damage.

Table 13 lists the maximum absolute ratings of operation for the

AMD Athlon XP processor model 8.

Table 13. Absolute Ratings

Parameter

Description

Min

Max

V_{CC_CORE}

VCCA

V

_{CC_CORE}Max + 0.5 V

AMD Athlon™ XP processor model 8 core supply

AMD Athlon XP processor model 8 PLL supply

Voltage on any signal pin

–0.5 V

VCCA Max + 0.5 V

V

_{CC_CORE}Max + 0.5 V

T_STORAGE

Storage temperature of processor

–40ºC

100ºC

36

Electrical Data

Chapter 8

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

8.9

SYSCLK and SYSCLK# DC Characteristics

Table 14 shows the DC characteristics of the SYSCLK and

SYSCLK# differential clocks. The SYSCLK signal represents

CLKIN and RSTCLK tied together while the SYSCLK# signal

represents CLKIN# and RSTCLK# tied together. For

information about SYSCLK and SYSCLK#, see “SYSCLK and

SYSCLK#” on page 79 and Table 24, “Pin Name

Abbreviations,” on page 58.

Table 14. SYSCLK and SYSCLK# DC Characteristics

Symbol

Description

Min

Max

Units

Crossing before transition is detected (DC)

400

mV

V_Threshold-DC

Crossing before transition is detected (AC)

450

–1

mV

mA

mV

pF

V_Threshold-AC

Leakage current through P-channel pullup to V_{CC_CORE}

I_{LEAK_P}

Leakage current through N-channel pulldown to VSS (Ground)

Differential signal crossover

1

I_{LEAK_N}

V

_{CC_CORE}/ 2 100

V_CROSS

Capacitance *

4

25 *

C

Note:

*

The following processor inputs have twice the listed capacitance because they connect to two input pads—SYSCLK and SYSCLK#.

SYSCLK connects to CLKIN/RSTCLK. SYSCLK# connects to CLKIN#/RSTCLK#.

Figure 11 shows the DC characteristics of the SYSCLK and

SYSCLK# signals.

V_CROSS

V_Threshold-DC= 400mV

V_Threshold-AC= 450mV

Figure 11. SYSCLK and SYSCLK# Differential Clock Signals

Chapter 8

Electrical Data

37

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

8.10

AMD Athlon™ System Bus DC Characteristics

Table 15 shows the DC characteristics of the AMD Athlon

system bus used by the AMD Athlon XP processor model 8.

Table 15. AMD Athlon™ System Bus DC Characteristics

Symbol

Parameter

Condition

Min

Max

Units Notes

(0.5 x V_{CC_CORE}) (0.5 x V_{CC_CORE}

)

V_REF

DC Input Reference Voltage

mV

1

–50

+50

100

I_{VREF_LEAK_P}V_REFTristate Leakage Pullup

V_IN= V_REFNominal

–100

µA

mV

I_{VREF_LEAK_N}V_REFTristate Leakage Pulldown V_IN= V_REFNominal

V_IH

V_IL

V

_REF+ 200

–500

V_{CC_CORE}+ 500

Input High Voltage

Input Low Voltage

V

_REF– 200

V_IN= VSS

(Ground)

I_{LEAK_P}

I_{LEAK_N}

Tristate Leakage Pullup

–1

mA

V_IN= V_{CC_CORE}

Nominal

Tristate Leakage Pulldown

1

7

C_IN

Input Pin Capacitance

4

pF

Ω

R_ON

0.90 x R_setN,P

1.1 x R_setN,P

Output Resistance

2

R_setP

R_setN

Notes:

Impedance Set Point, P Channel

Impedance Set Point, N Channel

40

70

1. V is nominally set to 50% of V

with actual values that are specific to motherboard design implementation. V must be

REF

CC_CORE

created with a sufficiently accurate DC source and a sufficiently quiet AC response to adhere to the 50 mV specification listed

above.

2. Measured at V

/ 2.

CC_CORE

38

Electrical Data

Chapter 8

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

8.11

General AC and DC Characteristics

Table 16 shows the AMD Athlon XP processor model 8 AC and

DC characteristics of the Southbridge, JTAG, test, and miscel-

laneous pins.

Table 16. General AC and DC Characteristics

Symbol

Parameter Description

Input High Voltage

Condition

Min

Max

Units Notes

(V_{CC_CORE}/ 2) +

200 mV

V_{CC_CORE}

300 mV

+

V_IH

V

1, 2

V_IL

Input Low Voltage

–300

350

mV

mA

V_{CC_CORE}

400

–

V_{CC_CORE}

300

V_OH

V_OL

Output High Voltage

Output Low Voltage

Tristate Leakage Pullup

–300

400

V_IN= VSS

(Ground)

I_{LEAK_P}

–1

V_IN= V_{CC_CORE}

Nominal

I_{LEAK_N}

Tristate Leakage Pulldown

600

–6

µA

I_OH

Output High Current

mA

ns

3

I_OL

Output Low Current

6

T_SU

Sync Input Setup Time

Sync Input Hold Time

2.0

0.0

4, 5

5

T_HD

ps

T_DELAY

Notes:

Output Delay with respect to RSTCLK

6.1

ns

1. Characterized across DC supply voltage range.

2. Values specified at nominal V . Scale parameters between V

minimum and V maximum.

CC_CORE.

CC_CORE

CC_CORE.

3. I and I are measured at V maximum and V minimum, respectively.

OL

OH

OL

OH

4. Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins.

5. These are aggregate numbers.

6. Edge rates indicate the range over which inputs were characterized.

7. In asynchronous operation, the signal must persist for this time to enable capture.

8. This value assumes RSTCLK period is 10 ns ==> TBIT = 2*fRST.

9. The approximate value for standard case in normal mode operation.

10. This value is dependent on RSTCLK frequency, divisors, Low Power mode, and core frequency.

11. Reassertions of the signal within this time are not guaranteed to be seen by the core.

12. This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase.

13. This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other

configurations.

14. Time to valid is for any open-drain pins. See requirements 7 and 8 in the “Power-Up Timing Requirements“ chapter for more

information.

Chapter 8

Electrical Data

39

Preliminary Information

AMD Athlon™ XP Processor Model 8 Data Sheet

25175H—March 2003

Table 16. General AC and DC Characteristics (continued)

Symbol

Parameter Description

Input Time to Acquire

Condition

Min

20.0

40.0

1.0

Max

Units Notes

T_BIT

ns

7, 8

9–13

6

T_RPT

T_RISE

T_FALL

Input Time to Reacquire

Signal Rise Time

3.0

12

V/ns

pF

Signal Fall Time

1.0

6

C

Pin Capacitance

4

T_VALID

Time to data valid