AMD-K6-2+PROCESSOR [ETC]
Mobile AMD-K6?-2+Processor Data Sheet ; 移动式AMD- K6 ？ -2 +处理器数据手册\n
| 型号： | AMD-K6-2+PROCESSOR |
| 厂家： | 
ETC |
| 描述： | Mobile AMD-K6?-2+Processor Data Sheet
|
| 文件： | 总332页 (文件大小：4936K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Information
Mobile
®
AMD-K6 -2+
Processor
Data Sheet
Publication # 23446
Issue Date: June 2000
Rev: B
Amendment/0
Preliminary Information
© 2000 Advanced Micro Devices, Inc. All rights reserved.
The contents of this document are provided in connection with Advanced Micro Devices, Inc.
(“AMD”) products. AMD makes no representations or warranties with respect to the accuracy
or completeness of the contents of this publication and reserves the right to make changes to
specifications and product descriptions at any time without notice. No license, whether
express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted
by this publication. Except as set forth in AMD’s Standard Terms and Conditions of Sale, AMD
assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its
products including, but not limited to, the implied warranty of merchantability, fitness for a
particular purpose, or infringement of any intellectual property right.
AMD’s products are not designed, intended, authorized or warranted for use as components
in systems intended for surgical implant into the body, or in other applications intended to
support or sustain life, or in any other application in which the failure of AMD’s product could
create a situation where personal injury, death, or severe property or environmental damage
may occur. AMD reserves the right to discontinue or make changes to its products at any time
without notice.
Trademarks
AMD, the AMD logo, K6, 3DNow!, and combinations thereof, TriLevel Cache, and Super7 are trademarks, and
AMD-K6 and RISC86 are registered trademarks of Advanced Micro Devices, Inc.
MMX is a trademark of Intel Corporation.
Microsoft, Windows, and Windows NT are registered trademarks of Microsoft Corporation.
Other product names used in this publication are for identification purposes only and may be trademarks of their
respective companies.
Preliminary Information
®
23446B/0—June 2000
Mobile AMD-K6 -2+ Processor Data Sheet
Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii
®
1
Mobile AMD-K6 -2+ Processor . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
PowerNow! Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Super7™ Platform Initiative . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Internal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Mobile AMD-K6 -2+ Processor Microarchitecture
®
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
®
Enhanced RISC86 Microarchitecture . . . . . . . . . . . . . . . . . . . 6
2.3
2.4
Cache, Instruction Prefetch, and Predecode Bits . . . . . . . . . . 9
Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Predecode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Instruction Fetch and Decode . . . . . . . . . . . . . . . . . . . . . . . . . 11
Instruction Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Instruction Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Centralized Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Register X and Y Pipelines . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Branch-Prediction Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Branch History Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Branch Target Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Return Address Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Branch Execution Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.5
2.6
2.7
3
Software Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Integer Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Segment Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Segment Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Instruction Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Floating-Point Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Floating-Point Register Data Types . . . . . . . . . . . . . . . . . . . . . 28
MMX™/3DNow!™ Technology Registers . . . . . . . . . . . . . . . . 29
MMX™ Technology Data Types . . . . . . . . . . . . . . . . . . . . . . . . 29
3DNow!™ Technology Data Types . . . . . . . . . . . . . . . . . . . . . . 30
EFLAGS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Debug Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Contents
iii
Preliminary Information
Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
Model-Specific Registers (MSR) . . . . . . . . . . . . . . . . . . . . . . . 37
Memory Management Registers . . . . . . . . . . . . . . . . . . . . . . . 46
Task State Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Descriptors and Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Instructions Supported by the
3.2
Mobile AMD-K6-2+ Processor . . . . . . . . . . . . . . . . . . . . . . . . . 55
4
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
Signal Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
A20M# (Address Bit 20 Mask) . . . . . . . . . . . . . . . . . . . . . . . . . 87
A[31:3] (Address Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
ADS# (Address Strobe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
ADSC# (Address Strobe Copy) . . . . . . . . . . . . . . . . . . . . . . . . 89
AHOLD (Address Hold) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
AP (Address Parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
APCHK# (Address Parity Check) . . . . . . . . . . . . . . . . . . . . . . 92
BE[7:0]# (Byte Enables) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.10 BF[2:0] (Bus Frequency) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.11 BOFF# (Backoff) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.12 BRDY# (Burst Ready) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.13 BRDYC# (Burst Ready Copy) . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.14 BREQ (Bus Request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.15 CACHE# (Cacheable Access) . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.16 CLK (Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.17 D/C# (Data/Code) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.18 D[63:0] (Data Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.19 DP[7:0] (Data Parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.20 EADS# (External Address Strobe) . . . . . . . . . . . . . . . . . . . . 102
4.21 EWBE# (External Write Buffer Empty) . . . . . . . . . . . . . . . . 103
4.22 FERR# (Floating-Point Error) . . . . . . . . . . . . . . . . . . . . . . . 104
4.23 FLUSH# (Cache Flush) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.24 HIT# (Inquire Cycle Hit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.25 HITM# (Inquire Cycle Hit To Modified Line) . . . . . . . . . . . 106
4.26 HLDA (Hold Acknowledge) . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.27 HOLD (Bus Hold Request) . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.28 IGNNE# (Ignore Numeric Exception) . . . . . . . . . . . . . . . . . 108
4.29 INIT (Initialization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.30 INTR (Maskable Interrupt) . . . . . . . . . . . . . . . . . . . . . . . . . . 110
4.31 INV (Invalidation Request) . . . . . . . . . . . . . . . . . . . . . . . . . . 110
4.32 KEN# (Cache Enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
4.33 LOCK# (Bus Lock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.34 M/IO# (Memory or I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
4.35 NA# (Next Address) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.36 NMI (Non-Maskable Interrupt) . . . . . . . . . . . . . . . . . . . . . . . 114
4.37 PCD (Page Cache Disable) . . . . . . . . . . . . . . . . . . . . . . . . . . 115
iv
Contents
Preliminary Information
®
23446B/0—June 2000
Mobile AMD-K6 -2+ Processor Data Sheet
4.38 PCHK# (Parity Check) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
4.39 PWT (Page Writethrough) . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.40 RESET (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
4.41 RSVD (Reserved) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
4.42 SCYC (Split Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4.43 SMI# (System Management Interrupt) . . . . . . . . . . . . . . . . 119
4.44 SMIACT# (System Management Interrupt Active) . . . . . . 120
4.45 STPCLK# (Stop Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
4.46 TCK (Test Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
4.47 TDI (Test Data Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
4.48 TDO (Test Data Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
4.49 TMS (Test Mode Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.50 TRST# (Test Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.51 VCC2DET (VCC2 Detect) . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.52 VCC2H/L# (VCC2 High/Low) . . . . . . . . . . . . . . . . . . . . . . . . 124
4.53 VID[4:0] (Voltage Identification) . . . . . . . . . . . . . . . . . . . . . 124
4.54 W/R# (Write/Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.55 WB/WT# (Writeback or Writethrough) . . . . . . . . . . . . . . . . 125
5
PowerNow! Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.1
5.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Enhanced Power Management Features . . . . . . . . . . . . . . . 131
Enhanced Power Management Register (EPMR) . . . . . . . . 131
EPM 16-Byte I/O Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Dynamic Core Frequency and Core Voltage Control . . . . . 134
Effective Bus Divisors EBF[2:0] . . . . . . . . . . . . . . . . . . . . . . . 134
Dynamic Core Frequency Control . . . . . . . . . . . . . . . . . . . . . 135
Voltage Identification (VID) Outputs . . . . . . . . . . . . . . . . . . 137
5.3
6
Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
6.1
6.2
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Bus State Machine Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 141
Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Data-NA# Requested . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Pipeline Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Pipeline Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Memory Reads and Writes . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Single-Transfer Memory Read and Write . . . . . . . . . . . . . . . 144
Misaligned Single-Transfer Memory Read and Write . . . . . 146
Burst Reads and Pipelined Burst Reads . . . . . . . . . . . . . . . . 148
Burst Writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
6.3
Contents
v
Preliminary Information
Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
6.4
6.5
I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Basic I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Misaligned I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . 153
Inquire and Bus Arbitration Cycles . . . . . . . . . . . . . . . . . . . 154
Hold and Hold Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . 154
HOLD-Initiated Inquire Hit to Shared or
Exclusive Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
HOLD-Initiated Inquire Hit to Modified Line . . . . . . . . . . . 158
AHOLD-Initiated Inquire Miss. . . . . . . . . . . . . . . . . . . . . . . . 160
AHOLD-Initiated Inquire Hit to Shared or
Exclusive Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
AHOLD-Initiated Inquire Hit to Modified Line . . . . . . . . . . 164
AHOLD Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Bus Backoff (BOFF#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Locked Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Basic Locked Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Locked Operation with BOFF# Intervention . . . . . . . . . . . . 172
Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Special Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Basic Special Bus Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Shutdown Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Stop Grant and Stop Clock States . . . . . . . . . . . . . . . . . . . . . 179
INIT-Initiated Transition from Protected Mode to
6.6
Real Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
7
Power-on Configuration and Initialization . . . . . . . . . . . . . . 185
7.1
Signals Sampled During the Falling Transition of
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
FLUSH# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
BF[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
RESET Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
State of Processor After RESET . . . . . . . . . . . . . . . . . . . . . . 186
Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
State of Processor After INIT . . . . . . . . . . . . . . . . . . . . . . . . 189
7.2
7.3
7.4
8
Cache Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
8.1
8.2
8.3
MESI States in the L1 Data Cache and L2 Cache . . . . . . . . 193
Predecode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Cache Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Cache-Related Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Cache Disabling and Flushing . . . . . . . . . . . . . . . . . . . . . . . 197
L1 and L2 Cache Disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
L2 Cache Disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
L2 Cache and Tag Array Testing . . . . . . . . . . . . . . . . . . . . . 198
Cache-Line Fills . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
8.4
8.5
8.6
vi
Contents
Preliminary Information
®
23446B/0—June 2000
Mobile AMD-K6 -2+ Processor Data Sheet
8.7
8.8
Cache-Line Replacements . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Write Allocate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Write to a Cacheable Page . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Write to a Sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Write Allocate Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Write Allocate Logic Mechanisms and Conditions . . . . . . . 204
Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Hardware Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Software Prefetching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
8.9
8.10 Cache States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
8.11 Cache Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Inquire Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Internal Snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
FLUSH# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
PFIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
WBINVD and INVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Cache-Line Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
8.12 Writethrough versus Writeback Coherency States . . . . . . . 214
8.13 A20M# Masking of Cache Accesses . . . . . . . . . . . . . . . . . . . 214
9
Write Merge Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
9.1
9.2
EWBE Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Memory Type Range Registers . . . . . . . . . . . . . . . . . . . . . . . 219
UC/WC Cacheability Control Register (UWCCR) . . . . . . . . 219
10
Floating-Point and Multimedia Execution Units . . . . . . . . . 223
10.1 Floating-Point Execution Unit . . . . . . . . . . . . . . . . . . . . . . . 223
Handling Floating-Point Exceptions . . . . . . . . . . . . . . . . . . . 223
External Logic Support of Floating-Point Exceptions . . . . . 223
10.2 Multimedia and 3DNow! Execution Units . . . . . . . . . . . . . . 225
10.3 Floating-Point and MMX/3DNow! Instruction
Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
FERR# and IGNNE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
11
System Management Mode (SMM) . . . . . . . . . . . . . . . . . . . . 227
11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
11.2 SMM Operating Mode and Default Register Values . . . . . 227
11.3 SMM State-Save Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
11.4 SMM Revision Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
11.5 SMM Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
11.6 Halt Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
11.7 I/O Trap Dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
11.8 I/O Trap Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
11.9 Exceptions, Interrupts, and Debug in SMM . . . . . . . . . . . . 237
Contents
vii
Preliminary Information
Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
12
Test and Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
12.1 Built-In Self-Test (BIST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
12.2 Tri-State Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
12.3 Boundary-Scan Test Access Port (TAP) . . . . . . . . . . . . . . . . 241
Test Access Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
TAP Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
TAP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
TAP Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
TAP Controller State Machine . . . . . . . . . . . . . . . . . . . . . . . . 248
12.4 Cache Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
12.5 L2 Cache and Tag Array Testing . . . . . . . . . . . . . . . . . . . . . 253
Level-2 Cache Array Access Register (L2AAR) . . . . . . . . . . 253
12.6 Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Debug Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Debug Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
13
Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
13.1 Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Enter Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Exit Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
13.2 Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Enter Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Exit Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
13.3 Stop Grant Inquire State . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Enter Stop Grant Inquire State . . . . . . . . . . . . . . . . . . . . . . . 266
Exit Stop Grant Inquire State . . . . . . . . . . . . . . . . . . . . . . . . 266
13.4 EPM Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Enter EPM Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . 266
Exit EPM Stop Grant State. . . . . . . . . . . . . . . . . . . . . . . . . . . 267
13.5 Stop Clock State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Enter Stop Clock State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Exit Stop Clock State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
14
15
Power and Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
14.1 Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
14.2 Decoupling Recommendations . . . . . . . . . . . . . . . . . . . . . . . 272
14.3 Pin Connection Requirements . . . . . . . . . . . . . . . . . . . . . . . 273
Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
15.1 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
15.2 Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
15.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
15.4 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
viii
Contents
Preliminary Information
®
23446B/0—June 2000
Mobile AMD-K6 -2+ Processor Data Sheet
16
Signal Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . 279
16.1 CLK Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . 279
16.2 Clock Switching Characteristics for 100-MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
16.3 Valid Delay, Float, Setup, and Hold Timings . . . . . . . . . . . 281
16.4 Output Delay Timings for 100-MHz Bus Operation . . . . . . 282
16.5 Input Setup and Hold Timings for 100-MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
16.6 RESET and Test Signal Timing . . . . . . . . . . . . . . . . . . . . . . 286
17
Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
17.1 Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . 293
Heat Dissipation Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Measuring Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 296
18
19
20
Pin Description Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Pin Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Package Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
20.1 321-Pin Staggered CPGA Package Specification . . . . . . . . 301
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
21
Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Contents
ix
Preliminary Information
®
Mobile AMD-K6 -2+ Processor Data Sheet
23446B/0—June 2000
x
Contents
Preliminary Information
Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
List of Figures
®
Figure 1. Mobile AMD-K6 -2+ Processor Block Diagram. . . . . . . . . . . . . . 7
Figure 2. Cache Sector Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 3. The Instruction Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 4. Mobile AMD-K6-2+ Processor Decode Logic . . . . . . . . . . . . . . . 13
Figure 5. Mobile AMD-K6-2+ Processor Scheduler . . . . . . . . . . . . . . . . . . 16
Figure 6. Register X and Y Functional Units . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7. EAX Register with 16-Bit and 8-Bit Name Components. . . . . . 22
Figure 8. Integer Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9. Segment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 10. Segment Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 11. Floating-Point Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 12. FPU Status Word Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 13. FPU Control Word Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 14. FPU Tag Word Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 15. Packed Decimal Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 16. Precision Real Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 17. MMX™/3DNow!™ Technology Registers. . . . . . . . . . . . . . . . . . 29
Figure 18. MMX™ Technology Data Types . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 19. 3DNow!™ Technology Data Types . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 20. EFLAGS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 21. Control Register 4 (CR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 22. Control Register 3 (CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 23. Control Register 2 (CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 24. Control Register 1 (CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 25. Control Register 0 (CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 26. Debug Register DR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 27. Debug Register DR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 28. Debug Registers DR5 and DR4. . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 29. Debug Registers DR3, DR2, DR1, and DR0. . . . . . . . . . . . . . . . 36
Figure 30. Machine-Check Address Register (MCAR) . . . . . . . . . . . . . . . . 38
Figure 31. Machine-Check Type Register (MCTR) . . . . . . . . . . . . . . . . . . . 38
Figure 32. Test Register 12 (TR12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
List of Figures
xi
Preliminary Information
Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
Figure 33. Time Stamp Counter (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 34. Extended Feature Enable Register (EFER)—
MSR C000_0080h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 35. SYSCALL/SYSRET Target Address Register (STAR) . . . . . . . 40
Figure 36. Write Handling Control Register (WHCR)—
MSR C0000_0082h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 37. UC/WC Cacheability Control Register (UWCCR)—
MSR C0000_0085h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 38. Processor State Observability Register (PSOR)—
MSR C000_0087h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 39. Page Flush/Invalidate Register (PFIR)— MSR C000_0088h . . 42
Figure 40. L2 Tag or Data Location - EDX . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 41. L2 Data - EAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 42. L2 Tag Information - EAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 43. Enhanced Power Management Register (EPMR)—
MSR C000_0086h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 44. Memory Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 45. Task State Segment (TSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 46. 4-Kbyte Paging Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 47. 4-Mbyte Paging Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 48. Page Directory Entry 4-Kbyte Page Table (PDE) . . . . . . . . . . . 50
Figure 49. Page Directory Entry 4-Mbyte Page Table (PDE) . . . . . . . . . . 50
Figure 50. Page Table Entry (PTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 51. Application Segment Descriptor . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 52. System Segment Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 53. Gate Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 54. Logic Symbol Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 55. Enhanced Power Management Register (EPMR)—
MSR C000_0086h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Figure 56. EPM 16-Byte I/O Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Figure 57. Bus Divisor and Voltage ID Control (BVC) Field . . . . . . . . . . 136
Figure 58. Waveform Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 59. Bus State Machine Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 60. Non-Pipelined Single-Transfer Memory Read/Write and
Write Delayed by EWBE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 61. Misaligned Single-Transfer Memory Read and Write . . . . . . 147
xii
List of Figures
Preliminary Information
®
23446B/0—June 2000
Mobile AMD-K6 -2+ Processor Data Sheet
Figure 62. Burst Reads and Pipelined Burst Reads . . . . . . . . . . . . . . . . . 149
Figure 63. Burst Writeback due to Cache-Line Replacement . . . . . . . . . 151
Figure 64. Basic I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 65. Misaligned I/O Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 66. Basic HOLD/HLDA Operation . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 67. HOLD-Initiated Inquire Hit to Shared or Exclusive Line . . . 157
Figure 68. HOLD-Initiated Inquire Hit to Modified Line . . . . . . . . . . . . . 159
Figure 69. AHOLD-Initiated Inquire Miss . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 70. AHOLD-Initiated Inquire Hit to Shared or
Exclusive Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 71. AHOLD-Initiated Inquire Hit to Modified Line . . . . . . . . . . . 165
Figure 72. AHOLD Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 73. BOFF# Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 74. Basic Locked Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Figure 75. Locked Operation with BOFF# Intervention . . . . . . . . . . . . . . 173
Figure 76. Interrupt Acknowledge Operation . . . . . . . . . . . . . . . . . . . . . . 175
Figure 77. Basic Special Bus Cycle (Halt Cycle) . . . . . . . . . . . . . . . . . . . . 177
Figure 78. Shutdown Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 79. Stop Grant and Stop Clock Modes, Part 1 . . . . . . . . . . . . . . . . 180
Figure 80. Stop Grant and Stop Clock Modes, Part 2 . . . . . . . . . . . . . . . . 181
Figure 81. INIT-Initiated Transition from Protected Mode to
Real Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 82. L1 and L2 Cache Organization . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 83. L1 Cache Sector Organization. . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 84. Write Handling Control Register (WHCR) . . . . . . . . . . . . . . . 202
Figure 85. Write Allocate Logic Mechanisms and Conditions . . . . . . . . . 204
Figure 86. Page Flush/Invalidate Register (PFIR)—
MSR C000_0088h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 87. UC/WC Cacheability Control Register (UWCCR)—
MSR C000_0085h (Model D) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Figure 88. External Logic for Supporting Floating-Point Exceptions. . . 224
Figure 89. SMM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Figure 90. TAP State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Figure 91. L2 Cache Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Figure 92. L2 Cache Sector and Line Organization . . . . . . . . . . . . . . . . . 254
List of Figures
xiii
Preliminary Information
Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
Figure 93. L2 Tag or Data Location - EDX . . . . . . . . . . . . . . . . . . . . . . . . . 254
Figure 94. L2 Data - EAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Figure 95. L2 Tag Information - EAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Figure 96. LRU Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Figure 97. Debug Register DR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Figure 98. Debug Register DR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Figure 99. Debug Registers DR5 and DR4. . . . . . . . . . . . . . . . . . . . . . . . . 258
Figure 100. Debug Registers DR3, DR2, DR1, and DR0. . . . . . . . . . . . . . . 259
Figure 101. Clock Control State Transitions . . . . . . . . . . . . . . . . . . . . . . . . 269
Figure 102. Suggested Component Placement . . . . . . . . . . . . . . . . . . . . . . 272
Figure 103. CLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Figure 104. Diagrams Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Figure 105. Output Valid Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Figure 106. Maximum Float Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . 289
Figure 107. Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Figure 108. Reset and Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . 290
Figure 109. TCK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Figure 110. TRST# Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Figure 111. Test Signal Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Figure 112. Thermal Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Figure 113. Power Consumption versus Thermal Resistance . . . . . . . . . . 294
Figure 114. Processor’s Heat Dissipation Path . . . . . . . . . . . . . . . . . . . . . . 295
Figure 115. Measuring Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Figure 116. Mobile AMD-K6-2+ Processor Top-Side View . . . . . . . . . . . . . 297
Figure 117. Mobile AMD-K6-2+ Processor Bottom-Side View . . . . . . . . . . 298
Figure 118. 321-Pin Staggered CPGA Package Specification . . . . . . . . . . 301
xiv
List of Figures
Preliminary Information
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23446B/0—June 2000
Mobile AMD-K6 -2+ Processor Data Sheet
List of Tables
Table 1.
Execution Latency and Throughput of Execution Units . . . . . 17
General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 2.
Table 3.
General-Purpose Register Doubleword, Word, and
Byte Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 4.
Table 5.
Table 6.
Table 7.
Segment Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
®
Mobile AMD-K6 -2+ Processor MSRs . . . . . . . . . . . . . . . . . . . . 37
Extended Feature Enable Register (EFER) . . . . . . . . . . . . . . . 39
SYSCALL/SYSRET Target Address Register (STAR)
Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 8.
Table 9.
Memory Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . 46
Application Segment Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 10. System Segment and Gate Types . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 11. Summary of Exceptions and Interrupts . . . . . . . . . . . . . . . . . . . 54
Table 12. Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 13. Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 14. MMX™ Technology Instructions . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 15. 3DNow!™ Technology Instructions . . . . . . . . . . . . . . . . . . . . . . 83
Table 16. 3DNow!™ Technology DSP Extensions . . . . . . . . . . . . . . . . . . . 84
Table 17. Processor-to-Bus Clock Ratios. . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 18. Output Pin Float Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 19. Input Pin Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 20. Output Pin Float Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 21. Input/Output Pin Float Conditions . . . . . . . . . . . . . . . . . . . . . . 127
Table 22. Test Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 23. Bus Cycle Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 24. Special Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Table 25. Enhanced Power Management Register (EPMR)
Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 26. EPM 16-Byte I/O Block Definition . . . . . . . . . . . . . . . . . . . . . . 134
Table 27. Processor-to-Bus Clock Ratios . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 28. Bus Divisor and Voltage ID Control (BVC) Definition . . . . . . 136
Table 29. Bus-Cycle Order During Misaligned Transfers . . . . . . . . . . . . 146
Table 30. A[4:3] Address-Generation Sequence During Bursts . . . . . . . 148
Table 31. Bus-Cycle Order During Misaligned I/O Transfers . . . . . . . . . 153
Table 32. Interrupt Acknowledge Operation Definition . . . . . . . . . . . . . 174
List of Tables
xv
Preliminary Information
Mobile AMD-K6 -2+ Processor Data Sheet
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23446B/0—June 2000
Table 33. Encodings For Special Bus Cycles . . . . . . . . . . . . . . . . . . . . . . 176
Table 34. Output Signal State After RESET . . . . . . . . . . . . . . . . . . . . . . 186
Table 35. Register State After RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 36. PWT Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 37. PCD Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 38. CACHE# Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 39. L1 and L2 Cache States for Read and Write Accesses . . . . . . 207
Table 40. Valid L1 and L2 Cache States and Effect of Inquire
Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Table 41. L1 and L2 Cache States for Snoops, Flushes, and
Invalidation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Table 42. EWBEC Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 43. WC/UC Memory Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 44. Valid Masks and Range Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 45. Initial State of Registers in SMM . . . . . . . . . . . . . . . . . . . . . . . 229
Table 46. SMM State-Save Area Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Table 47. SMM Revision Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Table 48. I/O Trap Dword Configuration . . . . . . . . . . . . . . . . . . . . . . . . . 234
Table 49. I/O Trap Restart Slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Table 50. Boundary Scan Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . 245
Table 51. Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . 246
Table 52. Supported Tap Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Table 53. Tag versus Data Selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Table 54. DR7 LEN and RW Definitions . . . . . . . . . . . . . . . . . . . . . . . . . 261
Table 55. Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Table 56. Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Table 57. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
Table 58. Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
Table 59. CLK Switching Characteristics for 100-MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Table 60. Output Delay Timings for 100-MHz Bus Operation . . . . . . . . 282
Table 61. Input Setup and Hold Timings for 100-MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Table 62. RESET and Configuration Signals for 100-MHz Bus
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Table 63. TCK Waveform and TRST# Timing at 25 MHz . . . . . . . . . . . . 287
Table 64. Test Signal Timing at 25 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . 287
Table 65. Package Thermal Specifications. . . . . . . . . . . . . . . . . . . . . . . . 293
xvi
List of Tables
Preliminary Information
®
23446B/0—June 2000
Mobile AMD-K6 -2+ Processor Data Sheet
Table 66. 321-Pin Staggered CPGA Package Specification . . . . . . . . . . 301
Table 67. Valid Ordering Part Number Combinations . . . . . . . . . . . . . . 303
List of Tables
xvii
Preliminary Information
®
Mobile AMD-K6 -2+ Processor Data Sheet
23446B/0—June 2000
xviii
List of Tables
Preliminary Information
Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
Revision History
Date
Rev
A
Description
May 2000
June 2000
Initial release.
Added 533- and 550-MHz specifications and OPNs.
B
Revision History
xix
Preliminary Information
®
Mobile AMD-K6 -2+ Processor Data Sheet
23446B/0—June 2000
xx
RevisionHistory
Preliminary Information
Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
®
1
Mobile AMD-K6 -2+ Processor
®
■ Advanced 6-Issue RISC86 Superscalar Microarchitecture
◆
◆
◆
◆
◆
◆
◆
Ten parallel specialized execution units
Multiple sophisticated x86-to-RISC86 instruction decoders
Advanced two-level branch prediction
Speculative execution
Out-of-order execution
Register renaming and data forwarding
Issues up to six RISC86 instructions per clock
■ Innovative TriLevel Cache™ Design
◆
192-Kbyte total internal cache
•
Internal split, two-way set associative, 64-Kbyte L1 Cache
− 32-Kbyte instruction cache with additional 20-Kbytes of predecode cache
− 32-Kbyte writeback dual-ported data cache
− MESI protocol support
•
Internal full-speed, four-way set associative, 128-Kbyte, L2 Cache
◆
◆
Multiport internal cache design enabling simultaneous 64-bit reads/writes of
L1 and L2 caches
100-MHz frontside bus to optional Level-3 cache on Super7™ platforms
■ 3DNow!™ Technology
◆
Additional instructions to improve 3D graphics and multimedia performance
Separate multiplier and ALU for superscalar instruction execution
◆
■ PowerNow! Technology for high-performance and advanced low-power modes
■ Compatible with Super7 platform notebook designs
◆
Leverages high-speed 100-MHz processor bus
Accelerated Graphic Port (AGP) support
◆
■ High-Performance IEEE 754-Compatible and 854-Compatible Floating-Point Unit
■ High-Performance Industry-Standard MMX™ Instructions
◆
Dual integer ALU for superscalar execution
■ 321-pin Ceramic Pin Grid Array (CPGA) Package
■ Industry-Standard System Management Mode (SMM)
■ IEEE 1149.1 Boundary Scan
■ x86 Binary Software Compatibility
■ Low Voltage 0.18-Micron Process Technology
®
Chapter 1
Mobile AMD-K6 -2+ Processor
1
Preliminary Information
®
Mobile AMD-K6 -2+ Processor Data Sheet
23446B/0—June 2000
®
Th e Mob ile AMD-K6 -2+ p roce ssor is a n a dva n ce d 6t h ge n e ra t ion x86 m ob ile
p roce ssor d e live r in g h igh p e r for m a n ce for n ot eb ook P C syst e m s. Th e Mob ile
AMD-K6-2+ p roce ssor is b u ilt on AMD' s 0.18u m p roce ss t e ch n ology a n d a dd s
PowerNow! tech nology for high performance and low power modes of operation,
allowing for significant improvements in the battery life of notebook PCs. The Mobile
AMD-K6-2+ p roce ssor su p p or t s AMD's in n ova t ive Tr iLeve l Ca ch e ™ d e sign for
enhanced system performance. The TriLevel Cache design provides a large 64-Kbyte
L1 cache, a 128-Kbyte L2 cache operating at full processor speed on a backside bus,
and up to 1 Mbyte of available L3 cache memory on the external 100-MHz frontside
bus. This combination of the largest and fastest cache memory subsystem gives the
Mobile AMD-K6-2+ processor a performance edge over competing x86 mobile CPU
solutions.
The Mobile AMD-K6-2+ processor also incorporates a superscalar MMX unit, support
for a 100-MHz frontside bus, and AMD's innovative 3DNow!™ technology for high-
performance multimedia and 3D graphics operation.
The Mobile AMD-K6-2+ processor includes several other key features for the mobile
market. The processor is implemented using an AMD-developed, state-of-the-art low
power 0.18-micron process technology. This process technology features a split-plane
design t hat allows the processor core to operate at a lower volt age while the I/O
p or t ion op e ra t e s a t t h e in d u st ry-st a n d a rd 3.3V leve l. Th e 0.18-m icron p roce ss
t e ch n ology wit h t h e sp lit -p la n e volt a ge d e sign e n ab le s t h e Mob ile AMD-K6-2+
processor to deliver excellent portable PC performance solutions while utilizing a
lower processor core voltage, which results in lower power consumption and longer
battery life. In addition, the Mobile AMD-K6-2+ processor includes the complete
in dustry-standard Syst em Management Mode (SMM), which is critical to system
resource and power management. The Mobile AMD-K6-2+ processor also features the
industry-standard Stop-Clock (STPCLK#) control circuitry and the Halt instruction,
both required for implementing the ACPI power management specification. The
Mobile AMD-K6-2+ processor is offered in an industry-standard Super7™ compatible,
321-pin Ceramic Pin Grid Array (CPGA) package.
Th e Mob ile AMD-K6-2+ p roce ssor ' s R ISC86 m icroa rch it e ct u re is a d e cou p le d
d e cod e /e xe cu t ion su p e rsca la r d e sign t h a t im p le m e n t s st a t e -of-t h e -a r t d e sign
t e ch n iq u e s t o a ch ieve le a d in g-e d ge p e r for m a n ce . Adva n ce d d e sign t e chn iq u e s
implemented in the Mobile AMD-K6-2+ processor include multiple x86 instruction
d e cod e , single -clock int e r na l R ISC op e ra t ions, t e n exe cution u nits t ha t sup port
superscalar operation, out-of-order execution, data forwarding, speculative execution,
a n d re gist e r re n a m in g. In a dd it ion , t he p roce ssor su p p or t s t h e in d u st ry's m ost
advanced branch prediction logic by implementing an 8192-entry branch history table,
the industry's only branch target cache, and a return address stack, which combine to
deliver better than a 95% prediction rate. These design techniques enable the Mobile
AMD-K6-2+ processor to issue, execute, and retire multiple x86 instructions per clock,
resulting in excellent scaleable performance.
®
2
Mobile AMD-K6 -2+ Processor
Chapter 1
Preliminary Information
Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
AMD's 3DNow! technology is an instruction set extension to x86 that includes 21 new
instructions to improve 3D graphics operations and other single precision floating-
point compute intensive operations. AMD has already shipped millions of AMD-K6
family processors with 3DNow! technology for desktop PCs, revolutionizing the 3D
experience with up to four times the peak floating-point performance of previous
generation solutions. AMD is now bringing this advanced capability to notebook
computing, working in conjunction with advanced mobile 3D graphic controllers to
®
reach new levels of realism in mobile computing. With support from Microsoft and
the x86 software developer community, a new generation of visually compelling
applications is coming to market that support 3DNow! technology.
The Mobile AMD-K6-2+ processor remains pin compatible with existing Super7™
notebook solutions, however to take advantage of the PowerNow! technology features
a number of new pins and registers have been defined that need to be supported in the
notebook platform.
The Mobile AMD-K6-2+ processor has undergone extensive testing and is compatible
®
®
with Windows 98, Windows NT and other leading operating systems. The Mobile
AMD-K6-2+ processor is also compatible with more than 60,000 software applications,
including the latest 3DNow! technology and MMX technology software. As the world's
second-largest supplier of processors for the Windows environment, AMD has shipped
more than 50 million Microsoft Windows compatible processors in the last five years.
The Mobile AMD-K6-2+ processor is the next generation in a long line of Microsoft
Windows compatible processors from AMD. With its combination of state-of-the-art
fe at u res, le a d in g-e d ge p er form a n ce , h igh -p e rfor m ance mult im e d ia e n gin e , x86
compatibility, and low-cost infrastructure, the Mobile AMD-K6-2+ processor is the
superior choice for performance notebook computers.
1.1
PowerNow! Technology
AMD has added a number of new features to the Mobile AMD-K6-2+ processor. These
features are called PowerNow! technology. The goal of PowerNow! technology is to
allow both high-performance and extended battery life in the same notebook system.
When the notebook is running under AC power, the processor operates at maximum
performance, within the thermal boundaries of the notebook system design. When the
notebook is running on DC power, the processor can run in an advanced low power
mode, providing significant benefits in battery life to the user. PowerNow! technology
also provides the user with an option to make a trade-off between performance and
r u n -t im e wh ile b a t t e ry p owe re d , t hrou gh t he ab ilit y t o dyn a m ica lly cha n ge t he
processor bus frequency and core voltage in a manner that is transparent to system
operation.
®
Chapter 1
Mobile AMD-K6 -2+ Processor
3
Preliminary Information
Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
1.2
Super7™ Platform Initiative
AMD and its industry partners are delivering many firsts to the notebook PC market
with the Super7 platform. Super7 notebook platforms were the first in the industry to
support a 100MHz front-side bus and AMD's TriLevel Cache architecture.
Super7™ Platform Features:
■ 100-MHz processor bus−The Mobile AMD-K6-2+ processor supports a 100-MHz, 800
Mbyte/second frontside bus to provide a high-speed interface to Super7 platform-
based chipsets. The 100-MHz interface to the frontside L3 cache and main system
memory speeds up access to the frontside cache and main memory by 50 percent
over the 66-MHz Socket 7 interface-resulting in a significant 10% increase in
overall system performance.
■ Accelerated graphics port support−AGP improves the performance of mid-range PCs
that have small amounts of video memory in the graphics sub-system. The
industry-standard AGP specification enables a 133-MHz graphics interface and
will scale to even higher levels of performance in the future.
■ Support for backside L2 and frontside L3 cache−The Super7 platform has the
'headroom' to support higher-performance Mobile AMD-K6 processors, with clock
speeds scaling to 550 MHz and beyond.
®
4
Mobile AMD-K6 -2+ Processor
Chapter 1
Preliminary Information
Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
2
Internal Architecture
2.1
Introduction
The Mobile AMD-K6-2+ processor implements advanced design
t e ch n iq u e s k n own a s t h e R ISC86 m icroa rch it e ct u re . Th e
RISC86 microarchit ect ure is a decouple d decode/execution
d e sig n a p p r oa ch t h a t yi e l d s su p e r ior sixt h -ge n e r a t ion
performance for x86-based software. This chapter describes the
techniques used and the functional elements of the RISC86
microarchitecture.
2.2
Mobile AMD-K6®-2+ Processor Microarchitecture Overview
When discussing processor design, it is important to understand
t h e t e r m s a r ch i t ect u r e, m i cr oa r ch i t ect u r e, a n d d esi gn
implementation. The term architecture refers to the instruction
se t a n d fe a t u re s of a p roce ssor t h a t a re visib le t o soft wa re
p r og r a m s r u n n i n g o n t h e p r o c e s s o r. Th e a r ch i t e c t u r e
d e t e r m in e s w h a t s o f t wa r e t h e p r o ce s s o r c a n r u n . Th e
a r ch it e ct u re of t h e Mob ile AMD-K6-2+ p r oce ssor is t h e
industry-standard x86 instruction set.
The term microarchitecture refers to the design techniques used
in t h e proce ssor t o reach t he ta rge t cost , pe rform ance, and
functionality goals. The Mobile AMD-K6 family of processors
are based on a sophisticated RISC core known as the Enhanced
R I S C 8 6 m i c r o a r c h i t e c t u r e . Th e E n h a n c e d R I S C 8 6
m icroa rch it e ct u re is a n a dva n ce d , se con d -orde r d e cou p le d
d e c o d e /e x e c u t i o n d e s i g n a p p r o a c h t h a t e n a b l e s
industry-leading performance for x86-based software.
The term design implem entation refers to the actual logic and
circuit designs from which the processor is created according to
the microarchitecture specifications.
Chapter 2
Internal Architecture
5
Preliminary Information
®
Mobile AMD-K6 -2+ Processor Data Sheet
23446B/0—June 2000
®
Enhanced RISC86
Microarchitecture
Th e E n h a n c e d R I S C 86 m i c r o a r ch i t e c t u r e d e f i n e s t h e
ch a ra ct e r ist ics of t h e AMD-K6 fa m ily of p roce ssors. Th e
innovative RISC86 microarchitecture approach implements the
x86 instruction set by internally translating x86 instructions
in t o R ISC86 op e r a t ion s. Th e se R ISC86 op e ra t ion s we re
sp e cia lly d e sign e d t o in clu d e d ire ct su p p or t for t h e x86
in st r u ct ion se t wh ile ob se r vin g t h e R ISC p e r for m a n ce
principles of fixed length encoding, regularized instru ction
fie ld s , a n d a la r ge r e gist e r se t . Th e E n h a n ce d R ISC86
microarchitecture used in the Mobile AMD-K6-2+ processor
e n ab le s h igh e r p roce ssor core p e r for m a n ce a n d p rom ot e s
straightforward extensions, such as those added in the current
Mobile AMD-K6-2+ processor and those planned for the future.
Instead of directly executing complex x86 instructions, which
have lengths of 1 to 15 bytes, the Mobile AMD-K6-2+ processor
e x e c u t e s t h e s i m p l e r a n d e a s i e r f i x e d -l e n g t h R I S C 8 6
o p e r a t i o n s , wh i l e m a i n t a i n i n g t h e i n s t r u c t i o n c o d i n g
efficiencies found in x86 programs.
The Mobile AMD-K6-2+ processor contains parallel decoders, a
ce nt ralized R ISC86 operation scheduler, and ten exe cution
units that support superscalar operation —multiple decode,
execution, and retirement —of x86 instructions. These elements
are packed into an aggressive and highly efficient six-stage
pipeline.
®
Mobile AMD-K6 -2+ Processor Block Diagram. As sh own in Figu re 1
on page 7, the high-performance, out-of-order execution engine
of t h e Mob ile AMD-K6-2+ p r oce ssor is m a t e d t o a sp lit ,
le ve l-on e , 64-Kb yt e , wr it e b a ck ca ch e wit h 32 Kb yt e s of
instruction cache and 32 Kbytes of data cache. Backing up the
leve l-on e ca ch e is a la r ge , u n ifie d , leve l-t wo, 128-Kbyt e ,
writeb a ck ca che . The level-one inst ruction ca che fe e ds the
decoders and, in turn, the decoders feed the scheduler. The ICU
issu e s a n d r e t ir e s R ISC86 op e r a t ion s con t a in e d in t h e
scheduler. The system bus int erface is an industry-standard
64-bit Super7 and Socket 7 demultiplexed bus.
Th e Mob ile AMD-K6-2+ p roce ssor com b in e s t h e la t e st in
p r oce ssor m icr oa r ch it e ct u r e t o p r ovid e t h e h igh e st x86
p e r for m a n ce for t od ay’s p e rson a l com p u t e rs. Th e Mob ile
AMD-K6-2+ processor offers true sixth-generation performance
and x86 binary software compatibility.
6
Internal Architecture
Chapter 2
Preliminary Information
®
23446B/0—June 2000
Mobile AMD-K6 -2+ Processor Data Sheet
32 KByte Level-One Instruction Cache
20 KByte Predecode Cache
64 Entry ITLB
Predecode
Logic
16 Byte Fetch
Level-One Cache
Branch Logic
(8192-Entry BHT)
(16-Entry BTC)
(16-Entry RAS)
Controller
Dual Instruction Decoders
x86 to RISC86
100 MHz
Super7™
Bus
Four RISC86
Decode
Interface
Out-of-Order
Execution Engine
Scheduler
Buffer
(24 RISC86)
Instruction
Control Unit
Branch
Resolution Unit
Six RISC86®
Operation Issue
Level-Two
Cache
(128 KByte)
Load
Unit
Store
Unit
Register Unit X
(Integer/
Floating- Point
Unit
Register Unit Y
(Integer/
Multimedia/3DNow!)
Multimedia/3DNow!TM
)
Store
Queue
Level-One Dual-Port Data Cache
(32 KByte)
128 Entry DTLB
®
Figure 1. Mobile AMD-K6 -2+ Processor Block Diagram
Decoders. De cod in g of t h e x86 in st r u ct ion s b e gin s wh e n t he
on-chip level-one instruction cache is filled. Predecode logic
determines the length of an x86 instruction on a byte-by-byte
basis. This predecode information is stored, along with the x86
instructions, in the level-one instruction cache, to be used later
by t h e d ecod e rs. The d ecod e rs t ran sla t e on-t h e -fly, wit h n o
additional latency, up to two x86 instructions per clock into
RISC86 operations.
Note: In this chapter, “clock” refers to a processor clock.
The Mobile AMD-K6-2+ processor categorizes x86 instructions
in t o t h re e t yp e s of d e cod e s—sh or t , lon g, a n d ve ct or. Th e
d e cod e rs p roce ss e it he r t wo sh or t , on e lon g, or on e ve ct or
decode at a time. The three types of decodes have the following
characteristics:
■ Short decodes—x86 instructions less than or equal to seven
bytes in length
■ Long decodes—x86 instructions less than or equal to 11
bytes in length
■ Vector decodes—complex x86 instructions
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Mobile AMD-K6 -2+ Processor Data Sheet
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Short and long decodes are processed completely within the
decoders. Vector decodes are started by the decoders and then
completed by fetched sequences from an on-chip ROM. After
decoding, the RISC86 operations are delivered to the scheduler
for dispatching to the executions units.
Scheduler/Instruction Control Unit. Th e ce n t r a lize d sch e d u le r or
buffer is managed by the Instruction Control Unit (ICU). The
ICU buffers and manages up to 24 RISC86 operations at a time.
This equals from 6 to 12 x86 instructions. This buffer size (24) is
perfectly matched to the processor’s six-stage RISC86 pipeline
and four RISC86-operations decode rate. The scheduler accepts
as many as four RISC86 operations at a time from the decoders
and retires up to four RISC86 operations per clock cycle. The
ICU is ca p ab le of simult a n e ou sly issu in g u p t o six R ISC86
operations at a time to the execution units. This consists of the
following types of operations:
■ Memory load operation
■ Memory store operation
■ Complex integer, MMX or 3DNow! register operation
■ Simple integer, MMX or 3DNow! register operation
■ Floating-point register operation
■ Branch condition evaluation
Registers. When managing the 24 RISC86 operations, the ICU
u se s 69 p h ysica l re gist e r s con t a in e d wit h in t h e R ISC86
microarchitecture. 48 of the physical registers are located in a
ge n e ra l re gist e r file a n d a re grou p e d a s 24 com m it t e d or
a rch it e ct u ra l re gist e rs p lu s 24 re n a m e re gist e rs. Th e 24
arch it ect u ra l regist ers consist of 16 scra t ch regist e rs and 8
registers that correspond to the x86 general-purpose registers—
EAX, EBX, ECX, EDX, EBP, ESP, ESI, and EDI. There is an
analogous set of registers specifically for MMX and 3DNow!
o p e r a t i o n s . Th e r e a r e 9 M M X /3 D N ow ! c o m m i t t e d o r
architectural registers plus 12 MMX/3DNow! rename registers.
The 9 architectural registers consist of one scratch register and
8 registers that correspond to the MMX registers (mm0–mm7).
For more detailed information, see the 3DNow!™ Technology
Manual, order# 21928.
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Mobile AMD-K6 -2+ Processor Data Sheet
Branch Logic. The Mobile AMD-K6-2+ processor is designed with
highly sophisticated dynamic branch logic consisting of the
following:
■ Branch history/Prediction table
■ Branch target cache
■ Return address stack
Th e Mob ile AMD-K6-2+ p roce ssor im p le m e n t s a t wo-leve l
b ra n ch p re d ict ion sch e m e b a se d on a n 8192-e n t ry b ra n ch
h ist ory t a b le . Th e b ra n ch h ist ory t a b le st ore s p re d ict ion
information that is used for predicting conditional branches.
Because the branch history table does not store predicted target
addresses, special address ALUs calculate target addresses
on-the-fly during instruction decode. The branch target cache
augme nt s predicte d branch perform ance by avoiding a one
clock cache-fetch penalty. This specialized target cache does
this by supplying the first 16 bytes of target instructions to the
decoders when branches a re predict e d. The re t urn address
stack is a unique device specifically designed for optimizing
CALL and RETURN pairs. In summary, the Mobile AMD-K6-2+
processor uses dynamic branch logic to minimize delays due to
the branch instructions that are common in x86 software.
3DNow!™ Technology. AMD has taken a lead role in improving the
multimedia and 3D capabilities of the x86 processor family with
the introduction of 3DNow! technology, which uses a packed,
sin gle -p r e cision , floa t in g-p oin t d a t a for m a t a n d Sin gle
In st r u ct ion Mu lt ip le Da t a (SIMD) op e ra t ion s b a se d on t h e
MMX technology model.
2.3
Cache, Instruction Prefetch, and Predecode Bits
Th e wr it eb a ck leve l-on e ca ch e on t h e Mob ile AMD-K6-2+
processor is organized as a separate 32-Kbyte instruction cache
and a 32-Kbyte data cache with two-way set associativity. The
level-two cache is 128 Kbytes, and is organized as a unified, four-
way set-associative cache. The cache line size is 32 bytes, and
lin e s a re fe t ch e d from ext e r n a l m e m ory u sin g a n e fficie n t
pipelined burst transaction. As the level-one instruction cache is
filled from the level-two cache or from external memory, each
instruction byte is analyzed for instruction boundaries using
predecoding logic. Predecoding annotates information (5 bits
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Preliminary Information
Mobile AMD-K6 -2+ Processor Data Sheet
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p e r b yt e ) t o e a ch in st r u ct ion byt e t h a t la t e r e n a b le s t h e
d e c o d e r s t o e f f i c i e n t ly d e c o d e m u l t i p l e i n s t r u c t i o n s
simultaneously.
Cache
Th e p roce ssor ca ch e d e sign t a ke s a dva n t a ge of a se ct ore d
organization (see Figure 2). Each sector consists of 64 bytes
configured as two 32-byte cache lines. The two cache lines of a
sect or share a common tag but have separate pairs of MESI
(Modified, Exclusive, Shared, Invalid) bits that track the state
of each cache line.
Two forms of cache misses and associated cache fills can take
place —a tag-miss cache fill and a tag-hit cache fill. In the case
of a tag-miss cache fill, the level-one cache miss is due to a tag
mismatch, in which case the required cache line is filled either
from t h e level-two cache or from ext ernal me mory, and t he
level-one cache line within the sector that was not required is
marked as invalid. In the case of a tag-hit cache fill, the address
ma tche s t h e t ag, but t he request ed ca che line is m arke d a s
invalid. The require d leve l-one ca che line is fille d from the
level-t wo cache or from externa l m emory, a nd the level-one
cache line within the sector that is not required remains in the
same cache state.
Prefetching
The Mobile AMD-K6-2+ processor conditionally performs cache
prefetching which results in the filling of the required cache
line first, and a prefetch of the second cache line making up the
other half of the sector. From the perspective of the external
bus, the two cache-line fills t ypically appear a s two 32-byte
b u rst re a d cycle s occu r r in g b a ck -t o-b a ck or, if a llowe d , a s
pipelined cycles.
Th e 3DNow! t e ch n ology in clu d e s a n in st r u ct ion ca lle d
PREFETCH that allows a cache line to be prefetched into the
level-one data cache and the level-two cache. The PREFETCH
i n s t r u c t i on fo r m a t i s d e f i n e d i n Ta b l e 1 5 , “ 3 D Now !™
Te ch n ology In st r u ct ion s,” on p a ge 83. For m ore d e t a ile d
in for m a t ion , se e t h e 3DNow!™ Tech n ology Ma nu a l, ord e r #
21928.
Predecode Bits
Decoding x86 instructions is particularly difficult because the
instructions are variable-length and can be from 1 to 15 bytes
long. Predecode logic supplies the five predecode bits that are
a ssocia t e d wit h e a ch in st r u ct ion byt e . Th e p re d e cod e b it s
in d ica t e t h e n u m b e r of byt e s t o t h e st a r t of t h e n e xt x86
in st r u ct ion . Th e p re d e cod e bit s a re st ore d in a n ext e n d e d
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Mobile AMD-K6 -2+ Processor Data Sheet
instruction cache alongside each x86 instruction byte as shown
in Figure 2. The predecode bits are passed with the instruction
byt e s t o t h e d e cod e rs wh e re t h ey a ssist wit h p a ra lle l x86
instruction decoding.
Tag
Address
Cache Line 0 Byte 31 Predecode Bits Byte 30 Predecode Bits ........ ........ Byte 0 Predecode Bits MESI Bits
Cache Line 1 Byte 31 Predecode Bits Byte 30 Predecode Bits ........ ........ Byte 0 Predecode Bits MESI Bits
Figure 2. Cache Sector Organization
2.4
Instruction Fetch and Decode
Instruction Fetch
The processor can fetch up to 16 bytes per clock out of the level-
on e in st r u ct ion ca ch e or b ra nch t a rge t ca che . The fe t ch e d
inform at ion is placed into a 16-byt e inst ruct ion buffer that
fe e d s d ire ct ly in t o t h e d e cod e rs (se e Figu re 3 on p a ge 12).
Fetching can occur along a single execution stream with up to
seven outstanding branches taken.
Th e in st r u ct ion fe t ch logic is ca p ab le of re t r ievin g a ny 16
cont iguous bytes of informa tion within a 32-byte boundary.
There is no additional penalty when the 16 bytes of instructions
lie a cross a ca che lin e b ou n d a ry. Th e in st r u ct ion byt e s a re
loaded into the instruction buffer as they are consumed by the
decoders. Although instructions can be consumed with byte
g r a n u l a r i t y, t h e i n s t r u c t i o n b u f f e r i s m a n a g e d o n a
m e m ory-a lign e d word (t wo byt e s) orga n iza t ion . The re fore ,
instructions are loaded and replaced with word granularity.
When a control transfer occurs —such as a J MP instruction —
the entire instruction buffer is flushed and reloaded with a new
set of 16 instruction bytes.
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Branch-Target Cache
16 x 16 Bytes
16 Bytes
32-Kbyte Level-One
Instruction Cache
16 Bytes
2:1
Branch Target
Address Adders
Return Address Stack
16 x 16 Bytes
Fetch Unit
16 Instruction Bytes
plus
16 Sets of Predecode Bits
Instruction Buffer
Figure 3. The Instruction Buffer
Instruction Decode
The Mobile AMD-K6-2+ processor decode logic is designed to
decode multiple x86 instructions per clock (see Figure 4 on
page 13). The decode logic accepts x86 instruction bytes and
their predecode bits from the instruction buffer, locates the
a c t u a l in st r u c t io n b o u n d a r ie s, a n d g e n e r a t e s R I SC 8 6
operations from these x86 instructions.
RISC86 operations are fixed-length internal instructions. Most
RISC86 operations execute in a single clock. RISC86 operations
are combined to perform every function of the x86 instruction
se t . Som e x86 in st ru ct ion s a re d e cod e d in t o a s few a s ze ro
R ISC86 op e ra t ion s —for in st a n ce a NOP —or on e R ISC86
op e ra t ion —a re gist e r -t o-re gist e r a d d . More com p le x x86
instructions are decoded into several RISC86 operations.
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Internal Architecture
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Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
Instruction Buffer
Short Decoder #1
Short Decoder #2
Long Decoder
On-Chip ROM
Vector Decoder
RISC86® Sequencer
Vector Address
4 RISC86 Operations
®
Figure 4. Mobile AMD-K6 -2+ Processor Decode Logic
Th e Mob ile AMD-K6-2+ p roce ssor u se s a com b in a t ion of
decoders to convert x86 instructions into RISC86 operations.
The hardware consists of three sets of decoders —two parallel
short decoders, one long decoder, and one vector decoder. The
two parallel short decoders translate the most commonly-used
x86 instructions ( moves, shifts, branches, ALU, FPU) and the
ext e n sion s t o t h e x86 in st r u ct ion se t (in clu d in g MMX a n d
3DNow! instructions) into zero, one, or two RISC86 operations
each. The short decoders only operate on x86 instructions that
are up to seven bytes long. In addition, they are designed to
d e c o d e u p t o t w o x 8 6 i n s t r u c t i o n s p e r c l o c k . T h e
commonly-used x86 instructions that are greater than seven
bytes but not more than 11 bytes long, and semi-commonly-used
x86 instructions that are up to seven bytes long are handled by
the long decoder.
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Th e lon g d e cod e r only p e r for m s on e de cod e p e r clock a n d
generates up to four RISC86 operations. All other translations
(complex instructions, serializing conditions, interrupts and
exceptions, etc.) are handled by a combination of the vector
d e cod e r a n d R ISC86 op e ra t ion se q u e n ce s fe t ch e d from a n
on-chip ROM. For complex operations, the vector decoder logic
provides the first set of RISC86 operations and a vector (initial
ROM address) to a sequence of further RISC86 operations. The
same types of RISC86 operations are fetched from the ROM as
those that are generated by the hardware decoders.
Note: Although all three sets of decoders are simultaneously fed a
copy of the instruction buffer contents, only one of the three
types of decoders is used during any one decode clock.
The decoders or the on-chip RISC86 ROM always generate a
group of four RISC86 operations. For decodes that cannot fill
the ent ire group with four RISC86 operations, RISC86 NOP
operations are placed in the empty locations of the grouping.
For example, a long-decoded x86 instruction that converts to
only three RISC86 operations is padded with a single RISC86
NOP op e ra tion a n d t h e n p a sse d t o t h e sch e d u le r. U p t o six
groups or 24 RISC86 operations can be placed in the scheduler
at a time.
All of the common, and a few of the uncommon, floating-point
in struct ions (also known as ESC instructions) are hardware
d ecode d as short de codes. This decode genera tes a RISC86
floa t in g-p oin t op e r a t ion a n d , op t ion a lly, a n a ssocia t e d
floating-point load or store operation. Floating-point or ESC
instruction decode is only allowed in the first short decoder, but
non-ESC instructions can be decoded simultaneously by the
second short decoder along with an ESC instruction decode in
the first short decoder.
All of the MMX and 3DNow! instructions, with the exception of
t h e E MMS, F E MMS, a n d P R E F E TCH in st r u ct ion s, a r e
h a rdwa re d e cod e d a s short d e cod e s. Th e MMX in st r uct ion
decode generates a RISC86 MMX operation and, optionally, an
associated MMX load or store operation. A 3DNow! instruction
decode generates a RISC86 3DNow! operation and, optionally,
a n a ssocia t e d loa d or st ore op e ra t ion . MMX a n d 3DNow!
in st r u ct ion s ca n b e d e cod e d in e it h e r or b ot h of t h e sh or t
decoders.
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Internal Architecture
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Mobile AMD-K6 -2+ Processor Data Sheet
2.5
Centralized Scheduler
The scheduler is the heart of the Mobile AMD-K6-2+ processor
(see Figu re 5 on page 16). It contains the logic necessary to
m a n a ge ou t -of-ord e r e xe cu t ion , d a t a for wa rd in g, re gist e r
re n a m in g, sim u lt a n e ou s issu e a n d re t ire m e n t of mu lt ip le
RISC86 operations, and speculative execution. The scheduler’s
buffer can hold up to 24 RISC86 operations. This equates to a
m a ximu m of 12 x86 in st r u ct ion s. Th e sch e d u le r ca n issu e
RISC86 operations from any of the 24 locations in the buffer.
When possible, the scheduler can simultaneously issue a RISC86
operation to any available execution unit (store, load, branch,
register X integer/multimedia, register Y integer/multimedia, or
floating-point). In total, the scheduler can issue up to six and
retire up to four RISC86 operations per clock.
The main advantage of the scheduler and its operation buffer is
the ability to examine an x86 instruction window equal to 12
x86 instructions at one time. This advantage is due to the fact
t h a t t h e sch e d u le r op e ra t e s on t h e R ISC86 op e ra t ion s in
parallel and allows the Mobile AMD-K6-2+ processor to perform
dynamic on-the-fly instruction code scheduling for optimized
execution. Although the scheduler can issue RISC86 operations
for out-of-order execution, it always retires x86 instructions in
order.
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Preliminary Information
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Mobile AMD-K6 -2+ Processor Data Sheet
23446B/0—June 2000
From Decode Logic
RISC86 #1
RISC86 #2
RISC86 #0
RISC86 #3
Centralized RISC86®
Operation Scheduler
RISC86 Issue Buses
RISC86 Operation Buffer
®
Figure 5. Mobile AMD-K6 -2+ Processor Scheduler
2.6
Execution Units
Th e Mob ile AMD-K6-2+ p r oce ssor con t a in s t e n p a ra lle l
execution units —store, load, integer X ALU, integer Y ALU,
MMX ALU (X), MMX ALU (Y), MMX/3DNow! mu lt ip lie r,
3DNow! ALU, floating-point, and branch condition. Each unit is
independent and capable of handling the RISC86 operations.
Tab le 1 on p a ge 17 d e t a ils t h e e xe cu t ion u n it s, fu n ct ion s
performed within these units, operation latency, and operation
throughput.
Th e st ore a nd load exe cut ion unit s are t wo-st a ge pipelined
d e sign s. Th e st ore u n it p e r for m s d a t a wr it e s a n d re gist e r
calculation for LEA/PUSH. Data memory and register writes
from stores are available after one clock. Store operations are
h e ld in a st ore q u e u e p r ior t o exe cu t ion. From t h e re , t h ey
execute in order. The load unit performs data memory reads.
Data is available from the load unit after two clocks.
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Th e I n t e g e r X e x e c u t io n u n it c a n o p e r a t e o n a ll A L U
operations, multiplies, divides (signed and unsigned), shifts,
and rotates.
The Integer Y execution unit can operate on the basic word and
d ou b leword ALU op e ra t ion s —ADD, AND, CMP, OR , SU B,
XOR, zero-extend and sign-extend operands.
Table 1. Execution Latency and Throughput of Execution Units
Functional Unit
Store
Function
LEA/PUSH, Address (Pipelined)
Memory Store (Pipelined)
Memory Loads (Pipelined)
Integer ALU
Latency Throughput
1
1
1
1
Load
2
1
1
1
Integer X
Integer Multiply
2–3
1
2–3
1
Integer Shift
MMX ALU
1
1
Multimedia
(processes
MMX instructions)
MMX Shifts, Packs, Unpack
MMX Multiply
1
1
2
1
Integer Y
Branch
FPU
Basic ALU (16-bit and 32-bit operands)
Resolves Branch Conditions
FADD, FSUB, FMUL
3DNow! ALU
1
1
1
1
2
2
2
1
3DNow!
3DNow! Multiply
2
1
3DNow! Convert
2
1
Register X and Y
Pipelines
Th e f u n c t i o n a l u n it s t h a t e x e c u t e M M X a n d 3 D N ow !
in st r u ct ion s sh a re p ip e lin e con t rol wit h t h e Int e ge r X a n d
Integer Y units.
The register X and Y functional units are attached to the issue
bus for the register X execution pipeline or the issue bus for the
register Y execution pipeline or both. Each register pipeline
has dedicated resources that consist of an integer execution
u n it a n d a n MMX ALU exe cu t ion u n it , t h e re fore a llowin g
superscalar opera tion on inte ger a nd MMX instruct ions. In
addition, both the X and Y issue buses are connected to the
3DNow! ALU, the MMX/3DNow! multiplier and MMX shifter,
which allows the appropriate RISC86 operation to be issued
through either bus. Figure 6 on page 18 shows the details of the
X and Y register pipelines.
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Mobile AMD-K6 -2+ Processor Data Sheet
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Scheduler
Buffer
(24 RISC86® Operations)
Issue Bus
for the
Issue Bus
for the
Register X
Execution
Pipeline
Register Y
Execution
Pipeline
Integer X
MMX
ALU
MMX
Shifter
3DNow!
ALU
MMX
ALU
Integer Y
MMX/
3DNow!
Multiplier
ALU
ALU
Figure 6. Register X and Y Functional Units
Th e b ra n ch con d it ion u n it is se p a r a t e fr om t h e b r a n ch
prediction logic in that it resolves conditional branches such as
J CC and LOOP after the branch condition has been evaluated.
2.7
Branch-Prediction Logic
Sophisticated branch logic that can minimize or hide the impact
of ch a n ge s in p r ogra m flow is d e sign e d in t o t h e Mob ile
AMD-K6-2+ p r oce ssor. Bra n ch e s in x86 cod e fit in t o t wo
ca t e gor ie s —u n con d it ion a l b ra n ch e s, wh ich a lways ch a n ge
p rogra m flow (t h a t is, t h e b ra n ch e s a re a lways t a ke n ) a n d
conditional branches, which may or may not divert program
flow (t h a t is, t h e b ra n che s are t aken or n ot -t a ke n ). When a
conditional branch is not taken, the processor simply continues
decoding and executing the next instructions in memory.
Typical applications have up to 10% of unconditional branches
a nd a nothe r 10% to 20% conditiona l bra nche s. The Mobile
AMD-K6-2+ processor branch logic has been designed to handle
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t h is t yp e of p rogra m b e h avior a n d it s n e ga t ive e ffe ct s on
instruction execution, such as stalls due to delayed instruction
fetching and the draining of the processor pipeline. The branch
logic contains an 8192-entry branch history table, a 16-entry by
16-byte branch target cache, a 16-entry return address stack,
and a branch execution unit.
Branch History Table
Th e Mob ile AMD-K6-2+ p roce ssor h a n d le s u n con d it ion a l
b ra n ch e s wit h ou t a ny p e n a lt y by re d ire ct in g in st r u ct ion
fe t ch in g to the t a rge t a ddre ss of t he uncon dit iona l bra nch.
However, conditional branches require the use of the dynamic
branch-prediction mechanism built into the Mobile AMD-K6-2+
p r o c e s s o r. A t wo -l e ve l a d a p t ive h i s t o r y a l g o r i t h m i s
implemented in an 8192-entry branch history table. This table
st ore s e xe cu t e d b ra n ch in for m a t ion , p re d ict s in d ivid u a l
branches, and predicts the behavior of groups of branches. To
a ccom m od a t e t h e la rge b ra n ch h ist ory t ab le , t h e Mob ile
A MD -K 6 -2 + p r o c e sso r d o e s n o t st o r e p r e d ic t e d t a r g e t
addresses. Instead, the branch target addresses are calculated
on-t he -fly using ALUs during the de code sta ge . The a dde rs
calculate all possible target addresses before the instructions
are fully decoded and the processor chooses which addresses
are valid.
Branch Target Cache
To avoid a on e clock ca ch e -fe t ch p e n a lt y wh e n a b ra n ch is
predicted taken, a built-in branch target cache supplies the first
16 byt e s of in st r u ct ion s d ire ct ly t o t h e in st r u ct ion b u ffe r
(assuming the target address hits this cache). (See Figure 3 on
page 12.) The branch target cache is organized as 16 entries of
16 bytes. In total, the branch prediction logic achieves branch
prediction rates greater than 95% .
Return Address Stack
Th e re t u r n a d d re ss st a ck is a sp e cia l d evice d e sign e d t o
optimize CALL and RET pairs. Software is typically compiled
with subroutines that are frequently called from various places
in a program. This is usually done to save space. Entry into the
subroutine occurs with the execution of a CALL instruction. At
t h a t t im e , t h e p r oce ssor p u sh e s t h e a d d re ss of t h e n e xt
instruction in memory following the CALL instruction onto the
st a ck (a lloca t e d sp a ce in m e m or y). Wh e n t h e p r oce ssor
e n cou n t e rs a R E T in st r u ct ion (wit h in or a t t h e e n d of t h e
subroutine), the branch logic pops the address from the stack
and begins fetching from that location. To avoid the latency of
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main memory accesses during CALL and RET operations, the
return address stack caches the pushed addresses.
Branch Execution
Unit
Th e b ra n ch e xe cu t ion u n it e n a b le s e fficie n t sp e cu la t ive
execution. This unit gives the processor the ability to execute
in st r u ct ion s b eyon d con d it ion a l b ra n ch e s b e fore k n owin g
wh e t h e r t h e b ra n ch p re d ict ion wa s cor re ct . Th e Mob ile
AMD-K6-2+ processor does not permanently update the x86
registers or memory locations until all speculatively executed
conditional branch instructions are resolved. When a prediction
is in cor re ct , t h e p r oce ssor b a ck s ou t t o t h e p oin t of t h e
mispredicted branch instruction and restores all registers. The
Mob i le AMD-K6-2+ p r oce s sor ca n su p p or t u p t o se ve n
outstanding branches.
20
Internal Architecture
Chapter 2
Preliminary Information
®
23446B/0—June 2000
Mobile AMD-K6 -2+ Processor Data Sheet
3
Software Environment
Th is ch a p t e r p r ovid e s a ge n e ra l ove r vie w of t h e Mob ile
AMD-K6-2+ processor’s x86 software environment and briefly
describes the data types, registers, operating modes, interrupts,
and instructions supported by the Mobile AMD-K6-2+ processor
architecture and design implementation.
The Mobile AMD-K6-2+ processor implements t he same ten
MSRs as the Mobile AMD-K6-2-P processor Model 8, and the
bits and fields within these ten MSRs are defined identically.
Th e Mob ile AMD-K6-2+ p roce ssor su p p or t s t wo a dd it iona l
MSRs for a total of twelve MSRs.
See “Model-Specific Registers (MSR)” on page 37 for the MSR
definitions.
3.1
Registers
Th e Mobile AMD-K6-2+ processor cont ains all t he registers
defined by the x86 architecture, including general-purpose,
segment, floating-point, MMX/3DNow! technology, EFLAGS,
control, task, debug, test, and descriptor/memory-management
registers. In addition, this chapter provides information on the
Mobile AMD-K6-2+ processor MSRs.
Note: Areas of the register designated as Reserved should not be
modified by software.
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Software Environment
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Preliminary Information
Mobile AMD-K6 -2+ Processor Data Sheet
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23446B/0—June 2000
General-Purpose
Registers
The eight 32-bit x86 general-purpose registers are used to hold
integer data or memory pointers used by instructions. Table 2
con t a in s a list of t h e ge n e r a l-p u r p ose re gist e r s a n d t h e
functions for which they are used.
Table 2. General-Purpose Registers
Register
Function
EAX Commonly used as an accumulator
EBX Commonly used as a pointer
ECX Commonly used for counting in loop operations
EDX Commonly used to hold I/O information and to pass parameters
EDI
ESI
Commonly used as a destination pointer by the ES segment
Commonly used as a source pointer by the DS segment
Used to point to the stack segment
ESP
EBP
Used to point to data within the stack segment
In order to support byte and word operations, EAX, EBX, ECX,
a nd EDX ca n a lso be use d a s 8-bit a nd 16-bit re giste rs. The
shorter registers are overlaid on the longer ones. For example,
th e n a me of the 16-bit version of E AX is AX (low 16 b it s of
EAX) and the 8-bit names for AX are AH (high order bits) and
AL (low order bits). The same naming convention applies to
EBX, ECX, and EDX. EDI, ESI, ESP, and EBP can be used as
smaller 16-bit registers called DI, SI, SP, and BP respectively,
but these registers do not have 8-bit versions. Figure 7 shows the
EAX register with its name components, and Table 3 lists the
d ou b le word (32-b it ) ge n e ra l-p u r p ose re gist e r s a n d t h e ir
corresponding word (16-bit) and byte (8-bit) versions.
31
16 15
8
7
0
EAX
AX
AL
AH
Figure 7. EAX Register with 16-Bit and 8-Bit Name Components
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Mobile AMD-K6 -2+ Processor Data Sheet
Table 3. General-Purpose Register Doubleword, Word, and Byte Names
32-Bit Name
(Doubleword)
16-Bit Name
(Word)
8-Bit Name
(High-order Bits) (Low-order Bits)
8-Bit Name
EAX
EBX
ECX
EDX
EDI
AX
BX
CX
DX
DI
AH
BH
CH
DH
–
AL
BL
CL
DL
–
ESI
SI
–
–
ESP
EBP
SP
BP
–
–
–
–
Integer Data Types
Four types of data are used in general-purpose registers—byte,
word, doubleword, and quadword integers. Figure 8 shows the
format of the integer data registers.
Byte Integer
7
0
Precision —
8 Bits
Word Integer
15
0
Precision — 16 Bits
Doubleword Integer
31
0
Precision — 32 Bits
Quadword Integer
63
0
Precision — 64 Bits
Figure 8. Integer Data Registers
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Software Environment
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Preliminary Information
Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
Segment Registers
The six 16-bit segment registers are used as pointers to areas
(segments) of memory. Table 4 lists the segment registers and
their functions. Figure 9 shows the format for all six segment
registers.
Table 4. Segment Registers
Segment
Segment Register Function
Register
CS
DS
ES
FS
GS
SS
Code segment, where instructions are located
Data segment, where data is located
Data segment, where data is located
Data segment, where data is located
Data segment, where data is located
Stack segment
15
0
Figure 9. Segment Register
Segment Usage
The operating system determines the type of memory model
that is implemented. The segment register usage is determined
by t h e op e ra t in g syst e m ’s m e m ory m od e l. In a R e a l m od e
memory model the segment register points to the base address
in memory. In a Protected mode memory model the segment
register is called a selector and it selects a segment descriptor
in a descriptor table. This descriptor contains a pointer to the
b a se of t h e se gm e n t , t h e lim it of t h e se gm e n t , a n d va r iou s
p rot e ct ion a t t r ib u t e s. For m ore in for m a t ion on d e scr ip t or
formats, see “Descriptors and Gates” on page 51. Figure 10 on
pa ge 25 shows segm ent usage for R eal mode and Prot ected
mode memory models.
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Software Environment
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23446B/0—June 2000
Mobile AMD-K6 -2+ Processor Data Sheet
Physical Memory
Segment Base
Segment Register
Real Mode Memory Model
Descriptor Table
Physical Memory
Base
Limit
Base
Base
Limit
Segment Base
Segment Selector
Protected Mode Memory Model
Figure 10. Segment Usage
Instruction Pointer
The instruction pointer (EIP or IP) is used in conjunction with
t h e cod e se gm e nt re gist e r (CS). Th e in st r u ct ion p oin t e r is
either a 32-bit register (EIP) or a 16-bit register (IP) that keeps
track of where the next instruction resides within memory. This
register cannot be directly manipulated, but can be altered by
modifying return pointers when a J MP or CALL instruction is
used.
Floating-Point
Registers
The floating-point execution unit in the Mobile AMD-K6-2+
processor is designed to perform mathematical operations on
non-integer numbers. This floating-point unit conforms to the
IEEE 754 and 854 standards and uses several registers to meet
t h e se st a n d a rd s —e igh t num e r ic floa t in g-p oin t re gist e rs, a
st atus word register, a cont rol word register, and a tag word
register.
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Software Environment
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Preliminary Information
Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
The eight floating-point registers are physically 80 bits wide
and labeled FPR0–FPR7. Figure 11 shows the format of these
floa t in g-p oint re gist ers. See “ F loat in g-Point R e gist e r Da t a
Types” on page 28 for information on allowable floating-point
data types.
79 78
Sign
64 63
0
Exponent
Significand
Figure 11. Floating-Point Register
The 16-bit FPU status word register contains information about
the state of the floating-point unit. Figure 12 shows the format
of this register.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
C
2
C C
E
S
S
F
P
E
U O Z
I
E
C
3
D
E
B
TOSP
1
0
E
E E
Symbol
B
C3
TOSP
C2
C1
C0
ES
SF
Description
FPU Busy
Bits
15
14
13–11
10
9
8
7
6
Condition Code
Top of Stack Pointer
Condition Code
Condition Code
Condition Code
Error Summary Status
Stack Fault
Exception Flags
Precision Error
Underflow Error
Overflow Error
Zero Divide Error
Denormalized Operation Error 1
Invalid Operation Error
TOSP Information
000 = FPR0
PE
UE
OE
ZE
DE
IE
5
4
3
2
0
111 = FPR7
Figure 12. FPU Status Word Register
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Mobile AMD-K6 -2+ Processor Data Sheet
The FPU control word register allows a programmer to manage
the FPU processing options. Figure 13 shows the format of this
register.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Y
R
C
P
C
P
U O Z
I
M
D
M
M M M M
Reserved
Symbol
Y
Description
Infinity Bit (80287 compatibility) 12
Bits
RC
PC
Rounding Control
Precision Control
Exception Masks
Precision
Underflow
Overflow
Zero Divide
Denormalized Operation
Invalid Operation
11–10
9–8
PM
UM
OM
ZM
DM
IM
5
4
3
2
1
0
Rounding Control Information
Precision Control Information
00b = 24 bits Single Precision Real
01b = Reserved
10b = 53 bits Double Precision Real
11b = 64 bits Extended Precision Real
00b = Round to the nearest or even number
01b = Round down toward negative infinity
10b = Round up toward positive infinity
11b = Truncate toward zero
Figure 13. FPU Control Word Register
Th e F P U t a g word re gist e r con t a in s in for m a t ion ab ou t t h e
registers in the register stack. Figure 14 shows the format of this
register.
15
14 13
12 11
10 9
8 7
6 5
4 3
2 1
0
TAG
(FPR7)
TAG
TAG
TAG
TAG
TAG
TAG
TAG
(FPR6) (FPR5) (FPR4) (FPR3) (FPR2) (FPR1) (FPR0)
Tag Values
00 = Valid
01 = Zero
10 = Special
11 = Empty
Figure 14. FPU Tag Word Register
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Preliminary Information
Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
Floating-Point
Register Data Types
F loa t in g-p oint re gist e rs u se fou r d iffe re n t t yp e s of d a t a —
packed decimal, single-precision real, double-precision real,
a n d e xt e n d e d -p re cision re a l. Figu re s 15 a n d 16 sh ow t h e
formats for these registers.
79 78 72 71
Ignore
0
S
or
Zero
Precision — 18 Digits, 72 Bits Used, 4-Bits/Digit
Description
Ignored on Load, Zeros on Store 78-72
Sign Bit 79
Bits
Figure 15. Packed Decimal Data Register
31 30
23 22
0
Single-Precision Real
Biased
Exponent
Significand
S
S=SignBit
Double-Precision Real
63 62
S
52 51
0
Biased
Exponent
Significand
S=SignBit
Extended-Precision Real
79 78
S
64 63 62
0
Biased
Exponent
I
Significand
S=SignBit
I = Integer Bit
Figure 16. Precision Real Data Registers
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Software Environment
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Mobile AMD-K6 -2+ Processor Data Sheet
MMX™/3DNow!™
Technology Registers
Th e Mob ile AMD-K6-2+ p roce ssor im p le m e n t s e igh t 64-b it
MMX/3DNow! registers for use by multimedia software. These
registers are mapped on the floating-point register stack. The
MMX and 3DNow! instructions refer to these registers as mm0
to mm7. Figure 17 shows the format of these registers. For more
®
information, see the AMD-K6 Processor Multimedia Technology
Manual, order# 20726 and the 3DNow!™ Technology Manual,
order# 21928.
63
0
mm0
mm1
mm2
mm3
mm4
mm5
mm6
mm7
Figure 17. MMX™/3DNow!™ Technology Registers
MMX™ Technology
Data Types
For the MMX instructions, the MMX registers use three types of
data —packed eight-byte integer, packed quadword integer, and
packed dual doubleword integer. Figure 18 on page 30 shows the
format of these data types.
Chapter 3
Software Environment
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Preliminary Information
®
Mobile AMD-K6 -2+ Processor Data Sheet
23446B/0—June 2000
Packed Bytes Integer
63
56 55
48 47
40 39
32 31
32 31
32 31
24 23
16 15
8
7
0
0
0
Byte 7
Byte 6
Byte 5
Byte 4
Byte 3
Byte 2
Byte 1
Byte 0
Packed Words Integer
63
48 47
16 15
Word 3
Word 2
Word 1
Word 0
Packed Doubleword Integer
63
Doubleword 1
Doubleword 0
Figure 18. MMX™ Technology Data Types
3DNow!™ Technology
Data Types
For 3DNow! in st r u ct ion s, t h e MMX/3DNow! re gist e rs u se
packed single-precision real data. Figure 19 shows the format of
the 3DNow! data type.
Packed Single Precision Floating Point
0
63 62
S
55 54
32 31 30
23 22
Biased
Exponent
Biased
Exponent
S
Significand
Significand
S=SignBit
S=SignBit
Figure 19. 3DNow!™ Technology Data Types
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Software Environment
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Mobile AMD-K6 -2+ Processor Data Sheet
EFLAGS Register
Th e EF LAGS re gist e r p rovid e s for t h re e d iffe re n t t yp e s of
flags —system, control, and status. The system flags provide
operating system controls, the control flag provides directional
information for string operations, and the status flags provide
information resulting from logical and arithmetic operations.
Figure 20 shows the format of this register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
I
V V
O
P
L
I
D
A V R
C M F
N
T
O D
I
F
T
F
S
F
Z
F
A
F
P
F
C
F
I
I
F
F
P
F
Reserved
Symbol
ID
Description
ID Flag
Bits
21
VIP
VIF
AC
VM
RF
NT
IOPL
OF
DF
IF
Virtual Interrupt Pending 20
Virtual Interrupt Flag
Alignment Check
Virtual-8086 Mode
Resume Flag
Nested Task
I/O Privilege Level
Overflow Flag
Direction Flag
Interrupt Flag
Trap Flag
19
18
17
16
14
13–12
11
10
9
TF
8
SF
Sign Flag
7
ZF
Zero Flag
6
AF
PF
Auxiliary Flag
Parity Flag
4
2
CF
Carry Flag
0
Figure 20. EFLAGS Registers
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Software Environment
31
Preliminary Information
Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
Control Registers
Th e five con t rol re gist e rs con t a in syst e m con t rol b it s a n d
p oin t e rs. Figu re s 21 t h rou gh 25 sh ow t he for m a t s of t h e se
registers.
31
7
6
5
4
3
2
1
0
M
C
E
P
S
E
T
S
D
P
V
D
E
V M
I
E
Reserved
Symbol
MCE
PSE
Description
Machine Check Enable
Page Size Extensions
Bit
6
4
DE
TSD
PVI
Debugging Extensions
Time Stamp Disable
Protected Virtual Interrupts
Virtual-8086 Mode Extensions
3
2
1
0
VME
Figure 21. Control Register 4 (CR4)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Page Directory Base
8
7
6
5
4
3
2
1
0
P
W
T
P
C
D
Reserved
Symbol
PCD
PWT
Description
Page Cache Disable
Page Writethrough
Bit
4
3
Figure 22. Control Register 3 (CR3)
31
0
Page Fault Linear Address
Figure 23. Control Register 2 (CR2)
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23446B/0—June 2000
31
Mobile AMD-K6 -2+ Processor Data Sheet
0
Reserved
Figure 24. Control Register 1 (CR1)
Symbol Description
Bit
31
30
29
PG
Paging
CD
NW
Cache Disable
Not Writethrough
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
P
C N
A
M
W
P
N
E
E T E M P
T S M P E
G D W
Reserved
Symbol
AM
WP
NE
ET
TS
EM
MP
PE
Description
Alignment Mask
Write Protect
Numeric Error
Extension Type
Task Switched
Emulation
Bit
18
16
5
4
3
2
1
0
Monitor Co-processor
Protection Enabled
Figure 25. Control Register 0 (CR0)
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Preliminary Information
Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
Debug Registers
Figu re s 26 t h r ou gh 29 sh ow t h e 32-b it d e b u g r e gist e r s
supported by the processor.
Symbol
LEN 3
R/W 3
LEN 2
R/W 2
LEN 1
R/W 1
LEN 0
R/W 0
Description
Length of Breakpoint #3
Bits
31–30
Type of Transaction(s) to Trap 29–28
Length of Breakpoint #2 27–26
Type of Transaction(s) to Trap 25–24
Length of Breakpoint #1 23–22
Type of Transaction(s) to Trap 21–20
Length of Breakpoint #0 19–18
Type of Transaction(s) to Trap 17–16
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G
D
G
E
L G
L
3
L
2
L G L G
L
0
LEN
3
R/W LEN R/W LEN R/W LEN R/W
E
3
2
1
1 0
3
2
2
1
1
0
0
Reserved
Symbol
GD
GE
LE
Description
General Detect Enabled
Global Exact Breakpoint Enabled
Local Exact Breakpoint Enabled
Bit
13
9
8
G3
L3
G2
L2
G1
L1
G0
L0
Global Exact Breakpoint # 3 Enabled
Local Exact Breakpoint # 3 Enabled
Global Exact Breakpoint # 2 Enabled
Local Exact Breakpoint # 2 Enabled
Global Exact Breakpoint # 1 Enabled
Local Exact Breakpoint # 1 Enabled
Global Exact Breakpoint # 0 Enabled
Local Exact Breakpoint # 0 Enabled
7
6
5
4
3
2
1
0
Figure 26. Debug Register DR7
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Mobile AMD-K6 -2+ Processor Data Sheet
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23446B/0—June 2000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
B
D
B
S
B B B
B
0
B
T
3
2
1
Reserved
Symbol
BT
BS
Description
Breakpoint Task Switch
Breakpoint Single Step
Bit
15
14
BD
B3
B2
B1
B0
Breakpoint Debug Access Detected 13
Breakpoint #3 Condition Detected
Breakpoint #2 Condition Detected
Breakpoint #1 Condition Detected
Breakpoint #0 Condition Detected
3
2
1
0
Figure 27. Debug Register DR6
DR5
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reserved
8
7
6
5
4
3
2
1 0
DR4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reserved
8
7
6
5
4
3
2
1 0
Figure 28. Debug Registers DR5 and DR4
Chapter 3
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Preliminary Information
®
Mobile AMD-K6 -2+ Processor Data Sheet
23446B/0—June 2000
DR3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1 0
Breakpoint 3 32-bit Linear Address
DR2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1 0
Breakpoint 2 32-bit Linear Address
DR1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1 0
Breakpoint 1 32-bit Linear Address
DR0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Breakpoint 0 32-bit Linear Address
Figure 29. Debug Registers DR3, DR2, DR1, and DR0
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Mobile AMD-K6 -2+ Processor Data Sheet
Model-Specific
Registers (MSR)
The Mobile AMD-K6-2+ processor provides twelve MSRs. The
value in the ECX register selects the MSR to be addressed by
the RDMSR and WRMSR instructions. The values in EAX and
E DX a re u se d a s in p u t s a n d ou t p u t s by t h e R DMSR a n d
W R M S R i n s t r u ct i o n s . Ta b l e 5 l i s t s t h e M S R s a n d t h e
corresponding value of the ECX register. Figures 30 through 42
show the MSR formats.
®
Table 5. Mobile AMD-K6 -2+ Processor MSRs
Model-Specific Register
Machine Check Address Register (MCAR)
Machine Check Type Register (MCTR)
Test Register 12 (TR12)
Value of ECX
00h
01h
0Eh
Time Stamp Counter (TSC)
10h
Extended Feature Enable Register (EFER)
C000_0080h
SYSCALL/SYSRET Target Address Register (STAR) C000_0081h
Write Handling Control Register (WHCR) C000_0082h
UC/WC Cacheability Control Register (UWCCR) C000_0085h
Processor State Observability Register (PSOR)
Page Flush/Invalidate Register (PFIR)
Level-2 Cache Array Register (L2AAR)
C000_0087h
C000_0088h
C000_0089h
Enhanced Power Management Register (EPMR) C000_0086h
®
For more information about the MSRs, see the Mobile AMD-K6
Processor BIOS Design Guide Application Note, order# 23015.
Fo r m o r e i n for m a t i o n a b o u t t h e R DM S R a n d W R M S R
instructions, see the AMD K86™ Family BIOS and Software Tools
Development Guide, order# 21062.
MCAR and MCTR. Th e Mob ile AMD-K6-2+ p roce ssor d oe s n ot
support the generation of a machine check exception. However,
t h e p rocessor d oe s p rovid e a 64-b it m a chin e che ck a dd re ss
register (MCAR), a 64-bit machine check type register (MCTR),
and a machine check enable (MCE) bit in CR4. Because the
p roce ssor d oe s n ot su p p or t m a ch in e ch e ck exce p t ion s, t he
con t e n t s of t h e MCAR a n d MCTR a re on ly a ffe ct e d by t he
WRMSR instruction and by RESET being sampled asserted
(where all bits in each register are reset to 0).
Chapter 3
Software Environment
37
Preliminary Information
®
Mobile AMD-K6 -2+ Processor Data Sheet
23446B/0—June 2000
63
0
MCAR
Figure 30. Machine-Check Address Register (MCAR)
63
5
4
0
MCTR
Reserved
Figure 31. Machine-Check Type Register (MCTR)
Test Register 12 (TR12). Te st re gist e r 12 p rovid e s a m e t h od for
disabling the L1 caches. Figure 32 shows the format of TR12.
63
4
2
1
0
3
C
I
Symbol Description
CI Cache Inhibit Bit
Bit
3
Reserved
Figure 32. Test Register 12 (TR12)
Time Stamp Counter. W i t h e a ch p r o c e s s o r c l o c k cy c l e , t h e
processor increments the 64-bit time stamp counter (TSC) MSR.
Figure 33 shows the format of the TSC.
63
0
TSC
Figure 33. Time Stamp Counter (TSC)
38
Software Environment
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23446B/0—June 2000
Mobile AMD-K6 -2+ Processor Data Sheet
Extended Feature Enable Register (EFER). T h e E x t e n d e d F e a t u r e
Enable Register (EFER) contains the control bits that enable
the extended features of the processor. Figure 34 shows the
format of the EFER register, and Table 6 defines the function of
each bit of the EFER register.
63
5
4
3
2
1
0
S
C
E
L
2
D
D
P
E
EWBEC
Reserved
Symbol
L2D
EWBEC
DPE
Description
L2 Cache Disable
EWBE Control
Data Prefetch Enable
System Call Extension
Bit
4
3-2
1
0
SCE
Figure 34. Extended Feature Enable Register (EFER)—MSR C000_0080h
Table 6. Extended Feature Enable Register (EFER)
Bit
Description
R/W
Function
Writing a 1 to any reserved bit causes a general protection fault to occur. All
reserved bits are always read as 0.
63–5
Reserved
R
If L2D is set to 1, the L2 cache is completely disabled. This bit is provided for
debug and testing purposes. For normal operation and maximum
performance, this bit must be set to 0 (this is the default setting following
reset).
4
L2D
R/W
This 2-bit field controls the behavior of the processor with respect to the
ordering of write cycles and the EWBE# signal. EFER[3] and EFER[2] are
Global EWBE Disable (GEWBED) and Speculative EWBE Disable (SEWBED),
respectively.
3-2
EWBE Control (EWBEC) R/W
DPE must be set to 1 to enable data prefetching (this is the default setting
following reset). If enabled, cache misses initiated by a memory read within
a 32-byte line are conditionally followed by cache-line fetches of the other
line in the 64-byte sector.
Data Prefetch Enable
1
0
R/W
(DPE)
System Call Extension
SCE must be set to 1 to enable the usage of the SYSCALL and SYSRET
instructions.
R/W
(SCE)
For m ore in for m a t ion on EWBE C, se e “ EWBE Con t rol” on
page 217.
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SYSCALL/SYSRET Target Address Register (STAR).
Th e SYSCALL/SYSR E T t a r ge t a d d r e ss r e gist e r (STAR )
con t a in s t h e t a r ge t E IP a d d r e ss u se d b y t h e SYSCALL
in st r u ct ion a n d t h e 16-bit cod e a n d st a ck segm e n t sele ct or
bases used by the SYSCALL and SYSRET instructions. Figure
35 shows the format of the STAR register, and Table 7 defines
t h e fu n ct ion of e a ch b it of t h e STAR r e gist e r. For m ore
in for m a t ion , se e t h e SYSCALL a n d SYSRET In st r u ct ion
Specification Application Note, order# 21086.
63
32 31
0
48 47
SYSRET CS Selector and SS
Selector Base
SYSCALL CS Selector and SS
Selector Base
Target EIP Address
Figure 35. SYSCALL/SYSRET Target Address Register (STAR)
Table 7. SYSCALL/SYSRET Target Address Register (STAR) Definition
Bit
Description
R/W
R/W
R/W
R/W
63–48 SYSRET CS and SS Selector Base
47–32 SYSCALL CS and SS Selector Base
31–0 Target EIP Address
Write Handling Control Register (WHCR). The Write Handling Control
Register (WHCR) is a MSR that contains two fields—the Write
Allocate Enable Limit (WAELIM) field, and the Write Allocate
Enable 15-to-16-Mbyte (WAE15M) bit (see Figure 36). For more
information, see “Write Allocate” on page 201.
Note: The WHCR register as defined in the Mobile AMD-K6-2+
processor is the same as the Mobile AMD-K6-2-P processor
Model 8.
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63
32 31
22 21 17 16 15
0
W
A
E
WAELIM
1
5
M
Reserved
Symbol
Description
Bits
WAELIM
Write Allocate Enable Limit
31-22
WAE15M Write Allocate Enable 15-to-16-Mbyte 16
Note: Hardware RESET initializes this MSR to all zeros.
Figure 36. Write Handling Control Register (WHCR)—MSR C0000_0082h
UC/WC Cacheability Control Register (UWCCR).
The Mobile AMD-K6-2+ processor provides two variable-range
Me m or y Ty p e R a n ge R e gist e r s (MTR R s)—MTR R 0 a n d
MTRR1—that each specify a range of memory. Each range can
b e d e fin e d a s u n ca ch e able (U C) or wr it e -com b in ing (WC)
m e m ory. For m ore in for m a t ion , se e “ Me m ory Typ e R a n ge
Registers” on page 219.
.
Symbol Description
Bits
32
Symbol Description
Bits
0
UC1
Uncacheable Memory Type
UC0
Uncacheable Memory Type
WC1
Write-Combining Memory Type 33
WC0
Write-Combining Memory Type
1
63
49 48
34 33 32 31
W U
17 16
2
1 0
W U
Physical Base Address 1
Physical Address Mask 1
Physical Base Address 0
Physical Address Mask 0
C
1
C
1
C
0
C
0
MTRR1
MTRR0
Figure 37. UC/WC Cacheability Control Register (UWCCR)— MSR C0000_0085h
Processor State Observability Register (PSOR).
The Mobile AMD-K6-2+ processor provides the Processor State
Observability Register (PSOR) (see Figure 38 on page 42).
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.
Symbol
PBF
VID
Description
Pin Bus Frequency Divisor
Voltage ID
Bits
23-21
20-16
63
24
23
21 20
16 15
9 8
7
2
4
3
0
N
O
L
2
STEP
EBF[2:0]
PBF[2:0]
VID
Reserved
Description
No L2 Functionality
Processor Stepping
Symbol
NOL2
STEP
Bits
8
7-4
EBF
Effective Bus Frequency Divisor 2-0
Figure 38. Processor State Observability Register (PSOR)— MSR C000_0087h
Page Flush/Invalidate Register (PFIR). Th e M o b i l e A M D -K 6 -2 +
processor contains the Page Flush/Invalidate Register (PFIR)
(see Figure 39) t hat allows ca che invalidat ion and opt ional
flushing of a specific 4-Kbyt e pa ge from t he linear a ddress
space. For more detailed information on PFIR, see “PFIR” on
page 210.
63
32 31
12 11 9 8 7
1
0
F
/
I
P
F
LINPAGE
Reserved
Description
LINPAGE 20-bit Linear Page Address
Symbol
Bit
31-12
8
PF
F/I
Page Fault Occurred
Flush/Invalidate Command
0
Figure 39. Page Flush/Invalidate Register (PFIR)— MSR C000_0088h
Level-2 Cache Array Access Register (L2AAR).
The Mobile AMD-K6-2+ processor provides the L2AAR register
that allows for direct access to the L2 cache and L2 tag arrays.
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The L2AAR register is MSR C000_0089h. The operation that is
p e r form e d on t h e L2 ca che is a fu n ct ion of t h e in st ru ct ion
executed —RDMSR or WRMSR —and the contents of the EDX
register. The EDX register specifies the location of the access,
and whether the access is to the L2 cache data or tags (refer to
Figure 40).
Symbol Description
Bit
T/D
Way
Selects Tag (1) or Data (0) access
Selects desired cache way
20
17-16
31
21 20 19 18 17 16 15 14
T
6
5
4
3 2
1
0
D
w
o
r
d
L
i
n
e
Octet
Way
/
Set
D
Reserved
Symbol Description
Bit
14-6
5
Set
Selects the desired cache set
Line
Octet
Selects Line1 (1) or Line0 (0)
Selects one of four octets
4-3
Dword Selects upper (1) or lower (0) dword
2
Figure 40. L2 Tag or Data Location - EDX
If t h e L2 cach e d at a is re ad (as op p osed t o rea d in g t h e t a g
information), the result (dword) is placed in EAX in the format
as illustrated in Figure 41. Similarly, if the L2 cache data is
written, the write data is taken from EAX.
31
0
Data
Figure 41. L2 Data - EAX
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Mobile AMD-K6 -2+ Processor Data Sheet
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If the L2 tag is read (as opposed to reading the cache data), the
result is placed in EAX in the format as illustrated in Figure 42.
Similarly, if the L2 tag is written, the write data is taken from
EAX.
31
14 13 12 11 10 9 8 7
Line1ST Line0ST
0
Tag
LRU
Reserved
Symbol Description
Tag Tag data read or written
Bit
31-14
Line1ST Line 1 state (M=11, E=10, S=01, I=00) 11-10
Line0ST Line 0 state (M=11, E=10, S=01, I=00) 9-8
LRU
Two bits of LRU for each way
7-0
Figure 42. L2 Tag Information - EAX
For more de ta ile d informa tion, re fe r to “ L2 Ca che a nd Tag
Array Testing” on page 253.
Enhanced Power Management Register (EPMR).
The Mobile AMD-K6-2+ processor is designed with Enhanced
Powe r Ma n a ge m en t (E P M) fe a tu res— dyn am ic Bu s Divisor
control and dynamic Voltage ID control. The EPMR register of
the Mobile AMD-K6-2+ processor (see Figure 43 on page 45)
d e fin e s t h e b a se a dd ress for a 16-byt e b lock of I/O a dd re ss
space. Enabling the EPMR allows software to access the EPM
16-byte I/O block, which contains bits for enabling, controlling,
and monitoring the EPM features.
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63
3
1 0
2
4
16 15
G
E
S
B
C
IOBASE
N
Reserved
Description
IOBASE I/O Base Address
Symbol
Bit
15-4
1
GSBC
EN
Generate Special Bus Cycle
Enable Mobile Feature Base Address
0
Figure 43. Enhanced Power Management Register (EPMR)—MSR C000_0086h
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Mobile AMD-K6 -2+ Processor Data Sheet
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Memory
Management
Registers
The Mobile AMD-K6-2+ processor controls segmented memory
ma nagem e nt wit h t he re gist ers list ed in Table 8. Figure 44
shows the formats of these registers.
Table 8. Memory Management Registers
Register Name
Function
Global Descriptor Table Register Contains a pointer to the base of the global descriptor table
Interrupt Descriptor Table Register Contains a pointer to the base of the interrupt descriptor table
Local Descriptor Table Register
Task Register
Contains a pointer to the local descriptor table of the current task
Contains a pointer to the task state segment of the current task
Global and Interrupt Descriptor Table Registers
15
15
0
47
16
32-Bit Linear Base Address
16-Bit Limit
Selector
Local Descriptor Table Register and Task Register
0
63
32 31
0
32-Bit Linear Base Address
32-Bit Limit
15
0
Attributes
Figure 44. Memory Management Registers
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Task State Segment
Figure 45 shows the format of the task state segment (TSS).
31
0
TSS Limit
from TR
I/O Permission Bitmap (IOPB)
(up to 8 Kbytes)
Interrupt Redirection Bitmap (IRB)
(eight 32-bit locations)
Operating System
Data Structure
Base Address of IOPB
0000h
T
64h
0000h
0000h
0000h
0000h
0000h
LDT Selector
GS
FS
DS
SS
CS
0000h
0000h
ES
EDI
ESI
EBP
ESP
EBX
EDX
ECX
EAX
EFLAGS
EIP
CR3
SS2
0000h
0000h
0000h
0000h
ESP2
ESP1
ESP0
SS1
SS0pu
Link (Prior TSS Selector)
0
Figure 45. Task State Segment (TSS)
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Paging
The Mobile AMD-K6-2+ processor can physically address up to
four Gbytes of memory. This memory can be segmented into
pages. The size of these pages is determined by the operating
syst e m d e sign a n d t h e va lu e s se t u p in t h e p a ge d ire ct ory
entries (PDE) and page table entries (PTE). The processor can
access both 4-Kbyte pages and 4-Mbyte pages, and the page
sizes can be intermixed within a page directory. When the page
size extension (PSE) bit in CR4 is set, the processor translates
linear addresses using either the 4-Kbyte translation lookaside
buffer (TLB) or the 4-Mbyte TLB, depending on the state of the
page size (PS) bit in the page directory entry. Figures 46 and 47
show how 4-Kbyte and 4-Mbyte page translations work.
4-Kbyte
Page
Directory
Page
Table
Page
Frame
PTE
Physical
Address
PDE
CR3
31
22 21
12 11
0
Page Directory
Offset
Page Table
Offset
Page
Offset
Linear Address
Figure 46. 4-Kbyte Paging Mechanism
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4-Mbyte
Page
Frame
Page
Directory
Physical
Address
PDE
CR3
31
22 21
0
Page Directory
Offset
Page
Offset
Linear Address
Figure 47. 4-Mbyte Paging Mechanism
Figures 48 through 50 show the formats of the PDE and PTE.
These entries contain information regarding the location of
pages and their status.
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31
12 11 10 9
8
7
0
6
5
4
3
2
1
0
U
/
S
P
W
T
W
/
R
A
V
L
P
C
D
A
P
Page Table Base Address
Symbol
AVL
Description
Available to Software
Reserved
Bits
11–9
8
PS
Page Size
7
Reserved
6
A
Accessed
5
PCD
PWT
U/S
W/R
P
Page Cache Disable
Page Writethrough
User/Supervisor
Write/Read
4
3
2
1
Present (valid)
0
Figure 48. Page Directory Entry 4-Kbyte Page Table (PDE)
31
22 21
12 11 10 9
8
7
1
6
5
4
3
2
1
0
U
/
S
P
W
T
W
/
R
A
V
L
P
C
D
A
P
Physical Page Base Address
Reserved
Symbol
AVL
Description
Available to Software
Reserved
Bits
11–9
8
PS
Page Size
7
Reserved
6
A
Accessed
5
PCD
PWT
U/S
W/R
P
Page Cache Disable
Page Writethrough
User/Supervisor
Write/Read
4
3
2
1
Present (valid)
0
Figure 49. Page Directory Entry 4-Mbyte Page Table (PDE)
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31
12 11 10 9
8
7
6
5
4
3
2
1
0
U
/
S
P
W
T
W
/
R
A
V
L
P
C
D
D
A
P
Physical Page Base Address
Symbol
Description
Bits
AVL
Available to Software
Reserved
Dirty
11–9
8–7
6
D
A
Accessed
5
PCD
PWT
U/S
W/R
P
Page Cache Disable
Page Writethrough
User/Supervisor
Write/Read
4
3
2
1
Present (valid)
0
Figure 50. Page Table Entry (PTE)
Descriptors and Gates
There are various types of structures and registers in the x86
architecture that define, protect, and isolate code segments,
data segments, task state segments, and gates. These structures
are called descriptors.
Figure 51 on page 52 shows the application segment descriptor
format. Table 9 contains information describing the memory
segment type to which the descriptor points. The application
segment descript or is used to point to either a data or code
segment.
Figure 52 on pa ge 53 shows the syste m se gm e nt de scriptor
format. Table 10 contains information describing the type of
segment or gate to which the descript or point s. The system
segment descriptor is used to point to a task state segment, a
call gate, or a local descriptor table.
The Mobile AMD-K6-2+ processor uses gates to transfer control
between executable segments with different privilege levels.
Figure 53 on page 54 shows the format of the gate descriptor
types. Table 10 contains information describing th e type of
segment or gate to which the descriptor points.
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Symbol
G
D
Description
Granularity
32-Bit/16-Bit
Bits
23
22
AVL Available to Software
Present/Valid Bit
DPL Descriptor Privilege Level
DT Descriptor Type
Type See Table 9
20
15
14-13
12
11-8
P
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
A
8
7
6
5
4
3
2
1 0
Base Address 31–24
G D
Segment
Limit
P
DPL
1
Type
Base Address 23–16
V
L
Base Address 15–0
Segment Limit 15–0
Figure 51. Application Segment Descriptor
Table 9. Application Segment Types
Type Data/Code
Description
0
1
2
Read-Only
Read-Only—Accessed
Read/Write
3
Read/Write—Accessed
Data
4
Read-Only—Expand-down
Read-Only—Expand-down, Accessed
Read/Write—Expand-down
Read/Write—Expand-down, Accessed
Execute-Only
5
6
7
8
9
A
Execute-Only—Accessed
Execute/Read
B
Execute/Read—Accessed
Code
C
Execute-Only—Conforming
Execute-Only—Conforming, Accessed
Execute/Read-Only—Conforming
D
E
F
Execute/Read-Only—Conforming, Accessed
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Symbol
G
X
Description
Granularity
Not Needed
Bits
23
22
AVL Availability to Software
Present/Valid Bit
DPL Descriptor Privilege Level
DT Descriptor Type
Type See Table 10
20
15
14-13
12
11-8
Reserved
P
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1 0
A
V
L
Base Address 31–24
G
X
Segment
Limit
P
DPL
0
Type
Base Address 23–16
Base Address 15–0
Segment Limit 15–0
Figure 52. System Segment Descriptor
Table 10. System Segment and Gate Types
Type
0
Description
Reserved
1
Available 16-bit TSS
LDT
2
3
Busy 16-bit TSS
16-bit Call Gate
Task Gate
4
5
6
16-bit Interrupt Gate
16-bit Trap Gate
Reserved
7
8
9
Available 32-bit TSS
Reserved
A
B
C
D
E
F
Busy 32-bit TSS
32-bit Call Gate
Reserved
32-bit Interrupt Gate
32-bit Trap Gate
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Symbol
P
Description
Present/Valid Bit
Bits
15
DPL Descriptor Privilege Level
DT Descriptor Type
Type See Table 10
14-13
12
11-8
Reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Offset 31–16
P
DPL
0
Type
Segment Selector
Offset 15–0
Figure 53. Gate Descriptor
Exceptions and
Interrupts
Table 11 summarizes the exceptions and interrupts.
Table 11. Summary of Exceptions and Interrupts
Interrupt
Interrupt Type
Number
Cause
0
1
Divide by Zero Error
Debug
DIV, IDIV
Debug trap or fault
2
Non-Maskable Interrupt NMI signal sampled asserted
3
Breakpoint
Int 3
4
Overflow
INTO
5
Bounds Check
Invalid Opcode
Device Not Available
Double Fault
BOUND
6
Invalid instruction
ESC and WAIT
7
8
Fault occurs while handling a fault
—
9
Reserved - Interrupt 13
Invalid TSS
10
11
12
13
14
16
Task switch to an invalid segment
Segment Not Present
Stack Segment
General Protection
Page Fault
Instruction loads a segment and present bit is 0 (invalid segment)
Stack operation causes limit violation or present bit is 0
Segment related or miscellaneous invalid actions
Page protection violation or a reference to missing page
Arithmetic error generated by floating-point instruction
Floating-Point Error
Data reference to an unaligned operand. (The AC flag and the AM bit of CR0 are
set to 1.)
17
Alignment Check
0–255 Software Interrupt
INT n
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3.2
Instructions Supported by the Mobile AMD-K6®-2+ Processor
This section documents all of the x86 instructions supported by
the Mobile AMD-K6-2+ processor. The following tables show the
instruction mnemonic, opcode, modR/M byte, decode type, and
RISC86 operation(s) for each instruction. Tables 12 through 16
define the integer, floating-point, MMX, 3DNow! instructions,
a n d 3DNow! t e ch n ology DSP e xt e n sion s for t h e Mob ile
AMD-K6-2+ processor, respectively. For details about the MMX,
3DNow! instructions, and 3DNow! technology DSP extensions
refer to the following manuals:
■ MMX—AMD-K6 MMX Processor Multimedia Extensions
Manual, order# 20726
■ 3DNow!—3DNow! Technology Manual, order# 21928
■ 3DNow! technology DSP extensions—AMD Extensions to the
3DNow! and MMX Instruction Set Manual, order# 22466
Th e first colu m n in t h e se t ab le s in d ica t e s t h e in st r u ct ion
mnemonic and operand types with the following notations:
■ reg8—byte integer register defined by instruction byte(s) or
bits 5, 4, and 3 of the modR/M byte
■ mreg8—byte integer register or byte integer value in
memory defined by the modR/M byte
■ reg16/32—word or doubleword integer register defined by
instruction byte(s) or bits 5, 4, and 3 of the modR/M byte
■ mreg16/32—word or doubleword integer register, or word or
doubleword integer value in memory defined by the
modR/M byte
■ mem8—byte integer value in memory
■ mem16/32—word or doubleword integer value in memory
■ mem32/48—doubleword or 48-bit integer value in memory
■ mem48—48-bit integer value in memory
■ mem64—64-bit value in memory
■ imm8—8-bit immediate value
■ imm16/32—16-bit or 32-bit immediate value
■ disp8—8-bit displacement value
■ disp16/32—16-bit or 32-bit displacement value
■ disp32/48—doubleword or 48-bit displacement value
■ eXX—register width depending on the operand size
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■ mem32real—32-bit floating-point value in memory
■ mem64real—64-bit floating-point value in memory
■ mem80real—80-bit floating-point value in memory
■ mmreg—MMX/3DNow! register
■ mmreg1—MMX/3DNow! register defined by bits 5, 4, and 3
of the modR/M byte
■ mmreg2—MMX/3DNow! register defined by bits 2, 1, and 0
of the modR/M byte
The second and third columns list all applicable opcode bytes.
Th e fourth column lists the modR/M byte when used by the
in st r u ct ion . Th e m od R /M byt e d e fin e s t h e in st r u ct ion a s a
register or memory form. If modR/M bits 7 and 6 are documented
as mm (memory form), mm can only be 10b, 01b or 00b.
The fifth column lists the type of instruction decode —short,
long, and vector. The Mobile AMD-K6-2+ processor decode logic
can process two short, one long, or one vector decode per clock .
The sixth column lists the type of RISC86 operation(s) required
for th e instruction. The ope ra tion type s a nd corre sponding
execution units are as follows:
■ load, fload, mload—load unit
■ store, fstore, mstore—store unit
■ alu —either of the integer execution units
■ alux—integer X execution unit only
■ branch —branch condition unit
■ float —floating-point execution unit
■ meu —Multimedia execution units for MMX and 3DNow!
instructions
■ limm —load immediate, instruction control unit
Table 12. Integer Instructions
Instruction Mnemonic
First
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
AAA
AAD
AAM
AAS
37h
D5h
D4h
3Fh
vector
vector
vector
vector
0Ah
0Ah
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Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
Table 12. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
ADC mreg8, reg8
10h
10h
11h
11h
12h
12h
13h
13h
14h
15h
80h
80h
81h
81h
83h
83h
00h
00h
01h
01h
02h
02h
03h
03h
04h
05h
80h
80h
81h
81h
83h
83h
20h
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
short
long
ADC mem8, reg8
ADC mreg16/32, reg16/32
ADC mem16/32, reg16/32
ADC reg8, mreg8
ADC reg8, mem8
ADC reg16/32, mreg16/32
ADC reg16/32, mem16/32
ADC AL, imm8
ADC EAX, imm16/32
ADC mreg8, imm8
11-010-xxx
mm-010-xxx
11-010-xxx
mm-010-xxx
11-010-xxx
mm-010-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
ADC mem8, imm8
ADC mreg16/32, imm16/32
ADC mem16/32, imm16/32
ADC mreg16/32, imm8 (signed ext.)
ADC mem16/32, imm8 (signed ext.)
ADD mreg8, reg8
alux
ADD mem8, reg8
load, alux, store
alu
ADD mreg16/32, reg16/32
ADD mem16/32, reg16/32
ADD reg8, mreg8
short
long
load, alu, store
alux
short
short
short
short
short
short
short
long
ADD reg8, mem8
load, alux
alu
ADD reg16/32, mreg16/32
ADD reg16/32, mem16/32
ADD AL, imm8
load, alu
alux
ADD EAX, imm16/32
alu
ADD mreg8, imm8
11-000-xxx
mm-000-xxx
11-000-xxx
mm-000-xxx
11-000-xxx
mm-000-xxx
11-xxx-xxx
alux
ADD mem8, imm8
load, alux, store
alu
ADD mreg16/32, imm16/32
ADD mem16/32, imm16/32
ADD mreg16/32, imm8 (signed ext.)
ADD mem16/32, imm8 (signed ext.)
AND mreg8, reg8
short
long
load, alu, store
alux
short
long
load, alux, store
alux
short
Chapter 3
Software Environment
57
Preliminary Information
®
Mobile AMD-K6 -2+ Processor Data Sheet
23446B/0—June 2000
Table 12. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
load, alux, store
alu
AND mem8, reg8
20h
21h
21h
22h
22h
23h
23h
24h
25h
80h
80h
81h
81h
83h
83h
63h
63h
62h
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
long
short
long
AND mreg16/32, reg16/32
AND mem16/32, reg16/32
AND reg8, mreg8
load, alu, store
alux
short
short
short
short
short
short
short
long
AND reg8, mem8
load, alux
alu
AND reg16/32, mreg16/32
AND reg16/32, mem16/32
AND AL, imm8
load, alu
alux
AND EAX, imm16/32
AND mreg8, imm8
AND mem8, imm8
AND mreg16/32, imm16/32
AND mem16/32, imm16/32
AND mreg16/32, imm8 (signed ext.)
AND mem16/32, imm8 (signed ext.)
ARPL mreg16, reg16
ARPL mem16, reg16
BOUND
alu
11-100-xxx
mm-100-xxx
11-100-xxx
mm-100-xxx
11-100-xxx
mm-100-xxx
11-xxx-xxx
alux
load, alux, store
alu
short
long
load, alu, store
alux
short
long
load, alux, store
vector
vector
vector
vector
vector
vector
vector
long
mm-xxx-xxx
BSF reg16/32, mreg16/32
BSF reg16/32, mem16/32
BSR reg16/32, mreg16/32
BSR reg16/32, mem16/32
BSWAP EAX
BCh
BCh
BDh
BDh
C8h
C9h
CAh
CBh
CCh
CDh
CEh
CFh
A3h
A3h
BAh
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
alu
alu
alu
alu
alu
alu
alu
alu
BSWAP ECX
long
BSWAP EDX
long
BSWAP EBX
long
BSWAP ESP
long
BSWAP EBP
long
BSWAP ESI
long
BSWAP EDI
long
BT mreg16/32, reg16/32
BT mem16/32, reg16/32
BT mreg16/32, imm8
11-xxx-xxx
mm-xxx-xxx
11-100-xxx
vector
vector
vector
58
Software Environment
Chapter 3
Preliminary Information
Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
Table 12. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
BT mem16/32, imm8
BTC mreg16/32, reg16/32
BTC mem16/32, reg16/32
BTC mreg16/32, imm8
BTC mem16/32, imm8
BTR mreg16/32, reg16/32
BTR mem16/32, reg16/32
BTR mreg16/32, imm8
BTR mem16/32, imm8
BTS mreg16/32, reg16/32
BTS mem16/32, reg16/32
BTS mreg16/32, imm8
BTS mem16/32, imm8
CALL full pointer
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
9Ah
E8h
FFh
FFh
FFh
98h
F8h
FCh
FAh
0Fh
F5h
38h
38h
39h
39h
3Ah
3Ah
3Bh
3Bh
3Ch
BAh
BBh
BBh
BAh
BAh
B3h
B3h
BAh
BAh
ABh
ABh
BAh
BAh
mm-100-xxx vector
11-xxx-xxx
mm-xxx-xxx
11-111-xxx
mm-111-xxx
11-xxx-xxx
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
short
mm-xxx-xxx
11-110-xxx
mm-110-xxx
11-xxx-xxx
mm-xxx-xxx
11-101-xxx
mm-101-xxx
CALL near imm16/32
CALL mem16:16/32
CALL near mreg32 (indirect)
CALL near mem32 (indirect)
CBW/CWDE EAX
store
11-011-xxx
11-010-xxx
mm-010-xxx
vector
vector
vector
vector
vector
vector
vector
vector
vector
short
CLC
CLD
CLI
CLTS
06h
CMC
CMP mreg8, reg8
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
alux
CMP mem8, reg8
short
load, alux
alu
CMP mreg16/32, reg16/32
CMP mem16/32, reg16/32
CMP reg8, mreg8
short
short
load, alu
alux
short
CMP reg8, mem8
short
load, alux
alu
CMP reg16/32, mreg16/32
CMP reg16/32, mem16/32
CMP AL, imm8
short
short
load, alu
alux
short
Chapter 3
Software Environment
59
Preliminary Information
®
Mobile AMD-K6 -2+ Processor Data Sheet
23446B/0—June 2000
Table 12. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
CMP EAX, imm16/32
CMP mreg8, imm8
CMP mem8, imm8
CMP mreg16/32, imm16/32
CMP mem16/32, imm16/32
CMP mreg16/32, imm8 (signed ext.)
CMP mem16/32, imm8 (signed ext.)
CMPSB mem8, mem8
CMPSW mem16, mem32
CMPSD mem32, mem32
CMPXCHG mreg8, reg8
CMPXCHG mem8, reg8
CMPXCHG mreg16/32, reg16/32
CMPXCHG mem16/32, reg16/32
CMPXCHG8B EDX:EAX
CMPXCHG8B mem64
CPUID
3Dh
80h
80h
81h
81h
83h
83h
A6h
A7h
A7h
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
99h
27h
2Fh
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
FEh
FEh
FFh
FFh
F6h
short
short
short
short
short
long
alu
11-111-xxx
mm-111-xxx
11-111-xxx
mm-111-xxx
11-111-xxx
mm-111-xxx
alux
load, alux
alu
load, alu
load, alu
load, alu
long
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
short
short
short
short
short
short
short
short
vector
long
B0h
B0h
B1h
B1h
C7h
C7h
A2h
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
CWD/CDQ EDX, EAX
DAA
DAS
DEC EAX
alu
alu
alu
alu
alu
alu
alu
alu
DEC ECX
DEC EDX
DEC EBX
DEC ESP
DEC EBP
DEC ESI
DEC EDI
DEC mreg8
11-001-xxx
mm-001-xxx
11-001-xxx
mm-001-xxx
11-110-xxx
DEC mem8
load, alux, store
load, alu, store
DEC mreg16/32
vector
long
DEC mem16/32
DIV AL, mreg8
vector
60
Software Environment
Chapter 3
Preliminary Information
Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
Table 12. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
DIV AL, mem8
F6h
F7h
F7h
F6h
F6h
F7h
F7h
69h
mm-110-xxx
11-110-xxx
mm-110-xxx
11-111-xxx
mm-111-xxx
11-111-xxx
mm-111-xxx
11-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
DIV EAX, mreg16/32
DIV EAX, mem16/32
IDIV mreg8
IDIV mem8
IDIV EAX, mreg16/32
IDIV EAX, mem16/32
IMUL reg16/32, imm16/32
IMUL reg16/32, mreg16/32, imm16/32 69h
IMUL reg16/32, mem16/32, imm16/32 69h
IMUL reg16/32, imm8 (sign extended) 6Bh
IMUL reg16/32, mreg16/32, imm8
(signed)
6Bh
11-xxx-xxx
vector
vector
IMUL reg16/32, mem16/32, imm8
(signed)
6Bh
mm-xxx-xxx
IMUL AX, AL, mreg8
IMUL AX, AL, mem8
IMUL EDX:EAX, EAX, mreg16/32
IMUL EDX:EAX, EAX, mem16/32
IMUL reg16/32, mreg16/32
IMUL reg16/32, mem16/32
IN AL, imm8
F6h
F6h
F7h
F7h
0Fh
0Fh
E4h
E5h
E5h
ECh
EDh
EDh
40h
41h
42h
43h
44h
45h
46h
11-101-xxx
mm-101-xxx
11-101-xxx
mm-101-xxx
11-xxx-xxx
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
short
AFh
AFh
mm-xxx-xxx
IN AX, imm8
IN EAX, imm8
IN AL, DX
IN AX, DX
IN EAX, DX
INC EAX
alu
alu
alu
alu
alu
alu
alu
INC ECX
short
INC EDX
short
INC EBX
short
INC ESP
short
INC EBP
short
INC ESI
short
Chapter 3
Software Environment
61
Preliminary Information
®
Mobile AMD-K6 -2+ Processor Data Sheet
23446B/0—June 2000
Table 12. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
INC EDI
47h
FEh
FEh
FFh
FFh
0Fh
0Fh
70h
71h
71h
73h
74h
75h
76h
77h
78h
79h
7Ah
7Bh
7Ch
7Dh
7Eh
7Fh
E3h
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
short
vector
long
alu
INC mreg8
11-000-xxx
mm-000-xxx
11-000-xxx
mm-000-xxx
INC mem8
load, alux, store
load, alu, store
INC mreg16/32
vector
long
INC mem16/32
INVD
08h
01h
vector
vector
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
vector
short
short
short
short
short
short
short
short
short
INVLPG
mm-111-xxx
JO short disp8
branch
branch
branch
branch
branch
branch
branch
branch
branch
branch
branch
branch
branch
branch
branch
branch
JB/JNAE short disp8
JNO short disp8
JNB/JAE short disp8
JZ/JE short disp8
JNZ/JNE short disp8
JBE/JNA short disp8
JNBE/JA short disp8
JS short disp8
JNS short disp8
JP/JPE short disp8
JNP/JPO short disp8
JL/JNGE short disp8
JNL/JGE short disp8
JLE/JNG short disp8
JNLE/JG short disp8
JCXZ/JEC short disp8
JO near disp16/32
JNO near disp16/32
JB/JNAE near disp16/32
JNB/JAE near disp16/32
JZ/JE near disp16/32
JNZ/JNE near disp16/32
JBE/JNA near disp16/32
JNBE/JA near disp16/32
JS near disp16/32
80h
81h
82h
83h
84h
85h
86h
87h
88h
branch
branch
branch
branch
branch
branch
branch
branch
branch
62
Software Environment
Chapter 3
Preliminary Information
Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
Table 12. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
JNS near disp16/32
JP/JPE near disp16/32
JNP/JPO near disp16/32
JL/JNGE near disp16/32
JNL/JGE near disp16/32
JLE/JNG near disp16/32
JNLE/JG near disp16/32
JMP near disp16/32 (direct)
JMP far disp32/48 (direct)
JMP disp8 (short)
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
E9h
EAh
EBh
EFh
EFh
FFh
FFh
9Fh
0Fh
0Fh
C5h
8Dh
C9h
C4h
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
ACh
ADh
ADh
E2h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
short
short
short
short
short
short
short
short
vector
short
vector
vector
vector
branch
branch
branch
branch
branch
branch
branch
branch
branch
JMP far mreg32 (indirect)
JMP far mem32 (indirect)
JMP near mreg16/32 (indirect)
JMP near mem16/32 (indirect)
LAHF
11-101-xxx
mm-101-xxx
11-100-xxx
mm-100-xxx vector
vector
LAR reg16/32, mreg16/32
LAR reg16/32, mem16/32
LDS reg16/32, mem32/48
LEA reg16/32, mem16/32
LEAVE
02h
02h
11-xxx-xxx
mm-xxx-xxx
mm-xxx-xxx
mm-xxx-xxx
vector
vector
vector
short
load, alu
long
load, alu, alu
LES reg16/32, mem32/48
LFS reg16/32, mem32/48
LGDT mem48
mm-xxx-xxx
mm-010-xxx
vector
vector
vector
vector
vector
vector
vector
vector
B4h
01h
B5h
01h
00h
00h
01h
01h
LGS reg16/32, mem32/48
LIDT mem48
mm-011-xxx
11-010-xxx
mm-010-xxx
11-100-xxx
LLDT mreg16
LLDT mem16
LMSW mreg16
LMSW mem16
mm-100-xxx vector
LODSB AL, mem8
long
long
long
short
load, alu
load, alu
load, alu
alu, branch
LODSW AX, mem16
LODSD EAX, mem32
LOOP disp8
Chapter 3
Software Environment
63
Preliminary Information
®
Mobile AMD-K6 -2+ Processor Data Sheet
23446B/0—June 2000
Table 12. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
LOOPE/LOOPZ disp8
LOOPNE/LOOPNZ disp8
LSL reg16/32, mreg16/32
LSL reg16/32, mem16/32
LSS reg16/32, mem32/48
LTR mreg16
E1h
E0h
0Fh
0Fh
0Fh
0Fh
0Fh
88h
88h
89h
89h
8Ah
8Ah
8Bh
8Bh
8Ch
8Ch
8Eh
8Eh
A0h
A1h
A2h
A3h
B0h
B1h
B2h
B3h
B4h
B5h
B6h
B7h
B8h
B9h
vector
vector
vector
vector
vector
vector
vector
short
short
short
short
short
short
short
short
long
03h
03h
B2h
00h
00h
11-xxx-xxx
mm-xxx-xxx
mm-xxx-xxx
11-011-xxx
mm-011-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
LTR mem16
MOV mreg8, reg8
alux
store
alu
MOV mem8, reg8
MOV mreg16/32, reg16/32
MOV mem16/32, reg16/32
MOV reg8, mreg8
store
alux
load
alu
MOV reg8, mem8
MOV reg16/32, mreg16/32
MOV reg16/32, mem16/32
MOV mreg16, segment reg
MOV mem16, segment reg
MOV segment reg, mreg16
MOV segment reg, mem16
MOV AL, mem8
load
load
vector
vector
vector
short
short
short
short
short
short
short
short
short
short
short
short
short
short
load
MOV EAX, mem16/32
MOV mem8, AL
load
store
store
limm
limm
limm
limm
limm
limm
limm
limm
limm
limm
MOV mem16/32, EAX
MOV AL, imm8
MOV CL, imm8
MOV DL, imm8
MOV BL, imm8
MOV AH, imm8
MOV CH, imm8
MOV DH, imm8
MOV BH, imm8
MOV EAX, imm16/32
MOV ECX, imm16/32
64
Software Environment
Chapter 3
Preliminary Information
Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
Table 12. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
MOV EDX, imm16/32
MOV EBX, imm16/32
MOV ESP, imm16/32
MOV EBP, imm16/32
MOV ESI, imm16/32
MOV EDI, imm16/32
MOV mreg8, imm8
MOV mem8, imm8
MOV mreg16/32, imm16/32
MOV mem16/32, imm16/32
MOV reg32, CR0
BAh
BBh
BCh
BDh
BEh
BFh
C6h
C6h
C7h
C7h
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
A4h
A5h
A5h
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
F6h
F6h
F7h
F7h
short
short
short
short
short
short
short
long
limm
limm
limm
limm
limm
limm
limm
store
limm
store
11-000-xxx
mm-000-xxx
11-000-xxx
mm-000-xxx
11-000-xxx
11-010-xxx
11-011-xxx
11-100-xxx
11-000-xxx
11-010-xxx
11-011-xxx
11-100-xxx
short
long
20h
20h
20h
20h
22h
22h
22h
22h
vector
vector
vector
vector
vector
vector
vector
vector
long
MOV reg32, CR2
MOV reg32, CR3
MOV reg32, CR4
MOV CR0, reg32
MOV CR2, reg32
MOV CR3, reg32
MOV CR4, reg32
MOVSB mem8,mem8
MOVSD mem16, mem16
MOVSW mem32, mem32
MOVSX reg16/32, mreg8
MOVSX reg16/32, mem8
MOVSX reg32, mreg16
MOVSX reg32, mem16
MOVZX reg16/32, mreg8
MOVZX reg16/32, mem8
MOVZX reg32, mreg16
MOVZX reg32, mem16
MUL AL, mreg8
load, store, alux, alux
long
load, store, alu, alu
long
load, store, alu, alu
BEh
BEh
BFh
BFh
B6h
B6h
B7h
B7h
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-100-xxx
short
short
short
short
short
short
short
short
vector
alu
load, alu
alu
load, alu
alu
load, alu
alu
load, alu
MUL AL, mem8
mm-100-xxx vector
11-100-xxx vector
mm-100-xxx vector
MUL EAX, mreg16/32
MUL EAX, mem16/32
Chapter 3
Software Environment
65
Preliminary Information
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Mobile AMD-K6 -2+ Processor Data Sheet
23446B/0—June 2000
Table 12. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
NEG mreg8
F6h
F6h
F7h
F7h
90h
F6h
F6h
F7h
F7h
08h
08h
09h
09h
0Ah
0Ah
0Bh
0Bh
0Ch
0Dh
80h
80h
81h
81h
83h
83h
E6h
E7h
E7h
EEh
EFh
EFh
07h
17h
11-011-xxx
mm-011-xxx
11-011-xxx
short
vector
short
vector
short
short
vector
short
vector
short
long
alux
alu
NEG mem8
NEG mreg16/32
NEG mem16/32
mm-011-xxx
NOP (XCHG EAX, EAX)
NOT mreg8
limm
alux
11-010-xxx
mm-010-xxx
11-010-xxx
mm-010-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
NOT mem8
NOT mreg16/32
alu
NOT mem16/32
OR mreg8, reg8
alux
OR mem8, reg8
load, alux, store
alu
OR mreg16/32, reg16/32
OR mem16/32, reg16/32
OR reg8, mreg8
short
long
load, alu, store
alux
short
short
short
short
short
short
short
long
OR reg8, mem8
load, alux
alu
OR reg16/32, mreg16/32
OR reg16/32, mem16/32
OR AL, imm8
load, alu
alux
OR EAX, imm16/32
OR mreg8, imm8
OR mem8, imm8
OR mreg16/32, imm16/32
OR mem16/32, imm16/32
OR mreg16/32, imm8 (signed ext.)
OR mem16/32, imm8 (signed ext.)
OUT imm8, AL
alu
11-001-xxx
mm-001-xxx
11-001-xxx
mm-001-xxx
11-001-xxx
mm-001-xxx
alux
load, alux, store
alu
short
long
load, alu, store
alux
short
long
load, alux, store
vector
vector
vector
vector
vector
vector
vector
vector
OUT imm8, AX
OUT imm8, EAX
OUT DX, AL
OUT DX, AX
OUT DX, EAX
POP ES
POP SS
66
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Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
Table 12. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
POP DS
1Fh
0Fh
0Fh
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
8Fh
8Fh
61h
9Dh
06h
0Eh
0Fh
0Fh
16h
1Eh
50h
51h
52h
53h
54h
55h
56h
57h
6Ah
68h
FFh
FFh
vector
vector
vector
short
short
short
short
short
short
short
short
short
long
POP FS
A1h
A9h
POP GS
POP EAX
load, alu
POP ECX
load, alu
load, alu
load, alu
load, alu
load, alu
load, alu
load, alu
load, alu
load, store, alu
POP EDX
POP EBX
POP ESP
POP EBP
POP ESI
POP EDI
POP mreg 16/32
POP mem 16/32
POPA/POPAD
POPF/POPFD
PUSH ES
11-000-xxx
mm-000-xxx
vector
vector
long
load, store
PUSH CS
vector
vector
vector
vector
long
PUSH FS
A0h
A8h
PUSH GS
PUSH SS
PUSH DS
load, store
store
PUSH EAX
PUSH ECX
PUSH EDX
PUSH EBX
PUSH ESP
PUSH EBP
PUSH ESI
short
short
short
short
short
short
short
short
long
store
store
store
store
store
store
PUSH EDI
PUSH imm8
PUSH imm16/32
PUSH mreg16/32
PUSH mem16/32
store
store
long
store
11-110-xxx
vector
long
mm-110-xxx
load, store
Chapter 3
Software Environment
67
Preliminary Information
®
Mobile AMD-K6 -2+ Processor Data Sheet
23446B/0—June 2000
Table 12. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
PUSHA/PUSHAD
PUSHF/PUSHFD
RCL mreg8, imm8
RCL mem8, imm8
RCL mreg16/32, imm8
RCL mem16/32, imm8
RCL mreg8, 1
60h
9Ch
C0h
C0h
C1h
C1h
D0h
D0h
D1h
D1h
D2h
D2h
D3h
D3h
C0h
C0h
C1h
C1h
D0h
D0h
D1h
D1h
D2h
D2h
D3h
D3h
0Fh
0Fh
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
11-010-xxx
mm-010-xxx
11-010-xxx
mm-010-xxx
11-010-xxx
mm-010-xxx
11-010-xxx
mm-010-xxx
11-010-xxx
mm-010-xxx
11-010-xxx
mm-010-xxx
11-011-xxx
mm-011-xxx
11-011-xxx
mm-011-xxx
11-011-xxx
mm-011-xxx
11-011-xxx
mm-011-xxx
11-011-xxx
mm-011-xxx
11-011-xxx
mm-011-xxx
RCL mem8, 1
RCL mreg16/32, 1
RCL mem16/32, 1
RCL mreg8, CL
RCL mem8, CL
RCL mreg16/32, CL
RCL mem16/32, CL
RCR mreg8, imm8
RCR mem8, imm8
RCR mreg16/32, imm8
RCR mem16/32, imm8
RCR mreg8, 1
RCR mem8, 1
RCR mreg16/32, 1
RCR mem16/32, 1
RCR mreg8, CL
RCR mem8, CL
RCR mreg16/32, CL
RCR mem16/32, CL
RDMSR
32h
31h
RDTSC
RET near imm16
RET near
C2h
C3h
CAh
CBh
C0h
RET far imm16
RET far
ROL mreg8, imm8
11-000-xxx
68
Software Environment
Chapter 3
Preliminary Information
Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
Table 12. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
ROL mem8, imm8
ROL mreg16/32, imm8
ROL mem16/32, imm8
ROL mreg8, 1
C0h
C1h
C1h
D0h
D0h
D1h
D1h
D2h
D2h
D3h
D3h
C0h
C0h
C1h
C1h
D0h
D0h
D1h
D1h
D2h
D2h
D3h
D3h
0Fh
mm-000-xxx vector
11-000-xxx vector
mm-000-xxx vector
11-000-xxx vector
mm-000-xxx vector
11-000-xxx vector
mm-000-xxx vector
11-000-xxx vector
mm-000-xxx vector
11-000-xxx vector
mm-000-xxx vector
11-001-xxx vector
mm-001-xxx vector
11-001-xxx vector
mm-001-xxx vector
11-001-xxx vector
mm-001-xxx vector
11-001-xxx vector
mm-001-xxx vector
11-001-xxx vector
mm-001-xxx vector
11-001-xxx vector
ROL mem8, 1
ROL mreg16/32, 1
ROL mem16/32, 1
ROL mreg8, CL
ROL mem8, CL
ROL mreg16/32, CL
ROL mem16/32, CL
ROR mreg8, imm8
ROR mem8, imm8
ROR mreg16/32, imm8
ROR mem16/32, imm8
ROR mreg8, 1
ROR mem8, 1
ROR mreg16/32, 1
ROR mem16/32, 1
ROR mreg8, CL
ROR mem8, CL
ROR mreg16/32, CL
ROR mem16/32, CL
RSM
mm-001-xxx vector
AAh
vector
vector
SAHF
9Eh
C0h
C0h
C1h
C1h
D0h
D0h
D1h
D1h
SAR mreg8, imm8
SAR mem8, imm8
SAR mreg16/32, imm8
SAR mem16/32, imm8
SAR mreg8, 1
11-111-xxx
mm-111-xxx
11-111-xxx
mm-111-xxx
11-111-xxx
mm-111-xxx
11-111-xxx
mm-111-xxx
short
vector
short
alux
alu
vector
short
alux
alu
SAR mem8, 1
vector
short
SAR mreg16/32, 1
SAR mem16/32, 1
vector
Chapter 3
Software Environment
69
Preliminary Information
®
Mobile AMD-K6 -2+ Processor Data Sheet
23446B/0—June 2000
Table 12. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
SAR mreg8, CL
D2h
D2h
D3h
D3h
18h
18h
19h
19h
1Ah
1Ah
1Bh
1Bh
1Ch
1Dh
80h
80h
81h
81h
83h
83h
AEh
AFh
AFh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
11-111-xxx
mm-111-xxx
11-111-xxx
mm-111-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
short
vector
short
alux
alu
SAR mem8, CL
SAR mreg16/32, CL
SAR mem16/32, CL
SBB mreg8, reg8
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
SBB mem8, reg8
SBB mreg16/32, reg16/32
SBB mem16/32, reg16/32
SBB reg8, mreg8
SBB reg8, mem8
SBB reg16/32, mreg16/32
SBB reg16/32, mem16/32
SBB AL, imm8
SBB EAX, imm16/32
SBB mreg8, imm8
11-011-xxx
mm-011-xxx
11-011-xxx
mm-011-xxx
11-011-xxx
mm-011-xxx
SBB mem8, imm8
SBB mreg16/32, imm16/32
SBB mem16/32, imm16/32
SBB mreg16/32, imm8 (signed ext.)
SBB mem16/32, imm8 (signed ext.)
SCASB AL, mem8
SCASW AX, mem16
SCASD EAX, mem32
SETO mreg8
90h
90h
91h
91h
92h
92h
93h
93h
94h
94h
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
SETO mem8
SETNO mreg8
SETNO mem8
SETB/SETNAE mreg8
SETB/SETNAE mem8
SETNB/SETAE mreg8
SETNB/SETAE mem8
SETZ/SETE mreg8
SETZ/SETE mem8
70
Software Environment
Chapter 3
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Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
Table 12. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
SETNZ/SETNE mreg8
SETNZ/SETNE mem8
SETBE/SETNA mreg8
SETBE/SETNA mem8
SETNBE/SETA mreg8
SETNBE/SETA mem8
SETS mreg8
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
C0h
C0h
C1h
C1h
D0h
D0h
D1h
D1h
D2h
95h
95h
96h
96h
97h
97h
98h
98h
99h
99h
9Ah
9Ah
9Bh
9Bh
9Ch
9Ch
9Dh
9Dh
9Eh
9Eh
9Fh
9Fh
01h
01h
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
SETS mem8
SETNS mreg8
SETNS mem8
SETP/SETPE mreg8
SETP/SETPE mem8
SETNP/SETPO mreg8
SETNP/SETPO mem8
SETL/SETNGE mreg8
SETL/SETNGE mem8
SETNL/SETGE mreg8
SETNL/SETGE mem8
SETLE/SETNG mreg8
SETLE/SETNG mem8
SETNLE/SETG mreg8
SETNLE/SETG mem8
SGDT mem48
mm-000-xxx vector
mm-001-xxx vector
SIDT mem48
SHL/SAL mreg8, imm8
SHL/SAL mem8, imm8
SHL/SAL mreg16/32, imm8
SHL/SAL mem16/32, imm8
SHL/SAL mreg8, 1
SHL/SAL mem8, 1
SHL/SAL mreg16/32, 1
SHL/SAL mem16/32, 1
SHL/SAL mreg8, CL
11-100-xxx
mm-100-xxx vector
11-100-xxx short
mm-100-xxx vector
11-100-xxx short
mm-100-xxx vector
11-100-xxx short
mm-100-xxx vector
11-100-xxx short
short
alux
alu
alux
alu
alux
Chapter 3
Software Environment
71
Preliminary Information
®
Mobile AMD-K6 -2+ Processor Data Sheet
23446B/0—June 2000
Table 12. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
SHL/SAL mem8, CL
SHL/SAL mreg16/32, CL
SHL/SAL mem16/32, CL
SHR mreg8, imm8
D2h
D3h
D3h
C0h
C0h
C1h
C1h
D0h
D0h
D1h
D1h
D2h
D2h
D3h
D3h
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
F9h
FDh
FBh
AAh
ABh
ABh
mm-100-xxx vector
11-100-xxx short
mm-100-xxx vector
alu
11-101-xxx
mm-101-xxx
11-101-xxx
mm-101-xxx
11-101-xxx
mm-101-xxx
11-101-xxx
mm-101-xxx
11-101-xxx
mm-101-xxx
11-101-xxx
mm-101-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-000-xxx
short
vector
short
alux
alu
SHR mem8, imm8
SHR mreg16/32, imm8
SHR mem16/32, imm8
SHR mreg8, 1
vector
short
alux
alu
SHR mem8, 1
vector
short
SHR mreg16/32, 1
SHR mem16/32, 1
vector
short
SHR mreg8, CL
alux
alu
SHR mem8, CL
vector
short
SHR mreg16/32, CL
SHR mem16/32, CL
SHLD mreg16/32, reg16/32, imm8
SHLD mem16/32, reg16/32, imm8
SHLD mreg16/32, reg16/32, CL
SHLD mem16/32, reg16/32, CL
SHRD mreg16/32, reg16/32, imm8
SHRD mem16/32, reg16/32, imm8
SHRD mreg16/32, reg16/32, CL
SHRD mem16/32, reg16/32, CL
SLDT mreg16
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
A4h
A4h
A5h
A5h
ACh
ACh
ADh
ADh
00h
00h
01h
SLDT mem16
mm-000-xxx vector
11-100-xxx vector
SMSW mreg16
SMSW mem16
01h
mm-100-xxx vector
STC
vector
vector
vector
long
STD
STI
STOSB mem8, AL
store, alux
store, alux
store, alux
STOSW mem16, AX
STOSD mem32, EAX
long
long
72
Software Environment
Chapter 3
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Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
Table 12. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
STR mreg16
0Fh
0Fh
28h
28h
29h
29h
2Ah
2Ah
2Bh
2Bh
2Ch
2Dh
80h
80h
81h
81h
83h
83h
0Fh
0Fh
84h
84h
85h
85h
A8h
A9h
F6h
F6h
F7h
F7h
0Fh
0Fh
0Fh
00h
00h
11-001-xxx
vector
STR mem16
mm-001-xxx vector
SUB mreg8, reg8
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
short
long
alux
SUB mem8, reg8
load, alux, store
alu
SUB mreg16/32, reg16/32
SUB mem16/32, reg16/32
SUB reg8, mreg8
short
long
load, alu, store
alux
short
short
short
short
short
short
short
long
SUB reg8, mem8
load, alux
alu
SUB reg16/32, mreg16/32
SUB reg16/32, mem16/32
SUB AL, imm8
load, alu
alux
SUB EAX, imm16/32
SUB mreg8, imm8
SUB mem8, imm8
SUB mreg16/32, imm16/32
SUB mem16/32, imm16/32
SUB mreg16/32, imm8 (signed ext.)
SUB mem16/32, imm8 (signed ext.)
SYSCALL
alu
11-101-xxx
mm-101-xxx
11-101-xxx
mm-101-xxx
11-101-xxx
mm-101-xxx
alux
load, alux, store
alu
short
long
load, alu, store
alux
short
long
load, alux, store
05h
07h
vector
vector
short
vector
short
vector
long
SYSRET
TEST mreg8, reg8
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
alux
alu
TEST mem8, reg8
TEST mreg16/32, reg16/32
TEST mem16/32, reg16/32
TEST AL, imm8
mm-xxx-xxx
alux
TEST EAX, imm16/32
TEST mreg8, imm8
TEST mem8, imm8
TEST mreg16/32, imm16/32
TEST mem16/32, imm16/32
VERR mreg16
long
alu
11-000-xxx
mm-000-xxx
11-000-xxx
mm-000-xxx
11-100-xxx
long
alux
long
load, alux
alu
long
long
load, alu
00h
00h
00h
vector
VERR mem16
mm-100-xxx vector
11-101-xxx vector
VERW mreg16
Chapter 3
Software Environment
73
Preliminary Information
®
Mobile AMD-K6 -2+ Processor Data Sheet
23446B/0—June 2000
Table 12. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
VERW mem16
0Fh
9Bh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
86h
86h
87h
87h
90h
91h
92h
93h
94h
95h
96h
97h
D7h
30h
30h
31h
31h
32h
32h
33h
33h
34h
35h
80h
80h
00h
mm-101-xxx
vector
vector
vector
vector
vector
WAIT
WBINVD
09h
30h
C0h
C0h
C1h
C1h
WRMSR
XADD mreg8, reg8
XADD mem8, reg8
XADD mreg16/32, reg16/32
XADD mem16/32, reg16/32
XCHG reg8, mreg8
XCHG reg8, mem8
XCHG reg16/32, mreg16/32
XCHG reg16/32, mem16/32
XCHG EAX, EAX
11-100-xxx
mm-100-xxx vector
11-101-xxx
mm-101-xxx
11-xxx-xxx
vector
vector
vector
vector
vector
vector
short
long
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
limm
XCHG EAX, ECX
alu, alu, alu
alu, alu, alu
alu, alu, alu
alu, alu, alu
alu, alu, alu
alu, alu, alu
alu, alu, alu
XCHG EAX, EDX
XCHG EAX, EBX
long
long
XCHG EAX, ESP
long
XCHG EAX, EBP
long
XCHG EAX, ESI
long
XCHG EAX, EDI
long
XLAT
vector
short
long
XOR mreg8, reg8
XOR mem8, reg8
XOR mreg16/32, reg16/32
XOR mem16/32, reg16/32
XOR reg8, mreg8
XOR reg8, mem8
XOR reg16/32, mreg16/32
XOR reg16/32, mem16/32
XOR AL, imm8
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
alux
load, alux, store
alu
short
long
load, alu, store
alux
short
short
short
short
short
short
short
long
load, alux
alu
load, alu
alux
XOR EAX, imm16/32
XOR mreg8, imm8
XOR mem8, imm8
alu
11-110-xxx
alux
mm-110-xxx
load, alux, store
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Table 12. Integer Instructions (continued)
First
Instruction Mnemonic
Byte
Second
Byte
ModR/M
Byte
Decode
Type
RISC86
Operations
XOR mreg16/32, imm16/32
81h
81h
83h
83h
11-110-xxx
mm-110-xxx
11-110-xxx
short
long
short
long
alu
XOR mem16/32, imm16/32
load, alu, store
alux
XOR mreg16/32, imm8 (signed ext.)
XOR mem16/32, imm8 (signed ext.)
mm-110-xxx
load, alux, store
Table 13. Floating-Point Instructions
Instruction Mnemonic
First Second ModR/M Decode
RISC86
Operations
Note
Byte
Byte
F0h
F1h
Byte
Type
F2XM1
D9h
D9h
D8h
D8h
DCh
DCh
DEh
DFh
DFh
D9h
DBh
D8h
D8h
DCh
D8h
D8h
DCh
DEh
D9h
D9h
D8h
D8h
D8h
short float
short float
short float
FABS
FADD ST(0), ST(i)
FADD ST(0), mem32real
FADD ST(i), ST(0)
FADD ST(0), mem64real
FADDP ST(i), ST(0)
FBLD
11-000-xxx
*
*
*
mm-000-xxx short fload, float
11-000-xxx short float
mm-000-xxx short fload, float
11-000-xxx short float
mm-100-xxx vector
mm-110-xxx vector
FBSTP
FCHS
E0h
E2h
short float
FCLEX
vector
FCOM ST(0), ST(i)
FCOM ST(0), mem32real
FCOM ST(0), mem64real
FCOMP ST(0), ST(i)
FCOMP ST(0), mem32real
FCOMP ST(0), mem64real
FCOMPP
11-010-xxx
short float
*
*
mm-010-xxx short fload, float
mm-010-xxx short fload, float
11-011-xxx
short float
mm-011-xxx short fload, float
mm-011-xxx short fload, float
D9h
FFh
F6h
11-011-001
short float
short float
short float
short float
short float
short float
FCOS
FDECSTP
FDIV ST(0), ST(i) (single precision)
FDIV ST(0), ST(i) (double precision)
FDIV ST(0), ST(i) (extended precision)
Note:
11-110-xxx
11-110-xxx
11-110-xxx
*
*
*
*
The last three bits of the modR/M byte select the stack entry ST(i).
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Table 13. Floating-Point Instructions (continued)
First Second ModR/M Decode
RISC86
Operations
Instruction Mnemonic
Note
Byte
DCh
DCh
DCh
D8h
DCh
DEh
D8h
DCh
D8h
DCh
DEh
DDh
DAh
DEh
DAh
DEh
DAh
DEh
DAh
DEh
DAh
DEh
DFh
DBh
DFh
DAh
DEh
D9h
DBh
DFh
DBh
Byte
Byte
Type
FDIV ST(i), ST(0) (single precision)
FDIV ST(i), ST(0) (double precision)
FDIV ST(i), ST(0) (extended precision)
FDIV ST(0), mem32real
FDIV ST(0), mem64real
FDIVP ST(0), ST(i)
11-111-xxx
11-111-xxx
11-111-xxx
short float
short float
short float
*
*
*
mm-110-xxx short fload, float
mm-110-xxx short fload, float
11-111-xxx
11-110-xxx
11-111-xxx
short float
short float
short float
*
*
*
FDIVR ST(0), ST(i)
FDIVR ST(i), ST(0)
FDIVR ST(0), mem32real
FDIVR ST(0), mem64real
FDIVRP ST(i), ST(0)
FFREE ST(i)
mm-111-xxx short fload, float
mm-111-xxx short fload, float
11-110-xxx
11-000-xxx
short float
short float
*
*
FIADD ST(0), mem32int
FIADD ST(0), mem16int
FICOM ST(0), mem32int
FICOM ST(0), mem16int
FICOMP ST(0), mem32int
FICOMP ST(0), mem16int
FIDIV ST(0), mem32int
FIDIV ST(0), mem16int
FIDIVR ST(0), mem32int
FIDIVR ST(0), mem16int
FILD mem16int
mm-000-xxx short fload, float
mm-000-xxx short fload, float
mm-010-xxx short fload, float
mm-010-xxx short fload, float
mm-011-xxx short fload, float
mm-011-xxx short fload, float
mm-110-xxx short fload, float
mm-110-xxx short fload, float
mm-111-xxx short fload, float
mm-111-xxx short fload, float
mm-000-xxx short fload, float
mm-000-xxx short fload, float
mm-101-xxx short fload, float
mm-001-xxx short fload, float
mm-001-xxx short fload, float
short
FILD mem32int
FILD mem64int
FIMUL ST(0), mem32int
FIMUL ST(0), mem16int
FINCSTP
F7h
E3h
FINIT
vector
FIST mem16int
mm-010-xxx short fload, float
mm-010-xxx short fload, float
FIST mem32int
Note:
*
The last three bits of the modR/M byte select the stack entry ST(i).
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Table 13. Floating-Point Instructions (continued)
Instruction Mnemonic
First Second ModR/M Decode
RISC86
Operations
Note
Byte
DFh
DBh
DFh
DAh
DEh
DAh
DEh
D9h
D9h
DDh
DBh
D9h
D9h
D9h
D9h
D9h
D9h
D9h
D9h
D9h
D8h
DCh
D8h
DCh
DEh
D9h
D9h
D9h
D9h
D9h
D9h
Byte
Byte
Type
FISTP mem16int
FISTP mem32int
FISTP mem64int
FISUB ST(0), mem32int
FISUB ST(0), mem16int
FISUBR ST(0), mem32int
FISUBR ST(0), mem16int
FLD ST(i)
mm-011-xxx short fload, float
mm-011-xxx short fload, float
mm-111-xxx short fload, float
mm-100-xxx short fload, float
mm-100-xxx short fload, float
mm-101-xxx short fload, float
mm-101-xxx short fload, float
11-000-xxx
short fload, float
*
FLD mem32real
FLD mem64real
FLD mem80real
FLD1
mm-000-xxx short fload, float
mm-000-xxx short fload, float
mm-101-xxx vector
short fload, float
mm-101-xxx vector
mm-100-xxx short fload, float
short float
E8h
FLDCW
FLDENV
FLDL2E
EAh
E9h
ECh
EDh
EBh
EEh
FLDL2T
short float
FLDLG2
short float
FLDLN2
short float
FLDPI
short float
FLDZ
short float
FMUL ST(0), ST(i)
FMUL ST(i), ST(0)
FMUL ST(0), mem32real
FMUL ST(0), mem64real
FMULP ST(0), ST(i)
FNOP
11-001-xxx
11-001-xxx
short float
short float
*
*
mm-001-xxx short fload, float
mm-001-xxx short fload, float
11-001-xxx
short float
short float
short float
short float
short float
vector
*
D0h
F3h
F8h
F5h
F2h
FCh
FPATAN
FPREM
FPREM1
FPTAN
FRNDINT
short float
Note:
*
The last three bits of the modR/M byte select the stack entry ST(i).
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Table 13. Floating-Point Instructions (continued)
First Second ModR/M Decode
RISC86
Operations
Instruction Mnemonic
FRSTOR
Note
Byte
DDh
DDh
D9h
D9h
D9h
D9h
D9h
D9h
D9h
DDh
DDh
D9h
D9h
D9h
DDh
D9h
DDh
DFh
DDh
D8h
DCh
D8h
DCh
DEh
D8h
DCh
D8h
DCh
DEh
D9h
DDh
Byte
Byte
Type
mm-100-xxx vector
mm-110-xxx vector
FSAVE
FSCALE
FDh
FEh
FBh
FAh
FAh
FAh
short float
FSIN
short float
vector
FSINCOS
FSQRT (single precision)
FSQRT (double precision)
FSQRT (extended precision)
FST mem32real
FST mem64real
FST ST(i)
short float
short float
short float
mm-010-xxx short fstore
mm-010-xxx short fstore
11-010-xxx
short fstore
*
*
FSTCW
mm-111-xxx vector
FSTENV
mm-110-xxx vector
FSTP mem32real
FSTP mem64real
FSTP mem80real
FSTP ST(i)
mm-011-xxx short fstore
mm-011-xxx short fstore
mm-111-xxx vector
11-011-xxx
short float
vector
FSTSW AX
E0h
FSTSW mem16
FSUB ST(0), mem32real
FSUB ST(0), mem64real
FSUB ST(0), ST(i)
FSUB ST(i), ST(0)
FSUBP ST(0), ST(i)
FSUBR ST(0), mem32real
FSUBR ST(0), mem64real
FSUBR ST(0), ST(i)
FSUBR ST(i), ST(0)
FSUBRP ST(i), ST(0)
FTST
mm-111-xxx vector
mm-100-xxx short fload, float
mm-100-xxx short fload, float
11-100-xxx
11-101-xxx
11-101-xxx
short float
short float
short float
*
*
*
mm-101-xxx short fload, float
mm-101-xxx short fload, float
11-100-xxx
11-101-xxx
11-100-xxx
short float
short float
short float
short float
short float
*
*
*
E4h
FUCOM
11-100-xxx
Note:
*
The last three bits of the modR/M byte select the stack entry ST(i).
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Table 13. Floating-Point Instructions (continued)
Instruction Mnemonic
First Second ModR/M Decode
RISC86
Operations
Note
Byte
DDh
DAh
D9h
D9h
D9h
D9h
D9h
9Bh
Byte
Byte
Type
FUCOMP
FUCOMPP
FXAM
11-101-xxx
short float
short float
short float
short float
vector
E9h
E5h
FXCH
11-001-xxx
FXTRACT
FYL2X
F4h
F1h
F9h
short float
short float
vector
FYL2XP1
FWAIT
Note:
*
The last three bits of the modR/M byte select the stack entry ST(i).
Table 14. MMX™ Technology Instructions
Prefix First ModR/M Decode
RISC86
Operations
Instruction Mnemonic
Note
Byte(s) Byte
77h
6Eh 11-xxx-xxx
6Eh mm-xxx-xxx short mload
Byte
Type
EMMS
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
vector
MOVD mmreg, mreg32
MOVD mmreg, mem32
MOVD mreg32, mmreg
MOVD mem32, mmreg
MOVQ mmreg1, mmreg2
MOVQ mmreg, mem64
MOVQ mmreg2, mmreg1
MOVQ mem64, mmreg
PACKSSDW mmreg1, mmreg2
PACKSSDW mmreg, mem64
PACKSSWB mmreg1, mmreg2
PACKSSWB mmreg, mem64
PACKUSWB mmreg1, mmreg2
PACKUSWB mmreg, mem64
PADDB mmreg1, mmreg2
PADDB mmreg, mem64
PADDD mmreg1, mmreg2
Note:
short meu
**
**
7Eh 11-xxx-xxx
short mstore, load
7Eh mm-xxx-xxx short mstore
6Fh 11-xxx-xxx
6Fh mm-xxx-xxx short mload
7Fh 11-xxx-xxx short meu
7Fh mm-xxx-xxx short mstore
6Bh 11-xxx-xxx short meu
6Bh mm-xxx-xxx short mload, meu
63h 11-xxx-xxx short meu
63h mm-xxx-xxx short mload, meu
67h 11-xxx-xxx short meu
67h mm-xxx-xxx short mload, meu
FCh 11-xxx-xxx short meu
FCh mm-xxx-xxx short mload, meu
FEh 11-xxx-xxx short meu
short meu
** Bits 2, 1, and 0 of the modR/M byte select the integer register.
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Table 14. MMX™ Technology Instructions (continued)
Prefix First ModR/M Decode
Byte(s) Byte Byte Type
RISC86
Operations
Instruction Mnemonic
PADDD mmreg, mem64
Note
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
FEh mm-xxx-xxx short mload, meu
ECh 11-xxx-xxx short meu
ECh mm-xxx-xxx short mload, meu
EDh 11-xxx-xxx short meu
EDh mm-xxx-xxx short mload, meu
DCh 11-xxx-xxx short meu
DCh mm-xxx-xxx short mload, meu
DDh 11-xxx-xxx short meu
DDh mm-xxx-xxx short mload, meu
FDh 11-xxx-xxx short meu
FDh mm-xxx-xxx short mload, meu
DBh 11-xxx-xxx short meu
DBh mm-xxx-xxx short mload, meu
DFh 11-xxx-xxx short meu
DFh mm-xxx-xxx short mload, meu
74h 11-xxx-xxx short meu
74h mm-xxx-xxx short mload, meu
76h 11-xxx-xxx short meu
76h mm-xxx-xxx short mload, meu
75h 11-xxx-xxx short meu
75h mm-xxx-xxx short mload, meu
64h 11-xxx-xxx short meu
64h mm-xxx-xxx short mload, meu
66h 11-xxx-xxx short meu
66h mm-xxx-xxx short mload, meu
65h 11-xxx-xxx short meu
65h mm-xxx-xxx short mload, meu
F5h 11-xxx-xxx short meu
F5h mm-xxx-xxx short mload, meu
E5h 11-xxx-xxx short meu
E5h mm-xxx-xxx short mload, meu
PADDSB mmreg1, mmreg2
PADDSB mmreg, mem64
PADDSW mmreg1, mmreg2
PADDSW mmreg, mem64
PADDUSB mmreg1, mmreg2
PADDUSB mmreg, mem64
PADDUSW mmreg1, mmreg2
PADDUSW mmreg, mem64
PADDW mmreg1, mmreg2
PADDW mmreg, mem64
PAND mmreg1, mmreg2
PAND mmreg, mem64
PANDN mmreg1, mmreg2
PANDN mmreg, mem64
PCMPEQB mmreg1, mmreg2
PCMPEQB mmreg, mem64
PCMPEQD mmreg1, mmreg2
PCMPEQD mmreg, mem64
PCMPEQW mmreg1, mmreg2
PCMPEQW mmreg, mem64
PCMPGTB mmreg1, mmreg2
PCMPGTB mmreg, mem64
PCMPGTD mmreg1, mmreg2
PCMPGTD mmreg, mem64
PCMPGTW mmreg1, mmreg2
PCMPGTW mmreg, mem64
PMADDWD mmreg1, mmreg2
PMADDWD mmreg, mem64
PMULHW mmreg1, mmreg2
PMULHW mmreg, mem64
Note:
** Bits 2, 1, and 0 of the modR/M byte select the integer register.
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Table 14. MMX™ Technology Instructions (continued)
Instruction Mnemonic
Prefix First ModR/M Decode
RISC86
Operations
Note
Byte(s) Byte
Byte
Type
PMULLW mmreg1, mmreg2
PMULLW mmreg, mem64
POR mmreg1, mmreg2
POR mmreg, mem64
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
D5h 11-xxx-xxx
short meu
D5h mm-xxx-xxx short mload, meu
EBh 11-xxx-xxx
EBh mm-xxx-xxx short mload, meu
F2h 11-xxx-xxx short meu
F2h mm-xxx-xxx short mload, meu
short meu
PSLLD mmreg1, mmreg2
PSLLD mmreg, mem64
PSLLD mmreg, imm8
PSLLQ mmreg1, mmreg2
PSLLQ mmreg, mem64
PSLLQ mmreg, imm8
PSLLW mmreg1, mmreg2
PSLLW mmreg, mem64
PSLLW mmreg, imm8
PSRAD mmreg1, mmreg2
PSRAD mmreg, mem64
PSRAD mmreg, imm8
PSRAW mmreg1, mmreg2
PSRAW mmreg, mem64
PSRAW mmreg, imm8
PSRLD mmreg1, mmreg2
PSRLD mmreg, mem64
PSRLD mmreg, imm8
PSRLQ mmreg1, mmreg2
PSRLQ mmreg, mem64
PSRLQ mmreg, imm8
PSRLW mmreg1, mmreg2
PSRLW mmreg, mem64
PSRLW mmreg, imm8
PSUBB mmreg1, mmreg2
PSUBB mmreg, mem64
PSUBD mmreg1, mmreg2
Note:
72h 11-110-xxx
F3h 11-xxx-xxx
short meu
short meu
F3h mm-xxx-xxx short mload, meu
73h 11-110-xxx
F1h 11-xxx-xxx
short meu
short meu
F1h mm-xxx-xxx short mload, meu
71h 11-110-xxx
E2h 11-xxx-xxx
short meu
short meu
E2h mm-xxx-xxx short mload, meu
72h 11-100-xxx
E1h 11-xxx-xxx
short meu
short meu
E1h mm-xxx-xxx short mload, meu
71h 11-100-xxx
D2h 11-xxx-xxx
short meu
short meu
D2h mm-xxx-xxx short mload, meu
72h 11-010-xxx
D3h 11-xxx-xxx
short meu
short meu
D3h mm-xxx-xxx short mload, meu
73h 11-010-xxx
D1h 11-xxx-xxx
short meu
short meu
D1h mm-xxx-xxx short mload, meu
71h 11-010-xxx
F8h 11-xxx-xxx
short meu
short meu
F8h mm-xxx-xxx short mload, meu
FAh 11-xxx-xxx short meu
** Bits 2, 1, and 0 of the modR/M byte select the integer register.
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Table 14. MMX™ Technology Instructions (continued)
Prefix First ModR/M Decode
Byte(s) Byte Byte Type
RISC86
Operations
Instruction Mnemonic
PSUBD mmreg, mem64
Note
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
FAh mm-xxx-xxx short mload, meu
E8h 11-xxx-xxx short meu
E8h mm-xxx-xxx short mload, meu
E9h 11-xxx-xxx short meu
E9h mm-xxx-xxx short mload, meu
D8h 11-xxx-xxx short meu
D8h mm-xxx-xxx short mload, meu
D9h 11-xxx-xxx short meu
D9h mm-xxx-xxx short mload, meu
F9h 11-xxx-xxx short meu
F9h mm-xxx-xxx short mload, meu
68h 11-xxx-xxx short meu
68h mm-xxx-xxx short mload, meu
6Ah 11-xxx-xxx short meu
6Ah mm-xxx-xxx short mload, meu
69h 11-xxx-xxx short meu
69h mm-xxx-xxx short mload, meu
60h 11-xxx-xxx short meu
60h mm-xxx-xxx short mload, meu
62h 11-xxx-xxx short meu
62h mm-xxx-xxx short mload, meu
61h 11-xxx-xxx short meu
61h mm-xxx-xxx short mload, meu
EFh 11-xxx-xxx short meu
EFh mm-xxx-xxx short mload, meu
PSUBSB mmreg1, mmreg2
PSUBSB mmreg, mem64
PSUBSW mmreg1, mmreg2
PSUBSW mmreg, mem64
PSUBUSB mmreg1, mmreg2
PSUBUSB mmreg, mem64
PSUBUSW mmreg1, mmreg2
PSUBUSW mmreg, mem64
PSUBW mmreg1, mmreg2
PSUBW mmreg, mem64
PUNPCKHBW mmreg1, mmreg2
PUNPCKHBW mmreg, mem64
PUNPCKHDQ mmreg1, mmreg2
PUNPCKHDQ mmreg, mem64
PUNPCKHWD mmreg1, mmreg2
PUNPCKHWD mmreg, mem64
PUNPCKLBW mmreg1, mmreg2
PUNPCKLBW mmreg, mem32
PUNPCKLDQ mmreg1, mmreg2
PUNPCKLDQ mmreg, mem32
PUNPCKLWD mmreg1, mmreg2
PUNPCKLWD mmreg, mem32
PXOR mmreg1, mmreg2
PXOR mmreg, mem64
Note:
** Bits 2, 1, and 0 of the modR/M byte select the integer register.
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Table 15. 3DNow!™ Technology Instructions
Instruction Mnemonic
Prefix Opcode ModR/M Decode
RISC86
Operations
Note
Byte(s)
Byte
Byte
Type
FEMMS
0Fh
0Eh
BFh
BFh
vector
PAVGUSB mmreg1, mmreg2
PAVGUSB mmreg, mem64
PF2ID mmreg1, mmreg2
PF2ID mmreg, mem64
PFACC mmreg1, mmreg2
PFACC mmreg, mem64
PFADD mmreg1, mmreg2
PFADD mmreg, mem64
PFCMPEQ mmreg1, mmreg2
PFCMPEQ mmreg, mem64
PFCMPGE mmreg1, mmreg2
PFCMPGE mmreg, mem64
PFCMPGT mmreg1, mmreg2
PFCMPGT mmreg, mem64
PFMAX mmreg1, mmreg2
PFMAX mmreg, mem64
PFMIN mmreg1, mmreg2
PFMIN mmreg, mem64
PFMUL mmreg1, mmreg2
PFMUL mmreg, mem64
PFRCP mmreg1, mmreg2
PFRCP mmreg, mem64
PFRCPIT1 mmreg1, mmreg2
PFRCPIT1 mmreg, mem64
PFRCPIT2 mmreg1, mmreg2
PFRCPIT2 mmreg, mem64
PFRSQIT1 mmreg1, mmreg2
PFRSQIT1 mmreg, mem64
Notes:
0Fh, 0Fh
0Fh, 0Fh
11-xxx-xxx
short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
0Fh, 0Fh 1Dh
0Fh, 0Fh 1Dh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
AEh
AEh
9Eh
9Eh
B0h
B0h
90h
90h
A0h
A0h
A4h
A4h
94h
94h
B4h
B4h
96h
96h
A6h
A6h
B6h
B6h
A7h
A7h
1. For PREFETCH and PREFETCHW, the mem8 value refers to a byte address within the 32-byte line that will be
prefetched.
2. PREFETCHW will be implemented in a future K86 processor. On the Mobile AMD-K6-2+ processor, this instruction
performs in the same manner as the PREFETCH instruction.
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Table 15. 3DNow!™ Technology Instructions (continued)
Prefix Opcode ModR/M Decode
RISC86
Operations
Instruction Mnemonic
Note
Byte(s)
0Fh, 0Fh
0Fh, 0Fh
Byte
97h
97h
Byte
Type
PFRSQRT mmreg1, mmreg2
PFRSQRT mmreg, mem64
PFSUB mmreg1, mmreg2
PFSUB mmreg, mem64
PFSUBR mmreg1, mmreg2
PFSUBR mmreg, mem64
PI2FD mmreg1, mmreg2
PI2FD mmreg, mem64
PMULHRW mmreg1, mmreg2
PMULHRW mmreg1, mem64
PREFETCH mem8
11-xxx-xxx
short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
0Fh, 0Fh 9Ah
0Fh, 0Fh 9Ah
0Fh, 0Fh AAh
0Fh, 0Fh AAh
0Fh, 0Fh 0Dh
0Fh, 0Fh 0Dh
0Fh, 0Fh
0Fh, 0Fh
0Fh
B7h
B7h
0Dh mm-000-xxx vector load
0Dh mm-001-xxx vector load
1
PREFETCHW mem8
0Fh
1, 2
Notes:
1. For PREFETCH and PREFETCHW, the mem8 value refers to a byte address within the 32-byte line that will be
prefetched.
2. PREFETCHW will be implemented in a future K86 processor. On the Mobile AMD-K6-2+ processor, this instruction
performs in the same manner as the PREFETCH instruction.
Table 16. 3DNow!™ Technology DSP Extensions
Prefix Opcode ModR/M Decode
RISC86
Operations
Instruction Mnemonic
Note
Byte(s)
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
Byte
1Ch
1Ch
8Ah
8Ah
8Eh
8Eh
0Ch
0Ch
BBh
BBh
Byte
Type
PF2IW mmreg1, mmreg2
PF2IW mmreg, mem64
11-xxx-xxx
short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
11-xxx-xxx short meu
mm-xxx-xxx short mload, meu
PFNACC mmreg1, mmreg2
PFNACC mmreg, mem64
PFPNACC mmreg1, mmreg2
PFPNACC mmreg, mem64
PI2FW mmreg1, mmreg2
PI2FW mmreg, mem64
PSWAPD mmreg1, mmreg2
PSWAPD mmreg, mem64
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4
Signal Descriptions
4.1
Signal Terminology
The following terminology is used in this chapter:
■ Driven —The processor actively pulls the signal up to the
High-voltage state or pulls the signal down to the
Low-voltage state.
■ Floated—The the signal is not being driven by the processor
(high-impedance state), which allows another device to
drive this signal.
■ Asserted—For all active-High signals, the term asserted
means the signal is in the High-voltage state. For all
active-Low signals, the term asserted means the signal is in
the Low-voltage state.
■ Negated—For all active-High signals, the term negated means
the signal is in the Low-voltage state. For all active-Low
signals, the term negated means the signal is in the
High-voltage state.
■ Sampled—The processor has measured the state of a signal
at predefined points in time and will take the appropriate
action based on the state of the signal. If a signal is not
sampled by the processor, its assertion or negation has no
effect on the operation of the processor.
Figure 54 on page 86 shows the signals grouped by function. The
arrows in the figure indicate the direction of the signal, either
into or out of the processor. Signals with double-headed arrows
are bidirectional. Signals with pound signs (#) are active Low.
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Clock
Voltage Detection
VID[4:0]
BF[2:0]
CLK
VCC2DET
VCC2H/L#
AHOLD
BOFF#
BREQ
HLDA
HOLD
BRDY#
BRDYC#
D[63:0]
DP[7:0]
PCHK#
Data
and
Data
Parity
Bus
Arbitration
A20M#
A[31:3]
AP
Address
and
Address
Parity
EADS#
HIT#
HITM#
INV
Inquire
Cycles
ADS#
ADSC#
APCHK#
BE[7:0]#
®
D/C#
Mobile AMD-K6 -2+
FERR#
IGNNE#
Floating-Point
Error Handling
EWBE#
LOCK#
M/IO#
NA#
Processor
Cycle
Definition
and
Control
SCYC
W/R#
FLUSH#
INIT
INTR
NMI
RESET
SMI#
External
Interrupts,
SMM, Reset and
Initialization
CACHE#
KEN#
PCD
Cache
Control
PWT
SMIACT#
STPCLK#
WB/WT#
TCK TDI TDO TMS
TRST#
JTAG Test
Figure 54. Logic Symbol Diagram
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4.2
A20M# (Address Bit 20 Mask)
Input
Summary
A20M# is u se d t o sim u la t e t h e b e h avior of t h e 8086 wh e n
r u n n in g in R e a l m od e . Th e a sse r t ion of A20M # ca u se s t h e
processor to force bit 20 of the physical address to 0 prior to
accessing the caches or driving out a memory bus cycle. The
clearing of address bit 20 maps addresses that extend above the
8086 1-Mbyte limit to below 1 Mbyte.
Sampled
The processor samples A20M# as a level-sensitive input on every
clock e d ge . Th e syst e m logic ca n d r ive t h e sign a l e it h e r
s y n c h r o n o u s l y o r a s y n c h r o n o u s l y. I f i t i s a s s e r t e d
asynchronously, it must be asserted for a minimum pulse width
of two clocks.
The following list explains the effects of the processor sampling
A20M# asserted under various conditions:
■ Inquire cycles and writeback cycles are not affected by the
state of A20M#.
■ The assertion of A20M# in System Management Mode
(SMM) is ignored.
■ When A20M# is sampled asserted in Protected mode, it
causes unpredictable processor operation. A20M# is only
defined in Real mode.
■ To ensure that A20M# is recognized before the first ADS#
occurs following the negation of RESET, A20M# must be
sampled asserted on the same clock edge that RESET is
sampled negated or on one of the two subsequent clock
edges.
■ To ensure A20M# is recognized before the execution of an
instruction, a serializing instruction must be executed
between the instruction that asserts A20M# and the
targeted instruction.
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4.3
A[31:3] (Address Bus)
A[31:5] Bidirectional, A[4:3] Output
Summary
A[31:3] contain the physical address for the current bus cycle.
The processor drives addresses on A[31:3] during memory and
I/O cycles, and cycle definition information during special bus
cycle s. Th e p roce ssor sa m p le s a dd re sse s on A[31:5] d u r in g
inquire cycles.
Driven, Sampled, and
Floated
As Outputs: A[31:3] are driven valid off the same clock edge as
ADS # a n d re m a in in t h e sa m e st a t e u n t il t h e clock e d ge on
which NA# or the last expected BRDY# of the cycle is sampled
asserted. A[31:3] are driven during memory cycles, I/O cycles,
sp e cia l b u s cycle s, a n d in t e r r u p t a ck n owle d ge cycle s. Th e
processor continues to drive the address bus while the bus is
idle.
As Inputs: The processor samples A[31:5] during inquire cycles
on the clock edge on which EADS # is sampled asserted. Even
though A4 and A3 are not used during the inquire cycle, they
must be driven to a valid state and must meet the same timings
as A[31:5].
A[31:3] are floated off the clock edge that AHOLD or BOFF # is
sa m p le d a sser t ed a n d off t h e clock e d ge t h a t t h e p roce ssor
asserts HLDA in recognition of HOLD.
The processor resumes driving A[31:3] off the clock edge on
which the processor samples AHOLD or BOFF # negated and off
the clock edge on which the processor negates HLDA.
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4.4
ADS# (Address Strobe)
Output
Summary
Th e assertion of ADS # indicates the beginning of a new bus
cycle . Th e a d d r e ss b u s a n d a ll cycle d e fin it ion sign a ls
corresponding to this bus cycle are driven valid off the same
clock edge as ADS#.
Driven and Floated
ADS # is assert ed for one clock at the beginning of e ach bus
cycle. For non-pipelined cycles, ADS# can be asserted as early as
the clock edge after the clock edge on which the last expected
BRDY# of the cycle is sampled asserted, resulting in a single idle
state between cycles. For pipelined cycles if the processor is
prepared to start a new cycle, ADS# can be asserted as early as
one clock edge after NA# is sampled asserted.
If AHOLD is sampled asserted, ADS # is only driven in order to
perform a writeback cycle due to an inquire cycle that hits a
modified cache line.
Th e processor float s ADS # off t he clock e dge that BOFF # is
sa m p le d a sser t ed a n d off t h e clock e d ge t h a t t h e p roce ssor
asserts HLDA in recognition of HOLD.
4.5
ADSC# (Address Strobe Copy)
Output
Summary
ADSC # has the identical function and timing as ADS #. In the
event ADS# becomes too heavily loaded due to a large fanout in
a syst e m , ADSC # ca n b e u se d t o sp lit t h e loa d a cross t wo
outputs, which can improve system timing.
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4.6
AHOLD (Address Hold)
Input
Summary
AHOLD can be asserted by the system to initiate one or more
inquire cycles. To allow t he syste m t o drive the a ddress bus
during an inquire cycle, the processor floats A[31:3] and AP off
the clock edge on which AHOLD is sampled asserted. The data
bus and all other control and status signals remain under the
control of the processor and are not floated. This allows a bus
cycle that is in progress when AHOLD is sampled asserted to
con t inu e t o com p let ion . The p roce ssor re su m es d r ivin g t h e
address bus off the clock e dge on which AHOLD is sampled
negated.
If AHOLD is sampled asserted, ADS# is only asserted in order to
perform a writeback cycle due to an inquire cycle that hits a
modified cache line.
Sampled
The processor samples AHOLD on every clock edge. AHOLD is
recognized while INIT and RESET are sampled asserted.
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4.7
AP (Address Parity)
Bidirectional
Summary
AP contains the even parity bit for cache line addresses driven
a n d sa m p le d on A[31:5]. E ve n p a r it y m e a n s t h a t t h e t ot a l
number of 1 bits on AP and A[31:5] is even. (A4 and A3 are not
used for the generation or checking of address parity because
these bits are not required to address a cache line.) AP is driven
b y t h e p roce ssor d u r in g p roce ssor -in it ia t e d cycle s a n d is
sampled by the processor during inquire cycles. If AP does not
reflect even parity during an inquire cycle, the processor asserts
APCHK# to indicate an address bus parity check. The processor
does not take an internal exception as the result of detecting an
a d d re ss b u s p a r it y ch e ck , a n d syst e m logic m u st re sp on d
appropriately to the assertion of this signal.
Driven, Sampled, and
Floated
As an Output: The processor drives AP valid off the clock edge on
which ADS# is asserted until the clock edge on which NA# or the
last exp ected BRDY # of the cycle is sampled asserted. AP is
driven during memory cycles, I/O cycles, special bus cycles, and
interrupt acknowledge cycles. The processor continues to drive
AP while the bus is idle.
As an Input: The processor samples AP during inquire cycles on
the clock edge on which EADS# is sampled asserted.
Th e p roce ssor floa t s AP off t h e clock e d ge t h a t AH OLD or
BOF F # is sa m p le d a sse r t e d a n d off t h e clock e d ge t h a t t h e
processor asserts HLDA in recognition of HOLD.
The processor resumes driving AP off the clock edge on which
the processor samples AHOLD or BOFF # negated and off the
clock edge on which the processor negates HLDA.
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4.8
APCHK# (Address Parity Check)
Output
Summary
If t h e p roce ssor d e t e ct s a n a dd re ss p a r it y e r ror d u r in g a n
inquire cycle, APCHK# is asserted for one clock. The processor
does not take an internal exception as the result of detecting an
a d d re ss b u s p a r it y ch e ck , a n d syst e m logic m u st re sp on d
appropriately to the assertion of this signal.
Th e p roce ssor is d e sign e d so t ha t AP CHK # d oe s n ot glit ch,
enabling the signal to be used as a clocking source for system
logic.
Driven
APCHK# is driven valid off the clock edge after the clock edge
on which the processor samples EADS# asserted. It is negated
off the next clock edge.
APCHK# is always driven except in the Tri-State Test mode.
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4.9
BE[7:0]# (Byte Enables)
Output
Summary
BE[7:0]# are used by the processor to indicate the valid data
bytes during a write cycle and the requested data bytes during a
read cycle. The byte enables can be used to derive address bits
A[2:0], which are not physically part of the processor’s address
bus. The processor checks and generates valid data parity for
the data bytes that are valid as defined by the byte enables. The
eight byte enables correspond to the eight bytes of the data bus
as follows:
■ BE7#: D[63:56]
■ BE6#: D[55:48]
■ BE5#: D[47:40]
■ BE4#: D[39:32]
■ BE3#: D[31:24]
■ BE2#: D[23:16]
■ BE1#: D[15:8]
■ BE0#: D[7:0]
The processor expects data to be driven by the system logic on
all eight bytes of the data bus during a burst cache-line read
cycle, independent of the byte enables that are asserted.
The byte enables are also used to distinguish between special
bus cycles as defined in Table 24 on page 129.
Driven and Floated
BE[7:0]# are driven off the same clock edge as ADS# and remain
in the same state until the clock edge on which NA# or the last
expected BRDY# of the cycle is sampled asserted. BE[7:0]# are
driven during memory cycles, I/O cycles, special bus cycles, and
interrupt acknowledge cycles.
The processor floats BE[7:0]# off the clock edge that BOFF # is
sa m p le d a sser t ed a n d off t h e clock e d ge t h a t t h e p roce ssor
asserts HLDA in recognition of HOLD. Unlike the address bus,
BE[7:0]# are not floated in response to AHOLD.
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4.10
BF[2:0] (Bus Frequency)
Inputs, Internal Pullups
Summary
BF [2:0] d e t e r m in e t h e in t e r n a l op e ra t in g fre q u e n cy of t h e
processor. The frequency of the CLK input signal is multiplied
internally by a ratio determined by the state of these signals as
defined in Table 17. BF[2:0] have weak internal pullup s and
default to the 3.5 multiplier if left unconnected.
Table 17. Processor-to-Bus Clock Ratios
State of BF[2:0] Inputs
Processor-Clock to Bus-Clock Ratio
100b
101b
110b
111b
000b
001b
010b
011b
2.0x
3.0x
6.0x
3.5x
4.5x
5.0x
4.0x
5.5x
Sampled
BF[2:0] are sampled during the falling transition of RESET.
They must meet a minimum setup time of 1.0 ms and a minimum
hold time of two clocks relative to the negation of RESET.
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4.11
BOFF# (Backoff)
Input
Summary
If BOFF # is sampled asserted, the processor unconditionally
aborts any cycles in progress and transitions to a bus hold state
by floating the following signals: A[31:3], ADS #, ADSC #, AP,
BE[7:0]#, CACHE #, D[63:0], D/C#, DP[7:0], LOCK#, M/IO#, PCD,
P WT, SCYC, a n d W/R #. Th e se sign a ls re m a in floa t e d u n t il
BOFF # is sampled negated. This allows an alternate bus master
or the system to control the bus.
When BOFF # is sampled negated, any processor cycle that was
aborted due to t he assertion of BOFF # is rest art ed from the
beginning of the cycle, regardless of the number of transfers
that were completed. If BOFF # is sampled asserted on the same
clock edge as BRDY # of a bus cycle of any length, then BOFF #
t akes p rece d e n ce ove r t h e BR DY #. In this ca se , t h e cycle is
aborted and restarted after BOFF # is sampled negated.
Sampled
BOFF # is sampled on every clock edge. The processor floats its
b u s sign a ls off t h e clock e d ge on wh ich BOF F # is sa m p le d
asserted. These signals remain floated until the clock edge on
which BOFF # is sampled negated.
BOF F # is re cogn ize d wh ile INIT a n d R E SE T a re sa m p le d
asserted.
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4.12
BRDY# (Burst Ready)
Input, Internal Pullup
Summary
BRDY # is asserted to the processor by system logic to indicate
either that the data bus is being driven with valid data during a
read cycle or that the data bus has been latched during a write
cycle. If necessary, the system logic can insert bus cycle wait
states by negating BRDY# until it is ready to continue the data
t ra n sfe r. BR DY # is a lso u se d t o in d ica t e t h e com p le t ion of
special bus cycles.
Sampled
BRDY# is sampled every clock edge within a bus cycle starting
with the clock edge after the clock edge that negates ADS #.
BRDY # is ignored while the bus is idle. The processor samples
t h e followin g in p u t s on t h e clock e d ge on wh ich BR DY # is
sa m p le d a sse r t e d : D[63:0], DP [7:0], a n d KEN # d u rin g re a d
cycle s, E WBE # d u r in g wr it e cycle s (if n ot m a ske d off), a n d
WB/WT # d u r in g re a d a n d wr it e cycle s. If NA # is sa m p le d
asserted prior to BRDY#, then KEN# and WB/WT# are sampled
on the clock edge on which NA# is sampled asserted.
The number of times the processor expects to sample BRDY #
asserted depends on the type of bus cycle, as follows:
■ One time for a single-transfer cycle, a special bus cycle, or
each of two cycles in an interrupt acknowledge sequence
■ Four times for a burst cycle (once for each data transfer)
BR DY # ca n b e h e ld a sse r t e d for fou r con se cu t ive clock s
throughout the four transfers of the burst, or it can be negated to
insert wait states.
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4.13
BRDYC# (Burst Ready Copy)
Input, Internal Pullup
Summary
BR DYC # h a s t h e id e n t ica l fu n ct ion as BR DY #. In t h e eve n t
BRDY # becom es t oo heavily loaded due to a large fanout or
loading in a system, BRDYC# can be used to reduce this loading,
which improves timing.
Sampled
4.14
BRDYC# is sampled every clock edge within a bus cycle starting
with the clock edge after the clock edge that negates ADS#.
BREQ (Bus Request)
Output
Summary
BREQ is asserted by the processor to request the bus in order to
complete an internally pending bus cycle. The system logic can
u se BR E Q t o a r b it ra t e a m on g t h e b u s p a r t icip a n t s. If t h e
p roce ssor d oe s not own t h e bus, BR E Q is a sse rt e d u nt il t he
processor gains access to the bus in order to begin the pending
cycle or until the processor no longer needs to run the pending
cycle. If the processor currently owns the bus, BREQ is asserted
with ADS #. The processor asserts BREQ for each assertion of
ADS# but does not necessarily assert ADS# for each assertion of
BREQ.
Driven
BREQ is assert ed off t he sam e clock e dge on which ADS # is
a sse r t e d . BR E Q ca n a lso b e a sse r t e d off a ny clock e d ge ,
independent of the assertion of ADS #. BREQ can be negated
one clock edge after it is asserted.
The processor always drives BREQ except in the Tri-State Test
mode.
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4.15
CACHE# (Cacheable Access)
Output
Summary
For reads, CACHE # is asserted to indicate the cacheability of
t h e cu r ren t b u s cycle . In a dd it ion , if t h e p roce ssor sam p le s
KEN# asserted, which indicates the driven address is cacheable,
the cycle is a 32-byte burst read cycle. For write cycles, CACHE #
is a sse r t e d t o in d ica t e t h e cu r re n t b u s cycle is a m od ifie d
cache-lin e writeback. KEN # is ignored du ring writebacks. If
CACHE # is not asserted, or if KEN# is sampled negated during a
r e a d cycle , t h e cycle is n ot ca ch e a b le a n d d e fa u lt s t o a
single-transfer cycle.
Driven and Floated
CACHE # is driven off the same clock edge as ADS# and remains
in the same state until the clock edge on which NA# or the last
expected BRDY# of the cycle is sampled asserted.
CACHE # is floated off the clock edge that BOFF # is sampled
asserted and off the clock edge that the processor asserts HLDA
in recognition of HOLD.
4.16
CLK (Clock)
Input
Summary
Th e CLK signal is the bus clock for the proce ssor and is the
reference for all signal timings under normal operation (except
for TDI, TDO, TMS, and TRST#). BF[2:0] determine the internal
frequency multiplier applied to CLK to obtain the processor’s
core operating frequency. See “BF[2:0] (Bus Frequency)” on
page 94 for a list of the processor-to-bus clock ratios.
Sampled
The CLK signal must be stable a minimum of 1.0 ms prior to the
n e ga t ion of R E SE T t o e n su re t h e p rop e r op e ra t ion of t h e
processor. See “CLK Switching Characteristics” on page 279 for
details regarding the CLK specifications.
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4.17
D/C# (Data/Code)
Output
Summary
The processor drives D/C# during a memory bus cycle to indicate
whether it is addressing data or executable code. D/C # is also
u s e d t o d e f i n e o t h e r b u s cy c l e s , i n c l u d i n g i n t e r r u p t
acknowledge and special cycles. See Table 24 on page 129 for
more details.
Driven and Floated
D/C # is driven off the same clock edge as ADS# and remains in
the same state until the clock edge on which NA # or the last
expected BRDY# of the cycle is sampled asserted. D/C# is driven
d u r in g m e m ory cycle s, I/O cycle s, sp e cia l b u s cycle s, a n d
interrupt acknowledge cycles.
D/C # is floa t e d off t h e clock e d ge t h a t BOF F # is sa m p le d
asserted and off the clock edge that the processor asserts HLDA
in recognition of HOLD.
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4.18
D[63:0] (Data Bus)
Bidirectional
Summary
D[63:0] represent the processor’s 64-bit data bus. Each of the
eight bytes of data that comprise this bus is qualified as valid by
its corresponding byte enable. See “BE[7:0]# (Byte Enables)” on
page 93.
Driven, Sampled, and
Floated
As Outputs: For single-transfer write cycles, the processor drives
D[63:0] with valid data one clock edge after the clock edge on
which ADS # is asserted and D[63:0] remain in the same state
until the clock edge on which BRDY# is sampled asserted. If the
cycle is a writeback—in which case four, 8-byte transfers occur —
D[63:0] are driven one clock edge after the clock edge on which
ADS# is asserted and are subsequently changed off the clock
e d ge on wh ich e a ch BR DY# a sse r t ion of t h e b u rst cycle is
sampled.
If the assertion of ADS# represents a pipelined write cycle that
follows a read cycle, the processor does not drive D[63:0] until it
is certain that contention on the data bus will not occur. In this
case, D[63:0] are driven the clock edge after the last expected
BRDY# of the previous cycle is sampled asserted.
As Inputs: During read cycles, the processor samples D[63:0] on
the clock edge on which BRDY# is sampled asserted.
The processor always floats D[63:0] except when they are being
driven during a write cycle as described above. In addition,
D[63:0] are floated off the clock edge that BOFF # is sampled
a sse rt e d a n d off t h e clock e d ge t h a t t h e p roce ssor a sse r t s
HLDA in recognition of HOLD.
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4.19
DP[7:0] (Data Parity)
Bidirectional
Summary
DP [7:0] are even p a r it y b it s for e ach va lid byt e of d a ta —a s
defined by BE[7:0]#—driven and sampled on the D[63:0] data
bus. Even parity means that the total number of 1 bits within
each byte of data and its respective data parity bit is an even
number. DP[7:0] are driven by the processor during write cycles
a n d sa m p le d b y t h e p r oce ssor d u r in g re a d cycle s. If t h e
processor detects bad parity on any valid byte of data during a
read cycle, PCHK# is asserted for one clock beginning the clock
edge after BRDY# is sampled asserted. The processor does not
t ake a n int er nal except ion as t he result of de t ect ing a da ta
parity check, and system logic must respond appropriately to
the assertion of this signal.
The eight data parity bits correspond to the eight bytes of the
data bus as follows:
■ DP7: D[63:56]
■ DP6: D[55:48]
■ DP5: D[47:40]
■ DP4: D[39:32]
■ DP3: D[31:24]
■ DP2: D[23:16]
■ DP1: D[15:8]
■ DP0: D[7:0]
For systems that do not support data parity, DP[7:0] should be
connected to V through pullup resistors.
CC3
Driven, Sampled, and
Floated
As Outputs: For single-transfer write cycles, the processor drives
DP[7:0] with valid parity one clock edge after the clock edge on
which ADS# is asserted and DP[7:0] remain in the same state
until the clock edge on which BRDY# is sampled asserted. If the
cycle is a writeback, DP[7:0] are driven one clock edge after the
clock edge on which ADS# is asserted and are subse quent ly
changed off the clock edge on which each BRDY# assertion of
the burst cycle is sampled.
As Inputs: During read cycles, the processor samples DP[7:0] on
the clock edge BRDY# is sampled asserted.
The processor always floats DP[7:0] except when they are being
driven during a write cycle as described above. In addition,
DP[7:0] are floated off the clock edge that BOFF # is sampled
a sse rt e d a n d off t h e clock e d ge t h a t t h e p roce ssor a sse r t s
HLDA in recognition of HOLD.
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4.20
EADS# (External Address Strobe)
Input
Summary
System logic asserts EADS # during a cache inquire cycle to
indicate that the address bus contains a valid address. EADS#
can only be driven after the system logic has taken control of the
a dd re ss b u s by a sse r t in g AH OLD or BOF F # or by re ce iving
HLDA. The processor responds to the sampling of EADS # and
the address bus by driving HIT#, which indicates if the inquired
cache line exists in the processor’s caches, and HITM #, which
indicates if it is in the modified state.
Sampled
If AHOLD or BOFF # is asserted by the system logic in order to
execute a cache inquire cycle, the processor begins sampling
E ADS # t wo clock ed ge s aft er AH OLD or BOF F # is sa m p le d
asserted. If the system logic asserts HOLD in order to execute a
cache inquire cycle, the processor begins sampling EADS# two
clock e d ge s a ft e r t h e clock e d ge H LDA is a sse r t e d by t h e
processor.
EADS# is ignored during the following conditions:
■ One clock edge after the clock edge on which EADS# is
sampled asserted
■ Two clock edges after the clock edge on which ADS# is
asserted
■ When the processor is driving the address bus
■ When the processor asserts HITM#
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4.21
EWBE# (External Write Buffer Empty)
Input
Summary
The system logic can negate EWBE # to the processor to indicate
that its external write buffers are full and that additional data
cannot be stored at this time. This causes the processor to delay
the following activities until EWBE # is sampled asserted:
■ The commitment of write hit cycles to cache lines in the
modified state or exclusive state in the processor’s caches
■ The decode and execution of an instruction that follows a
currently-executing serializing instruction
■ The assertion or negation of SMIACT#
■ The entering of the Halt state and the Stop Grant state
Negating EWBE # does not prevent the completion of any type of
cycle that is currently in progress.
Sampled
The processor samples EWBE # on each clock edge that BRDY#
is sa mpled assert ed during all m emory write cycles (except
writeback cycles), I/O write cycles, and special bus cycles.
If EWBE # is sampled negated, it is sampled on every clock edge
until it is asserted, and then it is ignored until BRDY# is sampled
asserted in the next write cycle or special cycle.
If EFER[3] is set to 1, then EWBE# is ignored by the processor.
For more information on the EFER settings and EWBE#, see
“EWBE Control” on page 217.
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4.22
FERR# (Floating-Point Error)
Output
Summary
Th e a sse r t ion of F E R R # in d ica t e s t h e occu r r e n ce of a n
unmasked floating-point exception resulting from the execution
of a floating-point instruction. This signal is provided to allow
the system logic to handle this exception in a manner consistent
w i t h I BM -c o m p a t i b l e P C /AT s y s t e m s . S e e “ H a n d l i n g
F loa t in g-Poin t E xce p t ion s” on p a ge 223 for a syst e m logic
implementation that supports floating-point exceptions.
The state of the numeric error (NE) bit in CR0 does not affect
the FERR # signal.
Th e p roce ssor is d e sign e d so t h a t F E R R # d oe s n ot glit ch ,
enabling the signal to be used as a clocking source for system
logic.
Driven
The processor asserts FERR # on the instruction boundary of the
n ext floa t in g-p oin t in st r u ct ion , MMX in st r u ct ion , 3DNow!
in st r u ct ion , or WAIT in st r u ct ion t h a t occu rs followin g t h e
f l o a t i n g -p o i n t i n s t r u c t i o n t h a t c a u s e d t h e u n m a s k e d
floating-point exception—that is, FERR # is not asserted at the
time the exception occurs. The IGNNE # signal does not affect
the assertion of FERR #.
FERR # is negated during the following conditions:
■ Following the successful execution of the floating-point
instructions FCLEX, FINIT, FSAVE, and FSTENV
■ Under certain circumstances, following the successful
execution of the floating-point instructions FLDCW,
FLDENV, and FRSTOR, which load the floating-point status
word or the floating-point control word
■ Following the falling transition of RESET
FERR # is always driven except in the Tri-State Test mode.
See “IGNNE# (Ignore Numeric Exception)” on page 108 for
more details on floating-point exceptions.
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4.23
FLUSH# (Cache Flush)
Input
Summary
In response to sampling FLUSH # asserted, the processor writes
back any cache lines in the L1 data cache or L2 cache that are in
the modified state, invalidates all lines in the L1 and L2 caches,
a n d t h e n e xe cu t e s a flu sh a ck n owle d ge sp e cia l cycle . Se e
Table 24 on page 129 for the bus definition of special cycles.
In a dd it ion , FLUSH # is sampled when RESET is ne gate d to
determine if the processor enters the Tri-State Test mode. If
F LU SH # is 0 d u r in g t h e fa llin g t ra n sit ion of R E SE T, t h e
processor enters the Tri-State Test mode instead of performing
the normal RESET functions.
Sampled
F LU SH # is sa m p le d a n d la t ch e d a s a fa llin g e d ge -se n sit ive
sign a l. Du r in g n or m a l op e ra t ion (n ot R E SE T), F LU SH # is
sampled on every clock edge but is not recognized until the next
instruction boundary. If FLUSH # is asserted synchronously, it
ca n b e a sse r t e d for a m in imu m of on e clock . If F LU SH # is
a sse r t e d a syn ch ron ou sly, it m u st h ave b e e n n e ga t e d for a
minimum of two clocks, followed by an assertion of a minimum
of two clocks.
FLUSH # is also sampled during the falling transition of RESET.
If RESET and FLUSH # are driven synchronously, FLUSH # is
sam p led on t he clock edge prior to t he clock e dge on which
RESET is sampled negated. If RESET is driven asynchronously,
the minimum setup and hold time for FLUSH #, relative to the
negation of RESET, is two clocks.
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4.24
HIT# (Inquire Cycle Hit)
Output
Summary
The processor asserts HIT# during an inquire cycle to indicate
that the cache line is valid within the processor’s L1 and/or L2
caches (also known as a cache hit). The cache line can be in the
modified, exclusive, or shared state.
Driven
HIT# is always driven —except in the Tri-State Test mode —and
only changes state the clock edge after the clock edge on which
EADS # is sampled asserted. It is driven in the same state until
the next inquire cycle.
4.25
HITM# (Inquire Cycle Hit To Modified Line)
Output
Summary
The processor asserts HITM# during an inquire cycle to indicate
that the cache line exists in the processor’s L1 data cache or L2
cache in the modified state. The processor performs a writeback
cycle as a result of this cache hit. If an inquire cycle hits a cache
line that is currently being written back, the processor asserts
H ITM # b u t d oe s n ot exe cu t e a n ot h e r wr it eb a ck cycle . Th e
system logic must not expect the processor to assert ADS# each
time HITM# is asserted.
Driven
HITM # is always driven —except in the Tri-State Test mode —
and, in particular, is driven to represent the result of an inquire
cycle the clock edge after the clock edge on which EADS # is
sa m p le d a sse r t e d . If H ITM # is n e ga t e d in re sp on se t o t h e
inquire address, it remains negated until the next inquire cycle.
If H ITM # is a sse r t e d in re sp on se t o t h e in q u ire a dd re ss, it
remains asserted throughout the writeback cycle and is negated
one clock edge after the last BRDY# of the writeback is sampled
asserted.
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4.26
HLDA (Hold Acknowledge)
Output
Summary
When HOLD is sampled asserted, the processor completes the
current bus cycles, floats the processor bus, and asserts HLDA
in an acknowledgment that these events have been completed.
The processor does not assert HLDA until the completion of a
locked sequence of cycles. While HLDA is asserted, another bus
master can drive cycles on the bus, including inquire cycles to
the processor. The following signals are floated when HLDA is
a sse r t e d : A[31:3], ADS #, ADSC #, AP, BE [7:0]#, CACH E #,
D[63:0], D/C #, DP[7:0], LOCK #, M/IO #, PCD, PWT, SCYC, and
W/R #.
The processor is designed so that HLDA does not glitch.
Driven
HLDA is always driven except in the Tri-State Test mode. If a
processor cycle is in progress while HOLD is sampled asserted,
HLDA is asserted one clock edge after the last BRDY # of the
cycle is sampled asserted. If the bus is idle, HLDA is asserted
on e clock e d ge a ft e r H OLD is sa m p le d a sse r t e d . H LDA is
negated one clock edge after the clock edge on which HOLD is
sampled negated.
The assertion of HLDA is independent of the sampled state of
BOFF #.
Th e p roce ssor floa t s t h e b u s eve ry clock in wh ich H LDA is
asserted.
4.27
HOLD (Bus Hold Request)
Input
Summary
Th e syst e m logic ca n a sse r t H OLD t o ga in con t r ol of t h e
processor’s bus. When HOLD is sampled asserted, the processor
completes the current bus cycles, floats the processor bus, and
asserts HLDA in an acknowledgment that these events have
been completed.
Sampled
The processor samples HOLD on every clock edge. If a processor
cycle is in progress while HOLD is sampled asserted, HLDA is
asserted one clock edge after t he last BRDY # of the cycle is
sampled asserted. If the bus is idle, HLDA is asserted one clock
e d ge a ft e r H OLD is sam ple d a sse r t e d . HOLD is re cogn ize d
while INIT and RESET are sampled asserted.
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4.28
IGNNE# (Ignore Numeric Exception)
Input
Summary
IGNNE #, in conjunction with the numeric error (NE) bit in CR0,
is used by the system logic to control the effect of an unmasked
floating-point exception on a previous floating-point instruction
d u r in g t h e exe cu t ion of a floa t in g-p oin t in st r u ct ion , MMX
in st ru ct ion , 3DNow! instr uction, or t h e WAIT inst ru ct ion—
hereafter referred to as the target instruction.
If a n unma sked floa ting-point exce ption is pe nding a nd the
t a rge t in st r u ct ion is con sid e re d e r ror -se n sit ive , t h e n t h e
relationship between NE and IGNNE # is as follows:
■ If NE = 0, then:
•
If IGNNE # is sampled asserted, the processor ignores the
floating-point exception and continues with the
execution of the target instruction.
•
If IGNNE # is sampled negated, the processor waits until
it samples IGNNE #, INTR, SMI#, NMI, or INIT asserted.
If IGNNE # is sampled asserted while waiting, the
processor ignores the floating-point exception and
continues with the execution of the target instruction.
If INTR, SMI#, NMI, or INIT is sampled asserted while
waiting, the processor handles its assertion
appropriately.
■ If NE = 1, the processor invokes the INT 10h exception
handler.
If a n unma sked floa ting-point exce ption is pe nding a nd the
t a rge t in st r u ct ion is con sid e re d e r ror -inse nsit ive , t h e n t he
processor ignores the floating-point exception and continues
with the execution of the target instruction.
FERR # is not affected by the state of the NE bit or IGNNE #.
FERR # is always asserted at the instruction boundary of the
target instruction that follows the floating-point instruction that
caused the unmasked floating-point exception.
Th is sign a l is p rovid e d t o a llow t h e syst e m logic t o h a n d le
exceptions in a manner consistent with IBM-compatible PC/AT
systems.
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Sampled
Th e processor samples IGNNE # as a level-sensitive input on
every clock edge. The system logic can drive the signal either
s y n c h r o n o u s l y o r a s y n c h r o n o u s l y. I f i t i s a s s e r t e d
asynchronously, it must be asserted for a minimum pulse width
of two clocks.
4.29
INIT (Initialization)
Input
Summary
Th e a sse r t ion of INIT ca u se s t h e p r oce ssor t o e m p t y it s
pipelines, to initialize most of its internal state, and to branch to
address FFFF_FFF0h—the same instruction execution starting
point used after RESET. Unlike RESET, the processor preserves
the contents of its caches, the floating-point state, the MMX
state, Model-Specific Registers, the CD and NW bits of the CR0
register, and other specific internal resources.
INIT can be used as an accelerator for 80286 code that requires a
reset to exit from Protected mode back to Real mode.
Sampled
INIT is sampled and latched as a rising edge-sensitive signal.
INIT is sampled on every clock edge but is not recognized until
the next instruction boundary. During an I/O write cycle, it must
be sampled asserted a minimum of three clock edges before
BR DY # is sa m p le d a sse r t e d if it is t o b e re cogn ize d on t h e
boundary between the I/O write instruction and the following
instruction.
If INIT is a sse r t e d syn ch ron ou sly, it ca n b e a sse r t e d for a
minimum of one clock. If it is asserted asynchronously, it must
have been negated for a minimum of two clocks, followed by an
assertion of a minimum of two clocks.
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4.30
INTR (Maskable Interrupt)
Input
Summary
INTR is the system’s maskable interrupt input to the processor.
When the processor samples and recognizes INTR asserted, the
processor executes a pair of interrupt acknowledge bus cycles
and then jumps to the interrupt service routine specified by the
in t e r r u p t nu m b e r t h a t wa s re t u r n e d d u r in g t h e in t e r r u p t
acknowledge sequence. The processor only recognizes INTR if
the interrupt flag (IF) in the EFLAGS register equals 1.
Sampled
The processor samples INTR as a level-sensitive input on every
clock edge, but the interrupt request is not recognized until the
next in struct ion boundary. The syst em logic can drive INTR
e it h e r syn ch ron ou sly or a syn ch r on ou sly. If it is a sse r t e d
asynchronously, it must be asserted for a minimum pulse width
of t wo clock s. In ord e r t o b e recogn ize d , INTR must rem a in
asserted until an interrupt acknowledge sequence is complete.
4.31
INV (Invalidation Request)
Input
Summary
During an inquire cycle, the state of INV determines whether an
addressed cache line that is found in the processor’s L1 and/or
L2 caches transitions to the invalid state or the shared state.
If INV is sampled asserted during an inquire cycle, the processor
t ra n sit ion s t h e ca ch e lin e (if fou n d ) t o t h e in va lid st a t e ,
re ga rd le ss of it s p reviou s st a t e . If INV is sa m p le d n e ga t e d
during an inquire cycle, the processor transitions the cache line
(if found) to the shared state. In either case, if the cache line is
fou n d in t h e m od ifie d st a t e , t h e p roce ssor wr it e s it b a ck t o
memory before changing its state.
Sampled
INV is sampled on the clock edge on which EADS # is sampled
asserted.
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4.32
KEN# (Cache Enable)
Input
Summary
If KE N # is sa m p le d a sse r t e d , it in d ica t e s t h a t t h e a d d re ss
presented by the processor is cacheable. If KEN # is sampled
asserted and the processor intends to perform a cache-line fill
(signified by the assertion of CACHE #), the processor executes a
32-byte burst read cycle and expects to sample BRDY# asserted
a total of four times. If KEN# is sampled negated during a read
cycle, a single-transfer cycle is executed and the processor does
not cach e the dat a. For writ e cycles, CACHE # is assert ed to
in d ica t e t h e cu r r e n t b u s cycle is a m od ifie d ca ch e -lin e
writeback. KEN# is ignored during writebacks.
If PCD is asserted during a bus cycle, the processor does not
cache any data read during that cycle, regardless of the state of
KEN #. See “PCD (Page Cache Disable)” on page 115 for more
details.
If the processor has sampled the state of KEN# during a cycle,
and that cycle is aborted due to the sampling of BOFF # asserted,
the system logic must ensure that KEN# is sampled in the same
state when the processor restarts the aborted cycle.
Sampled
KEN# is sampled on the clock edge on which the first BRDY# or
NA # of a read cycle is sampled asserted. If the read cycle is a
b u rst , KE N # is ign ore d d u r in g t h e la st t h re e a sse r t ion s of
BR DY #. KE N # is sa m p le d d u r in g r e a d cycle s on ly wh e n
CACHE # is asserted.
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4.33
LOCK# (Bus Lock)
Output
Summary
The processor asserts LOCK# during a sequence of bus cycles to
ensure that the cycles are completed without allowing other bus
masters to intervene. Locked operations consist of two to five
bus cycles. LOCK# is asserted during the following operations:
■ An interrupt acknowledge sequence
■ Descriptor Table accesses
■ Page Directory and Page Table accesses
■ XCHG instruction
■ An instruction with an allowable LOCK prefix
In order to ensure that locked operations appear on the bus and
are visible to the entire system, any data operands addressed
during a locked cycle that reside in the processor’s caches are
flushed and invalidate d from t he caches prior t o t he locked
operation. If the cache line is in the modified state, it is written
back and invalidated prior to the locked operation. Likewise,
any data read during a locked operation is not cached.
The processor is designed so that LOCK# does not glitch.
Driven and Floated
During a locked cycle, LOCK# is asserted off the same clock
edge on which ADS# is asserted and remains asserted until the
la st BR DY# of t h e la st b u s cycle is sa m p le d a sse r t e d . Th e
p roce ssor n e ga t e s LOCK# for a t le a st on e clock b e t we e n
consecutive sequences of locked operations to allow the system
logic to arbitrate for the bus.
LOCK# is floa te d off t he clock e dge t hat BOFF # is sa m ple d
asserted and off the clock edge that the processor asserts HLDA
in response to HOLD. When LOCK# is floated d ue to BOFF#
sampled asserted, the system logic is responsible for preserving
the lock condition while LOCK# is in the high-impedance state.
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4.34
M/IO# (Memory or I/O)
Output
Summary
Th e p roce ssor d r ive s M/IO# d u r in g a b u s cycle t o in d ica t e
whether it is addressing the memory or I/O space. If M/IO# = 1,
the processor is addressing memory or a memory-mapped I/O
port as the result of an instruction fetch or an instruction that
loads or stores data. If M/IO# = 0, the processor is addressing an
I/O port during the execution of an I/O instruction. In addition,
M/IO# is used to define other bus cycles, including interrupt
acknowledge and special cycles. See Table 24 on page 129 for
more details.
Driven and Floated
M/IO# is driven off the same clock edge as ADS# and remains in
the same state until the clock edge on which NA# or the last
exp ecte d BR DY# of th e cycle is sam p le d a sser t e d . M/IO# is
driven during memory cycles, I/O cycles, special bus cycles, and
interrupt acknowledge cycles.
M/IO# is floa t e d off t h e clock e d ge t h a t BOF F # is sa m ple d
asserted and off the clock edge that the processor asserts HLDA
in response to HOLD.
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4.35
NA# (Next Address)
Input
Summary
System logic asserts NA# to indicate to the processor that it is
ready to accept another bus cycle pipelined into the previous
bus cycle. ADS#, along with address and status signals, can be
a sse r t e d a s e a r ly a s on e clock e d ge a ft e r NA# is sa m p le d
a sse r t e d if t h e p roce ssor is p re p a re d t o st a r t a n ew cycle .
Because the processor allows a maximum of two cycles to be in
progress at a time, the assertion of NA# is sampled while two
cycle s a re in p rogre ss b u t ADS# is n ot a sse r t e d u n t il t h e
completion of the first cycle.
Sampled
NA# is sampled every clock edge during bus cycles, starting one
clock edge after the clock edge that negates ADS#, until the last
expected BRDY# of the last executed cycle is sampled asserted
(with the exception of the clock edge after the clock edge that
n e ga t e s t h e ADS# for a second pe nd ing cycle ). Be ca use the
processor latches NA# whe n sa mpled, the syste m logic only
needs to assert NA# for one clock.
4.36
NMI (Non-Maskable Interrupt)
Input
Summary
Wh e n NMI is sa m p le d a sse r t e d , t h e p rocessor j u m p s t o t h e
interr up t service rout ine de fined by interrupt number 02h.
Unlike the INTR signal, software cannot mask the effect of NMI
if it is sa m p le d a sse r t e d by t h e p roce ssor. H oweve r, NMI is
temporarily masked upon entering System Management Mode
(SMM). In a d d it ion , a n in t e r r u p t a ck n owle d ge cycle is n ot
executed because the interrupt number is predefined.
If NMI is sampled asserted while the processor is executing the
interrupt service routine for a previous NMI, the subsequent
NMI remains pending until the completion of the execution of
the IRET instruction at the end of the interrupt service routine.
Sampled
NMI is sampled and latched as a rising edge-sensitive signal.
During normal operation, NMI is sampled on every clock edge
but is not recognized until the next instruction boundary. If it is
asserted synchronously, it can be asserted for a minimum of one
clock. If it is asserted asynchronously, it must have been negated
for a m in imu m of t wo clock s, followe d by a n a sse r t ion of a
minimum of two clocks.
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4.37
PCD (Page Cache Disable)
Output
Summary
The processor drives PCD to indicate the operating system’s
sp e cificat ion of ca che ab ilit y for t h e p a ge b e in g a dd resse d .
System logic can use PCD to control external caching. If PCD is
asserted, the addressed page is not cached. If PCD is negated,
the cacheability of the addressed page depends upon the state
of CACHE# and KEN#.
The state of PCD depends upon the processor’s operating mode
and the state of certain bits in its control registers and TLB as
follows:
■ In Real mode, or in Protected and Virtual-8086 modes while
paging is disabled (PG bit in CR0 set to 0):
PCD output = CD bit in CR0
■ In Protected and Virtual-8086 modes while caching is
enabled (CD bit in CR0 set to 0) and paging is enabled (PG
bit in CR0 set to 1):
•
•
•
For accesses to I/O space, page directory entries, and
other non-paged accesses:
PCD output = PCD bit in CR3
For accesses to 4-Kbyte page table entries or 4-Mbyte
pages:
PCD output = PCD bit in page directory entry
For accesses to 4-Kbyte pages:
PCD output = PCD bit in page table entry
Driven and Floated
PCD is driven off the same clock edge as ADS# and remains in
the same state until the clock edge on which NA# or the last
expected BRDY# of the cycle is sampled asserted.
P CD is floa t e d off t h e clock e d ge t h a t BOF F # is sa m p le d
asserted and off the clock edge that the processor asserts HLDA
in response to HOLD.
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4.38
PCHK# (Parity Check)
Output
Summary
The processor asserts PCHK# during read cycles if it detects an
even parity error on one or more valid bytes of D[63:0] during a
read cycle. (Even parity means that the total number of 1 bits
within each byte of data and its respective data parity bit is
even.) The processor checks data parity for the data bytes that
are valid, as defined by BE[7:0]#, the byte enables.
PCHK# is always driven but is only asserted for memory and I/O
r e a d b u s cy c l e s a n d t h e s e c o n d cy c l e o f a n i n t e r r u p t
acknowledge sequence. PCHK# is not driven during any type of
write cycles or special bus cycles. The processor does not take an
internal exception as the result of detecting a data parity error,
and system logic must respond appropriately to the assertion of
this signal.
Th e p roce ssor is d e sign e d so t h a t P CH K# d oe s n ot glit ch ,
enabling the signal to be used as a clocking source for system
logic.
Driven
PCHK# is always driven except in the Tri-State Test mode. For
each BRDY# returned to the processor during a read cycle with a
parity error detected on the data bus, PCHK# is asserted for one
clock, one clock edge after BRDY# is sampled asserted.
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4.39
PWT (Page Writethrough)
Output
Summary
The processor drives PWT to indicate the operating system’s
specification of the writeback state or writethrough state for the
page being addressed. PWT, together with WB/WT#, specifies
the data cache-line state during cacheable read misses and write
h it s t o sh a r e d ca ch e lin e s. Se e “ WB/WT# (Wr it e b a ck or
Writethrough)” on page 125 for more details.
The state of PWT depends upon the processor’s operating mode
and the state of certain bits in its control registers and TLB as
follows:
■ In Real mode, or in Protected and Virtual-8086 modes while
paging is disabled (PG bit in CR0 set to 0):
PWT output = 0 (writeback state)
■ In Protected and Virtual-8086 modes while paging is
enabled (PG bit in CR0 set to 1):
•
•
•
For accesses to I/O space, page directory entries, and
other non-paged accesses:
PWT output = PWT bit in CR3
For accesses to 4-Kbyte page table entries or 4-Mbyte
pages:
PWT output = PWT bit in page directory entry
For accesses to 4-Kbyte pages:
PWT output = PWT bit in page table entry
Driven and Floated
PWT is driven off the same clock edge as ADS# and remains in
the same state until the clock edge on which NA# or the last
expected BRDY# of the cycle is sampled asserted.
P WT is floa t e d off t h e clock e d ge t h a t BOF F # is sa m p le d
asserted and off the clock edge that the processor asserts HLDA
in response to HOLD.
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4.40
RESET (Reset)
Input
Summary
When the processor samples RESET asserted, it immediately
flushes and initializes all internal resources and its internal
state including its pipelines and caches, the floating-point state,
the MMX state, the 3DNow! state, and all registers, and then the
processor jumps to address FFFF_FFF0h to start instruction
execution.
The FLUSH# signal is sampled during the falling transition of
RESET to invoke the Tri-State Test mode.
Sampled
RESET is sampled as a level-sensitive input on every clock edge.
Syst e m logic ca n d r ive t h e sign a l e it h e r syn ch ron ou sly or
asynchronously.
During the initial power-on reset of the processor, RESET must
remain asserted for a minimum of 1.0 ms after CLK and V
reach specification before it is negated.
CC
Du r in g a wa r m re se t , wh ile CLK a n d V
a re wit h in t h e ir
CC
specification, RESET must remain asserted for a minimum of 15
clocks prior to its negation.
4.41
RSVD (Reserved)
Summary
Reserved signals are a special class of pins that can be treated in
one of the following ways:
■ As no-connect (NC) pins, in which case these pins are left
unconnected
■ As pins connected to the system logic as defined by the
industry-standard Super7 and Socket 7 interface
■ Any combination of NC and Socket 7 pins
In any case, if the RSVD pins are treated accordingly, the normal
operation of the Mobile AMD-K6-2+ processor is not adversely
affected in any manner.
See “Pin Designations” on page 299 for a list of the locations of
the RSVD pins.
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4.42
SCYC (Split Cycle)
Output
Summary
The processor asserts SCYC during misaligned, locked transfers
on the D[63:0] data bus. The processor generates additional bus
cycles to complete the transfer of misaligned data.
For purposes of bus cycles, the term aligned means:
■ Any 1-byte transfers
■ 2-byte and 4-byte transfers that lie within 4-byte address
boundaries
■ 8-byte transfers that lie within 8-byte address boundaries
Driven and Floated
SCYC is asserted off the same clock edge as ADS#, and negated
off the clock edge on which NA# or the last expected BRDY# of
the entire locked sequence is sampled asserted. SCYC is only
valid during locked memory cycles.
SCYC is floa t e d off t h e clock e d ge t h a t BOF F # is sa m p le d
asserted and off the clock edge that the processor asserts HLDA
in response to HOLD.
4.43
SMI# (System Management Interrupt)
Input, Internal Pullup
Summary
Th e assertion of SMI# causes t he processor to enter System
Ma n a ge m e n t Mod e (SMM). U p on r e cogn izin g SMI#, t h e
processor performs the following actions, in the order shown:
1. Flushes its instruction pipelines
2. Completes all pending and in-progress bus cycle s
3. Acknowledges the interrupt by asserting SMIACT# after
sampling EWBE# asserted (if EWBE# is masked off, then
SMIACT# is not affected by EWBE#)
4. Saves the internal processor state in SMM memory
5. Disables interrupts by clearing the interrupt flag (IF) in
EFLAGS and disables NMI interrupts
6. Jumps to the entry point of the SMM service routine at the
SMM base physical address which defaults to 0003_8000h in
SMM memory
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See “System Management Mode (SMM)” on page 227 for more
details regarding SMM.
Sampled
SMI# is sampled and latched as a falling edge-sensitive signal.
SMI# is sampled on every clock edge but is not recognized until
the next instruction boundary. If SMI# is to be recognized on the
in st r u ct ion b ou n d a ry a ssocia t e d wit h a BR DY#, it mu st b e
sampled asserted a minimum of three clock edges before the
BRDY# is sampled asserted. If it is asserted synchronously, it
can be asserted for a m inimum of one clock. If it is asserted
asynchronously, it must have been negated for a minimum of two
clocks followed by an assertion of a minimum of two clocks.
A second assertion of SMI# while in SMM is latched but is not
recognized until the SMM service routine is exited.
4.44
SMIACT# (System Management Interrupt Active)
Output
Summary
Th e proce ssor a cknowle dge s the a sse rtion of SMI# with the
assertion of SMIACT# to indicate that the processor has entered
System Management Mode (SMM). The system logic can use
SMIACT# t o e n a b le SMM m e m or y. Se e “ SMI# ( Sy st e m
Management Interrupt)” on page 119 for more details.
See “System Management Mode (SMM)” on page 227 for more
details regarding SMM.
Driven
The processor asserts SMIACT# after the last BRDY# of the last
pending bus cycle is sampled asserted (including all pending
write cycles) and after EWBE# is sampled asserted (if EWBE# is
m a sk e d off, t h e n SMIACT# is n ot a ffe ct e d b y E WBE #).
SMIACT# remains asserted until after the last BRDY# of the last
p e n d in g b u s cycle a ssocia t e d wit h exit in g SMM is sa m p le d
asserted.
SMIACT# remains asserted during any flush, internal snoop, or
writeback cycle due to an inquire cycle.
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4.45
STPCLK# (Stop Clock)
Input, Internal Pullup
Summary
The assertion of STPCLK# causes the processor to enter the
Stop Grant state, during which the processor’s internal clock is
st o p p e d . Fr om t h e S t op Gr a n t st a t e , t h e p r oce ss or ca n
subsequently transition to the Stop Clock state, in which the bus
clock CLK is st op p e d . U p on r e cogn izin g STP CLK#, t h e
processor performs the following actions, in the order shown:
1. Flushes its instruction pipelines
2. Completes all pending and in-progress bus cycle s
3. Acknowledges the STPCLK# assertion by executing a Stop
Grant special bus cycle (see Table 24 on page 129)
4. Stops its internal clock after BRDY# of the Stop Grant
special bus cycle is sampled asserted and after EWBE# is
sampled asserted (if EWBE# is masked off, then entry into
the Stop Grant state is not affected by EWBE#)
5. Enters the Stop Clock state if the system logic stops the bus
clock CLK (optional)
See “Clock Control” on page 263 for more details regarding
clock control.
Sampled
STPCLK# is sampled as a level-sensitive input on every clock
edge but is not recognized until the next instruction boundary.
Syst e m logic ca n d r ive t h e sign a l e it h e r syn ch ron ou sly or
a syn ch ron ou sly. If it is a sser t ed a syn chron ou sly, it must b e
asserted for a minimum pulse width of two clocks.
STP CLK# mu st re m a in a sse r t e d u n t il re cogn ize d , wh ich is
indicated by the completion of the Stop Grant special cycle.
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4.46
TCK (Test Clock)
Input, Internal Pullup
Summary
TCK is the clock for boundary-scan testing using the Test Access
Port (TAP). See “Boundary-Scan Test Access Port (TAP)” on
p a ge 241 for d e t a ils re ga rd in g t h e op e ra t ion of t h e TAP
controller.
Sampled
4.47
Th e p roce ssor a lways sa m ple s TCK, exce pt while TR ST# is
asserted.
TDI (Test Data Input)
Input, Internal Pullup
Summary
T D I i s t h e s e r i a l t e s t d a t a a n d i n s t r u c t i o n i n p u t fo r
bound ary-scan testing using the Test Access Port (TAP). See
“Boundary-Scan Test Access Port (TAP)” on page 241 for details
regarding the operation of the TAP controller.
Sampled
4.48
The processor samples TDI on every rising TCK edge but only
while in the Shift-IR and Shift-DR states.
TDO (Test Data Output)
Output
Summary
T D O i s t h e s e r i a l t e s t d a t a a n d in s t r u ct i o n o u t p u t fo r
bound ary-scan testing using the Test Access Port (TAP). See
“Boundary-Scan Test Access Port (TAP)” on page 241 for details
regarding the operation of the TAP controller.
Driven and Floated
The processor drives TDO on every falling TCK edge but only
while in the Shift-IR and Shift-DR states. TDO is floated at all
other times.
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4.49
TMS (Test Mode Select)
Input, Internal Pullup
Summary
TMS specifies the test function and sequence of state changes
for boundary-scan testing using the Test Access Port (TAP). See
“Boundary-Scan Test Access Port (TAP)” on page 241 for details
regarding the operation of the TAP controller.
Sampled
The processor samples TMS on every rising TCK edge. If TMS is
sa m p le d H igh for five or m ore con se cu t ive clock s, t he TAP
controller enters its Test-Logic-Reset state, regardless of the
cont roller st ate. This a ct ion is the sam e a s t hat achieved by
asserting TRST#.
4.50
TRST# (Test Reset)
Input, Internal Pullup
Summary
The assertion of TRST# initializes the Test Access Port (TAP) by
resetting its state machine to the Test-Logic-Reset state. See
“Boundary-Scan Test Access Port (TAP)” on page 241 for details
regarding the operation of the TAP controller.
Sampled
TRST# is a completely asynchronous input that does not require
a minimum setup and hold time relative to TCK. See Table 63 on
page 287 for the minimum pulse width requirement.
4.51
VCC2DET (VCC2 Detect)
Output
Summary
VCC2DET is internally tied to V (logic level 0) to indicate to
SS
the system logic that it must supply the specified dual-voltage
requirements to the V
and V
pins. The V
pins supply
CC2
CC3
CC2
volt a ge t o t h e p roce ssor core , in d e p e n d e n t of t h e volt a ge
supplied to the I/O buffers on the V pins. Upon sampling
CC3
VCC2DE T Low, syst e m logic sh ou ld sa m p le VCC2H /L# t o
identify core voltage requirements.
Driven
VCC2DET always equals 0 and is never floated —even during
the Tri-State Test mode.
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4.52
VCC2H/L# (VCC2 High/Low)
Output
Summary
VCC2H/L# is internally tied to V (logic level 0) to indicate to
SS
the system logic that it must supply the specified processor core
voltage to the V
pins. The V
pins supply voltage to the
CC2
CC2
processor core, independent of the voltage supplied to the I/O
b u ffe rs on t h e V p in s. U p on sam p lin g VCC2DE T Low t o
CC3
id e n t ify d u a l-volt a ge p roce ssor re q u ire m e n t s, syst e m logic
s h o u ld s a m p l e V C C 2 H /L # t o id e n t if y t h e c or e vol t a g e
requirements for 2.9 V and 3.2 V products (High) or 2.1V, 2.2V,
and 2.4V products (Low).
Driven
VCC2H/L# always equals 0 and is never floated for 2.1V, 2.2 V,
and 2.4 V products —even during the Tri-State Test mode. To
en sure proper operation for 2.9 V and 3.2 V products, system
logic t h a t sa m p le s VCC2H /L# sh ou ld d e sign a we a k p u llu p
resistor for this signal.
Table 18. Output Pin Float Conditions
Name
VCC2DET
VCC2H/L#
Note:
Floated At:
Always Driven
Always Driven
Note
*
*
*
All outputs except VCC2DET, VCC2H/L#, and TDO float
during the Tri-State Test mode.
4.53
VID[4:0] (Voltage Identification)
Output
Summary
VID[4:0] a re u se d t o d r ive t h e VID in p u t s of t h e DC/DC
regulator that generates the core voltage for the processor. The
processor VID[4:0] outputs default to 01010b when RESET is
sampled asserted.
Driven
VID[4:0] are in itialize d t o t h e d e fa u lt st at e a ft er R E SE T is
sampled asserted, the CPU input clock is running, and the core
and I/O voltages are applied. Thereafter, the VID [4:0] outputs
are always driven.
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4.54
W/R# (Write/Read)
Output
Summary
The processor drives W/R# to indicate whether it is performing a
write or a read cycle on the bus. In addition, W/R# is used to
define other bus cycles, including interrupt acknowledge and
special cycles. See Table 24 on page 129 for more details.
Driven and Floated
W/R# is driven off the same clock edge as ADS# and remains in
the same state until the clock edge on which NA# or the last
exp e ct e d BR DY# of t h e cycle is sa m p le d a sse r t e d. W/R # is
driven during memory cycles, I/O cycles, special bus cycles, and
interrupt acknowledge cycles.
W/R # is floa t e d off t h e clock e d ge t h a t BOF F # is sa m p le d
asserted and off the clock edge that the processor asserts HLDA
in response to HOLD.
4.55
WB/WT# (Writeback or Writethrough)
Input
Summary
WB/WT#, together with PWT, specifies the data cache-line state
during cacheable read misses and write hits to shared cache
lines.
If WB/WT# = 0 or PWT = 1 during a cacheable read miss or write
hit t o a shared cache line, the accessed line is cached in the
sh a re d st a t e . Th is is re fe r re d t o a s t h e wr it e t h rou gh st a t e
because all write cycles to this cache line are driven externally
on the bus.
If WB/WT# = 1 and PWT = 0 during a cacheable read miss or a
write hit to a shared cache line, the accessed line is cached in the
exclusive state. Subsequent write hits to the same line cause its
state to transition from exclusive to modified. This is referred to
as the writeback state because the L1 data cache and the L2
cache can contain modified cache lines that are subject to be
written back—referred to as a writeback cycle—as the result of
an inquire cycle, an internal snoop, a flush operation, or the
WBINVD instruction.
Sampled
WB/WT# is sampled on the clock edge that the first BRDY# or
NA# of a bus cycle is sampled asserted. If the cycle is a burst
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rea d, WB/WT# is ignored during the last three assertions of
BR DY # . W B/W T # i s s a m p l e d d u r i n g m e m o r y r e a d a n d
non-writeback write cycles and is ignored during all other types
of cycles.
Table 19. Input Pin Types
Name
A20M#
Type
Note
Name
IGNNE#
Type
Note
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Clock
1
Asynchronous
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Asynchronous
Asynchronous
Asynchronous
Asynchronous
Synchronous
1
2
1
AHOLD
BF[2:0]
BOFF#
BRDY#
BRDYC#
CLK
INIT
4
INTR
INV
KEN#
NA#
NMI
2
5, 6
2
EADS#
EWBE#
FLUSH#
HOLD
Notes:
Synchronous
Synchronous
Asynchronous
Synchronous
RESET
SMI#
7
2, 3
STPCLK#
WB/WT#
1
1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and
hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.
2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and
hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must
remain asserted at least two clocks.
3. FLUSH# is also sampled during the falling transition of RESET and can be asserted synchronously or asynchronously. To be sam-
pled on a specific clock edge, setup and hold times must be met relative to the clock edge before the clock edge on which RESET
is sampled negated. If asserted asynchronously, FLUSH# must meet a minimum setup and hold time of two clocks relative to the
negation of RESET.
4. BF[2:0] are sampled during the falling transition of RESET. They must meet a minimum setup time of 1.0 ms and a minimum hold
time of two clocks relative to the negation of RESET.
5. During the initial power-on reset of the processor, RESET must remain asserted for a minimum of 1.0 ms after CLK and V reach
CC
specification before it is negated.
6. During a warm reset, while CLK and V are within their specification, RESET must remain asserted for a minimum of 15 clocks
CC
prior to its negation.
7. On the Mobile AMD-K6-2+ processor, if EFER[3] is set to 1, then EWBE# is ignored by the processor.
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Table 20. Output Pin Float Conditions
Name
A[4:3]
Floated At: (Note 1)
HLDA, AHOLD, BOFF#
HLDA, BOFF#
Note
Name
Floated At: (Note 1)
HLDA, BOFF#
HLDA, BOFF#
HLDA, BOFF#
Always Driven
HLDA, BOFF#
HLDA, BOFF#
Always Driven
Always Driven
Always Driven
Always Driven
HLDA, BOFF#
Note
Note 2,3 LOCK#
Note 2 M/IO#
Note 2 PCD
PCHK#
Note 2
Note 2
Note 2
ADS#
ADSC#
APCHK#
BE[7:0]#
BREQ
HLDA, BOFF#
Always Driven
HLDA, BOFF#
Note 2 PWT
SCYC
Note 2
Note 2
Always Driven
HLDA, BOFF#
CACHE#
D/C#
Note 2 SMIACT#
Note 2 VCC2DET
VCC2H/L#
HLDA, BOFF#
FERR#
HIT#
Always Driven
Always Driven
Always Driven
Always Driven
VID[4:0]
HITM#
HLDA
Notes:
W/R#
Note 2
1. All outputs except VCC2DET, VCC2H/L#, and TDO float during Tri-State Test mode.
2. Floated off the clock edge that BOFF# is sampled asserted and off the clock edge that HLDA is asserted.
3. Floated off the clock edge that AHOLD is sampled asserted.
Table 21. Input/Output Pin Float Conditions
Name
Floated At: (Note 1)
HLDA, AHOLD, BOFF#
HLDA, AHOLD, BOFF#
HLDA, BOFF#
Note
2,3
2,3
2
A[31:5]
AP
D[63:0]
DP[7:0]
Notes:
HLDA, BOFF#
2
1. All outputs except VCC2DET and TDO float during the Tri-State Test mode.
2. Floated off the clock edge that BOFF# is sampled asserted and off the clock edge that HLDA is asserted.
3. Floated off the clock edge that AHOLD is sampled asserted.
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Table 22. Test Pins
Name
TCK
Type
Clock
Input
Output
Input
Input
Note
TDI
Sampled on the rising edge of TCK
Driven on the falling edge of TCK
Sampled on the rising edge of TCK
Asynchronous (Independent of TCK)
TDO
TMS
TRST#
Table 23. Bus Cycle Definition
Bus Cycle Initiated
Generated
by the System
Generated by the Processor
M/IO#
D/C#
0
W/R# CACHE#
KEN#
Code Read, L1 Instruction Cache and L2 Cache Line Fill
Code Read, Noncacheable
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
1
0
0
1
0
0
0
1
1
0
1
x
1
1
1
1
0
1
x
0
1
0
x
1
x
x
x
x
0
x
1
x
x
0
Code Read, Noncacheable
0
Encoding for Special Cycle
0
Interrupt Acknowledge
0
I/O Read
1
I/O Write
1
Memory Read, L1 Data Cache and L2 Cache Line Fill
Memory Read, Noncacheable
Memory Read, Noncacheable
Memory Write, L1 Data Cache or L2 Cache Writeback
Memory Write, Noncacheable
1
1
1
1
1
Note:
x means “don’t care”
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Table 24. Special Cycles
Special Cycle
Stop Grant
1
0
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
0
0
0
0
1
1
1
1
x
x
Enhanced Power
Management (EPM)
Flush Acknowledge
(FLUSH# sampled asserted)
0
1
1
1
0
1
1
1
1
0
0
1
1
x
Writeback
(WBINVD instruction)
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
x
x
x
x
Halt
Flush (INVD, WBINVD
instruction)
Shutdown
Note:
x means “don’t care”
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5
PowerNow! Technology
5.1
Overview
AMD’s latest mobile initiative, PowerNow! technology, enables
portable designs to offer near desktop system performance in
notebook systems. PowerNow! technology uses combinations of
CPU core voltage and core frequency (PowerNow! states) to
allow for maximum Notebook PC performance in any thermal
environment while providing the user with an option to make a
trade-off bet wee n performance and run-t im e while batt ery
powered. PowerNow! technology can be used in conjunction
with the existing power management schemes in a Notebook
PC to provide a better combination of performance and power
savings than previously possible.
5.2
Enhanced Power Management Features
PowerNow!-enabled Mobile AMD-K6-2+ processors include two
n e w f e a t u r e s sp e c if ic a lly d e sig n e d t o e n h a n c e p owe r
management funct ionality—a m echanism for dynamic core
frequency control, and a mechanism for dynamic core voltage
control. These Enhanced Power Management (EPM) features
are accessed and controlled through an aligned 16-byte block
of I/O a dd re ss sp a ce t h a t is d e fin e d by t h e E P MR regist e r
(MSR —C000_0086h).
Enhanced Power
Management Register
(EPMR)
The EPMR register allows software to access the aligned EPM
16-byte b lock of I/O a dd re ss spa ce , wh ich con t a in s b it s for
enabling, controlling, and monitoring the EPM features. All
accesses to the EPM 16-byte I/O block must be aligned dword
a cce sse s. Va lid a cce sse s t o t h e E P M 16-byt e b lock d o n ot
generate I/O cycles on the host bus, while non-aligned and non-
dword accesses are passed to the host bus.
Figure 55 and Table 25 define the EPMR register. An assertion
of RESET clears all of the bits of the 16-byte I/O block to zero
(e xclu d in g t h e Volt a ge ID Ou t p u t b it s wh ich d e fa u lt t o
01010b). BIOS must always initialize the EPMR register and
EPM features whenever RESET is asserted.
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For more information about the EPMR register, see the Mobile
®
AMD-K6 Processor BIOS Design Guide Application Note, order#
23015.
3
1 0
2
4
63
16 15
G
E
N
S
B
C
IOBASE
Reserved
Symbol
IOBASE I/O Base Address
GSBC
EN
Description
Bit
15-4
1
Generate Special Bus Cycle
Enable Mobile Feature Base Address
0
Figure 55. Enhanced Power Management Register (EPMR)—MSR C000_0086h
Table 25. Enhanced Power Management Register (EPMR) Definition
Bit
Description
R/W
Function
63–16
Reserved
R
All reserved bits are always read as 0.
IOBASE defines a base address for a 16-byte block of I/O
15-4
3-2
I/O BASE Address (IOBASE)
Reserved
R/W address space accessible for enabling, controlling, and
monitoring the EPM features.
R
All reserved bits are always read as 0.
This bit controls whether a special bus cycle is generated
upon dword accesses within the EPM 16-byte I/O block. If set
to 1, an EPM special bus cycle is generated, where BE[7:0]#
= BFh and A[4:3] = 00b.
1
Generate Special Bus Cycle (GSBC)
R/W
This bit controls access to the I/O-mapped address space for
R/W the EPM features. Clearing this bit to zero does not affect the
state of bits defined in the EPM 16-byte I/O block.
Enable Mobile Feature Base Address
(EN)
0
Notes:
All bits default to 0 when RESET is asserted.
IOBASE. The IOBASE field is initialized during POST to an I/O
a dd re ss ra n ge u se d by a SMM h a n d le r t o a cce ss t h e E P M
features. Because the I/O range is only enabled and accessed by
the SMM handler during SMM, the EPM features are hidden
from all other software (OS included)—BIOS does not need to
report the I/O range to the operating system.
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GSBC. If the GSBC bit is enabled (set to 1), a special bus cycle is
generated upon a dword access within the EPM 16-byte I/O
block. The EPM special bus cycle is defined as the processor
driving D/C# = 0, M/IO# = 0, and W/R# = 1, BE[7:0]# = BFh and
A[31:3] = 0000h . Th e syst e m logic mu st re t u r n BR DY# in
response to all processor special cycles.
EN. Th e EN bit should only be enabled (set to 1) by a SMM
handler when the SMM handler accesses the EPM features.
Upon exiting, the SMM handler should disable the EN bit and
t h ereby p rot ect t h e E P M 16-byt e I/O b lock from u n want e d
accesses. When the EN bit is disabled, accesses to the EPM
block 16-byte I/O block are passed to the host bus.
EPM 16-Byte I/O
Block
Th e E P M 16-byt e I/O b lock con t a in s on e 4-byt e fie ld —Bu s
D iv i s o r a n d Vol t a g e ID C o n t r o l ( BV C ) —for e n a b l i n g ,
controlling, and monitoring the EPM features (see Figure 56).
Table 26 defines the function of the BVC field within the EPM
16-byte I/O block mapped by the EPMR.
8
7
0
12
15
11
BVC
Reserved
Symbol Description
BVC Bus Divisor and Voltage ID Control
Bytes
11-8
Figure 56. EPM 16-Byte I/O Block
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Table 26. EPM 16-Byte I/O Block Definition
Byte
Description
R/W
Function
15-12
Reserved
R
All reserved bits are always read as 0.
Bus Divisor and Voltage ID Control
(BVC)
The bit fields within the BVC bytes allow software to change
the processor bus divisor and core voltage.
11-8
R/W
R
7-0
Reserved
All reserved bits are always read as 0.
Notes:
All bits default to 0 when RESET is asserted.
5.3
Dynamic Core Frequency and Core Voltage Control
PowerNow!-enabled processors support the ability to change
the bus frequency divisor and core voltage transparently to the
u se r d u r in g r u n -t im e . Th e se fe a t u re s a re im p le m e n t e d in
con j un ct ion with a new clock cont rol sta te —t he EP M St op
Gra n t st a t e . For Powe r Now! st a t e t ra n sit ion s, t h e E P MR
register is accessed using a SMM handler. The SMM handler
initiates core voltage and frequency transitions by writing a
non-zero value to the Stop Grant Time-out Counter (SGTC).
This action automatically places the processor into the EPM
St op Grant Stat e and transitions the CPU core voltage and
fre quency to the values specified in the Voltage ID Output
(VIDO) and Internal BF Divisor (IBF) fields of the BVC field.
Once the timer of the SGTC has expired, the EPM Stop Grant
St a t e is e x it e d a n d t h e Powe r Now! st a t e t r a n sit ion is
completed.
Effective Bus Divisors
EBF[2:0]
The processor core frequency is controlled by the Effective Bus
Frequency Divisor—EBF[2:0]—which dictates the processor-to-
bus clock ratio supplied to the processor’s internal PLL. This
processor-to-bus clock ratio is multiplied by the external bus
frequency to set the frequency of operation for the processor
core. At the fall of RESET, the EBF[2:0] value is determined by
the state of the processor BF[2:0] input pins. Afterwards, the
E BF [2:0] va lu e ca n b e d yn a m ica lly con t r olle d t h r ou gh
PowerNow! state transitions. Table 27 on page 135 lists valid
EBF[2:0] states and equivalent processor- to-bus clock ratios.
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Table 27. Processor-to-Bus Clock Ratios
State of EBF[2:0]
Processor-to-Bus Clock Ratio
100b
101b
110b
111b
000b
001b
010b
011b
2.0x*
3.0x
6.0x
3.5x
4.5x
5.0x
4.0x
5.5x
Note:
*
0.18-micron processors do not support the 2.5x ratio supported by earlier AMD-K6
processors. Instead, a ratio of 2.0x is selected when EBF[2:0] equals 100b.
Dynamic Core
Frequency Control
For PowerNow! core frequency transitions, the BVC field of the
EPM 16-byte I/O block is accessed through a SMM handler. To
ch a n ge t h e p r oce ssor cor e fre q u e n cy, t h e SMM h a n d le r
initiates core voltage and frequency transitions by writing a
non-zero value to the SGTC. This action automatically places
the processor into the EPM Stop Grant state and transitions the
CPU core voltage and frequency to the values specified in the
VIDO and IBF fields of the BVC field.
Note: System-initiated inquire (snoop) cycles are not supported
and must be prevented during the EPM Stop Grant state.
BVC. Figure 57 on page 136 shows the format, and Table 28 on
p a ge 136 d e fin e s t h e fu n ct ion of e a ch b it of t h e BVC fie ld
located within the EPM 16-byte I/O block.
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11 10 9
7
8
5 4
0
12
31
V
I
D
C
B
V
C
SGTC
VIDO
BDC IBF[2:0]
M
Reserved
Symbol
SGTC
BVCM
VIDC
Description
Bits
31-12
11
Stop Grant Time-out Counter
Bus Divisor and VID Change Mode
Voltage ID Control
10
BDC
Bus Divisor Control
9-8
7-5
4-0
IBF[2:0] Internal BF Divisor
VIDO Voltage ID Output
Figure 57. Bus Divisor and Voltage ID Control (BVC) Field
Table 28. Bus Divisor and Voltage ID Control (BVC) Definition
Bit
Description
R/W
Function
Writing a non-zero value to this field causes the processor to
enter the EPM Stop Grant state internally. This 20-bit value is
multiplied by 4096 to determine the duration of the EPM
Stop Grant state, measured in processor bus clocks.
31-12 Stop Grant Time-out Counter (SGTC)
W
This bit controls the mode in which the bus-divisor and the
voltage control bits are allowed to change. If BVCM=0, the
R/W Bus Divisor and Voltage ID changes take effect only upon
entering the EPM Stop Grant state as a result of the SGTC
field being programmed. BVCM=1 is reserved.
Bus Divisor and VID Change Mode
11
(BVCM)
This bit controls the mode of Voltage ID control. If VIDC=0,
the processor VID[4:0] pins are unchanged upon entering
the EPM Stop Grant state. If VIDC=1, the processor VID[4:0]
pins are programmed to the VIDO value upon entering the
10
Voltage ID Control (VIDC)
R/W
EPM Stop Grant state. BIOS should initialize this bit to 1
during the POST routine.
This 2-bit field controls the mode of Bus Divisor control. If
BDC[1:0]=00b, the BF[2:0] pins are sampled at the falling
edge of RESET. If BDC[1:0]=1xb, the IBF[2:0] field is sampled
upon entering the EPM Stop Grant state. BDC[1:0]=01b is
reserved. BIOS should initialize these bits to 10b during the
POST routine.
9-8
7-5
Bus Divisor Control (BDC)
Internal BF Divisor (IBF[2:0])
R/W
If BDC[1:0]=1xb, the processor EBF[2:0] field of the PSOR is
R/W programmed to the IBF[2:0] value upon entering the EPM
Stop Grant state.
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Table 28. Bus Divisor and Voltage ID Control (BVC) Definition
Bit
Description
R/W
Function
This 5-bit value is driven out on the processor VID[4:0] pins
upon entering the EPM Stop Grant state if the VIDC bit=1.
These bits are initialized to 01010b and driven on the
processor VID[4:0] pins at RESET.
4-0
Voltage ID Output (VIDO)
R/W
Notes:
All bits default to 0 when RESET is asserted, except the VIDO bits which default to 01010b.
Voltage Identification
(VID) Outputs
Powe r Now!-e n ab le d p roce ssors fe a t u re Volt a ge ID (VID)
outputs to support dynamic control of the core voltage. These
outputs serve as inputs to a DC/DC regulator that supplies the
p roce ssor core volt a ge . Ba se d on it s VID[4:0] in p u t s, t h e
regulator outputs a corresponding voltage. For those regulators
that do not support VID inputs, the processor VID[4:0] outputs
must be used to manipulate the regulator’s feedback voltage to
vary the regulator output voltage.
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6
Bus Cycles
The following sections describe and illustrate the timing and
relationship of bus signals during various types of bus cycles. A
representative set of bus cycles is illustrated.
6.1
Timing Diagrams
The timing diagrams illustrate the signals on the external local
bus as a function of time, as measured by the bus clock (CLK).
Th rou gh ou t t h is ch a p t e r, t h e t e r m clock re fe rs t o a sin gle
bus-clock cycle. A clock extends from one rising CLK edge to
the next rising CLK edge. The processor samples and drives
most signals relative to the rising edge of CLK. The exceptions
to this rule include the following:
■ BF[2:0]—Sampled on the falling edge of RESET
■ FLUSH#—Sampled on the falling edge of RESET, also
sampled on the rising edge of CLK
■ All inputs and outputs are sampled relative to TCK in
Boundary-Scan Test Mode. Inputs are sampled on the rising
edge of TCK, outputs are driven off of the falling edge of
TCK.
Fo r e a ch sign a l in t h e t im in g d ia gr a m s, t h e H igh le ve l
represents 1, the Low level represents 0, and the Middle level
represents the floating (high-impedance) state. When both the
High and Low levels are shown, the meaning depends on the
signal. A single signal indicates ‘don’t care’. In the case of bus
activity, if both High and Low levels are shown, it indicates the
processor, alternate master, or system logic is driving a value,
but this value may or may not be valid. (For example, the value
on the address bus is valid only during the assertion of ADS#,
b u t a d d re sse s a re a lso d r ive n on t h e b u s a t ot h e r t im e s.)
Figu r e 58 on p a ge 140 d e fin e s t h e d iffe r e n t wa ve for m
representations.
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Waveform
Description
Don’t care or bus is driven
Signal or bus is changing from Low to High
Signal or bus is changing from High to Low
Bus is changing
Bus is changing from valid to invalid
Signal or bus is floating
Denotes multiple clock periods
Figure 58. Waveform Definitions
For all active-High signals, the term asserted means the signal is
in the High-voltage state and the term negated means the signal
is in the Low-voltage state. For all active-Low signals, the term
asserted means the signal is in the Low-voltage state and the
term negated means the signal is in the High-voltage state.
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6.2
Bus State Machine Diagram
Bus State
Branch Condition
Addr
Data
Yes
No
Pending
Address
Data
Request?
Idle
Idle
No
Yes
Yes
No
Last BRDY#
Asserted?
NA# Sampled
Asserted?
Yes
Data-NA#
Data-NA#
Requested
Last BRDY#
Asserted?
No
Yes
Pending
No
No
NA# Sampled
Asserted?
Request?
Yes
Pipe-A
Pipeline
Address
Pipe-D
Trans
Pipeline
Data
No
Yes
Last BRDY#
Asserted?
Yes
Yes
No
NA# Sampled
Asserted?
Transition
Bus Transition?
No
Note: The processor transitions to the IDLE state on the clock edge on which BOFF# or RESET is sampled asserted.
Figure 59. Bus State Machine Diagram
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Idle
The processor does not drive the system bus in the Idle state
and remains in this state until a new bus cycle is requested. The
processor enters this state off the clock edge on which the last
BRDY# of a cycle is sa mple d a sser t e d dur ing the following
conditions:
■ The processor is in the Data state
■ The processor is in the Data-NA# Requested state and no
internal pending cycle is requested
In addit ion, the processor is forced into t his stat e when the
system logic asserts RESET or BOFF#. The transition to this
state occurs on the clock edge on which RESET or BOFF# is
sampled asserted.
Address
Data
In t h is st a t e , t h e p r oce ssor d r ive s ADS# t o in d ica t e t h e
beginning of a new bus cycle by validat ing the addre ss and
control signals. The processor remains in this state for one clock
and uncon ditionally enters the Data state on the next clock
edge.
In the Data state, the processor drives the data bus during a
write cycle or expects data to be returned during a read cycle.
The processor remains in this state until either NA# or the last
BR DY# is sa m p le d a sse r t e d . If t h e la st BR DY# is sa m p le d
asserted or both the last BRDY# and NA# are sampled asserted
on the same clock edge, the processor enters the Idle state. If
NA# is sa m p le d a sse r t e d fir st , t h e p r oce ssor e n t e r s t h e
Data-NA# Requested state.
Data-NA# Requested
If the processor samples NA# asserted while in the Data state
and the current bus cycle is not completed (the last BRDY# is
not sampled asserted), it enters the Data-NA# Requested state.
The processor remains in this state until either the last BRDY#
is sampled asserted or an internal pending cycle is requested. If
the last BRDY# is sampled asserted before the processor drives
a new bus cycle, the processor enters the Idle state (no internal
pending cycle is requested) or the Address state (processor has
a internal pending cycle).
In t h is st a t e , t h e p r oce ssor d r ive s ADS# t o in d ica t e t h e
beginning of a new bus cycle by validat ing the addre ss and
control signals. In this state, the processor is still waiting for the
cu r re n t b u s cycle t o b e comp le t ed (u n t il t h e la st BR DY# is
Pipeline Address
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sampled asserted). If the last BRDY# is not sampled asserted,
the processor enters the Pipeline Data state.
If the processor samples the last BRDY# asserted in this state, it
determines if a bus transition is required between the current
b u s cycle a n d t h e p ip e lin e d b u s cycle . A b u s t ra n sit ion is
required whe n the da ta bus direct ion cha nge s betwe e n bus
cycles, such as a memory write cycle followed by a memory read
cycle. If a bus transition is required, the processor enters the
Transition state for one clock to prevent data bus contention. If
a bus transition is not required, the processor enters the Data
state.
The processor does not transition to the Data-NA# Requested
state from the Pipeline Address state because the processor
does not begin sampling NA# until it has exited the Pipeline
Address state.
Pipeline Data
Two bus cycles are concurrently executing in this state. The
p roce ssor ca n n ot issu e a ny a d d it ion a l b u s cycle s u n t il t h e
current bus cycle is completed. The processor drives the data
bus during write cycles or expects data to be returned during
read cycles for the current bus cycle until the last BRDY# of the
current bus cycle is sampled asserted.
If the processor samples the last BRDY# asserted in this state, it
determines if a bus transition is required between the current
bus cycle and the pipelined bus cycle. If the bus transition is
required, the processor enters the Transition state for one clock
t o p reve n t d a t a b u s con t e n t ion . If a b u s t ra n sit ion is n ot
re q u ire d , th e p roce ssor e nt ers the Dat a sta te (NA# was n ot
sampled asserted) or the Data-NA# Requested state (NA# was
sampled asserted).
Transition
The processor enters this state for one clock during data bus
transitions and enters the Data state on the next clock edge if
NA# is not sampled asserted. The sole purpose of this state is to
avoid bus contention caused by bus transitions during pipeline
operation.
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6.3
Memory Reads and Writes
Th e Mob ile AMD-K6-2+ p roce ssor p e r form s sin gle or b u rst
m e m ory b u s cycle s. Th e sin gle -t ra n sfe r m e m ory b u s cycle
t ra n sfe rs 1, 2, 4, or 8 byt e s a n d re q u ire s a m in imum of t wo
clocks. Misaligned instruct ions or operands result in a split
cycle, which requires multiple transactions on the bus. A burst
cycle consists of four back-to-back 8-byte (64-bit) transfers on
the data bus.
Single-Transfer
Memory Read and
Write
Figu re 60 on p a ge 145 sh ows a sin gle -t ra n sfe r re a d fr om
memory, followed by two single-transfer writes to memory. For
t h e m e m ory re a d cycle , t he p roce ssor a sse r t s ADS# for one
clock to validate the bus cycle and also drives A[31:3], BE[7:0]#,
D/C#, W/R#, and M/IO# to the bus. The processor then waits for
the system logic to return the data on D[63:0] (with DP[7:0] for
p a r it y ch e ck in g) a n d a sse r t BR DY#. The p roce ssor sa m p le s
BRDY# on every clock edge starting with the clock edge after
the clock edge that negates ADS#. See “BRDY# (Burst Ready)”
on page 96.
Dur ing the re ad cycle, the proce ssor dr ives P CD, P WT, a nd
CACHE# to indicate its caching and cache-coherency intent for
t h e a ccess. The syst em logic ret u r n s KE N# an d WB/WT# to
either confirm or change this intent. If the processor asserts
PCD and negates CACHE#, the accesses are noncacheable, even
though t he syst em logic asserts KEN# during the BRDY# to
in dica te it s su ppor t for ca ch e ab ility. Th e proce ssor (wh ich
drives CACHE#) and the system logic (which drives KEN#) must
agree in order for an access to be cacheable.
The processor can drive another cycle (in this example, a write
cycle) by asserting ADS# off the next clock edge after BRDY# is
sa m p le d a sse r t e d . Th e re fore , a n id le clock is gu a ra n t e e d
between any two bus cycles. The processor drives D[63:0] with
valid data one clock edge after the clock edge on which ADS# is
asserted. To minim ize processor idle times, the system logic
stores the address and data in write buffers, returns BRDY#, and
performs the store to memory later. If the processor samples
E WBE # n e ga t e d d u r in g a wr it e cycle , it su sp e n d s ce r t a in
a ct ivit ie s u n t il E WBE # is sa m p le d a sse r t e d . Se e “ E WBE #
(External Write Buffer Empty)” on page 103. In Figure 60, the
second write cycle occurs during the execution of a serializing
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in st r u ct ion . Th e p roce ssor d e lays t h e followin g cycle u n t il
EWBE# is sampled asserted.
Write Cycle (Next Cycle Delayed by EWBE#)
Write Cycle
Read Cycle
DATA IDLE ADDR DATA
ADDR DATA IDLE ADDR DATA
DATA IDLE IDLE
IDLE
IDLE ADDR
IDLE
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
BREQ
D[63:0]
DP[7:0]
CACHE#
EWBE#
KEN#
BRDY#
WB/WT#
Figure 60. Non-Pipelined Single-Transfer Memory Read/Write and Write Delayed by EWBE#
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Misaligned
Figure 61 on page 147 shows a misaligned (split) memory read
followed by a misaligned memory write. Any cycle that is not
a lign e d a s d e fin e d in “ SCYC (Sp lit Cycle )” on p a ge 119 is
con sid e re d m isa lign e d . Wh e n t h e p roce ssor e n cou n t e rs a
misaligned access, it determines the appropriate pair of bus
cycle s —e a ch wit h it s own ADS# a n d BR DY# — re qu ire d t o
complete the access.
Single-Transfer
Memory Read and
Write
The Mobile AMD-K6-2+ processor performs misaligned memory
reads and memory writes using least-significant bytes (LSBs)
first followed by most-significant bytes (MSBs). Table 29 shows
the order. In the first memory read cycle in Figure 61 on page
1 4 7 , t h e p r o c e s s o r r e a d s t h e l e a s t -s i g n i f i c a n t b y t e s .
Immediately after the processor samples BRDY# asserted, it
drives the second bus cycle to read the most-significant bytes to
complete the misaligned transfer.
Table 29. Bus-Cycle Order During Misaligned Transfers
Type of Access
Memory Read
Memory Write
First Cycle
LSBs
Second Cycle
MSBs
LSBs
MSBs
Similarly, the misaligned memory write cycle in Figure 61 on
page 147 transfers the LSBs to the memory bus first. In the next
cycle, after the processor samples BRDY# asserted, the MSBs
are written to the memory bus.
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Memory Write (Misaligned)
Memory Read (Misaligned)
DATA IDLE ADDR DATA
DATA IDLE
DATA
ADDR DATA DATA DATA IDLE
DATA IDLE ADDR DATA
ADDR DATA
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
LSB
MSB
LSB
MSB
D[63:0]
BRDY#
Figure 61. Misaligned Single-Transfer Memory Read and Write
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Burst Reads and
Pipelined Burst Reads
Figure 62 on page 149 shows normal burst read cycles and a
pipelined burst read cycle. The Mobile AMD-K6-2+ processor
drives CACHE# and ADS# together to specify that the current
b u s cycle is a b u rst cycle . If t h e p roce ssor sa m p le s KE N#
a sser t e d wit h t h e first BR DY#, it p e r form s b u rst t ran sfe rs.
Du r in g t h e b u rst t ra n sfe rs, t h e syst e m logic m u st ign ore
BE [7:0]# a n d mu st re t u r n a ll e igh t byt e s b e gin n in g a t t h e
starting address the processor asserts on A[31:3]. Depending on
t h e st a r t in g a d d re ss, t h e syst e m logic mu st d e t e r m in e t h e
successive quadword addresses (A[4:3]) for each transfer in a
burst, as shown in Table 30. The processor expects the second,
third, and fourth quadwords to occur in the sequences shown in
Table 30.
Table 30. A[4:3] Address-Generation Sequence During Bursts
Address Driven By
Processor on A[4:3]
A[4:3] Addresses of Subsequent
Quadwords* Generated By System Logic
Quadword 1
Quadword 2
Quadword 3
Quadword 4
00b
01b
10b
11b
01b
00b
11b
10b
10b
11b
00b
01b
11b
10b
01b
00b
Note:
*
quadword = 8 bytes
In Figu re 62 on p a ge 149, t h e p r oce ssor d r ive s CACH E #
throughout all burst read cycles. In the first burst read cycle,
the processor drives ADS# and CACHE#, then samples BRDY#
on every clock edge starting with the clock edge after the clock
edge that negates ADS#. The processor samples KEN# asserted
on the clock edge on which the first BRDY# is sampled asserted,
executes a 32-byte burst read cycle, and expects a total of four
BRDY# signals. An ideal no-wait state access is shown in Figure
62, whereas most system logic solutions add wait states between
the transfers.
The second burst read cycle illustrates a similar sequence, but
the processor samples NA# asserted on the same clock edge
t h a t t h e first BR DY# is sa m p le d a sse r t e d . NA# a sse r t ion
indicates the system logic is requesting the processor to output
t h e n ext a d d re ss e a rly (a lso k n own a s a p ip e lin e t ra n sfe r
request). Without waiting for the current cycle to complete, the
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processor drives ADS# and related signals for the next burst
cycle. Pipelining can reduce processor cycle-to-cycle idle times.
Burst Read
Burst Read
Pipelined Burst Read
DATA PIPE
ADDR DATA DATA DATA DATA IDLE ADDR DATA DATA
DATA DATA DATA DATA IDLE
-NA -ADDR
CLK
ADDR1
ADDR2
ADDR3
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
NA#
DATA1
DATA2
DATA3
D[63:0]
CACHE#
KEN#
BRDY#
Figure 62. Burst Reads and Pipelined Burst Reads
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Burst Writeback
Figu re 63 on p a ge 151 sh ows a b u r st r e a d followe d by a
wr it eb a ck t ra n sa ct ion . Th e Mob ile AMD-K6-2+ p roce ssor
initiates writebacks under the following conditions:
■ Replacement —If a cache-line fill is initiated for a cache line
currently filled with valid entries, the processor selects a
line for replacement based on a least-recently-used (LRU)
algorithm for the L1 instruction cache and the L2 cache, and
a least-recently-allocated (LRA) algorithm for the L1 data
cache. Before a replacement is made to a L1 data cache or L2
cache line that is in the modified state, the modified line is
scheduled to be written back to memory.
■ Internal Snoop—The processor snoops its L1 instruction
cache during read or write misses to its L1 data cache, and it
snoops its L1 data cache during read misses to its L1
instruction cache. This snooping is performed to determine
whether the same address is stored in both caches, a
situation that is taken to imply the occurrence of
self-modifying code. If an internal snoop hits a L1 data cache
line in the modified state, the line is written back to memory
before being invalidated.
■ WBINVD Instruction —When the processor executes a
WBINVD instruction, it writes back all modified lines in the
L1 data cache and L2 cache, and then invalidates all lines in
all caches.
■ Cache Flush —When the processor samples FLUSH#
asserted, it executes a flush acknowledge special cycle and
writes back all modified lines in the L1 data cache and L2
cache, and then invalidates all lines in all caches.
The processor drives writeback cycles during inquire or cache
flush cycles. The writeback shown in Figure 63 on page 151 is
caused by a cache-line replacement. The processor completes
t h e b u rst re a d cycle t h a t fills t h e ca ch e lin e . Im m e d ia t e ly
following the burst read cycle is the burst writeback cycle that
rep re sent s t he modified line to be writt en ba ck t o m emory.
D[63:0] are driven one clock edge after the clock edge on which
ADS# is asserted and are subsequently changed off the clock
edge on which each of the four BRDY# signals of the burst cycle
are sampled asserted.
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Burst Read
Burst Writeback from L1 Cache
DATA DATA DATA
ADDR
DATA IDLE
DATA DATA DATA
ADDR
DATA IDLE
CLK
A[31:3]
BE[7:0]#
ADS#
CACHE#
M/IO#
D/C#
W/R#
D[63:0]
KEN#
BRDY#
WB/WT#
Figure 63. Burst Writeback due to Cache-Line Replacement
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6.4
I/O Read and Write
Basic I/O Read and
Write
The processor accesses I/O when it executes an I/O instruction
(for example, IN or OUT). Figure 64 on page 152 shows an I/O
read followed by an I/O write. The processor drives M/IO# Low
and D/C# High during I/O cycles. In this example, the first cycle
shows a single wait st ate I/O read cycle. It follows the same
sequence as a single-transfer memory read cycle. The processor
drives ADS# to initiate the bus cycle, then it samples BRDY# on
every clock edge starting with the clock edge after the clock
edge that negates ADS#. The system logic must return BRDY#
t o comp le te t h e cycle . When t he processor sa mple s BR DY#
asserted, it can assert ADS# for the next cycle off the next clock
edge. (In this example, an I/O write cycle.)
The I/O write cycle is similar to a memory write cycle, but the
p roce ssor d r ive s M/IO# low d u r in g a n I/O wr it e cycle . Th e
processor asserts ADS# to initiate the bus cycle. The processor
drives D[63:0] with valid data one clock edge after the clock
edge on which ADS# is asserted. The system logic must assert
BRDY# when the data is properly stored to the I/O destination.
The processor samples BRDY# on every clock edge starting with
the clock edge after the clock edge that negates ADS#. In this
example, two wait states are inserted while the processor waits
for BRDY# to be asserted.
I/O Write Cycle
I/O Read Cycle
DATA
IDLE
IDLE
DATA
DATA
DATA
DATA
ADDR
ADDR
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
D[63:0]
BRDY#
Figure 64. Basic I/O Read and Write
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Misaligned I/O Read
and Write
Table 31 shows the misaligned I/O read and write cycle order
executed by the Mobile AMD-K6-2+ processor. In Figure 65, the
least-significant bytes (LSBs) are transferred first. Immediately
a ft e r t h e p roce ssor sa m p le s BR DY# a sse r t e d, it d r ive s t he
second bus cycle to transfer the most-significant bytes (MSBs)
to complete the misaligned bus cycle.
Table 31. Bus-Cycle Order During Misaligned I/O Transfers
Type of Access
I/O Read
First Cycle
LSBs
Second Cycle
MSBs
I/O Write
LSBs
MSBs
Misaligned I/O Write
Misaligned I/O Read
ADDR DATA DATA IDLE ADDR DATA DATA IDLE ADDR DATA
DATA
IDLE ADDR DATA
DATA
DATA
DATA IDLE
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
SCYC
D[63:0]
BRDY#
LSB
MSB
LSB
MSB
Figure 65. Misaligned I/O Transfer
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6.5
Inquire and Bus Arbitration Cycles
The Mobile AMD-K6-2+ processor provides built-in level-one
(L1) data and instruction caches, and a unified level-two (L2)
cache. Each L1 cache is 32 Kbytes and two-way set-associative.
The L2 cache is 128 Kbytes and four-way set-associative. The
system logic or other bus master devices can initiate an inquire
cycle to maintain cache/memory coherency. In response to the
inquire cycle, the processor compares the inquire address with
its cache tag addresses in all caches, and, if necessary, updates
the MESI state of the cache line and performs writebacks to
memory.
An inquire cycle can be initiated by asserting AHOLD, BOFF#,
or HOLD. AHOLD is exclusively used to support inquire cycles.
Du ring AHOLD-initia te d inquire cycle s, the proce ssor only
floats the address bus. BOFF# provides the fastest access to the
bus because it aborts any processor cycle that is in-progress,
wh ereas AHOLD and HOLD both permit an in-progress bus
cycle to complete. During HOLD-initiated and BOFF#-initiated
inquire cycles, the processor floats all of its bus-driving signals.
Th e Mobile AMD-K6-2+ processor does not support system-
i n i t i a t e d i n q u i r e cy c l e s d u r i n g t h e E n h a n c e d P owe r
Management (EPM) Stop Grant State. For more information on
the EPM Stop Grant State, see “Clock Control” on page 263.
Hold and Hold
Acknowledge Cycle
Th e system logic or another bus device can assert HOLD to
initiate an inquire cycle or to gain full control of the bus. When
the Mobile AMD-K6-2+ processor samples HOLD asserted, it
com p le t e s a ny in -p rogre ss b u s cycle a n d a sse r t s H LDA t o
a ck n owle d ge re le a se of t h e b u s. Th e p roce ssor floa t s t h e
following signals off the same clock edge that HLDA is asserted:
■ A[31:3]
■ ADS#
■ DP[7:0]
■ LOCK#
■ M/IO#
■ PCD
■ AP#
■ BE[7:0]#
■ CACHE#
■ D[63:0]
■ D/C#
■ PWT
■ SCYC
■ W/R#
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Figu re 66 sh ows a b a sic H OLD/H LDA op e ra t ion . In t h is
exa mple, the processor sam ples HOLD asserted during the
memory read cycle. It continues the current memory read cycle
until BRDY# is sampled asserted. The processor drives HLDA
and floats its outputs one clock edge after the last BRDY# of the
cycle is sampled asserted. The system logic can assert HOLD for
as long as it needs to utilize the bus. The processor samples
HOLD on every clock edge but does not assert HLDA until any
in-progress cycle or sequence of locked cycles is completed.
Wh e n t h e p roce ssor sa m ple s H OLD n e ga t e d d u r in g a h old
acknowledge cycle, it negates HLDA off the next clock edge.
The processor regains control of the bus and can assert ADS#
off the same clock edge on which HLDA is negated.
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
D[63:0]
HOLD
HLDA
BRDY#
Figure 66. Basic HOLD/HLDA Operation
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HOLD-Initiated
Inquire Hit to Shared
or Exclusive Line
Figure 67 on page 157 shows a HOLD-initiated inquire cycle. In
this example, the processor samples HOLD asserted during the
burst memory read cycle. The processor completes the current
cycle (until the la st expe cte d BRDY# is sample d a sserte d),
asserts HLDA and floats its outputs as described on page 154.
Th e syst e m logic d r ive s a n in q u ire cycle wit h in t h e h old
a ck n owle d ge cycle . It a sse r t s E ADS#, wh ich va lid a t e s t h e
in q u ire a dd re ss on A[31:5]. If E ADS# is sa m p le d a sse r t e d
before HOLD is sampled negated, the processor recognizes it as
a valid inquire cycle.
In Figu re 67 on p a ge 157, t h e p roce ssor a sse r t s H IT# a n d
negates HITM# on the clock edge after the clock edge on which
E ADS# is sa mple d a sser te d, in dica t ing t he curre nt inqu ire
cycle hit a shared or exclusive cache line. (Shared and exclusive
ca ch e lin e s h ave n ot b e e n m od ifie d a n d d o n ot n e e d t o b e
written back.) During an inquire cycle, the processor samples
INV to determine whether the addressed cache line found in
the processor’s caches transitions to the invalid state or the
sh a re d st a t e . In t h is exa m p le , t h e p roce ssor sa m p le s INV
asserted with EADS#, which invalidates the cache line.
The system logic can negate HOLD off the same clock edge on
which EADS# is sampled asserted. The processor continues
drivin g HIT# in the sam e state unt il the next inquire cycle.
HITM# is not asserted unless HIT# is asserted.
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Burst Memory Read
Inquire
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
HIT#
HITM#
D[63:0]
KEN#
BRDY#
HOLD
HLDA
EADS#
INV
Figure 67. HOLD-Initiated Inquire Hit to Shared or Exclusive Line
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HOLD-Initiated
Inquire Hit to
Modified Line
Figure 68 on page 159 shows the same sequence as Figure 67 on
page 157, but in Figure 68 the inquire cycle hits a modified line
a n d t h e p roce ssor a sse r t s b ot h H IT# a n d H ITM#. In t h is
example, the processor performs a writeback cycle immediately
after the inquire cycle. It updates the modified cache line to
exte rn al m emory (n orm ally, exte rna l cache or DRAM). The
processor uses the address (A[31:5]) that was latched during the
inquire cycle to perform the writeback cycle. The processor
asserts HITM# t hroughout t he writeback cycle and negate s
HITM# one clock edge after the last expected BRDY# of the
writeback is sampled asserted.
When the processor samples EADS# during the inquire cycle, it
also samples INV to determine the cache line MESI state after
the inquire cycle. If INV is sampled asserted during an inquire
cycle, the processor transitions the line (if found) to the invalid
st a t e , r e g a r d le ss of it s p r e v io u s st a t e . Th e c a ch e lin e
inva lid a t ion op e ra t ion is n ot visib le on t h e b u s. If INV is
sa m p le d n e ga t e d d u r in g a n in q u ire cycle , t h e p r oce ssor
transitions the line (if found) to the shared state. In Figure 68
on page 159 the processor samples INV asserted d uring the
inquire cycle.
In a HOLD-initiated inquire cycle, the system logic can negate
HOLD off the sam e clock edge on which EADS# is sampled
asserted. The processor drives HIT# and HITM# on the clock
edge after the clock edge on which EADS# is sampled asserted.
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Burst Memory Read
Writeback Cycle
Inquire
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
HIT#
HITM#
D[63:0]
KEN#
BRDY#
HOLD
HLDA
EADS#
INV
Figure 68. HOLD-Initiated Inquire Hit to Modified Line
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AHOLD-Initiated
Inquire Miss
AHOLD can be asserted by the system to initiate one or more
inquire cycles. To allow the system to drive the address bus
during an inquire cycle, the processor floats A[31:3] and AP off
the clock edge on which AHOLD is sampled asserted. The data
bus and all other control and status signals remain under the
control of the processor and are not floated. This functionality
allows a bus cycle in progress when AHOLD is sampled asserted
to continue to completion. The processor resumes driving the
address bus off the clock edge on which AHOLD is sampled
negated.
In Figu re 69 on p a ge 161, t h e p roce ssor sa m p le s AH OLD
asserted during the memory burst read cycle, and it floats the
a d d re ss b u s off t h e sa m e clock e d ge on wh ich it sa m p le s
AHOLD asserted. While the processor still controls the bus, it
completes the current cycle until the last expected BRDY# is
sa m p le d a sse r t e d . Th e syst e m logic d r ive s E ADS# wit h a n
in q u ire a d d re ss on A[31:5] d u r in g a n in q u ire cycle . Th e
processor samples EADS# asserted and compares the inquire
address to its tag address in the L1 instruction and data caches,
and in the L2 cache. In Figure 69, the inquire address misses the
t a g a d d re ss in t h e p r oce ssor (b ot h H IT# a n d H ITM# a re
negated). Therefore, the processor proceeds to the next cycle
when it samples AHOLD negated. (The processor can drive a
new cycle by asserting ADS# off the same clock edge that it
samples AHOLD negated.)
For an AHOLD-initiated inquire cycle to be recognized, the
p roce ssor m u st sa m p le AH OLD a sse r t e d for a t le a st t wo
consecutive clocks before it samples EADS# asserted. If the
processor detect s an address parit y error during an inquire
cycle, APCHK# is asserted for one clock. The system logic must
respond appropriately to the assertion of this signal.
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Inquire
Read
CLK
A[31:3]
BE[7:0]#
AP
APCHK#
ADS#
HIT#
HITM#
D[63:0]
KEN#
BRDY#
AHOLD
EADS#
INV
Figure 69. AHOLD-Initiated Inquire Miss
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AHOLD-Initiated
Inquire Hit to Shared
or Exclusive Line
In Figu re 70 on p a ge 163, t h e p roce ssor a sse r t s H IT# a n d
negates HITM# off the clock edge after the clock edge on which
E ADS# is sample d a sse r te d, indica t in g t he cu rre nt in quire
cycle hits either a shared or exclusive line. (HIT# is driven in
t h e sa me st a t e u n t il t h e n ext in q u ire cycle.) The p roce ssor
samples INV asserted during the inquire cycle and transitions
the line to the invalid state regardless of its previous state.
Du r in g a n AH OLD-in it ia t e d in q u ire cycle , t h e p roce ssor
sa mp le s AH OLD on eve ry clock e d ge u n t il it is n egat e d . In
Figure 70 on page 163, the processor asserts ADS# off the same
clock on which AHOLD is sampled negated. If the inquire cycle
hits a modified line, the processor performs a writeback cycle
before it drives a new bus cycle. The next section describes the
AHOLD-initiated inquire cycle that hits a modified line.
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Inquire
Burst Memory Read
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
HIT#
HITM#
D[63:0]
KEN#
BRDY#
AHOLD
EADS#
INV
Figure 70. AHOLD-Initiated Inquire Hit to Shared or Exclusive Line
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AHOLD-Initiated
Inquire Hit to
Modified Line
Figure 71 on page 165 shows an AHOLD-initiated inquire cycle
t h a t h it s a m od ifie d lin e . Du r in g t h e in q u ire cycle in t h is
example, the processor asserts both HIT# and HITM# on the
clock edge after the clock edge that it samples EADS# asserted.
Th is con d it ion in d ica t e s t h a t t h e ca ch e lin e e xist s in t h e
processor’s L1 data cache or L2 cache in the modified state.
If the inquire cycle hits a modified line, the processor performs
a writeback cycle immediately after the inquire cycle to update
the modified cache line to shared memory (normally external
cache or DRAM). In Figure 71 on page 165, the system logic
holds AHOLD asserted throughout the inquire cycle and the
processor writeback cycle. In this case, the processor is not
driving the address bus during the writeback cycle becau se
AHOLD is sampled asserted. The system logic writes the data to
memory by using its latched copy of the inquire cycle address. If
the processor samples AHOLD negated before it performs the
wr it eb a ck cycle , it d r ive s t h e wr it eb a ck cycle by u sin g t h e
address (A[31:5]) that it latched during the inquire cycle.
If INV is sa m p le d a sse r t e d d u r in g a n in q u ire cycle , t h e
processor transitions the line (if found) to the invalid state,
r e ga r d le ss of it s p re viou s st a t e (t h e ca ch e in va lid a t ion
operation is not visible on the bus). If INV is sampled negated
during an inquire cycle, the processor transitions the line (if
found) to the shared state. In either case, if the line is found in
t h e m od ified st a t e, t h e p roce ssor write s it b a ck t o m em ory
before changing its state. Figure 71 shows that the processor
samples INV asserted during the inquire cycle and invalidates
the cache line after the inquire cycle.
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Burst Memory Read
Inquire
Writeback
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
HIT#
HITM#
D[63:0]
KEN#
BRDY#
AHOLD
EADS#
INV
Figure 71. AHOLD-Initiated Inquire Hit to Modified Line
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AHOLD Restriction
Wh e n t h e syst e m logic d r ive s a n AH OLD-in it ia t e d in q u ire
cycle, it must assert AHOLD for at least two clocks before it
asse rt s EADS#. This requirem ent guarant ees t he processor
re cogn ize s a nd re sp on ds t o t he in quire cycle p rop erly. The
processor’s 32 address bus drivers turn on almost immediately
after AHOLD is sampled negated. If the processor switches the
data bus (D[63:0] and DP[7:0]) during a write cycle off the same
clock edge that switches the address bus (A[31:3] and AP), the
processor switches 102 drivers simultaneously, which can lead
to ground-bounce spikes. Therefore, before negating AHOLD
the following restrictions must be observed by the system logic:
■ When the system logic negates AHOLD during a write cycle,
it must ensure that AHOLD is not sampled negated on the
clock edge on which BRDY# is sampled asserted (See Figure
72 on page 167).
■ When the system logic negates AHOLD during a writeback
cycle, it must ensure that AHOLD is not sampled negated on
the clock edge on which ADS# is negated (See Figure 72 on
page 167).
■ When a write cycle is pipelined into a read cycle, AHOLD
must not be sampled negated on the clock edge after the
clock edge on which the last BRDY# of the read cycle is
sampled asserted to avoid the processor simultaneously
driving the data bus (for the pending write cycle) and the
address bus off this same clock edge.
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CLK
ADS#
W/R#
HITM#
EADS#
D[63:0]
BRDY#
Legal AHOLD negation during write cycle
AHOLD
Illegal AHOLD negation during write cycle
The system must ensure that AHOLD is not sampled negated on the clock edge that ADS# is negated.
The system must ensure that AHOLD is not sampled negated on the clock edge on which BRDY# is sampled
asserted.
Figure 72. AHOLD Restriction
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Bus Backoff (BOFF#)
BOFF# provides the fastest response among bus-hold inputs.
Either the system logic or another bus master can assert BOFF#
to gain control of the bus immediately. BOFF# is also used to
resolve potential deadlock problems that arise as a result of
inquire cycles. The processor samples BOFF# on every clock
e d g e . I f BO F F # i s s a m p l e d a s s e r t e d , t h e p r o c e s s o r
unconditionally aborts any cycles in progress and transitions to
a bus hold state. (See “BOFF# (Backoff)” on page 95.) Figure 73
on p a ge 169 sh ows a re a d cycle t h a t is a b or t e d wh e n t h e
p roce ssor sa m p le s BOF F # a sse r t e d eve n t h ou gh BR DY# is
sam pled asserted on t he same clock edge. The read cycle is
restarted after BOFF# is sampled negated (KEN# must be in
the same state during the restarted cycle as its state during the
aborted cycle).
During a BOFF#-initiated inquire cycle that hits a shared or
exclu sive lin e , t h e p roce ssor sa m p le s BOF F # n e ga t e d a n d
re st a r t s a ny b u s cycle t h a t wa s a b or t e d wh e n BOF F # wa s
asserted. If a BOFF#-initiated inquire cycle hits a modified line,
the processor performs a writeback cycle before it restarts the
aborted cycle.
If the processor samples BOFF# asserted on the same clock
edge that it asserts ADS#, ADS# is floated but the system logic
may erroneously interpret ADS# as asserted. In this case, the
system logic must properly interpret the state of ADS# when
BOFF# is negated.
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Read
Restart Read Cycle
Back Off Cycle
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
BOFF#
D[63:0]
BRDY#
Figure 73. BOFF# Timing
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Locked Cycles
The processor asserts LOCK# during a sequence of bus cycles to
en sure the cycles are completed without allowing other bus
masters to intervene. Locked operations can consist of two to
five cycles. LOCK# is asserted during the following operations:
■ An interrupt acknowledge sequence
■ Descriptor Table accesses
■ Page Directory and Page Table accesses
■ XCHG instruction
■ An instruction with an allowable LOCK prefix
In order to ensure that locked operations appear on the bus and
are visible to the entire system, any data operands addressed
during a locked cycle that reside in the processor’s caches are
flu shed an d invalidated from the caches prior to the locked
operation. If the cache line is in the modified state, it is written
back and invalidated prior to the locked operation. Likewise,
any da ta rea d during a locked operat ion is not cache d . The
p roce ssor n e ga t e s LOCK# for a t le a st on e clock b e t we e n
consecutive sequences of locked operations to allow the system
logic to arbitrate for the bus.
The processor asserts SCYC during misaligned locked transfers
on the D[63:0] data bus. The processor generates additional bus
cycles to complete the transfer of misaligned data.
Basic Locked
Operation
Figure 74 on page 171 shows a pair of read-write bus cycles. It
represents a typical read-modify-write locked operation. The
processor asserts LOCK# off the same clock edge that it asserts
ADS# of the first bus cycle in the locked operation and holds it
asserted until the last expected BRDY# of the last bus cycle in
t h e locke d op e ra t ion is sa m p le d a sse r t e d . (Th e p roce ssor
negates LOCK# off the same clock edge.)
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Locked Write Cycle
Locked Read Cycle
ADDR
IDLE IDLE
IDLE IDLE ADDR DATA DATA DATA
ADDR DATA DATA DATA
CLK
A[31:3]
BE[7:0]#
ADS#
LOCK#
M/IO#
D/C#
W/R#
SCYC
D[63:0]
BRDY#
Figure 74. Basic Locked Operation
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Locked Operation
with BOFF#
Intervention
Figure 75 on page 173 shows BOFF# asserted within a locked
read-write pair of bus cycles. In this example, the processor
asserts LOCK# with ADS# to drive a locked memory read cycle
followed by a locked memory write cycle. During the locked
me mory writ e cycle in t his exam ple , t he processor sam ple s
BOFF# asserted. The processor immediately aborts the locked
m e m ory wr it e cycle a n d floa t s a ll it s b u s-d r ivin g sign a ls,
including LOCK#. The system logic or another bus master can
initiate an inquire cycle or drive a new bus cycle one clock edge
after the clock edge on which BOFF# is sampled asserted. If the
system logic drives a BOFF#-initiated inquire cycle and hits a
modified line, the processor performs a writeback cycle before
it restarts the locked cycle (the processor asserts LOCK# during
the writeback cycle).
In Figure 75 on page 173, the processor immediately restarts
the aborted locked write cycle by driving the bus off the clock
ed ge on wh ich BOFF# is sampled negated. The system logic
m u st e n su r e t h e p r oce ssor r e su lt s for in t e r r u p t e d a n d
uninterrupted locked cycles are consistent. That is, the system
logic must guarantee the memory accessed by the processor is
not modified during the time another bus master controls the
bus.
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Locked Read Cycle
Restart Write Cycle
Aborted Write Cycle
CLK
A[31:3]
BE[7:0]#
ADS#
LOCK#
M/IO#
D/C#
W/R#
BOFF#
D[63:0]
BRDY#
Figure 75. Locked Operation with BOFF# Intervention
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Interrupt
Acknowledge
In response to recognizing the system ’s m askable interrupt
(INTR), the processor drives an interrupt acknowledge cycle at
t h e n e x t i n s t r u c t i o n b o u n d a r y. D u r i n g a n i n t e r r u p t
acknowledge cycle, the processor drives a locked pair of read
cycles as shown in Figure 76 on page 175. The first read cycle is
not functional, and the second read cycle returns the interrupt
number on D[7:0] (00h–FFh). Table 32 shows the state of the
signals during an interrupt acknowledge cycle.
Table 32. Interrupt Acknowledge Operation Definition
Processor Outputs
D/C#
First Bus Cycle
Low
Second Bus Cycle
Low
Low
M/IO#
Low
W/R#
Low
Low
BE[7:0]#
A[31:3]
EFh
FEh (low byte enabled)
0000_0000h
0000_0000h
Interrupt number expected from interrupt
controller on D[7:0]
D[63:0]
(ignored)
Th e syst e m logic ca n d r ive INTR e it h e r syn ch ron ou sly or
asyn ch ron ou sly. If it is asse rt e d a syn chron ou sly, it must b e
asserted for a minimum pulse width of two clocks. To ensure it
is recognized, INTR must remain asserted until an interrupt
acknowledge sequence is complete.
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Interrupt Acknowledge Cycles
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
LOCK#
INTR
Interrupt Number
D[63:0]
KEN#
BRDY#
Figure 76. Interrupt Acknowledge Operation
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6.6
Special Bus Cycles
The Mobile AMD-K6-2+ processor drives special bus cycles that
in clu d e st op gra n t , e n h a n ce d p owe r m a n a ge m e n t , flu sh
a ck n owle d ge , ca ch e wr it e b a ck in va lid a t ion , h a lt , ca ch e
invalidation, and shutdown cycles. During all special cycles,
D/C# = 0, M/IO# = 0, and W/R# = 1. BE[7:0]# and A[31:3] are
driven to differentiate among the special cycles, as shown in
Table 33. The system logic must return BRDY# in response to all
processor special cycles.
Table 33. Encodings For Special Bus Cycles
BE[7:0]#
A[4:3]*
Special Bus Cycle
Cause
FBh
10b
Stop Grant
STPCLK# sampled asserted
A dword access is made to the EPM
BFh
00b
EPM Stop Grant 16-byte I/O block and the GSBC bit of
the EPMR register is set to 1
EFh
F7h
00b
00b
00b
00b
00b
Flush Acknowledge
Writeback
Halt
FLUSH# sampled asserted
WBINVD instruction
HLT instruction
FBh
FDh
FEh
Flush
INVD,WBINVD instruction
Triple fault
Shutdown
Note:
*
A[31:5] = 0
Basic Special Bus
Cycle
Figure 77 on pa ge 177 shows a b asic special bus cycle . The
processor drives D/C# = 0, M/IO# = 0, and W/R# = 1 off the same
clock edge that it asserts ADS#. In this example, BE[7:0]# = FBh
and A[31:3] = 0000_0000h, which indicat es t hat t he special
cycle is a halt special cycle (See Table 33). A halt special cycle is
generated after the processor executes the HLT instruction.
If the processor samples FLUSH# asserted, it writes back any
L1 data cache and L2 cache lines that are in the modified state
and invalidates all lines in all caches. The processor then drives
a flush acknowledge special cycle.
If th e processor executes a WBINVD instruction, it drives a
wr it e b a ck sp e cia l cycle a ft e r t h e p r oce ssor com p le t e s
invalidating and writing back the cache lines.
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Halt Cycle
CLK
A[31:3]
BE[7:0]#
A[4:3] = 00b
FBh
ADS#
M/IO#
D/C#
W/R#
BRDY#
Figure 77. Basic Special Bus Cycle (Halt Cycle)
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Shutdown Cycle
In Figure 78, a shutdown (triple fault) occurs in the first half of
t h e wave for m , a n d a sh u t d own sp e cia l cycle follows in t h e
second half. The processor enters shutdown when an interrupt
or exception occurs during the handling of a double fault (INT
8), wh ich a m ou n t s t o a t r ip le fa u lt . Wh e n t h e p r oce ssor
encounters a triple fault, it stops its activity on the bus and
generates the shutdown special bus cycle (BE[7:0]# = FEh).
The system logic must assert NMI, INIT, RESET, or SMI# to get
the processor out of the shutdown state.
Shutdown Occurs
(Triple Fault)
Shutdown Special Cycle
CLK
A[4:3] = 00b
FEh
A[31:3]
BE[7:0]#
ADS#
LOCK#
M/IO#
D/C#
W/R#
D[63:0]
KEN#
BRDY#
Figure 78. Shutdown Cycle
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Stop Grant and Stop
Clock States
Figu re 79 and Figure 80 show the processor t ransit ion from
n orm a l execu t ion t o t h e St op Grant st at e , t h e n t o t h e St op
Clock state, back to the Stop Grant state, and finally back to
normal execution. The series of transitions begins when the
p r oce ssor sa m p le s STP CLK# a sse r t e d . On re cogn izin g a
STP CLK# in t e r r u p t a t t h e n e xt in st r u ct ion r e t ir e m e n t
boundary, the processor performs the following actions, in the
order shown:
1. Its instruction pipelines are flushed
2. All pending and in-progress bus cycle s are completed
3. The STPCLK# assertion is acknowledged by executing a
Stop Grant special bus cycle
4. Its internal clock is stopped after BRDY# of the Stop Grant
special bus cycle is sampled asserted (if EWBE# is masked
off, then entry into the Stop Grant state is not affected by
EWBE#) and after EWBE# is sampled asserted
5. The Stop Clock state is entered if the system logic stops the
bus clock CLK (optional)
STPCLK# is sampled as a level-sensitive input on every clock
edge but is not recognized until the next instruction boundary.
Th e syst e m logic d r ive s t h e sign a l e it h e r syn ch ron ou sly or
asyn ch ron ou sly. If it is asse rt e d a syn chron ou sly, it must b e
asserted for a minimum pulse width of two clocks. STPCLK#
must remain asserted until recognized, which is indicated by
the completion of the Stop Grant special cycle.
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Stop Clock
Stop Grant Special Cycle
STPCLK# Sampled Asserted
CLK
A[4:3] = 10b
FBh
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
CACHE#
STPCLK#
D[63:0]
KEN#
BRDY#
Figure 79. Stop Grant and Stop Clock Modes, Part 1
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Stop Clock
STPCLK# Sampled Negated Normal
Stop Grant State
(Re-entered after PLL stabilization)
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
CACHE#
STPCLK#
D[63:0]
KEN#
BRDY#
Figure 80. Stop Grant and Stop Clock Modes, Part 2
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INIT-Initiated
Transition from
Protected Mode to
Real Mode
INIT is typically asserted in response to a BIOS interrupt that
writes to an I/O port. This interrupt is often in response to a
Ctrl-Alt-Del keyboard input. The BIOS writes to a port (similar
to port 64h in the keyboard controller) that asserts INIT. INIT is
also used to support 80286 software that must return to Real
mode after accessing extended memory in Protected mode.
Th e a sse r t ion of INIT ca u se s t h e p r oce ssor t o e m p t y it s
pipelines, initialize most of its internal state, and branch to
address FFFF_FFF0h —the same instruction execution starting
point used after RESET. Unlike RESET, the processor preserves
the contents of its caches, the floating-point state, the MMX
state, Model-Specific Registers (MSRs), the CD and NW bits of
the CR0 register, the time stamp counter, and other specific
internal resources.
Figure 81 on page 183 shows an example in which the operating
system writes to an I/O port, causing the system logic to assert
INIT. Th e sa m p lin g of INIT a sse r t e d st a r t s a n e xt e n d e d
microcode sequence that terminates with a code fetch from
FFFF_FFF0h, the reset location. INIT is sampled on every clock
edge but is not recognized until the next instruction boundary.
Du r in g a n I/O wr it e cycle , it m u st b e sa m p le d a sse r t e d a
m in im u m of t h re e clock e d ge s b e fore BR DY# is sa m p le d
asserted if it is to be recognized on the boundary between the
I/O write instruction and the following instruction. If INIT is
asserted synchronously, it can be asserted for a minimum of one
clock . If it is a sse r t e d a syn ch ron ou sly, it m u st h ave b e e n
negated for a minimum of two clocks, followed by an assertion
of a minimum of two clocks.
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INIT Sampled Asserted
Code Fetch
FFFF_FFF0h
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
D[63:0]
KEN#
BRDY#
INIT
Figure 81. INIT-Initiated Transition from Protected Mode to Real Mode
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7
Power-on Configuration and Initialization
On power-on the system logic must reset the Mobile AMD-K6-2+
processor by asserting the RESET signal. When the processor
samples RESET asserted, it immediately flushes and initializes
a ll in t e r n a l re sou rce s a n d it s in t e r n a l st a t e , in clu d in g it s
pipelines and caches, the floating-point state, the MMX and
3DNow! states, and all registers. Then the processor jumps to
address FFFF_FFF0h to start instruction execution.
7.1
Signals Sampled During the Falling Transition of RESET
FLUSH#
F LU SH # is sa m p le d on t h e fa llin g t ra n sit ion of R E SE T t o
determine if the processor begins normal instruction execution
or enters Tri-State Test mode. If FLUSH# is High during the
falling transition of RESET, the processor unconditionally runs
it s Bu ilt -In Se lf Te st (BIST), p e r for m s t h e n or m a l re se t
fu n ct ion s, t h e n j u m p s t o a d d r e ss F F F F _F F F 0h t o st a r t
in st r u ct ion e xe cu t ion . (Se e “ Bu ilt -In Se lf-Te st (BIST)” on
page 239 for more details.) If FLUSH# is Low during the falling
transition of RESET, the processor enters Tri-State Test mode.
(See “Tri-State Test Mode” on page 240 and “FLUSH# (Cache
Flush)” on page 105 for more details.)
BF[2:0] Th e i n t e r n a l o p e r a t i n g f r e q u e n cy of t h e p r o c e s s o r i s
determined by the state of the bus frequency signals BF[2:0]
when they are sampled during the falling transition of RESET.
The frequency of the CLK input signal is multiplied internally
by a ratio defined by BF[2:0]. (See “BF[2:0] (Bus Frequency)”
on page 94 for the processor-clock to bus-clock ratios.)
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7.2
RESET Requirements
During the initial power-on reset of the processor, RESET must
remain asserted for a minimum of 1.0 ms after CLK and V
CC
reach specification. (See “CLK Switching Characteristics” on
page 279 for clock specifica tions. See “ Ele ct rical Dat a” on
page 275 for V specifications.)
CC
D u r i n g a wa r m r e s e t w h i l e C L K a n d V
a r e w i t h i n
C C
specification, RESET must remain asserted for a minimum of
15 clocks prior to its negation.
7.3
State of Processor After RESET
Output Signals
Ta b le 3 4 sh ows t h e st a t e o f a ll p r oc e sso r ou t p u t s a n d
b id ire ct ion a l sign a ls im m e d ia t e ly a ft e r R ESET is sa m p le d
asserted.
Table 34. Output Signal State After RESET
Signal
A[31:3], AP
State
Floating
High
Signal
State
High
Low
LOCK#
M/IO#
PCD
ADS#, ADSC#
APCHK#
BE[7:0]#
BREQ
High
Low
Floating
Low
PCHK#
PWT
High
Low
CACHE#
D/C#
High
SCYC
Low
Low
SMIACT#
TDO
High
Floating
Low
D[63:0], DP[7:0]
FERR#
Floating
High
VCC2DET
VCC2H/L#
VID[4:0]
W/R
HIT#
High
Low
HITM#
High
01010b
Low
HLDA
Low
Registers
Ta b le 35 on p a ge 187 sh ows t h e st a t e of a ll a rch it e ct u re
re gist e rs a n d Mod e l-Sp e cific R e gist e rs (MSR s) a ft e r t h e
processor has completed its initialization due to the recognition
of the assertion of RESET.
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Table 35. Register State After RESET
Register
State (hex)
Notes
GDTR
base:0000_0000h limit:0FFFFh
base:0000_0000h limit:0FFFFh
0000h
IDTR
TR
LDTR
0000h
EIP
FFFF_FFF0h
0000_0002h
0000_0000h
0000_0000h
0000_0000h
0000_059Xh
0000_0000h
0000_0000h
0000_0000h
0000_0000h
F000h
EFLAGS
EAX
1
2
EBX
ECX
EDX
ESI
EDI
EBP
ESP
CS
SS
0000h
DS
0000h
ES
0000h
FS
0000h
GS
0000h
FPU Stack R7–R0
FPU Control Word
FPU Status Word
FPU Tag Word
FPU Instruction Pointer
FPU Data Pointer
FPU Opcode Register
0000_0000_0000_0000_0000h
0040h
3
3
3
3
3
3
3
0000h
5555h
0000_0000_0000h
0000_0000_0000h
000_0000_0000b
Notes:
1. The contents of EAX indicate if BIST was successful. If EAX = 0000_0000h, BIST was successful.
If EAX is non-zero, BIST failed.
2. EDX contains the Mobile AMD-K6-2+ processor signature, where X indicates the processor
Stepping ID.
3. The contents of these registers are preserved following the recognition of INIT.
4. The CD and NW bits of CR0 are preserved following the recognition of INIT
5. “S” represents the Stepping. “B” represents PSOR[3:0], where PSOR[3] equals 0, and
PSOR[2:0] is equal to the value of the BF[2:0] signals sampled during the falling transition of
RESET.
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Table 35. Register State After RESET (continued)
Register
CR0
State (hex)
6000_0010h
Notes
4
CR2
0000_0000h
CR3
0000_0000h
CR4
0000_0000h
DR7
0000_0400h
DR6
FFFF_0FF0h
DR3
0000_0000h
DR2
0000_0000h
DR1
0000_0000h
DR0
0000_0000h
MCAR
MCTR
TR12
TSC
0000_0000_0000_0000h
0000_0000_0000_0000h
0000_0000_0000_0000h
0000_0000_0000_0000h
0000_0000_0000_0002h
0000_0000_0000_0000h
0000_0000_0000_0000h
0000_0000_0000_0000h
0000_0000_0000_01SBh
0000_0000_0000_0000h
0000_0000_0000_0000h
3
3
3
3
EFER
STAR
WHCR
UWCCR
PSOR
PFIR
EPMR
3
3
3
3
5
3,5
3
Notes:
1. The contents of EAX indicate if BIST was successful. If EAX = 0000_0000h, BIST was successful.
If EAX is non-zero, BIST failed.
2. EDX contains the Mobile AMD-K6-2+ processor signature, where X indicates the processor
Stepping ID.
3. The contents of these registers are preserved following the recognition of INIT.
4. The CD and NW bits of CR0 are preserved following the recognition of INIT
5. “S” represents the Stepping. “B” represents PSOR[3:0], where PSOR[3] equals 0, and
PSOR[2:0] is equal to the value of the BF[2:0] signals sampled during the falling transition of
RESET.
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7.4
State of Processor After INIT
The recognition of the assertion of INIT causes the processor to
empty its pipelines, to initialize most of its internal state, and to
b r a n ch t o a d d r e ss F F F F _F F F 0h —t h e sa m e in st r u ct ion
execution starting point used after RESET. Unlike RESET, the
processor preserves the contents of its caches, the floating-point
state, the MMX and 3DNow! states, MSRs, and the CD and NW
bits of the CR0 register.
The edge-sensitive interrupts FLUSH# and SMI# are sampled
a n d p re se r ve d d u r in g t h e INIT p r oce ss a n d a re h a n d le d
accordingly after the initialization is complete. However, the
processor resets any pending NMI interrupt upon sampling
INIT asserted.
INIT can be used as an accelerator for 80286 code that requires
a reset to exit from Protected mode back to Real mode.
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8
Cache Organization
Th e followin g sect ion s d e scr ib e t h e b a sic a rch it e ct u re a n d
resources of the Mobile AMD-K6-2+ processor internal caches.
Th e p e r for m a n ce of t h e Mob ile AMD-K6-2+ p roce ssor is
enhanced by writeback level-one (L1) and level-two (L2) caches.
The L1 cache is organized as separate 32-Kbyte instruction and
data caches, each with two-way set associativity. The L2 cache is
128 Kb yt e s, a n d is or ga n ize d a s a u n ifie d , fou r-way se t -
associative cache (See Figure 82 on page 192).
Th e ca ch e lin e size is 32 byt e s, a n d lin e s a re fe t ch e d from
external memory using an efficient pipelined burst transaction.
As the L1 instruction cache is filled from the L2 cache or from
e xt e r n a l m e m or y, e a ch in st r u ct ion b yt e is a n a lyze d for
instruct ion boundaries using predecode logic. Predecoding
annotates each instruction byte in the L1 instruction cache with
in for m a t ion t h a t la t e r e n ab le s t h e d e cod e rs t o e fficie n t ly
decode multiple instructions simultaneously.
Translation lookaside buffers (TLB) are used in conjunction
wit h t h e L1 cache t o t ra n sla t e lin ea r a dd re sse s t o p hysica l
a d d re sse s. Th e L1 in st r u ct ion ca ch e is a ssocia t e d wit h a
64-e n t ry TLB wh ile t h e L1 d a t a ca ch e is a ssocia t e d wit h a
128-entry TLB.
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32-Kbyte L1 Instruction Cache
State Tag
Tag
RAM
State
Bit
Way 0
Way 1
Bit RAM
64-Entry TLB
System Bus
Interface Unit
Processor
Core
Pre-Decode Instruction Cache
128-Entry TLB
MESI Tag
Tag
RAM
MESI
Bits
Way 0
Way 1
Bits RAM
32-Kbyte L1 Data Cache
Tag
RAM
MESI Tag
Bits RAM
MESI Tag
Bits RAM
MESI Tag
Bits RAM
MESI
Bits
Way 0
Way 1
Way 2
Way 3
128-Kbyte L2 Cache
Figure 82. L1 and L2 Cache Organization
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Th e p roce ssor ca ch e d e sign t a ke s a dva n t a ge of a se ct ore d
organization (See Figure 83). Each sector consists of 64 bytes
configured as two 32-byte cache lines. The two cache lines of a
sector share a common tag but have separate MESI (modified,
exclusive, shared, invalid) bits that track the state of each cache
line.
Note: L1 instruction-cache lines have only two coherency states
(valid or invalid) rather than the four MESI coherency
states of L1 data-cache and L2 cache lines. Only two states
are needed for the L1 instruction cache because these lines
are read-only.
L1 Instruction Cache Line
Tag
Address
Cache Line 0 Byte 31 Predecode Bits Byte 30 Predecode Bits ........ ........ Byte 0 Predecode Bits 1 MESI Bit
Cache Line 1 Byte 31 Predecode Bits Byte 30 Predecode Bits ........ ........ Byte 0 Predecode Bits 1 MESI Bit
L1 Data Cache Line and L2 Cache Line
Tag
Address
Cache Line 0 Byte 31
Cache Line 1 Byte 31
Byte 30
Byte 30
........
........
........
........
Byte 0
Byte 0
2 MESI Bits
2 MESI Bits
Figure 83. L1 Cache Sector Organization
8.1
MESI States in the L1 Data Cache and L2 Cache
The state of each line in the caches is tracked by the MESI bits.
The coherency of these states or MESI bits is maintained by
internal processor snoops and external inquire cycles by the
system logic. The following four states are defined for the L1
data cache and the L2 cache:
■ Modified—This line has been modified and is different from
external memory.
■ Exclusive—In general, an exclusive line in the L1 data cache
or the L2 cache is not modified and is the same as external
memory. The exception is the case where a line exists in the
modified state in the L1 data cache and also resides in the
L2 cache. By design, the line in the L2 cache must be in the
exclusive state.
■ Shared—If a cache line is in the shared state it means that
the same line can exist in more than one cache system.
■ Invalid—The information in this line is not valid.
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8.2
Predecode Bits
Decoding x86 instructions is particularly difficult because the
instructions vary in length, ranging from 1 to 15 bytes long.
Predecode logic supplies the predecode bits associated with
each instruction byte. The predecode bits indicate the number
of bytes to the start of the next x86 instruction. The predecode
bits are passed with the instruction bytes to the decoders where
t h e y a ssist wit h p a r a lle l x86 in st r u ct ion d e cod in g. Th e
p re d e cod e b it s u se m e m ory se p a ra t e from t h e 32-Kbyt e L1
instruction cache. The predecode bits are stored in an extended
L1 inst ru ction cache alongside each x86 instruction byt e as
shown in Figure 83 on page 193.
The L2 cache does not store predecode bits. As an instruction
cache line is fetched from the L2 cache, the predecode bits are
ge n e ra t e d a n d st ore d a lon gsid e t h e ca ch e lin e in t h e L1
instruction cache in the same manner as if the cache line were
fetched from the processor’s system bus.
8.3
Cache Operation
The operating modes for the caches are configured by software
using the not writethrough (NW) and cache disable (CD) bits of
control register 0 (CR0 bits 29 and 30, respectively). These bits
are used in all operating modes.
When the CD and NW bits are both set to 0, the cache is fully
enabled. This is the standard operating mode for the cache. If a
L1 cache read miss occurs, the processor determines if the read
hits the L2 cache, in which case the cache line is supplied from
the L2 cache to the L1 cache. If a read misses both the L1 and
the L2 caches, a line fill (32-byte burst read) on the system bus
occurs in order to fetch the cache line. The cache line is then
filled in both the L1 and the L2 caches. Write hits to the L1 and
L2 caches are updated, while write misses and writes to shared
line s ca use exte r na l memory upda te s. Refe r to Table 39 on
page 207 for a summary of cache read and write cycles and the
effect of these operations on the cache MESI state.
Note: A write allocate operation can modify the behavior of write
misses to the caches. See “Write Allocate” on page 201.
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The Mobile AMD-K6-2+ processor does not enforce any rules of
inclusion or exclusion as part of the protocol defined for the L1
and L2 caches. However, there are certain restrictions imposed
by design on t he allowable MESI stat es of a cache line that
exists in both the L1 cache and the L2 cache. Refer to Table 40
on page 212 for a list of the valid cache-line states allowed.
Wh en CD is se t t o 0 a n d NW is se t t o 1, a n inva lid m od e of
operation exists that causes a general protection fault to occur.
When CD is set to 1 (disabled) and NW is set to 0, the cache fill
mechanism is disabled but the contents of the cache are still
valid. The processor reads from the caches if the read hits the
L1 or t he L2 cache. If a read misses bot h t he L1 and t he L2
caches, a line fill does not occur on the system bus. Write hits to
the L1 or L2 cache are updated, while write misses and writes to
shared lines cause external memory updates. If PWT is driven
Low and WB/WT# is sampled High, a write hit to a shared line
changes the cache-line state to exclusive.
When the CD and NW bits are both set to 1, the cache is fully
disabled. Even though the cache is disabled, the contents are
not necessarily invalid. The processor reads from the caches if
the read hits the L1 or the L2 cache. If a read misses both the L1
and the L2 caches, a line fill does not occur on the system bus. If
a write hits the L1 or the L2 cache, the cache is updated but an
external memory update does not occur. If a cache line is in the
e xclu sive st a t e d u r in g a wr it e h it , t h e ca ch e -lin e st a t e is
changed to modified. Cache lines in the shared state remain in
the shared state after a write hit. Write misses access external
memory directly.
The operating system can control the cacheability of a page.
The paging mechanism is controlled by CR3, the Page Directory
Ent ry (PDE), and the Page Table Ent ry (P TE). Wit hin CR3,
P DE , a n d P TE a r e Pa ge Ca ch e Disa b le (P CD) a n d Pa ge
Writethrough (PWT) bits. The values of the PCD and PWT bits
used in Table 36 and Table 37 are taken from either the PTE or
PDE. For more information see the descriptions of PCD and
PWT on pages 115 and 117, respectively.
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Table 36 describes how the PWT signal is driven based on the
values of the PWT bits and the PG bit of CR0.
Table 36. PWT Signal Generation
PWT Bit*
PG Bit of CR0
PWT Signal
High
1
0
1
0
1
1
0
0
Low
Low
Low
Note:
* PWT is taken from PTE or PDE
Table 37 describes how the PCD signal is driven based on the
values of the CD bit of CR0, the PCD bits, and the PG bit of
CR0.
Table 37. PCD Signal Generation
CD Bit of CR0
PCD Bit*
PG Bit of CR0
PCD Signal
High
1
X
1
0
1
0
X
1
1
0
0
0
High
0
Low
0
0
Low
Low
Note:
* PCD is taken from PTE or PDE
Table 38 describes how the CACHE# signal is driven based on
t h e cycle t ype , t he CI bit of TR12, the P CD signal, and t he
UWCCR model-specific register.
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Table 38. CACHE# Signal Generation
Access Within
CACHE#
Cycle Type
CI Bit of TR12
PCD Signal
WC/UC Range*
Writebacks
Unlocked Reads
X
0
X
0
X
0
Low
Low
High
High
High
High
High
Locked Reads
X
X
1
X
X
X
1
X
X
X
X
1
Single Writes
Any Cycle Except Writebacks
Any Cycle Except Writebacks
Any Cycle Except Writebacks
X
X
X
Note:
* WC and UC refer to Write-Combining and Uncacheable Memory Ranges as defined in the UWCCR.
Cache-Related Signals
Complete descriptions of the signals that control cacheability
and cache coherency are given on the following pages:
■ CACHE#—page 98
■ EADS#—page 102
■ FLUSH#—page 105
■ HIT#—page 106
■ HITM#—page 106
■ INV—page 110
■ KEN#—page 111
■ PCD—page 115
■ PWT—page 117
■ WB/WT#—page 125
8.4
Cache Disabling and Flushing
L1 and L2 Cache
Disabling
To completely disable all accesses to the L1 and the L2 caches,
the CD bit must be set to 1 and the caches must be completely
flushed.
There are three different methods for flushing the caches. The
first m e t h od re lie s on t h e syst e m logic a n d t h e ot h e r t wo
methods rely on software.
For the system logic to flush the caches, the processor must
sample FLUSH# asserted. In this method, the processor writes
b a ck a ny L1 d a t a ca ch e a n d L2 ca ch e lin e s t h a t a re in t h e
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m od ifie d st a te , inva lida te s a ll line s in a ll cache s, a n d t h e n
executes a flush acknowledge special cycle (See Table 24 on
page 129).
The second method for flushing the caches is for software to
execut e t he WBINVD instruction which causes all modified
lines to first be written back to memory, then marks all cache
lines as invalid. Alternatively, if writing modified lines back to
memory is not necessary, the INVD instruction can be used to
invalidate all cache lines.
The third and final method for flushing the caches is to make
use of the Page Flush/Invalidate Register (PFIR), which allows
cache invalidation and optional flushing of a specific 4-Kbyte
page from the linear address space (see “PFIR” on page 210).
Unlike the previous two methods of flushing the caches, this
particular method requires the software to be aware of which
specific pages must be flushed and invalidated.
L2 Cache Disabling
Th e L2 ca ch e in t h e Mob ile AMD-K6-2+ p roce ssor ca n b e
com p le t e ly d isa b le d by se t t in g t h e L2 Disa b le (L2D) b it
(E F E R [4]) t o 1 (se e “ E xt e n d e d Fe a t u re E n a b le R e gist e r
(EFER)” on page 39). If disabled in this manner, the processor
d oe s n ot a cce ss t h e L2 ca ch e for a ny p u rp ose , in clu d in g
a lloca t ion s, re a d h it s, wr it e h it s, sn oop s, in q u ire cycle s,
flushing, and read/write attempts by means of the L2AAR. (See
“L2 Cache and Tag Array Testing” on page 198.) The L1 cache
operation is not affected by disabling the L2 cache.
The L2D bit is provided for debug and testing purposes only. For
normal operation and maximum performance, this bit must be
set to 0, which is the default setting following reset.
The Mobile AMD-K6-2+ processor does not provide a method
for disabling the L1 cache while the L2 cache remains enabled.
8.5
L2 Cache and Tag Array Testing
The Mobile AMD-K6-2+ processor provides the L2AAR MSR
that allows for direct access to the L2 cache and L2 tag arrays.
For more de ta ile d informa tion, re fe r to “ L2 Ca che a nd Tag
Array Testing” on page 253.
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8.6
Cache-Line Fills
The processor performs a cache-line fill for any area of system
memory defined as cacheable. If an area of system memory is
not explicitly defined as uncacheable by the software or system
logic, or implicitly treated as uncacheable by the processor,
then the memory access is assumed to be cacheable.
Software can prevent caching of certain pages by setting the
PCD bit in the PDE or PTE. Additionally, software can define
re gion s of m e m ory a s u n ca ch e ab le or wr it e com bin ab le by
programming the MTRRs in the UWCCR MSR (see “Memory
Typ e R a n ge R e gist e r s” on p a ge 219). Wr it e -com b in a b le
memory is defined as uncacheable.
Th e syste m logic a lso has control of the cache ability of bus
cycles. If it determines the address is not cacheable, system
logic negates the KEN# signal when asserting the first BRDY#
or NA# of a cycle.
The processor does not cache certain memory accesses such as
locked operations. In addition, the processor does not cache
PDE or PTE memory reads in the L1 cache (referred to as page
table walks). However, page table walks are cached in the L2
cache if the PDE or PTE is determined to be cacheable.
When the processor needs to read memory, the processor drives
a read cycle onto the bus. If the cycle is cacheable, the processor
a sse rt s CACHE #. If t h e cycle is n ot ca che able , a non-burst ,
single-transfer read takes place. The processor waits for the
system logic to return the data and assert a single BRDY# (See
Figure 60 on page 145). If the cycle is cacheable, the processor
executes a 32-byte burst read cycle. The processor expects a
total of four BRDY# signals for a burst read cycle to take place
(See Figure 62 on page 149).
Cache-line fills initiate 32-byte burst read cycles from memory
on the system bus for the L1 instruction cache and the L1 data
cache. All L1 cache-line fills supplied from the system bus are
also filled in the L2 cache.
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8.7
Cache-Line Replacements
As programs execute and task switches occur, some cache lines
eventually require replacement.
When a cache miss occurs in the L1 cache, the required cache
lin e is fille d from e it h e r t h e L2 ca ch e , if t h e ca ch e lin e is
present (L2 cache hit), or from external memory, if the cache
line is not present (L2 cache miss). If the cache line is filled
from external memory, the cache line is filled in both the L1 and
the L2 caches.
Two forms of cache misses and associated cache fills can take
place —a tag-miss cache fill and a tag-hit cache fill. In the case
of a tag-miss cache fill, the level-one cache miss is due to a tag
mismatch, in which case the required cache line is filled either
from t h e level-two cache or from ext ernal me mory, and t he
level-one cache line within the sector that was not required is
marked as invalid. In the case of a tag-hit cache fill, the address
ma tche s t h e t ag, but t he request ed ca che line is m arke d a s
invalid. The require d leve l-one ca che line is fille d from the
level-t wo cache or from externa l m emory, a nd the level-one
cache line within the sector that is not required remains in the
same cache state.
If a L1 data-cache line being filled replaces a modified line, the
modified line is written back to the L2 cache if the cache line is
p re se n t (L2 ca ch e h it ). By d e sign , if a ca ch e lin e is in t h e
modified state in the L1 cache, this cache line can only exist in
the L2 cache in the exclusive state. During the writeback, the
L2 cache-line state is changed from exclusive to modified, and
t h e wr it e b a ck d oe s n ot occu r on t h e syst e m b u s. If t h e
replacement writeback does not hit t he L2 cache (L2 cache
miss), then the modified L1 cache line is written back on the
system bus, and the L2 cache is not updated. If the other cache
line in this sector is in the modified state, it is also written back
in the same manner.
L1 instruction-cache lines and L2 cache lines are replaced using
a Least Recently Used (LRU) algorithm. If a line replacement is
required, lines are replaced when read cache misses occur.
The L1 data cache uses a slightly different approach to line
replacement. If a miss occurs, and a replacement is required,
lines are replaced by using a Least Recently Allocated (LRA)
algorithm.
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8.8
Write Allocate
Writ e allocate , if enable d, occurs when t he proce ssor has a
pending memory write cycle to a cacheable line and the line
does not currently reside in the L1 data cache. If the line does
not exist in the L2 cache, the processor performs a 32-byte burst
re a d cycle on t h e syst e m b u s t o fe t ch t h e d a t a -ca ch e lin e
addressed by the pending write cycle. If the line does exist in
the L2 cache, the data is supplied directly from the L2 cache, in
wh ich ca se a syst e m b u s cycle is n ot e xe cu t e d . Th e d a t a
associate d wit h the pending writ e cycle is merged wit h t he
recently-allocated data-cache line and stored in the processor’s
L1 data cache. If the data-cache line was fetched from memory
(b e ca u se of a L2 ca ch e m iss), t h e d a t a is st ore d , wit h ou t
modification, in the L2 cache. The final MESI state of the cache
lines depends on the st ate of t he WB/WT# and PWT signals
during the burst read cycle and the subsequent L1 data cache
write hit (See Table 39 on page 207 to determine the cache-line
states and the access types following a cache write miss). If the
L1 data cache line is stored in the modified state, then the same
cache line is stored in the L2 cache in the exclusive state. If the
L1 data cache line is stored in the shared state, then the same
cache line is stored in the L2 cache in the shared state.
If a data-cache line fetch from memory is attempted because
the write allocate misses the L2 cache, and KEN# is sampled
negated, the processor does not perform an allocation. In this
case, the pending write cycle is executed as a single write cycle
on the system bus.
During write allocates that miss the L2 cache, a 32-byte burst
read cycle is executed in place of a non-burst write cycle. While
the burst read cycle generally takes longer to execute than the
n on -b u rst wr it e cycle , p e r for m a n ce ga in s a re re a lize d on
subsequent write cycle hits to the write-allocated cache line.
Due to the nature of software, memory accesses tend to occur in
proximity of each other (principle of locality). The likelihood of
additional write hits to the write-allocated cache line is high.
Write allocates that hit the L2 cache increase performance by
avoiding accesses to the system bus.
The following is a description of three mechanisms by which the
Mobile AMD-K6-2+ processor performs writ e allocations. A
writ e a llocat e is p er for me d wh en a ny on e or m ore of the se
mechanisms indicates that a pending write is to a cacheable
area of memory.
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Write to a Cacheable
Page
Every time the processor completes a L1 cache line fill, the
address of the page in which the cache line resides is saved in
the Cacheability Control Register (CCR). The page address of
subsequent writ e cycles is com pared with the page address
st ore d in t he CCR . If t he two addresse s are equal, t he n t he
p roce ssor p e r for m s a wr it e a lloca t e b e ca u se t h e p a ge h a s
already been determined to be cacheable.
Wh e n t h e p roce ssor p e r for m s a L1 ca ch e lin e fill from a
different page than the address saved in the CCR, the CCR is
updated with the new page address.
Write to a Sector
If the address of a pending write cycle matches the tag address
of a valid L1 cache sector, but the addressed cache line within
the sector is marked invalid (a sector hit but a cache line miss),
then the processor performs a write allocate. The pending write
cycle is d e t e r m in e d t o b e ca che ab le b e ca u se t h e se ct or h it
indicates the presence of at least one valid cache line in the
sector. The two cache lines within a sector are guaranteed by
design to be within the same page.
Write Allocate Limit
The Mobile AMD-K6-2+ processor uses two mechanisms that are
programmable within the Write H andling Control Re giste r
(WH CR ) t o e n a b le wr it e a lloca t ion s for wr it e cycle s t h a t
address a definable area, or a special 1-Mbyte memory area.
Th e WHCR contains t wo fields —t he Writ e Allocat e Enable
Lim it (WAE LIM) fie ld , a n d t h e Wr it e Alloca t e E n a b le
15-to-16-Mbyte (WAE15M) bit (see Figure 84).
63
32 31
22 21 17 16 15
0
W
A
E
WAELIM
1
5
M
Reserved
Symbol
Description
Bits
WAELIM
Write Allocate Enable Limit
31-22
WAE15M Write Allocate Enable 15-to-16-Mbyte 16
Note: Hardware RESET initializes this MSR to all zeros.
Figure 84. Write Handling Control Register (WHCR)
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Write Allocate Enable Limit. The WAELIM field is 10 bits wide. This
field, multiplied by 4 Mbytes, defines an upper memory limit.
Any p e n d in g writ e cycle t h at m isses t h e L1 ca che and t h a t
a dd resse s m em ory b e low t h is lim it ca u se s t h e p roce ssor t o
perform a write allocate (assuming the address is not within a
range where write allocates are disallowed). Write allocate is
disabled for memory accesses at and above this limit unless the
processor determines a pending write cycle is cacheable by
means of one of the other write allocate mechanisms —“Write
to a Cacheable Page” and “Write to a Sector.” The maximum
10
value of this limit is ((2 –1) · 4 Mbytes) = 4092 Mbytes. When
all the bits in this field are set to 0, all memory is above this
limit a nd write a lloca tes due to this mecha nism is disable d
(even if all bits in the WAELIM field are set to 0, write allocates
ca n still occur due to the “ Wr ite to a Ca che able Page” a nd
“Write to a Sector” mechanisms).
Write Allocate Enable 15-to-16-Mbyte. Th e Wr it e Allo ca t e E n a b le
1 5 -t o -1 6 -M b y t e ( WA E 1 5 M ) b i t i s u s e d t o e n a b l e w r i t e
allocations for memory write cycles that address the 1 Mbyte of
memory between 15 Mbytes and 16 Mbytes. This bit must be set
t o 1 t o a llow writ e a lloca t e in t his me mory a re a. This bit is
p r ovid e d t o a cc ou n t for a sm a l l n u m b e r of u n com m on
memory-mapped I/O adapters that use this particular memory
address space. If the system contains one of these peripherals,
the bit should be set to 0 (even if the WAE15M bit is set to 0,
wr it e a lloca t e s ca n st ill occu r b e t we e n 15 Mbyt e s a n d 16
Mbytes due to the “Write to a Cacheable Page” and “Write to a
Sector” mechanisms). The WAE15M bit is ignored if the value
in the WAELIM field is set to less than 16 Mbytes.
By definition a write allocate is not performed in the memory
area bet wee n 640 Kbyt es and 1 Mbyte unless the processor
determines a pending write cycle is cacheable by means of one
of the other write allocate mechanisms—“Write to a Cacheable
Pa ge ” a n d “ Wr it e t o a Se ct or.” It is n ot con sid e re d sa fe t o
perform write allocat ions bet ween 640 Kbyt es and 1 Mbyte
(000A_0000h t o 000F _F F F F h ) b e ca u se it is con sid e re d a
noncacheable region of memory.
If a m e m or y r e g ion is d e fin e d a s wr it e c o m b in a b le or
uncacheable by a MTRR, write allocates are not performed in
that region.
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Write Allocate Logic
Mechanisms and
Conditions
Figure 85 shows the logic flow for all the mechanisms involved
with write allocate for memory bus cycles. The left side of the
diagram (the text) describes the conditions that need to be true
in order for the value of that line to be a 1. Items 1 to 4 of the
diagram are related to general cache operation and items 5 to
10 are related to the write allocate mechanisms.
Fo r m o r e i n fo r m a t i o n a b o u t w r i t e a l l o c a t e , s e e t h e
Im plem en t a t ion of W r it e Alloca t e in t h e K86™ Pr ocessor s
Application Note, order# 21326.
Perform
Write Allocate
1) CD Bit of CR0
2) PCD Signal
3) CI Bit of TR12
4) UC or WC
5) Write to Cacheable Page (CCR)
6) Write to a Sector
7) Less Than Limit (WAELIM)
8) Between 640 Kbytes and 1 Mbyte
9) Between 15–16 Mbytes
10) Write Allocate Enable 15–16 Mbyte (WAE15M)
Figure 85. Write Allocate Logic Mechanisms and Conditions
The following list describes the corresponding items in Figure
85:
1. CD Bit of CR0—When the cache disable (CD) bit within
control register 0 (CR0) is set to 1, the cache fill mechanism
for both reads and writes is disabled and write allocate does
not occur.
2. PCD Signal—When the PCD (page cache disable) signal is
driven High, caching for that page is disabled, even if KEN#
is sampled asserted, and write allocate does not occur.
3. CI Bit of TR12—When the cache inhibit bit of Test Register
12 is set to 1, L1 and L2 cache fills are disabled and write
allocate does not occur.
4. UC or WC—If a pending write cycle addresses a region of
memory defined as write combinable or uncacheable by an
MTRR, write allocates are not performed in that region.
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5. Write to a Cacheable Page (CCR)—A write allocate is
performed if the processor knows that a page is cacheable.
The CCR is used to store the page address of the last L1
cache fill for a read miss. See “Write to a Cacheable Page”
on page 202 for a detailed description of this condition.
6. Write to a Sector —A write allocate is performed if the
address of a pending write cycle matches the tag address of a
valid L1 cache sector but the addressed cache line within the
sector is invalid. See “Write to a Sector” on page 202 for a
detailed description of this condition.
7. Less Than Limit (WAELIM)—The write allocate limit
mechanism determines if the memory area being addressed
is less than the limit set in the WAELIM field of WHCR. If
the address is less than the limit, write allocate for that
memory address is performed as long as conditions 8
through 10 do not prevent write allocate (even if conditions
8 and 10 attempt to prevent write allocate, condition 5 or 6
allows write allocate to occur).
8. Between 640 Kbytes and 1 Mbyte—Write allocate is not
performed in the memory area between 640 Kbytes and 1
Mbyte. It is not considered safe to perform write allocations
between 640 Kbytes and 1 Mbyte (000A_0000h to
000F_FFFFh) because this area of memory is considered a
noncacheable region of memory (even if condition 8
attempts to prevent write allocate, condition 5 or 6 allows
write allocate to occur).
9. Between 15–16 Mbytes—If the address of a pending write
cycle is in the 1 Mbyte of memory between 15 Mbytes and 16
Mbytes, and the WAE15M bit is set to 1, write allocate for
this cycle is enabled.
10. Write Allocate Enable 15–16 Mbytes (WAE15M)—This
condition is associated with the Write Allocate Limit
mechanism and affects write allocate only if the limit
specified by the WAELIM field is greater than or equal to
16 Mbytes. If the memory address is between 15 Mbytes and
16 Mbytes, and the WAE15M bit in the WHCR is set to 0,
write allocate for this cycle is disabled (even if condition 10
attempts to prevent write allocate, condition 5 or 6 allows
write allocate to occur).
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8.9
Prefetching
Hardware
Prefetching
The Mobile AMD-K6-2+ processor conditionally performs cache
prefetching which results in the filling of the required cache
line first, and a prefetch of the second cache line making up the
other half of the sector. From the perspective of the external
bus, the two cache-line fills t ypically appear a s two 32-byte
b u rst re a d cycle s occu r r in g b a ck -t o-b a ck or, if a llowe d , a s
p i p e l i n e d cy c l e s . Th e b u r s t r e a d cy c l e s d o n o t o c c u r
back-to-back (wait states occur) if the processor is not ready to
start a new cycle, if higher priority data read or write requests
exist, or if NA# (next address) was sampled negated. Wait states
can also exist between burst cycles if the processor samples
AHOLD or BOFF# asserted.
Software Prefetching
Th e 3DNow! t e ch n ology in clu d e s a n in st r u ct ion ca lle d
PREFETCH that allows a cache line to be prefetched into the
L1 d at a ca che a n d t h e L2 cache . U n like p re fe t ching u n d e r
hardware control, software prefetching only fetches the cache
line specified by the operand of the PREFETCH instruction,
and does not attempt to fetch the other cache line in the sector.
Th e P R EF E TCH in st r u ct ion for m a t is d e fin e d in Tab le 15,
“3DNow!™ Te ch n ology In str u ct ion s,” on p age 83. For more
detailed in format ion, see t he 3DNow!™ Technology Manua l,
order# 21928.
8.10
Cache States
Table 39 on page 207 shows all the possible cache-line states
b e fore a n d a ft e r p rogra m -ge n e ra t ed a cce sse s t o in d ivid u a l
cache lines.
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Table 39. L1 and L2 Cache States for Read and Write Accesses
Cache State
Cache State
After Access
4
Access
Before Access
Type
1
Type
MESI State
L1
I
L2
I
L1
L2
single read from bus
I
I
Read Miss L1,
Read Miss L2
2
3
3
I
I
burst read from bus, fill L1 and L2 S or E S or E
E
S
M
I
–
–
E
S
–
–
–
E
S
E
Read Hit L1
–
–
Cache
Read
–
–
M
E
E
S
M
M
fill L1
fill L1
fill L1
fill L1
I
S
Read Miss L1,
Read Hit L2
I
M
9
9
I
E
M
Notes:
1. The final MESI state assumes that the state of the WB/WT# signal remains the same for all accesses to a
particular cache line.
2. If CACHE# is driven Low and KEN# is sampled asserted.
3. If PWT is driven Low and WB/WT# is sampled High, the line is cached in the exclusive (writeback) state. If
PWT is driven High or WB/WT# is sampled Low, the line is cached in the shared (writethrough) state.
4. M = Modified, E = Exclusive, S = Shared, I = Invalid. The exclusive and shared states are indistinguishable
in the L1 instruction cache and are treated as “valid” states.
5. Assumes the write allocate conditions as specified in “Write Allocate” on page 201 are not met.
6. Assumes the write allocate conditions as specified in “Write Allocate” on page 201 are met.
7. Assumes PWT is driven Low and WB/WT# is sampled High.
8. Assumes PWT is driven High or WB/WT# is sampled Low.
9. This entry only applies to the L1 instruction cache. By design, a cache line cannot exist in the exclusive state
in the L1 data cache and in the modified state in the L2 cache.
–
Not applicable or none.
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Table 39. L1 and L2 Cache States for Read and Write Accesses (continued)
Cache State
After Access
Cache State
4
Access
Type
Before Access
Type
1
MESI State
L1
L2
L1
L2
5
I
I
I
I
single write to bus
burst read from bus, fill L1 and L2,
7
7
I
I
I
I
M
E
6
Write Miss L1
Write Miss L2
write to L1
burst read from bus, fill L1 and L2,
write to L1 and L2, single write to
8
8
S
S
6
bus
write to L1,
single write to bus
3
S
S
I
I
S or E
Write Hit L1
write to L1 and L2,
single write to bus
3
3
Cache
Write
S
S or E S or E
E or M
–
E
write to L1
M
I
–
5
I
I
I
I
I
I
M
write to L2
5
3
S
I
write to L2, single write to bus
S or E
M
5
M
E
I
Write Miss L1
Write Hit L2
write to L2
6
M
E
fill L1, write to L1
6
3
3
S
write to L2, single write to bus
S or E S or E
6
M
M
E
fill L1, write to L1
Notes:
1. The final MESI state assumes that the state of the WB/WT# signal remains the same for all accesses to a
particular cache line.
2. If CACHE# is driven Low and KEN# is sampled asserted.
3. If PWT is driven Low and WB/WT# is sampled High, the line is cached in the exclusive (writeback) state. If
PWT is driven High or WB/WT# is sampled Low, the line is cached in the shared (writethrough) state.
4. M = Modified, E = Exclusive, S = Shared, I = Invalid. The exclusive and shared states are indistinguishable
in the L1 instruction cache and are treated as “valid” states.
5. Assumes the write allocate conditions as specified in “Write Allocate” on page 201 are not met.
6. Assumes the write allocate conditions as specified in “Write Allocate” on page 201 are met.
7. Assumes PWT is driven Low and WB/WT# is sampled High.
8. Assumes PWT is driven High or WB/WT# is sampled Low.
9. This entry only applies to the L1 instruction cache. By design, a cache line cannot exist in the exclusive state
in the L1 data cache and in the modified state in the L2 cache.
–
Not applicable or none.
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8.11
Cache Coherency
Different ways exist to maintain coherency between the system
memory and cache memories. Inquire cycles, internal snoops,
FLUSH#, WBINVD, INVD, and line replacements all prevent
inconsistencies between memories.
Inquire Cycles
Inquire cycles are bus cycles initiated by system logic which
ensure coherency between t he caches and m ain memory. In
syst em s wit h mult iple b u s m ast e rs, syst em logic m a in t a in s
ca ch e cohe rency by driving inquire cycle s to the proce ssor.
Syst e m logic in it ia t e s inq uire cycle s by a sse r t in g AH OLD,
BOFF#, or HOLD to obtain control of the address bus and then
d r ivin g E ADS#, INV (op t ion a l), a n d a n in q u ire a d d re ss
(A[31:5]). Th is t yp e of b u s cycle ca u se s t h e p roce ssor t o
compare the tags for its L1 instruction and L1 data caches, and
L2 cache, with the inquire address. If there is a hit to a shared or
exclusive line in the L1 data cache or the L2 cache, or a valid
line in the L1 instruction cache, the processor asserts HIT#. If
the compare hits a modified line in the L1 data cache or the L2
ca ch e , t h e p roce ssor a sse r t s H IT# a n d H ITM#. If H ITM# is
a sse r t e d , t h e p roce ssor wr it e s t h e m od ifie d lin e b a ck t o
m e m ory. If INV wa s sa m p le d a sse r t e d wit h E ADS#, a h it
invalidates the line. If INV was sampled negated with EADS#, a
hit leaves the line in the shared state or transitions it from the
exclusive or modified state to the shared state.
Table 40 on page 212 lists valid combinations of MESI states
permitted for a cache line in the L1 and L2 caches, and shows
the effects of inquire cycles performed wit h INV equal to 0
(non-invalidating) and INV equal to 1 (invalidating).
Internal Snooping
Int ern al snooping is initiat ed by the processor (rather than
syst e m logic) d u r in g ce r t a in ca ch e a cce sse s. It is u se d t o
maintain coherency between the L1 instruction cache and the
L1 data cache.
The processor automatically snoops its L1 instruction cache
during read or write misses to its L1 data cache, and it snoops
its L1 data cache during read misses to its L1 instruction cache.
The L2 cache is not snooped during misses to either of the L1
ca ch es. Table 41 on page 213 summarizes the a ct ions take n
during this internal snooping.
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If a n in t e r n a l sn oop h it s it s t a rge t , t he p roce ssor d oe s t h e
following:
■ L1 data cache snoop during a L1 instruction-cache read miss—
If modified, the line in the L1 data cache is written back. If
the writeback hits the L2 cache, the cache line is stored in
the L2 cache in the modified state and no writeback occurs
on the system bus. If the writeback misses the L2 cache, the
cache line is written back on the system bus to external
memory. Regardless of its state, the L1 data-cache line is
invalidated and the L1 instruction cache performs a read
from either the L2 cache (if a L2 hit occurs) or external
memory (if a L2 miss occurs).
■ L1 instruction cache snoop during a L1 data cache miss—The
line in the instruction cache is marked invalid, and the L1
data-cache read or write is performed as defined in Table 39
on page 207.
FLUSH#
PFIR
In response to sampling FLUSH# asserted, the processor writes
back any L1 data cache lines and L2 cache lines that are in the
modified state and then marks all lines in the L1 instruction
cache, the L1 data cache, and the L2 cache as invalid.
Th e M o b i l e A M D -K 6 -2 + p r o c e s s o r c o n t a i n s t h e P a g e
Flush/Invalidate Register (PFIR) that allows cache invalidation
and optional flushing of a specific 4-Kbyte page from the linear
add re ss sp ace (se e Figure 86). Whe n the P FIR is writ te n to
(u sin g t h e WR MSR in st r u ct i on ), t h e in va li d a t ion a n d ,
optionally, the flushing begins. The total amount of cache in the
Mobile AMD-K6-2+ processor is 320 Kbytes. Using this register
can result in a much lower cycle count for flushing particular
pages versus flushing the entire cache.
63
32 31
12 11 9 8 7
1
0
F
/
I
P
F
LINPAGE
Reserved
Description
Symbol
LINPAGE 20-bit Linear Page Address
PF
F/I
Bit
31-12
8
Page Fault Occurred
Flush/Invalidate Command
0
Figure 86. Page Flush/Invalidate Register (PFIR)—MSR C000_0088h
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LINPAGE. This 20-bit field must be written with bits 31:12 of the
linear address of the 4-Kbyte page that is to be invalidated and
optionally flushed from the L1 or the L2 cache.
PF. If an attempt to invalidate or flush a page results in a page
fault, the processor sets the PF bit to 1, and the invalidate or
flu sh op e ra t ion is n ot p e r for m e d (eve n t h ou gh inva lid a t e
operations do not normally generate page faults). In this case,
an actual page fault exception is not generated. If the PF bit
e q u a ls 0 a ft e r a n inva lid a t e or flu sh op e ra t ion , t h e n t h e
operation executed successfully. The PF bit must be read after
every write to the PFIR register to determine if the invalidate
or flush operation executed successfully.
F/I. This bit is used to control the type of action that occurs to
t h e sp e cifie d lin e a r p a ge . If a 0 is wr it t e n t o t h is b it , t h e
operation is a flush, in which case all cache lines in the modified
state within the specified page are written back to memory,
after which the entire page is invalidated. If a 1 is written to
t h is b it , t h e ope ra t ion is a n inva lid a t ion, in which ca se t he
e n t ire p a ge is inva lid a t e d wit h ou t t h e occu r re n ce of a ny
writebacks.
WBINVD and INVD
These x86 instructions cause all cache lines to be marked as
invalid. WBINVD writes back modified lines before marking all
cache lines invalid. INVD does not write back modified lines.
Cache-Line
Replacement
Replacing lines in the L1 cache and the L2 cache, according to
t h e lin e re p la cem en t a lgor it h m s d e scrib e d in “ Ca ch e-Lin e
Fills” on p a ge 199, e n su re s coh e re n cy b e t we e n e xt e r n a l
memory and the caches.
Table 41 on page 213 shows all possible cache-line states before
and after various cache-related operations.
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Table 40. Valid L1 and L2 Cache States and Effect of Inquire Cycles
Cache State After Inquire
INV = 0 INV = 1
Cache State
1
2
Before Inquire
Memory Access
L1
I
L2
M
E
S
L1
I
L2
S
S
S
I
L1
I
L2
I
writeback L2 to bus
I
–
I
I
I
I
–
I
I
I
I
I
–
I
I
I
3
3
writeback L2 to bus
S
S
S
S
S
S
S
S
S
I
I
I
E
M
E
E
E
I
–
I
I
–
I
I
M
M
S
E
I
writeback L1 to bus
I
I
I
writeback L1 to bus
I
I
I
S
I
–
–
S
I
I
I
S
I
I
Notes:
1. M = Modified, E = Exclusive, S = Shared, I = Invalid. The exclusive and shared states are
indistinguishable in the L1 instruction cache and are treated as “valid” states.
2. Writeback cycles to the bus are 32-byte burst writes.
3. This entry only applies to the L1 instruction cache. By design, a cache line cannot exist in the
exclusive state in the L1 data cache and in the modified state in the L2 cache.
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Table 41. L1 and L2 Cache States for Snoops, Flushes, and Invalidation
Cache State
Cache State After
Operation
1
2
Before Operation
Type of Operation
Access Type
L1
I
L2
M
E
S
L1
I
L2
M
E
S
I
–
–
–
–
–
–
–
I
I
I
I
I
I
I
3
3
I
M
E
I
E
M
Internal Snoop
E
E
E
I
I
I
M
M
S
E
I
writeback L1 to L2
I
M
I
writeback L1 to bus
I
S
I
–
I
S
I
S
–
I
S or E
S or E
–
I
I
FLUSH#
Signal
M
–
–
writeback L1 to bus
writeback L2 to bus
–
I
I
M
I
I
I
I
PFIR
(F/I = 0)
M
–
–
writeback L1 to bus
writeback L2 to bus
I
I
M
I
I
PFIR
(F/I = 1)
–
–
–
I
I
S or E
–
I
I
I
I
I
I
WBINVD
Instruction
M
–
–
writeback L1 to bus
writeback L2 to bus
M
INVD
Instruction
–
–
–
I
I
Notes:
1. M = Modified, E = Exclusive, S = Shared, I = Invalid. The exclusive and shared states are indistinguishable in the
L1 instruction cache and are treated as “valid” states.
2. Writeback cycles to the bus are 32-byte burst writes.
3. This entry only applies to the L1 instruction cache. By design, a cache line cannot exist in the exclusive state in the
L1 data cache and in the modified state in the L2 cache.
– Not applicable or none.
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8.12
Writethrough versus Writeback Coherency States
Th e t e rm s writ et h rou gh a nd writ eba ck a p p ly t o t wo relat e d
con ce p t s in a re a d -wr it e ca ch e like t h e Mob ile AMD-K6-2+
p roce ssor L1 d a t a ca ch e a n d t h e L2 ca ch e . Th e followin g
con d it ion s a p p ly t o b ot h t h e wr it e t h rou gh a n d wr it eb a ck
modes:
■ Memory Writes—A relationship exists between external
memory writes and their concurrence with cache updates:
•
An external memory write that occurs concurrently with
a cache update to the same location is a writethrough.
Writethroughs are driven as single cycles on the bus.
•
An external memory write that occurs after the processor
has modified a cache line is a writeback. Writebacks are
driven as burst cycles on the bus.
■ Coherency State—A relationship exists between MESI
coherency states and writethrough-writeback coherency
states of lines in the cache as follows:
•
Shared and invalid MESI lines are in the writethrough
state.
•
Modified and exclusive MESI lines are in the writeback
state.
8.13
A20M# Masking of Cache Accesses
Alt h ough the processor sample s A20M# a s a leve l-sensitive
input on every clock edge, it should only be asserted in Real
mode. The processor applies the A20M# masking to its tags,
t h rou gh wh ich a ll p rogra m s a cce ss t h e ca ch e s. Th e re fore ,
assertion of A20M# affects all addresses (cache and external
memory), including the following:
■ Cache-line fills (caused by read misses or write allocates)
■ Cache writethroughs (caused by write misses or write hits to
lines in the shared state)
However, A20M# does not mask writebacks or invalidations
caused by the following actions:
■ Internal snoops
■ Inquire cycles
■ The FLUSH# signal
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■ Writing to the PFIR
■ The WBINVD instruction
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Mobile AMD-K6 -2+ Processor Data Sheet
9
Write Merge Buffer
Th e Mob ile AMD-K6-2+ p roce ssor con t a in s a n 8-byt e writ e
merge buffer that allows the processor to conditionally combine
data from multiple noncacheable write cycles into this merge
b u ffe r. Th e m e rge b u ffe r op e ra t e s in con j u n ct ion wit h t he
Memory Typ e Range Registers (MTRRs). Refer to “Memory
Type Range Registers” on page 219 for a description of the
MTRRs.
Merging multiple write cycles into a single write cycle reduces
p r oce ssor b u s u t iliza t ion a n d p r oce ssor st a lls, t h e r e b y
increasing the overall system performance.
9.1
EWBE Control
Th e p re se n ce of t h e m e rge b u ffe r cre a t e s t h e p ot e n t ia l t o
perform out-of-order write cycles relative to t he processor’s
caches. In general, the ordering of write cycles that are driven
externally on the system bus and those that hit the processor’s
cache can be controlled by the EWBE# signal. See “EWBE#
(E xt e r n a l Wr it e Bu ffe r E m p t y)” on p a ge 103 for m or e
in for m a t ion . If E WBE # is sa m p le d n e ga t e d , t h e p roce ssor
delays the comm itment of write cycles t o cache lines in the
m od ifie d st a t e or exclu sive st a t e in t h e p rocessor’s ca che s.
The re fore, t h e syst e m logic ca n en force st ron g ord e r in g by
negatin g EWBE# until the external write cycle is complete,
thereby ensuring that a subsequent write cycle that hits a cache
does not complete ahead of the external write cycle.
However, the addition of the write merge buffer introduces the
potential for out-of-order write cycles to occur between writes
t o t h e m e rge b u ffe r a n d wr it e s t o t h e p roce ssor ’s ca ch e s.
Because these writes occur entirely within the processor and
are not sent out to the processor bus, the system logic is not able
to enforce strong ordering with the EWBE# signal.
The EWBE control (EWBEC) bits in the EFER register provide
a m e ch a n ism for e n forcin g t h re e d iffe re n t leve ls of wr it e
ordering in the presence of the write merge buffer:
■ EFER[3] is defined as the Global EWBE Disable
(GEWBED). When GEWBED equals 1, the processor does
not attempt to enforce any write ordering internally or
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externally (the EWBE# signal is ignored). This is the
maximum performance setting.
■ EFER[2] is defined as the Speculative EWBE Disable
(SEWBED). SEWBED only affects the processor when
GEWBED equals 0. If GEWBED equals 0 and SEWBED
equals 1, the processor enforces strong ordering for all
internal write cycles with the exception of write cycles
addressed to a range of memory defined as uncacheable
(UC) or write-combining (WC) by the MTRRs. In addition,
the processor samples the EWBE# signal. If EWBE# is
sampled negated, the processor delays the commitment of
write cycles to processor cache lines in the modified state or
exclusive state until EWBE# is sampled asserted.
This setting provides performance comparable to, but
slightly less than, the performance obtained when
GEWBED equals 1 because some degree of write ordering is
maintained.
■ If GEWBED equals 0 and SEWBED equals 0, the processor
enforces strong ordering for all internal and external write
cycles. In this setting, the processor assumes, or speculates,
that strong order must be maintained between writes to the
merge buffer and writes that hit the processor’s caches.
Once the merge buffer is written out to the processor’s bus,
the EWBE# signal is sampled. If EWBE# is sampled negated,
the processor delays the commitment of write cycles to
processor cache lines in the modified state or exclusive state
until EWBE# is sampled asserted.
This setting is the default after RESET and provides the
lowest performance of the three settings because full write
ordering is maintained.
Table 42 summarizes the three settings of the EWBEC field for
the EFER register, along with the effect of write ordering and
performance. For more information on the EFER register, see
“Extended Feature Enable Register (EFER)” on page 39.
Table 42. EWBEC Settings
EFER[3]
(GEWBED) (SEWBED)
EFER[2]
Write
Ordering
Performance
1
0
0 or 1
1
None
Best
All except UC/WC Close-to-Best
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Table 42. EWBEC Settings
EFER[3]
(GEWBED) (SEWBED)
EFER[2]
Write
Ordering
Performance
0
0
All
Slowest
9.2
Memory Type Range Registers
The Mobile AMD-K6-2+ processor provides two variable-range
Me m o r y Typ e R a n ge R e gist e r s (MTR R s)—MTR R 0 a n d
MTRR1—that each specify a range of memory. Each range can
be defined as one of the following memory types:
■ Uncacheable (UC) memory—Memory read cycles are
sourced directly from the specified memory address and the
processor does not allocate a cache line. Memory write
cycles are targeted at the specified memory address and a
write allocation does not occur.
■ Write-Combining (WC) memory—Memory read cycles are
sourced directly from the specified memory address and the
processor does not allocate a cache line. The processor
conditionally combines data from multiple noncacheable
write cycles that are addressed within this range into a
merge buffer. Merging multiple write cycles into a single
write cycle reduces processor bus utilization and processor
stalls, thereby increasing the overall system performance.
This memory type is applicable for linear video frame
buffers.
UC/WC Cacheability
Control Register
(UWCCR)
The MTRRs are accessed by addressing the 64-bit MSR known
as the UC/WC Cacheability Control Register (UWCCR). The
MSR address of the UWCCR is C000_0085h. Following reset, all
bits in the UWCCR register are set to 0. MTRR0 (lower 32 bits
of the UWCCR register) defines the size and memory type of
ra n ge 0 a n d MTR R 1 (u p p e r 32 b it s) d e fin e s t h e size a n d
memory type of range 1 (see Figure 87 on page 220).
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.
Symbol Description
Bits
Symbol Description
Bits
UC1
WC1
Uncacheable Memory Type
Write-Combining Memory Type 33
32
UC0
WC0
Uncacheable Memory Type
Write-Combining Memory Type
0
1
63
49 48
34 33 32 31
W U
17 16
2
1 0
W U
Physical Base Address 1
Physical Address Mask 1
Physical Base Address 0
Physical Address Mask 0
C
1
C
1
C
0
C
0
MTRR1
MTRR0
Figure 87. UC/WC Cacheability Control Register (UWCCR)—MSR C000_0085h (Model D)
Physical Base Address n (n=0, 1). T h i s a d d r e s s i s t h e 1 5 m o s t -
significant bit s of the physical base address of t he m em ory
range. The least-significant 17 bits of the base address are not
needed because the base address is by definition always aligned
on a 128-Kbyte boundary.
Physical Address Mask n (n=0, 1). T h i s va l u e i s t h e 1 5 m o s t -
significant bits of a physical address mask that is used to define
the size of the memory range. This mask is logically ANDed
wit h b ot h t h e p hysica l b a se a d d re ss fie ld of t h e U WCCR
register and the physical address generated by the processor. If
t h e re su lt s of t h e t wo AND op e ra t ion s a re e q u a l, t h e n t h e
generated physical address is considered within the range. That
is, if:
Mask & Physical Base Address = Mask & Physical Address Generated
then the physical address generated by the processor is in the
range.
WCn (n=0, 1). When set t o 1, t h is m e mory ra n ge is d efin ed a s
wr it e com b in a b le (re fe r t o Ta b le 43). Wr it e -com b in a b le
memory is uncacheable.
UCn (n=0, 1). Wh e n se t t o 1, t h is m e m ory ra n ge is d e fin e d a s
uncacheable (refer to Table 43).
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Table 43. WC/UC Memory Type
WCn
UCn
Memory Type
0
1
0
0
1
No effect on cacheability or write combining
Write-combining memory range (uncacheable)
Uncacheable memory range
0 or 1
Memory-Range Restrictions. Th e followin g r u le s r e ga r d in g t h e
address alignment and size of each range must be adhered to
wh e n p rogra m m in g t h e p hysica l b a se a dd re ss a n d p hysica l
address mask fields of the UWCCR register:
■ The minimum size of each range is 128 Kbytes.
■ The physical base address must be aligned on a 128-Kbyte
boundary.
■ The physical base address must be range-size aligned. For
example, if the size of the range is 1 Mbyte, then the
physical base address must be aligned on a 1-Mbyte
boundary.
■ All bits set to 1 in the physical address mask must be
contiguous. Likewise, all bits set to 0 in the physical address
mask must be contiguous. For example:
111_1111_1100_0000b is a valid physical address mask
111_1111_1101_0000b is invalid
Table 44 lists the valid physical address masks and the resulting
range sizes that can be programmed in the UWCCR register.
Table 44. Valid Masks and Range Sizes
Masks
111_1111_1111_1111b
111_1111_1111_1110b
111_1111_1111_1100b
111_1111_1111_1000b
111_1111_1111_0000b
111_1111_1110_0000b
111_1111_1100_0000b
Size
128 Kbytes
256 Kbytes
512 Kbytes
1 Mbyte
2 Mbytes
4 Mbytes
8 Mbytes
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Table 44. Valid Masks and Range Sizes (continued)
Masks
Size
16 Mbytes
32 Mbytes
64 Mbytes
128 Mbytes
256 Mbytes
512 Mbytes
1 Gbyte
111_1111_1000_0000b
111_1111_0000_0000b
111_1110_0000_0000b
111_1100_0000_0000b
111_1000_0000_0000b
111_0000_0000_0000b
110_0000_0000_0000b
100_0000_0000_0000b
000_0000_0000_0000b
2 Gbytes
4 Gbytes
Example. Suppose that the range of memory from 16 Mbytes to
32 Mbytes is uncacheable, and the 8-Mbyte range of memory on
top of 1 Gbyte is write-combinable. Range 0 is defined as the
u n ca ch e a b le ra n ge , a n d ra n ge 1 is d e fin e d a s t h e wr it e -
combining range.
Extracting the 15 most-significant bits of the 32-bit physical
base address that corresponds to 16 Mbytes (0100_0000h) yields
a p hysica l b a se a dd re ss 0 fie ld of 000_0000_1000_0000b .
Because the uncacheable range size is 16 Mbytes, the physical
mask value 0 field is 111_1111_1000_0000b, according to Table
44. Bit 1 of the UWCCR register (WC0) is set to 0 and bit 0 of
the UWCCR register is set to 1 (UC0).
Extracting the 15 most-significant bits of the 32-bit physical
base address that corresponds to 1 Gbyte (4000_0000h) yields a
physical base address 1 field of 010_0000_0000_0000b. Because
the write-combining range size is 8 Mbytes, the physical mask
value 1 field is 111_1111_1100_0000b, according to Table 44. Bit
33 of the UWCCR register (WC1) is set to 1 and bit 32 of the
UWCCR register is set to 0 (UC1).
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10
Floating-Point and Multimedia Execution Units
10.1
Floating-Point Execution Unit
Th e M o b i l e A M D -K 6 -2 + p r o c e s s o r c o n t a i n s a n I E E E
754-compatible and 854-compatible floating-point execution
unit designed to accelerate the performance of software that
utilizes the x86 floating-point instruction set. Floating-point
software is typically written to manipulate numbers that are
very large or very small, that require a high degree of precision,
or that result from complex mathematical operations such as
t r a n sc e n d e n t a ls. Ap p lic a t ion s t h a t t a k e a d va n t a ge of
floating-point operations include geometric calculations for
graphics acceleration, scientific, statistical, and engineering
applications, and business applications that use large amounts
of high-precision data.
The high-performance floating-point execution unit contains an
adder unit, a multiplier unit, and a divide/square root unit.
These low-latency units can execute floating-point instructions
in as few as two processor clocks. To increase performance, the
p r o c e s s o r i s d e s i g n e d t o s i m u l t a n e o u s ly d e c o d e m o s t
floa t in g-p oin t in st r u ct ion s wit h m ost sh or t -d e cod e a b le
instructions.
See “Software Environment” on page 21 for a description of the
floating-point data types, registers, and instructions.
Handling
The Mobile AMD-K6-2+ processor provides the following two
Floating-Point
Exceptions
types of exception handling for floating-point exceptions:
■ If the numeric error (NE) bit in CR0 is set to 1, the processor
invokes the interrupt 10h handler. In this manner, the
floating-point exception is completely handled by software.
■ If the NE bit in CR0 is set to 0, the processor requires
external logic to generate an interrupt on the INTR signal in
order to handle the exception.
External Logic
Support of
Floating-Point
Exceptions
The processor provides the FERR# (Floating-Point Error) and
IGNNE# (Ignore Numeric Error) signals to allow the external
logic t o gene rat e t he int er r up t in a man n er con sist ent wit h
IBM-com p a t ib le P C/AT syst e m s. Th e a sse r t ion of F E R R #
in d ica t e s t h e occu r re n ce of a n u n m a ske d floa t in g-p oin t
exce p t ion re su lt in g from t h e exe cu t ion of a floa t in g-p oin t
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instruction. IGNNE# is used by the external hardware to control
t h e e ffe ct of a n u n m a sked floa t in g-p oint exce p t ion . U n d e r
ce rt a in circu m st a n ce s, if IGNNE # is sa m p le d a sse rt e d , t h e
processor ignores the floating-point exception.
Figure 88 illustrates an implementation of external logic for
supporting floating-point exceptions. The following example
explains the operation of the external logic in Figure 88:
As the result of a floating-point exception, the processor
a s se r t s F E R R #. Th e a s se r t ion of F E R R # a n d t h e
sampling of IGNNE# negated indicates the processor has
st op p e d in st r u ct ion e xe cu t ion a n d is wa it in g for a n
interrupt. The assertion of FERR# leads to the assertion
of INTR by t h e in t e r r u p t con t r olle r. Th e p roce ssor
a c k n ow l e d g e s t h e i n t e r r u p t a n d j u m p s t o t h e
corresponding interrupt service routine in which an I/O
write cycle to address port F0h leads to the assertion of
IGNNE #. Wh e n IGNNE # is sa m p le d a sse r t e d , t h e
p r oce ssor ign ore s t h e floa t in g-p oin t e xce p t ion a n d
con t inu e s inst r uct ion exe cu t ion . Whe n t h e p roce ssor
negates FERR#, the external logic negates IGNNE#.
See “FERR# (Floating-Point Error)” on page 104 and “IGNNE#
(Ignore Numeric Exception)” on page 108 for more details.
I/O Address
Port F0h
Mobile
®
AMD-K6 -2+
IGNNE#
Processor
Flip-Flop
CLOCK
Q
Q
RESET
“1”
DATA
CLEAR
FERR#
Interrupt
Controller
FERR#
Flip-Flop
CLOCK
Q
Q
IRQ13
DATA
CLEAR
INTR
IGNNE#
Figure 88. External Logic for Supporting Floating-Point Exceptions
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10.2
Multimedia and 3DNow!™ Execution Units
Th e mu lt imedia and 3DNow! execut ion units of t he Mobile
A M D -K 6 -2 + p r o c e s s o r a r e d e s i g n e d t o a c c e l e r a t e t h e
performance of software written using the industry-standard
M M X i n s t r u c t i o n s a n d t h e n e w 3 DN ow ! i n s t r u ct i o n s .
Applications that can take advantage of the MMX and 3DNow!
instructions include graphics, video and audio compression and
decompression, speech recognition, and telephony applications.
The multimedia execution unit can execute MMX instructions
in a single processor clock. All MMX and 3DNow! arithmetic
instructions are pipelined for higher performance. To increase
p e r for m a n ce , t h e p roce ssor is d e sign e d t o simu lt a n e ou sly
d e cod e a ll MMX a n d 3DNow! inst r u ct ion s wit h m ost ot h e r
instructions.
®
For more information on MMX instructions, see the AMD-K6
Processor Mult im edia Tech n ology Manu al, ord er # 20726. For
more information on 3DNow! instructions, see the 3DNow!™
Technology Manual, order# 21928.
10.3
Floating-Point and MMX™/3DNow!™ Instruction Compatibility
Registers
Th e e igh t 64-b it MMX re gist e rs (wh ich a re a lso u t ilize d by
3DNow! instructions) are mapped on the floating-point stack.
This enables backward compatibility with all existing software.
For example, the register saving event t hat is performed by
operating systems during task switching requires no changes to
t h e op e r a t in g syst e m . Th e sa m e su p p or t p r ovid e d in a n
operating system’s interrupt 7 handler (Device Not Available)
for savin g a n d re st or in g t h e floa t in g-p oin t re gist e rs a lso
supports saving and restoring the MMX registers.
Exceptions
There are no new exceptions defined for supporting the MMX
a n d 3DNow! in st r u ct ion s. All exce p t ion s t h a t occu r wh ile
d e cod in g or exe cu t in g a n MMX or 3DNow! in st r u ct ion a re
handled in existing exception handlers without modification.
FERR# and IGNNE#
MMX instructions and 3DNow! instructions do not generate
f l o a t i n g -p o i n t e x c e p t i o n s . H o we ve r, i f a n u n m a s k e d
floa t in g-p oin t exce p t ion is p e n d in g, t h e p roce ssor a sse r t s
FERR# at the instruction boundary of the next floating-point
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in struct ion , MMX in st ruction, 3DNow! in struct ion or WAIT
instruction.
Th e sa m p lin g of IGNNE # a sse r t e d on ly a ffe ct s p roce ssor
o p e r a t i o n d u r i n g t h e e x e c u t i o n o f a n e r r o r -s e n s i t ive
f l o a t i n g -p o i n t i n s t r u c t i o n , M M X i n s t r u c t i o n , 3 D Now !
instruction or WAIT instruction when the NE bit in CR0 is set to
0.
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11
System Management Mode (SMM)
11.1
Overview
SMM is an alternate operating mode entered by way of a system
m a n a ge m e n t in t e r r u p t (SMI) a n d h a n d le d by a n in t e rr u p t
service routine. SMM is designed for system control activities
s u ch a s p owe r m a n a g e m e n t . Th e s e a c t iv i t i e s a p p e a r
transparent to conventional operating systems like DOS and
Windows. SMM is primarily targeted for use by the Basic Input
Output System (BIOS) and specialized low-level device drivers.
Th e code and dat a for SMM are stored in the SMM m emory
area, which is isolated from main memory.
The processor enters SMM by the system logic’s assertion of the
SMI# in terrupt a nd the processor’s acknowledgment by the
assertion of SMIACT#. At this point the processor saves its state
into the SMM memory state-save area and jumps to the SMM
se rvice rou t in e . Th e p roce ssor re t u r n s from SMM wh e n it
executes the RSM (resume) instruction from within the SMM
service routine. Subsequently, the processor restores its state
from t h e SMM save a re a , n e ga t e s SMIACT#, a n d re su m e s
exe cution with the instruct ion following the point wh e re it
entered SMM.
The following sections summarize the SMM state-save area,
entry in to and exit from SMM, exceptions and interrupts in
SMM, memory allocation and addressing in SMM, and the SMI#
and SMIACT# signals.
11.2
SMM Operating Mode and Default Register Values
Th e soft wa re e nviron m e n t wit h in SMM h a s t h e followin g
characteristics:
■ Addressing and operation in Real mode
■ 4-Gbyte segment limits
■ Default 16-bit operand, address, and stack sizes, although
instruction prefixes can override these defaults
■ Control transfers that do not override the default operand
size truncate the EIP to 16 bits
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■ Far jumps or calls cannot transfer control to a segment with
a base address requiring more than 20 bits, as in Real mode
segment-base addressing
■ A20M# is masked
■ Interrupt vectors use the Real-mode interrupt vector table
■ The IF flag in EFLAGS is cleared (INTR not recognized)
■ The TF flag in EFLAGS is cleared
■ The NMI and INIT interrupts are disabled
■ Debug register DR7 is cleared (debug traps disabled)
Figu re 89 on p a ge 229 sh ows t h e d e fa u lt m a p of t h e SMM
m e m o r y a r e a . It c on s i s t s o f a 6 4-K b yt e a r e a , b e t we e n
0003_0000h a n d 0003_F F F F h , of wh ich t h e t op 32 Kbyt e s
(0003_8000h to 0003_FFFFh) must be populated with RAM.
Th e de fa ult code -se gme nt (CS) ba se a ddre ss for the a re a —
called the SMM base address—is at 0003_0000h. The top 512
bytes (0003_FE00h to 0003_FFFFh) contain a fill-down SMM
stat e-save area. The default entry point for the SMM service
routine is 0003_8000h.
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Fill Down
0003_FFFFh
0003_FE00h
SMM
State-Save
Area
32-Kbyte
Minimum RAM
SMM
Service Routine
Service Routine Entry Point
SMM Base Address (CS)
0003_8000h
0003_0000h
Figure 89. SMM Memory
Table 45 shows the initial state of registers when entering SMM.
Table 45. Initial State of Registers in SMM
Registers
General Purpose Registers
EFLAGs
SMM Initial State
unmodified
0000_0002h
CR0
PE, EM, TS, and PG are cleared (bits 0, 2, 3,
and 31). The other bits are unmodified.
DR7
0000_0400h
unmodified
0000_8000h
0003_0000h
0000_0000h
GDTR, LDTR, IDTR, TSSR, DR6
EIP
CS
DS, ES, FS, GS, SS
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11.3
SMM State-Save Area
Wh e n t h e p roce ssor a ck n owle d ge s a n SMI# in t e r r u p t by
a sse r t in g SMIACT#, it save s it s st a t e in a 512-b yt e SMM
state-save area shown in Table 46. The save begins at the top of
the SMM memory area (SMM base address + FFFFh) and fills
down to SMM base address + FE00h.
Table 46 shows the offsets in the SMM state-save area relative to
the SMM base address. The SMM service routine can alter any
of the read/write values in the state-save area.
Table 46. SMM State-Save Area Map
Address Offset
Contents Saved
FFFCh
FFF8h
FFF4h
FFF0h
FFECh
FFE8h
FFE4h
FFE0h
FFDCh
FFD8h
FFD4h
FFD0h
FFCCh
FFC8h
FFC4h
FFC0h
FFBCh
FFB8h
FFB4h
FFB0h
FFACh
FFA8h
Notes:
CR0
CR3
EFLAGS
EIP
EDI
ESI
EBP
ESP
EBX
EDX
ECX
EAX
DR6
DR7
TR
LDTR Base
GS
FS
DS
SS
CS
ES
— No data dump at that address
*
Only contains information if SMI# is asserted during a valid I/O bus cycle.
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Table 46. SMM State-Save Area Map (continued)
Address Offset
Contents Saved
I/O Trap Dword
FFA4h
FFA0h
FF9Ch
FF98h
FF94h
FF90h
FF8Ch
FF88h
FF84h
FF80h
FF7Ch
FF78h
FF74h
FF70h
FF6Ch
FF68h
FF64h
FF60h
FF5Ch
FF58h
FF54h
FF50h
FF4Ch
FF48h
FF44h
FF40h
FF3Ch
FF38h
FF34h
FF30h
FF2Ch
Notes:
—
I/O Trap EIP*
—
—
IDT Base
IDT Limit
GDT Base
GDT Limit
TSS Attr
TSS Base
TSS Limit
—
LDT High
LDT Low
GS Attr
GS Base
GS Limit
FS Attr
FS Base
FS Limit
DS Attr
DS Base
DS Limit
SS Attr
SS Base
SS Limit
CS Attr
CS Base
CS Limit
ES Attr
— No data dump at that address
*
Only contains information if SMI# is asserted during a valid I/O bus cycle.
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Table 46. SMM State-Save Area Map (continued)
Address Offset
Contents Saved
FF28h
FF24h
FF20h
FF1Ch
FF18h
ES Base
ES Limit
—
—
—
FF14h
CR2
FF10h
CR4
FF0Ch
FF08h
FF04h
FF02h
FF00h
FEFCh
FEF8h
FEF7h–FE00h
Notes:
I/O restart ESI*
I/O restart ECX*
I/O restart EDI*
HALT Restart Slot
I/O Trap Restart Slot
SMM RevID
SMM BASE
—
— No data dump at that address
Only contains information if SMI# is asserted during a valid I/O bus cycle.
*
11.4
SMM Revision Identifier
Th e SMM revision id e n t ifie r a t offse t F E F Ch in t h e SMM
state-save area specifies the version of SMM and the extensions
that are available on the processor. The SMM revision identifier
fields are as follows:
■ Bits 31–18—Reserved
■ Bit 17—SMM base address relocation (1 = enabled)
■ Bit 16—I/O trap restart (1 = enabled)
■ Bits 15–0—SMM revision level for the Mobile AMD-K6-2+
processor = 0002h
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Table 47 shows the format of the SMM Revision Identifier.
Table 47. SMM Revision Identifier
31–18
Reserved
0
17
16
15–0
SMM Revision Level
0002h
SMM Base Relocation I/O Trap Extension
1
1
11.5
SMM Base Address
Du r in g R E SE T, t h e p roce ssor se t s t h e b a se a dd re ss of t h e
code-segment (CS) for the SMM memory area —the SMM base
address—to its default, 0003_0000h. The SMM base address at
offset FEF8h in the SMM state-save area can be changed by the
SMM se r vice r ou t in e t o a n y a d d re ss t h a t is a lign e d t o a
32-Kb yt e b ou n d a ry. (Loca t ion s n ot a lign e d t o a 32-Kbyt e
boundary cause the processor to enter the Shutdown state when
executing the RSM instruction.)
In some operating environments it may be desirable to relocate
the 64-Kbyte SMM memory area to a high memory area in order
to provide more low memory for legacy software. During system
initialization, the base of the 64-Kbyte SMM memory area is
relocated by the BIOS. To relocate the SMM base address, the
system enters the SMM handler at the default address. This
handler changes the SMM base address location in the SMM
state-save area, copies the SMM handler to the new location,
and exits SMM.
The next time SMM is entered, the processor saves its state at
the new base address. This new address is used for every SMM
entry until the SMM base address in the SMM state-save area is
changed or a hardware reset occurs.
11.6
Halt Restart Slot
During entry into SMM, the halt restart slot at offset FF02h in
the SMM state-save area indicates if SMM was entered from the
Halt state. Before returning from SMM, the halt restart slot
(offset FF02h) can be written to by the SMM service routine to
specify whether the return from SMM takes the processor back
t o t h e H a lt st a t e or t o t h e n e xt in st r u ct ion a ft e r t h e H LT
instruction.
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Upon entry into SMM, the halt restart slot is defined as follows:
■ Bits 15–1—Reserved
■ Bit 0—Point of entry to SMM:
1 = entered from Halt state
0 = not entered from Halt state
After entry into the SMI handler and before returning from
SMM, the halt restart slot can be written using the following
definition:
■ Bits 15–1—Reserved
■ Bit 0—Point of return when exiting from SMM:
1 = return to Halt state
0 = return to next instruction after the HLT instruction
If the return from SMM takes the processor back to the Halt
st a t e , t h e H LT in st r u ct ion is n ot re -exe cu t e d , b u t t h e H a lt
special bus cycle is driven on the bus after the return.
11.7
I /O Trap Dword
If the assertion of SMI# is recognized during the execution of an
I/O instruction, the I/O trap dword at offset FFA4h in the SMM
state-save area contains information about the instruction. The
fields of the I/O trap dword are configured as follows:
■ Bits 31–16—I/O port address
■ Bits 15–4—Reserved
■ Bit 3—REP (repeat) string operation
(1 = REP string, 0 = not a REP string)
■ Bit 2—I/O string operation
(1 = I/O string, 0 = not a I/O string)
■ Bit 1—Valid I/O instruction (1 = valid, 0 = invalid)
■ Bit 0—Input or output instruction (1 = INx, 0 = OUTx)
Table 48 shows the format of the I/O trap dword.
Table 48. I/O Trap Dword Configuration
31—16
15—4
3
2
1
0
I/O Port Reserved
Address
REP String
Operation
I/O String
Operation
Valid I/O
Instruction
Input or
Output
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The I/O trap dword is related to the I/O trap restart slot (see
“I/O Trap Restart Slot”). If bit 1 of the I/O trap dword is set by
t h e p roce ssor, it m e a ns t ha t SMI# wa s a sse r t e d d ur ing t h e
execution of an I/O instruction. The SMI handler tests bit 1 to
se e if t h e re is a va lid I/O in st r u ct ion t ra p p e d . If t h e I/O
instruction is valid, the SMI handler is required to ensure the
I/O trap restart slot is set prop erly. The I/O trap restart slot
in for m s t h e CP U wh e t h e r it sh ou ld r e -e xe cu t e t h e I/O
instruction after the RSM or execute the instruction following
the trapped I/O instruction.
Note: If SMI# is sampled asserted during an I/O bus cycle a mini-
mum of three clock edges before BRDY# is sampled asserted,
the associated I/O instruction is guaranteed to be trapped by
the SMI handler.
11.8
I/O Trap Restart Slot
The I/O trap restart slot at offset FF00h in the SMM state-save
area specifies whether the trapped I/O instruction should be
re-executed on return from SMM. This slot in the state-save area
is called t he I/O inst ruction restart funct ion. Re-executing a
trapped I/O instruction is useful, for example, if an I/O write
occu rs t o a d isk t h a t is p owe re d d own . Th e syst e m logic
m on itor in g su ch a n acce ss can a sser t SMI#. The n t h e SMM
service routine would query the system logic, detect a failed I/O
write, take action to power-up the I/O device, enable the I/O
trap restart slot feature, and return from SMM.
The fields of the I/O trap restart slot are defined as follows:
■ Bits 31–16—Reserved
■ Bits 15–0—I/O instruction restart on return from SMM:
0000h = execute the next instruction after the trapped
I/O instruction
00FFh = re-execute the trapped I/O instruction
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Table 49 shows the format of the I/O trap restart slot.
Table 49. I/O Trap Restart Slot
31–16
15–0
Reserved
I/O Instruction restart on return from SMM:
■
■
0000h = execute the next instruction after the trapped I/O
00FFh = re-execute the trapped I/O instruction
The processor initializes the I/O trap restart slot to 0000h upon
e n t ry in t o SMM. If SMM wa s e n t e re d d u e t o a t ra p p e d I/O
in st r u ct ion , t h e p roce ssor in d ica t e s t h e va lid it y of t h e I/O
instruction by setting or clearing bit 1 of the I/O trap dword at
offset FFA4h in the SMM st ate-save area . The SMM service
routine should test bit 1 of the I/O trap dword to determine if a
valid I/O instruction was being executed when entering SMM
and before writing the I/O trap restart slot. If the I/O instruction
is valid, the SMM service routine can safely rewrite the I/O trap
restart slot with the value 00FFh, which causes the processor to
r e -e xe c u t e t h e t r a p p e d I/O in st r u c t ion wh e n t h e R SM
instruction is executed. If the I/O instruction is invalid, writing
the I/O trap restart slot has undefined results.
If a second SMI# is asserted and a valid I/O instruction was
trapped by the first SMM handler, the CPU services the second
SMI# prior to re-executing the trapped I/O instruction. The
second entry into SMM never has bit 1 of the I/O trap dword set,
and the second SMM service routine must not rewrite the I/O
trap restart slot.
During a simultaneous SMI# I/O instruction trap and debug
b r e a k p oin t t ra p , t h e Mob ile AMD-K6-2+ p r oce ssor fir st
re spond s t o t he SMI# a nd postpone s recognizing t h e debug
e xce p t ion u n t il a ft e r r e t u r n in g fr om SMM via t h e R SM
instruction. If the debug registers DR3–DR0 are used while in
SMM, they must be saved and restored by the SMM handler.
The processor automatically saves and restores DR7–DR6. If the
I/O trap restart slot in the SMM state-save area contains the
value 00FFh when the RSM instruction is executed, the debug
trap does not occur until after the I/O instruction is re-executed.
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11.9
Exceptions, Interrupts, and Debug in SMM
During an SMI# I/O trap, the exception/interrupt priority of the
Mobile AMD-K6-2+ processor changes from its normal priority.
The normal priority places the debug traps at a priority higher
than the sampling of the FLUSH# or SMI# signals. However,
during an SMI# I/O trap, the sampling of the FLUSH# or SMI#
signals takes precedence over debug traps.
Th e proce ssor recognizes t he asse rtion of NMI within SMM
immediately after the completion of an IRET instruction. Once
NMI is re cogn ize d wit h in SMM, NMI re cogn it ion re m a in s
enabled until SMM is exited, at which point NMI masking is
restored to the state it was in before entering SMM.
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12
Test and Debug
The Mobile AMD-K6-2+ processor implements various test and
d eb u g m od e s t o e n ab le t h e fu n ct ion a l a n d m a nu fa ct u r in g
t e st in g of syst e m s a n d b oa rd s t h a t u se t h e p roce ssor. In
addition, the debug features of the processor allow designers to
debug the instruction execution of software components. This
chapter describes the following test and debug features:
■ Built-In Self-Test (BIST)—The BIST, which is invoked after
the falling transition of RESET, runs internal tests that
exercise most on-chip RAM structures.
■ Tri-State Test Mode—A test mode that causes the processor to
float its output and bidirectional pins.
■ Boundary-Scan Test Access Port (TAP)—The Joint Test Action
Group (J TAG) test access function defined by the IEEE
Standard Test Access Port and Boundary-Scan Architecture
(IEEE 1149.1-1990) specification.
■ Cache Inhibit —A feature that disables the processor’s
internal L1 and L2 caches.
■ Level-2 Cache Array Access Register (L2AAR)—The Mobile
AMD-K6-2+ processor provides the L2AAR that allows for
direct access to the L2 cache and L2 tag arrays.
■ Debug Support —Consists of all x86-compatible software
debug features, including the debug extensions.
12.1
Built-In Self-Test (BIST)
Followin g t h e fa llin g t ra n sit ion of R E SE T, t h e p roce ssor
unconditionally runs its BIST. The internal resources tested
during BIST include the following:
■ L1 instruction and data caches
■ L2 cache
■ Instruction and Data Translation Lookaside Buffers (TLBs)
Th e content s of the EAX general-purpose register aft er the
completion of reset indicate if the BIST was successful. If EAX
con t a in s 0000_0000h , t h e n BIST wa s su cce ssfu l. If E AX is
non-zero, the BIST failed. Following the completion of the BIST,
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t h e p r o c e s s o r j u m p s t o a d d r e s s F F F F _F F F 0h t o s t a r t
instruction execution, regardless of the outcome of the BIST.
The BIST takes approximately 5,000,000 processor clocks to
complete.
12.2
Tri-State Test Mode
The Tri-State Test mode causes the processor to float its output
a n d b id ir e ct ion a l p in s, wh ich is u se fu l for b oa r d -le ve l
m a n u fa ct u r i n g t e st i n g. In t h i s m od e , t h e p r oce sso r i s
electrically isolated from other components on a system board,
allowing automated test equipment (ATE) to test components
that drive the same signals as those the processor floats.
If t h e F LU SH # sign a l is sa m p le d Low d u r in g t h e fa llin g
transition of RESET, the processor enters the Tri-State Test
m od e . (Se e “ F LU SH # (Ca ch e F lu sh )” on p a ge 105 for t h e
spe cific sampling requirements.) The signa ls floate d in t he
Tri-State Test mode are as follows:
■ A[31:3]
■ ADS#
■ D/C#
■ M/IO#
■ PCD
■ D[63:0]
■ DP[7:0]
■ FERR#
■ HIT#
■ ADSC#
■ AP
■ PCHK#
■ PWT
■ APCHK#
■ BE[7:0]#
■ BREQ
■ CACHE#
■ SCYC
■ SMIACT#
■ W/R#
■ HITM#
■ HLDA
■ LOCK#
■ VID[4:0]
Th e VCC2DE T, VCC2H /L#, a n d TDO sign a ls a re t h e on ly
outputs not floated in the Tri-State Test mode. TDO is never
floa t e d b e ca u se t h e Bou n d a ry-Sca n Te st Acce ss Por t mu st
remain enabled at all times, including during the Tri-State Test
mode.
The Tri-State Test mode is exited when the processor samples
RESET asserted.
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12.3
Boundary-Scan Test Access Port (TAP)
The boundary-scan Test Access Port (TAP) is an IEEE standard
that defines synchronous scanning test methods for complex
logic circuits, such as boards containing a processor. The Mobile
AMD-K6-2+ processor supports the TAP standard defined in the
IEEE Standard Test Access Port and Boundary-Scan Architecture
(IEEE 1149.1-1990) specification.
Boundary scan testing uses a shift register con sisting of the
serial interconnection of boundary-scan cells that correspond to
each I/O buffer of the processor. This non-invertin g register
chain, called a Boundary Scan Register (BSR), can be used to
ca p t u re t h e st a t e of eve ry p roce ssor p in a n d t o d r ive eve ry
processor output and bidirectional pin to a known state.
Each BSR of every component on a board that implements the
boundary-scan architecture can be serially interconnected to
enable component interconnect testing.
Test Access Port
The TAP consists of the following:
■ Test Access Port (TAP) Controller —The TAP controller is a
synchronous, finite state machine that uses the TMS and
TDI input signals to control a sequence of test operations.
See “TAP Controller State Machine” on page 248 for a list
of TAP states and their definition.
■ Instruction Register (IR)—The IR contains the instructions
that select the test operation to be performed and the Test
Data Register (TDR) to be selected. See “TAP Registers” on
page 242 for more details on the IR.
■ Test Data Registers (TDR)—The three TDRs are used to
process the test data. Each TDR is selected by an
instruction in the Instruction Register (IR). See “TAP
Registers” on page 242 for a list of these registers and their
functions.
TAP Signals
Th e t e st sign a ls a ssocia t e d wit h t h e TAP con t rolle r a re a s
follows:
■ TCK—The Test Clock for all TAP operations. The rising edge
of TCK is used for sampling TAP signals, and the falling
edge of TCK is used for asserting TAP signals. The state of
the TMS signal sampled on the rising edge of TCK causes
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the state transitions of the TAP controller to occur. TCK can
be stopped in the logic 0 or 1 state.
■ TDI—The Test Data Input represents the input to the most
significant bit of all TAP registers, including the IR and all
test data registers. Test data and instructions are serially
shifted by one bit into their respective registers on the rising
edge of TCK.
■ TDO—The Test Data Output represents the output of the
least significant bit of all TAP registers, including the IR and
all test data registers. Test data and instructions are serially
shifted by one bit out of their respective registers on the
falling edge of TCK.
■ TMS—The Test Mode Select input specifies the test function
and sequence of state changes for boundary-scan testing. If
TMS is sampled High for five or more consecutive clocks, the
TAP controller enters its reset state.
■ TRST#—The Test Reset signal is an asynchronous reset that
unconditionally causes the TAP controller to enter its reset
state.
Refer to “Electrical Data” on page 275 and “Signal Switching
C h a r a c t e r i s t i cs ” on p a ge 2 7 9 t o ob t a i n t h e e l e c t r i c a l
specifications of the test signals.
TAP Registers
Th e Mob ile AMD-K6-2+ p roce ssor p rovid e s a n In st r u ct ion
Register (IR) and three Test Data Registers (TDR) to support
the boundary-scan architecture. The IR and one of the TDRs—
the Boundary-Scan Register (BSR) —consist of a shift register
and an output register. The shift register is loaded in parallel in
the Capture states. (See “TAP Controller State Machine” on
p age 248 for a d e scrip t ion of t h e TAP con t rolle r st at e s.) In
addition, the shift register is loaded and shifted serially in the
Shift states. The output register is loaded in parallel from its
corresponding shift register in the Update states.
Instruction Register (IR). The IR is a 5-bit register, without parity,
that determines which instruction to run and which test data
r e g ist e r t o se le ct . Wh e n t h e TAP con t r olle r e n t e r s t h e
Capture-IR state, the processor loads the following bits into the
IR shift register:
■ 01b—Loaded into the two least significant bits, as specified
by the IEEE 1149.1 standard
■ 000b—Loaded into the three most significant bits
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Loading 00001b into the IR shift register during the Capture-IR
state results in loading the SAMPLE/PRELOAD instruction.
For each entry into the Shift-IR state, the IR shift register is
serially shifted by one bit toward the TDO pin. During the shift,
the most significant bit of the IR shift register is loaded from
the TDI pin.
The IR output register is loaded from the IR shift register in the
Update-IR state, and the current instruction is defined by the IR
output register. See “TAP Instructions” on page 247 for a list and
d e f i n i t i o n o f t h e i n s t r u c t i o n s s u p p o r t e d b y t h e M o b i l e
AMD-K6-2+ processor.
Boundary Scan Register (BSR). Th e BSR is a Te st Da t a R e gist e r
consisting of the interconnection of 152 boundary-scan cells.
Each output and bidirectional pin of the processor requires a
two-bit cell, where one bit corresponds to the pin and the other
bit is the output enable for the pin. When a 0 is shifted into the
enable bit of a cell, the corresponding pin is floated, and when a
1 is shifted into the enable bit, the pin is driven valid. Each
input pin requires a one-bit cell that corresponds to the pin. The
last cell of the BSR is reserved and does not correspond to any
processor pin.
The total number of bits that comprise the BSR is 297. Table 50
on page 245 lists the order of these bits, where TDI is the input
t o b it 296, a n d TDO is d r ive n from t h e ou t p u t of b it 0. The
entries listed as pin_E (where pin is an output or bidirectional
signal) are the enable bits.
If the BSR is the register selected by the current instruction and
the TAP controller is in the Capture-DR state, the processor
loads the BSR shift register as follows:
■ If the current instruction is SAMPLE/PRELOAD, then the
current state of each input, output, and bidirectional pin is
loaded. A bidirectional pin is treated as an output if its
enable bit equals 1, and it is treated as an input if its enable
bit equals 0.
■ If the current instruction is EXTEST, then the current state
of each input pin is loaded. A bidirectional pin is treated as
an input, regardless of the state of its enable.
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While in the Shift-DR state, the BSR shift register is serially
shifted toward the TDO pin. During the shift, bit 280 of the BSR
is loaded from the TDI pin.
The BSR output register is loaded with the contents of the BSR
shift register in the Update-DR state. If the current instruction
is E XTE ST, t h e p r oce ssor ’s ou t p u t p in s, a s we ll a s t h ose
bidirectional pins that are enabled as outputs, are driven with
their corresponding values from the BSR output register.
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Table 50. Boundary Scan Bit Definitions
Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable
296 A6_E
295 A6
263 A28_E
262 A28
230 HIT#
229 A27_E
228 A27
197 AP
164 RSVD
163 RSVD
162 RSVD
161 RSVD
160 AHOLD
159 INV
131 D40_E
130 D40
196 A20_E
195 A20
294 VID1_E
293 VID1
292 A22_E
291 A22
261 ADS_E
260 ADS#
259 A17_E
258 A17
129 D59_E
128 D59
227 A4_E
226 A4
194 BREQ_E
193 BREQ
192 A11_E
191 A11
127 D9_E
126 D9
225 A7_E
224 A7
290 PCHK_E
289 PCHK#
288 A14_E
287 A14
257 A25_E
256 A25
158 CLK
125 D28_E
124 D28
223 A8_E
222 A8
190 A10_E
189 A10
157 VID2_E
156 VID2
255 PWT_E
254 PWT
253 A12_E
252 A12
123 D56_E
221 A15_E
220 A15
188 APCHK_E 155 CACHE_E 122 D56
286 A13_E
285 A13
187 APCHK#
154 CACHE#
121 D44_E
120 D44
219 DC_E
218 D/C#
217 A16_E
216 A16
186 SMIACT_E 153 MIO_E
284 A24_E
283 A24
251 A9_E
250 A9
185 SMIACT#
184 RSVD
183 A5_E
182 A5
152 M/IO#
151 FERR_E
150 FERR#
149 D0_E
148 D0
119 D11_E
118 D11
282 RESET
281 A18_E
280 A18
249 A26_E
248 A26
117 DP3_E
116 DP3
215 A19_E
214 A19
247 A30_E
246 A30
181 INTR
180 NMI
115 D39_E
114 D39
279 A21_E
278 A21
213 SCYC_E
212 SCYC
211 ADSC_E
210 ADSC#
209 BE6_E
208 BE6
147 D1_E
146 D1
245 VID0_E
244 VID0
243 HITM_E
242 HITM#
241 A20M#
240 FLUSH#
239 A3_E
238 A3
179 INIT
113 DP6_E
112 DP6
277 PCD_E
276 PCD
178 HOLD
177 IGNNE#
176 SMI#
175 WB/WT#
174 BF0
145 D61_E
144 D61
111 D8_E
110 D8
275 BE4_E
274 BE4#
273 BE7_E
272 BE7#
271 A23_E
270 A23
143 D62_E
142 D62
109 D32_E
108 D32
207 BE3_E
206 BE3
141 DP0_E
140 DP0
173 BOFF#
172 NA#
107 D36_E
106 D36
205 HLDA_E
204 HLDA
203 BE1_E
202 BE1#
201 EADS#
200 BE2_E
199 BE2#
198 AP_E
139 D21_E
138 D21
237 A31_E
236 A31
171 BF1
105 D51_E
104 D51
269 LOCK_E
268 LOCK#
267 BE0_E
266 BE0#
265 BE5_E
264 BE5#
170 BRDYC#
169 BRDY#
168 STPCLK#
167 BF2
137 D57_E
136 D57
235 A29_E
234 A29
103 D15_E
102 D15
135 D5_E
134 D5
233 WR_E
232 W/R#
231 HIT_E
101 D37_E
100 D37
166 KEN#
165 EWBE#
133 D24_E
132 D24
99 D41_E
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Table 50. Boundary Scan Bit Definitions (continued)
Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable
98 D41
81 D49
64 D20_E
63 D20
47 D35
30 D43_E
29 D43
13 D45
97 D52_E
96 D52
80 D17_E
79 D17
46 D10_E
45 D10
12 D60_E
11 D60
62 D13_E
61 D13
28 D58_E
27 D58
95 D14_E
94 D14
78 D19_E
77 D19
44 D53_E
43 D53
10 D22_E
60 DP5_E
59 DP5
26 D26_E
25 D26
9
8
7
6
5
4
3
2
1
0
D22
93 D29_E
92 D29
76 D48_E
75 D48
42 D34_E
41 D34
D63_E
D63
58 D31_E
57 D31
24 D3_E
23 D3
91 D33_E
90 D33
74 D47_E
73 D47
40 VID4_E
39 VID4
38 D7_E
37 D7
DP7_E
DP7
56 D27_E
55 D27
22 D55_E
21 D55
89 RSVD
88 D18_E
87 D18
72 D16_E
71 D16
D4_E
D4
54 D12_E
53 D12
20 D42_E
19 D42
70 DP1_E
69 DP1
36 DP4_E
35 DP4
D2_E
D2
86 D23_E
85 D23
52 D50_E
51 D50
18 VID3_E
17 VID3
16 D6_E
15 D6
68 D46_E
67 D46
34 D54_E
33 D54
Reserved
84 D25_E
83 D25
50 D38_E
49 D38
66 DP2_E
65 DP2
32 D30_E
31 D30
82 D49_E
48 D35_E
14 D45_E
Device Identification Register (DIR). Th e DIR is a 32-b it Te st Da t a
R e gist e r se le ct e d d u r in g t h e e xe cu t ion of t h e IDCODE
instruction. The fields of the DIR and their values are shown in
Table 51 and are defined as follows:
■ Version Code—This 4-bit field is incremented by AMD
manufacturing for each major revision of silicon.
■ Part Number —This 16-bit field identifies the specific
processor model.
■ Manufacturer —This 11-bit field identifies the manufacturer
of the component (AMD).
■ LSB—The least significant bit (LSB) of the DIR is always set
to 1, as specified by the IEEE 1149.1 standard.
Table 51. Device Identification Register
Version Code
(Bits 31–28)
Part Number
(Bits 27–12)
Manufacturer
(Bits 11–1)
LSB
(Bit 0)
Xh
05D0h
00000000001b
1b
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Bypass Register (BR). The BR is a Test Data Register consisting of
a 1-bit shift register that provides the shortest path between
TDI a n d TDO. Whe n t he p roce ssor is n ot involve d in a t e st
operation, the BR can be selected by an instruction to allow the
transfer of test data through the processor without having to
serially scan the test data through the BSR. This functionality
preserves the state of the BSR and significantly reduces test
time.
Th e BR re gist e r is se le ct e d b y t h e BYPASS a n d H IGH Z
instructions as well as by any instructions not supported by the
Mobile AMD-K6-2+ processor.
TAP Instructions
The processor supports the three instructions required by the
IE E E 1149.1 sta n d a rd —E XTE ST, SAMP LE /P RELOAD, a nd
BYPASS —as we ll as t wo addit ional optional instruct ions —
IDCODE and HIGHZ.
Table 52 shows the complete set of TAP instructions supported
by t h e p roce ssor a lon g wit h t h e 5-b it In st r u ct ion R e gist e r
encoding and the register selected by each instruction.
Table 52. Supported Tap Instructions
Instruction
Encoding
00000b
Register
BSR
BSR
DIR
Description
Sample inputs and drive outputs
Sample inputs and outputs, then load the BSR
Read DIR
1
EXTEST
SAMPLE / PRELOAD
IDCODE
00001b
00010b
HIGHZ
00011b
BR
Float outputs and bidirectional pins
Undefined instruction, execute the BYPASS instruction
2
00100b–11110b
BR
BYPASS
3
11111b
BR
Connect TDI to TDO to bypass the BSR
BYPASS
Notes:
1. Following the execution of the EXTEST instruction, the processor must be reset in order to return to normal, non-test operation.
2. These instruction encodings are undefined on the Mobile AMD-K6-2+ processor and default to the BYPASS instruction.
3. Because the TDI input contains an internal pullup, the BYPASS instruction is executed if the TDI input is not connected or open
during an instruction scan operation. The BYPASS instruction does not affect the normal operational state of the processor.
EXTEST. Wh e n t h e E X TE S T i n s t r u c t i o n i s e x e c u t e d , t h e
processor loads the BSR shift register with the current state of
the input and bidirectional pins in the Capture-DR state and
drives the output and bidirectional pins with the corresponding
values from the BSR output register in the Update-DR state.
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SAMPLE/PRELOAD. The SAMPLE/PRELOAD instruction performs
two functions. These functions are as follows:
■ During the Capture-DR state, the processor loads the BSR
shift register with the current state of every input, output,
and bidirectional pin.
■ During the Update-DR state, the BSR output register is
loaded from the BSR shift register in preparation for the
next EXTEST instruction.
The SAMPLE/PRELOAD instruction does not affect the normal
operational state of the processor.
BYPASS. The BYPASS instruction selects the BR register, which
reduces the boundary-scan length through the processor from
297 to one (TDI to BR to TDO). The BYPASS instruction does
not affect the normal operational state of the processor.
IDCODE. Th e IDCODE in st r u ct ion se le ct s t h e DIR re gist e r,
allowing the device identification code to be shifted out of the
processor. This instruction is loaded into the IR when the TAP
controller is reset. The IDCODE instruction does not affect the
normal operational state of the processor.
HIGHZ. T h e H I G H Z i n s t r u c t i o n f o r c e s a l l o u t p u t a n d
bidirectional pins to be floated. During this instruction, the BR
is selected and the normal operational state of the processor is
not affected.
TAP Controller State
Machine
The TAP controller state diagram is shown in Figure 90 on page
249. State transitions occur on the rising edge of TCK. The logic
0 or 1 next to the states represents the value of the TMS signal
sampled by the processor on the rising edge of TCK.
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Test-Logic-Reset
1
0
0
1
1
1
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
0
Capture-DR
0
0
1
1
Capture-IR
0
Shift-DR
Shift-IR
0
0
1
1
1
1
Exit1-DR
Exit1-IR
0
0
Pause-DR
Pause-IR
0
0
1
1
Exit2-DR
Exit2-IR
0
0
1
1
Update-DR
Update-IR
1
0
1
0
IEEE Std 1149.1-1990, Copyright © 1990. IEEE. All rights reserved
Figure 90. TAP State Diagram
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The states of the TAP controller are described as follows:
Test-Logic-Reset. This state represents the initial reset state of the
TAP con t rolle r a n d is e n t e re d wh e n t h e p roce ssor sa m p le s
RESET asserted, when TRST# is asynchronously asserted, and
when TMS is sampled High for five or more consecutive clocks.
In addition, this state can be entered from the Select-IR-Scan
state. The IR is initialized with the IDCODE instruction, and
the processor’s normal operation is not affected in this state.
Capture-DR. Du r in g t h e SAMP LE /P R E LOAD in st r u ct ion , t he
processor loads the BSR shift register with the current state of
every input, output, and bidirectional pin. During the EXTEST
instruction, the processor loads the BSR shift register with the
current state of every input and bidirectional pin.
Capture-IR. When the TAP controller enters the Capture-IR state,
the processor loads 01b into the two least significant bits of the
IR shift register and loads 000b into the three most significant
bits of the IR shift register.
Shift-DR. While in t h e Shift-DR sta te , the sele ct ed TDR shift
register is serially shifted toward the TDO pin. During the shift,
the most significant bit of the TDR is loaded from the TDI pin.
Shift-IR. Wh ile in t h e Sh ift -IR st a t e , t h e IR sh ift re gist e r is
serially shifted toward the TDO pin. During the shift, the most
significant bit of the IR is loaded from the TDI pin.
Update-DR. During the SAMPLE/PRELOAD instruction, the BSR
output register is loaded with the content s of t he BSR shift
register. During the EXTEST instruction, the output pins, as
well as those bidirectional pins defined as outputs, are driven
with their corresponding values from the BSR output register.
Update-IR. In this state, the IR output register is loaded from the
IR shift register, and the current instruction is defined by the IR
output register.
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Th e followin g st a t e s h ave n o e ffe ct on t h e n or m a l or t e st
operation of the processor other than as shown in Figure 90 on
page 249:
■ Run-Test/Idle —This state is an idle state between scan
operations.
■ Select-DR-Scan —This is the initial state of the test data
register state transitions.
■ Select-IR-Scan —This is the initial state of the Instruction
Register state transitions.
■ Exit1-DR —This state is entered to terminate the shifting
process and enter the Update-DR state.
■ Exit1-IR —This state is entered to terminate the shifting
process and enter the Update-IR state.
■ Pause-DR —This state is entered to temporarily stop the
shifting process of a Test Data Register.
■ Pause-IR —This state is entered to temporarily stop the
shifting process of the Instruction Register.
■ Exit2-DR —This state is entered in order to either terminate
the shifting process and enter the Update-DR state or to
resume shifting following the exit from the Pause-DR state.
■ Exit2-IR —This state is entered in order to either terminate
the shifting process and enter the Update-IR state or to
resume shifting following the exit from the Pause-IR state.
12.4
Cache Inhibit
Purpose
Th e Mob ile AMD-K6-2+ p r oce ssor p r ovid e s a m e a n s for
inhibiting the normal operation of its internal L1 and L2 caches
while still supporting an external cache. This capability allows
system designers to disable the L1 and L2 caches during the
testing and debug of a L3 cache.
If the Cache Inhibit bit (bit 3) of Test Register 12 (TR12) is set
to 0, the processor’s L1 and L2 caches are enabled and operate
as described in “Cache Organization” on page 191. If the Cache
Inhibit bit is set to 1, the L1 and L2 caches are disabled and no
new cache lines are allocated. Even though new allocations do
not occur, valid L1 and L2 cache lines remain valid and are read
by the processor when a requested address hits a cache line. In
a ddition, the proce ssor continue s to support inquire cycle s
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in it ia t e d by t h e syst e m logic, in clu d in g t h e e xe cu t ion of
writeback cycles when a modified cache line is hit.
While the L1 and L2 are inhibited, the processor continues to
drive the PCD output signal appropriately, which system logic
can use to control external L3 caching.
In order to completely disable the L1 and L2 caches so no valid
lines exist in the cache, the Cache Inhibit bit must be set to 1
and the cache must be flushed in one of the following ways:
■ Asserting the FLUSH# input signal
■ Executing the WBINVD instruction
■ Executing the INVD instruction (modified cache lines are
not written back to memory)
■ Make use of the Page Flush/Invalidate Register (PFIR) (see
“PFIR” on page 210)
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12.5
L2 Cache and Tag Array Testing
Level-2 Cache Array
Access Register
(L2AAR)
The Mobile AMD-K6-2+ processor provides the Level-2 Cache
Array Access Register (L2AAR) that allows for direct access to
the L2 cache and L2 tag arrays. The 128-Kbyte L2 cache in the
Mobile AMD-K6-2+ processor is organized as shown in Figure
91:
■ Four 32-Kbyte ways
■ Each way contains 512 sets
■ Each set contains four 64-byte sectors (one sector in each
way)
■ Each sector contains two 32-byte cache lines
■ Each cache line contains four 8-byte octets
■ Each octet contains an upper and lower dword (4 bytes)
Each line within a sector contains its own MESI state bits, and
associated with each sector is a tag and LRU (Least Recently
Used) information.
64 bytes
64 bytes
64 bytes
64 bytes
Line1/MESI
Line0/MESI
Line1/MESI Line0/MESI
Tag/LRU
Tag/LRU
Line1/MESI
Line0/MESI
Tag/LRU
Line1/MESI Line0/MESI Tag/LRU
Set 0
Way 0
Way 1
Way 2
Way 3
Set 511
Figure 91. L2 Cache Organization
Figu re 92 on p a ge 254 sh ows t h e L2 ca ch e se ct or a n d lin e
organization. If bit 5 of the address of a cache line equals 1, then
this cache line is stored in Line 1 of a sector. Similarly, if bit 5 of
t he a ddress of a cache line equals 0, the n t his ca che line is
stored in Line 0 of a sector.
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Octet 0
Octet 1
Octet 2
Octet 3
Upper Dword
Lower Dword
Upper Dword
Lower Dword
Line 1
Line 0
Sector
Figure 92. L2 Cache Sector and Line Organization
The L2AAR register is MSR C000_0089h. The operation that is
p e rfor me d on t h e L2 ca ch e is a fu n ct ion of t h e inst ru ct ion
executed —RDMSR or WRMSR —and the contents of the EDX
register. The EDX register specifies the location of the access,
and whether the access is to the L2 cache data or tags (refer to
Figure 93). Bit 20 of EDX (T/D) determines whether the access
is to the L2 cache data or tag. Table 53 describes the operation
that is performed based on the instruction and the T/D bit.
Symbol Description
Bit
T/D
Way
Selects Tag (1) or Data (0) access
Selects desired cache way
20
17-16
31
21 20 19 18
6
5
4
3 2
1
0
17 16 15 14
Way
D
w
o
r
d
L
i
n
e
T
/
D
Octet
Set
Reserved
Symbol Description
Bit
14-6
5
Set
Selects the desired cache set
Line
Octet
Selects Line1 (1) or Line0 (0)
Selects one of four octets
4-3
Dword Selects upper (1) or lower (0) dword
2
Figure 93. L2 Tag or Data Location - EDX
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Table 53. Tag versus Data Selector
T/D
Instruction
Operation
(EDX[20])
Read dword from L2 data array into EAX. Dword
location is specified by EDX.
RDMSR
RDMSR
WRMSR
WRMSR
0
1
0
1
Read tag, line state and LRU information from L2 tag
array into EAX. Location of tag is specified by EDX.
Write dword to the L2 data array using data in EAX.
Dword location is specified by EDX.
Write tag, line state and LRU information into L2 tag
array from EAX. Location of tag is specified by EDX.
When the L2AAR is read or written, EDX is left unchanged.
Th is fa cilit a t e s mu lt ip le a cce sse s wh e n t e st in g t h e e n t ire
cache/tag array.
If t h e L2 ca che d a t a is rea d (as op p osed t o rea d in g t h e t ag
information), the result (dword) is placed in EAX in the format
as illustrated in Figure 94. Similarly, if the L2 cache data is
written, the write data is taken from EAX.
31
0
Data
Figure 94. L2 Data - EAX
If the L2 tag is read (as opposed to reading the cache data), the
result is placed in EAX in the format as illustrated in Figure 95
on page 256. Similarly, if the L2 tag is written, the write data is
taken from EAX. When accessing the L2 tag, the Line, Octet,
and Dword fields of the EDX register are ignored.
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0
31
14 13 12 11 10
9
8 7
Line1ST Line0ST
Tag
LRU
Reserved
Symbol Description
Tag Tag data read or written
Bit
31-14
Line1ST Line 1 state (M=11, E=10, S=01, I=00) 11-10
Line0ST Line 0 state (M=11, E=10, S=01, I=00) 9-8
LRU
Two bits of LRU for each way
7-0
Figure 95. L2 Tag Information - EAX
LRU (Least Recently Used). For the 4-way set associative L2 cache,
each way has a 2-bit LRU field for each sector. Values for the
LRU field are 00b, 01b, 10b, and 11b, where 00b indicates that
the sector is “most recently used,” and 11b indicates that the
se ct or is “ le a st re ce n t ly u se d ” (se e Figu re 96). E AX[7:6]
in d ica t e LRU in for m a t ion for Way 0, E AX[5:4] for Way 1,
EAX[3:2] for Way 2, and EAX[1:0] for Way 3.
7
6
5
4
3
2
1
0
Way 0
Way 1
Way 2
Way 3
LRU Values
00b Most Recently Used
01b Used More Recent Than 10b, But Less Recent Than 00b
10b Used More Recent Than 11b, But Less Recent Than 01b
11b Least Recently Used
Figure 96. LRU Byte
12.6
Debug
The Mobile AMD-K6-2+ processor implements the standard x86
debug functions, re gist e rs, a nd exceptions. In a ddition, the
processor supports the I/O breakpoint debug extension. The
d eb u g fe a t u re a ssist s p rogra m m e rs a n d syst e m d e sign e rs
during software execution tracing by generating exceptions
when one or more events occur during processor execution. The
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excep t ion h a n d le r, or d eb u gge r, ca n b e wr it t e n t o p e r for m
various tasks, such as displaying the conditions that caused the
b re a k p oin t t o occu r, d isp layin g a n d m od ifyin g re gist e r or
m e m or y con t e n t s , or si n gle -s t e p p i n g t h r ou gh p r ogr a m
execution.
The following sections describe the debug registers and the
various types of breakpoints and exceptions that the processor
supports.
Debug Registers
Figu re s 97 t h r ou gh 100 sh ow t h e 32-b it d e b u g re gist e rs
supported by the processor.
Symbol
LEN 3
R/W 3
LEN 2
R/W 2
LEN 1
R/W 1
LEN 0
R/W 0
Description
Length of Breakpoint #3
Bits
31–30
Type of Transaction(s) to Trap 29–28
Length of Breakpoint #2 27–26
Type of Transaction(s) to Trap 25–24
Length of Breakpoint #1 23–22
Type of Transaction(s) to Trap 21–20
Length of Breakpoint #0 19–18
Type of Transaction(s) to Trap 17–16
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G
D
G
E
L G
L
3
L
2
L G L G
L
0
LEN
3
R/W LEN R/W LEN R/W LEN R/W
E
3
2
1
1 0
3
2
2
1
1
0
0
Reserved
Symbol
GD
GE
LE
Description
General Detect Enabled
Global Exact Breakpoint Enabled
Local Exact Breakpoint Enabled
Bit
13
9
8
G3
L3
G2
L2
G1
L1
G0
L0
Global Exact Breakpoint # 3 Enabled
Local Exact Breakpoint # 3 Enabled
Global Exact Breakpoint # 2 Enabled
Local Exact Breakpoint # 2 Enabled
Global Exact Breakpoint # 1 Enabled
Local Exact Breakpoint # 1 Enabled
Global Exact Breakpoint # 0 Enabled
Local Exact Breakpoint # 0 Enabled
7
6
5
4
3
2
1
0
Figure 97. Debug Register DR7
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
B
D
B
1
B
S
B
2
B
0
B
T
B
3
Reserved
Symbol
BT
BS
Description
Breakpoint Task Switch
Breakpoint Single Step
Bit
15
14
BD
B3
B2
B1
B0
Breakpoint Debug Access Detected 13
Breakpoint #3 Condition Detected
Breakpoint #2 Condition Detected
Breakpoint #1 Condition Detected
Breakpoint #0 Condition Detected
3
2
1
0
Figure 98. Debug Register DR6
DR5
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reserved
8
7
6
5
4
3
2
1 0
DR4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reserved
8
7
6
5
4
3
2
1 0
Figure 99. Debug Registers DR5 and DR4
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DR3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1 0
Breakpoint 3 32-bit Linear Address
DR2
DR1
DR0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Breakpoint 2 32-bit Linear Address
8
7
6
5
4
3
2
1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Breakpoint 1 32-bit Linear Address
8
7
6
5
4
3
2
1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Breakpoint 0 32-bit Linear Address
8
7
6
5
4
3
2
1 0
Figure 100. Debug Registers DR3, DR2, DR1, and DR0
DR3–DR0. Th e p r oce ssor a l lows t h e se t t in g of u p t o fou r
b re a k p oin t s. DR 3–DR 0 con t a in t h e lin e a r a d d re sse s for
b re a k p oin t 3 t h rou gh b re a k p oin t 0, re sp e ct ive ly, a n d a re
com p a re d t o t h e lin e a r a d d re sse s of p roce ssor cycle s t o
determine if a breakpoint occurs. Debug register DR7 defines
t h e sp e cific t yp e of cycle t h a t mu st occu r in ord e r for t h e
breakpoint to occur.
DR5–DR4. When debugging extensions are disabled (bit 3 of CR4
is set to 0), the DR5 and DR4 registers are mapped to DR7 and
DR 6, re sp e ct ive ly, in ord e r t o b e soft ware com p at ible wit h
p reviou s ge n e ra t ion s of x86 p roce ssors. Wh e n d eb u ggin g
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extensions are enabled (bit 3 of CR4 is set to 1), any attempt to
load DR5 or DR4 results in an undefined opcode exception.
Likewise, any attempt to store DR5 or DR4 also results in an
undefined opcode exception.
DR6. If a b re a k p oin t is e n able d in DR 7, a n d t h e b re a k p oin t
conditions as d efined in DR7 occur, th en the corresponding
B-b it (B3–B0) in DR 6 is se t t o 1. In a d d it ion , a n y ot h e r
b r e a k p oin t s d e fin e d u sin g t h e se p a r t icu la r b r e a k p oin t
con d it ion s a re re p or t e d b y t h e p r oce ssor b y se t t in g t h e
a p p r op r ia t e B-b it s in DR 6, r e ga r d le ss of wh e t h e r t h e se
breakpoints are enabled or disabled. However, if a breakpoint is
n ot e n a b le d , a d e b u g e xce p t ion d oe s n ot occu r for t h a t
breakpoint.
If the processor decodes an instruction that writes or reads DR7
through DR0, the BD bit (bit 13) in DR6 is set to 1 (if enabled in
DR 7) a n d t h e p roce ssor ge n e ra t e s a d eb u g exce p t ion . This
operation allows control to pass to the debugger prior to debug
register access by software.
If the Trap Flag (bit 8) of the EFLAGS register is set to 1, the
proce ssor generate s a debug exception afte r the succe ssful
execution of every instruction (single-step operation) and sets
t h e BS b it (b it 14) in DR 6 t o in d ica t e t h e sou r ce of t h e
exception.
When the processor switches to a new task and the debug trap
bit (T-bit) in the corresponding Task State Segment (TSS) is set
to 1, the processor sets the BT bit (bit 15) in DR6 and generates
a debug exception.
DR7. When set to 1, L3–L0 locally enable breakpoints 3 through
0, re sp e ct ive ly. L3–L0 a re se t t o 0 wh e n eve r t h e p roce ssor
e xe cu t e s a t a sk swit ch . Se t t in g L3–L0 t o 0 d isa b le s t h e
breakpoints and ensures that these particular debug exceptions
are only generated for a specific task.
When set to 1, G3–G0 globally enable breakpoints 3 through 0,
respectively. Unlike L3–L0, G3–G0 are not set to 0 whenever the
processor executes a task switch. Not setting G3–G0 to 0 allows
breakpoints to remain enabled across all tasks. If a breakpoint
is e n ab le d glob a lly bu t d isab le d loca lly, t h e glob a l e nable
overrides the local enable.
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The LE (bit 8) and GE (bit 9) bits in DR7 have no effect on the
op e ra t ion of t h e p roce ssor a n d are p rovid ed in ord e r t o b e
so ft wa r e com p a t ib le wi t h p r e vi ou s ge n e r a t i on s of x86
processors.
When set to 1, the GD bit in DR7 (bit 13) enables the debug
exception associated with the BD bit (bit 13) in DR6. This bit is
set to 0 when a debug exception is generated.
LE N3–LE N0 a n d RW3–RW0 a re t wo-b it fie ld s in DR 7 t h a t
specify the length and type of each breakpoint as defined in
Table 54.
Table 54. DR7 LEN and RW Definitions
1
RW Bits
Breakpoint
LEN Bits
00b
00b
01b
2
Instruction Execution
One-byte Data Write
00b
01b
Two-byte Data Write
11b
Four-byte Data Write
00b
01b
One-byte I/O Read or Write
Two-byte I/O Read or Write
Four-byte I/O Read or Write
One-byte Data Read or Write
Two-byte Data Read or Write
Four-byte Data Read or Write
3
10b
11b
00b
01b
11b
11b
Notes:
1. LEN bits equal to 10b is undefined.
2. When RW equals 00b, LEN must be equal to 00b.
3. When RW equals 10b, debugging extensions (DE) must be enabled (bit 3 of CR4 must be set
to 1). If DE is set to 0, then RW equal to 10b is undefined.
Debug Exceptions
A debug exception is categorized as either a debug trap or a
d eb u g fau lt . A d ebu g t ra p ca lls t h e d ebu gge r following the
execution of the instruction that caused the trap. A debug fault
calls the debugger prior to the execution of the instruction that
caused the fault. All debug traps and faults generate either an
Interrupt 01h or an Interrupt 03h exception.
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Interrupt 01h. The following events are considered debug traps
t h a t ca u se t h e p r oce s sor t o ge n e r a t e a n In t e r r u p t 01h
exception:
■ Enabled breakpoints for data and I/O cycles
■ Single Step Trap
■ Task Switch Trap
The following events are considered debug faults that cause the
processor to generate an Interrupt 01h exception:
■ Enabled breakpoints for instruction execution
■ BD bit in DR6 set to 1
Interrupt 03h. Th e INT 3 in s t r u ct ion is d e fi n e d i n t h e x86
architecture as a breakpoint instruction. This instruction causes
t h e p roce ssor t o ge n e ra t e a n In te r r u p t 03h exce p t ion . This
e xce p t ion is a d eb u g t ra p b e ca u se t h e d eb u gge r is ca lle d
following the execution of the INT 3 instruction.
The INT 3 instruction is a one-byte instruction (opcode CCh)
typically used to insert a breakpoint in software by writing CCh
to the address of the first byte of the instruction to be trapped
(t h e t a rge t in st r u ct ion ). Followin g t h e t ra p, if t h e t a rge t
instruction is to be executed, the debugger must replace the
INT 3 instruction with the first byte of the target instruction.
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13
Clock Control
The Mobile AMD-K6-2+ processor supports six modes of clock
control. The processor can transition between these modes to
maximize performance, to minimize power dissipation, or to
p rovid e a b a la n ce b e t we e n p e r for m a n ce a n d p owe r. (Se e
“ Powe r Dissip a t ion ” on p a ge 278 for t h e m a ximu m p owe r
d issip at ion of t h e Mob ile AMD-K6-2+ p roce ssor wit h in t he
normal and reduced-power states.)
The six clock-control states supported are as follows:
■ Normal State: The processor is running in Real Mode,
Virtual-8086 Mode, Protected Mode, or System Management
Mode (SMM). In this state, all clocks are running—
including the external bus clock CLK and the internal
processor clock—and the full features and functions of the
processor are available.
■ Halt State: This low-power state is entered following the
successful execution of the HLT instruction. During this
state, the internal processor clock is stopped.
■ Stop Grant State: This low-power state is entered following
the recognition of the assertion of the STPCLK# signal.
During this state, the internal processor clock is stopped.
■ Stop Grant Inquire State: This state is entered from the Halt
state and the Stop Grant state as the result of a
system-initiated inquire cycle.
■ Enhanced Power Management (EPM) Stop Grant State: This
low-power state is entered following the write of a non-zero
value to the SGTC field of the EPM 16-byte I/O block for the
purpose of performing dynamic processor core frequency
and voltage ID state transitions using PowerNow!
technology. During this state, the internal processor clock is
stopped.
■ Stop Clock State: This low-power state is entered from the
Stop Grant state when the CLK signal is stopped.
Th e followin g se ct ion s d e scr ib e e a ch of t h e five low-p owe r
states. Figure 101 on page 269 illustrates the clock control state
transitions.
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13.1
Halt State
Enter Halt State
Du r in g t h e e xe cu t ion of t h e H LT in st r u ct ion , t h e Mob ile
AMD-K6-2+ p roce ssor exe cu t e s a Ha lt sp e cia l cycle . Aft e r
BRDY# is sampled asserted during this cycle, and then EWBE#
is a lso sa m p le d a sse r t e d (if n ot m a sked off), t h e p rocessor
enters the Halt state in which the processor disables most of its
internal clock distribution. In order to support the following
operations, the internal phase-lock loop (PLL) continues to run,
and some internal resources are still clocked in the Halt state:
■ Inquire Cycles: The processor continues to sample AHOLD,
BOFF#, and HOLD in order to support inquire cycles that
are initiated by the system logic. The processor transitions to
the Stop Grant Inquire state during the inquire cycle. After
returning to the Halt state following the inquire cycle, the
processor does not execute another Halt special cycle.
■ Flush Cycles: The processor continues to sample FLUSH#. If
FLUSH# is sampled asserted, the processor performs the
flush operation in the same manner as it is performed in the
Normal state. Upon completing the flush operation, the
processor executes the Halt special cycle which indicates
the processor is in the Halt state.
■ Time Stamp Counter (TSC): The TSC continues to count in
the Halt state.
■ Signal Sampling: The processor continues to sample INIT,
INTR, NMI, RESET, and SMI#.
After entering the Halt state, all signals driven by the processor
retain their state as they existed following the completion of
the Halt special cycle.
Exit Halt State
Th e Mob ile AMD-K6-2+ processor remains in t he Halt st at e
until it samples INIT, INTR (if interrupts are enabled), NMI,
RESET, or SMI# asserted. If any of these signals is sampled
a sse r t e d , t h e p r oce ssor re t u r n s t o t h e Nor m a l st a t e a n d
p e r for m s t h e cor re sp on d in g op e ra t ion . All of t h e n or m a l
requirements for recognition of these input signals apply within
the Halt state.
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13.2
Stop Grant State
Enter Stop Grant
State
Aft e r re cogn izin g t h e a sse r t ion of STP CLK#, t h e Mob ile
AMD-K6-2+ p r oce ssor flu sh e s it s in st r u ct ion p ip e lin e s,
com p le t e s a ll p e n d in g a n d in -p r ogr e ss b u s cycle s , a n d
a ck n owle d ge s t h e STP CLK# a sse rt ion by exe cu t in g a St op
Gra n t spe cia l b us cycle . Aft e r BR DY# is sa m ple d a sse rt e d
during this cycle, and after EWBE# is also sampled asserted (if
not masked off), the processor enters the Stop Grant state. The
Stop Grant sta te is like t he Halt stat e in t hat the processor
disables most of its internal clock distribution in the Stop Grant
state. In order to support the following operations, the internal
PLL still runs, and some internal resources are still clocked in
the Stop Grant state:
■ Inquire cycles: The processor transitions to the Stop Grant
Inquire state during an inquire cycle. After returning to the
Stop Grant state following the inquire cycle, the processor
does not execute another Stop Grant special cycle.
■ Time Stamp Counter (TSC): The TSC continues to count in
the Stop Grant state.
■ Signal Sampling: The processor continues to sample INIT,
INTR, NMI, RESET, and SMI#.
FLUSH# is not recognized in the Stop Grant state (unlike while
in the Halt state).
Upon entering the Stop Grant state, all signals driven by the
p roce ssor re t a in t h e ir st a t e a s t h ey e xist e d followin g t h e
completion of the Stop Grant special cycle.
Exit Stop Grant State
The Mobile AMD-K6-2+ processor remains in the Stop Grant
state until it samples STPCLK# negated or RESET asserted. If
STPCLK# is sam p le d n e ga t e d , t h e p roce ssor re t u r n s t o t h e
Normal state in less than 10 bus clock (CLK) periods. After the
transition to the Normal state, the processor resumes execution
at the instruction boundary on which STPCLK# was initially
recognized.
If STPCLK# is recognized as negated in the Stop Grant state
and subsequently sampled asserted prior to returning to the
Normal state, a minimum of one instruction is executed prior to
re-entering the Stop Grant state.
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If INIT, INTR (if int errupts are enabled), FLUSH#, NMI, or
SMI# a r e sa m p le d a sse r t e d in t h e St op Gra n t st a t e , t h e
processor latches the edge-sensitive signals (INIT, FLUSH#,
NMI, and SMI#), but otherwise does not exit the Stop Grant
state to service the interrupt. When the processor returns to the
Normal state due to sampling STPCLK# negated, any pending
interrupts are recognized after returning to the Normal state.
To ensure their recognition, all of the normal requirements for
these input signals apply within the Stop Grant state.
If R ESE T is sa m p le d a sse r t e d in t he St op Gra n t st a t e , t he
processor imm ediately returns to the Norm al sta te a nd the
reset process begins.
13.3
Stop Grant Inquire State
Enter Stop Grant
Inquire State
The Stop Grant Inquire state is entered from the Stop Grant
state or the Halt state when EADS# is sampled asserted during
a n in q u ire cycle in it ia t e d by t h e syst e m logic. The Mob ile
AMD-K6-2+ processor responds to an inquire cycle in the same
manner as in the Normal state by driving HIT# and HITM#. If
t h e in q u ire cycle h it s a m od ifie d ca che lin e , t h e p roce ssor
performs a writeback cycle.
The Stop Grant Inquire state can not be entered from the EPM
(Enhanced Power Management) Stop Grant state.
Exit Stop Grant
Inquire State
Followin g t h e com p le t ion of a ny wr it eb a ck , t h e p roce ssor
re t u r n s t o t h e st a t e from wh ich it e n t e re d t h e St op Gra n t
Inquire state.
13.4
EPM Stop Grant State
Enter EPM Stop Grant
State
After receiving a write of a non-zero value to the SGTC (Stop
Grant Time-out Counter) field located within the EPM 16-byte
I/O b lock , t h e Mob ile AMD-K6-2+ p r oce ssor flu sh e s it s
instruction pipelines, completes all pending and in-progress
bus cycles, and performs the following:
■ Drives the processor VID[4:0] output pins to the value stored
in the VIDO field of the EPM 16-byte I/O block if the VIDC
bit is set to 1.
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■ Forwards the processor-to-bus clock ratio stored in the
IBF[2:0] field of the EPM 16-byte I/O block to the internal
PLL if the BDC[1:0] value is set to 1xb.
Th e EP M Stop Gra nt st a t e is like t he Ha lt sta t e in t hat the
processor disables most of its internal clock distribution in the
E P M St op Gra n t st a t e . In ord e r t o su p p or t t h e followin g
op e ra t ion s, t h e in t e r n a l P LL st ill r u n s, a n d som e in t e r n a l
resources are still clocked in the EPM Stop Grant state:
■ Time Stamp Counter (TSC): The TSC continues to count in
the EPM Stop Grant state.
■ Signal Sampling: The processor continues to sample INIT,
INTR, NMI, RESET, and SMI#.
Unlike the Halt and Stop Grant states, system-initiated inquire
cycles are not support ed and must be preve nt ed during t he
EPM Stop Grant state.
FLUSH# is not recognized in the EPM Stop Grant state (unlike
while in the Halt state).
Upon entering the EPM Stop Grant state, all signals driven by
the processor retain their state as they existed following the
completion of the EPM Stop Grant special cycle.
Exit EPM Stop Grant
State
Th e Mob ile AMD-K6-2+ processor remains in t he EPM Stop
Grant state until the allotted time expires, as determined by the
valu e writt en to t he SGTC field, or until RESET is sampled
asserted. Once the allotted time expires, the processor returns
to the Normal state. After the transition to the Normal state,
the processor resumes execution at the instruction boundary on
which the EPM Stop Grant state was entered.
If INIT, INTR (if int errupts are enabled), FLUSH#, NMI, or
SMI# are sampled asserted in the EPM Stop Grant state, the
processor latches the edge-sensitive signals (INIT, FLUSH#,
NMI, and SMI#), but otherwise does not exit the EP M St op
Grant state to service the interrupt. When the processor returns
to the Normal state, any pending interrupts are recognized. To
ensure their recognition, all of the normal requirements for
these input signals apply within the EPM Stop Grant state.
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If RESET is sampled asserted in the EPM Stop Grant state, the
processor imm ediately returns to the Norm al sta te a nd the
reset process begins.
13.5
Stop Clock State
Enter Stop Clock
State
If t h e CLK sign a l is st op p e d wh ile t h e Mobile AMD-K6-2+
processor is in the Stop Grant st ate or t he EPM Stop Grant
state, the processor enters the Stop Clock state. Because all
internal clocks and the PLL are not running in the Stop Clock
state, the Stop Clock state represents the minimum-power state
of all clock control states. The CLK signal must be held Low
while it is stopped.
The Stop Clock state cannot be entered from the Halt state.
INTR is the only input signal that is allowed to change states
while the processor is in the Stop Clock state. However, INTR is
not sampled until the processor returns to the state from which
it entered the Stop Grant state. All other input signals must
remain unchanged in the Stop Clock state.
Exit Stop Clock State
The Mobile AMD-K6-2+ processor returns to state from which it
entered the Stop Clock state after the CLK signal is started and
the internal PLL has stabilized. PLL stabilization is achieved
after the CLK signal has been running within its specification
for a minimum of 1.0 ms.
The frequency of CLK when exiting the Stop Clock state can be
different than the frequency of CLK when entering the Stop
Clock state.
The state of the external BF[2:0] signals when exiting the Stop
Clock st at e is ign ore d b eca u se t h e BF[2:0] sign als a re on ly
sampled during the falling transition of RESET.
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Non-zero value written to SGTC
HLT Instruction
Normal Mode
– Real
– Virtual-8086
– Protected
– SMM
RESET, SMI#, INIT,
or INTR Asserted
SGTC timer expires
STPCLK# Negated,
STPCLK# Asserted
or RESET Asserted
EPM Stop Grant
State
Stop Grant
State
CLK
Started
CLK
Stopped
CLK
Started
CLK
Stopped
EADS# Asserted
Writeback
Completed
EADS# Asserted
Stop Grant
Halt
State
Stop Clock
State
Inquire
State
Writeback
Completed
Figure 101. Clock Control State Transitions
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14
Power and Grounding
14.1
Power Connections
The Mobile AMD-K6-2+ processor is a dual voltage device. Two
separate supply voltages are required: V and V . V
CC2
CC2
CC3
provides the core voltage for the processor and V
provides
CC3
the I/O voltage. See “Electrical Data” on page 275 for the value
and range of V
and V
.
CC2
CC3
The re a re 28 V
, 32 V
, a n d 68 V p ins on t he Mob ile
CC3 SS
CC2
AMD-K6-2+ processor. (See “Pin Designations” on page 299 for
all power and ground pin designations.) The large number of
p owe r a n d gr ou n d p in s a r e p r ovid e d t o e n su r e t h a t t h e
p roce ssor a n d p a ck a ge m a in t a in a cle a n a n d st ab le p owe r
distribution network.
For proper operation and functionality, all V
, V
, and V
CC3 SS
CC2
pins must be connected to the appropriate planes in the circuit
board. The power planes have been arranged in a pattern to
simplify routing and minimize crosstalk on the circuit board.
The isolat ion region between two voltage planes must be at
least 0.254 mm if they are in the same layer of the circuit board.
( S e e F i g u r e 1 02 o n p a g e 2 7 2 .) I n o r d e r t o m a i n t a in a
low-impedance current sink and reference, the ground plane
must never be split.
Although the Mobile AMD-K6-2+ processor has two separate
su p p ly volt a ge s, t h e re a re n o sp e cia l p owe r se q u e n cin g
re q u ire m e n t s. Th e b e st p roce d ure is t o m in im ize t h e t im e
between which V
and V
are either both on or both off.
CC2
CC3
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0.254mm (min.) for
isolation region
C20
C17
C18
C5
C6
C21
C22
C23
C24
C25
C19
C7
CC3
CC4
+
+
C1
C2
+
+
CC5
CC6
+
C27
C28
C11
C12
C13
C29
C30
C31
C26
V (I/O) Plane
CC3
V (Core) Plane
CC2
CC1
CC2
Figure 102. Suggested Component Placement
14.2
Decoupling Recommendations
In a d d it ion t o t h e isola t ion re gion m e n t ion e d in “ Powe r
Connections” on page 271, adequate decoupling capacitance is
required between the two system power planes and the ground
plane to minimize ringing and to provide a low-impedance path
for return currents. Suggested decoupling capacitor placement
is shown in Figure 102.
Su r fa ce m ou n t e d ca p a cit or s sh ou ld b e u se d u n d e r t h e
processor’s ZIF socket to minimize resistance and inductance in
t h e le a d le n gt h s wh ile m a in t a in in g m in im a l h e igh t . For
information and recommendations about the specific value,
q u a n t it y, a n d loca t ion of t h e ca p a cit or s, se e t h e Mob ile
®
AMD-K6 Processor Power Supply Design Application Note, order#
22495.
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14.3
Pin Connection Requirements
For proper operation, the following requirements for signal pin
connections must be met:
■ Do not drive address and data signals into large capacitive
loads at high frequencies. If necessary, use buffer chips to
drive large capacitive loads.
■ Leave all NC (no-connect) pins unconnected.
■ Unused inputs should always be connected to an appropriate
signal level.
•
Active Low inputs that are not being used should be
connected to V through a 20-kohm pullup resistor.
CC3
•
Active High inputs that are not being used should be
connected to GND through a pulldown resistor.
■ Reserved signals can be treated in one of the following ways:
•
•
•
As no-connect (NC) pins, in which case these pins are left
unconnected
As pins connected to the system logic as defined by the
industry-standard Super7 and Socket 7 interface
Any combination of NC and Socket 7 pins
■ Keep trace lengths to a minimum.
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15
Electrical Data
15.1
Operating Ranges
Th e Mob ile AMD-K6-2+ p roce ssor is d e sign e d t o p rovid e
functional operation if the voltage and temperature parameters
are within the limits defined in Table 55.
Table 55. Operating Ranges
Parameter
Minimum
Typical
Maximum
Comments
V
1.9 V
2.0 V
2.1 V
Note
CC2
V
3.135 V
3.3 V
3.6 V
85°C
CC3
T
0°C
CASE
Note:
V
CC2 and VCC3 are referenced from V .
SS
15.2
Absolute Ratings
Th e Mob ile AMD-K6-2+ p r oce ssor is n ot d e sign e d t o b e
op e ra t e d b eyon d t h e op e ra t in g ra n ge s list e d in Tab le 55.
E xp osu re t o con d it ion s out sid e t h e se op e ra t in g ra n ge s for
ext e n d e d p e r iod s of t im e ca n a ffe ct lon g-t e r m re liab ilit y.
Permanent damage can occur if the absolute ratings listed in
Table 56 are exceeded.
Table 56. Absolute Ratings
Parameter
Minimum
Maximum
Comments
V
–0.5 V
2.2 V
CC2
V
–0.5 V
–0.5 V
–65°C
–65°C
3.6 V
CC3
V
V + 0.4 V and < 3.8V
Note
PIN
cc3
T
(under bias)
+110°C
+150°C
CASE
T
STORAGE
Note:
V
PIN (the voltage on any I/O pin) must not be greater than 0.4 V above the voltage being applied
CC3
to V . In addition, the VPIN voltage must never exceed 3.8V.
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15.3
DC Characteristics
The DC characteristics of the Mobile AMD-K6-2+ processor are
shown in Table 57.
Table 57. DC Characteristics
Preliminary Data
Symbol
Parameter Description
Comments
Min
Max
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.3 V
2.0 V
+0.8 V
IL
V
V
+0.3V
Note 1
IH
CC3
V
I = 4.0-mA load
0.4 V
OL
OL
V
I
= 3.0-mA load
2.4 V
OH
OH
450 MHz, Note 2,8
475 MHz, Note 2,7
500 MHz, Note 2,8
533 MHz, Note 2,9
550 MHz, Note 2,8
450 MHz, Note 3,8
475 MHz, Note 3,7
500 MHz, Note 3,8
533 MHz, Note 3,9
550 MHz, Note 3,8
Note 4
8.50 A
9.50 A
I
2.0 V Power Supply Current
3.3 V Power Supply Current
CC2
0.66 A
0.67 A
0.68 A
I
CC3
0.69 A
I
Input Leakage Current
Output Leakage Current
±15 µA
±15 µA
–500 µA
500 µA
10 pF
LI
I
Note 4
Note 5
Note 6
LO
I
Input Leakage Current Bias with Pullup
Input Leakage Current Bias with Pulldown
Input Capacitance
IL
I
IH
C
IN
C
Output Capacitance
15 pF
OUT
Notes:
1. VCC3 refers to the voltage being applied to VCC3 during functional operation.
2. VCC2 = 2.1 V — The maximum power supply current must be taken into account when designing a power supply.
3. VCC3 = 3.6 V — The maximum power supply current must be taken into account when designing a power supply.
4. Refers to inputs and I/O without an internal pullup resistor and 0 ≤ V ≤ V
IN
CC3.
5. Refers to inputs with an internal pullup and V = 0.4 V.
IL
6. Refers to inputs with an internal pulldown and V = 2.4 V.
IH
7. This specification applies to components using a CLK frequency of 95 MHz.
8. This specification applies to components using a CLK frequency of 100 MHz.
9. This specification applies to components using a CLK frequency of 97 MHz.
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Table 57. DC Characteristics (continued)
Preliminary Data
Comments
Symbol
Parameter Description
Min
Max
C
I/O Capacitance
CLK Capacitance
20 pF
10 pF
10 pF
15 pF
10 pF
OUT
C
CLK
C
Test Input Capacitance (TDI, TMS, TRST#)
Test Output Capacitance (TDO)
TCK Capacitance
TIN
C
TOUT
C
TCK
Notes:
1. VCC3 refers to the voltage being applied to VCC3 during functional operation.
2. VCC2 = 2.1 V — The maximum power supply current must be taken into account when designing a power supply.
3. VCC3 = 3.6 V — The maximum power supply current must be taken into account when designing a power supply.
4. Refers to inputs and I/O without an internal pullup resistor and 0 ≤ V ≤ V
IN
CC3.
5. Refers to inputs with an internal pullup and V = 0.4 V.
IL
6. Refers to inputs with an internal pulldown and V = 2.4 V.
IH
7. This specification applies to components using a CLK frequency of 95 MHz.
8. This specification applies to components using a CLK frequency of 100 MHz.
9. This specification applies to components using a CLK frequency of 97 MHz.
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15.4
Power Dissipation
Table 58 contains the typical and maximum power dissipation
of the Mobile AMD-K6-2+ processor during normal and reduced
power states.
Table 58. Power Dissipation
6
5
6
7
6
Clock Control State
Comments
Note 1
450 MHz 475 MHz 500 MHz 533 MHz 550 MHz
Design Power
Application Power
Stop Grant/Halt (Maximum)
Stop Clock (Maximum)
Notes:
16.00 W
12.60 W
2.47 W
2.25 W
18.00 W
14.20 W
Note 2
2.47 W
2.25 W
4.40 W
4.00 W
Note 3
Note 4
1. Design Power represents the maximum sustained power dissipated while executing software or instruction
sequences under normal system operation with VCC2 = 2.0 V and VCC3 = 3.3 V. Thermal solutions must use thermal
feedback to limit the processor’s peak power. Specified through characterization.
2. Application Power represents the average power dissipated while executing software or instruction sequences
under normal system operation with VCC2 = 2.0 V and VCC3 = 3.3 V.
3. The CLK signal and the internal PLL are still running but most internal clocking has stopped.
4. The CLK signal, the internal PLL, and all internal clocking has stopped.
5. This specification applies to components using a CLK frequency of 95 MHz.
6. This specification applies to components using a CLK frequency of 100 MHz.
7. This specification applies to components using a CLK frequency of 97 MHz.
278
Electrical Data
Chapter 15
Preliminary Information
®
23446B/0—June 2000
Mobile AMD-K6 -2+ Processor Data Sheet
16
Signal Switching Characteristics
Th e M o b i l e A M D -K 6 -2 + p r o c e s s o r s i g n a l s w i t c h i n g
charact eristics are presented in Table 59 through Table 64.
Valid delay, float, set up, and hold timing specifications a re
list e d . Th e se sp e cifica t ion s a re p rovid e d for t h e syst e m
designer to determine if the timings necessary for the processor
to interface with the system logic are met. Table 59 contains the
switching characteristics of the CLK input. Table 60 contains
the timings for the normal operation signals. Table 62 contains
the timings for RESET and the configuration signals. Table 63
and Table 64 contain the timings for the test operation signals.
All signal timings provided are:
■ Measured between CLK, TCK, or RESET at 1.5 V and the
corresponding signal at 1.5 V—this applies to input and
output signals that are switching from Low to High, or from
High to Low
■ Based on input signals applied at a slew rate of 1 V/ns
between 0 V and 3 V (rising) and 3 V to 0 V (falling)
■ Valid within the operating ranges given in “Operating
Ranges” on page 275
■ Based on a load capacitance (C ) of 0 pF
L
16.1
CLK Switching Characteristics
Table 59 contains the switching characteristics of the CLK input
to the Mobile AMD-K6-2+ processor for 100-MHz bus operation,
as measured at the voltage levels indicated by Figure 103 on
page 280.
The CLK Period Stability specifies the variance (jitter) allowed
between successive periods of the CLK input measured at 1.5 V.
This parameter must be considered as one of the elements of
clock skew between the Mobile AMD-K6-2+ processor and the
system logic.
Chapter 16
Signal Switching Characteristics
279
Preliminary Information
Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
16.2
Clock Switching Characteristics for 100-MHz Bus Operation
Table 59. CLK Switching Characteristics for 100-MHz Bus Operation
Preliminary Data
Symbol
Parameter Description
Figure
Comments
Min
Max
Frequency
33.3 MHz
10.0 ns
100 MHz
In Normal Mode
In Normal Mode
t
CLK Period
103
103
103
103
103
1
t
CLK High Time
CLK Low Time
CLK Fall Time
CLK Rise Time
CLK Period Stability
3.0 ns
3.0 ns
0.15 ns
0.15 ns
2
t
3
t
1.5 ns
1.5 ns
4
t
5
± 250 ps
Note
Note:
Jitter frequency power spectrum peaking must occur at frequencies greater than (Frequency of CLK)/3 or less than 500 kHz.
t2
2.0 V
1.5 V
t3
0.8 V
t4
t5
t1
Figure 103. CLK Waveform
280
Signal Switching Characteristics
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Preliminary Information
®
23446B/0—June 2000
Mobile AMD-K6 -2+ Processor Data Sheet
16.3
Valid Delay, Float, Setup, and Hold Timings
Valid delay and float timings are given for output signals during
functional operation and are given relative to the rising edge of
CLK. Du r in g b ou n d a ry-sca n t e st in g, va lid d e lay a n d floa t
timings for output signals are with respect to the falling edge of
TCK. The maximum valid delay timings are provided to allow a
system designer to determine if setup times to the system logic
can be met. Likewise, the minimum valid delay timings are used
to analyze hold times to the system logic.
Th e se t u p a n d h o ld t im e r e q u ir e m e n t s for t h e Mob ile
AMD-K6-2+ processor input signals must be met by the system
logic to assure the proper operation of the processor. The setup
a n d hold timin gs during fu nct iona l a n d boun da ry-sca n te st
mode are given relative to the rising edge of CLK and TCK,
respectively.
Chapter 16
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281
Preliminary Information
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®
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16.4
Output Delay Timings for 100-MHz Bus Operation
Table 60. Output Delay Timings for 100-MHz Bus Operation
Preliminary Data
Symbol
Parameter Description
Figure
Comments
Min
Max
4.0 ns
7.0 ns
4.0 ns
7.0 ns
4.0 ns
7.0 ns
5.5 ns
7.0 ns
4.5 ns
4.0 ns
7.0 ns
4.0 ns
4.0 ns
7.0 ns
4.0 ns
7.0 ns
4.5 ns
7.0 ns
4.5 ns
7.0 ns
4.5 ns
4.0 ns
4.0 ns
4.0 ns
4.0 ns
7.0 ns
4.0 ns
7.0 ns
t
A[31:3] Valid Delay
1.1 ns
105
106
105
106
105
106
105
106
105
105
106
105
105
106
105
106
105
106
105
106
105
105
105
105
105
106
105
106
6
t
A[31:3] Float Delay
ADS# Valid Delay
7
t
1.0 ns
1.0 ns
1.0 ns
8
t
ADS# Float Delay
9
t
ADSC# Valid Delay
ADSC# Float Delay
AP Valid Delay
10
t
11
t
12
t
AP Float Delay
13
t
APCHK# Valid Delay
BE[7:0]# Valid Delay
BE[7:0]# Float Delay
BREQ Valid Delay
1.0 ns
1.0 ns
14
t
15
t
16
t
1.0 ns
1.0 ns
17
t
CACHE# Valid Delay
CACHE# Float Delay
D/C# Valid Delay
18
t
19
t
1.0 ns
1.3 ns
1.3 ns
20
t
D/C# Float Delay
21
t
D[63:0] Write Data Valid Delay
D[63:0] Write Data Float Delay
DP[7:0] Write Data Valid Delay
DP[7:0] Write Data Float Delay
FERR# Valid Delay
HIT# Valid Delay
22
t
23
t
24
t
25
t
1.0 ns
1.0 ns
1.1 ns
1.0 ns
1.1 ns
26
t
27
t
HITM# Valid Delay
HLDA Valid Delay
28
t
29
t
LOCK# Valid Delay
LOCK# Float Delay
M/IO# Valid Delay
M/IO# Float Delay
30
t
31
t
1.0 ns
32
t
33
282
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Mobile AMD-K6 -2+ Processor Data Sheet
®
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Table 60. Output Delay Timings for 100-MHz Bus Operation (continued)
Preliminary Data
Symbol
Parameter Description
Figure
Comments
Min
Max
4.0 ns
7.0 ns
4.5 ns
4.0 ns
7.0 ns
4.0 ns
7.0 ns
4.0 ns
4.0 ns
7.0 ns
t
PCD Valid Delay
1.0 ns
105
106
105
105
106
105
106
105
105
106
34
t
PCD Float Delay
PCHK# Valid Delay
PWT Valid Delay
PWT Float Delay
SCYC Valid Delay
SCYC Float Delay
SMIACT# Valid Delay
W/R# Valid Delay
W/R# Float Delay
35
t
1.0 ns
1.0 ns
36
t
37
t
38
t
1.0 ns
39
t
40
t
1.0 ns
1.0 ns
41
t
42
t
43
Chapter 16
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®
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16.5
Input Setup and Hold Timings for 100-MHz Bus Operation
Table 61. Input Setup and Hold Timings for 100-MHz Bus Operation
Preliminary Data
Symbol
Parameter Description
Figure
Comments
Min
Max
t
A[31:5] Setup Time
3.0 ns
1.0 ns
3.0 ns
1.0 ns
3.5 ns
1.0 ns
1.7 ns
1.0 ns
3.5 ns
1.0 ns
3.0 ns
1.0 ns
3.0 ns
1.0 ns
1.7 ns
1.5 ns
1.7 ns
1.5 ns
3.0 ns
1.0 ns
1.7 ns
1.0 ns
1.7 ns
1.0 ns
107
107
107
107
107
107
107
107
107
107
107
107
107
107
107
107
107
107
107
107
107
107
107
107
44
t
A[31:5] Hold Time
45
t
A20M# Setup Time
A20M# Hold Time
Note 1
Note 1
46
t
47
t
AHOLD Setup Time
AHOLD Hold Time
48
t
49
t
AP Setup Time
50
t
AP Hold Time
51
t
BOFF# Setup Time
BOFF# Hold Time
52
t
53
t
BRDY# Setup Time
BRDY# Hold Time
54
t
55
t
BRDYC# Setup Time
BRDYC# Hold Time
D[63:0] Read Data Setup Time
D[63:0] Read Data Hold Time
DP[7:0] Read Data Setup Time
DP[7:0] Read Data Hold Time
EADS# Setup Time
EADS# Hold Time
56
t
57
t
58
t
59
t
60
t
61
t
62
t
63
t
EWBE# Setup Time
EWBE# Hold Time
64
t
65
t
FLUSH# Setup Time
FLUSH# Hold Time
Note 2
Note 2
66
t
67
Notes:
1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and
hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.
2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and
hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must
remain asserted at least two clocks.
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®
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Table 61. Input Setup and Hold Timings for 100-MHz Bus Operation (continued)
Preliminary Data
Symbol
Parameter Description
Figure
Comments
Min
Max
t
HOLD Setup Time
1.7 ns
1.5 ns
1.7 ns
1.0 ns
1.7 ns
1.0 ns
1.7 ns
1.0 ns
1.7 ns
1.0 ns
3.0 ns
1.0 ns
1.7 ns
1.0 ns
1.7 ns
1.0 ns
1.7 ns
1.0 ns
1.7 ns
1.0 ns
1.7 ns
1.0 ns
107
107
107
107
107
107
107
107
107
107
107
107
107
107
107
107
107
107
107
107
107
107
68
t
HOLD Hold Time
IGNNE# Setup Time
IGNNE# Hold Time
INIT Setup Time
INIT Hold Time
69
t
Note 1
Note 1
Note 2
Note 2
Note 1
Note 1
70
t
71
t
72
t
73
t
INTR Setup Time
INTR Hold Time
74
t
75
t
INV Setup Time
76
t
INV Hold Time
77
t
KEN# Setup Time
KEN# Hold Time
NA# Setup Time
NA# Hold Time
78
t
79
t
80
t
81
t
NMI Setup Time
NMI Hold Time
Note 2
Note 2
Note 2
Note 2
Note 1
Note 1
82
t
83
t
SMI# Setup Time
SMI# Hold Time
STPCLK# Setup Time
STPCLK# Hold Time
WB/WT# Setup Time
WB/WT# Hold Time
84
t
85
t
86
t
87
t
88
t
89
Notes:
1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and
hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.
2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup and
hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and must
remain asserted at least two clocks.
Chapter 16
Signal Switching Characteristics
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Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
16.6
RESET and Test Signal Timing
Table 62. RESET and Configuration Signals for 100-MHz Bus Operation
Preliminary Data
Symbol
Parameter Description
Figure
Comments
Min
1.7 ns
Max
t
RESET Setup Time
108
108
108
108
108
108
90
t
RESET Hold Time
1.0 ns
91
t
RESET Pulse Width, V and CLK Stable
15 clocks
1.0 ms
1.0 ms
2 clocks
92
CC
t
RESET Active After V and CLK Stable
93
CC
t
BF[2:0] Setup Time
BF[2:0] Hold Time
Note 3
Note 3
94
t
95
t
Intentionally left blank
Intentionally left blank
Intentionally left blank
FLUSH# Setup Time
FLUSH# Hold Time
FLUSH# Setup Time
FLUSH# Hold Time
96
t
97
t
98
t
1.7 ns
1.0 ns
108
108
108
108
Note 1
Note 1
Note 2
Note 2
99
t
100
t
2 clocks
2 clocks
101
t
102
Notes:
1. To be sampled on a specific clock edge, setup and hold times must be met the clock edge before the clock edge on which RESET
is sampled negated.
2. If asserted asynchronously, these signals must meet a minimum setup and hold time of two clocks relative to the negation of
RESET.
3. BF[2:0] must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of RESET.
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®
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Table 63. TCK Waveform and TRST# Timing at 25 MHz
Preliminary Data
Symbol
Parameter Description
TCK Frequency
Figure
Comments
Min
Max
25 MHz
109
109
109
109
109
109
110
t
TCK Period
40.0 ns
14.0 ns
14.0 ns
103
t
TCK High Time
TCK Low Time
TCK Fall Time
TCK Rise Time
TRST# Pulse Width
104
t
105
t
5.0 ns
5.0 ns
Note 1, 2
Note 1, 2
106
t
107
t
30.0 ns
Asynchronous
108
Notes:
1. Rise/Fall times can be increased by 1.0 ns for each 10 MHz that TCK is run below its maximum frequency of 25 MHz.
2. Rise/Fall times are measured between 0.8 V and 2.0 V.
Table 64. Test Signal Timing at 25 MHz
Preliminary Data
Symbol
Parameter Description
Figure
Notes
Min
Max
t
TDI Setup Time
5.0 ns
9.0 ns
5.0 ns
9.0 ns
3.0 ns
111
111
111
111
111
111
111
111
111
111
Note 2
Note 2
Note 2
Note 2
Note 1
Note 1
Note 1
Note 1
Note 2
Note 2
109
t
TDI Hold Time
110
t
TMS Setup Time
111
t
TMS Hold Time
112
t
TDO Valid Delay
13.0 ns
16.0 ns
13.0 ns
16.0 ns
113
t
TDO Float Delay
114
t
All Outputs (Non-Test) Valid Delay
All Outputs (Non-Test) Float Delay
All Inputs (Non-Test) Setup Time
All Inputs (Non-Test) Hold Time
3.0 ns
115
t
116
t
5.0 ns
9.0 ns
117
t
118
Notes:
1. Parameter is measured from the TCK falling edge.
2. Parameter is measured from the TCK rising edge.
Chapter 16
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287
Preliminary Information
®
Mobile AMD-K6 -2+ Processor Data Sheet
23446B/0—June 2000
WAVEFORM
INPUTS
OUTPUTS
Must be steady
Steady
Can change from
High to Low
Changing from High to Low
Changing from Low to High
Changing, State Unknown
Can change
from Low to High
Don’t care, any
change permitted
(Does not apply)
Center line is high
impedance state
Figure 104. Diagrams Key
T
T
x
x
1.5 V
CLK
Max
tv
Min
Output Signal
Valid n
Valid n +1
v = 6, 8, 10, 12, 14, 15, 17, 18, 20, 22, 24, 26, 27, 28, 29, 30, 32, 34, 36, 37, 39, 41, 42
Figure 105. Output Valid Delay Timing
288
Signal Switching Characteristics
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Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
T
T
T
T
x
x
x
x
1.5 V
CLK
tf
Output Signal
Valid
tv
Min
v = 6, 8, 10, 12, 15, 18, 20, 22, 24, 30, 32, 34, 37, 39, 42
f = 7, 9, 11, 13, 16, 19, 21, 23, 25, 31, 33, 35, 38, 40, 43
Figure 106. Maximum Float Delay Timing
T
T
T
T
x
x
x
x
1.5 V
CLK
ts
th
Input Signal
s = 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72, 74, 76, 78, 80, 82, 84, 86, 88
h = 45, 47, 49, 51, 53, 55, 57, 59, 61, 63, 65, 67, 69, 71, 73, 75, 77, 79, 81, 83, 85, 87, 89
Figure 107. Input Setup and Hold Timing
Chapter 16
Signal Switching Characteristics
289
Preliminary Information
®
Mobile AMD-K6 -2+ Processor Data Sheet
23446B/0—June 2000
T
T
x
x
1.5 V
CLK
• • •
• • •
t90
t91
RESET
1.5 V
1.5 V
t92, 93
t99
t100
FLUSH#
(Synchronous)
• • •
FLUSH#
(Asynchronous)
• • •
t101
t102
BF[2:0]
(Asynchronous)
• • •
t94
t95
Figure 108. Reset and Configuration Timing
290
Signal Switching Characteristics
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Mobile AMD-K6 -2+ Processor Data Sheet
t104
2.0 V
1.5 V
0.8 V
t105
t106
t107
t103
Figure 109. TCK Waveform
t108
1.5 V
Figure 110. TRST# Timing
t103
1.5 V
TCK
TDI, TMS
TDO
t109, 111 t110, 112
t114
t113
t116
t115
Output
Signals
Input
Signals
t117
t118
Figure 111. Test Signal Timing Diagram
Chapter 16
Signal Switching Characteristics
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Preliminary Information
Mobile AMD-K6 -2+ Processor Data Sheet
®
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292
Signal Switching Characteristics
Chapter 16
Preliminary Information
Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
17
Thermal Design
17.1
Package Thermal Specifications
The Mobile AMD-K6-2+ processor operating specifications call
for the case temperature (T ) to be in the range of 0°C to 85°C.
C
The ambient temperature (T ) is not specified as long as the
A
case temperature is not violated. The case temperature must be
measured on the top center of the package. Table 65 shows the
Mobile AMD-K6-2+ processor thermal specifications.
Table 65. Package Thermal Specifications
Maximum Design Power
475 MHz 500 MHz 533 MHz
16.00 W 18.00 W
T
C
Case Temperature
450 MHz
550 MHz
0°C – 85°C
Figure 112 on page 293 shows the thermal model of a processor
w i t h a p a s s ive t h e r m a l s o l u t i o n . Th e c a s e -t o -a m b i e n t
t e m p e ra t u re (T ) ca n b e ca lcu la t e d fr om t h e followin g
CA
equation:
TCA = PMAX • θ
CA
= PMAX • ( θI F + θ
)
SA
Where:
P
= Ma xi mum Powe r Cons umpt i on
MAX
CA
θ
θ
θ
= Ca s e - t o- Ambi e nt Ther ma l Re s i s t a nc e
= I nt e r f a c e Ma t e r i a l The r ma l Re s i s t anc e
= Si nk- t o- Ambi e nt Ther ma l Re s i s t a nc e
I F
SA
Thermal
Resistance
(°C/W)
Temperature
(Ambient)
θSA
TCA
θCA
Heat Exchange Device
Sink
Case
θIF
Figure 112. Thermal Model
Chapter 17
Thermal Design
293
Preliminary Information
Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
Figure 113 illustrates the case-to-ambient temperature (T ) in
CA
relation to the power consu mption (X-axis) and th e thermal
r e sist a n ce (Y-a xis). If t h e p owe r con su m p t ion a n d ca se
t e m p e r a t u r e a r e k n ow n , t h e t h e r m a l r e sist a n c e ( θ
)
CA
requirement can be calculated for a given ambient temperature
(T ) value.
A
6.0
5.0
4.0
3.0
2.0
1.0
0.0
T = T - T
A
CA
C
30° C
25° C
20° C
15° C
6 W
9 W
12 W
15 W
18 W
Power Consumption (Watts)
Figure 113. Power Consumption versus Thermal Resistance
The thermal resistance of a heatsink is determined by the heat
d issip a t ion su r fa ce a re a , t h e m a t e r ia l a n d sh a p e of t h e
h e a t sin k , a n d t h e a ir flow volu m e a cross t h e h e a t sin k . In
ge n e ra l, t h e la rge r t h e su r fa ce a re a t he lowe r t he t h e r m a l
resistance.
Th e re q u ired t h e r m a l re sist a n ce of a h e a t sin k (θSA) ca n be
calculated using the following example:
If:
T = 85° C
C
T = 55° C
A
MAX
P
= 18. 00 W
Then:
294
Thermal Design
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23446B/0—June 2000
Mobile AMD-K6 -2+ Processor Data Sheet
TC – TA
------------------
PMAX
30 °C
18. 00 W
(°C ⁄ W)
θCA
≤
= --------------------- = 1. 67
Thermal grease is recommended as interface material because
it provides the lowest thermal resistance (approx. 0.20°C/W).
The required thermal resistance (θ ) of the heat sink in this
SA
example is calculated as follows:
θ
= θ – θ
= 1. 67 – 0. 20 = 1. 47( ° C/ W)
I F
SA
CA
Heat Dissipation Path
Figure 114 illustrates the heat dissipation path of the processor.
Due to the lower thermal resistance between the processor die
junction and case, most of the heat generated by the processor
is t ra n sfe r re d from t h e t op su r fa ce of t h e ca se . Th e sm a ll
amount of heat generated from the bottom side of the processor
where the processor socket blocks the convection can be safely
ignored.
Ambient Temperature
Thin Lid
Case temperature
Figure 114. Processor’s Heat Dissipation Path
Chapter 17
Thermal Design
295
Preliminary Information
Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
Measuring Case
Temperature
The processor case temperature is measured to ensure that the
t h e r m a l s o l u t i o n m e e t s t h e p r o c e s s o r ’s o p e r a t i o n a l
specification. This temperature should be measured on the top
center of the package where most of the hea t is dissipat ed.
Figure 115 shows the correct location for measuring the case
temperature. If a heatsink is installed while measuring, the
thermocouple must be installed into the heatsink via a small
hole drilled through the heatsink base (for example, 1/16 of an
in ch). The thermocouple is then at tached to the base of the
heatsink and the small hole filled using thermal epoxy, allowing
the tip of the thermocouple to touch the top of the processor
case.
Thermally Conductive Epoxy
Thermocouple
Figure 115. Measuring Case Temperature
For more information on thermal design considerations, see the
®
AMD-K6 Processor Therm al Solution Design Application Note,
order# 21085.
296
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23446B/0—June 2000
Mobile AMD-K6 -2+ Processor Data Sheet
18
Pin Description Diagrams
Address Pins
Control/Parity Pins
Test Pins
V Pins
SS
NC, INC (Internal No Connect) Pins
VCC2 Pins
RSVD (Reserved) Pins
VCC3 Pins
Chip Positioning Key Pin
Data Pins
B
D
F
H
K
M
P
R
T
V
X
Z
AB AD AF AH AK AM
AA AC AE AG AJ AL AN
A
C
E
G
J
L
N
Q
S
U
W
Y
37
V
V
ss
V
V
V
V
V
V
ss
NC
D9
V
V
V
V
V
cc3
V
V
cc3
A22
V
V
cc3
cc3
ss
cc3
cc3
cc3
cc3
cc3
V
cc3
cc3
cc3
cc3
cc3
36
35
V
V
V
V
V
V
D11
D13
D16
D20
DP0
V
V
V
ss
V
V
A28
A29
A5
D4
D5
A30
A4
ss
ss
ss
ss
ss
ss
IGNNE# INC
INTR
ss
ss
ss
ss
ss
V
RSVD
RSVD
NC
TDI
ss
D6
D2
D15
D10
D14
D17
D21
INC
A25
A31
D1
D3
A24
A27
VID1
A6
BF2
RSVD
A3
A7
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
TMS
A21
INC
VID2
V
STPCLK#
D8
A26
TCK
BF1
D0
INC
SMI#
INIT
NMI
cc3
V
TRST#
NC
V
cc3
NC
A23
D18
D22
D7
TDO
RSVD
BF0
cc3
D12
DP1
D19
D23
D26
VID0
A8
V
V
ss
A11
A12
A10
ss
V
ss
A9
V
ss
V
V
V
cc3
cc3
cc3
V
ss
V
ss
A13
A15
A17
A19
V
V
ss
V
V
D24
A14
A16
cc3
cc3
cc3
V
V
ss
ss
V
ss
VID3
V
V
DP2
D25
cc3
cc3
V
V
ss
ss
V
ss
V
NC
A18
A20
V
cc3
cc3
V
V
ss
ss
D28
D30
DP3
V
ss
D27
D29
V
V
V
cc3
cc3
cc3
Top
View
V
V
ss
ss
RESET
V
ss
V
V
V
NC
V
cc3
cc3
cc2
V
V
ss
ss
CLK
ss
V
VID4
D31
D32
D34
D36
SCYC
V
cc2
cc2
V
V
BE7#
D33
ss
ss
NC
V
V
cc2
BE6#
V
cc2
cc2
V
V
ss
BE5#
D35
ss
V
V
ss
V
V
ss
BE4#
cc2
cc2
V
V
BE3#
BE1#
D37
D39
D40
ss
ss
V
V
V
BE2#
V
ss
cc2
cc2
cc2
V
V
ss
ss
V
ss
BE0#
V
D38
DP4
D45
D42
V
cc2
cc2
V
A20M#
V
ss
ss
FLUSH#
W/R#
VCC2H/L#
V
ss
V
D46
D49
INC
cc2
V
HIT#
ADS#
ss
D44
D48
D50
DP5
D51
DP6
D
D41
D53
D55
D58
D60
D61
PCD
RSVD APCHK#
FERR# RSVD
INV
KEN#
NA# WB/WT#
HITM#
DP7
D56
D43
RSVD M/IO# AHOLD#
LOCK#
D62
BRDY# BOFF# HOLD RSVD PCHK#
D/C#
D59
RSVD
EADS#
V
ss
D47
NC
D52
D54
D57
RSVD
RSVD
EWBE#
RSVD
SMIACT# HLDA
V
V
ss
D63
RSVD
BRDYC# RSVD
PWT
INC
CACHE#
V
V
V
V
ss
V
V
V
ss
V
ss
V
V
V
ss
V
ss
ss
ADSC#
VCC2DET
ss
ss
ss
ss
cc2
AP
ss
ss
INC
V
V
V
V
V
V
V
cc2
V
cc2
V
V
V
V
V
cc2
BREQ
cc2
cc2
cc2
cc2
cc2
cc2
cc2
cc2
cc2
cc2
B
D
F
H
K
M
P
R
T
V
X
Z
AB AD AF AH AK AM
AA AC AE AG AJ AL AN
A
C
E
G
J
L
N
Q
S
U
W
Y
®
Figure 116. Mobile AMD-K6 -2+ Processor Top-Side View
Chapter 18 Pin Description Diagrams
297
Preliminary Information
®
Mobile AMD-K6 -2+ Processor Data Sheet
23446B/0—June 2000
Address Pins
Test Pins
Control/Parity Pins
V Pins
SS
NC, INC (Internal No Connect) Pins
RSVD (Reserved) Pins
V
CC2 Pins
CC3 Pins
Data Pins
V
Chip Positioning Key Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
AN
AM
AL
AK
AJ
AH
AG
AF
AN
AM
AL
V
VID1
INC
INC VCC2H/L# FLUSH#
V
V
V
V
cc2
A10
A11
A6
V
V
V
V
V
cc3
V
V
V
cc3
ss
cc
2
cc
2
cc
2
cc
2
cc
2
cc
3
cc
3
cc
3
V
V
V
V
V
V
V
V
V
V
V
A8
A30
ADSC# EADS# W/R#
ss
ss
ss
BE2# BE4#
D/C# HIT# A20M# BE1# BE3# BE5#
ss
ss
ss
ss
ss
ss
ss
ss
ss
A4
A29
A26
BE0#
PWT
INC
VCC2DET
AP
V
ss
SCYC
NC
HITM#
BE6#
A20
A12
V
A16
A14
A3
A25
A24
A7
A18
AK
AJ
BE7# CLK
V
RESET A19
V
A17
A15
A13
A9
A5
A28
A22
BREQ HLDA ADS#
V
V
V
V
V
V
V
ss
V
ss
V
ss
NC
A31
NC
ss
ss
cc
2
ss
ss
cc
3
ss
ss
cc
3
AH
AG
AF
AE
AD
AC
V
LOCK#
VID0
ss
SMIACT#
V
V
PCD
A27
cc
2
cc
3
V
PCHK#
V
ss
ss
A21
A23 RSVD
AE
AD
V
V
APCHK#
cc
2
RSVD
cc3
V
ss
V
INTR
INC
RSVD
RSVD
ss
V
AC
AB
AA
Z
Y
X
W
V
cc
2
NMI
RSVD
WB/WT#
NA#
cc
3
AB
AA
Z
Y
X
W
V
V
SMI#
ss
ss
HOLD
V
INIT
V
cc3
IGNNE#
V
INC
cc
2
RSVD
V
BOFF#
ss
ss
V
BRDYC#
INC
V
cc3
BF0
NC
cc
2
V
V
ss
BRDY#
BF1
ss
V
EWBE#
BF2
KEN#
V
cc3
cc
2
V
U
V
U
V
AHOLD
V
ss
STPCLK#
V
ss
Bottom
View
CACHE#
V
V
V
cc3
ss
INV
ss
cc
2
cc
3
T
S
R
Q
P
N
T
S
R
Q
P
N
V
V
M/IO#
ss
V
cc
3
V
cc3
NC
TRST#
TDO
NC
V
cc
2
RSVD RSVD
RSVD
V
V
VID2
RSVD
ss
ss
V
V
V
FERR#
RSVD
cc
2
cc
3
V
V
ss
RSVD
TMS
TDI
ss
cc2
DP7
D60
D58
D53
D49
D63
V
cc
3
M
L
K
M
L
K
J
H
G
V
V
ss
D62
ss
TCK
V
V
V
cc
2
D61
cc
3
RSVD
cc
3
V
V
ss
D59
D56
D51
D0
ss
J
H
G
V
cc
2
RSVD
INC
D2
V
cc3
D57
D55
V
V
ss
ss
V
D3
D1
cc
2
V
cc3
F
E
D
C
F
E
D
C
DP6
D5
D4
DP5
D46
D40
DP4
D54
D52
D42
D39
V
V
V
VID4
DP3
V
V
V
VID3
D23
V
V
V
ss
D7
D6
D10
D15
V
cc3
ss
ss
cc
D33
D32
2
ss
cc
3
ss
cc
3
ss
D48
D47
D43
D44
D37
D36
D35
D30
D28
D27
D26
D19
DP1
D20
D12
D16
D8
DP0
D11
NC
D45
D38
D34
D31 D29
D25
DP2 D24
D21
D17
D22
D14
D18
D9
B
A
B
A
V
V
V
V
V
V
V
V
ss
V
ss
V
V
ss
V
ss
V
ss
D13
cc
2
ss
ss
ss
ss
ss
ss
ss
V
D41
V
V
V
V
V
V
V
V
V
V
V
V
cc3
NC
ss
cc
2
cc
2
cc
2
cc
2
cc
2
cc
2
cc
3
cc
3
cc
3
cc
3
cc
3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
®
Figure 117. Mobile AMD-K6 -2+ Processor Bottom-Side View
298
Pin Description Diagrams
Chapter 18
Preliminary Information
Mobile AMD-K6 -2+ Processor Data Sheet
®
23446B/0—June 2000
19
Pin Designations
®
Mobile AMD-K6 -2+ Processor Functional Grouping
Address
Data
Control
Control/Test
NC
V
V
V
ss
cc2
cc3
Pin
Name
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin
No.
Pin
Name
Pin
No.
Pin
No.
Pin
No.
Pin
No.
Pin
No.
A3
AL-35
D0
K-34
A20M#
ADS#
AK-08
A-37
A-07
A-19
A-03 AM-20
B-06 AM-22
B-08 AM-24
B-10 AM-26
B-12 AM-28
B-14 AM-30
B-16 AN-37
B-18
A4
AM-34
AK-32
AN-33
AL-33
AM-32
AK-30
AN-31
AL-31
AL-29
AK-28
AL-27
AK-26
AL-25
AK-24
AL-23
AK-22
AL-21
AF-34
AH-36
AE-33
AG-35
AJ-35
D1
G-35
J-35
AJ-05
AM-02
V-04
C-01
S-33
A-09
A-21
Voltage ID
A5
D2
ADSC#
AHOLD
APCHK#
BE0#
A-11
A-23
A6
D3
G-33
F-36
F-34
E-35
E-33
D-34
C-37
C-35
B-36
D-32
B-34
C-33
A-35
B-32
C-31
A-33
D-28
B-30
C-29
A-31
D-26
C-27
C-23
D-24
C-21
D-22
C-19
D-20
C-17
C-15
D-16
C-13
D-14
C-11
D-12
C-09
D-10
D-08
A-05
E-09
B-04
D-06
C-05
E-07
C-03
D-04
E-05
D-02
F-04
E-03
G-05
E-01
G-03
H-04
J-03
S-35
A-13
A-25
A7
D4
AE-05
AL-09
AK-10
AL-11
AK-12
AL-13
AK-14
AL-15
AK-16
Z-04
X-04
Y-03
AJ-01
U-03
AK-18
AK-04
AM-04
W-03
Q-05
AN-07
AK-06
AL-05
AJ-03
AB-04
AA-35
AA-33
AD-34
U-05
W-33
AJ-15
AJ-23
AL-19
A-15
A-27
VID[4]
VID[3]
VID[2]
VID[1]
VID[0]
E-17
A8
D5
A-17
A-29
E-25
A9
D6
BE1#
B-02
E-21
R-34
AN-35
AH-32
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
D7
BE2#
E-15
E-27
D8
BE3#
G-01
J-01
E-37
B-20
D9
BE4#
G-37
J-37
B-22
BE5#
INC
L-01
B-24
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
BE6#
N-01
Q-01
S-01
L-33
L-37
B-26
BE7#
B-28
Bus Frequency
Divisor
H-34
BOFF#
BRDY#
BRDYC#
BREQ
CACHE#
CLK
N-37
Q-37
S-37
E-11
Y-35
U-01
W-01
Y-01
E-13
Z-34
E-19
AC-35
AL-07
AN-01
AN-03
T-34
E-23
BF0
BF1
BF2
Y-33
X-34
W-35
AA-01
AC-01
AE-01
AG-01
AJ-11
AN-09
AN-11
AN-13
AN-15
AN-17
AN-19
U-33
U-37
W-37
Y-37
E-29
E-31
D/C#
H-02
EADS#
EWBE#
FERR#
FLUSH#
HIT#
H-36
AA-37
AC-37
AE-37
AG-37
AJ-19
AJ-29
AN-21
AN-23
AN-25
AN-27
AN-29
K-02
K-36
Test
RSVD
AH-34
AG-33
AK-36
AK-34
AM-36
AJ-33
M-02
M-36
TCK
TDI
M-34
N-35
N-33
P-34
Q-33
HITM#
HLDA
HOLD
IGNNE#
INIT
P-02
J-33
P-36
L-35
TDO
TMS
TRST#
R-02
P-04
R-36
Q-03
Q-35
R-04
T-02
INTR
T-36
INV
U-35
S-03
S-05
Parity
KEN#
W-05
AH-04
T-04
V-02
LOCK#
M/IO#
NA#
V-36
AA-03
AC-03
AC-05
AD-04
AE-03
AE-35
X-02
AP
AK-02
D-36
D-30
C-25
D-18
C-07
F-06
Y-05
X-36
DP0
DP1
DP2
DP3
DP4
DP5
DP6
DP7
NMI
PCD
PCHK#
PWT
RESET
SCYC
SMI#
AC-33
AG-05
AF-04
AL-03
AK-20
AL-17
AB-34
AG-03
V-34
Z-02
Z-36
AB-02
AB-36
AD-02
AD-36
AF-02
F-02
N-05
SMIACT#
STPCLK#
VCC2DET
VCC2H/L#
W/R#
AF-36
AH-02
AJ-07
AL-01
AN-05
AM-06
AA-05
AJ-09
AJ-13
WB/WT#
AJ-17
AJ-21
AJ-25
AJ-27
AJ-31
AJ-37
AL-37
AM-08
AM-10
AM-12
AM-14
AM-16
AM-18
J-05
K-04
L-05
L-03
M-04
N-03
Chapter 19
Pin Designations
299
Preliminary Information
®
Mobile AMD-K6 -2+ Processor Data Sheet
23446B/0—June 2000
300
Pin Designations
Chapter 19
Preliminary Information
®
23446B/0—June 2000
Mobile AMD-K6 -2+ Processor Data Sheet
20
Package Specifications
20.1
321-Pin Staggered CPGA Package Specification
Table 66. 321-Pin Staggered CPGA Package Specification
Millimeters
Inches
Symbol
Notes
Max
Min
Max
49.78
45.85
32.89
45.10
3.63
1.52
Min
1.940
1.795
1.221
1.768
0.115
0.051
0.120
0.017
0.090
0.045
0.060
0.060
—
A
B
C
D
E
F
49.28
45.59
31.01
44.90
2.91
1.30
3.05
0.43
2.29
1.14
1.960
1.805
1.295
1.776
0.143
0.060
0.130
0.020
0.110
0.055
0.090
0.100
G
H
M
N
d
3.30
0.51
2.79
1.40
1.52
1.52
—
2.29
2.54
0.13
e
f
0.005
Flatness
Figure 118. 321-Pin Staggered CPGA Package Specification
Chapter 20 Package Specifications
301
Preliminary Information
®
Mobile AMD-K6 -2+ Processor Data Sheet
23446B/0—June 2000
302
Package Specifications
Chapter 20
Preliminary Information
Mobile AMD-K6®-2+ Processor Data Sheet
23446B/0—June 2000
21
Ordering Information
Standard Products
AMD st a n d a rd m ob ile p rod u ct s a re ava ilab le in seve ra l ope ra t in g ra n ge s. The
ordering part number (OPN) is formed by a combination of the elements below.
AMD-K6-2+ /550
A C Z
Case Temperature
Z = 0°C–85°C
Operating Voltage
C = 1.9 V–2.1 V (Core) / 3.135 V–3.6 V (I/O)
Package Type
A = 321-pin CPGA
Performance Rating
/533 /500 /475 /450
/550
Family/Core
AMD-K6-2+
Table 67. Valid Ordering Part Number Combinations
OPN
Package Type
Operating Voltage
1.9V–2.1V (Core)
3.135V–3.6V (I/O)
1.9V–2.1V (Core)
3.135V–3.6V (I/O)
1.9V–2.1V (Core)
3.135V–3.6V (I/O)
1.9V–2.1V (Core)
3.135V–3.6V (I/O)
1.9V–2.1V (Core)
3.135V–3.6V (I/O)
Case Temperature
AMD-K6-2+/550ACZ
321-pin CPGA
0°C–85°C
AMD-K6-2+/533ACZ
AMD-K6-2+/500ACZ
AMD-K6-2+/475ACZ
AMD-K6-2+/450ACZ
321-pin CPGA
321-pin CPGA
321-pin CPGA
321-pin CPGA
0°C–85°C
0°C–85°C
0°C–85°C
0°C–85°C
Note:
This table lists configurations planned to be supported in volume for this device. Consult the local
AMD sales office to confirm availability of specific valid combinations and to check on newly-released
combinations.
Chapter 21
Ordering Information
303
Preliminary Information
Mobile AMD-K6®-2+ Processor Data Sheet
23446B/0—June 2000
304
Ordering Information
Chapter 21
Preliminary Information
®
23446B/0—June 2000
Mobile AMD-K6 -2+ Processor Data Sheet
Index
BRDY#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
BRDYC# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
BREQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
BSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Built-In Self-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Burst
Numerics
100-MHz Bus
input setup and hold timings. . . . . . . . . . . . . . . . . . . . . . 284
321-Pin Staggered CPGA
package specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
reads, pipelined . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
ready copy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97, 186
writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Bus
address . . . . . . . . . . . . 90–93, 102, 139, 160, 164, 166, 209
arbitration cycles, inquire and . . . . . . . . . . . . . . . . . . . . 154
backoff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
cycles, special . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
3DNow! Technology . . . . . . . . 7, 9–10, 13–14, 16–18, 21, 55,
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118, 185, 189, 206
execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17–18
instruction compatibility, floating-point and . . . . . . . . . 225
instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83–84, 226
register operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
A
A[31:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
A20M# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Masking of Cache Accesses . . . . . . . . . . . . . . . . . . . . . . . 214
Acknowledge, Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Address
data . . . . . . . . . . . . . . . . . . . 90, 93, 96, 100–101, 116, 119,
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142–144, 160, 166, 170
enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
hold request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
state machine diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Bus Frequency Divisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Bus States
address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
data-NA# requested . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
idle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
pipeline address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
pipeline data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
BYPASS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
bus . . . . . . . . . . . . . . . 88–93, 102, 139, 160, 164, 166, 209
hold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
parity check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
stack, return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ADS# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
ADSC# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
AHOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
-initiated inquire hit to modified line . . . . . . . . . . . . . . . 164
-initiated inquire hit to shared or exclusive line . . . . . . 162
-initiated inquire miss . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Allocate, Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
AP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
APCHK#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Architecture
internal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–20
Asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
C
Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1, 9–10
branch target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
flush. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
B
Backoff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
BE[7:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
BF[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94, 185
BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Bits, Predecode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10, 194
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
BOFF# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95, 168
locked operation with . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Boundary Scan
register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
test access port (TAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
BR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Branch
execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
history table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
L1. . . . . . . . . . . . . . 9–10, 38, 150, 154, 160, 164, 176, 191,
. . . . . . . . . . . . . . . . . . . . . . . . . 200–201, 204, 209, 214, 239
L2. . . . . . . . . . . . . . . . . . . . 9–10, 39, 42–43, 150, 154, 160,
. . . . . . . . . . . . . . . . . . . . . . . . . 164, 176, 191, 200, 253–255
L3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251–252
MESI states in the data . . . . . . . . . . . . . . . . . . . . . . . . . . 193
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191, 217
states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6, 9
CACHE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98, 196
Cacheable
access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
page, write to a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Cache-Line
fills. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198–199, 253
prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1, 9, 20
prediction logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 18–19
target cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Index
305
Preliminary Information
®
Mobile AMD-K6 -2+ Processor Data Sheet
23446B/0—June 2000
DR5–DR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
DR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
DR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Decode, Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1, 7
Decoupling Recommendations . . . . . . . . . . . . . . . . . . . . . . 272
Descriptions, Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Designations, Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200, 211
Capture-DR state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Capture-IR state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . .293–294, 296
Centralized Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
CLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Clock Control
Device Identification Register . . . . . . . . . . . . . . . . . . 245–246
Diagrams, Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
states
DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245–246
Disabling, Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
DP[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
DR3–DR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
DR5–DR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
DR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
DR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Driven . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
stop clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
stop grant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265–266
stop grant inquire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Clock States
stop clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
stop grant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Coherency States, Writethrough vs. Writeback . . . . . . . . . 214
Coherency, Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Compatibility, Floating-Point, MMX, and 3DNow!
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Configuration and Initialization, Power-on . . . . . . . . . . . . 185
Connection Requirements, Pin . . . . . . . . . . . . . . . . . . . . . . 273
Connections, Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Control
register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
unit, scheduler/instruction . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Counter, Time Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Cycle
hold and hold acknowledge . . . . . . . . . . . . . . . . . . . . . . . 154
shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Cycles
E
EADS# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
EFER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37, 188, 217
EFLAGS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Electrical Specifications
absolute ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Enhanced Power Management
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Register (EPMR) . . . . . . . . . . . . . . . . . . . . . . . . 44, 131–132
Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . 263, 266
Environment, Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
EWBE Control (EWBEC). . . . . . . . . . . . . . . . . . . . . . . . . . . 217
EWBE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103, 217
Exception . . . 91–92, 101, 104, 116, 178, 225, 237, 260–262
debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26–27
floating-point . . . . . . . . . . . . . . . . . . . . . . 104, 108, 223–225
handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
machine check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Exceptions
and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
floating-point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
handling floating-point . . . . . . . . . . . . . . . . . . . . . . . . . . 223
MMX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Exceptions, Interrupts, and Debug in SMM . . . . . . . . . . . 237
Execution
bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
inquire . . . . . . . . . . . . 87–92, 102, 106–107, 120, 125, 150,
. . . . . . . . . . . . . . . . . . . . 154, 156, 158, 160, 162–164, 166,
. . . . . . . . . . . . . . . . . . . . .168, 172, 209, 214, 251, 263–266
inquire and bus arbitration . . . . . . . . . . . . . . . . . . . . . . . 154
interrupt acknowledge . . . . . . . . . . 88, 91, 93, 99, 114, 125
locked . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
pipelined . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10, 89
pipelined write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
special . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234, 264–265
special bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
writeback . . . . . . 87, 89–90, 103, 106, 125, 150, 158, 162,
. . . . . . . . . . . . . . . . 164, 166, 168, 172, 196, 252, 266, 269
units. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Execution Unit
D
D/C# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
D[63:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Data
3DNow! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7, 17–18
branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7, 15, 20
floating-point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7, 15, 223
load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7, 15
multimedia . . . . . . . . . . . . . . . . . . . . . . . . .7, 15, 17–18, 225
register X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7, 15, 17–18
register Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7, 15, 17–18
store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7, 15
Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–8, 16
External
address strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
write buffer empty. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
EXTEST Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
bus 90, 93, 96, 100–101, 116, 119, 142–144, 160, 166, 170
cache, MESI states in the . . . . . . . . . . . . . . . . . . . . . . . . . 193
parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Data Types
3DNow!. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
floating-point register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
MMX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Data/Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Debug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34, 257
DR3–DR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
306
Index
Preliminary Information
®
23446B/0—June 2000
Mobile AMD-K6 -2+ Processor Data Sheet
IEEE 854 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
F
IGNNE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108, 224–225
Ignore Numeric Exception . . . . . . . . . . . . . . . . . . . . . . . . . 108
INIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
-initiated transition from protected mode to real mode 182
state of processor after . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
power-on configuration and . . . . . . . . . . . . . . . . . . . . . . 185
Input
setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Input Setup and Hold Timings for
100-MHz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Inquire. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157, 159, 161
and bus arbitration cycles. . . . . . . . . . . . . . . . . . . . . . . . 154
cycle hit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
cycle hit to modified line . . . . . . . . . . . . . . . . . . . . . . . . 106
FERR# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104, 224–225
Fetch, Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Float Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124, 127
Float Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Floated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Floating-Point
and MMX/3DNow! instruction compatibility . . . . . . . . . 225
and multimedia execution units . . . . . . . . . . . . . . . . . . . 223
error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
handling exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
register data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
FLUSH# . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105, 185, 210, 240
Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268, 280, 287
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Multiplier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
cycles . . . . . 87–92, 102, 106–107, 120, 125, 150, 154, 156,
. . . . . . . . 158, 160, 162–164, 166, 168, 172, 209, 214, 251
miss, AHOLD-initiated . . . . . . . . . . . . . . . . . . . . . . . . . . 160
operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94, 98, 185
Functional Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
multimedia . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Inquire Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263–266
Instruction
decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3DNow! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83–84, 225
EMMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
FEMMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
INVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
G
Gate Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51, 54
General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Global EWBE Disable (GEWBED) . . . . . . . . . . . . . . . . . . . 217
Grounding, Power and . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
MMX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79, 225
H
PREFETCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10, 206
TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
WBINVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Integer Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Internal
architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–20
snooping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Interrupt . . . . . . 110, 119, 174, 178–179, 182, 189, 223–225,
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237, 261, 266–267
acknowledge . . . . . . . . . 88, 96, 99, 110, 112, 116, 170, 174
acknowledge cycles . . . . . . . . . . . . 88, 91, 93, 99, 114, 125
descriptor table register . . . . . . . . . . . . . . . . . . . . . . . . . . 46
flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110, 119
flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
redirection bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
service routine . . . . . . . . . . . . . . . . . . . . . 110, 114, 224, 227
system management . . . . . . . . . . . . . . . . . . . . . . . . 227, 230
type of . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Interrupts
01h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
03h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
exceptions and . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
INTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
IRQ13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
INTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
INV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Invalidation Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
INVD Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Halt
restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
Handling Floating-Point Exceptions . . . . . . . . . . . . . . . . . . 223
Heat Dissipation Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
HIGHZ Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
History Table, Branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Hit to
modified line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
modified line, AHOLD-initiated inquire . . . . . . . . . . . . 164
modified line, HOLD-initiated inquire . . . . . . . . . . . . . . 158
shared or exclusive line, AHOLD-initiated inquire . . . . 162
shared or exclusive line, HOLD-initiated inquire . . . . . 156
HIT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
HITM# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
HLDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
HOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
-initiated inquire hit to modified line . . . . . . . . . . . . . . . 158
-initiated inquire hit to shared or exclusive line . . . . . . 156
Hold
acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . .107, 154–156
and hold acknowledge cycle . . . . . . . . . . . . . . . . . . . . . . 154
timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279, 289
I
I/O
misaligned read and write . . . . . . . . . . . . . . . . . . . . . . . . 153
read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
trap dword . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
trap restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
IDCODE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
IEEE 1149.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
IEEE 754 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25, 223
Index
307
Preliminary Information
®
Mobile AMD-K6 -2+ Processor Data Sheet
23446B/0—June 2000
Negated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Next Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
K
KEN# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
No-Connect Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118, 273
Non-Maskable Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Non-Pipelined . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
L
L1 Cache . . . . . . . . . 9–10, 38, 150, 154, 160, 164, 176, 191,
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200–201, 204, 209, 214
L2 Cache . . . . . . . 1–2, 9–10, 39, 42–43, 105–106, 125, 128,
. . . . . . . . . . . . . .150, 154, 160, 164, 176, 191–195, 197–201,
. . . . . . . . . . . . . . 204, 206–207, 209–214, 239, 251, 253–256
L2AAR . . . . . . . . . . . . . . . . . . . . 37, 42–43, 198, 239, 253–255
O
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Operation, Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
OPN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Ordering Part Number (OPN). . . . . . . . . . . . . . . . . . . . . . . 303
L3 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251–252
Limit, Write Allocate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Organization, Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . 191, 217
Output
valid delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Line Fills, Cache-. . . . . . . . . . . . . . . . . . . . . . . . . .198–199, 253
LOCK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Locked
cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
operation with BOFF# intervention . . . . . . . . . . . . . . . . 172
operation, basic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Logic
P
Page
cache disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
branch-prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–19
external support of floating-point exceptions . . . . . . . . 223
directory entry (PDE) . . . . . . . . . . . . . . . . . . . . . 49–50, 195
table entry (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . 49, 51, 195
writethrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Parity. . . . . . . . . . . . . . . . . . . . . . . . . 86, 91, 93, 101, 116, 144
bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91, 101, 116
check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91–92, 101, 116
error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92, 116, 160, 242
flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Part Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
PCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115, 195, 204
PCHK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
PFIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41–42, 188
Pin
connection requirements . . . . . . . . . . . . . . . . . . . . . . . . 273
designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19, 142–143, 148
control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
register X and Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
M
M/IO# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Machine Check Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Maskable Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
MCAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37, 188
MCTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37–38, 188
Memory
or I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
read and write, misaligned single-transfer . . . . . . . . . . 146
read and write, single-transfer . . . . . . . . . . . . . . . . . . . . 144
reads and writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
type range register (MTRR) . . . . . . . . . . . . . . . . . . . 41, 219
MESI. . . . . . . . . . . . . . . . . . . . . . . . . . 1, 10, 154, 158, 193, 214
bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11, 193, 195
states in the data cache . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
enhanced RISC86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Misaligned
I/O read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
single-transfer memory read and write . . . . . . . . . . . . . 146
MMX Technology . . . . . 13–14, 16–18, 21, 55, 118, 185, 189
exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
instruction compatibility, floating-point and . . . . . . . . . 225
instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79, 226
register operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Mode, Tri-State Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
Model-Specific Registers (MSR) . . . . . . . . . . . . . . . . . . . . . . 37
MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
six-stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6, 8
Pipelined . . . . . . . . . .9, 17, 114, 143, 148–149, 166, 191, 206
burst reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10, 89, 100
design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Pointer, Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Power
and grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
PowerNow! Technology . . . . . . . 1–3, 131, 134–135, 137, 263
Power-on Configuration and Initialization . . . . . . . . . . . . 185
Predecode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–10, 194
Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10, 206
PSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41, 188
PWT Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
MTRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41, 219
Multimedia
execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . .17–18, 225
functional unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
R
Read and Write
basic I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
misaligned I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Reads, Burst Reads and Pipelined Burst . . . . . . . . . . . . . . 148
N
NA#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
308
Index
Preliminary Information
®
23446B/0—June 2000
Mobile AMD-K6 -2+ Processor Data Sheet
Register
Shift-DR state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Shift-IR state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Shutdown Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Signal
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Signals
boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
bypass (BR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
data Types, floating-point . . . . . . . . . . . . . . . . . . . . . . . . . 28
debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34, 257
floating-point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
general-purpose. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Register X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Register X and Y
A[31:3]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
A20M# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87, 228
ADS# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
ADSC#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
pipelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Register Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8, 21, 186, 225
AHOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90, 264
AP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
APCHK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
BE[7:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
3DNow!. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21, 29
descriptors and gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
BF[2:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94, 268
BOFF# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95, 168, 264
device identification (DIR) . . . . . . . . . . . . . . . . . . . 245–246
DR3–DR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
DR5–DR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
DR6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
DR7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
EFER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
EFLAGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
EPMR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
L2AAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
MCAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
MCTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
MMX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21, 29
PFIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
PSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
STAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
TR12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
TSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
UWCCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
WHCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
BRDY#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96, 235, 264–265
BRDYC# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
BREQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
CACHE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98, 196
CLK . . . . . . . . . . . . . . . . . . . . . . . . . . 98, 263, 265, 268, 279
D/C#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
D[63:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
DP[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
EADS#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102, 266
EWBE# . . . . . . . . . . . . . . . . . . . . . . . . . . . 103, 217, 264–265
FERR#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104, 225
FLUSH# . . . . . . . . . . . . . 105, 185, 210, 237, 240, 264–267
HIT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106, 266
HITM# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106, 266
HLDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
HOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107, 264
IGNNE#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108, 225
INIT . . . . . . . . . . . . . . . . . . . . . . . . . .109, 228, 264–265, 267
INTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110, 264–265, 267
INV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
KEN# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
LOCK#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
M/IO#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
NA# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
X and Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15–17
Replacement, Cache-Line . . . . . . . . . . . . . . . . . . . . . . 200, 211
Requirements, Pin Connection . . . . . . . . . . . . . . . . . . . . . . 273
Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118, 186
signals sampled during. . . . . . . . . . . . . . . . . . . . . . . . . . . 185
state of processor after . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Reset and Configuration Timing . . . . . . . . . . . . . . . . . . . . . 290
Return Address Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
RISC86 Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
NMI . . . . . . . . . . . . . . . . . . . . . 114, 228, 237, 264–265, 267
output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
PCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
PCHK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
PWT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
RESET. . . . . . . . . . . . . . . . . . . 118, 264–265, 267–268, 279
RSVD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
sampled during RESET. . . . . . . . . . . . . . . . . . . . . . . . . . 185
SCYC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
RSM Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233, 236
RSVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
SMI# . . . . . . . . . . . . . . . . . . . . 119, 227, 235, 264–265, 267
SMIACT#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120, 227
STPCLK# . . . . . . . . . . . . . . . . . . . . . . . . . 121, 263, 265–266
TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
S
SAMPLE/PRELOAD Instruction . . . . . . . . . . . . . . . . . . . . . 248
Sampled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Scheduler
TCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122, 279
TDI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
TDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
TMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
TRST# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
centralized . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
instruction control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SCYC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Sector, Write to a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202, 206
Segment
VCC2DET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123–124
VCC2H/L#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
VID[4:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
W/R# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
descriptor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24, 51–53
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
task state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Index
309
Preliminary Information
®
Mobile AMD-K6 -2+ Processor Data Sheet
23446B/0—June 2000
WB/WT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
SIMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Single Instruction Multiple Data (SIMD) . . . . . . . . . . . . . . . . 9
Single-Transfer Memory Read and Write . . . . . . . . . . . . . . 144
SMI# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
SMIACT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
SMM
base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
default register values . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
initial state of registers . . . . . . . . . . . . . . . . . . . . . . . . . . 229
memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
revision identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
state-save area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Snoop . . . . . . . . . . . . . . . . . . . . . . . . . . 120, 125, 150, 210, 213
Snooping
internal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Software Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Special
bus cycle . . . . . . . . . . . . . . . . . . . . . . . . . . 96, 121, 176–179
cycle . . . . . . . . 103, 105, 121, 128, 150, 176, 178–179, 198
Special Bus Cycle . . . . . . . . . . . . . . . . . . . . . . . . .234, 264–265
Speculative EWBE Disable (SEWBED) . . . . . . . . . . . . . . . 218
Split Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Stack, Return Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
State Machine Diagram, Bus . . . . . . . . . . . . . . . . . . . . . . . . 141
State of Processor
TAP Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Target Cache, Branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Task State Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
TCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
TCK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287, 291
TDI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
TDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293–294
Terminology, Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Test
access port, boundary-scan . . . . . . . . . . . . . . . . . . . . . . . 241
and debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
-logic-reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
mode select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
mode, tri-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
register 12 (TR12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Test Signal
timing at 25 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Thermal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Time Stamp Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
after INIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
after RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
States, Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Stop
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 139, 145–183
TLB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
TMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
TR12 . . . . . . . . . . . . . . . . . . . . . . . . 37–38, 188, 196, 204, 251
Transition from Protected Mode to Real Mode,
clock state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179, 268
grant inquire state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
INIT-Initiated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Translation Lookaside Buffer (TLB) . . . . . . . . . . . . . . . . . 191
TriLevel Cache Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Tri-State Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287, 291
TRST# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
TSC . . . . . . . . . . . . . . . . . . . . . . . . . 37–38, 188, 264–265, 267
grant state . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179, 265–266
STPCLK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Switching Characteristics
input setup and hold timings for 100-MHz bus . . . . . . . 284
SYSCALL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
SYSCALL/SYSRET Target Address Register
(STAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37, 40, 188
SYSRET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
System
TSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47, 53–54, 260
management interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
management interrupt active . . . . . . . . . . . . . . . . . . . . . 120
U
UC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Uncacheable Memory . . . . . . . . . . . . . . . . . . . . . . 41, 218–219
UWCCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41, 186, 188, 219
T
Table, Branch History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
TAP Controller States
V
capture-DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
capture-IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
shift-DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
shift-IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
test-logic-reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
update-DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
update-IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
TAP Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
BYPASS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
EXTEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
HIGHZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
IDCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
SAMPLE/PRELOAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
TAP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
instruction register (IR) . . . . . . . . . . . . . . . . . . . . . . . . . . 242
VCC2DET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123–124
VCC2H/L# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
VID[4:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124, 137
Voltage . . . . . . . . . . . . . . . . . . . . 123–124, 140, 271, 275–276
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
W
W/R# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
WB/WT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
WBINVD Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
WC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
WHCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37, 40, 188, 205
Write
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Mobile AMD-K6 -2+ Processor Data Sheet
to a cacheable page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
to a sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202, 206
Write Allocate . . . . . . . . . . . . . . . . . . . 194, 201, 204–205, 207
limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
logic mechanisms and conditions . . . . . . . . . . . . . . . . . . 204
Write Merge Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Write/Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Writeback . . . . . . . . . . 98, 100–101, 111, 117, 120, 125, 128,
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150–151, 176, 191, 214
burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6, 9
cycles . . . . . . . . . 87, 89–90, 103, 106, 125, 150, 158, 162,
. . . . . . . . . . . . . . . . 164, 166, 168, 172, 196, 252, 266, 269
or writethrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Write-combining Memory . . . . . . . . . . . . . . . . . . .41, 218–219
Writethrough vs. Writeback Coherency States . . . . . . . . . 214
Index
311
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23446B/0—June 2000
312
Index
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