AMD-K6-2E/233AFZ [AMD]
AMD-K6⑩-2E Embedded Processor; AMD- K6 ™ -2E嵌入式处理器
| 型号： | AMD-K6-2E/233AFZ |
| 厂家： | 
AMD |
| 描述： | AMD-K6⑩-2E Embedded Processor |
| 文件： | 总332页 (文件大小：5615K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Information
TM
AMD-K6 -2E
Embedded Processor
Data Sheet
Publication # 22529
Issue Date: Jan 2000
Rev: B
Amendment/0
© 2000 Advanced Micro Devices, Inc. All rights reserved.
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Preliminary Information
22529B/0—January 2000
AMD-K6™-2E Processor Data Sheet
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Preliminary Information
AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
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iv
Preliminary Information
22529B/0—January 2000
AMD-K6™-2E Processor Data Sheet
Contents
Revision History.......................................................................... xv
About this Data Sheet...............................................................xvii
Overview................................................................................. xvii
AMD-K6™-2E Processor .............................................................. 1
1
2
1.1
1.2
1.3
AMD-K6™-2E Embedded Processor Features......................... 2
Process Technology..................................................................... 4
Super7™ Platform Initiative ..................................................... 4
Internal Architecture .................................................................. 7
2.1
2.2
2.3
2.4
2.5
2.6
AMD-K6™-2E Processor Microarchitecture Overview ........... 7
Cache, Instruction Prefetch, and Predecode Bits.................. 12
Instruction Fetch and Decode ................................................. 13
Centralized Scheduler.............................................................. 17
Execution Units......................................................................... 18
Branch-Prediction Logic........................................................... 20
3
Software Environment ............................................................... 23
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Registers .................................................................................... 23
Model-Specific Registers (MSR) ............................................. 40
Memory Management Registers.............................................. 47
Paging......................................................................................... 49
Descriptors and Gates .............................................................. 52
Exceptions and Interrupts ....................................................... 55
Instructions Supported by the AMD-K6™-2E Processor ...... 56
4
5
Logic Symbol Diagram ............................................................... 83
Signal Descriptions .................................................................... 85
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Signal Terminology................................................................... 85
A20M# (Address Bit 20 Mask) ................................................. 86
A[31:3] (Address Bus)............................................................... 87
ADS# (Address Strobe) ............................................................ 88
ADSC# (Address Strobe Copy)................................................ 88
AHOLD (Address Hold) ........................................................... 89
AP (Address Parity).................................................................. 90
APCHK# (Address Parity Check)............................................ 91
BE[7:0]# (Byte Enables) ........................................................... 92
5.10 BF[2:0] (Bus Frequency) .......................................................... 93
5.11 BOFF# (Backoff) ....................................................................... 94
5.12 BRDY# (Burst Ready)............................................................... 95
5.13 BRDYC# (Burst Ready Copy) .................................................. 96
5.14 BREQ (Bus Request)................................................................. 96
5.15 CACHE# (Cacheable Access) .................................................. 97
5.16 CLK (Clock)............................................................................... 97
5.17 D/C# (Data/Code) ...................................................................... 98
5.18 D[63:0] (Data Bus)..................................................................... 99
5.19 DP[7:0] (Data Parity).............................................................. 100
5.20 EADS# (External Address Strobe)........................................ 101
Contents
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5.21 EWBE# (External Write Buffer Empty) ............................... 102
5.22 FERR# (Floating-Point Error)............................................... 103
5.23 FLUSH# (Cache Flush) .......................................................... 104
5.24 HIT# (Inquire Cycle Hit)........................................................ 105
5.25 HITM# (Inquire Cycle Hit To Modified Line)...................... 105
5.26 HLDA (Hold Acknowledge)................................................... 106
5.27 HOLD (Bus Hold Request)..................................................... 107
5.28 IGNNE# (Ignore Numeric Exception)................................... 108
5.29 INIT (Initialization) ................................................................ 109
5.30 INTR (Maskable Interrupt).................................................... 110
5.31 INV (Invalidation Request) ................................................... 110
5.32 KEN# (Cache Enable)............................................................. 111
5.33 LOCK# (Bus Lock) .................................................................. 112
5.34 M/IO# (Memory or I/O)........................................................... 113
5.35 NA# (Next Address)................................................................ 114
5.36 NMI (Non-Maskable Interrupt) ............................................. 114
5.37 PCD (Page Cache Disable)..................................................... 115
5.38 PCHK# (Parity Check) ........................................................... 116
5.39 PWT (Page Writethrough) ..................................................... 117
5.40 RESET (Reset) ........................................................................ 118
5.41 RSVD (Reserved).................................................................... 119
5.42 SCYC (Split Cycle).................................................................. 120
5.43 SMI# (System Management Interrupt)................................. 121
5.44 SMIACT# (System Management Interrupt Active)............. 122
5.45 STPCLK# (Stop Clock) ........................................................... 123
5.46 TCK (Test Clock)..................................................................... 124
5.47 TDI (Test Data Input)............................................................. 124
5.48 TDO (Test Data Output)......................................................... 124
5.49 TMS (Test Mode Select)......................................................... 125
5.50 TRST# (Test Reset)................................................................. 125
5.51 VCC2DET (VCC2 Detect) ...................................................... 126
5.52 VCC2H/L# (VCC2 High/Low)................................................. 127
5.53 W/R# (Write/Read) ................................................................. 128
5.54 WB/WT# (Writeback or Writethrough)................................. 129
5.55 Pin Tables by Type ................................................................. 130
5.56 Bus Cycle Definitions ............................................................. 132
Bus Cycles ................................................................................. 133
6
6.1
6.2
6.3
6.4
6.5
6.6
Timing Diagrams..................................................................... 133
Bus States................................................................................. 135
Memory Reads and Writes..................................................... 138
I/O Read and Write................................................................. 146
Inquire and Bus Arbitration Cycles ...................................... 148
Special Bus Cycles .................................................................. 170
7
Power-On Configuration and Initialization ........................... 179
7.1
7.2
7.3
Signals Sampled During the Falling Transition of RESET.. 179
RESET Requirements ............................................................ 180
State of Processor After RESET............................................ 180
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Contents
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AMD-K6™-2E Processor Data Sheet
7.4
State of Processor After INIT ................................................ 183
8
Cache Organization .................................................................. 185
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
MESI States in the Data Cache ............................................. 186
Predecode Bits......................................................................... 187
Cache Operation ..................................................................... 187
Cache Disabling and Flushing............................................... 190
Cache-Line Fills ...................................................................... 191
Cache-Line Replacements...................................................... 192
Write Allocate ......................................................................... 192
Prefetching .............................................................................. 197
Cache States ............................................................................ 198
8.10 Cache Coherency .................................................................... 199
8.11 Writethrough and Writeback Coherency States.................. 204
8.12 A20M# Masking of Cache Accesses ...................................... 204
Write Merge Buffer ................................................................. 205
9
9.1
9.2
9.3
9.4
EWBE# Control ....................................................................... 205
Memory Type Range Registers ............................................. 207
Memory-Range Restrictions .................................................. 209
Examples.................................................................................. 211
10
11
Floating-Point and Multimedia Execution Units .................. 213
10.1 Floating-Point Execution Unit............................................... 213
10.2 Multimedia and 3DNow!™ Execution Units........................ 215
10.3 Floating-Point and MMX™/3DNow!™
Instruction Compatibility....................................................... 216
System Management Mode (SMM) ........................................ 217
11.1 SMM Operating Mode and Default Register Values........... 217
11.2 SMM State-Save Area............................................................. 219
11.3 SMM Revision Identifier........................................................ 221
11.4 SMM Base Address ................................................................. 222
11.5 Halt Restart Slot ..................................................................... 222
11.6 I/O Trap Doubleword.............................................................. 223
11.7 I/O Trap Restart Slot .............................................................. 224
11.8 Exceptions, Interrupts, and Debug in SMM......................... 226
Test and Debug ......................................................................... 227
12.1 Built-In Self-Test (BIST)......................................................... 227
12.2 Three-State Test Mode ........................................................... 228
12.3 Boundary-Scan Test Access Port (TAP)................................ 229
12.4 L1 Cache Inhibit...................................................................... 239
12.5 Debug ....................................................................................... 240
Clock Control ............................................................................ 247
13.1 Clock Control States............................................................... 247
13.2 Halt State................................................................................. 249
13.3 Stop Grant State...................................................................... 250
13.4 Stop Grant Inquire State........................................................ 251
13.5 Stop Clock State...................................................................... 252
Electrical Data .......................................................................... 253
14.1 Operating Ranges ................................................................... 254
12
13
14
Contents
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Preliminary Information
AMD-K6™-2E Processor Data Sheet
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14.2 Absolute Ratings..................................................................... 255
14.3 DC Characteristics.................................................................. 256
14.4 Power Dissipation ................................................................... 258
14.5 Power Derating Based on Lower CPU Frequencies............ 260
14.6 Power and Grounding............................................................. 262
14.7 I/O Buffer Characteristics ...................................................... 264
Signal Switching Characteristics ............................................ 267
15.1 CLK Switching Characteristics.............................................. 267
15.2 Clock Switching Characteristics
15
for 100-MHz Bus Operation.................................................... 268
15.3 Clock Switching Characteristics
for 66-MHz Bus Operation...................................................... 268
15.4 Valid Delay, Float, Setup, and Hold Timings ...................... 269
15.5 Output Delay Timings for 100-MHz Bus Operation............. 270
15.6 Input Setup and Hold Timings
for 100-MHz Bus Operation.................................................... 272
15.7 Output Delay Timings for 66-MHz Bus Operation............... 274
15.8 Input Setup and Hold Timings
for 66-MHz Bus Operation...................................................... 276
15.9 RESET and Test Signal Timing............................................. 278
15.10 Timing Diagrams..................................................................... 281
Thermal Design ........................................................................ 285
16.1 Package Thermal Specifications ........................................... 285
16.2 Measuring Case Temperature ............................................... 288
16.3 Sample Heatsink Measured Data.......................................... 289
16.4 Layout and Airflow Considerations ...................................... 295
Pin Designation Diagrams ....................................................... 299
17.1 Pin Designations by Functional Grouping ........................... 301
Package Specifications ............................................................ 303
18.1 321-Pin Staggered CPGA Package Specification................. 303
Ordering Information .............................................................. 305
Index........................................................................................... 307
16
17
18
19
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AMD-K6™-2E Processor Data Sheet
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
AMD-K6™-2E Processor Block Diagram.........................9
Cache Sector Organization.............................................12
The Instruction Buffer ....................................................14
AMD-K6™-2E Processor Decode Logic.........................15
AMD-K6™-2E Processor Scheduler...............................18
Register X and Y Functional Units ...............................20
EAX Register with 16-Bit and 8-Bit
Name Components ..........................................................24
Integer Data Registers....................................................25
Segment Register ............................................................26
Figure 8.
Figure 9.
Figure 10. Segment Usage ................................................................27
Figure 11. Floating-Point Register...................................................28
Figure 12. FPU Status Word Register .............................................28
Figure 13. FPU Control Word Register...........................................29
Figure 14. FPU Tag Word Register..................................................29
Figure 15. Packed Decimal Data Register ......................................30
Figure 16. Precision Real Data Registers .......................................30
Figure 17. MMX™/3DNow!™ Registers ..........................................31
Figure 18. MMX™ Data Types .........................................................32
Figure 19. 3DNow!™ Data Types .....................................................33
Figure 20. EFLAGS Register............................................................34
Figure 21. Control Register 4 (CR4)................................................35
Figure 22. Control Register 3 (CR3)................................................35
Figure 23. Control Register 2 (CR2)................................................35
Figure 24. Control Register 1 (CR1)................................................36
Figure 25. Control Register 0 (CR0)................................................36
Figure 26. Debug Register DR7 .......................................................37
Figure 27. Debug Register DR6 .......................................................38
Figure 28. Debug Registers DR5 and DR4......................................38
Figure 29. Debug Registers DR3, DR2, DR1, and DR0..................39
Figure 30. Machine-Check Address Register (MCAR) ..................41
Figure 31. Machine-Check Type Register (MCTR)........................41
Figure 32. Test Register 12 (TR12)..................................................42
Figure 33. Time Stamp Counter (TSC)............................................42
Figure 34. Extended Feature Enable Register (EFER).................43
Figure 35. SYSCALL/SYSRET Target Address
Register (STAR) ..............................................................44
Figure 36. Write Handling Control Register (WHCR)...................44
Figure 37. UC/WC Cacheability Control Register (UWCCR) .......45
Figure 38. Processor State Observability Register (PSOR) ..........45
Figure 39. Page Flush/Invalidate Register (PFIR).........................46
Figure 40. Memory Management Registers....................................47
Figure 41. Task State Segment (TSS)..............................................48
Figure 42. 4-Kbyte Paging Mechanism............................................49
Figure 43. 4-Mbyte Paging Mechanism ...........................................50
List of Figures
ix
Preliminary Information
AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
Figure 44. Page Directory Entry 4-Kbyte Page Table (PDE)........51
Figure 45. Page Directory Entry 4-Mbyte Page Table (PDE) .......51
Figure 46. Page Table Entry (PTE)..................................................52
Figure 47. Application Segment Descriptor ...................................53
Figure 48. System Segment Descriptor ...........................................54
Figure 49. Gate Descriptor ...............................................................55
Figure 50. Waveform Definitions...................................................134
Figure 51. Bus State Machine Diagram.........................................135
Figure 52. Non-Pipelined Single-Transfer Memory
Read/Write and Write Delayed by EWBE# ................139
Figure 53. Misaligned Single-Transfer Memory
Read and Write..............................................................141
Figure 54. Burst Reads and Pipelined Burst Reads .....................143
Figure 55. Burst Writeback due to Cache-Line Replacement.....145
Figure 56. Basic I/O Read and Write .............................................146
Figure 57. Misaligned I/O Transfer................................................147
Figure 58. Basic HOLD/HLDA Operation .....................................149
Figure 59. HOLD-Initiated Inquire Hit to Shared
or Exclusive Line...........................................................151
Figure 60. HOLD-Initiated Inquire Hit to Modified Line............153
Figure 61. AHOLD-Initiated Inquire Miss ....................................155
Figure 62. AHOLD-Initiated Inquire Hit to Shared
or Exclusive Line...........................................................157
Figure 63. AHOLD-Initiated Inquire Hit to Modified Line.........159
Figure 64. AHOLD Restriction.......................................................161
Figure 65. BOFF# Timing................................................................163
Figure 66. Basic Locked Operation................................................165
Figure 67. Locked Operation with BOFF# Intervention..............167
Figure 68. Interrupt Acknowledge Operation ..............................169
Figure 69. Basic Special Bus Cycle (Halt Cycle) ..........................171
Figure 70. Shutdown Cycle.............................................................172
Figure 71. Stop Grant and Stop Clock Modes, Part 1 ..................174
Figure 72. Stop Grant and Stop Clock Modes, Part 2 ..................175
Figure 73. INIT-Initiated Transition from Protected Mode
to Real Mode..................................................................177
Figure 74. Cache Organization.......................................................185
Figure 75. Cache Sector Organization...........................................186
Figure 76. Write Handling Control Register (WHCR).................194
Figure 77. Write Allocate Logic Mechanisms and Conditions....195
Figure 78. Page Flush/Invalidate Register (PFIR).......................200
Figure 79. UC/WC Cacheability Control Register (UWCCR) .....208
Figure 80. External Logic for Supporting Floating-Point
Exceptions......................................................................215
Figure 81. SMM Memory.................................................................218
Figure 82. TAP State Diagram .......................................................237
Figure 83. Debug Register DR7 .....................................................241
Figure 84. Debug Register DR6 .....................................................242
x
List of Figures
Preliminary Information
22529B/0—January 2000
AMD-K6™-2E Processor Data Sheet
Figure 85. Debug Registers DR5 and DR4....................................242
Figure 86. Debug Registers DR3, DR2, DR1, and DR0................243
Figure 87. Clock Control State Transitions...................................248
Figure 88. Suggested Component Placement ...............................263
Figure 89. CLK Waveform ..............................................................269
Figure 90. Key to Timing Diagrams...............................................281
Figure 91. Output Valid Delay Timing..........................................281
Figure 92. Maximum Float Delay Timing .....................................282
Figure 93. Input Setup and Hold Timing ......................................282
Figure 94. Reset and Configuration Timing .................................283
Figure 95. TCK Timing....................................................................284
Figure 96. TRST# Timing................................................................284
Figure 97. Test Signal Timing ........................................................284
Figure 98. Thermal Model ..............................................................286
Figure 99. Power Consumption v. Thermal Resistance...............287
Figure 100. Processor Heat Dissipation Path .................................288
Figure 101. Measuring Case Temperature......................................289
Figure 102. Heatsink A (15 mm height) ..........................................290
Figure 103. Heatsink B (20 mm height)...........................................290
Figure 104. Heatsink C (30 mm height) ..........................................290
Figure 105. Measured Thermal Resistance v. Airflow
(Socketed 321-Pin CPGA Package) .............................291
Figure 106. Measured Maximum Ambient Temperature
(Socketed 321-Pin CPGA Package) .............................292
Figure 107. Measured Thermal Resistance v. Airflow
(Soldered 321-Pin CPGA Package)..............................293
Figure 108. Measured Maximum Ambient Temperature
(Soldered, 321-Pin CPGA Package).............................294
Figure 109. Voltage Regulator Placement......................................295
Figure 110. Airflow for a Heatsink with Fan..................................296
Figure 111. Airflow Path in a Dual-Fan System .............................296
Figure 112. Airflow Path in an ATX Form-Factor System ............297
Figure 113. AMD-K6™-2E Processor Connection Diagram
(Top-Side View CPGA) .................................................299
Figure 114. AMD-K6™-2E Processor Connection Diagram
(Bottom-Side View CPGA)............................................300
Figure 115. 321-Pin Staggered CPGA Package Specification.......303
List of Figures
xi
Preliminary Information
AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
xii
List of Figures
Preliminary Information
22529B/0—January 2000
AMD-K6™-2E Processor Data Sheet
List of Tables
Table 1. Execution Latency and Throughput of Execution Units .19
Table 2. General-Purpose Registers .................................................24
Table 3. General-Purpose Register Doubleword, Word,
and Byte Names....................................................................25
Table 4. Segment Registers ...............................................................26
Table 5. AMD-K6™-2E Processor Model 8/[F:8]
Model-Specific Registers.....................................................40
Table 6. Extended Feature Enable Register (EFER)Definition ...43
Table 7. SYSCALL/SYSRET Target Address Register
(STAR) Definition................................................................44
Table 8. Memory Management Registers.........................................47
Table 9. Application Segment Types................................................53
Table 10. System Segment and Gate Types .......................................54
Table 11. Summary of Exceptions and Interrupts.............................55
Table 12. Integer Instructions .............................................................57
Table 13. Floating-Point Instructions .................................................74
Table 14. MMX™ Instructions.............................................................78
Table 15. 3DNow!™ Instructions.........................................................81
Table 16. Processor-to-Bus Clock Ratios ............................................93
Table 17. Output Pin Float Conditions.............................................127
Table 18. Input Pin Types..................................................................130
Table 19. Output Pin Float Conditions.............................................131
Table 20. Input/Output Pin Float Conditions ..................................131
Table 21. Test Pins..............................................................................131
Table 22. Bus Cycle Definition..........................................................132
Table 23. Special Cycles.....................................................................132
Table 24. Bus-Cycle Order During Misaligned Memory Transfers . 140
Table 25. A[4:3] Address-Generation Sequence During Bursts .....142
Table 26. Bus-Cycle Order During Misaligned I/O Transfers.........147
Table 27. Interrupt Acknowledge Operation Definition ................168
Table 28. Encodings for Special Bus Cycles.....................................170
Table 29. Output Signal State After RESET....................................180
Table 30. Register State After RESET.............................................181
Table 31. PWT Signal Generation.....................................................188
Table 32. PCD Signal Generation .....................................................189
Table 33. CACHE# Signal Generation..............................................189
Table 34. Data Cache States for Read and Write Accesses............198
Table 35. Cache States for Inquire Cycles, Snoops, Flushes,
and Invalidation.................................................................202
Table 36. Snoop Action ......................................................................203
Table 37. EWBEC Settings.................................................................207
Table 38. WC/UC Memory Type........................................................209
Table 39. Valid Masks and Range Sizes ...........................................210
Table 40. Initial State of Registers in System Management Mode. 219
Table 41. SMM State-Save Area Map ...............................................219
List of Tables
xiii
Preliminary Information
AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
Table 42. SMM Revision Identifier...................................................222
Table 43. I/O Trap Doubleword Configuration ................................224
Table 44. I/O Trap Restart Slot .........................................................225
Table 45. Boundary Scan Bit Definitions .........................................233
Table 46. Device Identification Register .........................................234
Table 47. Supported Test Access Port (TAP) Instructions.............235
Table 48. DR7 LEN and RW Definitions..........................................245
Table 49. Operating Ranges ..............................................................254
Table 50. Absolute Ratings................................................................255
Table 51. DC Characteristics.............................................................256
Table 52. Typical and Maximum Power Dissipation
for OPN Suffix AMZ (Low-Power Devices) .....................258
Table 53. Typical and Maximum Power Dissipation
for OPN Suffix AFR (Standard-Power Devices) .............259
Table 54. Power Derating Specification for Standard-Power
Devices (AMD-K6-2E/233AFR and 266AFR) ..................260
Table 55. Power Derating Specification for Low-Power
Devices (AMD-K6-2E/233AMZ and 266AMZ) .................261
Table 56. CLK Switching Characteristics
for 100-MHz Bus Operation...............................................268
Table 57. CLK Switching Characteristics
for 66-MHz Bus Operation.................................................268
Table 58. Output Delay Timings for 100-MHz Bus Operation........270
Table 59. Input Setup and Hold Timings
for 100-MHz Bus Operation...............................................272
Table 60. Output Delay Timings for 66-MHz Bus Operation..........274
Table 61. Input Setup and Hold Timings for 66-MHz Bus Operation 276
Table 62. RESET and Configuration Signals
for 100-MHz Bus Operation..............................................278
Table 63. RESET and Configuration Signals
for 66-MHz Bus Operation.................................................279
Table 64. TCK Waveform and TRST# Timing at 25 MHz...............280
Table 65. Test Signal Timing at 25 MHz...........................................280
Table 66. Package Thermal Specification
for OPN Suffix AMZ (Low-Power Devices) .....................285
Table 67. Package Thermal Specification
for OPN Suffix AFR (Standard-Power Devices) .............285
Table 68. Passive Heatsink Samples.................................................289
Table 69. Socketed CPGA Package: Measured Thermal
Resistance (°C/W) q and q .........................................291
JC
CA
Table 70. Socketed CPGA Package: Measured Maximum
Ambient Temperature (°C)...............................................292
Table 71. Soldered CPGA Package: Measured Thermal
Resistance (°C/W) q and q .........................................293
JC
CA
Table 72. Soldered CPGA Package: Measured Maximum
Ambient Temperature (°C)...............................................294
Table 73. Valid Ordering Part Number Combinations ...................306
xiv
List of Tables
Preliminary Information
22529B/0—January 2000
AMD-K6™-2E Processor Data Sheet
Revision History
Date
Rev Description
June 1999
Jan 2000
Jan 2000
A
B
B
Initial published release.
Replaced Figure 4, “AMD-K6™-2E Processor Decode Logic,” on page 15 with updated figure.
Replaced Table 45 on page 233 with revised boundary scan bit definitions.
Changed the V maximum specification from 2.6 V to 2.4 V in Table 50, “Absolute Ratings,” on
page 255 for all OPNs with the exception of the 233AFR, 233AMZ, 266AFR, 266AMZ, and 300 AFR,
cc2
Jan 2000
B
provided that the processor is not marked with a “7” following the date code.
For the 300AMZ, 333AMZ, and 350AMZ ordering part numbers, added DC characteristics to
Table 51 on page 256, added power dissipation specifications to Table 52 on page 258, added
package thermal specifications to Table 66 on page 285, and added ordering information
beginning on page 305.
Jan 2000
B
For the 333AFR, 350AFR, and 400AFR ordering part numbers, added DC characteristics to Table 51
on page 256, added power dissipation specifications to Table 53 on page 259, added package
thermal specifications to Table 67 on page 285, and added ordering information beginning on
page 305.
Jan 2000
B
Jan 2000
Jan 2000
B
B
Added power derating specifications beginning on page 260.
Added sample measured heat sink data beginning on page 289.
Revision History
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AMD-K6™-2E Processor Data Sheet
About this Data Sheet
The AMD-K6™-2E Processor Data Sheet is the complete specification of the
AMD-K6-2E embedded processor.
Overview
This data sheet is organized into the following sections:
Chapter 1, “AMD-K6™-2E Processor” on page 1, provides a list of the AMD-K6-2E
processor’s distinguishing characteristics, a description of the key features, and a
discussion about the Super7™ platform initiative.
Chapter 2, “Internal Architecture” on page 7, describes the functional elements of the
®
advanced design techniques, known as the RISC86 microarchitecture, implemented
by the AMD-K6-2E processor.
Chapter 3, “Software Environment” on page 23, provides a general overview of the
AMD-K6-2E processor’s x86 software environment and briefly describes the data
types, registers, operating modes, interrupts, and instructions supported by the
AMD-K6-2E processor’s architecture and design implementation.
Chapter 4, “Logic Symbol Diagram” on page 83, contains the AMD-K6-2E processor
logic symbol diagram.
Chapter 5, “Signal Descriptions” on page 85, lists the signals and their descriptions
alphabetically and by function.
Chapter 6, “Bus Cycles” on page 133, describes and illustrates the timing and
relationship of bus signals during various types of bus cycles.
Chapter 7, “Power-On Configuration and Initialization” on page 179, describes how
the system logic resets the AMD-K6-2E processor using the RESET signal.
Chapter 8, “Cache Organization” on page 185, describes the basic architecture and
resources of the AMD-K6-2E processor’s internal caches.
Chapter 9, “Write Merge Buffer” on page 205, describes the 8-byte write merge buffer
and how merging multiple write cycles into a single write cycle ultimately increases
overall system performance.
Chapter 10, “Floating-Point and Multimedia Execution Units” on page 213, describes
the AMD-K6-2E processor’s IEEE 754-compatible and 854-compatible floating point
About this Data Sheet
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execution unit, the multimedia and 3DNow!™ technology execution units, and the
floating-point and MMX/3DNow! technology instruction compatibility.
Chapter 11, “System Management Mode (SMM)” on page 217, describes SMM, the
state-save area, entry into and exit from SMM, exceptions and interrupts in SMM,
memory allocation and addressing in SMM, and the SMI# and SMIACT# signals.
Chapter 12, “Test and Debug” on page 227, describes the various test and debug modes
that enable the functional and manufacturing testing of systems and boards that use
the AMD-K6-2E processor and that allow designers to debug the instruction execution
of software components.
Chapter 13, “Clock Control” on page 247, describes the five modes of clock control
supported by the AMD-K6-2E processor.
Chapter 14, “Electrical Data” on page 253, includes operating ranges, absolute
ratings, DC characteristics, power dissipation data, power and grounding information,
decoupling recommendations, and I/O buffer characteristics.
Chapter 15, “Signal Switching Characteristics” on page 267, provides tables listing
valid delay, float, setup, and hold timing specifications for the AMD-K6-2E processor
signals.
Chapter 16, “Thermal Design” on page 285, lists the package thermal specifications,
discusses how to measure case temperature, and provides sample heat sink
measurement data, along with layout and airflow considerations.
Chapter 17, “Pin Designation Diagrams” on page 299, lists the AMD-K6-2E processor’s
pin designations by functional grouping.
Chapter 18, “Package Specifications” on page 303, provides a table and diagram
containing the 321-pin CPGA package specifications.
Chapter 19, “Ordering Information” on page 305, provides the ordering part number
(OPN) and valid OPN combinations.
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1
AMD-K6™-2E Processor
The following are key features of the AMD-K6™-2E processor:
®
■ Advanced 6-Issue RISC86 Superscalar Microarchitecture
•
•
•
•
•
•
•
Ten parallel specialized execution units
Multiple sophisticated x86-to-RISC86 instruction decoders
Advanced two-level branch prediction
Speculative execution
Out-of-order execution
Register renaming and data forwarding
Up to six RISC86 instructions per clock
■ Large on-chip split 64-Kbyte level-one (L1) cache
•
•
•
•
32-Kbyte instruction cache with additional 20 Kbytes of predecode cache
32-Kbyte writeback dual-ported data cache
Two-way set associative
MESI protocol support
■ 3DNow!™ technology
•
•
Additional instructions to improve 3D graphics and multimedia performance
Separate multiplier and ALU for superscalar instruction execution
■ 321-pin ceramic pin grid array (CPGA) package
■ Socket 7 platform compatible, 66-MHz frontside bus
■ Super7™ platform compatible, 100-MHz frontside bus supported on the 300-MHz,
350-MHz, and 400-MHz versions of the AMD-K6-2E processor
■ High-performance industry-standard MMX™ instructions
•
Dual integer ALU for superscalar execution
■ High-performance IEEE 754-compatible and 854-compatible floating-point unit
■ Industry-standard system management mode (SMM)
■ IEEE 1149.1 boundary scan
■ x86 binary software compatibility
■ Low-power 0.25-micron process technology
•
•
Split-plane power with support for full 3.3 V I/O
Available with a low-power 1.9-V core voltage and extended temperature rating
or with a standard-power 2.2-V core voltage and standard temperature rating
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1.1
AMD-K6™-2E Embedded Processor Features
The AMD-K6-2E processor with 3DNow!™ technology is a functionally compatible
embedded version of the sixth generation, Microsoft® Windows® compatible
AMD-K6-2 processor. The AMD-K6-2E embedded processor delivers the same high
performance and incorporates the same leading-edge features, including the
innovative and efficient RISC86® microarchitecture, a large 64-Kbyte level-one cache
(32-Kbyte dual-ported data cache, 32-Kbyte instruction cache with predecode data),
and a powerful IEEE 754-compatible and 854-compatible floating-point execution
unit.
The AMD-K6-2E embedded processor also supports the new features incorporated
into the AMD-K6-2 processor. These features include superscalar MMX™ instruction
execution support, support for the Super7™ 100-MHz frontside bus, and AMD’s
innovative 3DNow!™ technology for high-performance multimedia and 3D graphics
operation based on high-performance single instruction multiple data (SIMD)
execution resources.
The AMD-K6-2E embedded processor includes several key features that are very
beneficial to the embedded market. The AMD-K6-2E processor offers leading-edge
performance for embedded systems requiring compatibility with the extensive
installed base of x86 software. The AMD-K6-2E processor’s Socket 7 and Super7
platform-compatible, 321-pin ceramic pin grid array (CPGA) package allows the
product designer to reduce time-to-market by leveraging today’s cost-effective
industry-standard infrastructure to deliver a superior-performing embedded solution.
The AMD-K6-2E embedded processor is available in two versions.
■ The low-power version has a 1.9-V core voltage and extended temperature rating.
■ The standard-power version has a 2.2-V core voltage and is the embedded
equivalent of the industry-standard desktop version of the AMD-K6-2 processor.
System Management Mode and Power Management Features
The AMD-K6-2E processor includes the complete industry-standard system
management mode (SMM), which is critical to system resource and power
management. (See “System Management Mode (SMM)” on page 217 for more
detailed information about this feature.)
The AMD-K6-2E processor also features the industry-standard Stop-Clock (STPCLK#)
control circuitry and the Halt instruction, both required for implementing the ACPI
power management specification. (“Clock Control” on page 247 provides more
information on these power management features.)
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Microarchitecture
The AMD-K6-2E processor’s RISC86 microarchitecture is a decoupled
decode/execution superscalar design that implements state-of-the-art design
techniques to achieve leading-edge performance.
Advanced design techniques implemented in the AMD-K6-2E processor include
multiple x86 instruction decode, single-clock internal RISC operations, ten execution
units that support superscalar operation, out-of-order execution, data forwarding,
speculative execution, and register renaming.
In addition, the processor supports advanced branch prediction logic by
implementing an 8192-entry branch history table, a branch target cache, and a return
address stack, which combine to deliver better than a 95% prediction rate. These
design techniques enable the AMD-K6-2E to issue, execute, and retire multiple x86
instructions per clock, resulting in excellent scalable performance. The
microarchitecture of the AMD-K6-2E processor is more completely described in
“Internal Architecture” on page 7.
3DNow!™ Technology
AMD’s 3DNow! technology is an instruction-set extension to x86, which includes 21
new instructions to accelerate 3D graphics and other single-precision floating-point
compute intensive operations.
Improvements include fast frame rates on high-resolution graphics applications,
superior modeling of real-world environments and physics, life-like images, graphics,
and audio.
AMD has already shipped millions of processors with 3DNow! technology for desktop
and notebook PCs, revolutionizing the 3D experience with up to four times the peak
floating-point performance of previous sixth generation solutions. AMD is now
bringing this advanced capability to embedded systems.
AMD has taken a leadership role in developing these new instructions that enable
exciting new levels of performance and realism. 3DNow! technology was defined and
implemented in collaboration with Microsoft, application developers, and graphics
vendors, and has received an enthusiastic reception. It is compatible with today’s
existing x86 software, is supported by industry-standard APIs, and requires no
operating system support, thereby enabling a broad class of applications to benefit
from 3DNow! technology.
Industry-Standard x86 Architecture
The AMD-K6-2E processor is x86 binary code compatible. AMD’s extensive
experience through six generations of x86 processors has been carefully integrated
into the processor to enable compatibility with Windows®-based operating systems,
including Windows 95, Windows 98, Windows CE, Windows NT®, and Windows NTE.
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The AMD-K6-2E processor is also compatible with DOS, OS/2, UNIX, and other
leading operating systems, including real-time operating systems (RTOS) commonly
used in embedded applications such as pSOS, QNX, RTXC, and VxWorks.
The AMD-K6-2E processor is compatible with more than 60,000 software
applications, including the latest software optimized for 3DNow! and MMX
technologies. AMD has shipped more than 120 million x86 microprocessors, including
more than 60 million Windows-compatible processors.
The AMD-K6-2E processor is among a long line of Microsoft Windows compatible
processors from AMD. The combination of state-of-the-art features, leading-edge
performance, high-performance multimedia engine, x86 compatibility, and low-cost
infrastructure enable decreased development costs and improved time-to-market,
making the AMD-K6-2E processor the superior choice for embedded systems.
1.2
Process Technology
The AMD-K6-2E processor is implemented using an advanced CMOS 0.25-micron
process technology that utilizes a split core and I/O voltage supply, which allows the
core of the processor to operate at a low voltage while the I/O portion operates at the
industry-standard 3.3 V.
This technology enables high performance while reducing power consumption by
operating the core at a low voltage and limiting power requirements to the acceptable
levels for today’s embedded systems.
1.3
Super7™ Platform Initiative
All AMD-K6-2E processors remain pin compatible with existing Socket 7 solutions;
however, for maximum system performance, the 300-MHz, 350-MHz, and 400-MHz
versions of the processor work optimally in Super7 designs that incorporate advanced
features such as support for the 100-MHz frontside bus and AGP graphics.
AMD and its industry partners are investing in the future of Socket 7 with the new
Super7 platform initiative. The goal of the initiative is to maintain the competitive
vitality of the Socket 7 infrastructure through a series of enhancements, including
the development of an industry-standard 100-MHz processor bus protocol. In addition
to the 100-MHz processor bus protocol, the Super7 initiative includes the
introduction of chipsets that support the AGP specification and support for a
backside L2 cache and frontside L3 cache.
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Super7™ Platform Enhancements
■ 100-MHz processor bus—The AMD-K6-2E processor supports a 100-MHz, 800
Mbyte/second frontside bus to provide a high-speed interface to Super7
platform-based chipsets. The 100-MHz interface to the frontside Level 2 (L2)
cache and main system memory speeds up access to the frontside cache and main
memory by 50 percent over the 66-MHz Socket 7 interface, resulting in a
significant increase of 10% in overall system performance.
■ Accelerated graphics port support—AGP improves the performance of video
graphics systems that have small amounts of video memory on the graphics card.
The industry-standard AGP specification enables a 133-MHz graphics interface
and will scale to even higher levels of performance.
■ Support for backside L2 and frontside L3 cache—The Super7 platform has the
‘headroom’ to support higher-performance AMD-K6 processors with clock speeds
scaling to 500 MHz and beyond. The Super7 platform also supports the
AMD-K6-III processor, which features a full-speed, internal backside 256-Kbyte L2
cache designed to deliver new levels of system performance to desktop and
notebook PC systems. The AMD-K6-III processor also supports an optional
100-MHz frontside L3 cache for even higher-performance system configurations.
Super7™ Platform Advantages
The Super7 platform has the following advantages:
■ Delivers performance and features competitive with alternate platforms at the
same clock speed, and at a significantly lower cost
■ Takes advantage of existing system designs for superior value
■ Enables OEMs and resellers to take advantage of mature, high-volume
infrastructure supported by multiple BIOS, chipset, graphics, and motherboard
suppliers
■ Reduces inventory and design costs with one motherboard for a wide range of
products
■ Builds on a huge installed base of more than 100 million motherboards
■ Provides an easy upgrade path for future embedded applications, as well as a
bridge to legacy applications
By taking advantage of the low-cost, mature Socket 7 infrastructure, the Super7
platform will continue to provide superior value and leading-edge performance for
embedded systems.
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2
Internal Architecture
The AMD-K6-2E processor implements advanced design
techniques known as the RISC86 microarchitecture. The
RISC86 microarchitecture is a decoupled decode/execution
design approach that yields superior sixth-generation
performance for x86-based software. This chapter describes the
techniques used and the functional elements of the RISC86
microarchitecture.
2.1
AMD-K6™-2E Processor Microarchitecture Overview
When discussing processor design, it is important to understand
the terms architecture, microarchitecture, and design
implementation.
■ Architecture refers to the instruction set and features of a
processor that are visible to software programs running on
the processor. The architecture determines which software
the processor can run. The architecture of the AMD-K6-2E
processor is the industry-standard x86 instruction set.
■ Microarchitecture refers to the design techniques used in the
processor to reach the target cost, performance, and
functionality goals. The AMD-K6-2E processor is based on a
sophisticated RISC core known as the Enhanced RISC86
microarchitecture. The Enhanced RISC86 microarchitecture
is an advanced, second-order decoupled decode/execution
design approach that enables industry-leading performance
for x86-based software.
■ Design implementation refers to the actual logic and circuit
designs from which the processor is created according to the
microarchitecture specifications.
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®
Enhanced RISC86
Microarchitecture
The Enhanced RISC86 microarchitecture defines the
characteristics of the AMD-K6-2E processor. The innovative
RISC86 microarchitecture approach implements the x86
instruction set by internally translating x86 instructions into
RISC86 operations. These RISC86 operations were specially
designed to include direct support for the x86 instruction set
while observing the RISC performance principles of fixed
length encoding, regularized instruction fields, and a large
register set.
The Enhanced RISC86 microarchitecture used in the
AMD-K6-2E processor enables higher processor core
performance and promotes straightforward extensibility in
future designs. Instead of directly executing complex x86
instructions, which have lengths of 1 to 15 bytes, the
AMD-K6-2E processor executes the simpler and easier
fixed-length RISC86 opcodes, while maintaining the instruction
coding efficiencies found in x86 programs.
The AMD-K6-2E processor contains parallel decoders, a
centralized RISC86 operation scheduler, and ten execution
units that support superscalar operation—multiple decode,
execution, and retirement—of x86 instructions. These elements
are packed into an aggressive and highly efficient six-stage
pipeline.
AMD-K6™-2E
Processor Block
Diagram
As shown in Figure 1 on page 9, the high-performance,
out-of-order execution engine of the AMD-K6-2E processor is
mated to a split level-one 64-Kbyte writeback cache with 32
Kbytes of instruction cache and 32 Kbytes of data cache. The
instruction cache feeds the decoders and, in turn, the decoders
feed the scheduler. The Instruction Control Unit (ICU) issues
and retires RISC86 operations contained in the scheduler. The
system bus interface is an industry-standard 64-bit Super7 and
Socket 7 demultiplexed bus.
The AMD-K6-2E processor combines the latest in processor
microarchitecture to provide the highest x86 performance for
today’s computational systems. The AMD-K6-2E offers true
sixth-generation performance and x86 binary software
compatibility.
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32-KByte Level-One Instruction Cache
20-KByte Predecode Cache
Predecode
Logic
64-Entry ITLB
16-Byte Fetch
Level-One Cache
Controller
Branch Logic
(8192-Entry BHT)
(16-Entry BTC)
(16-Entry RAS)
Multiple Instruction Decoders
x86 to RISC86
Four RISC86
Decode
100 MHz
Super7
Bus
Out-of-Order
Scheduler
Execution Engine
Instruction
Control Unit
Buffer
Interface
(24 RISC86)
Six RISC86 ®
Operation Issue
Register X Functional Units
Integer/
Multimedia/3DNow!
Register Y Functional Units
Integer/
Multimedia /3DNow!
Load
Unit
Store
Unit
Branch
Unit
FPU
Store
Queue
32-KByte Level-One Dual-Port Data Cache
128-Entry DTLB
Figure 1. AMD-K6™-2E Processor Block Diagram
Decoders
Decoding of the x86 instructions begins when the on-chip
instruction cache is filled. Predecode logic determines the
length of an x86 instruction on a byte-by-byte basis. This
predecode information is stored, along with the x86
instructions, in the instruction cache, to be used later by the
decoders. The decoders translate on-the-fly, with no additional
latency, up to two x86 instructions per clock into RISC86
operations.
Note: In this chapter, “clock” refers to a processor clock.
The AMD-K6-2E processor categorizes x86 instructions into
three types of decodes—short, long, and vector. The decoders
process either two short, one long, or one vector decode at a
time.
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The three types of decodes have the following characteristics:
■ Short decodes—x86 instructions that are less than or equal
to seven bytes long
■ Long decodes—x86 instructions less than or equal to 11
bytes long
■ Vector decodes—complex x86 instructions
Short and long decodes are processed completely within the
decoders. Vector decodes are started by the decoders and then
completed by fetched sequences from an on-chip ROM. After
decoding, the RISC86 operations are delivered to the scheduler
for dispatching to the execution units.
Scheduler/Instruction
Control Unit
The centralized scheduler or buffer is managed by the ICU. The
ICU buffers and manages up to 24 RISC86 operations at a time.
This equals from 6 to 12 x86 instructions. This buffer size (24) is
perfectly matched to the processor’s six-stage RISC86 pipeline,
four RISC86-operations decode rate, and ten parallel execution
units.
The scheduler accepts as many as four RISC86 operations at a
time from the decoders and retires up to four RISC86
operations per clock cycle. The ICU is capable of
simultaneously issuing up to six RISC86 operations at a time to
the execution units. This consists of the following types of
operations:
■ Memory load operation
■ Memory store operation
■ Complex integer, MMX, or 3DNOW! register operation
■ Simple integer register operation
■ Floating-point register operation
■ Branch condition evaluation
Registers
When managing the RISC86 operations, the ICU uses 69
physical registers contained within the RISC86
microarchitecture.
■ Forty-eight of the physical registers are located in a general
register file.
•
•
Twenty-four of these are rename registers.
The other twenty-four are committed or architectural
registers, consisting of 16 scratch registers and 8 registers
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that correspond to the x86 general-purpose registers—
EAX, EBX, ECX, EDX, EBP, ESP, ESI, and EDI.
■ An analogous set of 21 registers is available specifically for
MMX and 3DNow! operations.
•
•
Twelve of these are MMX/3DNow! rename registers.
Nine are MMX/3DNow! committed or architectural
registers, consisting of one scratch register and eight
registers that correspond to the MMX registers (mm0–
mm7). For more detailed information, see the 3DNow!™
Technology Manual, order #21928.
Branch Logic
The AMD-K6-2E processor is designed with highly
sophisticated dynamic branch logic consisting of the following:
■ Branch history/Prediction table
■ Branch target cache
■ Return address stack
The AMD-K6-2E processor implements a two-level branch
prediction scheme based on an 8192-entry branch history table.
The branch history table stores prediction information that is
used for predicting conditional branches. Because the branch
history table does not store predicted target addresses, special
address ALUs calculate target addresses on-the-fly during
instruction decode.
The branch target cache augments predicted branch
performance by avoiding a one clock cache-fetch penalty. This
specialized target cache does this by supplying the first 16 bytes
of target instructions to the decoders when branches are
predicted. The return address stack is a unique device
specifically designed for optimizing CALL and RETURN pairs.
In summary, the AMD-K6-2E processor uses dynamic branch
logic to minimize delays due to the branch instructions that are
common in x86 software.
3DNow!™ Technology
AMD has taken a lead role in improving the multimedia and 3D
capabilities of the x86 processor family with the introduction of
3DNow! technology, which uses a packed, single-precision,
floating-point data format and Single Instruction Multiple Data
(SIMD) operations also found in the MMX technology model.
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2.2
Cache, Instruction Prefetch, and Predecode Bits
The writeback level-one cache on the AMD-K6-2E processor is
organized as a separate 32-Kbyte instruction cache and a
32-Kbyte data cache with two-way set associativity. The cache
line size is 32 bytes and lines are prefetched from main memory
using an efficient pipelined burst transaction.
As the instruction cache is filled, each instruction byte is
analyzed for instruction boundaries using predecoding logic.
Predecoding annotates each instruction byte with information
(5 bits per byte) that later enables the decoders to efficiently
decode multiple instructions simultaneously.
Cache
The processor cache design takes advantage of a sectored
organization (see Figure 2). Each sector consists of 64 bytes
configured as two 32-byte cache lines. The two cache lines of a
sector share a common tag but have separate pairs of MESI
(Modified, Exclusive, Shared, Invalid) bits that track the state
of each cache line.
Tag Address
Cache Line 0 Byte 31 Predecode Bits Byte 30 Predecode Bits ........ ........ Byte 0 Predecode Bits MESI Bits
Cache Line 1 Byte 31 Predecode Bits Byte 30 Predecode Bits ........ ........ Byte 0 Predecode Bits MESI Bits
Figure 2. Cache Sector Organization
Two forms of cache misses and associated cache fills can take
place—a tag-miss cache fill and a tag-hit cache fill.
■ Tag-miss cache fill—The miss is due to a tag mismatch, in
which case the required cache line is filled from external
memory, and the cache line within the sector that was not
required is marked as invalid.
■ Tag-hit cache fill—The address matches the tag, but the
requested cache line is marked as invalid. The required
cache line is filled from external memory, and the cache line
within the sector that is not required remains in the same
cache state.
Prefetching
The AMD-K6-2E processor conditionally performs cache
prefetching which results in the filling of the required cache
line first, and a prefetch of the second cache line making up the
other half of the sector. From the perspective of the external
bus, the two cache-line fills typically appear as two 32-byte
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burst read cycles occurring back-to-back or, if allowed, as
pipelined cycles.
The 3DNow! technology includes a new instruction named
PREFETCH that allows a cache line to be prefetched into the
data cache. The PREFETCH instruction format is defined in
Table 15, “3DNow!™ Instructions,” on page 81. For more
detailed information, see the 3DNow!™ Technology Manual,
order #21928.
Predecode Bits
Decoding x86 instructions is particularly difficult because the
instructions are variable in length (1 to 15 bytes). Predecode
logic supplies the five predecode bits associated with each
instruction byte. The predecode bits indicate the number of
bytes to the start of the next x86 instruction. The predecode
bits are stored in an extended instruction cache alongside each
x86 instruction byte, as shown in Figure 2 on page 12. The
predecode bits are passed with the instruction bytes to the
decoders where they assist with parallel x86 instruction
decoding.
2.3
Instruction Fetch and Decode
Instruction Fetch
The processor can fetch up to 16 bytes per clock out of the
instruction cache or branch target cache. The fetched
information is placed into a 16-byte instruction buffer that
feeds directly into the decoders (see Figure 3 on page 14).
Fetching can occur along a single execution stream with up to
seven outstanding branches taken.
The instruction fetch logic is capable of retrieving any 16
contiguous bytes of information within a 32-byte boundary.
There is no additional penalty when the 16 bytes of instructions
lie across a cache line boundary. The instruction bytes are
loaded into the instruction buffer as they are consumed by the
decoders.
Although instructions can be consumed with byte granularity,
the instruction buffer is managed on a memory-aligned word
(two bytes) organization. Therefore, instructions are loaded and
replaced with word granularity. When a control transfer
occurs—such as a JMP instruction—the entire instruction
buffer is flushed and reloaded with a new set of 16 instruction
bytes.
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Branch-Target Cache
16 x 16 Bytes
16 Bytes
32-Kbyte Level-One
Instruction Cache
16 Bytes
2:1
Branch Target
Address Adders
Return Address Stack
16 x 16 Bytes
Fetch Unit
16 Instruction Bytes
plus
16 Sets of Predecode Bits
Instruction Buffer
Figure 3. The Instruction Buffer
Instruction Decode
The AMD-K6-2E processor decode logic is designed to decode
multiple x86 instructions per clock (see Figure 4 on page 15).
The decode logic accepts x86 instruction bytes and their
predecode bits from the instruction buffer, locates the actual
instruction boundaries, and generates RISC86 operations from
these x86 instructions.
RISC86 operations are fixed-format internal instructions. Most
RISC86 operations execute in a single clock. RISC86 operations
are combined to perform every function of the x86 instruction
set. Some x86 instructions are decoded into as few as zero
RISC86 opcodes, for instance a NOP, or one RISC86 operation,
a register-to-register add. More complex x86 instructions are
decoded into several RISC86 operations.
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Instruction Buffer
Short Decoder #1
Short Decoder #2
Long Decoder
On-Chip ROM
Vector Decoder
RISC86® Sequencer
Vector Address
4 RISC86 Operations
Figure 4. AMD-K6™-2E Processor Decode Logic
The AMD-K6-2E processor uses a combination of decoders to
convert x86 instructions into RISC86 operations. The hardware
consists of three sets of decoders—two parallel short decoders,
one long decoder, and one vector decoder.
Parallel Short Decoders. The two parallel short decoders translate
the most commonly-used x86 instructions (moves, shifts,
branches, ALU, FPU) and the extensions to the x86 instruction
set (MMX and 3DNow! technology) into zero, one, or two
RISC86 operations each. The short decoders only operate on
x86 instructions that are up to seven bytes long. In addition, the
decoders are designed to decode up to two x86 instructions per
clock.
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Long Decoder. The commonly-used x86 instructions that are
greater than seven bytes but not more than 11 bytes long, and
the x86 instructions that are slightly less common and are up to
seven bytes long are handled by the long decoder. The long
decoder only performs one decode per clock and generates up
to four RISC86 operations.
Vector Decoder. All other translations (complex instructions,
serializing conditions, interrupts and exceptions, etc.) are
handled by a combination of the vector decoder and RISC86
operation sequences fetched from an on-chip ROM. For
complex operations, the vector decoder logic provides the first
set of RISC86 operations and a vector (initial ROM address) to a
sequence of further RISC86 operations. The same types of
RISC86 operations are fetched from the ROM as those that are
generated by the hardware decoders.
Note: Although all three sets of decoders are simultaneously fed a
copy of the instruction buffer contents, only one of the three
types of decoders is used during any one decode clock.
Grouped Operations. The decoders or the RISC86 sequencer
always generate a group of four RISC86 operations. For decodes
that cannot fill the entire group with four RISC86 operations,
RISC86 NOP operations are placed in the empty locations of
the grouping. For example, a long-decoded x86 instruction that
converts to only three RISC86 operations is padded with a
single RISC86 NOP operation and then passed to the scheduler.
Up to six groups, or 24 RISC86 operations, can be placed in the
scheduler at a time.
Floating Point Instructions. All of the common, and a few of the
uncommon, floating-point instructions (also known as ESC
instructions) are hardware decoded as short decodes. This
decode generates a RISC86 floating-point operation and,
optionally, an associated floating-point load or store operation.
Floating-point or ESC instruction decode is only allowed in the
first short decoder, but non-ESC instructions, excluding MMX
instructions, can be decoded simultaneously by the second
short decoder along with an ESC instruction decode in the first
short decoder.
MMX and 3DNow!™ Instructions. All of the MMX and 3DNow!
instructions, with the exception of the EMMS, FEMMS, and
PREFETCH instructions, are hardware decoded as short
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decodes. The MMX instruction decode generates a RISC86
MMX operation and, optionally, an associated MMX load or
store operation. A 3DNow! instruction decode generates a
RISC86 3DNow! operation and, optionally, an associated load or
store operation. MMX and 3DNow! instructions can be decoded
in either or both of the short decoders.
2.4
Centralized Scheduler
The scheduler is the heart of the AMD-K6-2E processor (see
Figure 5 on page 18). The scheduler contains the logic necessary
to manage out-of-order execution, data forwarding, register
renaming, simultaneous issue and retirement of multiple
RISC86 operations, and speculative execution.
The scheduler’s buffer can hold up to 24 RISC86 operations.
This equates to a maximum of 12 x86 instructions. When
possible, the scheduler can simultaneously issue a RISC86
operation to any available execution unit (store, load, branch,
integer, integer/multimedia, or floating-point). In total, the
scheduler can issue up to six and retire up to four RISC86
operations per clock.
The main advantage of the scheduler and its operation buffer is
the ability to examine an x86 instruction window equal to 12
x86 instructions at one time. This advantage is due to the fact
that the scheduler operates on the RISC86 operations in
parallel and allows the AMD-K6-2E processor to perform
dynamic on-the-fly instruction code scheduling for optimized
execution. Although the scheduler can issue RISC86 operations
for out-of-order execution, it always retires x86 instructions in
order.
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From Decode Logic
RISC86 #0
RISC86 #3
RISC86 #1
RISC86 #2
Centralized RISC86®
Operation Scheduler
RISC86 Issue Buses
RISC86 Operation Buffer
Figure 5. AMD-K6™-2E Processor Scheduler
2.5
Execution Units
The AMD-K6-2E processor contains ten parallel execution
units—store, load, integer X ALU, integer Y ALU, MMX ALU
(X), MMX ALU (Y), MMX/3DNow! multiplier, 3DNow! ALU,
floating-point, and branch condition. Each unit is independent
and capable of handling the RISC86 operations. Table 1 on
page 19 details the execution units, functions performed within
these units, operation latency, and operation throughput.
The store and load execution units are two-stage pipelined
designs.
■ The store unit performs data writes and register calculation
for LEA/PUSH. Data memory and register writes from stores
are available after one clock. Store operations are held in a
store queue prior to execution. From there, they execute in
order.
■ The load unit performs data memory reads. Data is available
from the load unit after two clocks.
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The Integer X execution unit can operate on all ALU
operations, multiplies, divides (signed and unsigned), shifts,
and rotates.
The Integer Y execution unit can operate on the basic word and
doubleword ALU operations—ADD, AND, CMP, OR, SUB,
XOR, zero-extend, and sign-extend operands.
Table 1. Execution Latency and Throughput of Execution Units
Functional Unit
Store
Function
Latency Throughput
LEA/PUSH, Address (Pipelined)
Memory Store (Pipelined)
Memory Loads (Pipelined)
Integer ALU
1
1
1
1
Load
2
1
1
1
Integer X
Integer Multiply
2–3
1
2–3
1
Integer Shift
MMX ALU
1
1
Multimedia
(processes
MMX instructions)
MMX Shifts, Packs, Unpack
MMX Multiply
1
1
2
1
Integer Y
Branch
FPU
Basic ALU (16-bit and 32-bit operands)
Resolves Branch Conditions
FADD, FSUB, FMUL
3DNow! ALU
1
1
1
1
2
2
2
1
3DNow!
3DNow! Multiply
2
1
3DNow! Convert
2
1
The functional units that execute MMX and 3DNow!
instructions share pipeline control with the Integer X and
Integer Y units.
Register X and Y
Pipelines
The register X and Y functional units are attached to the issue
bus for the register X execution pipeline or the issue bus for the
register Y execution pipeline or both. Each register pipeline
has dedicated resources that consist of an integer execution
unit and an MMX ALU execution unit, therefore allowing
superscalar operation on integer and MMX instructions. In
addition, both the X and Y issue buses are connected to the
3DNow! ALU, the MMX/3DNow! multiplier, and MMX shifter,
which allows the appropriate RISC86 operation to be issued
through either bus. Figure 6 on page 20 shows the details of the
X and Y register pipelines.
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Scheduler
Buffer
(24 RISC86® Operations)
Issue Bus
for the
Register X
Execution
Pipeline
Issue Bus
for the
Register Y
Execution
Pipeline
Integer X
MMXÉ
ALU
MMX
Shifter
3DNow!
ALU
MMX
ALU
Integer Y
MMX/
3DNow!É
Multiplier
ALU
ALU
Figure 6. Register X and Y Functional Units
The branch condition unit is separate from the branch
prediction logic in that it resolves conditional branches such as
JCC and LOOP after the branch condition has been evaluated.
2.6
Branch-Prediction Logic
Sophisticated branch logic that can minimize or hide the impact
of changes in program flow is designed into the AMD-K6-2E
processor. Branches in x86 code fit into two categories:
■ Unconditional branches always change program flow (that is,
the branches are always taken)
■ Conditional branches may or may not divert program flow
(that is, the branches are taken or not-taken). When a
conditional branch is not taken, the processor simply
continues decoding and executing the next instructions in
memory.
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Typical applications have up to 10% of unconditional branches
and another 10% to 20% conditional branches. The AMD-K6-2E
processor branch logic has been designed to handle this type of
program behavior and its negative effects on instruction
execution, such as stalls due to delayed instruction fetching and
the draining of the processor pipeline. The branch logic
contains an 8192-entry branch history table, a 16-entry by
16-byte branch target cache, a 16-entry return address stack,
and a branch execution unit.
Branch History Table
The AMD-K6-2E processor handles unconditional branches
without any penalty by redirecting instruction fetching to the
target address of the unconditional branch. However,
conditional branches require the use of the dynamic
branch-prediction mechanism built into the AMD-K6-2E
processor.
A two-level adaptive history algorithm is implemented in an
8192-entry branch history table. This table stores executed
branch information, predicts individual branches, and predicts
the behavior of groups of branches.
To accommodate the large branch history table, the AMD-K6-2E
processor does not store predicted target addresses. Instead,
the branch target addresses are calculated on-the-fly using
ALUs during the decode stage. The adders calculate all
possible target addresses before the instructions are fully
decoded, and the processor chooses which addresses are valid.
Branch Target Cache
To avoid a one clock cache-fetch penalty when a branch is
predicted taken, a built-in branch target cache supplies the first
16 bytes of instructions directly to the instruction buffer
(assuming the target address hits this cache). (See Figure 3 on
page 14.)
The branch target cache is organized as 16 entries of 16 bytes.
In total, the branch prediction logic achieves branch prediction
rates greater than 95%.
Return Address Stack
The return address stack is a special device designed to
optimize CALL and RET pairs. Software is typically compiled
with subroutines that are frequently called from various places
in a program. This is usually done to save space.
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Entry into the subroutine occurs with the execution of a CALL
instruction. At that time, the processor pushes the address of
the next instruction in memory following the CALL instruction
onto the stack (allocated space in memory). When the processor
encounters a RET instruction (within or at the end of the
subroutine), the branch logic pops the address from the stack
and begins fetching from that location. To avoid the latency of
main memory accesses during CALL and RET operations, the
return address stack caches the pushed addresses.
Branch Execution
Unit
The branch execution unit enables efficient speculative
execution. This unit gives the processor the ability to execute
instructions beyond conditional branches before knowing
whether the branch prediction was correct.
The AMD-K6-2E processor does not permanently update the
x86 registers or memory locations until all speculatively
executed conditional branch instructions are resolved. When a
prediction is incorrect, the processor backs out to the point of
the mispredicted branch instruction and restores all registers.
The AMD-K6-2E processor can support up to seven outstanding
branches.
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3
Software Environment
This chapter provides a general overview of the AMD-K6-2E
processor’s x86 software environment and briefly describes the
data types, registers, operating modes, interrupts, and
instructions supported by the AMD-K6-2E architecture and
design implementation.
The stepping of the Model 8 version of the processor
determines the implementation and format of ten Model-
Specific Registers (MSRs).
The AMD-K6-2E processor supports Model 8 steppings [F:8] in
any of eight possible model/steppings—Models 8/8, 8/9, 8/A, 8/B,
8/C, 8/D, 8/E, or 8/F.
Note that the name AMD-K6-2E processor by itself refers to all
steppings of the Model 8/[F:8] version.
3.1
Registers
The AMD-K6-2E processor contains all the registers defined by
the x86 architecture, including general-purpose, segment,
floating-point, MMX/3DNow!, EFLAGS, control, task, debug,
test, and descriptor/memory-management registers.
In addition to information about these registers, this chapter
provides information on the AMD-K6-2E processor MSRs.
Note: Areas of the register designated as Reserved should not be
modified by software.
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General-Purpose
Registers
The eight 32-bit x86 general-purpose registers are used to hold
integer data or memory pointers used by instructions. Table 2
contains a list of the general-purpose registers and the
functions for which they are used.
Table 2. General-Purpose Registers
Register Function
EAX
EBX
ECX
EDX
EDI
ESI
Commonly used as an accumulator
Commonly used as a pointer
Commonly used for counting in loop operations
Commonly used to hold I/O information and to pass parameters
Commonly used as a destination pointer by the ES segment
Commonly used as a source pointer by the DS segment
Used to point to the stack segment
ESP
EBP
Used to point to data within the stack segment
To support byte and word operations, EAX, EBX, ECX, and
EDX can also be used as 8-bit and 16-bit registers. The shorter
registers are overlaid on the longer ones. For example, the
name of the 16-bit version of EAX is AX (low 16 bits of EAX)
and the 8-bit names for AX are AH (high order bits) and AL (low
order bits). The same naming convention applies to EBX, ECX,
and EDX.
EDI, ESI, ESP, and EBP can be used as smaller 16-bit registers
called DI, SI, SP, and BP respectively, but these registers do not
have 8-bit versions. Figure 7 shows the EAX register with its
name components, and Table 3 on page 25 lists the doubleword
(32-bit) general-purpose registers and their corresponding word
(16-bit) and byte (8-bit) versions.
31
16 15
8
7
0
EAX
AX
AL
AH
Figure 7. EAX Register with 16-Bit and 8-Bit Name Components
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Table 3. General-Purpose Register Doubleword, Word, and Byte Names
32-Bit Name
(Doubleword)
16-Bit Name
(Word)
8-Bit Name
(High-order Bits) (Low-order Bits)
8-Bit Name
EAX
EBX
ECX
EDX
EDI
ESI
AX
BX
CX
DX
DI
AH
BH
CH
DH
–
AL
BL
CL
DL
–
SI
–
–
ESP
EBP
SP
BP
–
–
–
–
Integer Data Types
Four types of data are used in general-purpose registers—byte,
word, doubleword, and quadword integers. Figure 8 shows the
format of the integer data registers.
Byte Integer
7
0
Precision —
8 Bits
Word Integer
15
0
Precision — 16 Bits
Doubleword Integer
31
0
Precision — 32 Bits
Quadword Integer
63
0
Precision — 64 Bits
Figure 8. Integer Data Registers
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Segment Registers
The six 16-bit segment registers are used as pointers to areas
(segments) of memory. Table 4 lists the segment registers and
their functions. Figure 9 shows the format for all six segment
registers.
Table 4. Segment Registers
Segment
Segment Register Function
Register
CS
DS
ES
FS
GS
SS
Code segment, where instructions are located
Data segment, where data is located
Data segment, where data is located
Data segment, where data is located
Data segment, where data is located
Stack segment
15
0
Figure 9. Segment Register
Segment Usage
The operating system determines the type of memory model
that is implemented. The segment register usage is determined
by the operating system’s memory model. In a real mode
memory model, the segment register points to the base address
in memory.
In a protected mode memory model, the segment register is
called a selector and it selects a segment descriptor in a
descriptor table. This descriptor contains a pointer to the base
of the segment, the limit of the segment, and various protection
attributes. For more information on descriptor formats, see
“Descriptors and Gates” on page 52. Figure 10 on page 27 shows
segment usage for real mode and protected mode memory
models.
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Physical Memory
Segment Base
Segment Register
Real Mode Memory Model
Descriptor Table
Physical Memory
Base
Limit
Base
Base
Limit
Segment Base
Segment Selector
Protected Mode Memory Model
Figure 10. Segment Usage
Instruction Pointer
The instruction pointer (EIP or IP) is used in conjunction with
the code segment register (CS). The instruction pointer is
either a 32-bit register (EIP) or a 16-bit register (IP) that keeps
track of where the next instruction resides within memory. This
register cannot be directly manipulated, but can be altered by
modifying return pointers when a JMP or CALL instruction is
used.
Floating-Point
Registers
The floating-point execution unit in the AMD-K6-2E processor
is designed to perform mathematical operations on non-integer
numbers. This floating-point unit conforms to the IEEE 754 and
854 standards and uses several registers to meet these
standards—eight numeric floating-point registers, a status
word register, a control word register, and a tag word register.
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The eight floating-point registers are physically 80 bits wide
and labeled FPR0–FPR7. Figure 11 shows the format of these
floating-point registers. See “Floating-Point Register Data
Types” on page 30 for information on allowable floating-point
data types.
79 78
Sign
64 63
0
Exponent
Significand
Figure 11. Floating-Point Register
The 16-bit FPU status word register contains information about
the state of the floating-point unit. Figure 12 shows the format
of the FPU status word register.
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
C
2
C
1
C
0
E
S
S
F
P
E
U
E
O
E
Z
E
I
E
C
3
D
E
B
TOSP
Symbol
B
C3
TOSP
C2
C1
C0
ES
SF
Description
FPU Busy
Bits
15
14
13–11
10
9
8
7
6
Condition Code
Top of Stack Pointer
Condition Code
Condition Code
Condition Code
Error Summary Status
Stack Fault
Exception Flags
Precision Error
Underflow Error
Overflow Error
Zero Divide Error
Denormalized Operation Error 1
Invalid Operation Error
TOSP Information
000 = FPR0
PE
UE
OE
ZE
DE
IE
5
4
3
2
0
111 = FPR7
Figure 12. FPU Status Word Register
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The FPU control word register allows a programmer to manage
the FPU processing options. Figure 13 shows the format of the
FPU control word register.
15 14 13 12 11 10
9
8
7
6
5
P
4
3
2
Z
1
0
Y
R
C
P
C
U
O
I
M
D
M
M M M M
Reserved
Symbol
Description
Bits
Y
Infinity Bit (80287 compatibility) 12
RC
PC
Rounding Control
Precision Control
Exception Masks
Precision
Underflow
Overflow
Zero Divide
Denormalized Operation
Invalid Operation
11–10
9–8
PM
UM
OM
ZM
DM
IM
5
4
3
2
1
0
Rounding Control Information
00b = Round to the nearest or even number
01b = Round down toward negative infinity
10b = Round up toward positive infinity
11b = Truncate toward zero
Precision Control Information
00b = 24 bits Single Precision Real
01b = Reserved
10b = 53 bits Double Precision Real
11b = 64 bits Extended Precision Real
Figure 13. FPU Control Word Register
The FPU tag word register contains information about the
registers in the register stack. Figure 14 shows the format of the
FPU tag word register.
15
14 13
12 11
10 9
8 7
6 5
4 3
2 1
0
TAG
(FPR7)
TAG
TAG
TAG
TAG
TAG
TAG
TAG
(FPR6) (FPR5) (FPR4) (FPR3) (FPR2) (FPR1) (FPR0)
Tag Values
00 = Valid
01 = Zero
10 = Special
11 = Empty
Figure 14. FPU Tag Word Register
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Floating-Point
Register Data Types
Floating-point registers use four different types of data—
packed decimal, single-precision real, double-precision real,
and extended-precision real. Figures 15 and 16 show the
formats for these registers.
79 78 72 71
0
Ignore
or
S
Precision — 18 Digits, 72 Bits Used, 4-Bits/Digit
Zero
Description
Ignored on Load, Zeros on Store 78-72
Sign Bit 79
Bits
Figure 15. Packed Decimal Data Register
31 30
23 22
0
Single-Precision Real
Biased
Exponent
Significand
S
S= Sign Bit
Double-Precision Real
63 62
S
52 51
0
Biased
Exponent
Significand
S = Sign Bit
Extended-Precision Real
79 78
S
64 63 62
0
Biased
Exponent
I
Significand
S= Sign Bit
I = Integer Bit
Figure 16. Precision Real Data Registers
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MMX™/3DNow!™
Registers
The AMD-K6-2E processor implements eight 64-bit
MMX/3DNow! registers for use by multimedia software. These
registers are mapped on the floating-point register stack. The
MMX and 3DNow! instructions refer to these registers as mm0
to mm7. Figure 17 shows the format of these registers. For more
information, see the AMD-K6® Processor Multimedia
Technology Manual, order #20726 and the 3DNow! Technology
Manual, order #21928.
63
0
mm0
mm1
mm2
mm3
mm4
mm5
mm6
mm7
Figure 17. MMX™/3DNow!™ Registers
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MMX™ Data Types
For the MMX instructions, the MMX registers use three types of
data—packed 8-byte integer, packed quadword integer, and
packed dual doubleword integer. Figure 18 shows the format of
the MMX data types.
Packed Bytes Integer
63
56 55
48 47
40 39
32 31
32 31
32 31
24 23
16 15
8
7
0
0
0
Byte 7
Byte 6
Byte 5
Byte 4
Byte 3
Byte 2
Byte 1
Byte 0
Packed Words Integer
63
48 47
16 15
Word 3
Word 2
Word 1
Word 0
Packed Doubleword Integer
63
Doubleword 1
Doubleword 0
Figure 18. MMX™ Data Types
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3DNow!™ Data Types
For 3DNow! instructions, the MMX/3DNow! registers use
packed single-precision real data. Figure 19 shows the format of
the 3DNow! data type.
Packed Single Precision Floating Point
0
63 62
S
55 54
Biased
32 31 30
23 22
Biased
Exponent
S
Significand
Significand
Exponent
S = Sign Bit
S = Sign Bit
Figure 19. 3DNow!™ Data Types
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EFLAGS Register
The EFLAGS register provides for three different types of
flags—system, control, and status. The system flags provide
operating system controls, the control flag provides directional
information for string operations, and the status flags provide
information resulting from logical and arithmetic operations.
Figure 20 shows the format of the EFLAGS register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
I
V
I
P
V
I
F
O
P
L
I
D
A
C
V
M
R
F
N
T
O
F
D
F
I
F
T
F
S
F
Z
F
A
F
P
F
C
F
Reserved
Symbol
ID
Description
ID Flag
Bits
21
20
19
18
17
16
14
13–12
11
10
9
VIP
VIF
AC
VM
RF
NT
IOPL
OF
DF
IF
Virtual Interrupt Pending
Virtual Interrupt Flag
Alignment Check
Virtual-8086 Mode
Resume Flag
Nested Task
I/O Privilege Level
Overflow Flag
Direction Flag
Interrupt Flag
Trap Flag
TF
8
SF
Sign Flag
7
ZF
Zero Flag
6
AF
PF
Auxiliary Flag
Parity Flag
4
2
CF
Carry Flag
0
Figure 20. EFLAGS Register
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AMD-K6™-2E Processor Data Sheet
Control Registers
The five control registers contain system control bits and
pointers. Figures 21 through 25 show the formats of the control
registers.
31
7
6
5
4
3
2
1
0
M
C
E
P
S
E
T
S
D
P
V
I
V
M
E
D
E
Reserved
Symbol
MCE
PSE
Description
Machine Check Enable
Page Size Extensions
Bit
6
4
DE
TSD
PVI
Debugging Extensions
Time Stamp Disable
Protected Virtual Interrupts
Virtual-8086 Mode Extensions
3
2
1
0
VME
Figure 21. Control Register 4 (CR4)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Page Directory Base
9
8
7
6
5
4
3
2
1
0
P
W
T
P
C
D
Reserved
Symbol
PCD
Description
Page Cache Disable
Bit
4
PWT
Page Writethrough
3
Figure 22. Control Register 3 (CR3)
31
0
Page Fault Linear Address
Figure 23. Control Register 2 (CR2)
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Preliminary Information
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31
0
Reserved
Figure 24. Control Register 1 (CR1)
Symbol
PG
CD
Description
Paging
Cache Disable
Not Writethrough
Bit
31
30
29
NW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
P
G
C
N
A
M
W
P
N
E
E
T
T
S
E
M
M
P
P
E
D W
Reserved
Symbol
AM
WP
NE
ET
TS
EM
MP
PE
Description
Alignment Mask
Write Protect
Numeric Error
Extension Type
Task Switched
Emulation
Bit
18
16
5
4
3
2
1
0
Monitor Co-processor
Protection Enabled
Figure 25. Control Register 0 (CR0)
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AMD-K6™-2E Processor Data Sheet
Debug Registers
Figures 26 through 29 show the 32-bit debug registers
supported by the processor. These registers are further
described in “Debug” on page 240.
Symbol
LEN 3
R/W 3
LEN 2
R/W 2
LEN 1
R/W 1
LEN 0
R/W 0
Description
Length of Breakpoint #3
Bits
31–30
Type of Transaction(s) to Trap 29–28
Length of Breakpoint #2 27–26
Type of Transaction(s) to Trap 25–24
Length of Breakpoint #1 23–22
Type of Transaction(s) to Trap 21–20
Length of Breakpoint #0 19–18
Type of Transaction(s) to Trap 17–16
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G
D
G
E
L
E
G
3
L
3
L
2
L
2
G
1
L
1
G
0
L
0
LEN
3
R/W LEN R/W
LEN
1
R/W LEN
R/W
0
3
2
2
1
0
Reserved
Symbol
GD
GE
LE
Description
General Detect Enabled
Global Exact Breakpoint Enabled
Local Exact Breakpoint Enabled
Bit
13
9
8
G3
L3
G2
L2
G1
L1
G0
L0
Global Exact Breakpoint # 3 Enabled
Local Exact Breakpoint # 3 Enabled
Global Exact Breakpoint # 2 Enabled
Local Exact Breakpoint # 2 Enabled
Global Exact Breakpoint # 1 Enabled
Local Exact Breakpoint # 1 Enabled
Global Exact Breakpoint # 0 Enabled
Local Exact Breakpoint # 0 Enabled
7
6
5
4
3
2
1
0
Figure 26. Debug Register DR7
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
B
D
B
S
B
3
B
2
B
1
B
0
B
T
Reserved
Symbol
BT
BS
Description
Breakpoint Task Switch
Breakpoint Single Step
Bit
15
14
BD
B3
B2
B1
B0
Breakpoint Debug Access Detected 13
Breakpoint #3 Condition Detected
Breakpoint #2 Condition Detected
Breakpoint #1 Condition Detected
Breakpoint #0 Condition Detected
3
2
1
0
Figure 27. Debug Register DR6
DR5
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
DR4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
Figure 28. Debug Registers DR5 and DR4
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AMD-K6™-2E Processor Data Sheet
DR3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Breakpoint 3 32-bit Linear Address
9
8
7
6
5
4
3
2
1
0
DR2
DR1
DR0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Breakpoint 2 32-bit Linear Address
9
8
7
6
5
4
3
2
1
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Breakpoint 1 32-bit Linear Address
9
8
7
6
5
4
3
2
1
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Breakpoint 0 32-bit Linear Address
9
8
7
6
5
4
3
2
1
0
Figure 29. Debug Registers DR3, DR2, DR1, and DR0
Chapter 3
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Preliminary Information
AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
3.2
Model-Specific Registers (MSR)
The AMD-K6-2E processor is based on and functionally
identical to the AMD-K6-2 processor Model 8/[F:8], which
provides ten model-specific registers (MSRs).
■ The value in the ECX register selects the MSR to be
addressed by the RDMSR and WRMSR instructions.
■ The values in EAX and EDX are used as inputs and outputs
by the RDMSR and WRMSR instructions.
Table 5 lists the MSRs and the corresponding value of the ECX
register. Figures 30 through 39 show the MSR formats.
Table 5. AMD-K6™-2E Processor Model 8/[F:8] Model-Specific Registers
Model-Specific Register
Value of ECX
00h
Machine-Check Address Register (MCAR)
Machine-Check Type Register (MCTR)
Test Register 12 (TR12)
01h
0Eh
Time Stamp Counter (TSC)
10h
Extended Feature Enable Register (EFER)
SYSCALL/SYSRET Target Address Register (STAR)
Write Handling Control Register (WHCR)
UC/WC Cacheability Control Register (UWCCR)
Processor State Observability Register (PSOR)
Page Flush/Invalidate Register (PFIR)
C000_0080h
C000_0081h
C000_0082h
C000_0085h
C000_0087h
C000_0088h
For more information about the MSRs, see the AMD-K6®
Processor BIOS Design Application Note, order #21329.
For more information about the RDMSR and WRMSR
instructions, see the AMD K86™ Family BIOS and Software Tools
Development Guide, order #21062.
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AMD-K6™-2E Processor Data Sheet
MCAR and MCTR
The AMD-K6-2E processor does not support the generation of a
machine-check exception. However, the processor does provide
a 64-bit machine-check address register (MCAR), a 64-bit
machine-check type register (MCTR), and a machine check
enable (MCE) bit in CR4.
Because the processor does not support machine check
exceptions, the contents of the MCAR and MCTR registers are
only affected by the WRMSR instruction and by RESET being
sampled asserted (where all bits in each register are reset to 0).
The formats for the machine-check address register and the
machine-check type register are shown in Figure 30 and Figure
31, respectively.
63
0
MCAR
Figure 30. Machine-Check Address Register (MCAR)
63
5
4
0
MCTR
Reserved
Figure 31. Machine-Check Type Register (MCTR)
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AMD-K6™-2E Processor Data Sheet
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Test Register 12
(TR12)
Test register 12 provides a method for disabling the L1 caches.
Figure 32 shows the format of the TR12 register.
63
4
2
1
0
3
C
I
Symbol Description
CI Cache Inhibit Bit
Bit
3
Reserved
Figure 32. Test Register 12 (TR12)
Time Stamp Counter
With each processor clock cycle, the processor increments the
64-bit time stamp counter (TSC) MSR. Figure 33 shows the
format of the TSC register.
63
0
TSC
Figure 33. Time Stamp Counter (TSC)
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AMD-K6™-2E Processor Data Sheet
Extended Feature
Enable Register
(EFER)
The extended feature enable register (EFER) contains the
control bits that enable the extended features of the
AMD-K6-2E processor. Figure 34 shows the format of the EFER
register, and Table 6 defines the function of each bit in the
EFER register.
63
4
3
2
1
0
S
C
E
D
P
E
EWBEC
Reserved
Symbol
EWBEC
DPE
Description
EWBE# Control
Data Prefetch Enable
System Call Extension
Bit
3-2
1
SCE
0
Figure 34. Extended Feature Enable Register (EFER)
Table 6. Extended Feature Enable Register (EFER)Definition
Bit
Description
R/W Function
63–4
Reserved
R
Writing a 1 to any reserved bit causes a general protection fault to occur. All
reserved bits are always read as 0.
3-2
1
EWBE# Control
(EWBEC)
R/W This 2-bit field controls the behavior of the processor with respect to the ordering of
write cycles and the EWBE# signal. EFER[3] and EFER[2] are Global EWBE# Disable
(GEWBED) and Speculative EWBE# Disable (SEWBED), respectively.
Data Prefetch Enable
(DPE)
R/W DPE must be set to 1 to enable data prefetching (this is the default setting following
reset). If enabled, cache misses initiated by a memory read within a 32-byte cache
line are conditionally followed by cache-line fetches of the other line in the 64-byte
sector.
0
System Call Extension
(SCE)
R/W
SCE must be set to 1 to enable the usage of the SYSCALL and SYSRET instructions.
For more information about the EWBEC bits, see “EWBE#
Control” on page 205.
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AMD-K6™-2E Processor Data Sheet
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SYSCALL/SYSRET
Target Address
Register (STAR)
The SYSCALL/SYSRET target address register (STAR)
contains the target EIP address used by the SYSCALL
instruction and the 16-bit code and stack segment selector
bases used by the SYSCALL and SYSRET instructions. Figure
35 shows the format of the STAR register, and Table 7 defines
the function of each bit of the STAR register. For more
information, see the SYSCALL and SYSRET Instruction
Specification Application Note, order #21086.
63
31
32
0
48 47
SYSRET CS Selector and SS
Selector Base
SYSCALL CS Selector and SS
Selector Base
Target EIP Address
Figure 35. SYSCALL/SYSRET Target Address Register (STAR)
Table 7. SYSCALL/SYSRET Target Address Register (STAR) Definition
Bit
Description
R/W
R/W
R/W
R/W
63–48
47–32
31–0
SYSRET CS and SS Selector Base
SYSCALL CS and SS Selector Base
Target EIP Address
Write Handling
Control Register
(WHCR)
The write handling control register (WHCR) is an MSR that
contains two fields—the write allocate enable limit (WAELIM)
field, and the write allocate enable 15-to-16-Mbyte (WAE15M)
bit. Figure 36 shows the format of the WHCR register. See
“Write Allocate” on page 192 for more information.
63
32 31
22 21 17 16 15
0
W
A
E
WAELIM
1
5
M
Reserved
Symbol
WAELIM
WAE15M
Description
Write Allocate Enable Limit
Write Allocate Enable 15-to-16-Mbyte 16
Bits
31-22
Note: Hardware RESET initializes this MSR to all zeros.
Figure 36. Write Handling Control Register (WHCR)
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AMD-K6™-2E Processor Data Sheet
UC/WC Cacheability
Control Register
(UWCCR)
The AMD-K6-2E processor provides two variable-range Memory
Type Range Registers (MTRRs)—MTRR0 and MTRR1—that
each specify a range of memory. Each range can be defined as
uncacheable (UC) or write-combining (WC) memory. Figure 37
shows the format of the UWCCR register. For more detailed
information about the MTRR0, MTRR1, and UWCCR registers,
see “Memory Type Range Registers” on page 207.
.
Symbol Description
Bits
32
Symbol Description
Bits
0
UC1
Uncacheable Memory Type
UC0
Uncacheable Memory Type
WC1
Write-Combining Memory Type 33
WC0
Write-Combining Memory Type
1
63
49 48
34 33 32 31
17 16
2
1
0
W
C
1
U
C
1
W
C
0
U
C
0
Physical Base Address 1
Physical Address Mask 1
Physical Base Address 0
Physical Address Mask 0
MTRR1
MTRR0
Figure 37. UC/WC Cacheability Control Register (UWCCR)
Processor State
Observability
The AMD-K6-2E processor provides the processor state
observability register (PSOR) (see Figure 38).
Register (PSOR)
63
4
3
2
0
9
8
7
N
O
L
STEP
BF
2
Reserved
Symbol
Description
Bit
8
7-4
2-0
NOL2
STEP
BF
No L2 Functionality
Processor Stepping
Bus Frequency Divisor
Figure 38. Processor State Observability Register (PSOR)
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AMD-K6™-2E Processor Data Sheet
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Page Flush/Invalidate
Register (PFIR)
The AMD-K6-2E processor contains the Page Flush/Invalidate
Register (PFIR) (see Figure 39) that allows cache invalidation
and optional flushing of a specific 4-Kbyte page from the linear
address space. Using this register can result in a much lower
cycle count for flushing particular pages versus flushing the
entire cache. When the PFIR is written to (using the WRMSR
instruction), the invalidation and, optionally, the flushing
begins.
63
32 31
12 11 9 8 7
1 0
F
/
I
P
F
LINPAGE
Reserved
Symbol
Description
Bit
LINPAGE 20-bit Linear Page Address
31-12
PF
F/I
Page Fault Occurred
Flush/Invalidate Command
8
0
Figure 39. Page Flush/Invalidate Register (PFIR)
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AMD-K6™-2E Processor Data Sheet
3.3
Memory Management Registers
The AMD-K6-2E processor controls segmented memory
management with the registers listed in Table 8. Figure 40
shows the formats of the memory management registers.
Table 8. Memory Management Registers
Register Name
Function
Global Descriptor Table Register
Interrupt Descriptor Table Register
Local Descriptor Table Register
Task Register
Contains a pointer to the base of the global descriptor table
Contains a pointer to the base of the interrupt descriptor table
Contains a pointer to the local descriptor table of the current task
Contains a pointer to the task state segment of the current task
Global and Interrupt Descriptor Table Registers
15
16
0
47
32-Bit Linear Base Address
16-Bit Limit
Selector
Local Descriptor Table Register and Task Register
15
0
63
32 31
0
32-Bit Linear Base Address
32-Bit Limit
15
0
Attributes
Figure 40. Memory Management Registers
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Task State Segment
Figure 41 shows the format of the task state segment (TSS).
31
0
TSS Limit
from TR
I/O Permission Bitmap (IOPB)
(up to 8 Kbytes)
Interrupt Redirection Bitmap (IRB)
(eight 32-bit locations)
Operating System
Data Structure
Base Address of IOPB
0000h
T
64h
0000h
0000h
0000h
0000h
0000h
LDT Selector
GS
FS
DS
SS
CS
0000h
0000h
ES
EDI
ESI
EBP
ESP
EBX
EDX
ECX
EAX
EFLAGS
EIP
CR3
SS2
0000h
0000h
0000h
0000h
ESP2
ESP1
ESP0
SS1
SS0
Link (Prior TSS Selector)
0
Figure 41. Task State Segment (TSS)
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AMD-K6™-2E Processor Data Sheet
3.4
Paging
The AMD-K6-2E processor can physically address up to four
Gbytes of memory. This memory can be segmented into pages.
The size of these pages is determined by the operating system
design and the values set up in the page directory entries (PDE)
and page table entries (PTE).
The processor can access both 4-Kbyte pages and 4-Mbyte
pages, and the page sizes can be intermixed within a page
directory. When the page size extension (PSE) bit in CR4 is set,
the processor translates linear addresses using either the
4-Kbyte translation lookaside buffer (TLB) or the 4-Mbyte TLB,
depending on the state of the page size (PS) bit in the page
directory entry. Figures 42 and 43 show how 4-Kbyte and
4-Mbyte page translations work.
4-Kbyte
Page
Directory
Page
Table
Page
Frame
PTE
Physical
Address
PDE
CR3
31
22 21
12 11
0
Page Directory
Offset
Page Table
Offset
Page
Offset
Linear Address
Figure 42. 4-Kbyte Paging Mechanism
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4-Mbyte
Page
Frame
Page
Directory
Physical
Address
PDE
CR3
31
22 21
0
Page Directory
Offset
Page
Offset
Linear Address
Figure 43. 4-Mbyte Paging Mechanism
Figures 44 through 46 show the formats of the PDE and PTE.
These entries contain information regarding the location of
pages and their status.
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31
12 11 10
9
8
7
0
6
5
A
4
3
2
1
0
P
U
/
S
P
W
T
W
/
R
A
V
L
P
C
D
Page Table Base Address
Symbol
AVL
Description
Available to Software
Reserved
Page Size
Reserved
Bits
11–9
8
7
6
5
4
3
2
1
0
PS
A
Accessed
PCD
PWT
U/S
W/R
P
Page Cache Disable
Page Writethrough
User/Supervisor
Write/Read
Present (valid)
Figure 44. Page Directory Entry 4-Kbyte Page Table (PDE)
31
22 21
12 11 10
9
8
7
1
6
5
A
4
3
2
1
0
P
U
/
S
P
W
T
W
/
R
A
V
L
P
C
D
Physical Page Base Address
Reserved
Symbol
AVL
Description
Available to Software
Reserved
Page Size
Reserved
Bits
11–9
8
7
6
5
4
3
2
1
0
PS
A
Accessed
PCD
PWT
U/S
W/R
P
Page Cache Disable
Page Writethrough
User/Supervisor
Write/Read
Present (valid)
Figure 45. Page Directory Entry 4-Mbyte Page Table (PDE)
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31
12 11 10
A
9
8
7
6
5
A
4
3
2
1
0
P
U
/
S
P
W
T
W
/
R
P
C
D
V
L
D
Physical Page Base Address
Symbol
AVL
Description
Available to Software
Reserved
Bits
11–9
8–7
6
D
Dirty
A
Accessed
5
PCD
PWT
U/S
W/R
P
Page Cache Disable
Page Writethrough
User/Supervisor
Write/Read
4
3
2
1
Present (valid)
0
Figure 46. Page Table Entry (PTE)
3.5
Descriptors and Gates
There are various types of structures and registers in the x86
architecture that define, protect, and isolate code segments,
data segments, task state segments, and gates. These structures
are called descriptors.
■ The application segment descriptor is used to point to either a
data or code segment. Figure 47 on page 53 shows the
application segment descriptor format. Table 9 contains
information describing the memory segment type to which
the descriptor points.
■ The system segment descriptor is used to point to a task state
segment, a call gate, or a local descriptor table. Figure 48 on
page 54 shows the system segment descriptor format. Table
10 contains information describing the type of segment or
gate to which the descriptor points.
■ The AMD-K6-2E processor uses gates to transfer control
between executable segments with different privilege
levels. Figure 49 on page 55 shows the format of the gate
descriptor types. Table 10 contains information describing
the type of segment or gate to which the descriptor points.
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Symbol
G
Description
Granularity
Bits
23
D
32-Bit/16-Bit
22
AVL
P
DPL
DT
Available to Software
Present/Valid Bit
Descriptor Privilege Level
Descriptor Type
20
15
14-13
12
Reserved
Type See Table 9
11-8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
A
9
8
7
6
5
4
3
2
1
0
Base Address 31–24
G
D
Segment
Limit
P
DPL
1
Type
Base Address 23–16
V
L
Base Address 15–0
Segment Limit 15–0
Figure 47. Application Segment Descriptor
Table 9. Application Segment Types
Type Data/Code Description
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Read-Only
Read-Only—Accessed
Read/Write
Read/Write—Accessed
Read-Only—Expand-down
Data
Read-Only—Expand-down, Accessed
Read/Write—Expand-down
Read/Write—Expand-down, Accessed
Execute-Only
Execute-Only—Accessed
Execute/Read
Execute/Read—Accessed
Code
Execute-Only—Conforming
Execute-Only—Conforming, Accessed
Execute/Read-Only—Conforming
Execute/Read-Only—Conforming, Accessed
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Symbol
G
Description
Granularity
Bits
23
X
Not Needed
22
AVL
P
DPL
DT
Availability to Software
Present/Valid Bit
Descriptor Privilege Level
Descriptor Type
20
15
14-13
12
Reserved
Type See Table 10
11-8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
A
9
8
7
6
5
4
3
2
1
0
Base Address 31–24
G
X
Segment
Limit
P
DPL
0
Type
Base Address 23–16
V
L
Base Address 15–0
Segment Limit 15–0
Figure 48. System Segment Descriptor
Table 10. System Segment and Gate Types
Type Description
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Reserved
Available 16-bit TSS
LDT
Busy 16-bit TSS
16-bit Call Gate
Task Gate
16-bit Interrupt Gate
16-bit Trap Gate
Reserved
Available 32-bit TSS
Reserved
Busy 32-bit TSS
32-bit Call Gate
Reserved
32-bit Interrupt Gate
32-bit Trap Gate
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AMD-K6™-2E Processor Data Sheet
Symbol
P
Description
Present/Valid Bit
Bits
15
DPL
DT
Descriptor Privilege Level
Descriptor Type
14-13
12
Reserved
Type See Table 10
11-8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Offset 31–16
P
DPL
0
Type
Segment Selector
Offset 15–0
Figure 49. Gate Descriptor
3.6
Exceptions and Interrupts
Table 11 summarizes the exceptions and interrupts.
Table 11. Summary of Exceptions and Interrupts
Interrupt
Interrupt Type
Cause
Number
0
1
Divide by Zero Error
Debug
DIV, IDIV
Debug trap or fault
2
Non-Maskable Interrupt
Breakpoint
NMI signal sampled asserted
3
Int 3
4
Overflow
INTO
5
Bounds Check
BOUND
6
Invalid Opcode
Device Not Available
Double Fault
Invalid instruction
7
ESC and WAIT
8
Fault occurs while handling a fault
—
9
Reserved - Interrupt 13
Invalid TSS
10
11
12
13
14
16
17
0–255
Task switch to an invalid segment
Instruction loads a segment and present bit is 0 (invalid segment)
Stack operation causes limit violation or present bit is 0
Segment related or miscellaneous invalid actions
Page protection violation or a reference to missing page
Arithmetic error generated by floating-point instruction
Segment Not Present
Stack Segment
General Protection
Page Fault
Floating-Point Error
Alignment Check
Software Interrupt
Data reference to an unaligned operand. (The AC flag and the AM bit of CR0 are set to 1.)
INT n
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AMD-K6™-2E Processor Data Sheet
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3.7
Instructions Supported by the AMD-K6™-2E Processor
This section documents all of the x86 instructions supported by
the AMD-K6™-2E processor. Tables 12 through 15 define the
integer, floating-point, MMX, and 3DNow! instructions for the
AMD-K6-2E processor, respectively.
Each table shows the instruction mnemonic, opcode, modR/M
byte, decode type, and RISC86 operation(s) for each
instruction.
Instruction
Mnemonic and
Operand Types
The first column in each table indicates the instruction
mnemonic and operand types, with the following notations:
■ disp16/32—16-bit or 32-bit displacement value
■ disp32/48—doubleword or 48-bit displacement value
■ disp8—8-bit displacement value
■ eXX—register width depending on the operand size
■ imm16/32—16-bit or 32-bit immediate value
■ imm8—8-bit immediate value
■ mem16/32—word or doubleword integer value in memory
■ mem32/48—doubleword or 48-bit integer value in memory
■ mem32real—32-bit floating-point value in memory
■ mem48—48-bit integer value in memory
■ mem64—64-bit value in memory
■ mem64real—64-bit floating-point value in memory
■ mem8—byte integer value in memory
■ mem80real—80-bit floating-point value in memory
■ mmreg—MMX/3DNow! register
■ mmreg1—MMX/3DNow! register defined by bits 5, 4, and 3
of the modR/M byte
■ mmreg2—MMX/3DNow! register defined by bits 2, 1, and 0
of the modR/M byte
■ mreg16/32—word or doubleword integer register, or word or
doubleword integer value in memory defined by the
modR/M byte
■ mreg8—byte integer register or byte integer value in
memory defined by the modR/M byte
■ reg8—byte integer register defined by instruction byte(s) or
bits 5, 4, and 3 of the modR/M byte
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■ reg16/32—word or doubleword integer register defined by
instruction byte(s) or bits 5, 4, and 3 of the modR/M byte
Opcode Bytes
ModR/M Byte
The second and third columns list all applicable opcode bytes.
The fourth column lists the modR/M byte when used by the
instruction. The modR/M byte defines the instruction as a
register or memory form. If modR/M bits 7 and 6 are documented
as mm (memory form), mm can only be 10b, 01b or 00b.
Decode Type
The fifth column lists the type of instruction decode—short,
long, and vector. The AMD-K6-2E processor decode logic can
process two short, one long, or one vector decode per clock.
RISC86 Operation
The sixth column lists the type of RISC86 operation(s) required
for the instruction. The operation types and corresponding
execution units are as follows:
■ alu—either of the integer execution units
■ alux—integer X execution unit only
■ branch—branch condition unit
■ float—floating-point execution unit
■ limm—load immediate, instruction control unit
■ load, fload, mload—load unit
■ meu—Multimedia execution units for MMX and 3DNow!
instructions
■ store, fstore, mstore—store unit
Table 12. Integer Instructions
Instruction Mnemonic
First
Byte
Second
Byte
ModR/M
Byte
Decode RISC86
Type Operations
AAA
37h
D5h
D4h
3Fh
10h
10h
11h
11h
12h
12h
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
AAD
0Ah
0Ah
AAM
AAS
ADC mreg8, reg8
ADC mem8, reg8
ADC mreg16/32, reg16/32
ADC mem16/32, reg16/32
ADC reg8, mreg8
ADC reg8, mem8
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
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Table 12. Integer Instructions (continued)
First
Second
Byte
ModR/M
Byte
Decode RISC86
Type Operations
Instruction Mnemonic
Byte
13h
13h
14h
15h
80h
80h
81h
81h
83h
83h
00h
00h
01h
01h
02h
02h
03h
03h
04h
05h
80h
80h
81h
81h
83h
83h
20h
20h
21h
21h
22h
22h
23h
23h
24h
ADC reg16/32, mreg16/32
ADC reg16/32, mem16/32
ADC AL, imm8
11-xxx-xxx
vector
mm-xxx-xxx
vector
vector
ADC EAX, imm16/32
vector
ADC mreg8, imm8
11-010-xxx
mm-010-xxx
11-010-xxx
mm-010-xxx
11-010-xxx
mm-010-xxx
11-xxx-xxx
vector
ADC mem8, imm8
vector
ADC mreg16/32, imm16/32
ADC mem16/32, imm16/32
ADC mreg16/32, imm8 (signed ext.)
ADC mem16/32, imm8 (signed ext.)
ADD mreg8, reg8
vector
vector
vector
vector
short
long
alux
ADD mem8, reg8
mm-xxx-xxx
11-xxx-xxx
load, alux, store
alu
ADD mreg16/32, reg16/32
ADD mem16/32, reg16/32
ADD reg8, mreg8
short
long
mm-xxx-xxx
11-xxx-xxx
load, alu, store
alux
short
short
short
short
short
short
short
long
ADD reg8, mem8
mm-xxx-xxx
11-xxx-xxx
load, alux
alu
ADD reg16/32, mreg16/32
ADD reg16/32, mem16/32
ADD AL, imm8
mm-xxx-xxx
load, alu
alux
ADD EAX, imm16/32
alu
ADD mreg8, imm8
11-000-xxx
mm-000-xxx
11-000-xxx
mm-000-xxx
11-000-xxx
mm-000-xxx
11-xxx-xxx
alux
ADD mem8, imm8
load, alux, store
alu
ADD mreg16/32, imm16/32
ADD mem16/32, imm16/32
ADD mreg16/32, imm8 (signed ext.)
ADD mem16/32, imm8 (signed ext.)
AND mreg8, reg8
short
long
load, alu, store
alux
short
long
load, alux, store
alux
short
long
AND mem8, reg8
mm-xxx-xxx
11-xxx-xxx
load, alux, store
alu
AND mreg16/32, reg16/32
AND mem16/32, reg16/32
AND reg8, mreg8
short
long
mm-xxx-xxx
11-xxx-xxx
load, alu, store
alux
short
short
short
short
short
AND reg8, mem8
mm-xxx-xxx
11-xxx-xxx
load, alux
alu
AND reg16/32, mreg16/32
AND reg16/32, mem16/32
AND AL, imm8
mm-xxx-xxx
load, alu
alux
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Table 12. Integer Instructions (continued)
First
Second
Byte
ModR/M
Byte
Decode RISC86
Type Operations
Instruction Mnemonic
Byte
25h
80h
80h
81h
81h
83h
83h
63h
63h
62h
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
AND EAX, imm16/32
AND mreg8, imm8
short
short
long
alu
11-100-xxx
mm-100-xxx
11-100-xxx
mm-100-xxx
11-100-xxx
mm-100-xxx
11-xxx-xxx
alux
AND mem8, imm8
load, alux, store
alu
AND mreg16/32, imm16/32
AND mem16/32, imm16/32
AND mreg16/32, imm8 (signed ext.)
AND mem16/32, imm8 (signed ext.)
ARPL mreg16, reg16
ARPL mem16, reg16
BOUND
short
long
load, alu, store
alux
short
long
load, alux, store
vector
vector
vector
vector
vector
vector
vector
long
mm-xxx-xxx
BSF reg16/32, mreg16/32
BSF reg16/32, mem16/32
BSR reg16/32, mreg16/32
BSR reg16/32, mem16/32
BSWAP EAX
BCh
BCh
BDh
BDh
C8h
C9h
CAh
CBh
CCh
CDh
CEh
CFh
A3h
A3h
BAh
BAh
BBh
BBh
BAh
BAh
B3h
B3h
BAh
BAh
ABh
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
alu
alu
alu
alu
alu
alu
alu
alu
BSWAP ECX
long
BSWAP EDX
long
BSWAP EBX
long
BSWAP ESP
long
BSWAP EBP
long
BSWAP ESI
long
BSWAP EDI
long
BT mreg16/32, reg16/32
BT mem16/32, reg16/32
BT mreg16/32, imm8
BT mem16/32, imm8
BTC mreg16/32, reg16/32
BTC mem16/32, reg16/32
BTC mreg16/32, imm8
BTC mem16/32, imm8
BTR mreg16/32, reg16/32
BTR mem16/32, reg16/32
BTR mreg16/32, imm8
BTR mem16/32, imm8
BTS mreg16/32, reg16/32
11-xxx-xxx
mm-xxx-xxx
11-100-xxx
mm-100-xxx
11-xxx-xxx
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
mm-xxx-xxx
11-111-xxx
mm-111-xxx
11-xxx-xxx
mm-xxx-xxx
11-110-xxx
mm-110-xxx
11-xxx-xxx
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Table 12. Integer Instructions (continued)
First
Second
Byte
ModR/M
Byte
Decode RISC86
Type Operations
Instruction Mnemonic
Byte
0Fh
0Fh
0Fh
9Ah
E8h
FFh
FFh
FFh
98h
F8h
FCh
FAh
0Fh
F5h
38h
38h
39h
39h
3Ah
3Ah
3Bh
3Bh
3Ch
3Dh
80h
80h
81h
81h
83h
83h
A6h
A7h
A7h
0Fh
0Fh
BTS mem16/32, reg16/32
BTS mreg16/32, imm8
BTS mem16/32, imm8
CALL full pointer
ABh
BAh
BAh
mm-xxx-xxx
11-101-xxx
vector
vector
vector
vector
mm-101-xxx
CALL near imm16/32
CALL mem16:16/32
CALL near mreg32 (indirect)
CALL near mem32 (indirect)
CBW/CWDE EAX
short
vector
vector
vector
vector
vector
vector
vector
vector
vector
short
short
short
short
short
short
short
short
short
short
short
short
short
short
long
store
11-011-xxx
11-010-xxx
mm-010-xxx
CLC
CLD
CLI
CLTS
06h
CMC
CMP mreg8, reg8
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
alux
CMP mem8, reg8
load, alux
alu
CMP mreg16/32, reg16/32
CMP mem16/32, reg16/32
CMP reg8, mreg8
load, alu
alux
CMP reg8, mem8
load, alux
alu
CMP reg16/32, mreg16/32
CMP reg16/32, mem16/32
CMP AL, imm8
load, alu
alux
CMP EAX, imm16/32
CMP mreg8, imm8
CMP mem8, imm8
CMP mreg16/32, imm16/32
CMP mem16/32, imm16/32
CMP mreg16/32, imm8 (signed ext.)
CMP mem16/32, imm8 (signed ext.)
CMPSB mem8, mem8
CMPSW mem16, mem32
CMPSD mem32, mem32
CMPXCHG mreg8, reg8
CMPXCHG mem8, reg8
alu
11-111-xxx
mm-111-xxx
11-111-xxx
mm-111-xxx
11-111-xxx
mm-111-xxx
alux
load, alux
alu
load, alu
load, alu
load, alu
long
vector
vector
vector
vector
vector
B0h
B0h
11-xxx-xxx
mm-xxx-xxx
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Table 12. Integer Instructions (continued)
First
Second
Byte
ModR/M
Byte
Decode RISC86
Type Operations
Instruction Mnemonic
Byte
0Fh
0Fh
0Fh
0Fh
0Fh
99h
27h
2Fh
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
FEh
FEh
FFh
FFh
F6h
F6h
F7h
F7h
F6h
F6h
F7h
F7h
69h
69h
69h
6Bh
6Bh
6Bh
F6h
CMPXCHG mreg16/32, reg16/32
CMPXCHG mem16/32, reg16/32
CMPXCHG8B EDX:EAX
CMPXCHG8B mem64
CPUID
B1h
B1h
C7h
C7h
A2h
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
vector
vector
vector
vector
vector
vector
vector
vector
mm-xxx-xxx
CWD/CDQ EDX, EAX
DAA
DAS
DEC EAX
short
short
alu
alu
alu
alu
alu
alu
alu
alu
DEC ECX
DEC EDX
short
DEC EBX
short
DEC ESP
short
DEC EBP
short
DEC ESI
short
DEC EDI
short
DEC mreg8
11-001-xxx
mm-001-xxx
11-001-xxx
mm-001-xxx
11-110-xxx
mm-110-xxx
11-110-xxx
mm-110-xxx
11-111-xxx
mm-111-xxx
11-111-xxx
mm-111-xxx
11-xxx-xxx
vector
long
DEC mem8
load, alux, store
load, alu, store
DEC mreg16/32
vector
long
DEC mem16/32
DIV AL, mreg8
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
DIV AL, mem8
DIV EAX, mreg16/32
DIV EAX, mem16/32
IDIV mreg8
IDIV mem8
IDIV EAX, mreg16/32
IDIV EAX, mem16/32
IMUL reg16/32, imm16/32
IMUL reg16/32, mreg16/32, imm16/32
IMUL reg16/32, mem16/32, imm16/32
IMUL reg16/32, imm8 (sign extended)
IMUL reg16/32, mreg16/32, imm8 (signed)
IMUL reg16/32, mem16/32, imm8 (signed)
IMUL AX, AL, mreg8
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-101-xxx
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Table 12. Integer Instructions (continued)
First
Second
Byte
ModR/M
Byte
Decode RISC86
Type Operations
Instruction Mnemonic
Byte
F6h
F7h
F7h
0Fh
0Fh
E4h
E5h
E5h
ECh
EDh
EDh
40h
41h
42h
43h
44h
45h
46h
47h
FEh
FEh
FFh
FFh
0Fh
0Fh
70h
71h
71h
73h
74h
75h
76h
77h
78h
79h
IMUL AX, AL, mem8
IMUL EDX:EAX, EAX, mreg16/32
IMUL EDX:EAX, EAX, mem16/32
IMUL reg16/32, mreg16/32
IMUL reg16/32, mem16/32
IN AL, imm8
mm-101-xxx
11-101-xxx
mm-101-xxx
11-xxx-xxx
vector
vector
vector
AFh
AFh
vector
mm-xxx-xxx
vector
vector
IN AX, imm8
vector
IN EAX, imm8
IN AL, DX
vector
vector
IN AX, DX
vector
IN EAX, DX
vector
INC EAX
short
short
short
short
short
short
short
short
vector
long
alu
alu
alu
alu
alu
alu
alu
alu
INC ECX
INC EDX
INC EBX
INC ESP
INC EBP
INC ESI
INC EDI
INC mreg8
11-000-xxx
mm-000-xxx
11-000-xxx
mm-000-xxx
INC mem8
load, alux, store
load, alu, store
INC mreg16/32
INC mem16/32
INVD
vector
long
08h
01h
vector
vector
short
short
short
short
short
short
short
short
short
short
INVLPG
mm-111-xxx
JO short disp8
JB/JNAE short disp8
JNO short disp8
JNB/JAE short disp8
JZ/JE short disp8
JNZ/JNE short disp8
JBE/JNA short disp8
JNBE/JA short disp8
JS short disp8
JNS short disp8
branch
branch
branch
branch
branch
branch
branch
branch
branch
branch
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Table 12. Integer Instructions (continued)
First
Second
Byte
ModR/M
Byte
Decode RISC86
Type Operations
Instruction Mnemonic
Byte
7Ah
7Bh
7Ch
7Dh
7Eh
7Fh
E3h
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
E9h
EAh
EBh
EFh
EFh
FFh
FFh
9Fh
0Fh
0Fh
C5h
8Dh
JP/JPE short disp8
short
short
short
short
short
short
vector
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
vector
short
vector
vector
vector
vector
vector
vector
vector
vector
short
branch
branch
branch
branch
branch
branch
JNP/JPO short disp8
JL/JNGE short disp8
JNL/JGE short disp8
JLE/JNG short disp8
JNLE/JG short disp8
JCXZ/JEC short disp8
JO near disp16/32
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
branch
branch
branch
branch
branch
branch
branch
branch
branch
branch
branch
branch
branch
branch
branch
branch
branch
JNO near disp16/32
JB/JNAE near disp16/32
JNB/JAE near disp16/32
JZ/JE near disp16/32
JNZ/JNE near disp16/32
JBE/JNA near disp16/32
JNBE/JA near disp16/32
JS near disp16/32
JNS near disp16/32
JP/JPE near disp16/32
JNP/JPO near disp16/32
JL/JNGE near disp16/32
JNL/JGE near disp16/32
JLE/JNG near disp16/32
JNLE/JG near disp16/32
JMP near disp16/32 (direct)
JMP far disp32/48 (direct)
JMP disp8 (short)
branch
JMP far mreg32 (indirect)
JMP far mem32 (indirect)
JMP near mreg16/32 (indirect)
JMP near mem16/32 (indirect)
LAHF
11-101-xxx
mm-101-xxx
11-100-xxx
mm-100-xxx
LAR reg16/32, mreg16/32
LAR reg16/32, mem16/32
LDS reg16/32, mem32/48
LEA reg16/32, mem16/32
02h
02h
11-xxx-xxx
mm-xxx-xxx
mm-xxx-xxx
mm-xxx-xxx
load, alu
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Table 12. Integer Instructions (continued)
First
Second
Byte
ModR/M
Byte
Decode RISC86
Type Operations
Instruction Mnemonic
Byte
C9h
C4h
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
ACh
ADh
ADh
E2h
E1h
E0h
0Fh
0Fh
0Fh
0Fh
0Fh
88h
88h
89h
89h
8Ah
8Ah
8Bh
8Bh
8Ch
8Ch
8Eh
8Eh
A0h
A1h
LEAVE
long
vector
vector
vector
vector
vector
vector
vector
vector
vector
long
load, alu, alu
LES reg16/32, mem32/48
LFS reg16/32, mem32/48
LGDT mem48
mm-xxx-xxx
mm-010-xxx
B4h
01h
B5h
01h
00h
00h
01h
01h
LGS reg16/32, mem32/48
LIDT mem48
mm-011-xxx
11-010-xxx
LLDT mreg16
LLDT mem16
mm-010-xxx
11-100-xxx
mm-100-xxx
LMSW mreg16
LMSW mem16
LODSB AL, mem8
load, alu
load, alu
load, alu
alu, branch
LODSW AX, mem16
LODSD EAX, mem32
LOOP disp8
long
long
short
vector
vector
vector
vector
vector
vector
vector
short
short
short
short
short
short
short
short
long
LOOPE/LOOPZ disp8
LOOPNE/LOOPNZ disp8
LSL reg16/32, mreg16/32
LSL reg16/32, mem16/32
LSS reg16/32, mem32/48
LTR mreg16
03h
03h
B2h
00h
00h
11-xxx-xxx
mm-xxx-xxx
mm-xxx-xxx
11-011-xxx
mm-011-xxx
11-xxx-xxx
LTR mem16
MOV mreg8, reg8
alux
store
alu
MOV mem8, reg8
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
MOV mreg16/32, reg16/32
MOV mem16/32, reg16/32
MOV reg8, mreg8
store
alux
load
alu
MOV reg8, mem8
MOV reg16/32, mreg16/32
MOV reg16/32, mem16/32
MOV mreg16, segment reg
MOV mem16, segment reg
MOV segment reg, mreg16
MOV segment reg, mem16
MOV AL, mem8
load
load
mm-xxx-xxx
11-xxx-xxx
vector
vector
vector
short
short
mm-xxx-xxx
load
load
MOV EAX, mem16/32
64
Software Environment
Chapter 3
Preliminary Information
22529B/0—January 2000
AMD-K6™-2E Processor Data Sheet
Table 12. Integer Instructions (continued)
First
Second
Byte
ModR/M
Byte
Decode RISC86
Type Operations
Instruction Mnemonic
Byte
A2h
A3h
B0h
B1h
B2h
B3h
B4h
B5h
B6h
B7h
B8h
B9h
BAh
BBh
BCh
BDh
BEh
BFh
C6h
C6h
C7h
C7h
A4h
A5h
A5h
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
F6h
F6h
MOV mem8, AL
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
long
store
MOV mem16/32, EAX
MOV AL, imm8
store
limm
MOV CL, imm8
limm
MOV DL, imm8
limm
MOV BL, imm8
limm
MOV AH, imm8
limm
MOV CH, imm8
limm
MOV DH, imm8
limm
MOV BH, imm8
limm
MOV EAX, imm16/32
MOV ECX, imm16/32
MOV EDX, imm16/32
MOV EBX, imm16/32
MOV ESP, imm16/32
MOV EBP, imm16/32
MOV ESI, imm16/32
MOV EDI, imm16/32
MOV mreg8, imm8
MOV mem8, imm8
MOV mreg16/32, imm16/32
MOV mem16/32, imm16/32
MOVSB mem8,mem8
MOVSD mem16, mem16
MOVSW mem32, mem32
MOVSX reg16/32, mreg8
MOVSX reg16/32, mem8
MOVSX reg32, mreg16
MOVSX reg32, mem16
MOVZX reg16/32, mreg8
MOVZX reg16/32, mem8
MOVZX reg32, mreg16
MOVZX reg32, mem16
MUL AL, mreg8
limm
limm
limm
limm
limm
limm
limm
limm
11-000-xxx
mm-000-xxx
11-000-xxx
mm-000-xxx
limm
store
short
long
limm
store
long
load, store, alux, alux
long
load, store, alu, alu
long
load, store, alu, alu
BEh
BEh
BFh
BFh
B6h
B6h
B7h
B7h
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
short
short
short
short
short
short
short
short
vector
vector
alu
load, alu
alu
mm-xxx-xxx
11-xxx-xxx
load, alu
alu
mm-xxx-xxx
11-xxx-xxx
load, alu
alu
mm-xxx-xxx
11-100-xxx
mm-100-xxx
load, alu
MUL AL, mem8
Chapter 3
Software Environment
65
Preliminary Information
AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
Table 12. Integer Instructions (continued)
First
Second
Byte
ModR/M
Byte
Decode RISC86
Type Operations
Instruction Mnemonic
Byte
F7h
F7h
F6h
F6h
F7h
F7h
90h
F6h
F6h
F7h
F7h
08h
08h
09h
09h
0Ah
0Ah
0Bh
0Bh
0Ch
0Dh
80h
80h
81h
81h
83h
83h
E6h
E7h
E7h
EEh
EFh
EFh
07h
17h
MUL EAX, mreg16/32
MUL EAX, mem16/32
NEG mreg8
11-100-xxx
mm-100-xxx
11-011-xxx
mm-011-xxx
11-011-xxx
vector
vector
short
vector
short
vector
short
short
vector
short
vector
short
long
alux
alu
NEG mem8
NEG mreg16/32
NEG mem16/32
mm-011-xxx
NOP (XCHG EAX, EAX)
NOT mreg8
limm
alux
11-010-xxx
mm-010-xxx
11-010-xxx
mm-010-xxx
11-xxx-xxx
NOT mem8
NOT mreg16/32
alu
NOT mem16/32
OR mreg8, reg8
alux
OR mem8, reg8
mm-xxx-xxx
11-xxx-xxx
load, alux, store
OR mreg16/32, reg16/32
OR mem16/32, reg16/32
OR reg8, mreg8
short
long
alu
mm-xxx-xxx
11-xxx-xxx
load, alu, store
alux
short
short
short
short
short
short
short
long
OR reg8, mem8
mm-xxx-xxx
11-xxx-xxx
load, alux
alu
OR reg16/32, mreg16/32
OR reg16/32, mem16/32
OR AL, imm8
mm-xxx-xxx
load, alu
alux
OR EAX, imm16/32
OR mreg8, imm8
OR mem8, imm8
OR mreg16/32, imm16/32
OR mem16/32, imm16/32
OR mreg16/32, imm8 (signed ext.)
OR mem16/32, imm8 (signed ext.)
OUT imm8, AL
alu
11-001-xxx
mm-001-xxx
11-001-xxx
mm-001-xxx
11-001-xxx
mm-001-xxx
alux
load, alux, store
alu
short
long
load, alu, store
alux
short
long
load, alux, store
vector
vector
vector
vector
vector
vector
vector
vector
OUT imm8, AX
OUT imm8, EAX
OUT DX, AL
OUT DX, AX
OUT DX, EAX
POP ES
POP SS
66
Software Environment
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AMD-K6™-2E Processor Data Sheet
Table 12. Integer Instructions (continued)
First
Second
Byte
ModR/M
Byte
Decode RISC86
Type Operations
Instruction Mnemonic
Byte
1Fh
0Fh
0Fh
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
8Fh
8Fh
61h
9Dh
06h
0Eh
0Fh
0Fh
16h
1Eh
50h
51h
52h
53h
54h
55h
56h
57h
6Ah
68h
FFh
FFh
60h
9Ch
POP DS
vector
vector
vector
POP FS
A1h
A9h
POP GS
POP EAX
short
short
short
short
short
short
short
short
short
long
load, alu
load, alu
load, alu
load, alu
load, alu
load, alu
load, alu
load, alu
load, alu
load, store, alu
POP ECX
POP EDX
POP EBX
POP ESP
POP EBP
POP ESI
POP EDI
POP mreg 16/32
POP mem 16/32
POPA/POPAD
POPF/POPFD
PUSH ES
11-000-xxx
mm-000-xxx
vector
vector
long
load, store
PUSH CS
vector
vector
vector
vector
long
PUSH FS
A0h
A8h
PUSH GS
PUSH SS
PUSH DS
load, store
store
PUSH EAX
PUSH ECX
PUSH EDX
PUSH EBX
PUSH ESP
PUSH EBP
PUSH ESI
short
short
short
short
short
short
short
short
long
store
store
store
store
store
store
PUSH EDI
store
PUSH imm8
PUSH imm16/32
PUSH mreg16/32
PUSH mem16/32
PUSHA/PUSHAD
PUSHF/PUSHFD
store
long
store
11-110-xxx
vector
long
mm-110-xxx
load, store
vector
vector
Chapter 3
Software Environment
67
Preliminary Information
AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
Table 12. Integer Instructions (continued)
First
Second
Byte
ModR/M
Byte
Decode RISC86
Instruction Mnemonic
Byte
C0h
C0h
C1h
C1h
D0h
D0h
D1h
D1h
D2h
D2h
D3h
D3h
C0h
C0h
C1h
C1h
D0h
D0h
D1h
D1h
D2h
D2h
D3h
D3h
C2h
C3h
CAh
CBh
C0h
C0h
C1h
C1h
D0h
D0h
D1h
Type Operations
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
RCL mreg8, imm8
RCL mem8, imm8
RCL mreg16/32, imm8
RCL mem16/32, imm8
RCL mreg8, 1
11-010-xxx
mm-010-xxx
11-010-xxx
mm-010-xxx
11-010-xxx
mm-010-xxx
11-010-xxx
mm-010-xxx
11-010-xxx
mm-010-xxx
11-010-xxx
mm-010-xxx
11-011-xxx
mm-011-xxx
11-011-xxx
mm-011-xxx
11-011-xxx
mm-011-xxx
11-011-xxx
mm-011-xxx
11-011-xxx
mm-011-xxx
11-011-xxx
mm-011-xxx
RCL mem8, 1
RCL mreg16/32, 1
RCL mem16/32, 1
RCL mreg8, CL
RCL mem8, CL
RCL mreg16/32, CL
RCL mem16/32, CL
RCR mreg8, imm8
RCR mem8, imm8
RCR mreg16/32, imm8
RCR mem16/32, imm8
RCR mreg8, 1
RCR mem8, 1
RCR mreg16/32, 1
RCR mem16/32, 1
RCR mreg8, CL
RCR mem8, CL
RCR mreg16/32, CL
RCR mem16/32, CL
RET near imm16
RET near
RET far imm16
RET far
ROL mreg8, imm8
ROL mem8, imm8
ROL mreg16/32, imm8
ROL mem16/32, imm8
ROL mreg8, 1
11-000-xxx
mm-000-xxx
11-000-xxx
mm-000-xxx
11-000-xxx
mm-000-xxx
11-000-xxx
ROL mem8, 1
ROL mreg16/32, 1
68
Software Environment
Chapter 3
Preliminary Information
22529B/0—January 2000
AMD-K6™-2E Processor Data Sheet
Table 12. Integer Instructions (continued)
First
Second
Byte
ModR/M
Byte
Decode RISC86
Type Operations
Instruction Mnemonic
Byte
D1h
D2h
D2h
D3h
D3h
C0h
C0h
C1h
C1h
D0h
D0h
D1h
D1h
D2h
D2h
D3h
D3h
9Eh
C0h
C0h
C1h
C1h
D0h
D0h
D1h
D1h
D2h
D2h
D3h
D3h
18h
ROL mem16/32, 1
ROL mreg8, CL
mm-000-xxx
11-000-xxx
mm-000-xxx
11-000-xxx
mm-000-xxx
11-001-xxx
mm-001-xxx
11-001-xxx
mm-001-xxx
11-001-xxx
mm-001-xxx
11-001-xxx
mm-001-xxx
11-001-xxx
mm-001-xxx
11-001-xxx
mm-001-xxx
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
ROL mem8, CL
ROL mreg16/32, CL
ROL mem16/32, CL
ROR mreg8, imm8
ROR mem8, imm8
ROR mreg16/32, imm8
ROR mem16/32, imm8
ROR mreg8, 1
ROR mem8, 1
ROR mreg16/32, 1
ROR mem16/32, 1
ROR mreg8, CL
ROR mem8, CL
ROR mreg16/32, CL
ROR mem16/32, CL
SAHF
SAR mreg8, imm8
SAR mem8, imm8
SAR mreg16/32, imm8
SAR mem16/32, imm8
SAR mreg8, 1
11-111-xxx
mm-111-xxx
11-111-xxx
mm-111-xxx
11-111-xxx
mm-111-xxx
11-111-xxx
mm-111-xxx
11-111-xxx
mm-111-xxx
11-111-xxx
mm-111-xxx
11-xxx-xxx
short
vector
short
alux
alu
vector
short
alux
alu
SAR mem8, 1
vector
short
SAR mreg16/32, 1
SAR mem16/32, 1
SAR mreg8, CL
vector
short
alux
alu
SAR mem8, CL
vector
short
SAR mreg16/32, CL
SAR mem16/32, CL
SBB mreg8, reg8
SBB mem8, reg8
SBB mreg16/32, reg16/32
SBB mem16/32, reg16/32
SBB reg8, mreg8
vector
vector
vector
vector
vector
vector
18h
mm-xxx-xxx
11-xxx-xxx
19h
19h
mm-xxx-xxx
11-xxx-xxx
1Ah
Chapter 3
Software Environment
69
Preliminary Information
AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
Table 12. Integer Instructions (continued)
First
Second
Byte
ModR/M
Byte
Decode RISC86
Instruction Mnemonic
Byte
1Ah
1Bh
1Bh
1Ch
1Dh
80h
80h
81h
81h
83h
83h
AEh
AFh
AFh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
Type Operations
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
SBB reg8, mem8
mm-xxx-xxx
11-xxx-xxx
SBB reg16/32, mreg16/32
SBB reg16/32, mem16/32
SBB AL, imm8
mm-xxx-xxx
SBB EAX, imm16/32
SBB mreg8, imm8
SBB mem8, imm8
SBB mreg16/32, imm16/32
SBB mem16/32, imm16/32
SBB mreg16/32, imm8 (signed ext.)
SBB mem16/32, imm8 (signed ext.)
SCASB AL, mem8
11-011-xxx
mm-011-xxx
11-011-xxx
mm-011-xxx
11-011-xxx
mm-011-xxx
SCASW AX, mem16
SCASD EAX, mem32
SETO mreg8
90h
90h
91h
91h
92h
92h
93h
93h
94h
94h
95h
95h
96h
96h
97h
97h
98h
98h
99h
99h
9Ah
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
SETO mem8
SETNO mreg8
SETNO mem8
SETB/SETNAE mreg8
SETB/SETNAE mem8
SETNB/SETAE mreg8
SETNB/SETAE mem8
SETZ/SETE mreg8
SETZ/SETE mem8
SETNZ/SETNE mreg8
SETNZ/SETNE mem8
SETBE/SETNA mreg8
SETBE/SETNA mem8
SETNBE/SETA mreg8
SETNBE/SETA mem8
SETS mreg8
SETS mem8
SETNS mreg8
SETNS mem8
SETP/SETPE mreg8
70
Software Environment
Chapter 3
Preliminary Information
22529B/0—January 2000
AMD-K6™-2E Processor Data Sheet
Table 12. Integer Instructions (continued)
First
Second
Byte
ModR/M
Byte
Decode RISC86
Type Operations
Instruction Mnemonic
Byte
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
C0h
C0h
C1h
C1h
D0h
D0h
D1h
D1h
D2h
D2h
D3h
D3h
C0h
C0h
C1h
C1h
D0h
D0h
D1h
D1h
D2h
D2h
SETP/SETPE mem8
SETNP/SETPO mreg8
SETNP/SETPO mem8
SETL/SETNGE mreg8
SETL/SETNGE mem8
SETNL/SETGE mreg8
SETNL/SETGE mem8
SETLE/SETNG mreg8
SETLE/SETNG mem8
SETNLE/SETG mreg8
SETNLE/SETG mem8
SGDT mem48
9Ah
9Bh
9Bh
9Ch
9Ch
9Dh
9Dh
9Eh
9Eh
9Fh
9Fh
01h
01h
mm-xxx-xxx
11-xxx-xxx
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
mm-000-xxx
mm-001-xxx
11-100-xxx
mm-100-xxx
11-100-xxx
mm-100-xxx
11-100-xxx
mm-100-xxx
11-100-xxx
mm-100-xxx
11-100-xxx
mm-100-xxx
11-100-xxx
mm-100-xxx
11-101-xxx
mm-101-xxx
11-101-xxx
mm-101-xxx
11-101-xxx
mm-101-xxx
11-101-xxx
mm-101-xxx
11-101-xxx
mm-101-xxx
SIDT mem48
SHL/SAL mreg8, imm8
SHL/SAL mem8, imm8
SHL/SAL mreg16/32, imm8
SHL/SAL mem16/32, imm8
SHL/SAL mreg8, 1
SHL/SAL mem8, 1
short
vector
short
alux
alu
vector
short
alux
alu
vector
short
SHL/SAL mreg16/32, 1
SHL/SAL mem16/32, 1
SHL/SAL mreg8, CL
SHL/SAL mem8, CL
SHL/SAL mreg16/32, CL
SHL/SAL mem16/32, CL
SHR mreg8, imm8
SHR mem8, imm8
SHR mreg16/32, imm8
SHR mem16/32, imm8
SHR mreg8, 1
vector
short
alux
alu
vector
short
vector
short
alux
alu
vector
short
vector
short
alux
alu
SHR mem8, 1
vector
short
SHR mreg16/32, 1
SHR mem16/32, 1
vector
short
SHR mreg8, CL
alux
SHR mem8, CL
vector
Chapter 3
Software Environment
71
Preliminary Information
AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
Table 12. Integer Instructions (continued)
First
Second
Byte
ModR/M
Byte
Decode RISC86
Type Operations
Instruction Mnemonic
Byte
D3h
D3h
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
F9h
FDh
FBh
AAh
ABh
ABh
0Fh
0Fh
28h
28h
29h
29h
2Ah
2Ah
2Bh
2Bh
2Ch
2Dh
80h
80h
81h
SHR mreg16/32, CL
SHR mem16/32, CL
SHLD mreg16/32, reg16/32, imm8
SHLD mem16/32, reg16/32, imm8
SHLD mreg16/32, reg16/32, CL
SHLD mem16/32, reg16/32, CL
SHRD mreg16/32, reg16/32, imm8
SHRD mem16/32, reg16/32, imm8
SHRD mreg16/32, reg16/32, CL
SHRD mem16/32, reg16/32, CL
SLDT mreg16
11-101-xxx
mm-101-xxx
11-xxx-xxx
short
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
long
alu
A4h
A4h
A5h
A5h
ACh
ACh
ADh
ADh
00h
00h
01h
01h
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-000-xxx
mm-000-xxx
11-100-xxx
mm-100-xxx
SLDT mem16
SMSW mreg16
SMSW mem16
STC
STD
STI
STOSB mem8, AL
store, alux
store, alux
store, alux
STOSW mem16, AX
STOSD mem32, EAX
STR mreg16
long
long
00h
00h
11-001-xxx
mm-001-xxx
11-xxx-xxx
vector
vector
short
long
STR mem16
SUB mreg8, reg8
alux
SUB mem8, reg8
mm-xxx-xxx
11-xxx-xxx
load, alux, store
SUB mreg16/32, reg16/32
SUB mem16/32, reg16/32
SUB reg8, mreg8
short
long
alu
mm-xxx-xxx
11-xxx-xxx
load, alu, store
short
short
short
short
short
short
short
long
alux
SUB reg8, mem8
mm-xxx-xxx
11-xxx-xxx
load, alux
SUB reg16/32, mreg16/32
SUB reg16/32, mem16/32
SUB AL, imm8
alu
mm-xxx-xxx
load, alu
alux
SUB EAX, imm16/32
SUB mreg8, imm8
alu
11-101-xxx
mm-101-xxx
11-101-xxx
alux
SUB mem8, imm8
load, alux, store
alu
SUB mreg16/32, imm16/32
short
72
Software Environment
Chapter 3
Preliminary Information
22529B/0—January 2000
AMD-K6™-2E Processor Data Sheet
Table 12. Integer Instructions (continued)
First
Second
Byte
ModR/M
Byte
Decode RISC86
Type Operations
Instruction Mnemonic
Byte
81h
83h
83h
0Fh
0Fh
84h
84h
85h
85h
A8h
A9h
F6h
F6h
F7h
F7h
0Fh
0Fh
0Fh
0Fh
9Bh
0Fh
0Fh
0Fh
0Fh
0Fh
86h
86h
87h
87h
90h
91h
92h
93h
94h
95h
SUB mem16/32, imm16/32
SUB mreg16/32, imm8 (signed ext.)
SUB mem16/32, imm8 (signed ext.)
SYSCALL
mm-101-xxx
11-101-xxx
long
short
long
load, alu, store
alux
mm-101-xxx
load, alux, store
05h
07h
vector
vector
short
vector
short
vector
long
SYSRET
TEST mreg8, reg8
TEST mem8, reg8
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
alux
alu
TEST mreg16/32, reg16/32
TEST mem16/32, reg16/32
TEST AL, imm8
mm-xxx-xxx
alux
TEST EAX, imm16/32
TEST mreg8, imm8
TEST mem8, imm8
TEST mreg16/32, imm16/32
TEST mem16/32, imm16/32
VERR mreg16
long
alu
11-000-xxx
mm-000-xxx
11-000-xxx
mm-000-xxx
11-100-xxx
mm-100-xxx
11-101-xxx
long
alux
long
load, alux
alu
long
long
load, alu
00h
00h
00h
00h
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
vector
short
long
VERR mem16
VERW mreg16
VERW mem16
mm-101-xxx
WAIT
WBINVD
09h
C0h
C0h
C1h
C1h
XADD mreg8, reg8
XADD mem8, reg8
XADD mreg16/32, reg16/32
XADD mem16/32, reg16/32
XCHG reg8, mreg8
XCHG reg8, mem8
XCHG reg16/32, mreg16/32
XCHG reg16/32, mem16/32
XCHG EAX, EAX
11-100-xxx
mm-100-xxx
11-101-xxx
mm-101-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
limm
XCHG EAX, ECX
alu, alu, alu
alu, alu, alu
alu, alu, alu
alu, alu, alu
alu, alu, alu
XCHG EAX, EDX
long
XCHG EAX, EBX
long
XCHG EAX, ESP
long
XCHG EAX, EBP
long
Chapter 3
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Table 12. Integer Instructions (continued)
First
Second
Byte
ModR/M
Byte
Decode RISC86
Type Operations
Instruction Mnemonic
Byte
96h
97h
D7h
30h
30h
31h
31h
32h
32h
33h
33h
34h
35h
80h
80h
81h
81h
83h
83h
XCHG EAX, ESI
long
long
alu, alu, alu
alu, alu, alu
XCHG EAX, EDI
XLAT
vector
short
long
XOR mreg8, reg8
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
alux
XOR mem8, reg8
load, alux, store
XOR mreg16/32, reg16/32
XOR mem16/32, reg16/32
XOR reg8, mreg8
short
long
alu
load, alu, store
alux
short
short
short
short
short
short
short
long
XOR reg8, mem8
load, alux
alu
XOR reg16/32, mreg16/32
XOR reg16/32, mem16/32
XOR AL, imm8
load, alu
alux
XOR EAX, imm16/32
XOR mreg8, imm8
alu
11-110-xxx
mm-110-xxx
11-110-xxx
mm-110-xxx
11-110-xxx
mm-110-xxx
alux
XOR mem8, imm8
load, alux, store
alu
XOR mreg16/32, imm16/32
XOR mem16/32, imm16/32
XOR mreg16/32, imm8 (signed ext.)
XOR mem16/32, imm8 (signed ext.)
short
long
load, alu, store
alux
short
long
load, alux, store
Table 13. Floating-Point Instructions
Instruction Mnemonic
First
Byte
Second
Byte
ModR/M
Byte
Decode RISC86
Type
short
short
short
short
short
short
short
vector
vector
short
vector
Operations
F2XM1
FABS
D9h
D9h
D8h
D8h
DCh
DCh
DEh
DFh
DFh
D9h
DBh
F0h
F1h
float
float
FADD ST(0), ST(i)1
11-000-xxx
mm-000-xxx
11-000-xxx
mm-000-xxx
11-000-xxx
mm-100-xxx
mm-110-xxx
float
FADD ST(0), mem32real
fload, float
float
FADD ST(i), ST(0)1
FADD ST(0), mem64real
fload, float
float
FADDP ST(i), ST(0)1
FBLD
FBSTP
FCHS
FCLEX
E0h
E2h
float
74
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AMD-K6™-2E Processor Data Sheet
Table 13. Floating-Point Instructions (continued)
First
Byte
Second
Byte
ModR/M
Byte
Decode RISC86
Instruction Mnemonic
Type
Operations
FCOM ST(0), ST(i)1
D8h
11-010-xxx
mm-010-xxx
mm-010-xxx
11-011-xxx
short
short
short
short
short
short
short
short
short
short
float
FCOM ST(0), mem32real
FCOM ST(0), mem64real
D8h
DCh
D8h
D8h
DCh
DEh
D9h
D9h
D8h
fload, float
fload, float
float
FCOMP ST(0), ST(i)1
FCOMP ST(0), mem32real
FCOMP ST(0), mem64real
FCOMPP
mm-011-xxx
mm-011-xxx
11-011-001
fload, float
fload, float
float
D9h
FFh
F6h
FCOS
float
FDECSTP
float
FDIV ST(0), ST(i) (single precision)1
FDIV ST(0), ST(i) (double precision)1
FDIV ST(0), ST(i) (extended precision)1
FDIV ST(i), ST(0) (single precision)1
FDIV ST(i), ST(0) (double precision)1
11-110-xxx
11-110-xxx
11-110-xxx
11-111-xxx
11-111-xxx
float
D8h
D8h
DCh
DCh
short
short
short
short
float
float
float
float
FDIV ST(i), ST(0) (extended precision)1
FDIV ST(0), mem32real
DCh
D8h
DCh
DEh
11-111-xxx
mm-110-xxx
mm-110-xxx
11-111-xxx
short
short
short
short
float
fload, float
fload, float
float
FDIV ST(0), mem64real
FDIVP ST(0), ST(i)1
FDIVR ST(0), ST(i)1
D8h
11-110-xxx
short
float
FDIVR ST(i), ST(0)1
DCh
D8h
DCh
DEh
11-111-xxx
mm-111-xxx
mm-111-xxx
11-110-xxx
short
short
short
short
float
FDIVR ST(0), mem32real
FDIVR ST(0), mem64real
fload, float
fload, float
float
FDIVRP ST(i), ST(0)1
FFREE ST(i)1
DDh
DAh
DEh
DAh
DEh
DAh
DEh
DAh
DEh
DAh
11-000-xxx
mm-000-xxx
mm-000-xxx
mm-010-xxx
mm-010-xxx
mm-011-xxx
mm-011-xxx
mm-110-xxx
mm-110-xxx
mm-111-xxx
short
short
short
short
short
short
short
short
short
short
float
FIADD ST(0), mem32int
FIADD ST(0), mem16int
FICOM ST(0), mem32int
FICOM ST(0), mem16int
FICOMP ST(0), mem32int
FICOMP ST(0), mem16int
FIDIV ST(0), mem32int
FIDIV ST(0), mem16int
FIDIVR ST(0), mem32int
fload, float
fload, float
fload, float
fload, float
fload, float
fload, float
fload, float
fload, float
fload, float
Chapter 3
Software Environment
75
Preliminary Information
AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
Table 13. Floating-Point Instructions (continued)
First
Byte
Second
Byte
ModR/M
Byte
Decode RISC86
Instruction Mnemonic
Type
short
short
short
short
short
short
short
vector
short
short
short
short
short
short
short
short
short
short
short
short
vector
short
vector
short
short
short
short
short
short
short
short
Operations
fload, float
fload, float
fload, float
fload, float
fload, float
fload, float
FIDIVR ST(0), mem16int
FILD mem16int
DEh
DFh
DBh
DFh
DAh
DEh
D9h
DBh
DFh
DBh
DFh
DBh
DFh
DAh
DEh
DAh
DEh
D9h
D9h
DDh
DBh
D9h
D9h
D9h
D9h
D9h
D9h
D9h
D9h
D9h
D8h
mm-111-xxx
mm-000-xxx
mm-000-xxx
mm-101-xxx
mm-001-xxx
mm-001-xxx
FILD mem32int
FILD mem64int
FIMUL ST(0), mem32int
FIMUL ST(0), mem16int
FINCSTP
F7h
E3h
FINIT
FIST mem16int
mm-010-xxx
mm-010-xxx
mm-011-xxx
mm-011-xxx
mm-111-xxx
mm-100-xxx
mm-100-xxx
mm-101-xxx
mm-101-xxx
11-000-xxx
fload, float
fload, float
fload, float
fload, float
fload, float
fload, float
fload, float
fload, float
fload, float
fload, float
fload, float
fload, float
FIST mem32int
FISTP mem16int
FISTP mem32int
FISTP mem64int
FISUB ST(0), mem32int
FISUB ST(0), mem16int
FISUBR ST(0), mem32int
FISUBR ST(0), mem16int
FLD ST(i)1
FLD mem32real
FLD mem64real
FLD mem80real
FLD1
mm-000-xxx
mm-000-xxx
mm-101-xxx
E8h
fload, float
FLDCW
mm-101-xxx
mm-100-xxx
FLDENV
fload, float
float
FLDL2E
EAh
E9h
ECh
EDh
EBh
EEh
FLDL2T
float
FLDLG2
float
FLDLN2
float
FLDPI
float
FLDZ
float
FMUL ST(0), ST(i)1
11-001-xxx
float
FMUL ST(i), ST(0)1
DCh
D8h
DCh
DEh
11-001-xxx
mm-001-xxx
mm-001-xxx
11-001-xxx
short
short
short
short
float
FMUL ST(0), mem32real
FMUL ST(0), mem64real
fload, float
fload, float
float
FMULP ST(0), ST(i)1
76
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AMD-K6™-2E Processor Data Sheet
Table 13. Floating-Point Instructions (continued)
First
Byte
Second
Byte
ModR/M
Byte
Decode RISC86
Instruction Mnemonic
Type
short
short
short
short
vector
short
vector
vector
short
short
vector
short
short
short
short
short
short
vector
vector
short
short
vector
short
vector
vector
short
short
short
Operations
FNOP
D9h
D9h
D9h
D9h
D9h
D9h
DDh
DDh
D9h
D9h
D9h
D9h
D9h
D9h
D9h
DDh
DDh
D9h
D9h
D9h
DDh
D9h
DDh
DFh
DDh
D8h
DCh
D8h
D0h
F3h
F8h
F5h
F2h
FCh
float
FPATAN
float
FPREM
float
FPREM1
float
FPTAN
FRNDINT
float
FRSTOR
mm-100-xxx
mm-110-xxx
FSAVE
FSCALE
FDh
FEh
FBh
FAh
FAh
FAh
float
float
FSIN
FSINCOS
FSQRT (single precision)
FSQRT (double precision)
FSQRT (extended precision)
FST mem32real
FST mem64real
float
float
float
mm-010-xxx
mm-010-xxx
11-010-xxx
fstore
fstore
fstore
FST ST(i)1
FSTCW
mm-111-xxx
mm-110-xxx
mm-011-xxx
mm-011-xxx
mm-111-xxx
11-011-xxx
FSTENV
FSTP mem32real
FSTP mem64real
FSTP mem80real
fstore
fstore
FSTP ST(i)1
float
FSTSW AX
E0h
FSTSW mem16
mm-111-xxx
mm-100-xxx
mm-100-xxx
11-100-xxx
FSUB ST(0), mem32real
FSUB ST(0), mem64real
fload, float
fload, float
float
FSUB ST(0), ST(i)1
FSUB ST(i), ST(0)1
DCh
11-101-xxx
short
float
FSUBP ST(0), ST(i)1
DEh
D8h
DCh
D8h
11-101-xxx
mm-101-xxx
mm-101-xxx
11-100-xxx
short
short
short
short
float
FSUBR ST(0), mem32real
FSUBR ST(0), mem64real
fload, float
fload, float
float
FSUBR ST(0), ST(i)1
FSUBR ST(i), ST(0)1
DCh
11-101-xxx
short
float
Chapter 3
Software Environment
77
Preliminary Information
AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
Table 13. Floating-Point Instructions (continued)
First
Byte
Second
Byte
ModR/M
Byte
Decode RISC86
Instruction Mnemonic
Type
Operations
FSUBRP ST(i), ST(0)1
DEh
11-100-xxx
short
short
short
short
short
short
short
vector
short
short
vector
float
float
float
float
float
float
float
FTST
D9h
DDh
DDh
DAh
D9h
D9h
D9h
D9h
D9h
9Bh
E4h
FUCOM
FUCOMP
FUCOMPP
FXAM
11-100-xxx
11-101-xxx
E9h
E5h
FXCH
11-001-xxx
FXTRACT
FYL2X
F4h
F1h
F9h
float
float
FYL2XP1
FWAIT
Notes:
1. The last three bits of the modR/M byte select the stack entry ST(i).
Table 14. MMX™ Instructions
Prefix
Byte(s)
First
Byte
ModR/M
Byte
Decode RISC86
Operations
Instruction Mnemonic
Type
vector
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
EMMS
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
77h
6Eh
6Eh
7Eh
7Eh
6Fh
6Fh
7Fh
7Fh
6Bh
6Bh
63h
63h
67h
67h
FCh
FCh
MOVD mmreg, mreg321
MOVD mmreg, mem32
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
meu
mload
MOVD mreg32, mmreg1
MOVD mem32, mmreg
mstore, load
mstore
meu
MOVQ mmreg1, mmreg2
MOVQ mmreg, mem64
mload
MOVQ mmreg2, mmreg1
MOVQ mem64, mmreg
meu
mstore
meu
PACKSSDW mmreg1, mmreg2
PACKSSDW mmreg, mem64
PACKSSWB mmreg1, mmreg2
PACKSSWB mmreg, mem64
PACKUSWB mmreg1, mmreg2
PACKUSWB mmreg, mem64
PADDB mmreg1, mmreg2
PADDB mmreg, mem64
mload, meu
meu
mload, meu
meu
mload, meu
meu
mload, meu
78
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AMD-K6™-2E Processor Data Sheet
Table 14. MMX™ Instructions (continued)
Prefix
First
Byte
ModR/M
Byte
Decode RISC86
Instruction Mnemonic
Byte(s)
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
Type
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
Operations
PADDD mmreg1, mmreg2
PADDD mmreg, mem64
FEh
FEh
ECh
ECh
EDh
EDh
DCh
DCh
DDh
DDh
FDh
FDh
DBh
DBh
DFh
DFh
74h
74h
76h
76h
75h
75h
64h
64h
66h
66h
65h
65h
F5h
F5h
E5h
E5h
D5h
D5h
EBh
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
meu
mload, meu
meu
PADDSB mmreg1, mmreg2
PADDSB mmreg, mem64
PADDSW mmreg1, mmreg2
PADDSW mmreg, mem64
PADDUSB mmreg1, mmreg2
PADDUSB mmreg, mem64
PADDUSW mmreg1, mmreg2
PADDUSW mmreg, mem64
PADDW mmreg1, mmreg2
PADDW mmreg, mem64
PAND mmreg1, mmreg2
mload, meu
meu
mload, meu
meu
mload, meu
meu
mload, meu
meu
mload, meu
meu
PAND mmreg, mem64
mload, meu
meu
PANDN mmreg1, mmreg2
PANDN mmreg, mem64
mload, meu
meu
PCMPEQB mmreg1, mmreg2
PCMPEQB mmreg, mem64
PCMPEQD mmreg1, mmreg2
PCMPEQD mmreg, mem64
PCMPEQW mmreg1, mmreg2
PCMPEQW mmreg, mem64
PCMPGTB mmreg1, mmreg2
PCMPGTB mmreg, mem64
PCMPGTD mmreg1, mmreg2
PCMPGTD mmreg, mem64
PCMPGTW mmreg1, mmreg2
PCMPGTW mmreg, mem64
PMADDWD mmreg1, mmreg2
PMADDWD mmreg, mem64
PMULHW mmreg1, mmreg2
PMULHW mmreg, mem64
PMULLW mmreg1, mmreg2
PMULLW mmreg, mem64
POR mmreg1, mmreg2
mload, meu
meu
mload, meu
meu
mload, meu
meu
mload, meu
meu
mload, meu
meu
mload, meu
meu
mload, meu
meu
mload, meu
meu
mload, meu
meu
Chapter 3
Software Environment
79
Preliminary Information
AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
Table 14. MMX™ Instructions (continued)
Prefix
First
Byte
ModR/M
Byte
Decode RISC86
Instruction Mnemonic
Byte(s)
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
Type
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
Operations
mload, meu
meu
POR mmreg, mem64
EBh
F2h
F2h
72h
F3h
F3h
73h
F1h
F1h
71h
E2h
E2h
72h
E1h
E1h
71h
D2h
D2h
72h
D3h
D3h
73h
D1h
D1h
71h
F8h
F8h
FAh
FAh
E8h
E8h
E9h
E9h
D8h
D8h
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-110-xxx
11-xxx-xxx
mm-xxx-xxx
11-110-xxx
11-xxx-xxx
mm-xxx-xxx
11-110-xxx
11-xxx-xxx
mm-xxx-xxx
11-100-xxx
11-xxx-xxx
mm-xxx-xxx
11-100-xxx
11-xxx-xxx
mm-xxx-xxx
11-010-xxx
11-xxx-xxx
mm-xxx-xxx
11-010-xxx
11-xxx-xxx
mm-xxx-xxx
11-010-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
PSLLD mmreg1, mmreg2
PSLLD mmreg, mem64
PSLLD mmreg, imm8
mload, meu
meu
PSLLQ mmreg1, mmreg2
PSLLQ mmreg, mem64
PSLLQ mmreg, imm8
meu
mload, meu
meu
PSLLW mmreg1, mmreg2
PSLLW mmreg, mem64
PSLLW mmreg, imm8
meu
mload, meu
meu
PSRAD mmreg1, mmreg2
PSRAD mmreg, mem64
PSRAD mmreg, imm8
meu
mload, meu
meu
PSRAW mmreg1, mmreg2
PSRAW mmreg, mem64
PSRAW mmreg, imm8
PSRLD mmreg1, mmreg2
PSRLD mmreg, mem64
PSRLD mmreg, imm8
meu
mload, meu
meu
meu
mload, meu
meu
PSRLQ mmreg1, mmreg2
PSRLQ mmreg, mem64
PSRLQ mmreg, imm8
meu
mload, meu
meu
PSRLW mmreg1, mmreg2
PSRLW mmreg, mem64
PSRLW mmreg, imm8
meu
mload, meu
meu
PSUBB mmreg1, mmreg2
PSUBB mmreg, mem64
PSUBD mmreg1, mmreg2
PSUBD mmreg, mem64
PSUBSB mmreg1, mmreg2
PSUBSB mmreg, mem64
PSUBSW mmreg1, mmreg2
PSUBSW mmreg, mem64
PSUBUSB mmreg1, mmreg2
PSUBUSB mmreg, mem64
meu
mload, meu
meu
mload, meu
meu
mload, meu
meu
mload, meu
meu
mload, meu
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AMD-K6™-2E Processor Data Sheet
Table 14. MMX™ Instructions (continued)
Prefix
First
Byte
ModR/M
Byte
Decode RISC86
Instruction Mnemonic
Byte(s)
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
Type
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
Operations
PSUBUSW mmreg1, mmreg2
PSUBUSW mmreg, mem64
PSUBW mmreg1, mmreg2
D9h
D9h
F9h
F9h
68h
68h
6Ah
6Ah
69h
69h
60h
60h
62h
62h
61h
61h
EFh
EFh
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
meu
mload, meu
meu
PSUBW mmreg, mem64
mload, meu
meu
PUNPCKHBW mmreg1, mmreg2
PUNPCKHBW mmreg, mem64
PUNPCKHDQ mmreg1, mmreg2
PUNPCKHDQ mmreg, mem64
PUNPCKHWD mmreg1, mmreg2
PUNPCKHWD mmreg, mem64
PUNPCKLBW mmreg1, mmreg2
PUNPCKLBW mmreg, mem64
PUNPCKLDQ mmreg1, mmreg2
PUNPCKLDQ mmreg, mem64
PUNPCKLWD mmreg1, mmreg2
PUNPCKLWD mmreg, mem64
PXOR mmreg1, mmreg2
mload, meu
meu
mload, meu
meu
mload, meu
meu
mload, meu
meu
mload, meu
meu
mload, meu
meu
PXOR mmreg, mem64
mload, meu
Notes:
1. Bits 2, 1, and 0 of the modR/M byte select the integer register.
Table 15. 3DNow!™ Instructions
Prefix Opcode
ModR/M
Byte
Decode RISC86
Type Operations
Instruction Mnemonic
Byte(s)
Byte
0Eh
BFh
BFh
1Dh
1Dh
AEh
AEh
9Eh
9Eh
B0h
B0h
FEMMS
0Fh
vector
PAVGUSB mmreg1, mmreg2
PAVGUSB mmreg, mem64
PF2ID mmreg1, mmreg2
PF2ID mmreg, mem64
PFACC mmreg1, mmreg2
PFACC mmreg, mem64
PFADD mmreg1, mmreg2
PFADD mmreg, mem64
PFCMPEQ mmreg1, mmreg2
PFCMPEQ mmreg, mem64
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
short
short
short
short
short
short
short
short
short
short
meu
mload, meu
meu
mload, meu
meu
mload, meu
meu
mload, meu
meu
mload, meu
Chapter 3
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Table 15. 3DNow!™ Instructions (continued)
Prefix Opcode
ModR/M
Byte
Decode RISC86
Type Operations
Instruction Mnemonic
Byte(s)
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh, 0Fh
0Fh
Byte
90h
90h
A0h
A0h
A4h
A4h
94h
94h
B4h
B4h
96h
96h
A6h
A6h
B6h
B6h
A7h
A7h
97h
97h
9Ah
9Ah
AAh
AAh
0Dh
0Dh
B7h
B7h
0Dh
PFCMPGE mmreg1, mmreg2
PFCMPGE mmreg, mem64
PFCMPGT mmreg1, mmreg2
PFCMPGT mmreg, mem64
PFMAX mmreg1, mmreg2
PFMAX mmreg, mem64
PFMIN mmreg1, mmreg2
PFMIN mmreg, mem64
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
11-xxx-xxx
mm-xxx-xxx
mm-000-xxx
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
short
vector
meu
mload, meu
meu
mload, meu
meu
mload, meu
meu
mload, meu
meu
PFMUL mmreg1, mmreg2
PFMUL mmreg, mem64
PFRCP mmreg1, mmreg2
PFRCP mmreg, mem64
mload, meu
meu
mload, meu
meu
PFRCPIT1 mmreg1, mmreg2
PFRCPIT1 mmreg, mem64
PFRCPIT2 mmreg1, mmreg2
PFRCPIT2 mmreg, mem64
PFRSQIT1 mmreg1, mmreg2
PFRSQIT1 mmreg, mem64
PFRSQRT mmreg1, mmreg2
PFRSQRT mmreg, mem64
PFSUB mmreg1, mmreg2
PFSUB mmreg, mem64
mload, meu
meu
mload, meu
meu
mload, meu
meu
mload, meu
meu
mload, meu
meu
PFSUBR mmreg1, mmreg2
PFSUBR mmreg, mem64
PI2FD mmreg1, mmreg2
PI2FD mmreg, mem64
mload, meu
meu
mload, meu
meu
PMULHRW mmreg1, mmreg2
PMULHRW mmreg1, mem64
mload, meu
load
PREFETCH mem81
PREFETCHW mem81,2
Notes:
0Fh
0Dh
mm-001-xxx
vector
load
1. For PREFETCH and PREFETCHW, the mem8 value refers to a byte address within the 32-byte line that will be prefetched.
2. PREFETCHW will be implemented in a future K86 processor. On the AMD-K6-2E processor, this instruction performs in the same
manner as the PREFETCH instruction.
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4
Logic Symbol Diagram
Clock
Voltage Detection
BF[2:0]
VCC2H/L#
VCC2DET
CLK
AHOLD
BOFF#
BREQ
HLDA
HOLD
BRDY#
BRDYC#
D[63:0]
DP[7:0]
PCHK#
Data
and
Data
Parity
Bus
Arbitration
A20M#
A[31:3]
AP
Address
and
Address
Parity
EADS#
HIT#
HITM#
INV
Inquire
Cycles
ADS#
ADSC#
APCHK#
BE[7:0]#
AMD-K6™-2E
D/C#
FERR#
IGNNE#
Floating-Point
Error Handling
EWBE#
LOCK#
M/IO#
NA#
Processor
Cycle
Definition
and
Control
SCYC
W/R#
FLUSH#
INIT
INTR
NMI
RESET
SMI#
External
Interrupts,
SMM, Reset and
Initialization
CACHE#
KEN#
PCD
Cache
Control
PWT
SMIACT#
STPCLK#
WB/WT#
TCK TDI TDO TMS TRST#
JTAG Test
Notes:
The signals are grouped by function. The arrows show the direction of the signal, either into or out of the processor. Signals with double-
headed arrows are bidirectional. Signals with pound signs (#) are active Low.
Chapter 4
Logic Symbol Diagram
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Logic Symbol Diagram
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AMD-K6™-2E Processor Data Sheet
5
Signal Descriptions
This chapter includes a detailed description of each signal
supported on the AMD-K6-2E processor. This chapter also
provides tables listing the signals grouped by type, beginning
on page 130.
The logic symbol diagram on page 83 shows the signals grouped
by function.
Connection diagrams and pins listed by high-level function are
included in Chapter 17, “Pin Designation Diagrams” on page
299.
5.1
Signal Terminology
The following terminology is used in this chapter:
■ Driven—The processor actively pulls the signal up to the
High-voltage state or pulls the signal down to the
Low-voltage state.
■ Floated—The the signal is not being driven by the processor
(high-impedance state), which allows another device to
drive this signal.
■ Asserted—For all active-High signals, the term asserted
means the signal is in the High-voltage state. For all
active-Low signals, the term asserted means the signal is in
the Low-voltage state.
■ Negated—For all active-High signals, the term negated
means the signal is in the Low-voltage state. For all
active-Low signals, the term negated means the signal is in
the High-voltage state.
■ Sampled—The processor has measured the state of a signal
at predefined points in time and will take the appropriate
action based on the state of the signal. If a signal is not
sampled by the processor, its assertion or negation has no
effect on the operation of the processor.
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5.2
A20M# (Address Bit 20 Mask)
Pin Attribute
Pin Location
Summary
Input
AK-08
A20M# is used to simulate the behavior of the 8086 when
running in real mode. The assertion of A20M# causes the
processor to force bit 20 of the physical address to 0 prior to
accessing the cache or driving out a memory bus cycle. The
clearing of address bit 20 maps addresses that wrap above
1 Mbyte to addresses below 1 Mbyte.
Sampled
The processor samples A20M# as a level-sensitive input on
every clock edge. The system logic can drive the signal either
synchronously or asynchronously. If it is asserted
asynchronously, it must be asserted for a minimum pulse width
of two clocks.
The following list explains the effects of the processor sampling
A20M# asserted under various conditions:
■ Inquire cycles and writeback cycles are not affected by the
state of A20M#.
■ The assertion of A20M# in system management mode
(SMM) is ignored.
■ When A20M# is sampled asserted in protected mode, it
causes unpredictable processor operation. A20M# is only
defined in real mode.
■ To ensure that A20M# is recognized before the first ADS#
occurs following the negation of RESET, A20M# must be
sampled asserted on the same clock edge that RESET is
sampled negated or on one of the two subsequent clock
edges.
■ To ensure A20M# is recognized before the execution of an
instruction, a serializing instruction must be executed
between the instruction that asserts A20M# and the
targeted instruction.
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5.3
A[31:3] (Address Bus)
Pin Attribute
Pin Location
Summary
A[31:5] Bidirectional, A[4:3] Output
See “Pin Designations by Functional Grouping” on page 301.
A[31:3] contain the physical address for the current bus cycle.
The processor drives addresses on A[31:3] during memory and
I/O cycles, and cycle definition information during special bus
cycles. The processor samples addresses on A[31:5] during
inquire cycles.
Driven, Sampled, and
Floated
As Outputs: A[31:3] are driven valid off the same clock edge as
ADS# and remain in the same state until the clock edge on
which NA# or the last expected BRDY# of the cycle is sampled
asserted. A[31:3] are driven during memory cycles, I/O cycles,
special bus cycles, and interrupt acknowledge cycles. The
processor continues to drive the address bus while the bus is
idle.
As Inputs: The processor samples A[31:5] during inquire cycles
on the clock edge on which EADS# is sampled asserted. Even
though A4 and A3 are not used during the inquire cycle, they
must be driven to a valid state and must meet the same timings
as A[31:5].
A[31:3] are floated off the clock edge that AHOLD or BOFF# is
sampled asserted and off the clock edge that the processor
asserts HLDA in recognition of HOLD.
The processor resumes driving A[31:3] off the clock edge on
which the processor samples AHOLD or BOFF#negated and off
the clock edge on which the processor negates HLDA.
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5.4
ADS# (Address Strobe)
Pin Attribute
Pin Location
Summary
Output
AJ-05
The assertion of ADS# indicates the beginning of a new bus
cycle. The address bus and all cycle definition signals
corresponding to this bus cycle are driven valid off the same
clock edge as ADS#.
Driven and Floated
ADS# is asserted for one clock at the beginning of each bus
cycle. For non-pipelined cycles, ADS# can be asserted as early
as the clock edge after the clock edge on which the last
expected BRDY#of the cycle is sampled asserted, resulting in a
single idle state between cycles. For pipelined cycles if the
processor is prepared to start a new cycle, ADS#can be asserted
as early as one clock edge after NA#is sampled asserted.
If AHOLD is sampled asserted, ADS# is only driven in order to
perform a writeback cycle due to an inquire cycle that hits a
modified cache line.
The processor floats ADS# off the clock edge that BOFF# is
sampled asserted and off the clock edge that the processor
asserts HLDA in recognition of HOLD.
5.5
ADSC# (Address Strobe Copy)
Pin Attribute
Pin Location
Summary
Output
AM-02
ADSC# has the identical function and timing as ADS#. In the
event ADS# becomes too heavily loaded due to a large fanout in
a system, ADSC# can be used to split the load across two
outputs, which can improve system timing.
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5.6
AHOLD (Address Hold)
Pin Attribute
Pin Location
Summary
Input
V-04
AHOLD can be asserted by the system to initiate one or more
inquire cycles. To allow the system to drive the address bus
during an inquire cycle, the processor floats A[31:3] and AP off
the clock edge on which AHOLD is sampled asserted. The data
bus and all other control and status signals remain under the
control of the processor and are not floated. This allows a bus
cycle that is in progress when AHOLD is sampled asserted to
continue to completion. The processor resumes driving the
address bus off the clock edge on which AHOLD is sampled
negated.
If AHOLD is sampled asserted, ADS# is only asserted in order
to perform a writeback cycle due to an inquire cycle that hits a
modified cache line.
Sampled
The processor samples AHOLD on every clock edge. AHOLD is
recognized while INIT and RESET are sampled asserted.
Chapter 5
Signal Descriptions
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5.7
AP (Address Parity)
Pin Attribute
Pin Location
Summary
Bidirectional
AK-02
AP contains the even parity bit for cache line addresses driven
and sampled on A[31:5]. Even parity means that the total
number of 1 bits on AP and A[31:5] is even. (A4 and A3 are not
used for the generation or checking of address parity because
these bits are not required to address a cache line.) AP is driven
by the processor during processor-initiated cycles and is
sampled by the processor during inquire cycles. If AP does not
reflect even parity during an inquire cycle, the processor
asserts APCHK# to indicate an address bus parity check. The
processor does not take an internal exception as the result of
detecting an address bus parity check, and system logic must
respond appropriately to the assertion of this signal.
Driven, Sampled, and
Floated
As an Output: The processor drives AP valid off the clock edge
on which ADS#is asserted until the clock edge on which NA#or
the last expected BRDY# of the cycle is sampled asserted. AP is
driven during memory cycles, I/O cycles, special bus cycles, and
interrupt acknowledge cycles. The processor continues to drive
AP while the bus is idle.
As an Input: The processor samples AP during inquire cycles on
the clock edge on which EADS#is sampled asserted.
The processor floats AP off the clock edge that AHOLD or
BOFF# is sampled asserted and off the clock edge that the
processor asserts HLDA in recognition of HOLD.
The processor resumes driving AP off the clock edge on which
the processor samples AHOLD or BOFF# negated and off the
clock edge on which the processor negates HLDA.
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5.8
APCHK# (Address Parity Check)
Pin Attribute
Pin Location
Summary
Output
AE-05
If the processor detects an address parity error during an
inquire cycle, APCHK# is asserted for one clock. The processor
does not take an internal exception as the result of detecting an
address bus parity check, and system logic must respond
appropriately to the assertion of this signal.
The processor is designed so that APCHK# does not glitch,
enabling the signal to be used as a clocking source for system
logic.
Driven
APCHK# is driven valid off the clock edge after the clock edge
on which the processor samples EADS# asserted. It is negated
off the next clock edge.
APCHK# is always driven except in the three-state test mode.
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5.9
BE[7:0]# (Byte Enables)
Pin Attribute
Pin Location
Summary
Output
See “Pin Designations by Functional Grouping” on page 301.
BE[7:0]# are used by the processor to indicate the valid data
bytes during a write cycle and the requested data bytes during
a read cycle. The byte enables can be used to derive address bits
A[2:0], which are not physically part of the processor’s address
bus. The processor checks and generates valid data parity for
the data bytes that are valid as defined by the byte enables. The
eight byte enables correspond to the eight bytes of the data bus
as follows:
■ BE7#: D[63:56]
■ BE6#: D[55:48]
■ BE5#: D[47:40]
■ BE4#: D[39:32]
■ BE3#: D[31:24]
■ BE2#: D[23:16]
■ BE1#: D[15:8]
■ BE0#: D[7:0]
The processor expects data to be driven by the system logic on
all eight bytes of the data bus during a burst cache-line read
cycle, independent of the byte enables that are asserted.
The byte enables are also used to distinguish between special
bus cycles as defined in Table 23 on page 132.
Driven and Floated
BE[7:0]# are driven off the same clock edge as ADS# and
remain in the same state until the clock edge on which NA# or
the last expected BRDY# of the cycle is sampled asserted.
BE[7:0]# are driven during memory cycles, I/O cycles, special
bus cycles, and interrupt acknowledge cycles.
The processor floats BE[7:0]# off the clock edge that BOFF# is
sampled asserted and off the clock edge that the processor
asserts HLDA in recognition of HOLD. Unlike the address bus,
BE[7:0]# are not floated in response to AHOLD.
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5.10
BF[2:0] (Bus Frequency)
Pin Attributes
Pin Location
Summary
Inputs, Internal Pullups
See “Pin Designations by Functional Grouping” on page 301.
BF[2:0] determine the internal operating frequency of the
processor. The frequency of the CLK input signal is multiplied
internally by a ratio determined by the state of these signals as
defined in Table 16. BF[2:0] have weak internal pullups and
default to the 3.5 multiplier if left unconnected.
Table 16. Processor-to-Bus Clock Ratios
State of BF[2:0] Inputs
Processor-Clock to Bus-Clock Ratio
100b
101b
111b
010b
000b
001b
011b
110b
2.5x
3.0x
3.5x
4.0x
4.5x
5.0x
5.5x
6.0x
Sampled
BF[2:0] are sampled during the falling transition of RESET.
They must meet a minimum setup time of 1.0 ms and a
minimum hold time of two clocks relative to the negation of
RESET.
Chapter 5
Signal Descriptions
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5.11
BOFF# (Backoff)
Pin Attribute
Pin Location
Summary
Input
Z-04
If BOFF# is sampled asserted, the processor unconditionally
aborts any cycles in progress and transitions to a bus hold state
by floating the following signals: A[31:3], ADS#, ADSC#, AP,
BE[7:0]#, CACHE#, D[63:0], D/C#, DP[7:0], LOCK#, M/IO#,
PCD, PWT, SCYC, and W/R#. These signals remain floated until
BOFF# is sampled negated. This allows an alternate bus master
or the system to control the bus.
When BOFF# is sampled negated, any processor cycle that was
aborted due to the assertion of BOFF# is restarted from the
beginning of the cycle, regardless of the number of transfers
that were completed. If BOFF# is sampled asserted on the same
clock edge as BRDY# of a bus cycle of any length, then BOFF#
takes precedence over the BRDY#. In this case, the cycle is
aborted and restarted after BOFF#is sampled negated.
Sampled
BOFF# is sampled on every clock edge. The processor floats its
bus signals off the clock edge on which BOFF# is sampled
asserted. These signals remain floated until the clock edge on
which BOFF#is sampled negated.
BOFF# is recognized while INIT and RESET are sampled
asserted.
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5.12
BRDY# (Burst Ready)
Pin Attribute
Pin Location
Summary
Input, Internal Pullup
X-04
BRDY# is asserted to the processor by system logic to indicate
either that the data bus is being driven with valid data during a
read cycle or that the data bus has been latched during a write
cycle. If necessary, the system logic can insert bus cycle wait
states by negating BRDY# until it is ready to continue the data
transfer. BRDY# is also used to indicate the completion of
special bus cycles.
Sampled
BRDY# is sampled every clock edge within a bus cycle starting
with the clock edge after the clock edge that negates ADS#.
BRDY# is ignored while the bus is idle. The processor samples
the following inputs on the clock edge on which BRDY# is
sampled asserted: D[63:0], DP[7:0], and KEN# during read
cycles, EWBE# during write cycles (if not masked off), and
WB/WT# during read and write cycles. If NA# is sampled
asserted prior to BRDY#, then KEN# and WB/WT# are sampled
on the clock edge on which NA#is sampled asserted.
The number of times the processor expects to sample BRDY#
asserted depends on the type of bus cycle, as follows:
■ One time for a single-transfer cycle, a special bus cycle, or
each of two cycles in an interrupt acknowledge sequence
■ Four times for a burst cycle (once for each data transfer)
BRDY# can be held asserted for four consecutive clocks
throughout the four transfers of the burst, or it can be negated
to insert wait states.
Chapter 5
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5.13
BRDYC# (Burst Ready Copy)
Pin Attribute
Pin Location
Summary
Input, Internal Pullup
Y-03
BRDYC# has the identical function as BRDY#. In the event
BRDY# becomes too heavily loaded due to a large fanout or
loading in a system, BRDYC# can be used to reduce this
loading, which improves timing.
Sampled
BRDYC#is sampled every clock edge within a bus cycle starting
with the clock edge after the clock edge that negates ADS#.
5.14
BREQ (Bus Request)
Pin Attribute
Pin Location
Summary
Output
AJ-01
BREQ is asserted by the processor to request the bus in order to
complete an internally pending bus cycle. The system logic can
use BREQ to arbitrate among the bus participants. If the
processor does not own the bus, BREQ is asserted until the
processor gains access to the bus in order to begin the pending
cycle or until the processor no longer needs to run the pending
cycle. If the processor currently owns the bus, BREQ is asserted
with ADS#. The processor asserts BREQ for each assertion of
ADS#but does not necessarily assert ADS#for each assertion of
BREQ.
Driven
BREQ is asserted off the same clock edge on which ADS# is
asserted. BREQ can also be asserted off any clock edge,
independent of the assertion of ADS#. BREQ can be negated
one clock edge after it is asserted.
The processor always drives BREQ except in the three-state test
mode.
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5.15
CACHE# (Cacheable Access)
Pin Attribute
Pin Location
Summary
Output
U-03
For reads, CACHE# is asserted to indicate the cacheability of
the current bus cycle. In addition, if the processor samples
KEN # asserted, which indicates the driven address is
cacheable, the cycle is a 32-byte burst read cycle. For write
cycles, CACHE#is asserted to indicate the current bus cycle is a
modified cache-line writeback. KEN# is ignored during
writebacks. If CACHE# is not asserted, or if KEN# is sampled
negated during a read cycle, the cycle is not cacheable and
defaults to a single-transfer cycle.
Driven and Floated
CACHE#is driven off the same clock edge as ADS#and remains
in the same state until the clock edge on which NA# or the last
expected BRDY#of the cycle is sampled asserted.
CACHE# is floated off the clock edge that BOFF# is sampled
asserted and off the clock edge that the processor asserts HLDA
in recognition of HOLD.
5.16
CLK (Clock)
Pin Attribute
Pin Location
Summary
Input
AK-18
The CLK signal is the bus clock for the processor and is the
reference for all signal timings under normal operation (except
for TDI, TDO, TMS, and TRST#). BF[2:0] determine the internal
frequency multiplier applied to CLK to obtain the processor’s
core operating frequency. See “BF[2:0] (Bus Frequency)” on
page 93 for a list of the processor-to-bus clock ratios.
Sampled
The CLK signal must be stable a minimum of 1.0 ms prior to the
negation of RESET to ensure the proper operation of the
processor. See “CLK Switching Characteristics” on page 267 for
details regarding the CLK specifications.
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5.17
D/C# (Data/Code)
Pin Attribute
Pin Location
Summary
Output
AK-04
The processor drives D/C# during a memory bus cycle to
indicate whether it is addressing data or executable code. D/C#
is also used to define other bus cycles, including interrupt
acknowledge and special cycles. See Table 23 on page 132 for
more details.
Driven and Floated
D/C# is driven off the same clock edge as ADS# and remains in
the same state until the clock edge on which NA# or the last
expected BRDY# of the cycle is sampled asserted. D/C# is
driven during memory cycles, I/O cycles, special bus cycles, and
interrupt acknowledge cycles.
D/C# is floated off the clock edge that BOFF# is sampled
asserted and off the clock edge that the processor asserts HLDA
in recognition of HOLD.
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5.18
D[63:0] (Data Bus)
Pin Attribute
Pin Location
Summary
Bidirectional
See “Pin Designations by Functional Grouping” on page 301.
D[63:0] represent the processor’s 64-bit data bus. Each of the
eight bytes of data that comprise this bus is qualified as valid
by its corresponding byte enable. See “BE[7:0]# (Byte
Enables)” on page 92.
Driven, Sampled, and
Floated
As Outputs: For single-transfer write cycles, the processor drives
D[63:0] with valid data one clock edge after the clock edge on
which ADS# is asserted and D[63:0] remain in the same state
until the clock edge on which BRDY#is sampled asserted. If the
cycle is a writeback—in which case four, 8-byte transfers
occur—D[63:0] are driven one clock edge after the clock edge
on which ADS# is asserted and are subsequently changed off
the clock edge on which each BRDY# assertion of the burst
cycle is sampled.
If the assertion of ADS# represents a pipelined write cycle that
follows a read cycle, the processor does not drive D[63:0] until it
is certain that contention on the data bus will not occur. In this
case, D[63:0] are driven the clock edge after the last expected
BRDY#of the previous cycle is sampled asserted.
As Inputs: During read cycles, the processor samples D[63:0] on
the clock edge on which BRDY#is sampled asserted.
The processor always floats D[63:0] except when they are being
driven during a write cycle as described above. In addition,
D[63:0] are floated off the clock edge that BOFF# is sampled
asserted and off the clock edge that the processor asserts
HLDA in recognition of HOLD.
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5.19
DP[7:0] (Data Parity)
Pin Attribute
Pin Location
Summary
Bidirectional
See “Pin Designations by Functional Grouping” on page 301.
DP[7:0] are even parity bits for each valid byte of data—as
defined by BE[7:0]#—driven and sampled on the D[63:0] data
bus. Even parity means that the total number of odd (1) bits
within each byte of data and its respective data parity bit is an
even number. DP[7:0] are driven by the processor during write
cycles and sampled by the processor during read cycles.
If the processor detects bad parity on any valid byte of data
during a read cycle, PCHK# is asserted for one clock beginning
the clock edge after BRDY# is sampled asserted. The processor
does not take an internal exception as the result of detecting a
data parity check, and system logic must respond appropriately
to the assertion of this signal.
The eight data parity bits correspond to the eight bytes of the
data bus as follows:
■ DP7: D[63:56]
■ DP6: D[55:48]
■ DP5: D[47:40]
■ DP4: D[39:32]
■ DP3: D[31:24]
■ DP2: D[23:16]
■ DP1: D[15:8]
■ DP0: D[7:0]
For systems that do not support data parity, DP[7:0] should be
connected to V through pullup resistors.
CC3
Driven, Sampled, and
Floated
As Outputs: For single-transfer write cycles, the processor drives
DP[7:0] with valid parity one clock edge after the clock edge on
which ADS# is asserted and DP[7:0] remain in the same state
until the clock edge on which BRDY# is sampled asserted. If the
cycle is a writeback, DP[7:0] are driven one clock edge after the
clock edge on which ADS# is asserted and are subsequently
changed off the clock edge on which each BRDY# assertion of
the burst cycle is sampled.
As Inputs: During read cycles, the processor samples DP[7:0] on
the clock edge on which BRDY#is sampled asserted.
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The processor always floats DP[7:0] except when they are being
driven during a write cycle as described above. In addition,
DP[7:0] are floated off the clock edge that BOFF# is sampled
asserted and off the clock edge that the processor asserts HLDA
in recognition of HOLD.
5.20
EADS# (External Address Strobe)
Pin Attribute
Pin Location
Summary
Input
AM-04
System logic asserts EADS# during a cache inquire cycle to
indicate that the address bus contains a valid address. EADS#
can only be driven after the system logic has taken control of
the address bus by asserting AHOLD or BOFF# or by receiving
HLDA. The processor responds to the sampling of EADS# and
the address bus by driving HIT#, which indicates if the inquired
cache line exists in the processor’s cache, and HITM#, which
indicates if it is in the modified state.
Sampled
If AHOLD or BOFF# is asserted by the system logic in order to
execute a cache inquire cycle, the processor begins sampling
EADS# two clock edges after AHOLD or BOFF# is sampled
asserted. If the system logic asserts HOLD in order to execute a
cache inquire cycle, the processor begins sampling EADS# two
clock edges after the clock edge HLDA is asserted by the
processor.
EADS#is ignored during the following conditions:
■ One clock edge after the clock edge on which EADS# is
sampled asserted
■ Two clock edges after the clock edge on which ADS# is
asserted
■ When the processor is driving the address bus
■ When the processor asserts HITM#
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5.21
EWBE# (External Write Buffer Empty)
Pin Attribute
Pin Location
Summary
Input
W-03
The system logic can negate EWBE#to the processor to indicate
that its external write buffers are full and that additional data
cannot be stored at this time. This causes the processor to delay
the following activities until EWBE# is sampled asserted:
■ The commitment of write hit cycles to cache lines in the
modified state or exclusive state in the processor’s cache
■ The decode and execution of an instruction that follows a
currently-executing serializing instruction
■ The assertion or negation of SMIACT#
■ The entering of the Halt state and the Stop Grant state
Negating EWBE# does not prevent the completion of any type
of cycle that is currently in progress.
Sampled
The processor samples EWBE# on each clock edge that BRDY#
is sampled asserted during all memory write cycles (except
writeback cycles), I/O write cycles, and special bus cycles.
If EWBE# is sampled negated, it is sampled on every clock edge
until it is asserted, and then it is ignored until BRDY# is
sampled asserted in the next write cycle or special cycle.
If EFER[3] is 1, then EWBE# is ignored by the processor. For
more information on the EFER settings and EWBE#, see
“EWBE# Control” on page 205.
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5.22
FERR# (Floating-Point Error)
Pin Attribute
Pin Location
Summary
Output
Q-05
The assertion of FERR# indicates the occurrence of an
unmasked floating-point exception resulting from the
execution of a floating-point instruction. This signal is provided
to allow the system logic to handle this exception in a manner
consistent with IBM-compatible PC/AT systems. See “Handling
Floating-Point Exceptions” on page 213 for a system logic
implementation that supports floating-point exceptions.
The state of the numeric error (NE) bit in CR0 does not affect
the FERR# signal.
The processor is designed so that FERR# does not glitch,
enabling the signal to be used as a clocking source for system
logic.
Driven
The processor asserts FERR# on the instruction boundary of
the next floating-point instruction, MMX instruction, 3DNow!
instruction, or WAIT instruction that occurs following the
floating-point instruction that caused the unmasked
floating-point exception—that is, FERR# is not asserted at the
time the exception occurs. The IGNNE# signal does not affect
the assertion of FERR#.
FERR#is negated during the following conditions:
■ Following the successful execution of the floating-point
instructions FCLEX, FINIT, FSAVE, and FSTENV
■ Under certain circumstances, following the successful
execution of the floating-point instructions FLDCW,
FLDENV, and FRSTOR, which load the floating-point status
word or the floating-point control word
■ Following the falling transition of RESET
FERR#is always driven except in the three-state test mode.
See “IGNNE# (Ignore Numeric Exception)” on page 108 for
more details on floating-point exceptions.
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5.23
FLUSH# (Cache Flush)
Pin Attribute
Pin Location
Summary
Input
AN-07
In response to sampling FLUSH# asserted, the processor writes
back any data cache lines that are in the modified state,
invalidates all lines in the instruction and data caches, and then
executes a flush acknowledge special cycle. See Table 23 on
page 132 for the bus definition of special cycles.
In addition, FLUSH# is sampled when RESET is negated to
determine if the processor enters the three-state test mode. If
FLUSH# is 0 during the falling transition of RESET, the
processor enters the three-state test mode instead of
performing the normal RESET functions.
Sampled
FLUSH# is sampled and latched as a falling edge-sensitive
signal. During normal operation (not RESET), FLUSH# is
sampled on every clock edge but is not recognized until the next
instruction boundary. If FLUSH# is asserted synchronously, it
can be asserted for a minimum of one clock. If FLUSH# is
asserted asynchronously, it must have been negated for a
minimum of two clocks, followed by an assertion of a minimum
of two clocks.
FLUSH#is also sampled during the falling transition of RESET.
If RESET and FLUSH# are driven synchronously, FLUSH# is
sampled on the clock edge prior to the clock edge on which
RESET is sampled negated. If RESET is driven asynchronously,
the minimum setup and hold time for FLUSH#, relative to the
negation of RESET, is two clocks.
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5.24
HIT# (Inquire Cycle Hit)
Pin Attribute
Pin Location
Summary
Output
AK-06
The processor asserts HIT# during an inquire cycle to indicate
that the cache line is valid within the processor’s instruction or
data cache (also known as a cache hit). The cache line can be in
the modified, exclusive, or shared state.
Driven
HIT# is always driven—except in the three-state test mode—
and only changes state the clock edge after the clock edge on
which EADS# is sampled asserted. It is driven in the same state
until the next inquire cycle.
5.25
HITM# (Inquire Cycle Hit To Modified Line)
Pin Attribute
Pin Location
Summary
Output
AL-05
The processor asserts HITM# during an inquire cycle to
indicate that the cache line exists in the processor’s data cache
in the modified state. The processor performs a writeback cycle
as a result of this cache hit. If an inquire cycle hits a cache line
that is currently being written back, the processor asserts
HITM# but does not execute another writeback cycle. The
system logic must not expect the processor to assert ADS# each
time HITM#is asserted.
Driven
HITM# is always driven—except in the three-state test mode—
and, in particular, is driven to represent the result of an inquire
cycle the clock edge after the clock edge on which EADS# is
sampled asserted. If HITM# is negated in response to the
inquire address, it remains negated until the next inquire cycle.
If HITM# is asserted in response to the inquire address, it
remains asserted throughout the writeback cycle and is negated
one clock edge after the last BRDY# of the writeback is
sampled asserted.
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5.26
HLDA (Hold Acknowledge)
Pin Attribute
Pin Location
Summary
Output
AJ-03
When HOLD is sampled asserted, the processor completes the
current bus cycles, floats the processor bus, and asserts HLDA
in an acknowledgment that these events have been completed.
The processor does not assert HLDA until the completion of a
locked sequence of cycles. While HLDA is asserted, another bus
master can drive cycles on the bus, including inquire cycles to
the processor. The following signals are floated when HLDA is
asserted: A[31:3], ADS#, ADSC#, AP, BE[7:0]#, CACHE#,
D[63:0], D/C#, DP[7:0], LOCK#, M/IO#, PCD, PWT, SCYC, and
W/R#.
The processor is designed so that HLDA does not glitch.
Driven
HLDA is always driven except in the three-state test mode. If a
processor cycle is in progress while HOLD is sampled asserted,
HLDA is asserted one clock edge after the last BRDY# of the
cycle is sampled asserted. If the bus is idle, HLDA is asserted
one clock edge after HOLD is sampled asserted. HLDA is
negated one clock edge after the clock edge on which HOLD is
sampled negated.
The assertion of HLDA is independent of the sampled state of
BOFF#.
The processor floats the bus every clock in which HLDA is
asserted.
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5.27
HOLD (Bus Hold Request)
Pin Attribute
Pin Location
Summary
Input
AB-04
The system logic can assert HOLD to gain control of the
processor’s bus. When HOLD is sampled asserted, the processor
completes the current bus cycles, floats the processor bus, and
asserts HLDA in an acknowledgment that these events have
been completed.
Sampled
The processor samples HOLD on every clock edge. If a
processor cycle is in progress while HOLD is sampled asserted,
HLDA is asserted one clock edge after the last BRDY# of the
cycle is sampled asserted. If the bus is idle, HLDA is asserted
one clock edge after HOLD is sampled asserted. HOLD is
recognized while INIT and RESET are sampled asserted.
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5.28
IGNNE# (Ignore Numeric Exception)
Pin Attribute
Pin Location
Summary
Input
AA-35
IGNNE#, in conjunction with the numeric error (NE) bit in CR0,
is used by the system logic to control the effect of an unmasked
floating-point exception on a previous floating-point instruction
during the execution of a floating-point instruction, MMX
instruction, 3DNow! instruction, or the WAIT instruction—
hereafter referred to as the target instruction.
If an unmasked floating-point exception is pending and the
target instruction is considered error-sensitive, then the
relationship between NE and IGNNE# is as follows:
■ If NE = 0, then:
•
If IGNNE# is sampled asserted, the processor ignores the
floating-point exception and continues with the
execution of the target instruction.
•
If IGNNE# is sampled negated, the processor waits until
it samples IGNNE#, INTR, SMI#, NMI, or INIT asserted.
If IGNNE# is sampled asserted while waiting, the
processor ignores the floating-point exception and
continues with the execution of the target instruction.
If INTR, SMI#, NMI, or INIT is sampled asserted while
waiting,
the
processor
handles
its
assertion
appropriately.
■ If NE = 1, the processor invokes the INT 10h exception
handler.
If an unmasked floating-point exception is pending and the
target instruction is considered error-insensitive, then the
processor ignores the floating-point exception and continues
with the execution of the target instruction.
FERR# is not affected by the state of the NE bit or IGNNE#.
FERR# is always asserted at the instruction boundary of the
target instruction that follows the floating-point instruction
that caused the unmasked floating-point exception.
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This signal is provided to allow the system logic to handle
exceptions in a manner consistent with IBM-compatible PC/AT
systems.
Sampled
The processor samples IGNNE# as a level-sensitive input on
every clock edge. The system logic can drive the signal either
synchronously or asynchronously. If it is asserted
asynchronously, it must be asserted for a minimum pulse width
of two clocks.
5.29
INIT (Initialization)
Pin Attribute
Pin Location
Summary
Input
AA-33
The assertion of INIT causes the processor to empty its
pipelines, to initialize most of its internal state, and to branch
to address FFFF_FFF0h—the same instruction execution
starting point used after RESET. Unlike RESET, the processor
preserves the contents of its caches, the floating-point state, the
MMX state, model-specific registers, the CD and NW bits of the
CR0 register, and other specific internal resources.
INIT can be used as an accelerator for 80286 code that requires
a reset to exit from protected mode back to real mode.
Sampled
INIT is sampled and latched as a rising edge-sensitive signal.
INIT is sampled on every clock edge but is not recognized until
the next instruction boundary. During an I/O write cycle, it must
be sampled asserted a minimum of three clock edges before
BRDY# is sampled asserted if it is to be recognized on the
boundary between the I/O write instruction and the following
instruction.
If INIT is asserted synchronously, it can be asserted for a
minimum of one clock. If it is asserted asynchronously, it must
have been negated for a minimum of two clocks, followed by an
assertion of a minimum of two clocks.
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5.30
INTR (Maskable Interrupt)
Pin Attribute
Pin Location
Summary
Input
AD-34
INTR is the system’s maskable interrupt input to the processor.
When the processor samples and recognizes INTR asserted, the
processor executes a pair of interrupt acknowledge bus cycles
and then jumps to the interrupt service routine specified by the
interrupt number that was returned during the interrupt
acknowledge sequence. The processor only recognizes INTR if
the interrupt flag (IF) in the EFLAGS register equals 1.
Sampled
The processor samples INTR as a level-sensitive input on every
clock edge, but the interrupt request is not recognized until the
next instruction boundary. The system logic can drive INTR
either synchronously or asynchronously. If it is asserted
asynchronously, it must be asserted for a minimum pulse width
of two clocks. In order to be recognized, INTR must remain
asserted until an interrupt acknowledge sequence is complete.
5.31
INV (Invalidation Request)
Pin Attribute
Pin Location
Summary
Input
U-05
During an inquire cycle, the state of INV determines whether
an addressed cache line that is found in the processor’s
instruction or data cache transitions to the invalid state or the
shared state.
If INV is sampled asserted during an inquire cycle, the
processor transitions the cache line (if found) to the invalid
state, regardless of its previous state. If INV is sampled negated
during an inquire cycle, the processor transitions the cache line
(if found) to the shared state. In either case, if the cache line is
found in the modified state, the processor writes it back to
memory before changing its state.
Sampled
INV is sampled on the clock edge on which EADS# is sampled
asserted.
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5.32
KEN# (Cache Enable)
Pin Attribute
Pin Location
Summary
Input
W-05
If KEN# is sampled asserted, it indicates that the address
presented by the processor is cacheable. If KEN# is sampled
asserted and the processor intends to perform a cache-line fill
(signified by the assertion of CACHE#), the processor executes
a 32-byte burst read cycle and expects to sample BRDY#
asserted a total of four times. If KEN# is sampled negated
during a read cycle, a single-transfer cycle is executed and the
processor does not cache the data. For write cycles, CACHE# is
asserted to indicate the current bus cycle is a modified
cache-line writeback. KEN#is ignored during writebacks.
If PCD is asserted during a bus cycle, the processor does not
cache any data read during that cycle, regardless of the state of
KEN#. See “PCD (Page Cache Disable)” on page 115 for more
details.
If the processor has sampled the state of KEN# during a cycle,
and that cycle is aborted due to the sampling of BOFF#
asserted, the system logic must ensure that KEN# is sampled in
the same state when the processor restarts the aborted cycle.
Sampled
KEN# is sampled on the clock edge on which the first BRDY# or
NA# of a read cycle is sampled asserted. If the read cycle is a
burst, KEN# is ignored during the last three assertions of
BRDY#. KEN# is sampled during read cycles only when
CACHE# is asserted.
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5.33
LOCK# (Bus Lock)
Pin Attribute
Pin Location
Summary
Output
AH-04
The processor asserts LOCK# during a sequence of bus cycles to
ensure that the cycles are completed without allowing other bus
masters to intervene. Locked operations consist of two to five
bus cycles. LOCK# is asserted during the following operations:
■ An interrupt acknowledge sequence
■ Descriptor Table accesses
■ Page Directory and Page Table accesses
■ XCHG instruction
■ An instruction with an allowable LOCK prefix
In order to ensure that locked operations appear on the bus and
are visible to the entire system, any data operands addressed
during a locked cycle that reside in the processor’s cache are
flushed and invalidated from the cache prior to the locked
operation. If the cache line is in the modified state, it is written
back and invalidated prior to the locked operation. Likewise,
any data read during a locked operation is not cached.
The processor is designed so that LOCK# does not glitch.
Driven and Floated
During a locked cycle, LOCK# is asserted off the same clock
edge on which ADS# is asserted and remains asserted until the
last BRDY# of the last bus cycle is sampled asserted. The
processor negates LOCK# for at least one clock between
consecutive sequences of locked operations to allow the system
logic to arbitrate for the bus.
LOCK# is floated off the clock edge on which BOFF# is sampled
asserted and off the clock edge on which the processor asserts
HLDA in response to HOLD. When LOCK# is floated due to
BOFF# sampled asserted, the system logic is responsible for
preserving the lock condition while LOCK# is in the
high-impedance state.
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5.34
M/IO# (Memory or I/O)
Pin Attribute
Pin Location
Summary
Output
T-04
The processor drives M/IO# during a bus cycle to indicate
whether it is addressing the memory or I/O space. If M/IO# = 1,
the processor is addressing memory or a memory-mapped I/O
port as the result of an instruction fetch or an instruction that
loads or stores data. If M/IO# = 0, the processor is addressing an
I/O port during the execution of an I/O instruction. In addition,
M/IO# is used to define other bus cycles, including interrupt
acknowledge and special cycles. See Table 23 on page 132 for
more details.
Driven and Floated
M/IO# is driven off the same clock edge as ADS# and remains in
the same state until the clock edge on which NA# or the last
expected BRDY# of the cycle is sampled asserted. M/IO# is
driven during memory cycles, I/O cycles, special bus cycles, and
interrupt acknowledge cycles.
M/IO# is floated off the clock edge on which BOFF# is sampled
asserted and off the clock edge on which the processor asserts
HLDA in response to HOLD.
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5.35
NA# (Next Address)
Pin Attribute
Pin Location
Summary
Input
Y-05
System logic asserts NA# to indicate to the processor that it is
ready to accept another bus cycle pipelined into the previous
bus cycle. ADS#, along with address and status signals, can be
asserted as early as one clock edge after NA# is sampled
asserted if the processor is prepared to start a new cycle.
Because the processor allows a maximum of two cycles to be in
progress at a time, the assertion of NA# is sampled while two
cycles are in progress, but ADS# is not asserted until the
completion of the first cycle.
Sampled
NA# is sampled every clock edge during bus cycles, starting one
clock edge after the clock edge that negates ADS#, until the last
expected BRDY# of the last executed cycle is sampled asserted
(with the exception of the clock edge after the clock edge that
negates the ADS# for a second pending cycle). Because the
processor latches NA# when sampled, the system logic only
needs to assert NA# for one clock.
5.36
NMI (Non-Maskable Interrupt)
Pin Attribute
Pin Location
Summary
Input
AC-33
When NMI is sampled asserted, the processor jumps to the
interrupt service routine defined by interrupt number 02h.
Unlike the INTR signal, software cannot mask the effect of NMI
if it is sampled asserted by the processor. However, NMI is
temporarily masked upon entering system management mode
(SMM). In addition, an interrupt acknowledge cycle is not
executed because the interrupt number is predefined.
If NMI is sampled asserted while the processor is executing the
interrupt service routine for a previous NMI, the subsequent
NMI remains pending until the completion of the execution of
the IRET instruction at the end of the interrupt service routine.
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Sampled
NMI is sampled and latched as a rising edge-sensitive signal.
During normal operation, NMI is sampled on every clock edge
but is not recognized until the next instruction boundary. If it is
asserted synchronously, it can be asserted for a minimum of one
clock. If it is asserted asynchronously, it must have been
negated for a minimum of two clocks, followed by an assertion
of a minimum of two clocks.
5.37
PCD (Page Cache Disable)
Pin Attribute
Pin Location
Summary
Output
AG-05
The processor drives PCD to indicate the operating system’s
specification of cacheability for the page being addressed.
System logic can use PCD to control external caching. If PCD is
asserted, the addressed page is not cached. If PCD is negated,
the cacheability of the addressed page depends upon the state
of CACHE# and KEN#.
The state of PCD depends upon the processor’s operating mode
and the state of certain bits in its control registers and TLB as
follows:
■ In real mode, or in protected and virtual-8086 modes while
paging is disabled (PG bit in CR0 is 0):
PCD output = CD bit in CR0
■ In protected and virtual-8086 modes while caching is
enabled (CD bit in CR0 is 0) and paging is enabled (PG bit in
CR0 is 1):
•
•
•
For accesses to I/O space, page directory entries, and
other non-paged accesses:
PCD output = PCD bit in CR3
For accesses to 4-Kbyte page table entries or 4-Mbyte
pages:
PCD output = PCD bit in page directory entry
For accesses to 4-Kbyte pages:
PCD output = PCD bit in page table entry
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Driven and Floated
PCD is driven off the same clock edge as ADS# and remains in
the same state until the clock edge on which NA# or the last
expected BRDY# of the cycle is sampled asserted.
PCD is floated off the clock edge that BOFF# is sampled
asserted and off the clock edge that the processor asserts HLDA
in response to HOLD.
5.38
PCHK# (Parity Check)
Pin Attribute
Pin Location
Summary
Output
AF-04
The processor asserts PCHK# during read cycles if it detects an
even parity error on one or more valid bytes of D[63:0] during a
read cycle. (Even parity means that the total number of odd (1)
bits within each byte of data and its respective data parity bit is
even.) The processor checks data parity for the data bytes that
are valid, as defined by BE[7:0]#, the byte enables.
PCHK# is always driven but is only asserted for memory and I/O
read bus cycles and the second cycle of an interrupt
acknowledge sequence. PCHK# is not driven during any type of
write cycles or special bus cycles. The processor does not take
an internal exception as the result of detecting a data parity
error, and system logic must respond appropriately to the
assertion of this signal.
The processor is designed so that PCHK# does not glitch,
enabling the signal to be used as a clocking source for system
logic.
Driven
PCHK# is always driven except in the three-state test mode. For
each BRDY# returned to the processor during a read cycle with
a parity error detected on the data bus, PCHK# is asserted for
one clock, one clock edge after BRDY# is sampled asserted.
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5.39
PWT (Page Writethrough)
Pin Attribute
Pin Location
Summary
Output
AL-03
The processor drives PWT to indicate the operating system’s
specification of the writeback state or writethrough state for
the page being addressed. PWT, together with WB/WT#,
specifies the data cache-line state during cacheable read misses
and write hits to shared cache lines. See “WB/WT# (Writeback
or Writethrough)” on page 129 for more details.
The state of PWT depends upon the processor’s operating mode
and the state of certain bits in its control registers and TLB as
follows:
■ In real mode, or in protected and virtual-8086 modes while
paging is disabled (PG bit in CR0 is 0):
PWT output = 0 (writeback state)
■ In protected and virtual-8086 modes while paging is enabled
(PG bit in CR0 is 1):
•
•
•
For accesses to I/O space, page directory entries, and
other non-paged accesses:
PWT output = PWT bit in CR3
For accesses to 4-Kbyte page table entries or 4-Mbyte
pages:
PWT output = PWT bit in page directory entry
For accesses to 4-Kbyte pages:
PWT output = PWT bit in page table entry
Driven and Floated
PWT is driven off the same clock edge as ADS# and remains in
the same state until the clock edge on which NA# or the last
expected BRDY# of the cycle is sampled asserted.
PWT is floated off the clock edge on which BOFF# is sampled
asserted and off the clock edge on which the processor asserts
HLDA in response to HOLD.
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5.40
RESET (Reset)
Pin Attribute
Pin Location
Summary
Input
AK-20
When the processor samples RESET asserted, it immediately
flushes and initializes all internal resources and its internal
state including its pipelines and caches, the floating-point
state, the MMX state, the 3DNow! state, and all registers, and
then the processor jumps to address FFFF_FFF0h to start
instruction execution.
The FLUSH# signal is sampled during the falling transition of
RESET to invoke the three-state test mode.
Sampled
RESET is sampled as a level-sensitive input on every clock
edge. System logic can drive the signal either synchronously or
asynchronously.
During the initial power-on reset of the processor, RESET must
remain asserted for a minimum of 1.0 ms after CLK and V
CC
reach specification before it is negated.
During a warm reset, while CLK and V
are within their
CC
specification, RESET must remain asserted for a minimum of
15 clocks prior to its negation.
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5.41
RSVD (Reserved)
Pin Attribute
Pin Location
Summary
Not Applicable
See “Pin Designations by Functional Grouping” on page 301.
Reserved signals are a special class of pins that can be treated
in one of the following ways:
■ As no-connect (NC) pins, in which case these pins are left
unconnected
■ As pins connected to the system logic as defined by the
industry-standard Pentium® interface (Socket 7)
■ Any combination of NC and Socket 7 pins
In any case, if the RSVD pins are treated accordingly, the
normal operation of the AMD-K6-2E processor is not adversely
affected in any manner.
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5.42
SCYC (Split Cycle)
Pin Attribute
Pin Location
Summary
Output
AL-17
The processor asserts SCYC during misaligned, locked transfers
on the D[63:0] data bus. The processor generates additional bus
cycles to complete the transfer of misaligned data.
For purposes of bus cycles, the term aligned means:
■ Any 1-byte transfers
■ 2-byte and 4-byte transfers that lie within 4-byte address
boundaries
■ 8-byte transfers that lie within 8-byte address boundaries
Driven and Floated
SCYC is asserted off the same clock edge as ADS#, and negated
off the clock edge on which NA# or the last expected BRDY# of
the entire locked sequence is sampled asserted. SCYC is only
valid during locked memory cycles.
SCYC is floated off the clock edge on which BOFF# is sampled
asserted and off the clock edge on which the processor asserts
HLDA in response to HOLD.
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5.43
SMI# (System Management Interrupt)
Pin Attribute
Pin Location
Summary
Input, Internal Pullup
AB-34
The assertion of SMI# causes the processor to enter system
management mode (SMM). Upon recognizing SMI#, the
processor performs the following actions, in the order shown:
1. Flushes its instruction pipelines
2. Completes all pending and in-progress bus cycles
3. Acknowledges the interrupt by asserting SMIACT# after
sampling EWBE# asserted (if EWBE# is masked off, then
SMIACT# is not affected by EWBE#)
4. Saves the internal processor state in SMM memory
5. Disables interrupts by clearing the interrupt flag (IF) in
EFLAGS and disables NMI interrupts
6. Jumps to the entry point of the SMM service routine at the
SMM base physical address which defaults to 0003_8000h in
SMM memory
See “System Management Mode (SMM)” on page 217 for more
details regarding SMM.
Sampled
SMI# is sampled and latched as a falling edge-sensitive signal.
SMI# is sampled on every clock edge but is not recognized until
the next instruction boundary. If SMI# is to be recognized on
the instruction boundary associated with a BRDY#, it must be
sampled asserted a minimum of three clock edges before the
BRDY# is sampled asserted. If it is asserted synchronously, it
can be asserted for a minimum of one clock. If it is asserted
asynchronously, it must have been negated for a minimum of
two clocks followed by an assertion of a minimum of two clocks.
A second assertion of SMI# while in SMM is latched but is not
recognized until the SMM service routine is exited.
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5.44
SMIACT# (System Management Interrupt Active)
Pin Attribute
Pin Location
Summary
Output
AG-03
The processor acknowledges the assertion of SMI# with the
assertion of SMIACT# to indicate that the processor has
entered system management mode (SMM). The system logic
can use SMIACT# to enable SMM memory. See “SMI# (System
Management Interrupt)” on page 121 for more details.
See “System Management Mode (SMM)” on page 217 for more
details regarding SMM.
Driven
The processor asserts SMIACT# after the last BRDY# of the last
pending bus cycle is sampled asserted (including all pending
write cycles) and after EWBE# is sampled asserted (if EWBE#
is masked off, then SMIACT# is not affected by EWBE#).
SMIACT# remains asserted until after the last BRDY# of the
last pending bus cycle associated with exiting SMM is sampled
asserted.
SMIACT# remains asserted during any flush, internal snoop, or
writeback cycle due to an inquire cycle.
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5.45
STPCLK# (Stop Clock)
Pin Attribute
Pin Location
Summary
Input, Internal Pullup
V-34
The assertion of STPCLK# causes the processor to enter the
Stop Grant state, during which the processor’s internal clock is
stopped. From the Stop Grant state, the processor can
subsequently transition to the Stop Clock state, in which the
bus clock CLK is stopped. Upon recognizing STPCLK#, the
processor performs the following actions, in the order shown:
1. Flushes its instruction pipelines
2. Completes all pending and in-progress bus cycles
3. Acknowledges the STPCLK# assertion by executing a Stop
Grant special bus cycle (see Table 23 on page 132)
4. Stops its internal clock after BRDY# of the Stop Grant
special bus cycle is sampled asserted and after EWBE# is
sampled asserted (if EWBE# is masked off, then entry into
the Stop Grant state is not affected by EWBE#)
5. Enters the Stop Clock state if the system logic stops the bus
clock CLK (optional)
See “Clock Control States” on page 247 for more details
regarding clock control.
Sampled
STPCLK# is sampled as a level-sensitive input on every clock
edge but is not recognized until the next instruction boundary.
System logic can drive the signal either synchronously or
asynchronously. If it is asserted asynchronously, it must be
asserted for a minimum pulse width of two clocks.
STPCLK# must remain asserted until recognized, which is
indicated by the completion of the Stop Grant special cycle.
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5.46
TCK (Test Clock)
Pin Attribute
Pin Location
Summary
Input, Internal Pullup
M-34
TCK is the clock for boundary-scan testing using the Test
Access Port (TAP). See “Boundary-Scan Test Access Port
(TAP)” on page 229 for details regarding the operation of the
TAP controller.
Sampled
The processor always samples TCK, except while TRST# is
asserted.
5.47
TDI (Test Data Input)
Pin Attribute
Pin Location
Summary
Input, Internal Pullup
N-35
TDI is the serial test data and instruction input for
boundary-scan testing using the Test Access Port (TAP). See
“Boundary-Scan Test Access Port (TAP)” on page 229 for details
regarding the operation of the TAP controller.
Sampled
The processor samples TDI on every rising TCK edge, but only
while in the Shift-IR and Shift-DR states.
5.48
TDO (Test Data Output)
Pin Attribute
Pin Location
Summary
Output
N-33
TDO is the serial test data and instruction output for
boundary-scan testing using the Test Access Port (TAP). See
“Boundary-Scan Test Access Port (TAP)” on page 229 for details
regarding the operation of the TAP controller.
Driven and Floated
The processor drives TDO on every falling TCK edge, but only
while in the Shift-IR and Shift-DR states. TDO is floated at all
other times.
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5.49
TMS (Test Mode Select)
Pin Attribute
Pin Location
Summary
Input, Internal Pullup
P-34
TMS specifies the test function and sequence of state changes
for boundary-scan testing using the Test Access Port (TAP). See
“Boundary-Scan Test Access Port (TAP)” on page 229 for details
regarding the operation of the TAP controller.
Sampled
The processor samples TMS on every rising TCK edge. If TMS is
sampled High for five or more consecutive clocks, the TAP
controller enters its Test-Logic-Reset state, regardless of the
controller state. This action is the same as that achieved by
asserting TRST#.
5.50
TRST# (Test Reset)
Pin Attribute
Pin Location
Summary
Input, Internal Pullup
Q-33
The assertion of TRST# initializes the Test Access Port (TAP) by
resetting its state machine to the Test-Logic-Reset state. See
“Boundary-Scan Test Access Port (TAP)” on page 229 for details
regarding the operation of the TAP controller.
Sampled
TRST# is a completely asynchronous input that does not
require a minimum setup and hold time relative to TCK. See
Table 64 on page 280 for the minimum pulse width
requirement.
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5.51
VCC2DET (VCC2 Detect)
Pin Attribute
Pin Location
Summary
Output
AL-01
VCC2DET is internally tied to V (logic level 0) to indicate to
the system logic that it must supply the specified dual-voltage
SS
requirements to the V
and V
pins. The V
pins supply
CC2
CC3
CC2
voltage to the processor core, independent of the voltage
supplied to the I/O buffers on the V pins. Upon sampling
CC3
VCC2DET Low, system logic should sample VCC2H/L# to
identify core voltage requirements.
Driven
VCC2DET always equals 0 and is never floated—even during
the three-state test mode.
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5.52
VCC2H/L# (VCC2 High/Low)
Pin Attribute
Pin Location
Summary
Output
AN-05
VCC2H/L# is internally tied to V (logic level 0) to indicate to
the system logic that it must supply the specified processor core
SS
voltage to the V
pins. The V
pins supply voltage to the
CC2
CC2
processor core, independent of the voltage supplied to the I/O
buffers on the V pins.
CC3
Upon sampling VCC2DET Low to identify dual-voltage
processor requirements, system logic should sample VCC2H/L#
to identify the core voltage requirements for 2.9V and 3.2V
products (High) or 2.4 V, 2.2 V, and 1.9 V products (Low).
Driven
VCC2H/L# always equals 0 and is never floated for 2.4 V, 2.2 V,
and 1.9 V products—even during the three-state test mode. To
ensure proper operation for 2.9V and 3.2V products, system
logic that samples VCC2H/L# should design a weak pullup
resistor for this signal.
The output pin float conditions for VCC2DET and VCC2H/L#
are listed in Table 17.
Table 17. Output Pin Float Conditions
Name
Floated At:
VCC2DET1
Always Driven
VCC2H/L#
Always Driven
Notes:
1. All outputs except VCC2DET, VCC2H/L#, and TDO float during the three-state test mode.
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5.53
W/R# (Write/Read)
Pin Attribute
Pin Location
Summary
Output
AM-06
The processor drives W/R# to indicate whether it is performing
a write or a read cycle on the bus. In addition, W/R# is used to
define other bus cycles, including interrupt acknowledge and
special cycles. See Table 23 on page 132 for more details.
Driven and Floated
W/R# is driven off the same clock edge as ADS# and remains in
the same state until the clock edge on which NA# or the last
expected BRDY# of the cycle is sampled asserted. W/R# is
driven during memory cycles, I/O cycles, special bus cycles, and
interrupt acknowledge cycles.
W/R# is floated off the clock edge on which BOFF# is sampled
asserted and off the clock edge on which the processor asserts
HLDA in response to HOLD.
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5.54
WB/WT# (Writeback or Writethrough)
Pin Attribute
Pin Location
Summary
Input
AA-05
WB/WT#, together with PWT, specifies the data cache-line state
during cacheable read misses and write hits to shared cache
lines.
■ If WB/WT# = 0 or PWT = 1 during a cacheable read miss or
write hit to a shared cache line, the accessed line is cached
in the shared state. This is referred to as the writethrough
state, because all write cycles to this cache line are driven
externally on the bus.
■ If WB/WT# = 1 and PWT = 0 during a cacheable read miss or
a write hit to a shared cache line, the accessed line is cached
in the exclusive state. Subsequent write hits to the same line
cause its state to transition from exclusive to modified. This
is referred to as the writeback state, because the data cache
can contain modified cache lines that are subject to be
written back—referred to as a writeback cycle—as the result
of an inquire cycle, an internal snoop, a flush operation, or
the WBINVD instruction.
Sampled
WB/WT# is sampled on the clock edge on which the first BRDY#
or NA# of a bus cycle is sampled asserted. If the cycle is a burst
read, WB/WT# is ignored during the last three assertions of
BRDY#. WB/WT# is sampled during memory read and
non-writeback write cycles and is ignored during all other types
of cycles.
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5.55
Pin Tables by Type
Table 18. Input Pin Types
Name
A20M#1
Type
Name
IGNNE#1
INIT2
Type
Asynchronous
Asynchronous
Asynchronous
Asynchronous
AHOLD
Synchronous
Synchronous
BF[2:0]3
BOFF#
BRDY#
BRDYC#
CLK
INTR1
INV
Synchronous
Synchronous
Synchronous
Clock
Synchronous
Synchronous
Synchronous
Asynchronous
KEN#
NA#
NMI2
RESET4,5
SMI#2
EADS#
Synchronous
Synchronous
Asynchronous
Synchronous
Asynchronous
Asynchronous
Asynchronous
Synchronous
EWBE#6
FLUSH#2,7
HOLD
STPCLK#1
WB/WT#
Notes:
1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup
and hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.
2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup
and hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and
must remain asserted at least two clocks.
3. BF[2:0] are sampled during the falling transition of RESET. They must meet a minimum setup time of 1.0 ms and a minimum
hold time of two clocks relative to the negation of RESET.
4. During the initial power-on reset of the processor, RESET must remain asserted for a minimum of 1.0 ms after CLK and VCC
reach specification before it is negated.
5. During a warm reset, while CLK and VCC are within their specification, RESET must remain asserted for a minimum of 15 clocks
prior to its negation.
6. When EFER[3] is 1, EWBE# is ignored by the processor.
7. FLUSH# is also sampled during the falling transition of RESET and can be asserted synchronously or asynchronously. To be
sampled on a specific clock edge, setup and hold times must be met relative to the clock edge before the clock edge on which
RESET is sampled negated. If asserted asynchronously, FLUSH# must meet a minimum setup and hold time of two clocks
relative to the negation of RESET.
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Table 19. Output Pin Float Conditions
1
1
Name
Name
Floated At:
Floated At:
A[4:3]2,3
ADS#2
ADSC#2
APCHK#
HLDA, AHOLD, BOFF#
HLDA
Always Driven
HLDA, BOFF#
HLDA, BOFF#
HLDA, BOFF#
Always Driven
HLDA, BOFF#
HLDA, BOFF#
Always Driven
LOCK#2
M/IO#2
PCD2
HLDA, BOFF#
HLDA, BOFF#
Always Driven
HLDA, BOFF#
Always Driven
HLDA, BOFF#
HLDA, BOFF#
BE[7:0]#2
BREQ
PCHK#
PWT2
SCYC2
CACHE#2
D/C#2
FERR#
HIT#
SMIACT#
Always Driven
Always Driven
Always Driven
VCC2DET
Always Driven
Always Driven
HLDA, BOFF#
VCC2H/L#
W/R#2
HITM#
Notes:
1. All outputs except VCC2DET, VCC2H/L#, and TDO float during three-state test mode.
2. Floated off the clock edge that BOFF# is sampled asserted and off the clock edge that HLDA is asserted.
3. Floated off the clock edge that AHOLD is sampled asserted.
Table 20. Input/Output Pin Float Conditions
1
Name
Floated At:
A[31:5]2,3
AP2,3
D[63:0]2
DP[7:0]2
HLDA, AHOLD, BOFF#
HLDA, AHOLD, BOFF#
HLDA, BOFF#
HLDA, BOFF#
Notes:
1. All outputs except VCC2DET and TDO float during three-state test mode.
2. Floated off the clock edge that BOFF# is sampled asserted and off the clock edge that
HLDA is asserted.
3. Floated off the clock edge that AHOLD is sampled asserted.
Table 21. Test Pins
Name
TCK
Type
Clock
Input
Output
Input
Input
Comment
TDI
Sampled on the rising edge of TCK
Driven on the falling edge of TCK
Sampled on the rising edge of TCK
Asynchronous (Independent of TCK)
TDO
TMS
TRST#
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5.56
Bus Cycle Definitions
Table 22. Bus Cycle Definition
Generated
by System Logic
Generated by CPU
D/C# W/R# CACHE#
Bus Cycle Initiated
M/IO#
KEN#
Code Read, Instruction Cache Line Fill
Code Read, Noncacheable
Code Read, Noncacheable
Encoding for Special Cycle
Interrupt Acknowledge
1
1
1
0
0
0
0
0
1
0
1
x
0
x
0
0
0
1
x
1
0
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
0
0
1
0
0
0
1
1
1
1
1
0
1
x
x
x
x
0
x
1
x
x
I/O Read
I/O Write
Memory Read, Data Cache Line Fill
Memory Read, Noncacheable
Memory Read, Noncacheable
Memory Write, Data Cache Writeback
Memory Write, Noncacheable
0
1
Notes:
x means “don’t care”.
Table 23. Special Cycles
Special Cycle
Stop Grant
1
0
1
1
1
1
1
1
1
0
1
0
1
1
1
1
0
0
0
0
1
1
1
1
x
x
Flush Acknowledge
(FLUSH# sampled asserted)
1
1
Writeback (WBINVD
instruction)
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
x
x
x
x
Halt
Flush (INVD, WBINVD
instruction)
Shutdown
Notes:
x means “don’t care”.
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6
Bus Cycles
The following sections describe and illustrate the timing and
relationship of bus signals during various types of bus cycles. A
representative set of bus cycles is illustrated.
6.1
Timing Diagrams
The timing diagrams illustrate the signals on the external local
bus as a function of time, as measured by the bus clock (CLK).
Bus Clock (CLK)
Throughout this chapter, the term clock refers to a single
bus-clock cycle. A clock extends from one rising CLK edge to
the next rising CLK edge. The processor samples and drives
most signals relative to the rising edge of CLK. The exceptions
to this rule include the following:
■ BF[2:0]—Sampled on the falling edge of RESET
■ FLUSH#—Sampled on the falling edge of RESET, also
sampled on the rising edge of CLK
■ All inputs and outputs are sampled relative to TCK in
boundary-scan test mode. Inputs are sampled on the rising
edge of TCK, outputs are driven off of the falling edge of
TCK.
Waveform
Definitions
For each signal in the timing diagrams, the High level
represents 1, the Low level represents 0, and the Middle level
represents the floating (high-impedance) state.
When both the High and Low levels are shown, the meaning
depends on the signal:
■ A single signal indicates ‘don’t care’.
■ In the case of bus activity, if both High and Low levels are
shown, it indicates that the processor, alternate master, or
system logic is driving a value, but this value may or may not
be valid. (For example, the value on the address bus is valid
only during the assertion of ADS#, but addresses are also
driven on the bus at other times.)
Figure 50 defines the different waveform representations.
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Active High Signals
Active Low Signals
For all active High signals, the term asserted means the signal is
in the High-voltage state and the term negated means the signal
is in the Low-voltage state.
For all active Low signals, the term asserted means the signal is
in the Low-voltage state and the term negated means the signal
is in the High-voltage state.
Waveform
Description
Don’t care or bus is driven
Signal or bus is changing from Low to High
Signal or bus is changing from High to Low
Bus is changing
Bus is changing from valid to invalid
Signal or bus is floating
Denotes multiple clock periods
Figure 50. Waveform Definitions
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6.2
Bus States
Bus State
Branch Condition
Addr
Yes
No
Pending
Request?
Address
Data
Data
Idle
Idle
No
Yes
Yes
No
Last BRDY#
Asserted?
NA# Sampled
Asserted?
Yes
Data-NA#
Data-NA#
Requested
Last BRDY#
Asserted?
No
Yes
Pending
Request?
No
No
NA# Sampled
Asserted?
Yes
Pipe-A
Pipeline
Address
Pipe-D
Trans
Pipeline
Data
No
Yes
Last BRDY#
Asserted?
Yes
Yes
No
NA# Sampled
Asserted?
Transition
Bus Transition?
No
Note: The processor transitions to the IDLE state on the clock edge on which BOFF# or RESET is sampled asserted.
Figure 51. Bus State Machine Diagram
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Idle
The processor does not drive the system bus in the Idle state
and remains in this state until a new bus cycle is requested. The
processor enters this state off the clock edge on which the last
BRDY# of a cycle is sampled asserted during the following
conditions:
■ The processor is in the Data state
■ The processor is in the Data-NA# Requested state and no
internal pending cycle is requested
In addition, the processor is forced into this state when the
system logic asserts RESET or BOFF#. The transition to this
state occurs on the clock edge on which RESET or BOFF# is
sampled asserted.
Address
Data
In this state, the processor drives ADS# to indicate the
beginning of a new bus cycle by validating the address and
control signals. The processor remains in this state for one clock
and unconditionally enters the Data state on the next clock
edge.
In the Data state, the processor drives the data bus during a
write cycle or expects data to be returned during a read cycle.
The processor remains in this state until either NA# or the last
BRDY# is sampled asserted. If the last BRDY# is sampled
asserted or both the last BRDY# and NA# are sampled asserted
on the same clock edge, the processor enters the Idle state. If
NA# is sampled asserted first, the processor enters the
Data-NA# Requested state.
Data-NA# Requested
If the processor samples NA# asserted while in the Data state
and the current bus cycle is not completed (the last BRDY# is
not sampled asserted), it enters the Data-NA# Requested state.
The processor remains in this state until either the last BRDY#
is sampled asserted or an internal pending cycle is requested. If
the last BRDY# is sampled asserted before the processor drives
a new bus cycle, the processor enters the Idle state (no internal
pending cycle is requested) or the Address state (processor has
a internal pending cycle).
In this state, the processor drives ADS# to indicate the
beginning of a new bus cycle by validating the address and
control signals. In this state, the processor is still waiting for the
current bus cycle to be completed (until the last BRDY# is
Pipeline Address
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sampled asserted). If the last BRDY# is not sampled asserted,
the processor enters the Pipeline Data state.
If the processor samples the last BRDY# asserted in this state, it
determines if a bus transition is required between the current
bus cycle and the pipelined bus cycle. A bus transition is
required when the data bus direction changes between bus
cycles, such as a memory write cycle followed by a memory read
cycle. If a bus transition is required, the processor enters the
Transition state for one clock to prevent data bus contention. If
a bus transition is not required, the processor enters the Data
state.
The processor does not transition to the Data-NA# Requested
state from the Pipeline Address state because the processor
does not begin sampling NA# until it has exited the Pipeline
Address state.
Pipeline Data
Two bus cycles are executing concurrently in this state. The
processor cannot issue any additional bus cycles until the
current bus cycle is completed. The processor drives the data
bus during write cycles or expects data to be returned during
read cycles for the current bus cycle until the last BRDY# of the
current bus cycle is sampled asserted.
If the processor samples the last BRDY# asserted in this state, it
determines if a bus transition is required between the current
bus cycle and the pipelined bus cycle. If the bus transition is
required, the processor enters the Transition state for one clock
to prevent data bus contention. If a bus transition is not
required, the processor enters the Data state (NA# was not
sampled asserted) or the Data-NA# Requested state (NA# was
sampled asserted).
Transition
The processor enters the Transition state for one clock during
data bus transitions and enters the Data state on the next clock
edge if NA# is not sampled asserted. The sole purpose of this
state is to avoid bus contention caused by bus transitions during
pipeline operation.
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6.3
Memory Reads and Writes
The AMD-K6-2E processor performs single or burst memory bus
cycles.
■ The single-transfer memory bus cycle transfers 1, 2, 4, or 8
bytes and requires a minimum of two clocks.
■ Misaligned instructions or operands result in a split cycle,
which requires multiple transactions on the bus.
■ A burst cycle consists of four back-to-back 8-byte (64-bit)
transfers on the data bus.
Single-Transfer
Memory Read and
Write
Figure 52 on page 139 shows a single-transfer read from memory,
followed by two single-transfer writes to memory. For the
memory read cycle, the processor asserts ADS# for one clock to
validate the bus cycle and also drives A[31:3], BE[7:0]#, D/C#,
W/R#, and M/IO# to the bus. The processor then waits for the
system logic to return the data on D[63:0] (with DP[7:0] for
parity checking) and assert BRDY#. The processor samples
BRDY# on every clock edge starting with the clock edge after
the clock edge that negates ADS#. See “BRDY# (Burst Ready)”
on page 95.
During the read cycle, the processor drives PCD, PWT, and
CACHE# to indicate its caching and cache-coherency intent for
the access. The system logic returns KEN# and WB/WT# to
either confirm or change this intent. If the processor asserts
PCD and negates CACHE#, the accesses are noncacheable, even
though the system logic asserts KEN# during the BRDY# to
indicate its support for cacheability. The processor (which
drives CACHE#) and the system logic (which drives KEN#) must
agree in order for an access to be cacheable.
The processor can drive another cycle (in this example, a write
cycle) by asserting ADS# off the next clock edge after BRDY# is
sampled asserted. Therefore, an idle clock is guaranteed
between any two bus cycles. The processor drives D[63:0] with
valid data one clock edge after the clock edge on which ADS# is
asserted. To minimize processor idle times, the system logic
stores the address and data in write buffers, returns BRDY#, and
performs the store to memory later. If the processor samples
EWBE# negated during a write cycle, it suspends certain
activities until EWBE# is sampled asserted. See “EWBE#
(External Write Buffer Empty)” on page 102. In Figure 52, the
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second write cycle occurs during the execution of a serializing
instruction. The processor delays the following cycle until
EWBE# is sampled asserted.
Write Cycle (Next Cycle Delayed by EWBE#)
Write Cycle
Read Cycle
DATA IDLE ADDR DATA
ADDR DATA IDLE ADDR DATA
DATA IDLE
IDLE
IDLE
IDLE ADDR
IDLE
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
BREQ
D[63:0]
DP[7:0]
CACHE#
EWBE#
KEN#
BRDY#
WB/WT#
Figure 52. Non-Pipelined Single-Transfer Memory Read/Write and Write Delayed by EWBE#
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Misaligned
Figure 53 on page 141 shows a misaligned (split) memory read
followed by a misaligned memory write. Any cycle that is not
aligned as defined in “SCYC (Split Cycle)” on page 120 is
considered misaligned. When the processor encounters a
misaligned access, it determines the appropriate pair of bus
cycles—each with its own ADS# and BRDY#— required to
complete the access.
Single-Transfer
Memory Read and
Write
The AMD-K6-2E processor performs misaligned memory reads
and memory writes using least-significant bytes (LSBs) first
followed by most-significant bytes (MSBs). Table 24 shows the
order. In the first memory read cycle in Figure 53, the processor
reads the least-significant bytes. Immediately after the
processor samples BRDY# asserted, it drives the second bus
cycle to read the most-significant bytes to complete the
misaligned transfer.
Table 24. Bus-Cycle Order During Misaligned Memory Transfers
Type of Access
Memory Read
Memory Write
First Cycle
LSBs
Second Cycle
MSBs
LSBs
MSBs
Similarly, the misaligned memory write cycle in Figure 53
transfers the LSBs to the memory bus first. In the next cycle,
after the processor samples BRDY# asserted, the MSBs are
written to the memory bus.
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Memory Write (Misaligned)
Memory Read (Misaligned)
DATA IDLE ADDR DATA
DATA IDLE
DATA
ADDR DATA DATA DATA IDLE
DATA IDLE ADDR DATA
ADDR DATA
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
LSB
MSB
LSB
MSB
D[63:0]
BRDY#
Figure 53. Misaligned Single-Transfer Memory Read and Write
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Burst Reads and
Pipelined Burst Reads
Figure 54 on page 143 shows normal burst read cycles and a
pipelined burst read cycle. The AMD-K6-2E processor drives
CACHE# and ADS# together to specify that the current bus
cycle is a burst cycle. If the processor samples KEN# asserted
with the first BRDY#, it performs burst transfers. During the
burst transfers, the system logic must ignore BE[7:0]# and must
return all eight bytes beginning at the starting address the
processor asserts on A[31:3]. Depending on the starting
address, the system logic must determine the successive
quadword addresses (A[4:3]) for each transfer in a burst, as
shown in Table 25. The processor expects the second, third, and
fourth quadwords to occur in the sequences shown in Table 25.
Table 25. A[4:3] Address-Generation Sequence During Bursts
A[4:3] Addresses of Subsequent
Quadwords Generated by System Logic
Address Driven By
Processor on A[4:3]
1
Quadword 1
Quadword 2
Quadword 3
Quadword 4
00b
01b
10b
11b
01b
00b
11b
10b
10b
11b
00b
01b
11b
10b
01b
00b
Notes:
1. quadword = 8 bytes
In Figure 54, the processor drives CACHE# throughout all burst
read cycles. In the first burst read cycle, the processor drives
ADS# and CACHE#, then samples BRDY# on every clock edge
starting with the clock edge after the clock edge that negates
ADS#. The processor samples KEN# asserted on the clock edge
on which the first BRDY# is sampled asserted, executes a
32-byte burst read cycle, and expects a total of four BRDY#
signals. An ideal no-wait state access is shown in Figure 54,
whereas most system logic solutions add wait states between
the transfers.
The second burst read cycle illustrates a similar sequence, but
the processor samples NA# asserted on the same clock edge
that the first BRDY# is sampled asserted. NA# assertion
indicates the system logic is requesting the processor to output
the next address early (also known as a pipeline transfer
request). Without waiting for the current cycle to complete, the
processor drives ADS# and related signals for the next burst
cycle. Pipelining can reduce processor cycle-to-cycle idle times.
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Burst Read
Burst Read
Pipelined Burst Read
DATA PIPE
ADDR DATA DATA DATA DATA IDLE ADDR DATA DATA
DATA DATA DATA DATA IDLE
-NA -ADDR
CLK
ADDR1
ADDR2
ADDR3
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
NA#
DATA1
DATA2
DATA3
D[63:0]
CACHE#
KEN#
BRDY#
Figure 54. Burst Reads and Pipelined Burst Reads
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Burst Writeback
Figure 55 on page 145 shows a burst read followed by a
writeback transaction. The AMD-K6-2E processor initiates
writebacks under the following conditions:
■ Replacement—If a cache-line fill is initiated for a cache line
currently filled with valid entries, the processor selects a
line for replacement based on a least-recently-used (LRU)
algorithm
for
the
instruction
cache,
and
a
least-recently-allocated (LRA) algorithm for the data cache.
Before a replacement is made to an L1 data cache line that is
in the Modified state, the modified line is scheduled to be
written back to memory.
■ Internal Snoop—The processor snoops its instruction cache
during read or write misses to its data cache, and it snoops
its data cache during read misses to its instruction cache.
This snooping is performed to determine whether the same
address is stored in both caches, a situation that implies the
occurrence of self-modifying code. If a snoop hits a data
cache line in the Modified state, the line is written back to
memory before being invalidated.
■ WBINVD Instruction—When the processor executes a
WBINVD instruction, it writes back all modified lines in the
data cache and then invalidates all lines in both caches.
■ Cache Flush—When the processor samples FLUSH#
asserted, it executes a flush acknowledge special cycle and
writes back all modified lines in the data cache and then
invalidates all lines in both caches.
The processor drives writeback cycles during inquire or cache
flush cycles. The writeback shown in Figure 55 is caused by a
cache-line replacement. The processor completes the burst read
cycle that fills the cache line. Immediately following the burst
read cycle is the burst writeback cycle that represents the
modified line to be written back to memory. D[63:0] are driven
one clock edge after the clock edge on which ADS# is asserted
and are subsequently changed off the clock edge on which each
of the four BRDY# signals of the burst cycle are sampled
asserted.
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Burst Read
Burst Writeback from L1 Cache
DATA
DATA DATA
DATA
DATA DATA
ADDR
DATA
IDLE
ADDR
DATA
IDLE
CLK
A[31:3]
BE[7:0]#
ADS#
CACHE#
M/IO#
D/C#
W/R#
D[63:0]
KEN#
BRDY#
WB/WT#
Figure 55. Burst Writeback due to Cache-Line Replacement
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6.4
I/O Read and Write
Basic I/O Read and
Write
The processor accesses I/O when it executes an I/O instruction
(for example, IN or OUT). Figure 56 shows an I/O read followed
by an I/O write. The processor drives M/IO# Low and D/C# High
during I/O cycles. In this example, the first cycle shows a single
wait state I/O read cycle. It follows the same sequence as a
single-transfer memory read cycle. The processor drives ADS#
to initiate the bus cycle, then it samples BRDY# on every clock
edge starting with the clock edge after the clock edge that
negates ADS#. The system logic must return BRDY# to
complete the cycle. When the processor samples BRDY#
asserted, it can assert ADS# for the next cycle off the next clock
edge. (In this example, an I/O write cycle.)
The I/O write cycle is similar to a memory write cycle, but the
processor drives M/IO# low during an I/O write cycle. The
processor asserts ADS# to initiate the bus cycle. The processor
drives D[63:0] with valid data one clock edge after the clock
edge on which ADS# is asserted. The system logic must assert
BRDY# when the data is properly stored to the I/O destination.
The processor samples BRDY# on every clock edge starting with
the clock edge after the clock edge that negates ADS#. In this
example, two wait states are inserted while the processor waits
for BRDY# to be asserted.
I/O Write Cycle
I/O Read Cycle
DATA
IDLE
IDLE
DATA
DATA
DATA
DATA
ADDR
ADDR
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
D[63:0]
BRDY#
Figure 56. Basic I/O Read and Write
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Misaligned I/O Read
and Write
Table 26 shows the misaligned I/O read and write cycle order
executed by the AMD-K6-2E processor. In Figure 57, the
least-significant bytes (LSBs) are transferred first. Immediately
after the processor samples BRDY# asserted, it drives the
second bus cycle to transfer the most-significant bytes (MSBs)
to complete the misaligned bus cycle.
Table 26. Bus-Cycle Order During Misaligned I/O Transfers
Type of Access
I/O Read
First Cycle
LSBs
Second Cycle
MSBs
I/O Write
LSBs
MSBs
Misaligned I/O Write
Misaligned I/O Read
ADDR DATA DATA IDLE ADDR DATA DATA IDLE ADDR DATA
DATA
IDLE ADDR DATA DATA DATA IDLE
DATA
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
SCYC
D[63:0]
BRDY#
LSB
MSB
LSB
MSB
Figure 57. Misaligned I/O Transfer
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6.5
Inquire and Bus Arbitration Cycles
The AMD-K6-2E processor provides built-in level-one data and
instruction caches. Each cache is 32 Kbytes and two-way
set-associative. The system logic or other bus master devices
can initiate an inquire cycle to maintain cache/memory
coherency. In response to the inquire cycle, the processor
compares the inquire address with its cache tag addresses in
both caches, and, if necessary, updates the MESI state of the
cache line and performs writebacks to memory.
An inquire cycle can be initiated by asserting AHOLD, BOFF#,
or HOLD. AHOLD is exclusively used to support inquire cycles.
During AHOLD-initiated inquire cycles, the processor only
floats the address bus. BOFF# provides the fastest access to the
bus because it aborts any processor cycle that is in-progress,
whereas AHOLD and HOLD both permit an in-progress bus
cycle to complete. During HOLD-initiated and BOFF#-initiated
inquire cycles, the processor floats all of its bus-driving signals.
Hold and Hold
Acknowledge Cycle
The system logic or another bus device can assert HOLD to
initiate an inquire cycle or to gain full control of the bus. When
the AMD-K6-2E processor samples HOLD asserted, it
completes any in-progress bus cycle and asserts HLDA to
acknowledge release of the bus. The processor floats the
following signals off the same clock edge on which HLDA is
asserted:
■ A[31:3]
■ ADS#
■ DP[7:0]
■ LOCK#
■ M/IO#
■ PCD
■ AP#
■ BE[7:0]#
■ CACHE#
■ D[63:0]
■ D/C#
■ PWT
■ SCYC
■ W/R#
Figure 58 shows a basic HOLD/HLDA operation. In this
example, the processor samples HOLD asserted during the
memory read cycle. It continues the current memory read cycle
until BRDY# is sampled asserted. The processor drives HLDA
and floats its outputs one clock edge after the last BRDY# of the
cycle is sampled asserted. The system logic can assert HOLD for
as long as it needs to utilize the bus. The processor samples
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HOLD on every clock edge but does not assert HLDA until any
in-progress cycle or sequence of locked cycles is completed.
When the processor samples HOLD negated during a hold
acknowledge cycle, it negates HLDA off the next clock edge.
The processor regains control of the bus and can assert ADS#
off the same clock edge on which HLDA is negated.
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
D[63:0]
HOLD
HLDA
BRDY#
Figure 58. Basic HOLD/HLDA Operation
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HOLD-Initiated
Inquire Hit to Shared
or Exclusive Line
Figure 59 on page 151 shows a HOLD-initiated inquire cycle. In
this example, the processor samples HOLD asserted during the
burst memory read cycle. The processor completes the current
cycle (until the last expected BRDY# is sampled asserted),
asserts HLDA, and floats its outputs as described on “Hold and
Hold Acknowledge Cycle” on page 148.
The system logic drives an inquire cycle within the hold
acknowledge cycle. It asserts EADS#, which validates the
inquire address on A[31:5]. If EADS# is sampled asserted
before HOLD is sampled negated, the processor recognizes it as
a valid inquire cycle.
In Figure 59, the processor asserts HIT# and negates HITM# on
the clock edge after the clock edge on which EADS# is sampled
asserted, indicating the current inquire cycle hit a shared or
exclusive cache line. (Shared and exclusive cache lines have not
been modified and do not need to be written back.) During an
inquire cycle, the processor samples INV to determine whether
the addressed cache line found in the processor’s instruction or
data cache transitions to the Invalid state or the Shared state.
In this example, the processor samples INV asserted with
EADS#, which invalidates the cache line.
The system logic can negate HOLD off the same clock edge on
which EADS# is sampled asserted. The processor continues
driving HIT# in the same state until the next inquire cycle.
HITM# is not asserted unless HIT# is asserted.
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Burst Memory Read
Inquire
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
HIT#
HITM#
D[63:0]
KEN#
BRDY#
HOLD
HLDA
EADS#
INV
Figure 59. HOLD-Initiated Inquire Hit to Shared or Exclusive Line
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HOLD-Initiated
Inquire Hit to
Modified Line
Figure 60 on page 153 shows the same sequence as Figure 59,
but in Figure 60, the inquire cycle hits a modified line and the
processor asserts both HIT# and HITM#. In this example, the
processor performs a writeback cycle immediately after the
inquire cycle. It updates the modified cache line to the external
memory (normally, external cache or DRAM). The processor
uses the address (A[31:5]) that was latched during the inquire
cycle to perform the writeback cycle. The processor asserts
HITM# throughout the writeback cycle and negates HITM# one
clock edge after the last expected BRDY# of the writeback is
sampled asserted.
When the processor samples EADS# during the inquire cycle, it
also samples INV to determine the cache line MESI state after
the inquire cycle. If INV is sampled asserted during an inquire
cycle, the processor transitions the line (if found) to the Invalid
state, regardless of its previous state. The cache line
invalidation operation is not visible on the bus. If INV is
sampled negated during an inquire cycle, the processor
transitions the line (if found) to the Shared state. In Figure 60
the processor samples INV asserted during the inquire cycle.
In a HOLD-initiated inquire cycle, the system logic can negate
HOLD off the same clock edge on which EADS# is sampled
asserted. The processor drives HIT# and HITM# on the clock
edge after the clock edge on which EADS# is sampled asserted.
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Burst Memory Read
Writeback Cycle
Inquire
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
HIT#
HITM#
D[63:0]
KEN#
BRDY#
HOLD
HLDA
EADS#
INV
Figure 60. HOLD-Initiated Inquire Hit to Modified Line
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AHOLD-Initiated
Inquire Miss
AHOLD can be asserted by the system to initiate one or more
inquire cycles. To allow the system to drive the address bus
during an inquire cycle, the processor floats A[31:3] and AP off
the clock edge on which AHOLD is sampled asserted. The data
bus and all other control and status signals remain under the
control of the processor and are not floated. This functionality
allows a bus cycle in progress when AHOLD is sampled asserted
to continue to completion. The processor resumes driving the
address bus off the clock edge on which AHOLD is sampled
negated.
In Figure 61 on page 155, the processor samples AHOLD
asserted during the memory burst read cycle, and it floats the
address bus off the same clock edge on which it samples AHOLD
asserted. While the processor still controls the bus, it completes
the current cycle until the last expected BRDY# is sampled
asserted. The system logic drives EADS# with an inquire
address on A[31:5] during an inquire cycle. The processor
samples EADS# asserted and compares the inquire address to
its tag address in both the instruction and data caches. In Figure
61, the inquire address misses the tag address in the processor
(both HIT# and HITM# are negated). Therefore, the processor
proceeds to the next cycle when it samples AHOLD negated.
(The processor can drive a new cycle by asserting ADS# off the
same clock edge that it samples AHOLD negated.)
For an AHOLD-initiated inquire cycle to be recognized, the
processor must sample AHOLD asserted for at least two
consecutive clocks before it samples EADS# asserted. If the
processor detects an address parity error during an inquire
cycle, APCHK# is asserted for one clock. The system logic must
respond appropriately to the assertion of this signal.
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Inquire
Read
CLK
A[31:3]
BE[7:0]#
AP
APCHK#
ADS#
HIT#
HITM#
D[63:0]
KEN#
BRDY#
AHOLD
EADS#
INV
Figure 61. AHOLD-Initiated Inquire Miss
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AHOLD-Initiated
Inquire Hit to Shared
or Exclusive Line
In Figure 62, the processor asserts HIT# and negates HITM# off
the clock edge after the clock edge on which EADS# is sampled
asserted, indicating the current inquire cycle hits either a
shared or exclusive line. (HIT# is driven in the same state until
the next inquire cycle.) The processor samples INV asserted
during the inquire cycle and transitions the line to the Invalid
state regardless of its previous state.
During an AHOLD-initiated inquire cycle, the processor
samples AHOLD on every clock edge until it is negated. In
Figure 62, the processor asserts ADS# off the same clock on
which AHOLD is sampled negated. If the inquire cycle hits a
modified line, the processor performs a writeback cycle before
it drives a new bus cycle. The next section describes the
AHOLD-initiated inquire cycle that hits a modified line.
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Inquire
Burst Memory Read
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
HIT#
HITM#
D[63:0]
KEN#
BRDY#
AHOLD
EADS#
INV
Figure 62. AHOLD-Initiated Inquire Hit to Shared or Exclusive Line
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AHOLD-Initiated
Inquire Hit to
Modified Line
Figure 63 on page 159 shows an AHOLD-initiated inquire cycle
that hits a modified line. During the inquire cycle in this
example, the processor asserts both HIT# and HITM# on the
clock edge after the clock edge that it samples EADS# asserted.
This condition indicates that the cache line exists in the
processor’s data cache in the Modified state.
If the inquire cycle hits a modified line, the processor performs
a writeback cycle immediately after the inquire cycle to update
the modified cache line to shared memory (normally external
cache or DRAM). In Figure 63, the system logic holds AHOLD
asserted throughout the inquire cycle and the processor
writeback cycle. In this case, the processor is not driving the
address bus during the writeback cycle because AHOLD is
sampled asserted. The system logic writes the data to memory
by using its latched copy of the inquire cycle address. If the
processor samples AHOLD negated before it performs the
writeback cycle, it drives the writeback cycle by using the
address (A[31:5]) that it latched during the inquire cycle.
If INV is sampled asserted during an inquire cycle, the
processor transitions the line (if found) to the Invalid state,
regardless of its previous state (the cache invalidation
operation is not visible on the bus). If INV is sampled negated
during an inquire cycle, the processor transitions the line (if
found) to the Shared state. In either case, if the line is found in
the Modified state, the processor writes it back to memory
before changing its state. Figure 63 shows that the processor
samples INV asserted during the inquire cycle and invalidates
the cache line after the inquire cycle.
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Burst Memory Read
Inquire
Writeback
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
HIT#
HITM#
D[63:0]
KEN#
BRDY#
AHOLD
EADS#
INV
Figure 63. AHOLD-Initiated Inquire Hit to Modified Line
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AHOLD Restriction
When the system logic drives an AHOLD-initiated inquire
cycle, it must assert AHOLD for at least two clocks before it
asserts EADS#. This requirement guarantees the processor
recognizes and responds to the inquire cycle properly. The
processor’s 32 address bus drivers turn on almost immediately
after AHOLD is sampled negated. If the processor switches the
data bus (D[63:0] and DP[7:0]) during a write cycle off the same
clock edge that switches the address bus (A[31:3] and AP), the
processor switches 102 drivers simultaneously, which can lead
to ground-bounce spikes. Therefore, before negating AHOLD,
the following restrictions must be observed by the system logic:
■ When the system logic negates AHOLD during a write cycle,
it must ensure that AHOLD is not sampled negated on the
clock edge on which BRDY# is sampled asserted (See Figure
64 on page 161).
■ When the system logic negates AHOLD during a writeback
cycle, it must ensure that AHOLD is not sampled negated on
the clock edge on which ADS# is negated (See Figure 64).
■ When a write cycle is pipelined into a read cycle, AHOLD
must not be sampled negated on the clock edge after the
clock edge on which the last BRDY# of the read cycle is
sampled asserted. This avoids the processor simultaneously
driving the data bus (for the pending write cycle) and the
address bus off this same clock edge.
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CLK
ADS#
W/R#
HITM#
EADS#
D[63:0]
BRDY#
Legal AHOLD negation during write cycle
AHOLD
Illegal AHOLD negation during write cycle
The system must ensure that AHOLD is not sampled negated on the clock edge that ADS# is negated.
The system must ensure that AHOLD is not sampled negated on the clock edge on which BRDY# is sampled asserted.
Figure 64. AHOLD Restriction
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Bus Backoff (BOFF#)
BOFF# provides the fastest response among bus-hold inputs.
Either the system logic or another bus master can assert BOFF#
to gain control of the bus immediately. BOFF# is also used to
resolve potential deadlock problems that arise as a result of
inquire cycles. The processor samples BOFF# on every clock
edge. If BOFF# is sampled asserted, the processor
unconditionally aborts any cycles in progress and transitions to
a Bus Hold state. (See “BOFF# (Backoff)” on page 94.) Figure
65 on page 163 shows a read cycle that is aborted when the
processor samples BOFF# asserted even though BRDY# is
sampled asserted on the same clock edge. The read cycle is
restarted after BOFF# is sampled negated (KEN# must be in
the same state during the restarted cycle as its state during the
aborted cycle).
During a BOFF#-initiated inquire cycle that hits a shared or
exclusive line, the processor samples BOFF# negated and
restarts any bus cycle that was aborted when BOFF# was
asserted. If a BOFF#-initiated inquire cycle hits a modified line,
the processor performs a writeback cycle before it restarts the
aborted cycle.
If the processor samples BOFF# asserted on the same clock
edge that it asserts ADS#, ADS# is floated but the system logic
may erroneously interpret ADS# as asserted. In this case, the
system logic must properly interpret the state of ADS# when
BOFF# is negated.
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Read
Restart Read Cycle
Backoff Cycle
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
BOFF#
D[63:0]
BRDY#
Figure 65. BOFF# Timing
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Locked Cycles
The processor asserts LOCK# during a sequence of bus cycles to
ensure the cycles are completed without allowing other bus
masters to intervene. Locked operations can consist of two to
five cycles. LOCK# is asserted during the following operations:
■ An interrupt acknowledge sequence
■ Descriptor Table accesses
■ Page Directory and Page Table accesses
■ XCHG instruction
■ An instruction with an allowable LOCK prefix
In order to ensure that locked operations appear on the bus and
are visible to the entire system, any data operands addressed
during a locked cycle that reside in the processor’s cache are
flushed and invalidated from the cache prior to the locked
operation. If the cache line is in the Modified state, it is written
back and invalidated prior to the locked operation. Likewise,
any data read during a locked operation is not cached. The
processor negates LOCK# for at least one clock between
consecutive sequences of locked operations to allow the system
logic to arbitrate for the bus.
The processor asserts SCYC during misaligned locked transfers
on the D[63:0] data bus. The processor generates additional bus
cycles to complete the transfer of misaligned data.
Basic Locked
Operation
Figure 66 on page 165 shows a pair of read-write bus cycles. It
represents a typical read-modify-write locked operation. The
processor asserts LOCK# off the same clock edge that it asserts
ADS# of the first bus cycle in the locked operation and holds it
asserted until the last expected BRDY# of the last bus cycle in
the locked operation is sampled asserted. (The processor
negates LOCK# off of the same clock edge.)
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Locked Write Cycle
Locked Read Cycle
ADDR
IDLE IDLE
IDLE IDLE ADDR DATA DATA DATA
ADDR DATA DATA DATA
CLK
A[31:3]
BE[7:0]#
ADS#
LOCK#
M/IO#
D/C#
W/R#
SCYC
D[63:0]
BRDY#
Figure 66. Basic Locked Operation
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Locked Operation
with BOFF#
Intervention
Figure 67 on page 167 shows BOFF# asserted within a locked
read-write pair of bus cycles. In this example, the processor
asserts LOCK# with ADS# to drive a locked memory read cycle
followed by a locked memory write cycle. During the locked
memory write cycle in this example, the processor samples
BOFF# asserted. The processor immediately aborts the locked
memory write cycle and floats all its bus-driving signals,
including LOCK#. The system logic or another bus master can
initiate an inquire cycle or drive a new bus cycle one clock edge
after the clock edge on which BOFF# is sampled asserted. If the
system logic drives a BOFF#-initiated inquire cycle and hits a
modified line, the processor performs a writeback cycle before
it restarts the locked cycle (the processor asserts LOCK# during
the writeback cycle).
In Figure 67, the processor immediately restarts the aborted
locked write cycle by driving the bus off the clock edge on
which BOFF# is sampled negated. The system logic must ensure
the processor results for interrupted and uninterrupted locked
cycles are consistent. That is, the system logic must guarantee
the memory accessed by the processor is not modified during
the time another bus master controls the bus.
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Locked Read Cycle
Restart Write Cycle
Aborted Write Cycle
CLK
A[31:3]
BE[7:0]#
ADS#
LOCK#
M/IO#
D/C#
W/R#
BOFF#
D[63:0]
BRDY#
Figure 67. Locked Operation with BOFF# Intervention
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Interrupt
Acknowledge
In response to recognizing the system’s maskable interrupt
(INTR), the processor drives an interrupt acknowledge cycle at
the next instruction boundary. During an interrupt
acknowledge cycle, the processor drives a locked pair of read
cycles as shown in Figure 68 on page 169. The first read cycle is
not functional, and the second read cycle returns the interrupt
number on D[7:0] (00h–FFh). Table 27 shows the state of the
signals during an interrupt acknowledge cycle.
Table 27. Interrupt Acknowledge Operation Definition
Processor
First Bus Cycle
Second Bus Cycle
Outputs
D/C#
Low
Low
M/IO#
W/R#
Low
Low
Low
Low
BE[7:0]#
A[31:3]
D[63:0]
EFh
FEh (low byte enabled)
0000_0000h
0000_0000h
(ignored)
Interrupt number expected from interrupt controller
on D[7:0]
The system logic can drive INTR either synchronously or
asynchronously. If it is asserted asynchronously, it must be
asserted for a minimum pulse width of two clocks. To ensure it
is recognized, INTR must remain asserted until an interrupt
acknowledge sequence is complete.
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Interrupt Acknowledge Cycles
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
LOCK#
INTR
Interrupt Number
D[63:0]
KEN#
BRDY#
Figure 68. Interrupt Acknowledge Operation
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6.6
Special Bus Cycles
The AMD-K6-2E processor drives special bus cycles that
include the following:
■ Stop grant
■ Flush acknowledge
■ Cache writeback invalidation
■ Halt
■ Cache invalidation
■ Shutdown
During all special cycles, D/C# = 0, M/IO# = 0, and W/R# = 1.
BE[7:0]# and A[31:3] are driven to differentiate among the
special cycles, as shown in Table 28. (See also Table 23 on
page 132.)
Note that the system logic must return BRDY# in response to all
processor special cycles.
Table 28. Encodings for Special Bus Cycles
1
BE[7:0]#
FBh
Special Bus Cycle
Stop Grant
Flush Acknowledge
Writeback
Cause
A[4:3]
10b
STPCLK# sampled asserted
FLUSH# sampled asserted
WBINVD instruction
HLT instruction
EFh
00b
F7h
00b
FBh
00b
Halt
FDh
00b
Flush
INVD,WBINVD instruction
Triple fault
FEh
00b
Shutdown
Notes:
1. A[31:5] = 0
Basic Special Bus
Cycle
Figure 69 on page 171 shows a basic special bus cycle.
The processor drives D/C# = 0, M/IO# = 0, and W/R# = 1 off the
same clock edge that it asserts ADS#.
In this example, BE[7:0]# = FBh and A[31:3] = 0000_0000h,
which indicates that the special cycle is a halt special cycle (See
Table 28). A halt special cycle is generated after the processor
executes the HLT instruction.
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If the processor samples FLUSH# asserted, it writes back any
data cache lines that are in the Modified state and invalidates
all lines in the instruction and data cache. The processor then
drives a flush acknowledge special cycle.
If the processor executes a WBINVD instruction, it drives a
writeback special cycle after the processor completes
invalidating and writing back the cache lines.
Halt Cycle
CLK
A[31:3]
A[4:3] = 00b
FBh
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
BRDY#
Figure 69. Basic Special Bus Cycle (Halt Cycle)
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Shutdown Cycle
In Figure 70, a shutdown (triple fault) occurs in the first half of
the waveform, and a shutdown special cycle follows in the
second half. The processor enters shutdown when an interrupt
or exception occurs during the handling of a double fault (INT
8), which amounts to a triple fault. When the processor
encounters a triple fault, it stops its activity on the bus and
generates the shutdown special bus cycle (BE[7:0]# = FEh).
The system logic must assert NMI, INIT, RESET, or SMI# to get
the processor out of the Shutdown state.
Shutdown Occurs
(Triple Fault)
Shutdown Special Cycle
CLK
A[4:3] = 00b
FEh
A[31:3]
BE[7:0]#
ADS#
LOCK#
M/IO#
D/C#
W/R#
D[63:0]
KEN#
BRDY#
Figure 70. Shutdown Cycle
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Stop Grant and Stop
Clock States
Figure 71 on page 174 and Figure 72 on page 175 show the
processor transition from normal execution to the Stop Grant
state, then to the Stop Clock state, back to the Stop Grant state,
and finally back to normal execution. The series of transitions
begins when the processor samples STPCLK# asserted. On
recognizing a STPCLK# interrupt at the next instruction
retirement boundary, the processor performs the following
actions, in the order shown:
1. Its instruction pipelines are flushed.
2. All pending and in-progress bus cycles are completed.
3. The STPCLK# assertion is acknowledged by executing a
Stop Grant special bus cycle.
4. Its internal clock is stopped after BRDY# of the Stop Grant
special bus cycle is sampled asserted and after EWBE# is
sampled asserted (if EWBE# is masked off, then entry into
the Stop Grant state is not affected by EWBE#).
5. The Stop Clock state is entered if the system logic stops the
bus clock CLK (optional).
STPCLK# is sampled as a level-sensitive input on every clock
edge but is not recognized until the next instruction boundary.
The system logic drives the signal either synchronously or
asynchronously. If it is asserted asynchronously, it must be
asserted for a minimum pulse width of two clocks. STPCLK#
must remain asserted until recognized, which is indicated by
the completion of the Stop Grant special cycle.
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Stop Clock
Stop Grant Special Cycle
STPCLK# Sampled Asserted
CLK
A[4:3] = 10b
FBh
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
CACHE#
STPCLK#
D[63:0]
KEN#
BRDY#
Figure 71. Stop Grant and Stop Clock Modes, Part 1
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Stop Clock
STPCLK# Sampled Negated Normal
Stop Grant State
(Re-entered after PLL stabilization)
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
CACHE#
STPCLK#
D[63:0]
KEN#
BRDY#
Figure 72. Stop Grant and Stop Clock Modes, Part 2
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INIT-Initiated
Transition from
Protected Mode to
Real Mode
INIT is typically asserted in response to a BIOS interrupt that
writes to an I/O port. This interrupt is often in response to a
Ctrl-Alt-Del keyboard input. The BIOS writes to a port (similar
to port 64h in the keyboard controller) that asserts INIT. INIT is
also used to support 80286 software that must return to real
mode after accessing extended memory in protected mode.
The assertion of INIT causes the processor to empty its
pipelines, initialize most of its internal state, and branch to
address FFFF_FFF0h—the same instruction execution starting
point used after RESET. Unlike RESET, the processor
preserves the contents of its caches, the Floating-Point state,
the MMX state, Model-Specific Registers (MSRs), the CD and
NW bits of the CR0 register, the time stamp counter, and other
specific internal resources.
Figure 73 on page 177 shows an example in which the operating
system writes to an I/O port, causing the system logic to assert
INIT. The sampling of INIT asserted starts an extended
microcode sequence that terminates with a code fetch from
FFFF_FFF0h, the reset location. INIT is sampled on every clock
edge but is not recognized until the next instruction boundary.
During an I/O write cycle, it must be sampled asserted a
minimum of three clock edges before BRDY# is sampled
asserted if it is to be recognized on the boundary between the
I/O write instruction and the following instruction. If INIT is
asserted synchronously, it can be asserted for a minimum of one
clock. If it is asserted asynchronously, it must have been
negated for a minimum of two clocks, followed by an assertion
of a minimum of two clocks.
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INIT Sampled Asserted
Code Fetch
FFFF_FFF0h
CLK
A[31:3]
BE[7:0]#
ADS#
M/IO#
D/C#
W/R#
D[63:0]
KEN#
BRDY#
INIT
Figure 73. INIT-Initiated Transition from Protected Mode to Real Mode
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7
Power-On Configuration and Initialization
On power-on, the system logic must reset the AMD-K6-2E
processor by asserting the RESET signal. When the processor
samples RESET asserted, it immediately flushes and initializes
all internal resources and its internal state, including its
pipelines and caches, the floating-point state, the MMX and
3DNow! states, and all registers. Then, the processor jumps to
address FFFF_FFF0h to start instruction execution.
7.1
Signals Sampled During the Falling Transition of RESET
FLUSH#
FLUSH# is sampled on the falling transition of RESET to
determine if the processor begins normal instruction execution
or enters three-state test mode.
■ If FLUSH# is High during the falling transition of RESET,
the processor unconditionally runs its Built-In Self Test
(BIST), performs the normal reset functions, then jumps to
address FFFF_FFF0h to start instruction execution. (See
“Built-In Self-Test (BIST)” on page 227 for more details.)
■ If FLUSH# is Low during the falling transition of RESET,
the processor enters three-state test mode. (See
“Three-State Test Mode” on page 228 and “FLUSH# (Cache
Flush)” on page 104 for more details.)
BF[2:0]
The internal operating frequency of the processor is
determined by the state of the bus frequency signals BF[2:0]
when they are sampled during the falling transition of RESET.
The frequency of the CLK input signal is multiplied internally
by a ratio defined by BF[2:0]. (See “BF[2:0] (Bus Frequency)”
on page 93 for the processor-clock to bus-clock ratios.)
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7.2
RESET Requirements
During the initial power-on reset of the processor, RESET must
remain asserted for a minimum of 1.0 ms after CLK and V
CC
reach specification. (See “CLK Switching Characteristics” on
page 267 for clock specifications. See “Electrical Data” on page
253 for V specifications.)
CC
During a warm reset while CLK and V
are within
CC
specification, RESET must remain asserted for a minimum of
15 clocks prior to its negation.
7.3
State of Processor After RESET
Output Signals
Table 29 shows the state of all processor outputs and
bidirectional signals immediately after RESET is sampled
asserted.
Table 29. Output Signal State After RESET
Signal
State
Floating
High
Signal
LOCK#
M/IO#
PCD
State
High
Low
Low
High
Low
Low
High
Floating
Low
Low
Low
–
A[31:3], AP
ADS#, ADSC#
APCHK#
BE[7:0]#
BREQ
High
Floating
Low
PCHK#
PWT
CACHE#
D/C#
High
SCYC
Low
SMIACT#
TDO
D[63:0], DP[7:0]
FERR#
Floating
High
VCC2DET
VCC2H/L#
W/R#
HIT#
High
HITM#
High
HLDA
Low
–
Registers
Table 30 on page 181 shows the state of all architecture
registers and Model-Specific Registers (MSRs) after the
processor has completed its initialization due to the recognition
of the assertion of RESET.
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Table 30. Register State After RESET
Register
GDTR
IDTR
State (hex)
base:0000_0000h limit:0FFFFh
base:0000_0000h limit:0FFFFh
0000h
TR
LDTR
EIP
0000h
FFFF_FFF0h
0000_0002h
0000_0000h
0000_0000h
0000_0000h
0000_058Xh
0000_0000h
0000_0000h
0000_0000h
0000_0000h
F000h
EFLAGS
EAX1
EBX
ECX
EDX2
ESI
EDI
EBP
ESP
CS
SS
0000h
DS
0000h
ES
0000h
FS
0000h
GS
0000h
FPU Stack R7–R03
FPU Control Word3
FPU Status Word3
FPU Tag Word3
0000_0000_0000_0000_0000h
0040h
0000h
5555h
FPU Instruction Pointer3
FPU Data Pointer3
FPU Opcode Register3
0000_0000_0000h
0000_0000_0000h
000_0000_0000b
CR04
CR2
CR3
CR4
DR7
DR6
DR3
6000_0010h
0000_0000h
0000_0000h
0000_0000h
0000_0400h
FFFF_0FF0h
0000_0000h
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Table 30. Register State After RESET (continued)
Register
DR2
State (hex)
0000_0000h
0000_0000h
0000_0000h
DR1
DR0
MCAR3
MCTR3
TR123
0000_0000_0000_0000h
0000_0000_0000_0000h
0000_0000_0000_0000h
0000_0000_0000_0000h
0000_0000_0000_0002h (Model 8/[F:8])
0000_0000_0000_0000h
0000_0000_0000_0000h
0000_0000_0000_0000h
0000_0000_0000_01SBh
0000_0000_0000_0000h
TSC3
EFER3
STAR3
WHCR3
UWCCR3
PSOR3,5
PFIR3
Notes:
1. The contents of EAX indicate if BIST was successful. If EAX = 0000_0000h, BIST was successful.
If EAX is non-zero, BIST failed.
2. EDX contains the AMD-K6-2E processor signature, where X indicates the processor Stepping
ID.
3. The contents of these registers are preserved following the recognition of INIT.
4. The CD and NW bits of CR0 are preserved following the recognition of INIT.
5. “S” represents the Stepping. “B” represents PSOR[3:0], where PSOR[3] equals 0, and
PSOR[2:0] is equal to the value of the BF[2:0] signals sampled during the falling transition of
RESET.
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7.4
State of Processor After INIT
The recognition of the assertion of INIT causes the processor to
empty its pipelines, to initialize most of its internal state, and to
branch to address FFFF_FFF0h—the same instruction
execution starting point used after RESET.
Unlike RESET, the processor preserves the contents of its
caches, the floating-point state, the MMX and 3DNow! states,
MSRs, and the CD and NW bits of the CR0 register.
The edge-sensitive interrupts FLUSH# and SMI# are sampled
and preserved during the INIT process and are handled
accordingly after the initialization is complete. However, the
processor resets any pending NMI interrupt upon sampling
INIT asserted.
INIT can be used as an accelerator for 80286 code that requires
a reset to exit from protected mode back to real mode.
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8
Cache Organization
The following sections describe the basic architecture and
resources of the AMD-K6-2E processor internal caches.
The performance of the AMD-K6-2E processor is enhanced by a
writeback level-one (L1) cache. The cache is organized as a
separate 32-Kbyte instruction cache and a 32-Kbyte data cache,
each with two-way set associativity (See Figure 74). The cache
line size is 32 bytes, and lines are prefetched from external
memory using an efficient, pipelined burst transaction.
As the instruction cache is filled, each instruction byte is
analyzed for instruction boundaries using predecode logic.
Predecoding annotates each instruction byte with information
that later enables the decoders to efficiently decode multiple
instructions simultaneously. Translation lookaside buffers
(TLB) are also used to translate linear addresses to physical
addresses. The instruction cache is associated with a 64-entry
TLB, while the data cache is associated with a 128-entry TLB.
32-Kbyte Instruction Cache
Tag
RAM
State Tag
Bit RAM
State
Bit
Way 0
Way 1
64-Entry TLB
System Bus
Interface Unit
Processor
Core
Predecode Instruction Cache
128-Entry TLB
MESI Tag
Tag
RAM
MESI
Bits
Way 0
Way 1
Bits RAM
32-Kbyte Data Cache
Figure 74. Cache Organization
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The processor cache design takes advantage of a sectored
organization (See Figure 75). Each sector consists of 64 bytes
configured as two 32-byte cache lines. The two cache lines of a
sector share a common tag but have separate MESI (modified,
exclusive, shared, invalid) bits that track the state of each cache
line.
Instruction Cache Line
Tag
Address
Cache Line 0
Cache Line 1
Byte 31
Byte 31
Predecode Bits
Predecode Bits
Byte 30
Byte 30
Predecode Bits
Predecode Bits
........ ........ Byte 0
........ ........ Byte 0
Predecode Bits
Predecode Bits
1 MESI Bit
1 MESI Bit
Data Cache Line
Tag
Address
Cache Line 0
Cache Line 1
Byte 31
Byte 31
Byte 30
Byte 30
........
........
........
........
Byte 0
Byte 0
2 MESI Bits
2 MESI Bits
Notes:
Instruction-cache lines have only two coherency states (valid or invalid) rather than the four MESI coherency states of data-cache lines.
Only two states are needed for the instruction cache because these lines are read-only.
Figure 75. Cache Sector Organization
8.1
MESI States in the Data Cache
The state of each line in the caches is tracked by the MESI bits.
The coherency of these states or MESI bits is maintained by
internal processor snoops and external inquiries by the system
logic. The following four states are defined for the data cache:
■ Modified—This line has been modified and is different from
main memory.
■ Exclusive—This line is not modified and is the same as
external memory. If this line is written to, it becomes
Modified.
■ Shared—If a cache line is in the Shared state it means that
the same line can exist in more than one cache system.
■ Invalid—The information in this line is not valid.
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8.2
Predecode Bits
Decoding x86 instructions is particularly difficult because the
instructions vary in length, ranging from 1 to 15 bytes long.
Predecode logic supplies the predecode bits associated with
each instruction byte.
Predecode bits indicate the number of bytes to the start of the
next x86 instruction. The predecode bits are passed with the
instruction bytes to the decoders, where they assist with
parallel x86 instruction decoding. The predecode bits use
memory separate from the 32-Kbyte instruction cache. The
predecode bits are stored in an extended instruction cache
alongside each x86 instruction byte as shown in Figure 75 on
page 186.
8.3
Cache Operation
The operating modes for the caches are configured by software
using the Not Writethrough (NW) and Cache Disable (CD) bits
of control register 0 (CR0 bits 29 and 30 respectively). These
bits are used in all operating modes.
■ When the CD and NW bits are both 0, the cache is fully
enabled. This is the standard operating mode for the cache.
If a read miss occurs when the processor reads from the
cache, a line fill (32-byte burst read) on the system bus
occurs in order to fetch the cache line. Write hits to the
cache are updated, while write misses and writes to shared
lines cause external memory updates. Refer to Table 34,
“Data Cache States for Read and Write Accesses,” on
page 198 for a summary of cache read and write cycles and
the effect of these operations on the cache MESI state.
Note: A write allocate operation can modify the behavior of write
misses to the cache. See “Write Allocate” on page 192.
■ When the CD bit is 0 and the NW bit is 1, an invalid mode of
operation exists that causes a general protection fault to
occur.
■ When the CD bit is 1 (disabled) and the NW bit is 0, the
cache fill mechanism is disabled but the contents of the
cache are still valid. The processor reads from the cache, and
if a read miss occurs, no line fills take place. Write hits to the
cache are updated, while write misses and writes to shared
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lines cause external memory updates. If PWT is driven Low
and WB/WT# is sampled High, a write hit to a shared line
changes the cache-line state to Exclusive.
■ When the CD and NW bits are both 1, the cache is fully
disabled. Even though the cache is disabled, the contents
are not necessarily invalid. The processor reads from the
cache and, if a read miss occurs, no line fills take place. If a
write hit occurs, the cache is updated but an external
memory update does not occur. If a cache line is in the
Exclusive state during a write hit, the cache-line state is
changed to Modified. Cache lines in the Shared state remain
in the Shared state after a write hit. Write misses access
external memory directly.
The operating system can control the cacheability of a page.
The paging mechanism is controlled by CR3, the Page Directory
Entry (PDE), and the Page Table Entry (PTE). Within CR3,
PDE, and PTE are Page Cache Disable (PCD) and Page
Writethrough (PWT) bits. The values of the PCD and PWT bits
used in Table 31 and Table 32 are taken from either the PTE or
PDE. For more information see the descriptions of PCD and
PWT on page 115 and page 117, respectively.
Tables 31 through 33 describe the logic that determines the
cacheability of a cycle and how that cacheability is affected by
the PCD bits, the PWT bits, the PG and CD bits of CR0,
writeback cycles, the Cache Inhibit (CI) bit of Test Register 12
(TR12), and unlocked memory reads.
Table 31 describes how the PWT signal is driven based on the
values of the PWT bits and the PG bit of CR0.
Table 31. PWT Signal Generation
1
PG Bit of CR0
PWT Signal
PWT Bit
1
0
1
0
1
1
0
0
High
Low
Low
Low
Notes:
1. PWT is taken from PTE or PDE.
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Table 32 describes how the PCD signal is driven based on the
values of the CD bit of CR0, the PCD bits, and the PG bit of
CR0.
Table 32. PCD Signal Generation
1
CD Bit of CR0
PG Bit of CR0
PCD Signal
PCD Bit
1
0
0
0
0
Don’t care
Don’t care
High
High
Low
Low
Low
1
0
1
0
1
1
0
0
Notes:
1. PCD is taken from PTE or PDE.
Table 33 describes how the CACHE# signal is driven based on
the cycle type, the CI bit of TR12, the PCD signal, and the
UWCCR model-specific register.
Table 33. CACHE# Signal Generation
Access Within
Cycle Type
CI Bit of TR12
PCD Signal
CACHE#
1
WC/UC Range
Don’t care
0
Writebacks
Don’t care
0
Don’t care
0
Low
Low
High
High
High
High
High
Unlocked Reads
Locked Reads
Don’t care
Don’t care
1
Don’t care
Don’t care
Don’t care
1
Don’t care
Don’t care
Don’t care
Don’t care
1
Single Writes
Any Cycle Except Writebacks
Any Cycle Except Writebacks
Any Cycle Except Writebacks
Don’t care
Don’t care
Don’t care
Notes:
1. WC and UC refer to Write-Combining and Uncacheable Memory Ranges as defined in the UWCCR.
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Cache-Related Signals
Complete descriptions of the signals that control cacheability
and cache coherency are given on the following pages:
■ CACHE#—page 97
■ EADS#—page 101
■ FLUSH#—page 104
■ HIT#—page 105
■ HITM#—page 105
■ INV—page 110
■ KEN#—page 111
■ PCD—page 115
■ PWT—page 117
■ WB/WT#—page 129
8.4
Cache Disabling and Flushing
To completely disable all cache accesses, the CD bit must be set
to 1 and the cache must be completely flushed. There are three
different methods for flushing the cache. The first method
relies on the system logic, and the other two rely on software.
■ For the system logic to flush the cache, the processor must
sample FLUSH# asserted. In this method, the processor
writes back any data cache lines that are in the Modified
state, invalidates all lines in the instruction and data caches,
and then executes a flush acknowledge special cycle (See
Table 23 on page 132).
■ The second method relies on software to execute the
WBINVD instruction which causes all modified lines to first
be written back to memory, then marks all cache lines as
invalid. Alternatively, if writing modified lines back to
memory is not necessary, the INVD instruction can be used
to invalidate all cache lines.
■ The third method is to make use of the Page Flush/Invalidate
Register (PFIR), which allows cache invalidation and
optional flushing of a specific 4-Kbyte page from the linear
address space (see “Page Flush/Invalidate Register (PFIR)”
on page 200). Unlike the previous two methods of flushing
the cache, this particular method requires the software to be
aware of which specific pages must be flushed and
invalidated.
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8.5
Cache-Line Fills
The processor performs a cache-line fill for any area of system
memory defined as cacheable. If an area of system memory is
not explicitly defined as uncacheable by the software or system
logic, or implicitly treated as uncacheable by the processor,
then the memory access is assumed to be cacheable.
Software can prevent caching of certain pages by setting the
PCD bit in the page directory entry (PDE) or page table entry
(PTE). Additionally, software can define regions of memory as
uncacheable or write combinable by programming the MTRRs
in the UC/WC cacheability control register (UWCCR) (see
“Memory Type Range Registers” on page 207). Write-
combinable memory is defined as uncacheable.
The system logic also has control of the cacheability of bus
cycles. If system logic determines the address is not cacheable,
system logic negates the KEN# signal when asserting the first
BRDY# or NA# of a cycle.
The processor does not cache certain memory accesses, such as
locked operations. In addition, the processor does not cache
PDE or PTE memory reads in the L1 cache (referred to as page
table walks).
When the processor needs to read memory, the processor drives
a read cycle onto the bus. If the cycle is cacheable, the
processor asserts CACHE#. If the cycle is not cacheable, a
non-burst, single-transfer read takes place. The processor waits
for the system logic to return the data and assert a single
BRDY# (See Figure 52 on page 139). If the cycle is cacheable,
the processor executes a 32-byte burst read cycle. The processor
expects a total of four BRDY# signals for a burst read cycle to
take place (See Figure 54 on page 143).
Cache-line fills initiate 32-byte burst read cycles from memory
on the system bus for the instruction cache and the data cache.
If a data-cache line being filled replaces a modified line, the
modified contents of the line are copied to a 32-byte writeback
(copyback) buffer in the bus interface unit while the new line is
being read.
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8.6
Cache-Line Replacements
As programs execute and task switches occur, some cache lines
eventually require replacement.
Instruction cache lines are replaced using a Least Recently
Used (LRU) algorithm. If line replacement is required, lines are
replaced when read cache misses occur.
The data cache uses a slightly different approach to line
replacement. If a miss occurs, and a replacement is required,
lines are replaced by using a Least Recently Allocated (LRA)
algorithm.
Two forms of cache misses and associated cache fills can take
place—a tag-miss cache fill and a tag-hit cache fill.
■ In the case of a tag-miss cache fill, the miss is due to a tag
mismatch, in which case the required cache line is filled
from external memory, and the cache line within the sector
that was not required is marked as invalid.
■ In the case of a tag-hit cache fill, the address matches the
tag, but the requested cache line is marked as invalid. The
required cache line is filled from external memory, and the
cache line within the sector that is not required remains in
the same cache state.
8.7
Write Allocate
Write allocate, if enabled, occurs when the processor has a
pending memory write cycle to a cacheable line and the line
does not currently reside in the data cache. In this case, the
processor performs a 32-byte burst read cycle to fetch the
data-cache line addressed by the pending write cycle. The data
associated with the pending write cycle is merged with the
recently-allocated data-cache line and stored in the processor’s
data cache. The final MESI state of the cache line depends on
the state of the WB/WT# and PWT signals during the burst read
cycle and the subsequent data cache write hit (See Table 34 on
page 198 to determine the cache-line states and the access
types following a cache read miss and cache write hit).
If a data-cache line fetch from memory is attempted because
the write allocate misses the data cache, and KEN# is sampled
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negated, the processor does not perform an allocation. In this
case, the pending write cycle is executed as a single write cycle
on the system bus.
During write allocates, a 32-byte burst read cycle is executed in
place of a non-burst write cycle. While the burst read cycle
generally takes longer to execute than the write cycle,
performance gains are realized on subsequent write cycle hits
to the write-allocated cache line. Due to the nature of software,
memory accesses tend to occur in proximity of each other
(principle of locality). The likelihood of additional write hits to
the write-allocated cache line is high.
The following is a description of three mechanisms by which the
AMD-K6-2E processor performs write allocations. A write
allocate is performed when any one or more of these
mechanisms indicates that a pending write is to a cacheable
area of memory.
Write to a Cacheable
Page
Every time the processor performs a cache line fill, the address
of the page in which the cache line resides is saved in the
Cacheability Control Register (CCR). The page address of
subsequent write cycles is compared with the page address
stored in the CCR. If the two addresses are equal, then the
processor performs a write allocate because the page has
already been determined to be cacheable.
When the processor performs a cache line fill from a different
page than the address saved in the CCR, the CCR is updated
with the new page address.
Write to a Sector
If the address of a pending write cycle matches the tag address
of a valid cache sector, but the addressed cache line within the
sector is marked invalid (a sector hit but a cache line miss),
then the processor performs a write allocate. The pending write
cycle is determined to be cacheable because the sector hit
indicates the presence of at least one valid cache line in the
sector. The two cache lines within a sector are guaranteed by
design to be within the same page.
Write Allocate Limit
The AMD-K6-2E processor uses two mechanisms that are
programmable within the Write Handling Control register
(WHCR) to enable write allocations for write cycles that
address a definable or special 1-Mbyte memory area.
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Write Handling Control Register (WHCR) . The WHCR register
contains two fields —the Write Allocate Enable Limit
(WAELIM) field, and the Write Allocate Enable 15-to-16-Mbyte
(WAE15M) bit (see Figure 76).
63
32 31
22 21 17 16 15
0
W
A
E
WAELIM
1
5
M
Reserved
Symbol
WAELIM
WAE15M
Description
Write Allocate Enable Limit
Write Allocate Enable 15-to-16-Mbyte 16
Bits
31-22
Note: Hardware RESET initializes this MSR to all zeros.
Figure 76. Write Handling Control Register (WHCR)
Write Allocate Enable Limit Field. The WAELIM field is 10 bits wide.
This field, multiplied by 4 Mbytes, defines an upper memory
limit. Any pending write cycle that addresses memory below
this limit causes the processor to perform a write allocate
(assuming the address is not within a range where write
allocates are disallowed). Write allocate is disabled for memory
accesses at and above this limit unless the processor determines
a pending write cycle is cacheable by means of one of the other
write allocate mechanisms—“Write to a Cacheable Page” and
10
“Write to a Sector.” The maximum value of this limit is ((2 –1)
· 4 Mbytes) = 4092 Mbytes. When all the bits in this field are 0,
all memory is above this limit and the write allocate mechanism
is disabled (even if all bits in the WAELIM field are 0, write
allocates can still occur due to the “Write to a Cacheable Page”
and “Write to a Sector” mechanisms).
Write Allocate Enable 15-to-16-Mbyte Bit. The Write Allocate Enable
15-to-16-Mbyte (WAE15M) bit is used to enable write
allocations for the memory write cycles that address the 1
Mbyte of memory between 15 Mbytes and 16 Mbytes. This bit
must be set to 1 to allow write allocate in this memory area. This
bit is provided to account for a small number of uncommon
memory-mapped I/O adapters that use this particular memory
address space. If the system contains one of these peripherals,
the bit should be written to 0 (even if the WAE15M bit is 0,
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write allocates can still occur between 15 Mbytes and 16
Mbytes due to the “Write to a Cacheable Page” and “Write to a
Sector” mechanisms). The WAE15M bit is ignored if the value
in the WAELIM field is less than 16 Mbytes.
By definition, a write allocate is never performed in the
memory area between 640 Kbytes and 1 Mbyte unless the
processor determines a pending write cycle is cacheable by
means of one of the other write allocate mechanisms—“Write
to a Cacheable Page” and “Write to a Sector”. It is not
considered safe to perform write allocations between 640
Kbytes and 1 Mbyte (000A_0000h to 000F_FFFFh) because it is
considered a noncacheable region of memory.
If a memory region is defined as write-combinable or
uncacheable by a MTRR, write allocates are not performed in
that region.
Write Allocate Logic
Mechanisms and
Conditions
Figure 77 shows the logic flow for all the mechanisms involved
with write allocate for memory bus cycles. The left side of the
diagram (the text) describes the conditions that need to be true
for the value of that line to be a 1. Items 1–4 of the diagram are
related to general cache operation and items 5–10 are related to
the write allocate mechanisms.
For more information about write allocate, see the
Implementation of Write Allocate in the K86™ Processors
Application Note, order #21326.
Perform
Write Allocate
1) CD Bit of CR0
2) PCD Signal
3) CI Bit of TR12
4) UC or WC
5) Write to Cacheable Page (CCR)
6) Write to a Sector
7) Less Than Limit (WAELIM)
8) Between 640 Kbytes and 1 Mbyte
9) Between 15–16 Mbytes
10) Write Allocate Enable 15–16 Mbyte (WAE15M)
Figure 77. Write Allocate Logic Mechanisms and Conditions
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The following list corresponds to the items in Figure 77 on page
195:
1. CD Bit of CR0—When the Cache Disable (CD) bit within
control register 0 (CR0) is 1, the cache fill mechanism for
both reads and writes is disabled, and write allocate does
not occur.
2. PCD Signal—When the PCD (page cache disable) signal is
driven High, caching for that page is disabled even if KEN#
is sampled asserted, and write allocate does not occur.
3. CI Bit of TR12—When the cache inhibit bit of test register 12
is 1, L1 cache fills are disabled, and write allocate does not
occur.
4. UC or WC—If a pending write cycle addresses a region of
memory defined as write combinable or uncacheable by an
MTRR, write allocates are not performed in that region.
5. Write to a Cacheable Page (CCR)—A write allocate is
performed if the processor knows that a page is cacheable.
The CCR is used to store the page address of the last cache
fill for a read miss. See “Write to a Cacheable Page” on page
193 for a detailed description of this condition.
6. Write to a Sector—A write allocate is performed if the
address of a pending write cycle matches the tag address of a
valid cache sector, but the addressed cache line within the
sector is invalid. See “Write to a Sector” on page 193 for a
detailed description of this condition.
7. Less Than Limit (WAELIM)—The write allocate limit
mechanism determines if the memory area being addressed
is less than the limit set in the WAELIM field of WHCR. If
the address is less than the limit, write allocate for that
memory address is performed as long as conditions 8
through 10 do not prevent write allocate (even if conditions
8 and 10 attempt to prevent write allocate, condition 5 or 6
allows write allocates to occur).
8. Between 640 Kbytes and 1 Mbyte—Write allocate is not
performed in the memory area between 640 Kbytes and 1
Mbyte. It is not considered safe to perform write allocations
between 640 Kbytes and 1 Mbyte (000A_0000h to
000F_FFFFh) because this area of memory is considered a
noncacheable region of memory (even if condition 8
attempts to prevent write allocate, condition 5 or 6 allows
write allocate to occur).
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9. Between 15–16 Mbytes—If the address of a pending write
cycle is in the 1 Mbyte of memory between 15 Mbytes and 16
Mbytes, and the WAE15M bit is 1, write allocate for this
cycle is enabled.
10.Write Allocate Enable 15–16 Mbytes (WAE15M)—This
condition is associated with the Write Allocate Limit
mechanism and affects write allocate only if the limit
specified by the WAELIM field is greater than or equal to
16 Mbytes. If the memory address is between 15 Mbytes and
16 Mbytes, and the WAE15M bit in the WHCR is 0, write
allocate for this cycle is disabled (even if condition 10
attempts to prevent write allocate, condition 5 or 6 allows
write allocate to occur).
8.8
Prefetching
Hardware
Prefetching
The AMD-K6-2E processor conditionally performs cache
prefetching which results in the filling of the required cache
line first, and a prefetch of the second cache line making up the
other half of the sector. From the perspective of the external
bus, the two cache-line fills typically appear as two 32-byte
burst read cycles occurring back-to-back or, if allowed, as
pipelined cycles. The burst read cycles do not occur
back-to-back (wait states occur) if the processor is not ready to
start a new cycle, if higher priority data read or write requests
exist, or if NA# (next address) was sampled negated. Wait states
can also exist between burst cycles if the processor samples
AHOLD or BOFF# asserted.
Software Prefetching
The 3DNow! technology includes an instruction called
PREFETCH that allows a cache line to be prefetched into the
L1 data cache. Unlike prefetching under hardware control,
software prefetching only fetches the cache line specified by
the operand of the PREFETCH instruction, and does not
attempt to fetch the other cache line in the sector. The
PREFETCH instruction format is defined in Table 15,
“3DNow!™ Instructions,” on page 81. For more detailed
information, see the 3DNow!™ Technology Manual, order#
21928.
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8.9
Cache States
Table 34 shows all the possible cache-line states before and
after program-generated accesses to individual cache lines. The
table includes the correspondence between MESI states and
Writethrough or Writeback states for lines in the data cache.
Table 34. Data Cache States for Read and Write Accesses
Cache State After Access
Cache State Before
Access
1
Type
Access Type
Writeback/
2
MESI State
Writethrough State
Invalid
Invalid
Single read from bus
Burst read from bus, fill
cache3
Invalid
Not applicable or none
Read miss
Shared or
exclusive4
Exclusive
Modified
Shared
Writethrough or writeback4
Cache
Read
Exclusive
Modified
Shared
Not applicable or none
Not applicable or none
Not applicable or none
Writeback
Read hit
Writeback
Writethrough
Not applicable or none
Single write to bus5
Invalid
Invalid
Burst read from bus, fill
cache, write to cache6
Modified7
Invalid
Invalid
Not applicable or none
Not applicable or none
Write miss
Write hit
Burst read from bus, fill
cache, write to cache,
single write to bus6
Cache
Write
Shared8
Exclusive or modified
Shared
Write to cache
Modified
Writeback
Write to cache, single write Shared or
to bus
exclusive4
Writethrough or writeback4
Notes:
1. Single read, single write, cache update, and writethrough = 1 to 8 bytes. Line fill = 32-byte burst read.
2. The final MESI state assumes that the state of the WB/WT# signal remains the same for all accesses to a particular cache line.
3. If CACHE# is driven Low and KEN# is sampled asserted.
4. If PWT is driven Low and WB/WT# is sampled High, the line is cached in the exclusive (writeback) state. If PWT is driven High or
WB/WT# is sampled Low, the line is cached in the shared (writethrough) state.
5. Assumes the write allocate conditions as specified in “Write Allocate” on page 192 are not met.
6. Assumes the write allocate conditions as specified in “Write Allocate” on page 192 are met.
7. Assumes PWT is driven Low and WB/WT# is sampled High.
8. Assumes PWT is driven High or WB/WT # is sampled Low.
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8.10
Cache Coherency
Different methods exist to maintain coherency between the
system memory and cache memories. Inquire cycles, internal
snoops, FLUSH#, WBINVD, INVD, and line replacements all
prevent inconsistencies between memories.
Inquire Cycles
Inquire cycles are bus cycles initiated by system logic. These
inquiries ensure coherency between the caches and main
memory. In systems with multiple caching masters, system logic
maintains cache coherency by driving inquire cycles to the
processor. System logic initiates inquire cycles by asserting
AHOLD, BOFF#, or HOLD to obtain control of the address bus
and then driving EADS#, INV (optional), and an inquire
address (A[31:5]).
This type of bus cycle causes the processor to compare the tags
for both its instruction and data caches with the inquire
address.
■ If there is a hit to a shared or exclusive line in the data cache
or a valid line in the instruction cache, the processor asserts
HIT#.
■ If the compare hits a modified line in the data cache, the
processor asserts HIT# and HITM#. If HITM# is asserted, the
processor writes the modified line back to memory.
■ If INV was sampled asserted with EADS#, a hit invalidates
the line.
■ If INV was sampled negated with EADS#, a hit leaves the
line in the Shared state or transitions it from the Exclusive
or Modified to Shared state.
Table 35 on page 202 shows the effects of inquire cycles—
performed with INV equal to 0 (non-validating) and INV equal
to 1 (invalidating) snoops and invalidations.
Internal Snooping
Internal snooping is initiated by the processor (rather than
system logic) during certain cache accesses. It is used to
maintain coherency between the L1 instruction and data
caches.
The processor automatically snoops its instruction cache during
read or write misses to its data cache, and it snoops its data
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cache during read misses to its instruction cache. Table 35
summarizes the actions taken during this internal snooping.
If an internal snoop hits its target, the processor does the
following:
■ Data Cache Snoop During an Instruction-Cache Read
Miss—If modified, the line in the data cache is written back
on the system bus to external memory. Regardless of its
state, the data-cache line is invalidated and the instruction
cache performs a burst read cycle from external memory.
■ Instruction Cache Snoop During a Data-Cache Miss—The
line in the instruction cache is marked invalid, and the
data-cache read or write is performed from memory.
FLUSH#
In response to sampling FLUSH# asserted, the processor writes
back any data cache lines that are in the Modified state and
then marks all lines in the instruction and data caches as
invalid.
Page Flush/Invalidate
Register (PFIR)
The AMD-K6-2E processor contains the page flush/invalidate
register (PFIR) (see Figure 78) that allows cache invalidation
and optional flushing of a specific 4-Kbyte page from the linear
address space. When the PFIR is written to (using the WRMSR
instruction), the invalidation and the flushing (optional) begin.
The total amount of cache in the AMD-K6-2E processor is 64
Kbytes. Using this register can result in a much lower cycle
count for flushing particular pages versus flushing the entire
cache.
63
32 31
12 11 9 8 7
1 0
F
/
I
P
F
LINPAGE
Reserved
Symbol
Description
Bit
LINPAGE 20-bit Linear Page Address
31-12
PF
F/I
Page Fault Occurred
Flush/Invalidate Command
8
0
Figure 78. Page Flush/Invalidate Register (PFIR)—MSR C000_0088h
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LINPAGE Field. This 20-bit field must be written with bits 31:12 of
the linear address of the 4-Kbyte page that is to be invalidated
and optionally flushed from the L1 cache.
PF Bit. If an attempt to invalidate or flush a page results in a
page fault, the processor sets the PF bit to 1, and the invalidate
or flush operation is not performed (even though invalidate
operations do not normally generate page faults). In this case,
an actual page fault exception is not generated. If the PF bit
equals 0 after an invalidate or flush operation, then the
operation executed successfully. The PF bit must be read after
every write to the PFIR register to determine if the invalidate
or flush operation executed successfully.
F/I Bit. This bit is used to control the type of action that occurs to
the specified linear page. If a 0 is written to this bit, the
operation is a flush, in which case all cache lines in the
modified state within the specified page are written back to
memory, after which the entire page is invalidated. If a 1 is
written to this bit, the operation is an invalidation, in which
case the entire page is invalidated without the occurrence of
any writebacks.
WBINVD and INVD
Instructions
These x86 instructions cause all cache lines to be marked as
invalid. WBINVD writes back modified lines before marking all
cache lines invalid. INVD does not write back modified lines.
Cache-Line
Replacement
Replacing lines in the instruction or data cache, according to
the line replacement algorithms described in “Cache-Line
Fills” on page 191, ensures coherency between external
memory and the caches.
Table 35 on page 202 shows all possible cache-line states before
and after various cache-related operations.
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Table 35. Cache States for Inquire Cycles, Snoops, Flushes, and Invalidation
Cache State After Operation
Cache State
Before Operation
Type of Operation
Memory Access
Writeback/
MESI State
Writethrough State
INV=0
INV=1
INV=0
INV=1
Shared
Invalid
Shared
Invalid
Writethrough
Invalid
Shared or exclusive
Modified
Not applicable or none
Writeback to bus
Inquire Cycle
Writethrough
Invalid
Shared or exclusive
Modified
Not applicable or none
Writeback to bus
Internal Snoop
FLUSH# Signal
Invalid
Invalid
Shared or
exclusive
Not applicable or none
Invalid
Invalid
Modified
Writeback to bus
Shared or exclusive
Modified
Not applicable or none
Writeback to bus
PFIR
(F/I = 0)
Invalid
Invalid
Invalid
Invalid
PFIR
(F/I = 1)
Not applicable or none Not applicable or none
Shared or exclusive
Modified
Not applicable or none
Writeback to bus
WBINVD Instruction
Invalid
Invalid
Invalid
Invalid
INVD Instruction
Not applicable or none Not applicable or none
Notes:
All writebacks are 32-byte burst write cycles.
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Cache Snooping
Table 36 shows the conditions under which snooping occurs in
the AMD-K6-2E processor and the resources that are snooped.
Table 36. Snoop Action
Snooping Action
Type of Access
Type of Event
Instruction Cache
Data Cache
Yes1
Yes1
Inquire Cycle
System Logic
Read
Miss
Yes2
Not applicable
Not applicable
Instruction Cache
Read
Hit
No
Read
Miss
Yes3
No
Not applicable
Not applicable
Not applicable
Not applicable
Internal Snoop
Read
Hit
Data Cache
Write
Miss
Yes3
No
Write
Hit
Notes:
1. The processor’s response to an inquire cycle depends on the state of the INV input signal and the state of the cache line as
follows:
For the instruction cache, if INV is sampled negated, the line remains invalid or valid, but if INV is sampled asserted, the line is
invalidated.
For the data cache, if INV is sampled negated, valid lines remain in or transition to the Shared state, a modified data cache line
is written back before the line is marked shared (with HITM# asserted), and invalid lines remain invalid. For the data cache, if
INV is sampled asserted, the line is marked invalid. Modified lines are written back before invalidation.
2. If an internal snoop hits a modified line in the data cache, the line is written back and invalidated. Then the instruction cache
performs a burst read from memory.
3. If an internal snoop hits a line in the instruction cache, the instruction cache line is invalidated and the data-cache read or write
is performed from memory.
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8.11
Writethrough and Writeback Coherency States
The terms writethrough and writeback apply to two related
concepts in a read-write cache like the AMD-K6-2E processor’s
L1 data cache. The following conditions apply to both the
writethrough and writeback modes:
■ Memory Writes—A relationship exists between external
memory writes and their concurrence with cache updates:
•
An external memory write that occurs concurrently with
a cache update to the same location is a writethrough.
Writethroughs are driven as single cycles on the bus.
•
An external memory write that occurs after the processor
has modified a cache line is a writeback. Writebacks are
driven as burst cycles on the bus.
■ Coherency State—A relationship exists between MESI
coherency states and writethrough-writeback coherency
states of lines in the cache as follows:
•
•
Shared and invalid MESI lines are in writethrough state.
Modified and exclusive MESI lines are in writeback state.
8.12
A20M# Masking of Cache Accesses
Although the processor samples A20M# as a level-sensitive
input on every clock edge, it should only be asserted in real
mode. The processor applies the A20M# masking to its tags,
through which all programs access the caches. Therefore,
assertion of A20M# affects all addresses (cache and external
memory), including the following:
■ Cache-line fills (caused by read misses or write allocates)
■ Cache writethroughs (caused by write misses or write hits to
lines in the Shared state)
However, A20M# does not mask writebacks or invalidations
caused by the following actions:
■ Internal snoops
■ Inquire cycles
■ The FLUSH# signal
■ The WBINVD instruction
■ Writing to the page flush/invalidate register (PFIR)
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9
Write Merge Buffer
The AMD-K6-2E processor contains an 8-byte write merge
buffer that allows the processor to conditionally combine data
from multiple noncacheable write cycles into this merge buffer.
The merge buffer operates in conjunction with the Memory
Type Range Registers (MTRRs). Refer to “Memory Type Range
Registers” on page 207 for a description of the MTRRs.
Merging multiple write cycles into a single write cycle reduces
processor bus utilization and processor stalls, thereby
increasing the overall system performance.
9.1
EWBE# Control
The presence of the merge buffer creates the potential to
perform out-of-order write cycles relative to the processor’s L1
cache. In general, the ordering of write cycles that are driven
externally on the system bus and those that hit the processor’s
cache can be controlled by the EWBE# signal. See “EWBE#
(External Write Buffer Empty)” on page 102 for more
information.
If EWBE# is sampled negated, the processor delays the
commitment of write cycles to cache lines in the Modified state
or Exclusive state in the processor’s cache. Therefore, the
system logic can enforce strong ordering by negating EWBE#
until the external write cycle is complete, thereby ensuring that
a subsequent write cycle that hits the cache does not complete
ahead of the external write cycle.
However, the addition of the write merge buffer introduces the
potential for out-of-order write cycles to occur between writes
to the merge buffer and writes to the processor’s cache. Because
these writes occur entirely within the processor and are not
sent out to the processor bus, the system logic is not able to
enforce strong ordering with the EWBE# signal.
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The EWBE control (EWBEC) bits in the EFER register provide
a mechanism for enforcing three different levels of write
ordering in the presence of the write merge buffer:
■ EFER[3] is defined as the Global EWBE# Disable
(GEWBED). When GEWBED equals 1, the processor does
not attempt to enforce any write ordering internally or
externally (the EWBE# signal is ignored). This is the
maximum performance setting.
■ EFER[2] is defined as the Speculative EWBE# Disable
(SEWBED). SEWBED only affects the processor when
GEWBED equals 0. If GEWBED equals 0 and SEWBED
equals 1, the processor enforces strong ordering for all
internal write cycles with the exception of write cycles
addressed to a range of memory defined as uncacheable
(UC) or write-combining (WC) by the MTRRs. In addition,
the processor samples the EWBE# signal. If EWBE# is
sampled negated, the processor delays the commitment of
write cycles to processor cache lines in the Modified state or
Exclusive state until EWBE# is sampled asserted.
This setting provides performance comparable to, but
slightly less than, the performance obtained when
GEWBED equals 1 because some degree of write ordering is
maintained.
■ If GEWBED equals 0 and SEWBED equals 0, the processor
enforces strong ordering for all internal and external write
cycles. In this setting, the processor assumes, or speculates,
that strong order must be maintained between writes to the
merge buffer and writes that hit the processor’s cache. Once
the merge buffer is written out to the processor’s bus, the
EWBE# signal is sampled. If EWBE# is sampled negated, the
processor delays the commitment of write cycles to
processor cache lines in the Modified state or Exclusive
state until EWBE# is sampled asserted.
This setting is the default after RESET and provides the
lowest performance of the three settings because full write
ordering is maintained.
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Table 37 summarizes the three settings of the EWBEC field for
the EFER register, along with the effect of write ordering and
performance. For more information on the EFER register, see
“Extended Feature Enable Register (EFER)” on page 43.
Table 37. EWBEC Settings
EFER[3]
(GEWBED) (SEWBED)
EFER[2]
Write Ordering
Performance
1
0
0
0 or 1
None
Best
1
0
All except UC/WC Close-to-Best
All Slowest
9.2
Memory Type Range Registers
The AMD-K6-2E processor provides two variable-range Memory
Type Range registers (MTRRs), MTRR0 and MTRR1, each of
which specifies a range of memory. Each range can be defined
as one of the following memory types:
■ Uncacheable (UC) Memory—Memory read cycles are
sourced directly from the specified memory address and the
processor does not allocate a cache line. Memory write
cycles are targeted at the specified memory address and a
write allocation does not occur.
■ Write-Combining (WC) Memory—Memory read cycles are
sourced directly from the specified memory address and the
processor does not allocate a cache line. The processor
conditionally combines data from multiple noncacheable
write cycles that are addressed within this range into a
merge buffer. Merging multiple write cycles into a single
write cycle reduces processor bus utilization and processor
stalls, thereby increasing the overall system performance.
This memory type is applicable for linear video frame
buffers.
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UC/WC Cacheability
Control Register
(UWCCR)
The MTRRs are accessed by addressing the 64-bit MSR known
as the UC/WC Cacheability Control Register (UWCCR). The
MSR address of the UWCCR is C000_0085h. Following reset, all
bits in the UWCCR register are 0. MTRR0 (lower 32 bits of the
UWCCR register) defines the size and memory type of range 0
and MTRR1 (upper 32 bits) defines the size and memory type of
range 1 (see Figure 79 on page 208).
.
Symbol Description
Bits
32
Symbol Description
Bits
0
UC1
Uncacheable Memory Type
UC0
Uncacheable Memory Type
WC1
Write-Combining Memory Type 33
WC0
Write-Combining Memory Type
1
63
49 48
34 33 32 31
17 16
2
1
0
W
C
1
U
C
1
W
C
0
U
C
0
Physical Base Address 1
Physical Address Mask 1
Physical Base Address 0
Physical Address Mask 0
MTRR1
MTRR0
Figure 79. UC/WC Cacheability Control Register (UWCCR)—MSR C000_0085h
Physical Base Address n (n=0, 1). This address is the 15 most-
significant bits of the physical base address of the memory
range. The least-significant 17 bits of the base address are not
needed because the base address is by definition always aligned
on a 128-Kbyte boundary.
Physical Address Mask n (n=0, 1). This value is the 15 most-
significant bits of a physical address mask that is used to define
the size of the memory range. This mask is logically ANDed
with both the physical base address field of the UWCCR
register and the physical address generated by the processor. If
the results of the two AND operations are equal, then the
generated physical address is considered within the range.
That is, if:
Mask & Physical Base Address = Mask & Physical Address Generated
then, the physical address generated by the processor is in the
range.
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WCn (n=0, 1). When set to 1, this memory range is defined as
write combinable (see Table 38 on page 209). Write-combinable
memory is uncacheable.
UCn (n=0, 1). When set to 1, this memory range is defined as
uncacheable (see Table 38).
Table 38. WC/UC Memory Type
WCn
UCn
Memory Type
0
1
0
0
1
No effect on cacheability or write combining
Write-combining memory range (uncacheable)
Uncacheable memory range
0 or 1
9.3
Memory-Range Restrictions
The following rules regarding the address alignment and size of
each range must be adhered to when programming the physical
base address and physical address mask fields of the UWCCR
register:
■ The minimum size of each range is 128 Kbytes.
■ The physical base address must be aligned on a 128-Kbyte
boundary.
■ The physical base address must be range-size aligned. For
example, if the size of the range is 1 Mbyte, then the
physical base address must be aligned on a 1-Mbyte
boundary.
■ All bits set to 1 in the physical address mask must be
contiguous. Likewise, all bits cleared to 0 in the physical
address mask must be contiguous. For example:
111_1111_1100_0000b is a valid physical address mask
111_1111_1101_0000b is invalid
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Table 39 lists the valid physical address masks and the resulting
range sizes that can be programmed in the UWCCR register.
Table 39. Valid Masks and Range Sizes
Masks
Size
128 Kbytes
256 Kbytes
512 Kbytes
1 Mbyte
111_1111_1111_1111b
111_1111_1111_1110b
111_1111_1111_1100b
111_1111_1111_1000b
111_1111_1111_0000b
111_1111_1110_0000b
111_1111_1100_0000b
111_1111_1000_0000b
111_1111_0000_0000b
111_1110_0000_0000b
111_1100_0000_0000b
111_1000_0000_0000b
111_0000_0000_0000b
110_0000_0000_0000b
100_0000_0000_0000b
000_0000_0000_0000b
2 Mbytes
4 Mbytes
8 Mbytes
16 Mbytes
32 Mbytes
64 Mbytes
128 Mbytes
256 Mbytes
512 Mbytes
1 Gbyte
2 Gbytes
4 Gbytes
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9.4
Examples
Suppose that the range of memory from 16 Mbytes to 32 Mbytes
is uncacheable, and the 8-Mbyte range of memory on top of 1
Gbyte is write-combinable. Range 0 is defined as the
uncacheable range, and range 1 is defined as the write-
combining range.
■ Extracting the 15 most-significant bits of the 32-bit physical
base address that corresponds to 16 Mbytes (0100_0000h)
yields
a
physical
base
address
0
field
of
000_0000_1000_0000b. Because the uncacheable range size
is 16 Mbytes, the physical mask value 0 field is
111_1111_1000_0000b, according to Table 39. Bit 1 of the
UWCCR register (WC0) is cleared to 0 and bit 0 of the
UWCCR register is set to 1 (UC0).
■ Extracting the 15 most-significant bits of the 32-bit physical
base address that corresponds to 1 Gbyte (4000_0000h)
yields
a
physical
base
address
1
field
of
010_0000_0000_0000b. Because the write-combining range
size is 8 Mbytes, the physical mask value 1 field is
111_1111_1100_0000b, according to Table 39. Bit 33 of the
UWCCR register (WC1) is set to 1 and bit 32 of the UWCCR
register is cleared to 0 (UC1).
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10
Floating-Point and Multimedia Execution Units
10.1
Floating-Point Execution Unit
The AMD-K6-2E processor contains an IEEE 754-compatible
and IEEE 854-compatible floating-point execution unit
designed to accelerate the performance of software that utilizes
the x86 floating-point instruction set. Floating-point software is
typically written to manipulate numbers that are very large or
very small, that require a high degree of precision, or that result
from complex mathematical operations such as
transcendentals. Applications that take advantage of
floating-point operations include geometric calculations for
graphics acceleration, scientific, statistical, and engineering
applications, and business applications that use large amounts
of high-precision data.
The high-performance floating-point execution unit contains an
adder unit, a multiplier unit, and a divide/square root unit.
These low-latency units can execute floating-point instructions
in as few as two processor clocks. To increase performance, the
processor is designed to simultaneously decode most
floating-point instructions with most short-decodeable
instructions.
See “Software Environment” on page 23 for a description of the
floating-point data types, registers, and instructions.
Handling
Floating-Point
Exceptions
The AMD-K6-2E processor provides the following two types of
exception handling for floating-point exceptions:
■ If the numeric error (NE) bit in CR0 is 1, the processor
invokes the interrupt 10h handler. In this manner, the
floating-point exception is completely handled by software.
■ If the NE bit in CR0 is 0, the processor requires external
logic to generate an interrupt on the INTR signal in order to
handle the exception.
External Logic
Support of
Floating-Point
Exceptions
The processor provides the FERR# (Floating-Point Error) and
IGNNE# (Ignore Numeric Error) signals to allow the external
logic to generate the interrupt in a manner consistent with
PC/AT-compatible systems. The assertion of FERR# indicates
the occurrence of an unmasked floating-point exception
resulting from the execution of a floating-point instruction.
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IGNNE# is used by the external hardware to control the effect
of an unmasked floating-point exception. Under certain
circumstances, if IGNNE# is sampled asserted, the processor
ignores the floating-point exception.
Figure 80 illustrates an implementation of external logic for
supporting floating-point exceptions. The following example
explains the operation of the external logic in Figure 80:
1. As the result of a floating-point exception, the processor
asserts FERR#.
2. The assertion of FERR# and the sampling of IGNNE#
negated indicates the processor has stopped instruction
execution and is waiting for an interrupt.
3. The assertion of FERR# leads to the assertion of INTR by
the interrupt controller.
4. The processor acknowledges the interrupt and jumps to the
corresponding interrupt service routine in which an I/O
write cycle to address port F0h leads to the assertion of
IGNNE#.
5. When IGNNE# is sampled asserted, the processor ignores
the floating-point exception and continues instruction
execution.
6. When the processor negates FERR#, the external logic
negates IGNNE#.
See “FERR# (Floating-Point Error)” on page 103 and “IGNNE#
(Ignore Numeric Exception)” on page 108 for more details.
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I/O Address
Port F0h
AMD-K6™-2E
Processor
IGNNE#
Flip-Flop
CLOCKQ
RESET
“1”
DATAQ
CLEAR
FERR#
Interrupt
Controller
FERR#
Flip-Flop
CLOCKQ
DATAQ
CLEAR
IRQ13
INTR
IGNNE#
Figure 80. External Logic for Supporting Floating-Point Exceptions
10.2
Multimedia and 3DNow!™ Execution Units
The multimedia and 3DNow! execution units of the AMD-K6-2E
processor are designed to accelerate the performance of
software written using the industry-standard MMX instructions
and the 3DNow! instructions. Applications that can take
advantage of the MMX and 3DNow! instructions include
graphics, video and audio compression and decompression,
speech recognition, and telephony applications.
The multimedia execution unit can execute MMX instructions
in a single processor clock. All MMX and 3DNow! arithmetic
instructions are pipelined for higher performance. To increase
performance, the processor is designed to simultaneously
decode all MMX and 3DNow! instructions with most other
instructions.
®
For more information on MMX instructions, see the AMD-K6
Processor Multimedia Technology Manual, order #20726. For
more information on 3DNow! instructions, see the 3DNow!™
Technology Manual, order #21928.
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10.3
Floating-Point and MMX™/3DNow!™ Instruction Compatibility
Registers
The eight 64-bit MMX registers (which are also utilized by
3DNow! instructions) are mapped on the floating-point stack.
This enables backward compatibility with all existing software.
For example, the register saving event that is performed by
operating systems during task switching requires no changes to
the operating system. The same support provided in an
operating system’s interrupt 7 handler (Device Not Available)
for saving and restoring the floating-point registers also
supports saving and restoring the MMX registers.
Exceptions
There are no new exceptions defined for supporting the MMX
and 3DNow! instructions. All exceptions that occur while
decoding or executing an MMX or 3DNow! instruction are
handled in existing exception handlers without modification.
FERR# and IGNNE#
MMX instructions and 3DNow! instructions do not generate
floating-point exceptions. However, if an unmasked
floating-point exception is pending, the processor asserts
FERR# at the instruction boundary of the next floating-point
instruction, MMX instruction, 3DNow! instruction or WAIT
instruction.
The sampling of IGNNE# asserted only affects processor
operation during the execution of an error-sensitive
floating-point instruction, MMX instruction, 3DNow!
instruction or WAIT instruction when the NE bit in CR0 is
cleared to 0.
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11
System Management Mode (SMM)
SMM is an alternate operating mode entered by way of a system
management interrupt (SMI) and handled by an interrupt
service routine. SMM is designed for system control activities
such as power management. These activities appear
transparent to conventional operating systems like DOS and
Windows. SMM is primarily targeted for use by the Basic Input
Output System (BIOS) and specialized low-level device drivers.
The code and data for SMM are stored in the SMM memory
area, which is isolated from main memory.
The processor enters SMM by the system logic’s assertion of the
SMI# interrupt and the processor’s acknowledgment by the
assertion of SMIACT#. At this point the processor saves its state
into the SMM memory state-save area and jumps to the SMM
service routine. The processor returns from SMM when it
executes the resume (RSM) instruction from within the SMM
service routine. Subsequently, the processor restores its state
from the SMM save area, negates SMIACT#, and resumes
execution with the instruction following the point where it
entered SMM.
The following sections summarize the SMM state-save area,
entry into and exit from SMM, exceptions and interrupts in
SMM, memory allocation and addressing in SMM, and the SMI#
and SMIACT# signals.
11.1
SMM Operating Mode and Default Register Values
The software environment within SMM has the following
characteristics:
■ Addressing and operation in real mode
■ 4-Gbyte segment limits
■ Default 16-bit operand, address, and stack sizes, although
instruction prefixes can override these defaults
■ Control transfers that do not override the default operand
size truncate the EIP to 16 bits
■ Far jumps or calls cannot transfer control to a segment with
a base address requiring more than 20 bits, as in real mode
segment-base addressing
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■ A20M# is masked
■ Interrupt vectors use the real-mode interrupt vector table
■ The IF flag in EFLAGS is cleared (INTR not recognized)
■ The TF flag in EFLAGS is cleared
■ The NMI and INIT interrupts are disabled
■ Debug register DR7 is cleared (debug traps disabled)
Figure 81 shows the default map of the SMM memory area. It
consists of a 64-Kbyte area, between 0003_0000h and
0003_FFFFh, of which the top 32 Kbytes (0003_8000h to
0003_FFFFh) must be populated with RAM. The default
code-segment (CS) base address for the area—called the SMM
base address — is at 0003_0000h. The top 512 bytes
(0003_FE00h to 0003_FFFFh) contain a fill-down SMM
state-save area. The default entry point for the SMM service
routine is 0003_8000h.
Fill Down
0003_FFFFh
0003_FE00h
SMM
State-Save
Area
32-Kbyte
Minimum RAM
SMM
Service Routine
Service Routine Entry Point
0003_8000h
0003_0000h
SMM Base Address (CS)
Figure 81. SMM Memory
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Table 40 shows the initial state of registers when entering SMM.
Table 40. Initial State of Registers in System Management Mode (SMM)
Register
SMM Initial State
Unmodified
General-Purpose Registers
EFLAGs
0000_0002h
PE, EM, TS, and PG are cleared (bits 0, 2, 3, and 31).
The other bits are unmodified.
CR0
DR7
0000_0400h
GDTR, LDTR, IDTR, TSSR, DR6 Unmodified
EIP
0000_8000h
0003_0000h
0000_0000h
CS
DS, ES, FS, GS, SS
11.2
SMM State-Save Area
When the processor acknowledges an SMI# interrupt by
asserting SMIACT#, it saves its state in a 512-byte SMM
state-save area shown in Table 41. The save begins at the top of
the SMM memory area (SMM base address + FFFFh) and fills
down to SMM base address + FE00h.
Table 41 shows the offsets in the SMM state-save area relative
to the SMM base address. The SMM service routine can alter
any of the read/write values in the state-save area.
Table 41. SMM State-Save Area Map
Address Offset
FFFCh
Contents Saved
CR0
CR3
EFLAGS
EIP
FFF8h
FFF4h
FFF0h
FFECh
EDI
FFE8h
ESI
FFE4h
EBP
ESP
FFE0h
FFDCh
FFD8h
FFD4h
FFD0h
EBX
EDX
ECX
EAX
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Table 41. SMM State-Save Area Map (continued)
Address Offset
FFCCh
Contents Saved
DR6
FFC8h
DR7
FFC4h
TR
FFC0h
LDTR Base
FFBCh
GS
FFB8h
FS
FFB4h
DS
FFB0h
SS
FFACh
CS
FFA8h
ES
FFA4h
I/O Trap Doubleword
FFA0h
FF9Ch
No data dump at that address
I/O Trap EIP1
FF98h
FF94h
FF90h
FF8Ch
FF88h
FF84h
FF80h
FF7Ch
FF78h
FF74h
FF70h
FF6Ch
FF68h
FF64h
FF60h
FF5Ch
FF58h
FF54h
FF50h
FF4Ch
FF48h
FF44h
FF40h
No data dump at that address
No data dump at that address
IDT Base
IDT Limit
GDT Base
GDT Limit
TSS Attr
TSS Base
TSS Limit
No data dump at that address
LDT High
LDT Low
GS Attr
GS Base
GS Limit
FS Attr
FS Base
FS Limit
DS Attr
DS Base
DS Limit
SS Attr
SS Base
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Table 41. SMM State-Save Area Map (continued)
Address Offset
FF3Ch
Contents Saved
SS Limit
FF38h
CS Attr
FF34h
CS Base
FF30h
CS Limit
ES Attr
FF2Ch
FF28h
ES Base
FF24h
ES Limit
FF20h
FF1Ch
FF18h
FF14h
FF10h
FF0Ch
No data dump at this address
No data dump at this address
No data dump at this address
CR2
CR4
I/O restart ESI1
I/O restart ECX1
FF08h
FF04h
I/O restart EDI1
HALT Restart Slot
FF02h
FF00h
I/O Trap Restart Slot
SMM RevID
FEFCh
FEF8h
SMM BASE
FEF7h–FE00h
No data dump at these addresses
Notes:
1. Only contains information if SMI# is asserted during a valid I/O bus cycle.
11.3
SMM Revision Identifier
The SMM revision identifier at offset FEFCh in the SMM
state-save area specifies the version of SMM and the extensions
that are available on the processor. The SMM revision identifier
fields are as follows:
■ Bits 31–18—Reserved
■ Bit 17—SMM base address relocation (1 = enabled)
■ Bit 16—I/O trap restart (1 = enabled)
■ Bits 15–0—SMM revision level for the AMD-K6-2E processor
= 0002h
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Table 42 shows the format of the SMM revision identifier.
Table 42. SMM Revision Identifier
31–18
Reserved
0
17
16
15–0
SMM Revision Level
0002h
SMM Base Relocation
1
I/O Trap Extension
1
11.4
SMM Base Address
During RESET, the processor sets the base address of the
code-segment (CS) for the SMM memory area—the SMM base
address—to its default, 0003_0000h. The SMM base address at
offset FEF8h in the SMM state-save area can be changed by the
SMM service routine to any address that is aligned to a
32-Kbyte boundary. (Locations not aligned to a 32-Kbyte
boundary cause the processor to enter the Shutdown state when
executing the RSM instruction.)
In some operating environments it may be desirable to relocate
the 64-Kbyte SMM memory area to a high memory area in order
to provide more low memory for legacy software. During system
initialization, the base of the 64-Kbyte SMM memory area is
relocated by the BIOS. To relocate the SMM base address, the
system enters the SMM handler at the default address. This
handler changes the SMM base address location in the SMM
state-save area, copies the SMM handler to the new location,
and exits SMM.
The next time SMM is entered, the processor saves its state at
the new base address. This new address is used for every SMM
entry until the SMM base address in the SMM state-save area is
changed or a hardware reset occurs.
11.5
Halt Restart Slot
During entry into SMM, the halt restart slot at offset FF02h in
the SMM state-save area indicates if SMM was entered from the
Halt state. Before returning from SMM, the halt restart slot
(offset FF02h) can be written to by the SMM service routine to
specify whether the return from SMM takes the processor back
to the Halt state or to the next instruction after the HLT
instruction.
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Upon entry into SMM, the halt restart slot is defined as follows:
■ Bits 15–1—Reserved
■ Bit 0—Point of entry to SMM:
1 = entered from Halt state
0 = not entered from Halt state
After entry into the SMI handler and before returning from
SMM, the halt restart slot can be written using the following
definition:
■ Bits 15–1—Reserved
■ Bit 0—Point of return when exiting from SMM:
1 = return to Halt state
0 = return to next instruction after the HLT instruction
If the return from SMM takes the processor back to the Halt
state, the HLT instruction is not re-executed, but the Halt
special bus cycle is driven on the bus after the return.
11.6
I/O Trap Doubleword
If the assertion of SMI# is recognized during the execution of an
I/O instruction, the I/O trap doubleword at offset FFA4h in the
SMM state-save area contains information about the
instruction. The fields of the I/O trap doubleword are
configured as follows:
■ Bits 31–16—I/O port address
■ Bits 15–4—Reserved
■ Bit 3—REP (repeat) string operation (1 = REP string, 0 = not
a REP string)
■ Bit 2—I/O string operation (1 = I/O string, 0 = not a I/O
string)
■ Bit 1—Valid I/O instruction (1 = valid, 0 = invalid)
■ Bit 0—Input or output instruction (1 = INx, 0 = OUTx)
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Table 43 shows the format of the I/O trap doubleword.
Table 43. I/O Trap Doubleword Configuration
31—16
15—4
3
2
1
0
I/O Port
Address
Reserved
REP String
Operation
I/O String
Operation
Valid I/O
Instruction
Input or
Output
The I/O trap doubleword is related to the I/O trap restart slot
(see “I/O Trap Restart Slot” on page 224). If bit 1 of the I/O
trap doubleword is set by the processor, it means that SMI#
was asserted during the execution of an I/O instruction. The
SMI handler tests bit 1 to see if there is a valid I/O instruction
trapped. If the I/O instruction is valid, the SMI handler is
required to ensure the I/O trap restart slot is set properly. The
I/O trap restart slot informs the CPU whether it should
re-execute the I/O instruction after the RSM or execute the
instruction following the trapped I/O instruction.
Note: If SMI# is sampled asserted during an I/O bus cycle a mini-
mum of three clock edges before BRDY# is sampled asserted,
the associated I/O instruction is guaranteed to be trapped by
the SMI handler.
11.7
I/O Trap Restart Slot
The I/O trap restart slot at offset FF00h in the SMM state-save
area specifies whether the trapped I/O instruction should be
re-executed on return from SMM. This slot in the state-save area
is called the I/O instruction restart function. Re-executing a
trapped I/O instruction is useful, for example, if an I/O write
occurs to a disk that is powered down. The system logic
monitoring such an access can assert SMI#. Then the SMM
service routine would query the system logic, detect a failed I/O
write, take action to power-up the I/O device, enable the I/O
trap restart slot feature, and return from SMM.
The fields of the I/O trap restart slot are defined as follows:
■ Bits 31–16—Reserved
■ Bits 15–0—I/O instruction restart on return from SMM:
0000h = execute the next instruction after the trapped
I/O instruction
00FFh = re-execute the trapped I/O instruction
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Table 44 shows the format of the I/O trap restart slot.
Table 44. I/O Trap Restart Slot
31–16
15–0
Reserved
I/O Instruction restart on return from SMM:
■
■
0000h = Execute the next instruction after the trapped I/O
00FFh = Re-execute the trapped I/O instruction
The processor initializes the I/O trap restart slot to 0000h upon
entry into SMM. If SMM was entered due to a trapped I/O
instruction, the processor indicates the validity of the I/O
instruction by setting or clearing bit 1 of the I/O trap
doubleword at offset FFA4h in the SMM state-save area. The
SMM service routine should test bit 1 of the I/O trap
doubleword to determine if a valid I/O instruction was being
executed when entering SMM and before writing the I/O trap
restart slot. If the I/O instruction is valid, the SMM service
routine can safely rewrite the I/O trap restart slot with the value
00FFh, which causes the processor to re-execute the trapped I/O
instruction when the RSM instruction is executed. If the I/O
instruction is invalid, writing the I/O trap restart slot has
undefined results.
If a second SMI# is asserted and a valid I/O instruction was
trapped by the first SMM handler, the CPU services the second
SMI# prior to re-executing the trapped I/O instruction. The
second entry into SMM never has bit 1 of the I/O trap
doubleword set, and the second SMM service routine must not
rewrite the I/O trap restart slot.
During a simultaneous SMI# I/O instruction trap and debug
breakpoint trap, the AMD-K6-2E processor first responds to the
SMI# and postpones recognizing the debug exception until
after returning from SMM via the RSM instruction. If the debug
registers DR3–DR0 are used while in SMM, they must be saved
and restored by the SMM handler. The processor automatically
saves and restores DR7–DR6. If the I/O trap restart slot in the
SMM state-save area contains the value 00FFh when the RSM
instruction is executed, the debug trap does not occur until
after the I/O instruction is re-executed.
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11.8
Exceptions, Interrupts, and Debug in SMM
During an SMI# I/O trap, the exception/interrupt priority of the
AMD-K6-2E processor changes from its normal priority. The
normal priority places the debug traps at a priority higher than
the sampling of the FLUSH# or SMI# signals. However, during
an SMI# I/O trap, the sampling of the FLUSH# or SMI# signals
takes precedence over debug traps.
The processor recognizes the assertion of NMI within SMM
immediately after the completion of an IRET instruction. Once
NMI is recognized within SMM, NMI recognition remains
enabled until SMM is exited, at which point NMI masking is
restored to the state it was in before entering SMM.
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12
Test and Debug
The AMD-K6-2E processor implements various test and debug
modes to enable the functional and manufacturing testing of
systems and boards that use the processor. In addition, the
debug features of the processor allow designers to debug the
instruction execution of software components. This chapter
describes the following test and debug features:
■ Built-In Self-Test (BIST)—The BIST, which is invoked after
the falling transition of RESET, runs internal tests that
exercise most on-chip RAM structures.
■ Three-State Test Mode—A test mode that causes the
processor to float its output and bidirectional pins.
■ Boundary-Scan Test Access Port (TAP)—The Joint Test
Action Group (JTAG) test access function defined by the
IEEE Standard Test Access Port and Boundary-Scan
Architecture (IEEE 1149.1-1990) specification.
■ Level-One (L1) Cache Inhibit—A feature that disables the
processor’s internal L1 instruction and data caches.
■ Debug Support—Consists of all x86-compatible software
debug features, including the debug extensions.
12.1
Built-In Self-Test (BIST)
Following the falling transition of RESET, the processor
unconditionally runs its built-in self test (BIST). The internal
resources tested during BIST include the following:
■ L1 instruction and data caches
■ Instruction and Data Translation Lookaside Buffers (TLBs)
The contents of the EAX general-purpose register after the
completion of reset indicate if the BIST was successful.
■ If EAX contains 0000_0000h, then BIST was successful.
■ If EAX is non-zero, the BIST failed.
Following the completion of the BIST, the processor jumps to
address FFFF_FFF0h to start instruction execution, regardless
of the outcome of the BIST. The BIST takes approximately
295,000 processor clocks to complete.
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12.2
Three-State Test Mode
The three-state test mode causes the processor to float its
output and bidirectional pins, which is useful for board-level
manufacturing testing. In this mode, the processor is
electrically isolated from other components on a system board,
allowing automated test equipment (ATE) to test components
that drive the same signals as those the processor floats.
If the FLUSH# signal is sampled Low during the falling
transition of RESET, the processor enters the three-state test
mode. (See “FLUSH# (Cache Flush)” on page 104 for the
specific sampling requirements.) The signals floated in the
three-state test mode are as follows:
■ A[31:3]
■ ADS#
■ D/C#
■ M/IO#
■ PCD
■ D[63:0]
■ DP[7:0]
■ FERR#
■ HIT#
■ ADSC#
■ AP
■ PCHK#
■ PWT
■ APCHK#
■ BE[7:0]#
■ BREQ
■ CACHE#
■ SCYC
■ SMIACT#
■ W/R#
■ HITM#
■ HLDA
■ LOCK#
The VCC2DET, VCC2H/L#, and TDO signals are the only
outputs not floated in the three-state test mode.
■ VCC2DET and VCC2H/L# must remain Low to ensure the
system continues to supply the specified processor core
voltage to the V
pins.
CC2
■ TDO is never floated because the boundary-scan Test Access
Port must remain enabled at all times, including during the
three-state test mode.
The three-state test mode is exited when the processor samples
RESET asserted.
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12.3
Boundary-Scan Test Access Port (TAP)
The boundary-scan Test Access Port (TAP) is an IEEE standard
that defines synchronous scanning test methods for complex
logic circuits, such as boards containing a processor. The
AMD-K6-2E processor supports the TAP standard defined in
the IEEE Standard Test Access Port and Boundary-Scan
Architecture (IEEE 1149.1-1990) specification.
Boundary scan testing uses a shift register consisting of the
serial interconnection of boundary-scan cells that correspond to
each I/O buffer of the processor. This non-inverting register
chain, called a Boundary Scan register (BSR), can be used to
capture the state of every processor pin and to drive every
processor output and bidirectional pin to a known state.
Each BSR of every component on a board that implements the
boundary-scan architecture can be serially interconnected to
enable component interconnect testing.
Test Access Port
The Test Access Port (TAP) consists of the following:
■ Test Access Port (TAP) Controller—The TAP controller is a
synchronous, finite state machine that uses the TMS and
TDI input signals to control a sequence of test operations.
See “TAP Controller State Machine” on page 236 for a list
of TAP states and their definition.
■ Instruction Register (IR)—The IR contains the instructions
that select the test operation to be performed and the Test
Data Register (TDR) to be selected. See “TAP Registers” on
page 231 for more details on the IR.
■ Test Data Registers (TDR)—The three TDRs are used to
process the test data. Each TDR is selected by an
instruction in the Instruction Register (IR). See “TAP
Registers” on page 231 for a list of these registers and their
functions.
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TAP Signals
The test signals associated with the TAP controller are as
follows:
■ TCK—The Test Clock for all TAP operations. The rising
edge of TCK is used for sampling TAP signals, and the
falling edge of TCK is used for asserting TAP signals. The
state of the TMS signal sampled on the rising edge of TCK
causes the state transitions of the TAP controller to occur.
TCK can be stopped in the logic 0 or 1 state.
■ TDI—The Test Data Input represents the input to the most
significant bit of all TAP registers, including the IR and all
test data registers. Test data and instructions are serially
shifted by one bit into their respective registers on the rising
edge of TCK.
■ TDO—The Test Data Output represents the output of the
least significant bit of all TAP registers, including the IR and
all test data registers. Test data and instructions are serially
shifted by one bit out of their respective registers on the
falling edge of TCK.
■ TMS—The Test Mode Select input specifies the test
function and sequence of state changes for boundary-scan
testing. If TMS is sampled High for five or more consecutive
clocks, the TAP controller enters its reset state.
■ TRST#—The Test Reset signal is an asynchronous reset that
unconditionally causes the TAP controller to enter its reset
state.
Refer to “Electrical Data” on page 253 and “Signal Switching
Characteristics” on page 267 to obtain the electrical
specifications of the test signals.
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TAP Registers
The AMD-K6-2E processor provides an Instruction register (IR)
and three Test Data registers (TDR) to support the
boundary-scan architecture. The IR and one of the TDRs—the
Boundary-Scan register (BSR)—consist of a shift register and
an output register. The shift register is loaded in parallel in the
Capture states. (See “TAP Controller State Machine” on page
236 for a description of the TAP controller states.) In addition,
the shift register is loaded and shifted serially in the Shift
states. The output register is loaded in parallel from its
corresponding shift register in the Update states.
Instruction Register (IR). The IR is a 5-bit register, without parity,
that determines which instruction to run and which test data
register to select. When the TAP controller enters the
Capture-IR state, the processor loads the following bits into the
IR shift register:
■ 01b—Loaded into the two least significant bits, as specified
by the IEEE 1149.1 standard
■ 000b—Loaded into the three most significant bits
Loading 00001b into the IR shift register during the Capture-IR
state results in loading the SAMPLE/PRELOAD instruction.
For each entry into the Shift-IR state, the IR shift register is
serially shifted by one bit toward the TDO pin. During the shift,
the most significant bit of the IR shift register is loaded from
the TDI pin.
TheIRoutputregisterisloadedfromtheIRshiftregisterinthe
Update-IRstate,andthecurrentinstructionisdefinedbytheIR
outputregister.See“TAPInstructions”onpage235foralistand
definition of the instructions supported by the AMD-K6-2E
processor.
Boundary Scan Register (BSR). The Boundary Scan Register is a Test
Data register consisting of the interconnection of 152
boundary-scan cells. Each output and bidirectional pin of the
processor requires a two-bit cell, where one bit corresponds to
the pin and the other bit is the output enable for the pin. When
a 0 is shifted into the enable bit of a cell, the corresponding pin
is floated, and when a 1 is shifted into the enable bit, the pin is
driven valid. Each input pin requires a one-bit cell that
corresponds to the pin. The last cell of the BSR is reserved and
does not correspond to any processor pin.
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The total number of bits that comprise the BSR is 281. Table 45
on page 233 lists the order of these bits, where TDI is the input
to bit 280, and TDO is driven from the output of bit 0. The
entries listed as pin_E (where pin is an output or bidirectional
signal) are the enable bits.
If the BSR is the register selected by the current instruction
and the TAP controller is in the Capture-DR state, the processor
loads the BSR shift register as follows:
■ If the current instruction is SAMPLE/PRELOAD, then the
current state of each input, output, and bidirectional pin is
loaded. A bidirectional pin is treated as an output if its
enable bit equals 1, and it is treated as an input if its enable
bit equals 0.
■ If the current instruction is EXTEST, then the current state
of each input pin is loaded. A bidirectional pin is treated as
an input, regardless of the state of its enable.
While in the Shift-DR state, the BSR shift register is serially
shifted toward the TDO pin. During the shift, bit 280 of the BSR
is loaded from the TDI pin.
The BSR output register is loaded with the contents of the BSR
shift register in the Update-DR state. If the current instruction
is EXTEST, the processor’s output pins, as well as those
bidirectional pins that are enabled as outputs, are driven with
their corresponding values from the BSR output register.
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Table 45. Boundary Scan Bit Definitions
Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable
280 D35_E
279 D35
247 D19
214 BF1
181 A24
148 A14
115 BE7#
246 D16_E
245 D16
213 BF2
180 A18_E
179 A18
147 A17_E
146 A17
114 PCD_E
113 PCD
278 D29_E
277 D29
212 RESET
211 BF0
244 D17_E
243 D17
178 A5_E
177 A5
145 A16_E
144 A16
112 DC_E
276 D33_E
275 D33
210 FLUSH#
209 INTR
208 NMI
207 SMI#
206 A25_E
205 A25
111 D/C#
242 D15_E
241 D15
176 EADS#
175 A22_E
174 A22
143 HIT_E
142 HIT#
141 ADS_E
140 ADS#
139 CLK
110 WR_E
109 W/R#
108 NA#
274 D27_E
273 D27
240 DP1_E
239 DP1
238 D13_E
237 D13
272 DP0_E
271 DP0
173 AHOLD
172 HITM_E
171 HITM#
170 A4_E
169 A4
107 PWT_E
106 PWT
270 DP3_E
269 DP3
204 A26_E
203 A26
138 ADSC_E
137 ADSC#
136 BE0_E
135 BE0#
134 AP_E
133 AP
105 CACHE_E
104 CACHE#
103 WB/WT#
102 MIO_E
101 M/IO#
100 BREQ_E
99 BREQ
236 D6_E
235 D6
268 D25_E
267 D25
202 A29_E
201 A29
234 D14_E
233 D14
168 A9_E
167 A9
266 D0_E
265 D0
200 A28_E
199 A28
232 D11_E
231 D11
166 A8_E
165 A8
264 D30_E
263 D30
198 A23_E
197 A23
132 BE1_E
131 BE1#
130 BE2_E
129 BE2#
128 BRDY#
127 BE3_E
126 BE3#
125 BE4_E
124 BE4#
123 BRDYC#
122 BE5_E
121 BE5#
120 BE6_E
119 BE6#
118 KEN#
117 INV
230 D1_E
229 D1
164 A19_E
163 A19
98 SCYC_E
97 SCYC
262 DP2_E
261 DP2
196 A27_E
195 A27
228 D12_E
227 D12
162 BOFF#
161 A6_E
160 A6
96 LOCK_E
95 LOCK#
94 APCHK_E
93 APCHK#
92 PCHK_E
91 PCHK#
90 EWBE#
89 SMIACT_E
88 SMIACT#
87 FERR_E
86 FERR#
85 D20_E
84 D20
260 D2_E
259 D2
194 A11_E
193 A11
226 D10_E
225 D10
258 D28_E
257 D28
192 A3_E
191 A3
159 A20_E
158 A20
224 D7_E
223 D7
256 D24_E
255 D24
190 A31_E
189 A31
157 A13_E
156 A13
222 D8_E
221 D8
254 D26_E
253 D26
188 A21_E
187 A21
155 A12_E
154 A12
220 D9_E
219 D9
252 D21_E
251 D21
186 A30_E
185 A30
153 A10_E
152 A10
218 HOLD
217 STPCLK#
216 INIT
215 IGNNE#
250 D18_E
249 D18
184 A7_E
183 A7
151 A15_E
150 A15
248 D19_E
182 A24_E
149 A14_E
116 BE7_E
83 D22_E
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1
Table 45. Boundary Scan Bit Definitions (continued)
Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable Bit Pin/Enable
82 D22
68 D54_E
67 D54
54 D47_E
53 D47
40 D62_E
39 D62
26 D38_E
25 D38
12 D3_E
11 D3
81 D23_E
80 D23
66 D50_E
65 D50
52 D59_E
51 D59
38 D49_E
37 D49
24 D58_E
23 D58
10 D39_E
79 A20M#
78 HLDA_E
77 HLDA
76 DP7_E
75 DP7
9
8
7
6
5
4
3
2
1
0
D39
64 D56_E
63 D56
50 D51_E
49 D51
36 DP4_E
35 DP4
22 D42_E
21 D42
D32_E
D32
62 D55_E
61 D55
48 D45_E
47 D45
34 D4_E
33 D4
20 D36_E
19 D36
D5_E
D5
74 D63_E
73 D63
60 D48_E
59 D48
46 D61_E
45 D61
32 D46_E
31 D46
18 D60_E
17 D60
D37_E
D37
72 D52_E
71 D52
58 D57_E
57 D57
44 DP5_E
43 DP5
30 D41_E
29 D41
16 D40_E
15 D40
D31_E
D31
70 DP6_E
69 DP6
56 D53_E
55 D53
42 D43_E
41 D43
28 D44_E
27 D44
14 D34_E
13 D34
Reserved
Notes:
1. TDI is the input to bit 280, and TDO is driven from the output of bit 0. The entries listed as pin_E (where pin is an output or
bidirectional signal) are the enable bits.
Device Identification Register (DIR). The DIR is a 32-bit Test Data
register selected during the execution of the IDCODE
instruction. The fields of the DIR and their values are shown in
Table 46 and are defined as follows:
■ Version Code—This 4-bit field is incremented by AMD
manufacturing for each major revision of silicon.
■ Part Number—This 16-bit field identifies the specific
processor model.
■ Manufacturer—This 11-bit field identifies the manufacturer
of the component (AMD).
■ LSB—The least significant bit (LSB) of the DIR is always 1,
as specified by the IEEE 1149.1 standard.
Table 46. Device Identification Register
Version Code
(Bits 31–28)
Part Number
(Bits 27–12)
Manufacturer
(Bits 11–1)
LSB
(Bit 0)
Xh
0580h
00000000001b
1b
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Bypass Register (BR). The BR is a Test Data register consisting of a
1-bit shift register that provides the shortest path between TDI
and TDO. When the processor is not involved in a test
operation, the BR can be selected by an instruction to allow the
transfer of test data through the processor without having to
serially scan the test data through the BSR. This functionality
preserves the state of the BSR and significantly reduces test
time.
The BR register is selected by the BYPASS and HIGHZ
instructions as well as by any instructions not supported by the
AMD-K6-2E processor.
TAP Instructions
The processor supports the three instructions required by the
IEEE 1149.1 standard—EXTEST, SAMPLE/PRELOAD, and
BYPASS—as well as two additional optional instructions—
IDCODE and HIGHZ.
Table 47 shows the complete set of TAP instructions supported
by the processor along with the 5-bit Instruction Register
encoding and the register selected by each instruction.
Table 47. Supported Test Access Port (TAP) Instructions
Instruction
Encoding
Register
Description
EXTEST1
SAMPLE / PRELOAD
IDCODE
00000b
BSR
Sample inputs and drive outputs
Sample inputs and outputs, then load the BSR
Read DIR
00001b
00010b
BSR
DIR
BR
HIGHZ
00011b
Float outputs and bidirectional pins
Undefined instruction, execute the BYPASS instruction
BYPASS2
00100b–11110b
BR
BYPASS3
11111b
BR
Connect TDI to TDO to bypass the BSR
Notes:
1. Following the execution of the EXTEST instruction, the processor must be reset to return to normal, non-test operation.
2. These instruction encodings are undefined on the AMD-K6-2E processor and default to the BYPASS instruction.
3. Because the TDI input contains an internal pullup, the BYPASS instruction is executed if the TDI input is not connected or open
during an instruction scan operation. The BYPASS instruction does not affect the normal operational state of the processor.
EXTEST Instruction. When the EXTEST instruction is executed,
the processor loads the BSR shift register with the current state
of the input and bidirectional pins in the Capture-DR state and
drives the output and bidirectional pins with the corresponding
values from the BSR output register in the Update-DR state.
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SAMPLE/PRELOAD Instruction. The SAMPLE/PRELOAD instruction
performs two functions. These functions are as follows:
■ During the Capture-DR state, the processor loads the BSR
shift register with the current state of every input, output,
and bidirectional pin.
■ During the Update-DR state, the BSR output register is
loaded from the BSR shift register in preparation for the
next EXTEST instruction.
The SAMPLE/PRELOAD instruction does not affect the normal
operational state of the processor.
BYPASS Instruction. The BYPASS instruction selects the BR
register, which reduces the boundary-scan length through the
processor from 281 to one (TDI to BR to TDO). The BYPASS
instruction does not affect the normal operational state of the
processor.
IDCODE Instruction. The IDCODE instruction selects the DIR
register, allowing the device identification code to be shifted
out of the processor. This instruction is loaded into the IR when
the TAP controller is reset. The IDCODE instruction does not
affect the normal operational state of the processor.
HIGHZ Instruction. The HIGHZ instruction forces all output and
bidirectional pins to be floated. During this instruction, the BR
is selected and the normal operational state of the processor is
not affected.
TAP Controller State
Machine
The TAP controller state diagram is shown in Figure 82 on page
237. State transitions occur on the rising edge of TCK. The logic
0 or 1 next to the states represents the value of the TMS signal
sampled by the processor on the rising edge of TCK.
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Test-Logic-Reset
1
0
0
1
1
1
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
0
0
Capture-IR
0
1
1
Capture-DR
0
Shift-DR
Shift-IR
0
0
1
1
1
1
Exit1-DR
Exit1-IR
0
0
Pause-DR
Pause-IR
0
0
1
1
Exit2-DR
0
Exit2-IR
0
1
1
Update-DR
Update-IR
1
0
1
0
IEEE Std 1149.1-1990, Copyright © 1990. IEEE. All rights reserved
Figure 82. TAP State Diagram
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The states of the TAP controller are described as follows:
Test-Logic-Reset. This state represents the initial reset state of the
TAP controller and is entered when the processor samples
RESET asserted, when TRST# is asynchronously asserted, and
when TMS is sampled High for five or more consecutive clocks.
In addition, this state can be entered from the Select-IR-Scan
state. The IR is initialized with the IDCODE instruction, and
the processor’s normal operation is not affected in this state.
Capture-DR. During the SAMPLE/PRELOAD instruction, the
processor loads the BSR shift register with the current state of
every input, output, and bidirectional pin. During the EXTEST
instruction, the processor loads the BSR shift register with the
current state of every input and bidirectional pin.
Capture-IR. When the TAP controller enters the Capture-IR state,
the processor loads 01b into the two least significant bits of the
IR shift register and loads 000b into the three most significant
bits of the IR shift register.
Shift-DR. While in the Shift-DR state, the selected TDR shift
register is serially shifted toward the TDO pin. During the shift,
the most significant bit of the TDR is loaded from the TDI pin.
Shift-IR. While in the Shift-IR state, the IR shift register is
serially shifted toward the TDO pin. During the shift, the most
significant bit of the IR is loaded from the TDI pin.
Update-DR. During the SAMPLE/PRELOAD instruction, the BSR
output register is loaded with the contents of the BSR shift
register. During the EXTEST instruction, the output pins, as
well as those bidirectional pins defined as outputs, are driven
with their corresponding values from the BSR output register.
Update-IR. In this state, the IR output register is loaded from the
IR shift register, and the current instruction is defined by the
IR output register.
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The following states have no effect on the normal or test
operation of the processor other than as shown in Figure 82 on
page 237:
■ Run-Test/Idle—This state is an idle state between scan
operations.
■ Select-DR-Scan—This is the initial state of the test data
register state transitions.
■ Select-IR-Scan—This is the initial state of the Instruction
Register state transitions.
■ Exit1-DR—This state is entered to terminate the shifting
process and enter the Update-DR state.
■ Exit1-IR—This state is entered to terminate the shifting
process and enter the Update-IR state.
■ Pause-DR—This state is entered to temporarily stop the
shifting process of a test data register.
■ Pause-IR—This state is entered to temporarily stop the
shifting process of the instruction register.
■ Exit2-DR—This state is entered in order to either terminate
the shifting process and enter the Update-DR state or to
resume shifting following the exit from the Pause-DR state.
■ Exit2-IR—This state is entered in order to either terminate
the shifting process and enter the Update-IR state or to
resume shifting following the exit from the Pause-IR state.
12.4
L1 Cache Inhibit
The AMD-K6-2E processor provides a means for inhibiting the
normal operation of its L1 instruction and data caches while
still supporting an external level-2 (L2) cache. This capability
allows system designers to disable the L1 cache during the
testing and debug of an L2 cache.
If the Cache Inhibit bit (bit 3) of test register 12 (TR12) is 0, the
processor’s L1 cache is enabled and operates as described in
“Cache Organization” on page 185. If the Cache Inhibit bit is 1,
the L1 cache is disabled and no new cache lines are allocated.
Even though new allocations do not occur, valid L1 cache lines
remain valid and are read by the processor when a requested
address hits a cache line. In addition, the processor continues to
support inquire cycles initiated by the system logic, including
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the execution of writeback cycles when a modified cache line is
hit.
While the L1 is inhibited, the processor continues to drive the
PCD output signal appropriately, which system logic can use to
control external L2 caching.
In order to completely disable the L1 cache so that no valid
lines exist in the cache, the Cache Inhibit bit must be set to 1
and the cache must be flushed in one of the following ways:
■ By asserting the FLUSH# input signal
■ By executing the WBINVD instruction
■ By executing the INVD instruction (modified cache lines are
not written back to memory)
■ By using the Page Flush/Invalidate register (PFIR) (see
“Page Flush/Invalidate Register (PFIR)” on page 200)
12.5
Debug
The AMD-K6-2E processor implements the standard x86 debug
functions, registers, and exceptions. In addition, the processor
supports the I/O breakpoint debug extension. The debug
feature assists programmers and system designers during
software execution tracing by generating exceptions when one
or more events occur during processor execution. The exception
handler, or debugger, can be written to perform various tasks,
such as displaying the conditions that caused the breakpoint to
occur, displaying and modifying register or memory contents, or
single-stepping through program execution.
The following sections describe the debug registers and the
various types of breakpoints and exceptions that the processor
supports.
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Debug Registers
Figures 83 through 86 show the 32-bit debug registers
supported by the processor.
Symbol
LEN 3
R/W 3
LEN 2
R/W 2
LEN 1
R/W 1
LEN 0
R/W 0
Description
Length of Breakpoint #3
Bits
31–30
Type of Transaction(s) to Trap 29–28
Length of Breakpoint #2 27–26
Type of Transaction(s) to Trap 25–24
Length of Breakpoint #1 23–22
Type of Transaction(s) to Trap 21–20
Length of Breakpoint #0 19–18
Type of Transaction(s) to Trap 17–16
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
G
D
G
E
L
E
G
3
L
3
G
2
L
2
G
1
L
1
G
0
L
0
LEN
3
R/W LEN R/W
LEN
1
R/W LEN
R/W
0
3
2
2
1
0
Reserved
Symbol
GD
GE
LE
Description
General Detect Enabled
Global Exact Breakpoint Enabled
Local Exact Breakpoint Enabled
Bit
13
9
8
G3
L3
G2
L2
G1
L1
G0
L0
Global Exact Breakpoint # 3 Enabled 7
Local Exact Breakpoint # 3 Enabled 6
Global Exact Breakpoint # 2 Enabled 5
Local Exact Breakpoint # 2 Enabled 4
Global Exact Breakpoint # 1 Enabled 3
Local Exact Breakpoint # 1 Enabled 2
Global Exact Breakpoint # 0 Enabled 1
Local Exact Breakpoint # 0 Enabled 0
Figure 83. Debug Register DR7
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
B
D
B
1
B
S
B
2
B
0
B
T
B
3
Reserved
Symbol
BT
BS
Description
Breakpoint Task Switch
Breakpoint Single Step
Bit
15
14
BD
B3
B2
B1
B0
Breakpoint Debug Access Detected 13
Breakpoint #3 Condition Detected
Breakpoint #2 Condition Detected
Breakpoint #1 Condition Detected
Breakpoint #0 Condition Detected
3
2
1
0
Figure 84. Debug Register DR6
DR5
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
DR4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
Figure 85. Debug Registers DR5 and DR4
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DR3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Breakpoint 3 32-bit Linear Address
9
8
7
6
5
4
3
2
1
0
DR2
DR1
DR0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Breakpoint 2 32-bit Linear Address
9
8
7
6
5
4
3
2
1
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Breakpoint 1 32-bit Linear Address
9
8
7
6
5
4
3
2
1
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Breakpoint 0 32-bit Linear Address
9
8
7
6
5
4
3
2
1
0
Figure 86. Debug Registers DR3, DR2, DR1, and DR0
DR3–DR0. The processor allows the setting of up to four
breakpoints. DR3–DR0 contain the linear addresses for
breakpoint 3 through breakpoint 0, respectively, and are
compared to the linear addresses of processor cycles to
determine if a breakpoint occurs. Debug register DR7 defines
the specific type of cycle that must occur in order for the
breakpoint to occur.
DR5–DR4. When debugging extensions are disabled (bit 3 of CR4
is 0), the DR5 and DR4 registers are mapped to DR7 and DR6,
respectively, in order to be software compatible with previous
generations of x86 processors. When debugging extensions are
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enabled (bit 3 of CR4 is 1), any attempt to load DR5 or DR4
results in an undefined opcode exception. Likewise, any
attempt to store DR5 or DR4 also results in an undefined
opcode exception.
DR6. If a breakpoint is enabled in DR7, and the breakpoint
conditions as defined in DR7 occur, then the corresponding B
bit (B3–B0) in DR6 is set to 1. In addition, any other breakpoints
defined using these particular breakpoint conditions are
reported by the processor by setting the appropriate B bits in
DR6, regardless of whether these breakpoints are enabled or
disabled. However, if a breakpoint is not enabled, a debug
exception does not occur for that breakpoint.
If the processor decodes an instruction that writes or reads DR7
through DR0, the BD bit (bit 13) in DR6 is set to 1 (if enabled in
DR7) and the processor generates a debug exception. This
operation allows control to pass to the debugger prior to debug
register access by software.
If the Trap Flag (bit 8) of the EFLAGS register is 1, the
processor generates a debug exception after the successful
execution of every instruction (single-step operation) and sets
the BS bit (bit 14) in DR6 to indicate the source of the
exception.
When the processor switches to a new task and the debug trap
bit (T bit) in the corresponding Task State Segment (TSS) is 1,
the processor sets the BT bit (bit 15) in DR6 and generates a
debug exception.
DR7. When set to 1, L3–L0 locally enable breakpoints 3 through
0, respectively. L3–L0 are cleared to 0 whenever the processor
executes a task switch. Clearing L3–L0 to 0 disables the
breakpoints and ensures that these particular debug exceptions
are only generated for a specific task.
When set to 1, G3–G0 globally enable breakpoints 3 through 0,
respectively. Unlike L3–L0, G3–G0 are not cleared to 0
whenever the processor executes a task switch. Not clearing
G3–G0 to 0 allows breakpoints to remain enabled across all
tasks. If a breakpoint is enabled globally but disabled locally,
the global enable overrides the local enable.
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The LE (bit 8) and GE (bit 9) bits in DR7 have no effect on the
operation of the processor and are provided to be software-
compatible with previous generations of x86 processors.
When set to 1, the GD bit in DR7 (bit 13) enables the debug
exception associated with the BD bit (bit 13) in DR6. This bit is
cleared to 0 when a debug exception is generated.
LEN3–LEN0 and RW3–RW0 are two-bit fields in DR7 that
specify the length and type of each breakpoint as defined in
Table 48.
Table 48. DR7 LEN and RW Definitions
1
RW Bits
Breakpoint
LEN Bits
00b2
01b
00b
Instruction Execution
00b
01b
11b
00b
01b
11b
00b
01b
11b
One-byte Data Write
Two-byte Data Write
Four-byte Data Write
10b3
11b
One-byte I/O Read or Write
Two-byte I/O Read or Write
Four-byte I/O Read or Write
One-byte Data Read or Write
Two-byte Data Read or Write
Four-byte Data Read or Write
Notes:
1. LEN bits equal to 10b is undefined.
2. When RW equals 00b, LEN must be equal to 00b.
3. When RW equals 10b, debugging extensions (DE) must be enabled (bit 3 of CR4 must be set
to 1). If DE is cleared to 0, then RW equal to 10b is undefined.
Debug Exceptions
A debug exception is categorized as either a debug trap or a
debug fault.
■ A debug trap calls the debugger following the execution of
the instruction that caused the trap.
■ A debug fault calls the debugger prior to the execution of the
instruction that caused the fault.
All debug traps and faults generate either an Interrupt 01h or
an Interrupt 03h exception.
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Interrupt 01h. The following events are considered debug traps
that cause the processor to generate an Interrupt 01h
exception:
■ Enabled breakpoints for data and I/O cycles
■ Single-step trap
■ Task-switch trap
The following events are considered debug faults that cause the
processor to generate an Interrupt 01h exception:
■ Enabled breakpoints for instruction execution
■ BD bit in DR6 set to 1
Interrupt 03h. The INT 3 instruction is defined in the x86
architecture as a breakpoint instruction. This instruction
causes the processor to generate an Interrupt 03h exception.
This exception is a debug trap because the debugger is called
following the execution of the INT 3 instruction.
The INT 3 instruction is a one-byte instruction (opcode CCh)
typically used to insert a breakpoint in software by writing CCh
to the address of the first byte of the instruction to be trapped
(the target instruction). Following the trap, if the target
instruction is to be executed, the debugger must replace the
INT 3 instruction with the first byte of the target instruction.
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13
Clock Control
13.1
Clock Control States
The AMD-K6-2E processor supports five modes of clock control.
The processor can transition between these modes to maximize
performance, to minimize power dissipation, or to provide a
balance between performance and power. (See “Power
Dissipation” on page 258 for the maximum power dissipation of
the AMD-K6-2E processor within the normal and the
reduced-power states.)
The five clock-control states supported are:
■ Normal State—The processor is running in real mode,
virtual-8086 mode, protected mode, or system management
mode (SMM). In this state, all clocks are running— including
the external bus clock, CLK, and the internal processor
clock—and the full features and functions of the processor
are available.
■ Halt State—This low-power state is entered following the
successful execution of the HLT instruction. During this
state, the internal processor clock is stopped.
■ Stop Grant State—This low-power state is entered following
the recognition of the assertion of the STPCLK# signal.
During this state, the internal processor clock is stopped.
■ Stop Grant Inquire State—This state is entered from the
Halt state and the Stop Grant state as the result of a
system-initiated inquire cycle.
■ Stop Clock State—This low-power state is entered from the
Stop Grant state when the CLK signal is stopped.
Figure 87 on page 248 illustrates the clock control state
transitions. Each of the four reduced-power states are described
in the following sections.
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STPCLK# Asserted
HLT Instruction
Normal Mode
– Real
– Virtual-8086
– Protected
– SMM
STPCLK# Negated,
or RESET Asserted
RESET, SMI#, INIT,
or INTR Asserted
EADS# Asserted
EADS# Asserted
Stop Grant
Inquire
State
Halt
State
Stop Grant
State
Writeback
Completed
Writeback
Completed
CLK
Stopped
CLK
Started
Stop Clock
State
Figure 87. Clock Control State Transitions
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13.2
Halt State
Enter Halt State
During the execution of the HLT instruction, the AMD-K6-2E
processor executes a Halt special cycle. After BRDY# is
sampled asserted during this cycle, and then EWBE# is also
sampled asserted (if not masked off), the processor enters the
Halt state in which the processor disables most of its internal
clock distribution.
To support the following operations, the internal phase-lock
loop (PLL) continues to run, and some internal resources are
still clocked in the Halt state:
■ Inquire Cycles—The processor continues to sample AHOLD,
BOFF#, and HOLD to support inquire cycles that are
initiated by the system logic. The processor transitions to
the Stop Grant Inquire state during the inquire cycle. After
returning to the Halt state following the inquire cycle, the
processor does not execute another Halt special cycle.
■ Flush Cycles—The processor continues to sample FLUSH#.
If FLUSH# is sampled asserted, the processor performs the
flush operation in the same manner as it is performed in the
Normal state. Upon completing the flush operation, the
processor executes the Halt special cycle which indicates
the processor is in the Halt state.
■ Time Stamp Counter (TSC)—The TSC continues to count in
the Halt state.
■ Signal Sampling—The processor continues to sample INIT,
INTR, NMI, RESET, and SMI#.
After entering the Halt state, all signals driven by the processor
retain their state as they existed following the completion of
the Halt special cycle.
Exit Halt State
The AMD-K6-2E processor remains in the Halt state until it
samples INIT, INTR (if interrupts are enabled), NMI, RESET, or
SMI# asserted. If any of these signals is sampled asserted, the
processor returns to the Normal state and performs the
corresponding operation. All of the normal requirements for
recognition of these input signals apply within the Halt state.
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13.3
Stop Grant State
Enter Stop Grant
State
After recognizing the assertion of STPCLK#, the AMD-K6-2E
processor flushes its instruction pipelines, completes all
pending and in-progress bus cycles, and acknowledges the
STPCLK# assertion by executing a Stop Grant special bus cycle.
After BRDY# is sampled asserted during this cycle, and after
EWBE# is also sampled asserted (if not masked off), the
processor enters the Stop Grant state.
The Stop Grant state is like the Halt state in that the processor
disables most of its internal clock distribution in the Stop Grant
state.
In order to support the following operations, the internal PLL
still runs, and some internal resources are still clocked in the
Stop Grant state:
■ Inquire cycles—The processor transitions to the Stop Grant
Inquire state during an inquire cycle. After returning to the
Stop Grant state following the inquire cycle, the processor
does not execute another Stop Grant special cycle.
■ Time Stamp Counter (TSC)—The TSC continues to count in
the Stop Grant state.
■ Signal Sampling—The processor continues to sample INIT,
INTR, NMI, RESET, and SMI#.
FLUSH# is not recognized in the Stop Grant state (unlike while
in the Halt state).
Upon entering the Stop Grant state, all signals driven by the
processor retain their state as they existed following the
completion of the Stop Grant special cycle.
Exit Stop Grant State
The AMD-K6-2E processor remains in the Stop Grant state until
it samples STPCLK# negated or RESET asserted. If STPCLK#
is sampled negated, the processor returns to the Normal state in
less than 10 bus clock (CLK) periods. After the transition to the
Normal state, the processor resumes execution at the
instruction boundary on which STPCLK# was initially
recognized.
If STPCLK# is recognized as negated in the Stop Grant state
and subsequently sampled asserted prior to returning to the
250
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Normal state, a minimum of one instruction is executed prior to
re-entering the Stop Grant state.
If INIT, INTR (if interrupts are enabled), FLUSH#, NMI, or
SMI# are sampled asserted in the Stop Grant state, the
processor latches the edge-sensitive signals (INIT, FLUSH#,
NMI, and SMI#), but otherwise does not exit the Stop Grant
state to service the interrupt. When the processor returns to the
Normal state due to sampling STPCLK# negated, any pending
interrupts are recognized after returning to the Normal state.
To ensure their recognition, all of the normal requirements for
these input signals apply within the Stop Grant state.
If RESET is sampled asserted in the Stop Grant state, the
processor immediately returns to the Normal state and the
reset process begins.
13.4
Stop Grant Inquire State
Enter Stop Grant
Inquire State
The Stop Grant Inquire state is entered from the Stop Grant
state or the Halt state when EADS# is sampled asserted during
an inquire cycle initiated by the system logic. The AMD-K6-2E
processor responds to an inquire cycle in the same manner as in
the Normal state by driving HIT# and HITM#. If the inquire
cycle hits a modified data cache line, the processor performs a
writeback cycle.
Exit Stop Grant
Inquire State
Following the completion of any writeback, the processor
returns to the state from which it entered the Stop Grant
Inquire state.
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13.5
Stop Clock State
Enter Stop Clock
State
If the CLK signal is stopped while the AMD-K6-2E processor is
in the Stop Grant state, the processor enters the Stop Clock
state. Because all internal clocks and the PLL are not running
in the Stop Clock state, the Stop Clock state represents the
minimum-power state of all clock control states. The CLK signal
must be held Low while it is stopped.
The Stop Clock state cannot be entered from the Halt state.
INTR is the only input signal that is allowed to change states
while the processor is in the Stop Clock state. However, INTR is
not sampled until the processor returns to the Stop Grant state.
All other input signals must remain unchanged in the Stop
Clock state.
Exit Stop Clock State
The AMD-K6-2E processor returns to the Stop Grant state from
the Stop Clock state after the CLK signal is started and the
internal PLL has stabilized. PLL stabilization is achieved after
the CLK signal has been running within its specification for a
minimum of 1.0 ms.
The frequency of CLK when exiting the Stop Clock state can be
different than the frequency of CLK when entering the Stop
Clock state.
The state of the BF[2:0] signals when exiting the Stop Clock
state is ignored because the BF[2:0] signals are only sampled
during the falling transition of RESET.
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14
Electrical Data
This chapter includes specifications for the operating ranges,
absolute ratings, and DC characteristics of the AMD-K6-2E
embedded processor. Typical and maximum power dissipation
values for the AMD-K6-2E processor during normal and
reduced power states are listed, as are example power derating
values based on lower CPU frequencies. The derating data may
be of special interest to embedded customers who want to use
AMD’s standard- or low-power devices at lower CPU
frequencies. The chapter concludes with a discussion of power
and grounding requirements and I/O buffer characteristics.
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14.1
Operating Ranges
The AMD-K6-2E processor is designed to provide functional
operation if the voltage and temperature parameters are within
the limits defined in Table 49.
Table 49. Operating Ranges
Parameter
Parameter Description
Minimum
Typical
Maximum
Core Supply Voltage—Low Power2
1
1.8 V
1.9 V
2.0 V
VCC2
Core Supply Voltage—Standard Power3
2.1 V
2.2 V
3.3 V
2.3 V
3.6 V
1
3.135 V
I/O Supply Voltage—Standard and Low Power
VCC3
Case Temperature—Low Power4
Case Temperature—Standard Power5
TCASE
0C
0C
–
–
85C
70C
Notes:
1. VCC2 and VCC3 are referenced from VSS.
2. VCC2 specification for 1.9-V component.
3. VCC2 specification for 2.2-V component.
4. Case temperature range required for AMD-K6-2E/xxxAMZ valid ordering part number combinations, where xxx represents the
processor core frequency.
5. Case temperature range required for AMD-K6-2E/xxxAFR valid ordering part number combinations, where xxx represents the
processor core frequency.
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14.2
Absolute Ratings
The AMD-K6-2E processor is not designed to be operated
beyond the operating ranges listed in Table 49. Exposure to
conditions outside these operating ranges for extended periods
of time can affect long-term reliability. Permanent damage can
occur if the absolute ratings listed in Table 50 are exceeded.
Note: If the AMD-K6-2E processor shows a “7” after the date code,
refer to the numbers in the last (rightmost) column of Table
50. The AMD-K6®-2 Revision Guide (order #21641)
available on AMD’s web site contains package marking
details, including the location of the date codeꢀ
Table 50. Absolute Ratings
Maximum for OPN
Suffixes: 233AFR,
2
Parameter
Minimum
Maximum for All OPNs
233AMZ, 266AFR,
1
266AMZ, 300AFR
VCC2
–0.5 V
–0.5 V
–0.5 V
2.6 V
2.4 V
3.6 V
VCC3
3.6 V
3
V
CC3 + 0.5 V and < 4.0 V
VCC3 + 0.5 V and < 4.0 V
VPIN
TCASE (under bias)
TSTORAGE
–65C
–65C
+110C
+150C
+110C
+150C
Notes:
1. The data in this column applies to OPN suffixes 233AFR, 233AMZ, 266AFR, 266AMZ, and
300AFR, provided that the processor is not marked with “7” following the date code (i.e., is
blank).
2. The data in this column applies to all OPNs listed in Table 73, “Valid Ordering Part Number
Combinations,” on page 306 (including 233AFR, 233AMZ, 266AFR, 266AMZ, and 300AFR
when the processor is marked with a “7” following the date code).
3. VPIN (the voltage on any I/O pin) must not be greater than 0.5 V above the voltage being
applied to VCC3. In addition, the VPIN voltage must never exceed 4.0 V.
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14.3
DC Characteristics
The DC characteristics of the AMD-K6-2E processor are shown
in Table 51.
Table 51. DC Characteristics
Symbol
Parameter Description
Min
Max
Comments
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.3 V
+0.8 V
1
V
CC3+0.3 V
2.0 V
2.4 V
VIH
VOL
IOL = 4.0-mA load
0.4 V
VOH
IOH = 3.0-mA load
233 MHz2,3
266 MHz2,3
300 MHz2,3,5
333 MHz2,3,4
350 MHz2,5
233 MHz3,6
266 MHz3,6
300 MHz3,5,6
333 MHz3,4,6
350 MHz5,6
400 MHz3,5,6
233 MHz3,7
266 MHz3,7
300 MHz3,5,7
333 MHz3,4,7
350 MHz5,7
400 MHz3,5,7
4.75 A
5.35 A
5.50 A
5.65 A
6.25 A
6.50 A
7.35 A
8.45 A
9.40 A
9.85 A
10.00 A
0.52 A
0.54 A
0.56 A
0.58 A
0.60 A
0.62 A
15 mA
ICC2
1.9 V Power Supply Current2
Low Power
ICC2
2.2 V Power Supply Current6
Standard
Power
ICC3
Standard
and
Low Power
3.3 V Power Supply Current7
8
Input Leakage Current
Output Leakage Current
ILI
8
15 mA
ILO
9
Input Leakage Current Bias with Pullup
–400 mA
IIL
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Table 51. DC Characteristics (continued)
Symbol
Parameter Description
Input Leakage Current Bias with Pulldown
Input Capacitance
Min
Max
200 mA
10 pF
15 pF
20 pF
10 pF
10 pF
15 pF
10 pF
Comments
10
IIH
CIN
COUT
COUT
CCLK
CTIN
Output Capacitance
I/O Capacitance
CLK Capacitance
Test Input Capacitance (TDI, TMS, TRST#)
Test Output Capacitance (TDO)
TCK Capacitance
CTOUT
CTCK
Notes:
1. VCC3 refers to the voltage being applied to VCC3 during functional operation.
2. VCC2=2.0 V —The maximum power supply current must be taken into account when designing a power supply.
3. This specification applies to components using a CLK frequency of 66 MHz.
4. This specification applies to components using a CLK frequency of 95 MHz.
5. This specification applies to components using a CLK frequency of 100 MHz.
6. VCC2=2.3 V —The maximum power supply current must be taken into account when designing a power supply.
7. VCC3=3.6 V —The maximum power supply current must be taken into account when designing a power supply.
8. Refers to inputs and I/O without an internal pullup resistor and 0 VIN VCC3
.
9. Refers to inputs with an internal pullup and VIL=0.4 V.
10. Refers to inputs with an internal pulldown and VIH=2.4 V.
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14.4
Power Dissipation
Table 52 and Table 53 list the typical and maximum power
dissipation of the AMD-K6-2E processor during normal and
reduced power states.
.
Table 52. Typical and Maximum Power Dissipation for OPN Suffix AMZ (Low-Power Devices)
1
1
1 3
1,2
3
,
Clock Control State
Thermal Power
233 MHz
266 MHz
300 MHz
333 MHz
350 MHz
9.00 W
10.00 W
10.00 W
7.00 W
1.20 W
1.00 W
10.00 W
7.00 W
1.20 W
1.00 W
11.00 W
4,5
(Maximum)
Thermal Power
6.30 W
1.20 W
1.00 W
7.00 W
1.20 W
1.00 W
7.70 W
1.20 W
1.00 W
6
(Typical)
Stop Grant/Halt
7
(Maximum)
Stop Clock
(Maximum)
8
Notes:
1. This specification applies to components using a CLK frequency of 66 MHz.
2. This specification applies to components using a CLK frequency of 95 MHz.
3. This specification applies to components using a CLK frequency of 100 MHz.
4. The maximum power dissipated in the normal clock control state must be taken into account when designing a solution for
thermal dissipation for the AMD-K6-2E processor.
5. Maximum power is determined for the worst-case instruction sequence or function for the listed clock control states with
VCC2 = 1.9 V, and VCC3 = 3.3 V.
6. Typical power is determined for the typical instruction sequences or functions associated with normal system operation with
VCC2 = 1.9 V, and VCC3 = 3.3 V.
7. The CLK signal and the internal PLL are still running but most internal clocking has stopped.
8. The CLK signal, the internal PLL, and all internal clocking has stopped.
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Table 53. Typical and Maximum Power Dissipation for OPN Suffix AFR (Standard-Power Devices)
1
1
1,3
1,2
3
1,3
Clock Control State
Thermal Power
233 MHz
266 MHz
300 MHz
333 MHz
350 MHz
400 MHz
13.50 W
14.70 W
17.20 W
19.00 W
11.40 W
3.94 W
3.50 W
19.95 W
16.90 W
10.15 W
4.40 W
4.00 W
4,5
(Maximum)
Thermal Power
8.10
8.85 W
2.48 W
2.25
10.35 W
2.50 W
2.25 W
11.98 W
3.96 W
3.50 W
6
(Typical)
Stop Grant/Halt
2.46 W
2.25 W
7
(Maximum)
Stop Clock
8
(Maximum)
Notes:
1. This specification applies to components using a CLK frequency of 66 MHz.
2. This specification applies to components using a CLK frequency of 95 MHz.
3. This specification applies to components using a CLK frequency of 100 MHz.
4. The maximum power dissipated in the normal clock control state must be taken into account when designing a solution for
thermal dissipation for the AMD-K6-2E processor.
5. Maximum power is determined for the worst-case instruction sequence or function for the listed clock control states with
VCC2 = 2.2 V, and VCC3 = 3.3 V.
6. Typical power is determined for the typical instruction sequences or functions associated with normal system operation with
VCC2 = 2.2 V, and VCC3 = 3.3 V.
7. The CLK signal and the internal PLL are still running but most internal clocking has stopped.
8. The CLK signal, the internal PLL, and all internal clocking has stopped.
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14.5
Power Derating Based on Lower CPU Frequencies
This section provides standard- and low-power product
specification power derating based on lower CPU frequencies.
Note: The 166-MHz and 200-MHz data provided in Table 54 and
Table 55 was derived from the standard- and low-power
AMD-K6-2E/233AFR (and AMZ) and AMD-K6-2E/266AFR
(and AMZ) products and is solely for informational
purposes. The guaranteed electrical and thermal
specification data for the AMD-K6-2E/233AFR (and AMZ)
and AMD-K6-2E/266AFR (and AMZ) is also included here
for convenience. The derating data may be of interest to
customers who want to use AMD’s standard- or low-power
devices at lower CPU frequencies. AMD does not guarantee
the 166-MHz and 200-MHz CPU frequency derating data
and does not provide devices with these lower CPU
frequencies. Only devices listed in Table 73, “Valid Ordering
Part Number Combinations,” on page 306 are available.
Table 54. Power Derating Specification for Standard-Power Devices (AMD-K6-2E/233AFR and 266AFR)
1
1
1
1
Clock Control State
Maximum I (core)
166.7 MHz
200.0 MHz
233.3 MHz
266.7 MHz
CC2
5.31 A
6.00 A
6.50 A
7.35 A
2
V
= 2.2 V 100 mV
CC2
Maximum I (I/O)
CC3
0.48 A
0.50 A
0.52 A
0.54 A
3
V
= 3.3 V +300 mV, –165 mV
CC3
4
11.10 W
12.50 W
13.50 W
14.70 W
Thermal Power (Maximum)
5
6.65 W
2.5x
7.50 W
3.0x
8.10 W
3.5x
8.85 W
4.0x
Thermal Power (Typical)
Clock Multiple
BF[2:0] Inputs
100b
101b
111b
010b
Notes:
1. This specification applies to components using a clock and bus frequency of 66 MHz.
2. The maximum ICC2 specification is taken at VCC2 = 2.3 V. (The maximum power supply current must be taken into account when
designing a power supply.)
3. The maximum ICC3 specification is taken at VCC3 = 3.6 V. (The maximum power supply current must be taken into account when
designing a power supply.)
4. Maximum thermal power is determined for the worst-case instruction sequence or functions for the listed clock control states
with VCC2 = 2.2 V and VCC3 = 3.3 V.
5. Typical thermal power is determined for the typical instruction sequence or functions associated with normal system operation
with VCC2 = 2.2 V and VCC3 = 3.3 V.
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Table 55. Power Derating Specification for Low-Power Devices (AMD-K6-2E/233AMZ and 266AMZ)
1
1
1
1
Clock Control State
166.7 MHz
200.0 MHz
233.3 MHz
266.7 MHz
Maximum I (core)
CC2
3.79 A
4.37 A
4.75 A
5.35 A
2
V
= 1.9 V 100 mV
CC2
Maximum I (I/O)
CC3
0.48 A
7.07 W
0.50 A
8.10 W
0.52 A
0.54 A
3
V
= 3.3 V +300 mV, –165 mV
CC3
4
9.00 W
10.00 W
Thermal Power (Maximum)
5
4.95 W
2.5x
5.67 W
3.0x
6.30 W
3.5x
7.00 W
4.0x
Thermal Power (Typical)
Clock Multiple
BF[2:0] Inputs
100b
101b
111b
010b
Notes:
1. This specification applies to components using a clock and bus frequency of 66 MHz.
2. The maximum ICC2 specification is taken at VCC2 = 2.0 V. (The maximum power supply current must be taken into account when
designing a power supply.)
3. The maximum ICC3 specification is taken at VCC3 = 3.6 V. (The maximum power supply current must be taken into account when
designing a power supply.)
4. Maximum thermal power is determined for the worst-case instruction sequence or functions for the listed clock control states
with VCC2 = 1.9 V and VCC3 = 3.3 V.
5. Typical thermal power is determined for the typical instruction sequence or functions associated with normal system operation
with VCC2 = 1.9 V and VCC3 = 3.3 V.
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14.6
Power and Grounding
Power Connections
The AMD-K6-2E processor is a dual voltage device. Two
separate supply voltages are required: V and V
.
CC3
CC2
■ VCC2 provides the core voltage for the processor.
■ VCC3 provides the I/O voltage.
See “Electrical Data” on page 253 for the value and range of
V
and V
.
CC2
CC3
There are 28 V
, 32 V
, and 68 V pins on the AMD-K6-2E
CC3 SS
CC2
processor. (See Chapter 17, “Pin Designation Diagrams” on
page 299 for all power and ground pin designations.) The large
number of power and ground pins are provided to ensure that
the processor and package maintain a clean and stable power
distribution network.
For proper operation and functionality, all V
, V
, and V
CC3 SS
CC2
pins must be connected to the appropriate planes in the circuit
board. The power planes have been arranged in a pattern to
simplify routing and minimize crosstalk on the circuit board.
The isolation region between two voltage planes must be at
least 0.254 mm if they are in the same layer of the circuit board.
(See Figure 88 on page 263.) To maintain low-impedance
current sink and reference, the ground plane must never be
split.
Although the AMD-K6-2E processor has two separate supply
voltages, there are no special power sequencing requirements.
The best procedure is to minimize the time between which V
CC2
and V
are either both on or both off.
CC3
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AMD-K6™-2E Processor Data Sheet
0.254mm (min.) for
isolation region
C20
C21
C22
C23
C24
C25
C18
C17
C19
C5
C6
C7
CC3
+
+
+
C27
C28
C1
C2
CC4
CC5
CC6
+
+
C11
C12
C13
C29
C30
C31
C26
VCC3 (I/O) Plane
VCC2 (Core) Plane
CC1
CC2
Figure 88. Suggested Component Placement
Decoupling
Recommendations
In addition to the isolation region mentioned in “Power
Connections” on page 262, adequate decoupling capacitance is
required between the two system power planes and the ground
plane to minimize ringing and to provide a low-impedance path
for return currents. Suggested decoupling capacitor placement
is shown in Figure 88.
Surface mounted capacitors should be used as close as possible
to the processor to minimize resistance and inductance in the
lead lengths while maintaining minimal height.
For recommendations about the specific value, quantity, and
location of the capacitors illustrated in Figure 88, see the AMD-
K6® Processor Power Supply Design Application Note, order
#21103.
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Pin Connection
Requirements
For proper operation, the following requirements for signal pin
connections must be met:
■ Do not drive address and data signals into large capacitive
loads at high frequencies. If necessary, use buffer chips to
drive large capacitive loads.
■ Leave all NC (no-connect) pins unconnected.
■ Unused inputs should always be connected to an
appropriate signal level.
•
•
Active Low inputs that are not being used should be
connected to V through a 20-kW pullup resistor.
CC3
Active High inputs that are not being used should be
connected to GND through a pulldown resistor.
■ Reserved signals can be treated in one of the following ways:
•
•
•
As no-connect (NC) pins, in which case these pins are left
unconnected
As pins connected to the system logic as defined by the
industry-standard Socket 7 and Super7 interfaces
Any combination of NC and Socket 7 pins
■ Keep trace lengths to a minimum.
14.7
I/O Buffer Characteristics
All of the AMD-K6-2E processor inputs, outputs, and
bidirectional buffers are implemented using a 3.3V buffer
design. AMD has developed a model that represents the
characteristics of the actual I/O buffer to allow system
designers to perform analog simulations of AMD-K6-2E
processor signals that interface with the system logic. Analog
simulations are used to determine a signal’s time of flight from
source to destination and to ensure that the system’s signal
quality requirements are met. Signal quality measurements
include overshoot, undershoot, slope reversal, and ringing.
I/O Buffer Model
AMD provides a model of the AMD-K6-2E processor I/O buffer
for system designers to use in board-level simulations. This I/O
buffer model conforms to the I/O Buffer Information
Specification (IBIS). The I/O model contains voltage versus
current (V/I) and voltage versus time (V/T) data tables for
accurate modeling of I/O buffer behavior.
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The following list characterizes the properties of the I/O buffer
model:
■ All data tables contain minimum, typical, and maximum
values to allow for worst-case, typical, and best-case
simulations, respectively.
■ The pullup, pulldown, power clamp, and ground clamp
device V/I tables contain enough data points to accurately
represent the nonlinear nature of the V/I curves. In addition,
the voltage ranges provided in these tables extend beyond
the normal operating range of the AMD-K6-2E processor for
those simulators that yield more accurate results based on
this wider range.
■ The rising and falling ramp rates are specified.
■ The min/typ/max V
operating range is specified as
CC3
3.135V, 3.3V, and 3.6V, respectively.
■ V = 0.8V, V = 2.0V, and V = 1.5V.
IL
IH
MEAS
■ The R/L/C of the package is modeled.
■ The capacitance of the silicon die is modeled.
■ The model assumes a test load resistance of 50 W.
I/O Model
Application Note
For the AMD-K6-2E processor I/O Buffer IBIS Models and their
application, refer to the AMD-K6 Processor I/O Model (IBIS)
®
Application Note, order #21084.
I/O Buffer AC and DC
Characteristics
See “Signal Switching Characteristics” on page 267 for the
AMD-K6-2E processor AC timing specifications.
Use this chapter for the AMD-K6-2E processor DC
specifications.
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AMD-K6™-2E Processor Data Sheet
15
Signal Switching Characteristics
The AMD-K6-2E processor signal switching characteristics are
presented in tables 56 through 65. Valid delay, float, setup, and
hold timing specifications are listed. These specifications are
provided for the system designer to determine if the timings
necessary for the processor to interface with the system logic
are met.
■ Table 56 and Table 57 on page 268 contain the switching
characteristics of the CLK input.
■ Table 58 through Table 61, beginning on page 270, contain
the timings for the normal operation signals.
■ Table 62 on page 278 and Table 63 on page 279 contain the
timings for RESET and the configuration signals.
■ Table 64 and Table 65 on page 280 contain the timings for
the test operation signals.
All signal timings provided are:
■ Measured between CLK, TCK, or RESET at 1.5 V and the
corresponding signal at 1.5 V—this applies to input and
output signals that are switching from Low to High, or from
High to Low
■ Based on input signals applied at a slew rate of 1 V/ns
between 0 V and 3 V (rising) and 3 V to 0 V (falling)
■ Valid within the operating ranges given in “Operating
Ranges” on page 254
■ Based on a load capacitance (C ) of 0 pF
L
15.1
CLK Switching Characteristics
Table 56 and Table 57 contain the switching characteristics of
the CLK input to the AMD-K6-2E processor for 100-MHz and
66-MHz bus operation, respectively, as measured at the voltage
levels indicated by Figure 89 on page 269.
The CLK Period Stability parameter specifies the variance
(jitter) allowed between successive periods of the CLK input
measured at 1.5 V. This parameter must be considered as one of
the elements of clock skew between the AMD-K6-2E and the
system logic.
Chapter 15
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Preliminary Information
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15.2
Clock Switching Characteristics for 100-MHz Bus Operation
Table 56. CLK Switching Characteristics for 100-MHz Bus Operation
Preliminary Data
Symbol Parameter Description
Figure
Comments
Min
33.3 MHz
10.0 ns
3.0 ns
3.0 ns
0.15 ns
0.15 ns
–
Max
100 MHz
–
Frequency
–
In Normal Mode
t1
t2
t3
t4
t5
CLK Period
89
89
89
89
89
–
In Normal Mode
CLK High Time
CLK Low Time
CLK Fall Time
CLK Rise Time
CLK Period Stability
–
–
–
–
1.5 ns
1.5 ns
250 ps
–
–
Note
Notes:
The jitter frequency power spectrum peaking must occur at frequencies greater than (Frequency of CLK)/3 or less than 500 kHz.
15.3
Clock Switching Characteristics for 66-MHz Bus Operation
Table 57. CLK Switching Characteristics for 66-MHz Bus Operation
Preliminary Data
Symbol Parameter Description
Figure
Comments
Min
33.3 MHz
15.0 ns
4.0 ns
Max
Frequency
66.6 MHz
30.0 ns
In Normal Mode
In Normal Mode
t1
t2
t3
t4
t5
CLK Period
89
89
89
89
89
CLK High Time
CLK Low Time
CLK Fall Time
CLK Rise Time
CLK Period Stability
4.0 ns
0.15 ns
0.15 ns
1.5 ns
1.5 ns
250 ps
Note
Notes:
The jitter frequency power spectrum peaking must occur at frequencies greater than (Frequency of CLK)/3 or less than 500 KHz.
268
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t2
2.0 V
1.5 V
t3
0.8 V
t4
t5
t1
Figure 89. CLK Waveform
15.4
Valid Delay, Float, Setup, and Hold Timings
Valid Delay and Float
Timing
The maximum valid delay timings are provided to allow a
system designer to determine if setup times to the system logic
can be met. Likewise, the minimum valid delay timings are used
to analyze hold times to the system logic.
■ Valid delay and float timings are given for output signals
during functional operation and are given relative to the
rising edge of CLK.
■ During boundary-scan testing, valid delay and float timings
for output signals are with respect to the falling edge of
TCK.
Setup and Hold
Timing
The setup and hold time requirements for the AMD-K6-2E
processor input signals must be met by the system logic to
assure the proper operation of the processor.
■ The setup and hold timings during functional and
boundary-scan test mode are given relative to the rising
edge of CLK and TCK, respectively.
Chapter 15
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269
Preliminary Information
AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
15.5
Output Delay Timings for 100-MHz Bus Operation
Table 58. Output Delay Timings for 100-MHz Bus Operation
Preliminary Data
Min
Symbol
Parameter Description
Figure
Max
4.0 ns
7.0 ns
4.0 ns
7.0 ns
4.0 ns
7.0 ns
5.5 ns
7.0 ns
4.5 ns
4.0 ns
7.0 ns
4.0 ns
4.0 ns
7.0 ns
4.0 ns
7.0 ns
4.5 ns
7.0 ns
4.5 ns
7.0 ns
4.5 ns
4.0 ns
4.0 ns
4.0 ns
4.0 ns
7.0 ns
4.0 ns
7.0 ns
4.0 ns
t6
A[31:3] Valid Delay
A[31:3] Float Delay
ADS# Valid Delay
1.1 ns
1.0 ns
1.0 ns
1.0 ns
91
92
91
92
91
92
91
92
91
91
92
91
91
92
91
92
91
92
91
92
91
91
91
91
91
92
91
92
91
t7
t8
t9
ADS# Float Delay
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
t29
t30
t31
t32
t33
t34
ADSC# Valid Delay
ADSC# Float Delay
AP Valid Delay
AP Float Delay
APCHK# Valid Delay
BE[7:0]# Valid Delay
BE[7:0]# Float Delay
BREQ Valid Delay
1.0 ns
1.0 ns
1.0 ns
1.0 ns
CACHE# Valid Delay
CACHE# Float Delay
D/C# Valid Delay
1.0 ns
1.3 ns
1.3 ns
D/C# Float Delay
D[63:0] Write Data Valid Delay
D[63:0] Write Data Float Delay
DP[7:0] Write Data Valid Delay
DP[7:0] Write Data Float Delay
FERR# Valid Delay
HIT# Valid Delay
1.0 ns
1.0 ns
1.1 ns
1.0 ns
1.1 ns
HITM# Valid Delay
HLDA Valid Delay
LOCK# Valid Delay
LOCK# Float Delay
M/IO# Valid Delay
M/IO# Float Delay
PCD Valid Delay
1.0 ns
1.0 ns
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AMD-K6™-2E Processor Data Sheet
Table 58. Output Delay Timings for 100-MHz Bus Operation (continued)
Preliminary Data
Symbol
Parameter Description
Figure
Min
Max
t35
t36
t37
t38
t39
t40
t41
t42
t43
PCD Float Delay
PCHK# Valid Delay
PWT Valid Delay
PWT Float Delay
SCYC Valid Delay
SCYC Float Delay
SMIACT# Valid Delay
W/R# Valid Delay
W/R# Float Delay
7.0 ns
4.5 ns
4.0 ns
7.0 ns
4.0 ns
7.0 ns
4.0 ns
4.0 ns
7.0 ns
92
91
91
92
91
92
91
91
92
1.0 ns
1.0 ns
1.0 ns
1.0 ns
1.0 ns
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15.6
Input Setup and Hold Timings for 100-MHz Bus Operation
Table 59. Input Setup and Hold Timings for 100-MHz Bus Operation
Preliminary Data
Min Max
Symbol
Parameter Description
Figure
t44
t45
A[31:5] Setup Time
A[31:5] Hold Time
A20M# Setup Time
3.0 ns
1.0 ns
3.0 ns
93
93
93
1
t46
1
A20M# Hold Time
1.0 ns
3.5 ns
1.0 ns
1.7 ns
1.0 ns
3.5 ns
1.0 ns
3.0 ns
1.0 ns
3.0 ns
1.0 ns
1.7 ns
1.5 ns
1.7 ns
1.5 ns
3.0 ns
1.0 ns
1.7 ns
1.0 ns
1.7 ns
93
93
93
93
93
93
93
93
93
93
93
93
93
93
93
93
93
93
93
93
t47
t48
t49
t50
t51
t52
t53
t54
t55
t56
t57
t58
t59
t60
t61
t62
t63
t64
t65
AHOLD Setup Time
AHOLD Hold Time
AP Setup Time
AP Hold Time
BOFF# Setup Time
BOFF# Hold Time
BRDY# Setup Time
BRDY# Hold Time
BRDYC# Setup Time
BRDYC# Hold Time
D[63:0] Read Data Setup Time
D[63:0] Read Data Hold Time
DP[7:0] Read Data Setup Time
DP[7:0] Read Data Hold Time
EADS# Setup Time
EADS# Hold Time
EWBE# Setup Time
EWBE# Hold Time
2
FLUSH# Setup Time
t66
2
FLUSH# Hold Time
HOLD Setup Time
HOLD Hold Time
IGNNE# Setup Time
1.0 ns
1.7 ns
1.5 ns
1.7 ns
93
93
93
93
t67
t68
t69
1
t70
1
IGNNE# Hold Time
1.0 ns
93
t71
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Table 59. Input Setup and Hold Timings for 100-MHz Bus Operation (continued)
Preliminary Data
Symbol
Parameter Description
Figure
Min
Max
2
INIT Setup Time
INIT Hold Time
INTR Setup Time
1.7 ns
93
93
93
t72
2
1.0 ns
1.7 ns
t73
1
t74
1
INTR Hold Time
INV Setup Time
INV Hold Time
1.0 ns
1.7 ns
1.0 ns
3.0 ns
1.0 ns
1.7 ns
1.0 ns
1.7 ns
93
93
93
93
93
93
93
93
t75
t76
t77
t78
t79
t80
t81
KEN# Setup Time
KEN# Hold Time
NA# Setup Time
NA# Hold Time
NMI Setup Time
2
t82
2
NMI Hold Time
1.0 ns
1.7 ns
1.0 ns
1.7 ns
93
93
93
93
t83
2
SMI# Setup Time
SMI# Hold Time
STPCLK# Setup Time
t84
2
t85
1
t86
1
STPCLK# Hold Time
WB/WT# Setup Time
WB/WT# Hold Time
1.0 ns
1.7 ns
1.0 ns
93
93
93
t87
t88
t89
Notes:
1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup
and hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.
2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup
and hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and
must remain asserted at least two clocks.
Chapter 15
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AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
15.7
Output Delay Timings for 66-MHz Bus Operation
Table 60. Output Delay Timings for 66-MHz Bus Operation
Preliminary Data
Symbol
Parameter Description
Figure
Min
Max
6.3 ns
10.0 ns
6.0 ns
10.0 ns
7.0 ns
t6
A[31:3] Valid Delay
A[31:3] Float Delay
ADS# Valid Delay
1.1 ns
1.0 ns
1.0 ns
1.0 ns
91
92
91
92
91
92
91
92
91
91
92
91
91
92
91
92
91
92
91
92
91
91
91
91
91
92
91
92
91
t7
t8
t9
ADS# Float Delay
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
t29
t30
t31
t32
t33
t34
ADSC# Valid Delay
ADSC# Float Delay
AP Valid Delay
10.0 ns
8.5 ns
10.0 ns
8.3 ns
7.0 ns
AP Float Delay
APCHK# Valid Delay
BE[7:0]# Valid Delay
BE[7:0]# Float Delay
BREQ Valid Delay
1.0 ns
1.0 ns
10.0 ns
8.0 ns
7.0 ns
1.0 ns
1.0 ns
CACHE# Valid Delay
CACHE# Float Delay
D/C# Valid Delay
10.0 ns
7.0 ns
1.0 ns
1.3 ns
1.3 ns
D/C# Float Delay
10.0 ns
7.5 ns
D[63:0] Write Data Valid Delay
D[63:0] Write Data Float Delay
DP[7:0] Write Data Valid Delay
DP[7:0] Write Data Float Delay
FERR# Valid Delay
HIT# Valid Delay
10.0 ns
7.5 ns
10.0 ns
8.3 ns
6.8 ns
6.0 ns
6.8 ns
7.0 ns
1.0 ns
1.0 ns
1.1 ns
1.0 ns
1.1 ns
HITM# Valid Delay
HLDA Valid Delay
LOCK# Valid Delay
LOCK# Float Delay
M/IO# Valid Delay
M/IO# Float Delay
PCD Valid Delay
10.0 ns
5.9 ns
10.0 ns
7.0 ns
1.0 ns
1.0 ns
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Table 60. Output Delay Timings for 66-MHz Bus Operation (continued)
Preliminary Data
Symbol
Parameter Description
Figure
Min
Max
10.0 ns
7.0 ns
t35
t36
t37
t38
t39
t40
t41
t42
t43
PCD Float Delay
PCHK# Valid Delay
PWT Valid Delay
PWT Float Delay
SCYC Valid Delay
SCYC Float Delay
SMIACT# Valid Delay
W/R# Valid Delay
W/R# Float Delay
92
91
91
92
91
92
91
91
92
1.0 ns
1.0 ns
7.0 ns
10.0 ns
7.0 ns
1.0 ns
10.0 ns
7.3 ns
1.0 ns
1.0 ns
7.0 ns
10.0 ns
Chapter 15
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AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
15.8
Input Setup and Hold Timings for 66-MHz Bus Operation
Table 61. Input Setup and Hold Timings for 66-MHz Bus Operation
Preliminary Data
Min Max
Symbol
Parameter Description
Figure
t44
t45
A[31:5] Setup Time
A[31:5] Hold Time
A20M# Setup Time
6.0 ns
1.0 ns
5.0 ns
93
93
93
1
t46
1
A20M# Hold Time
1.0 ns
5.5 ns
1.0 ns
5.0 ns
1.0 ns
5.5 ns
1.0 ns
5.0 ns
1.0 ns
5.0 ns
1.0 ns
2.8 ns
1.5 ns
2.8 ns
1.5 ns
5.0 ns
1.0 ns
5.0 ns
1.0 ns
5.0 ns
93
93
93
93
93
93
93
93
93
93
93
93
93
93
93
93
93
93
93
93
t47
t48
t49
t50
t51
t52
t53
t54
t55
t56
t57
t58
t59
t60
t61
t62
t63
t64
t65
AHOLD Setup Time
AHOLD Hold Time
AP Setup Time
AP Hold Time
BOFF# Setup Time
BOFF# Hold Time
BRDY# Setup Time
BRDY# Hold Time
BRDYC# Setup Time
BRDYC# Hold Time
D[63:0] Read Data Setup Time
D[63:0] Read Data Hold Time
DP[7:0] Read Data Setup Time
DP[7:0] Read Data Hold Time
EADS# Setup Time
EADS# Hold Time
EWBE# Setup Time
EWBE# Hold Time
2
FLUSH# Setup Time
t66
2
FLUSH# Hold Time
HOLD Setup Time
HOLD Hold Time
IGNNE# Setup Time
1.0 ns
5.0 ns
1.5 ns
5.0 ns
93
93
93
93
t67
t68
t69
1
t70
1
IGNNE# Hold Time
1.0 ns
93
t71
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Table 61. Input Setup and Hold Timings for 66-MHz Bus Operation (continued)
Preliminary Data
Symbol
Parameter Description
Figure
Min
Max
2
INIT Setup Time
INIT Hold Time
INTR Setup Time
5.0 ns
93
93
93
t72
2
1.0 ns
5.0 ns
t73
1
t74
1
INTR Hold Time
INV Setup Time
INV Hold Time
1.0 ns
5.0 ns
1.0 ns
5.0 ns
1.0 ns
4.5 ns
1.0 ns
5.0 ns
93
93
93
93
93
93
93
93
t75
t76
t77
t78
t79
t80
t81
KEN# Setup Time
KEN# Hold Time
NA# Setup Time
NA# Hold Time
NMI Setup Time
2
t82
2
NMI Hold Time
1.0 ns
5.0 ns
1.0 ns
5.0 ns
93
93
93
93
t83
2
SMI# Setup Time
SMI# Hold Time
STPCLK# Setup Time
t84
2
t85
1
t86
1
STPCLK# Hold Time
WB/WT# Setup Time
WB/WT# Hold Time
1.0 ns
4.5 ns
1.0 ns
93
93
93
t87
t88
t89
Notes:
1. These level-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup
and hold times must be met. If asserted asynchronously, they must be asserted for a minimum pulse width of two clocks.
2. These edge-sensitive signals can be asserted synchronously or asynchronously. To be sampled on a specific clock edge, setup
and hold times must be met. If asserted asynchronously, they must have been negated at least two clocks prior to assertion and
must remain asserted at least two clocks.
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Signal Switching Characteristics
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AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
15.9
RESET and Test Signal Timing
Table 62. RESET and Configuration Signals for 100-MHz Bus Operation
Preliminary Data
Min Max
Symbol Parameter Description
Figure
t90
t91
t92
t93
RESET Setup Time
1.7 ns
1.0 ns
94
94
94
94
94
RESET Hold Time
RESET Pulse Width, VCC and CLK Stable
RESET Active After VCC and CLK Stable
15 clocks
1.0 ms
1.0 ms
1
BF[2:0] Setup Time
t94
1
BF[2:0] Hold Time
2 clocks
94
t95
t96
t97
t98
intentionally left blank
intentionally left blank
intentionally left blank
FLUSH# Setup Time
2
1.7 ns
1.0 ns
94
94
94
94
t99
3
FLUSH# Hold Time
FLUSH# Setup Time
FLUSH# Hold Time
t100
3
2 clocks
2 clocks
t101
3
t102
Notes:
1. BF[2:0] must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of RESET.
2. To be sampled on a specific clock edge, setup and hold times must be met the clock edge before the clock edge on which RESET
is sampled negated.
3. If asserted asynchronously, these signals must meet a minimum setup and hold time of two clocks relative to the negation of
RESET.
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Table 63. RESET and Configuration Signals for 66-MHz Bus Operation
Symbol Parameter Description
Preliminary Data
Figure
Min
5.0 ns
Max
t90
t91
t92
t93
RESET Setup Time
94
94
94
94
94
RESET Hold Time
1.0 ns
RESET Pulse Width, VCC and CLK Stable
RESET Active After VCC and CLK Stable
15 clocks
1.0 ms
1
BF[2:0] Setup Time
1.0 ms
t94
1
BF[2:0] Hold Time
2 clocks
94
t95
t96
t97
t98
intentionally left blank
intentionally left blank
intentionally left blank
FLUSH# Setup Time
2
5.0 ns
1.0 ns
94
94
94
94
t99
2
FLUSH# Hold Time
FLUSH# Setup Time
FLUSH# Hold Time
t100
3
2 clocks
2 clocks
t101
3
t102
Notes:
1. BF[2:0] must meet a minimum setup time of 1.0 ms and a minimum hold time of two clocks relative to the negation of RESET.
2. To be sampled on a specific clock edge, setup and hold times must be met the clock edge before the clock edge on which RESET
is sampled negated.
3. If asserted asynchronously, these signals must meet a minimum setup and hold time of two clocks relative to the negation of
RESET.
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Preliminary Information
AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
Table 64. TCK Waveform and TRST# Timing at 25 MHz
Preliminary Data
Symbol
Parameter Description
Figure
Min
Max
TCK Frequency
TCK Period
25 MHz
95
95
95
95
t103
t104
t105
40.0 ns
14.0 ns
14.0 ns
TCK High Time
TCK Low Time
1,2
TCK Fall Time
5.0 ns
5.0 ns
95
95
96
t106
1,2
TCK Rise Time
TRST# Pulse Width
t107
3
30.0 ns
t108
Notes:
1. Rise/Fall times can be increased by 1.0 ns for each 10 MHz that TCK is run below its maximum frequency of 25 MHz.
2. Rise/Fall times are measured between 0.8 V and 2.0 V.
3. Asynchronous.
Table 65. Test Signal Timing at 25 MHz
Preliminary Data
Symbol
Parameter Description
Figure
Min
Max
1
TDI Setup Time
5.0 ns
97
97
97
97
97
97
97
97
97
97
t109
1
TDI Hold Time
9.0 ns
5.0 ns
9.0 ns
3.0 ns
t110
1
TMS Setup Time
t111
1
TMS Hold Time
t112
2
TDO Valid Delay
13.0 ns
16.0 ns
13.0 ns
16.0 ns
t113
2
TDO Float Delay
t114
2
All Outputs (Non-Test) Valid Delay
All Outputs (Non-Test) Float Delay
All Inputs (Non-Test) Setup Time
All Inputs (Non-Test) Hold Time
3.0 ns
t115
2
t116
1
5.0 ns
9.0 ns
t117
1
t118
Notes:
1. Parameter is measured from the TCK rising edge.
2. Parameter is measured from the TCK falling edge.
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AMD-K6™-2E Processor Data Sheet
15.10
Timing Diagrams
WAVEFORM
INPUTS
OUTPUTS
Must be steady
Steady
Can change from
High to Low
Changing from High to Low
Changing from Low to High
Changing, State Unknown
Can change
from Low to High
Don’t care, any
change permitted
(Does not apply)
Center line is high
impedance state
Figure 90. Key to Timing Diagrams
Tx
Tx
1.5 V
CLK
Max
tv
Min
Output Signal
Valid n
Valid n +1
Note: For symbols tv listed in Table 58 on page 270 and Table 60 on page 274, where:
v = 6, 8, 10, 12, 14, 15, 17, 18, 20, 22, 24, 26, 27, 28, 29, 30, 32, 34, 36, 37, 39, 41, 42
Figure 91. Output Valid Delay Timing
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Preliminary Information
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22529B/0—January 2000
Tx
Tx
Tx
Tx
1.5 V
CLK
tf
Output Signal
Valid
tv
Min
Note: For symbols tv and tf listed in Table 58 on page 270 and Table 60 on page 274, where:
v = 6, 8, 10, 12, 15, 18, 20, 22, 24, 30, 32, 34, 37, 39, 42
f = 7, 9, 11, 13, 16, 19, 21, 23, 25, 31, 33, 35, 38, 40, 43
Figure 92. Maximum Float Delay Timing
Tx
Tx
Tx
Tx
1.5 V
CLK
ts
th
Input Signal
Note: For symbols ts and th listed in Table 59 on page 272 and Table 61 on page 276, where:
s = 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72, 74, 76, 78, 80, 82, 84, 86, 88
h = 45, 47, 49, 51, 53, 55, 57, 59, 61, 63, 65, 67, 69, 71, 73, 75, 77, 79, 81, 83, 85, 87, 89
Figure 93. Input Setup and Hold Timing
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AMD-K6™-2E Processor Data Sheet
Tx
Tx
1.5 V
CLK
• • •
• • •
t90
t91
RESET
1.5 V
1.5 V
t92, 93
t99
t100
FLUSH#
(Synchronous)
• • •
FLUSH#
(Asynchronous)
• • •
t101
t102
BF[2:0]
(Asynchronous)
• • •
t94
t95
Figure 94. Reset and Configuration Timing
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22529B/0—January 2000
t104
2.0 V
1.5 V
t105
0.8 V
t106
t107
t103
Figure 95. TCK Timing
t108
1.5 V
Figure 96. TRST# Timing
t103
1.5 V
TCK
TDI, TMS
TDO
t109, 111 t110, 112
t114
t113
t116
t115
Output
Signals
Input
Signals
t117
t118
Figure 97. Test Signal Timing
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AMD-K6™-2E Processor Data Sheet
16
Thermal Design
16.1
Package Thermal Specifications
The AMD-K6-2E processor operating specification calls for the
case temperature (T ) to be in the range of 0°C to 70°C (for the
C
standard-power 2.2-V component) or 0°C to 85°C (for the low-
power 1.9-V component). The ambient temperature (T ) is not
A
specified as long as the case temperature is not violated. The
case temperature must be measured on the top center of the
package. Table 66 and Table 67 show the package thermal
specifications for the AMD-K6-2E processor.
Table 66. Package Thermal Specification for OPN Suffix AMZ (Low-Power Devices)
Maximum Thermal Power
q
JC
Junction-Case
233 MHz
266 MHz
300 MHz
333 MHz
350 MHz
9.00 W
10.00 W
10.00 W
10.00 W
11.00 W
1.0 °C/W
1.20 W
1.00 W
1.20 W
1.00 W
1.20 W
1.00 W
1.20 W
1.00 W
1.20 W
1.00 W
Stop Grant Mode
Stop Clock Mode
0°C–85°C
T Case Temperature
C
Table 67. Package Thermal Specification for OPN Suffix AFR (Standard-Power Devices)
Maximum Thermal Power
q
JC
Junction-Case
233 MHz 266 MHz 300 MHz 333 MHz 350 MHz 400 MHz
13.50 W
2.46 W
2.25 W
14.70 W
2.48 W
2.25 W
17.20 W
2.50 W
2.25 W
19.00 W
3.94 W
3.50 W
19.95 W
3.96 W
3.50 W
16.90 W
4.40 W
4.00 W
1.0 °C/W
Stop Grant Mode
Stop Clock Mode
0°C–70°C
T Case Temperature
C
Chapter 16
Thermal Design
285
Preliminary Information
AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
Figure 98 shows the thermal model of a processor with a passive
thermal solution. The ambient temperature (T ) is guaranteed
A
as long as T is not violated. The case-to-ambient temperature
C
(T ) can be calculated from the following equation:
CA
TCA
= PMAX • qCA
= PMAX • ( qIF + qSA
)
Where:
PMAX
qCA
qIF
qSA
= Maximum Power Consumption
= Case-to-Ambient Thermal Resistance
= Interface Material Thermal Resistance
= Sink-to-Ambient Thermal Resistance
Thermal
Resistance
(°C/W)
Temperature
(Ambient)
TCA
qSA
qCA
Sink
Case
qIF
Figure 98. Thermal Model
Figure 99 illustrates the case-to-ambient temperature
(T =T – T ) in relation to the power consumption (X-axis)
CA
C
A
and the thermal resistance (Y-axis). If the power consumption
and case temperature are known, the thermal resistance (q
)
CA
requirement can be calculated for a given ambient temperature
(T ) value.
A
286
Thermal Design
Chapter 16
Preliminary Information
22529B/0—January 2000
AMD-K6™-2E Processor Data Sheet
&DVHꢁWRꢁ$PELHQWꢂ7HPSHUDWXUH
ꢃ7 ꢂꢁꢂ7 ꢄ
Figure 99. Power Consumption v. Thermal Resistance
The thermal resistance of a heatsink is determined by the heat
dissipation surface area, the material and shape of the
heatsink, and the airflow volume across the heatsink. In
general, the larger the surface area the lower the thermal
resistance.
The required thermal resistance of a heatsink (qSA) can be
calculated using the following example:
If:
TC = 70°C
TA = 45°C
PMAX = 19.95 W at 350 MHz (Standard-power AMD-K6-2E/350AFR)
Then:
T
– T
Ë
Û
C
A
25C
(C W)
q
-------------------- = --------------------- = 1.25
Ì
Ü
CA
19.95W
P
Í
Ý
MAX
Chapter 16
Thermal Design
287
Preliminary Information
AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
Thermal grease is recommended as interface material because
it provides the lowest thermal resistance (@ 0.20°C/W). The
required thermal resistance (q ) of the heatsink in this
SA
example is calculated as follows:
qSA = qCA – qIF = 1.25 – 0.20 = 1.05(°C/W)
Heat Dissipation Path
Figure 100 illustrates the heat dissipation path of the processor.
Due to the lower thermal resistance between the processor die
junction and case, most of the heat generated by the processor
is transferred from the top surface of the case. The small
amount of heat generated from the bottom side of the processor
where the processor socket blocks the convection can be safely
ignored.
Ambient Temperature
Thin Lid
Case temperature
Figure 100. Processor Heat Dissipation Path
16.2
Measuring Case Temperature
The processor case temperature is measured to ensure that the
thermal solution meets the processor’s operational
specification. This temperature should be measured on the top
center of the package, where most of the heat is dissipated.
Figure 101 on page 289 shows the correct location for measuring
the case temperature. The tip of the thermocouple should be
secured to the package surface with a small amount of
thermally conductive epoxy. A second location along the
thermocouple should also be secured to avoid any movement
during testing.
If a heatsink is installed while measuring, the thermocouple
must be installed into the heatsink via a small hole drilled
through the heatsink base (e.g., 1/16 of an inch). Secure the
thermocouple to the base of the heatsink by filling the small
hole with thermal epoxy, allowing the tip of the thermocouple
to protrude the epoxy and touch the top of the processor case.
288
Thermal Design
Chapter 16
Preliminary Information
22529B/0—January 2000
AMD-K6™-2E Processor Data Sheet
Thermally Conductive Epoxy
Thermocouple
Figure 101. Measuring Case Temperature
16.3
Sample Heatsink Measured Data
The example measured data (provided in tables 69 through 72
and figures 105 through 108) shows case-to-ambient thermal
resistance and maximum ambient temperature for both
socketed and soldered processors using three passive heatsink
samples with different height profiles (see Table 68) and
different levels of airflow in the system. This data is based on
the following specification assumptions:
TC = 85°C = TC(MAX) for 1.9-V low-power K6-2E processors
Pd = 10 W
q
CA= qSA + qIF
TA(MAX) = TC(MAX) – (qCA·Pd)
TA(MAX) = 85 - (qSA+ qIF)·Pd
Note: AMD does not guarantee the example measured heatsink
data provided in tables 69 through 72 and figures 105
through 108. This data is supplied for informational
purposes only to facilitate the selection of an appropriate
thermal solution.
Example Heatsinks
Table 68 describes the three heatsinks tested. Figure 102,
Figure 103, and Figure 104 show the actual heatsinks.
Table 68. Passive Heatsink Samples
Identifier Size X (mm) Size Y (mm) Size Z Height (mm)
A
B
C
52
52
50
50
50
50
15
20
30
Chapter 16
Thermal Design
289
Preliminary Information
AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
Figure 102. Heatsink A (15 mm height)
Figure 103. Heatsink B (20 mm height)
Figure 104. Heatsink C (30 mm height)
290
Thermal Design
Chapter 16
Preliminary Information
22529B/0—January 2000
AMD-K6™-2E Processor Data Sheet
Socketed Installation:
Case-to-Ambient
Thermal Resistance
Table 69 and Figure 105 show the measured values for the case-
to-ambient thermal resistance (q in °C/watt) at different
CA
levels of airflow in the system for the low-power embedded
AMD-K6-2E processors with a maximum thermal power
dissipation of 10.0 watts (OPNs: AMD-K6-2E/266AMZ,
AMD-K6-2E/300AMZ, and AMD-K6-2E/333AMZ) and a
maximum case temperature rating of 85°C, in the 321-pin
Ceramic Pin Grid Array package (CPGA) when installed into a
socket.
Table 69. Socketed CPGA Package: Measured Thermal Resistance (°C/W) q and q
JC
CA
q
(°C/W) v. Airflow (m/s)
CA
q (°C/W)
Heatsink Type
JC
0.0 m/s
9.1
1.0 m/s
7.5
2.0 m/s
6.1
3.0 m/s
4.7
4.0 m/s
4.0
No Heatsink
A (15 mm)
B (20 mm)
C (30 mm)
1.0
1.0
1.0
1.0
6.5
4.3
3.1
2.6
2.3
5.7
3.8
2.7
2.3
2.0
4.7
2.8
1.8
1.5
1.3
10
9
8
7
6
5
4
3
2
1
0
None
A
B
C
0
1
2
3
4
Airflow Rate (m/s)
Figure 105. Measured Thermal Resistance v. Airflow (Socketed 321-Pin CPGA Package)
Chapter 16
Thermal Design
291
Preliminary Information
AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
Socketed Installation:
Maximum Ambient
Temperature
Table 70 and Figure 106 show the measured maximum ambient
temperature (T ) values in °C at different levels of airflow in
A
the system for the low-power embedded AMD-K6-2E processors
with a maximum thermal power dissipation of 10.0 watts (for
OPNs: AMD-K6-2E/266AMZ, AMD-K6-2E/300AMZ, and
AMD-K6-2E/333AMZ) and a maximum case temperature rating
of 85 °C, in the 321-pin Ceramic Pin Grid Array package (CPGA)
when installed into a socket.
Table 70. Socketed CPGA Package: Measured Maximum Ambient Temperature (°C)
Maximum T (°C) v. Airflow (m/s)
A
Heatsink Type
0.0 m/s
-10°C
20°C
1.0 m/s
6°C
2.0 m/s
21°C
3.0 m/s
36°C
4.0 m/s
43°C
No Heatsink
A (15 mm)
B (20 mm)
C (30mm)
42°C
47°C
57°C
54°C
59°C
62°C
28°C
58°C
62°C
65°C
38°C
67°C
70°C
72°C
TC = 85°C, Pd = 10 W
80
70
60
50
40
30
20
10
0
1RQH
$
%
&
-10
-20
0
1
2
3
4
Airflow Rate (m/s)
Figure 106. Measured Maximum Ambient Temperature (Socketed 321-Pin CPGA Package)
292
Thermal Design
Chapter 16
Preliminary Information
22529B/0—January 2000
AMD-K6™-2E Processor Data Sheet
Soldered Installation:
Case-to-Ambient
Thermal Resistance
Table 71 and Figure 107 show the measured values for the case-
to-ambient thermal resistance (q in °C/watt) at different
CA
levels of airflow in the system for the low-power embedded
AMD-K6-2E processors with a maximum thermal power
dissipation of 10.0 watts (OPNs: AMD-K6-2E/266AMZ,
AMD-K6-2E/300AMZ, and AMD-K6-2E/333AMZ) and a
maximum case temperature rating of 85°C, in the 321-pin
Ceramic Pin Grid Array package (CPGA) when soldered into a
printed circuit board.
.
Table 71. Soldered CPGA Package: Measured Thermal Resistance (°C/W) q and q
JC
CA
q
(°C/W) v. Airflow (m/s)
CA
q (°C/W)
Heatsink Type
JC
0.0 m/s
7.0
1.0 m/s
5.2
2.0 m/s
4.2
3.0 m/s
3.3
4.0 m/s
2.7
No Heatsink
A (15 mm)
B (20 mm)
C (30 mm)
1.0
1.0
1.0
1.0
5.2
3.4
2.4
1.9
1.7
4.9
2.9
2.0
1.5
1.3
4.3
2.5
1.6
1.4
1.2
8
7
6
5
4
3
2
1
0
1RQH
$
%
&
0
1
2
3
4
Airflow Rate (m/s)
Figure 107. Measured Thermal Resistance v. Airflow (Soldered 321-Pin CPGA Package)
Chapter 16
Thermal Design
293
Preliminary Information
AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
Soldered Installation:
Maximum Ambient
Temperature
Table 72 and Figure 108 show the measured maximum ambient
temperature (T ) values in °C at different levels of airflow in
A
the system for the low-power embedded AMD-K6-2E processors
with a maximum thermal power dissipation of 10.0 watts (for
OPNs: AMD-K6-2E/266AMZ, AMD-K6-2E/300AMZ, and
AMD-K6-2E/333AMZ) and a maximum case temperature rating
of 85 °C, in the 321-pin Ceramic Pin Grid Array package (CPGA)
when soldered into a printed circuit board.
.
Table 72. Soldered CPGA Package: Measured Maximum Ambient Temperature (°C)
Maximum T (°C) v. Airflow (m/s)
A
Heatsink Type
0.0 m/s
14°C
1.0 m/s
31°C
2.0 m/s
42°C
3.0 m/s
53°C
4.0 m/s
58°C
No Heatsink
A (15 mm)
B (20 mm)
C (30 mm)
33°C
51°C
61°C
66°C
68°C
36°C
56°C
65°C
70°C
72°C
42°C
60°C
69°C
71°C
73°C
ꢀ
TC = 85°C, Pd = 10 W
80
70
60
50
40
30
20
10
0
1RQH
$
%
&
0
1
2
3
4
Airflow Rate (m/s)
Figure 108. Measured Maximum Ambient Temperature (Soldered, 321-Pin CPGA Package)
294
Thermal Design
Chapter 16
Preliminary Information
22529B/0—January 2000
AMD-K6™-2E Processor Data Sheet
16.4
Layout and Airflow Considerations
Voltage Regulator
A voltage regulator is required to support the lower voltage
(3.3 V and lower) to the processor. In most applications, the
voltage regulator is designed with power transistors. As a
result, additional heatsinks are required to dissipate the heat
from the power transistors. Figure 109 shows the voltage
regulator placed parallel to the processor with the airflow
aligned with the devices. With this alignment, the heat
generated by the voltage regulator has minimal effect on the
processor.
Voltage Regulator
Airflow
Processor
Figure 109. Voltage Regulator Placement
A heatsink and fan combination can deliver much better
thermal performance than a heatsink alone. More importantly,
with a fan/sink, the airflow requirements in a system design are
not as critical. A unidirectional heatsink with a fan moves air
from the top of the heatsink to the side. In this case, the best
location for the voltage regulator is on the side of the processor
in the path of the airflow exiting the fan sink (see Figure 110 on
page 296). This location guarantees that the heatsinks on both
the processor and the regulator receive adequate air
circulation.
Chapter 16
Thermal Design
295
Preliminary Information
AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
Airflow
Ideal areas for voltage regulator
Figure 110. Airflow for a Heatsink with Fan
Airflow Management
in a System Design
Complete airflow management in a system is important. In
addition to the volume of air, the path of the air is also
important. Figure 111 shows the airflow in a dual-fan system.
The fan in the front end pulls cool air into the system through
intake slots in the chassis. The power supply fan forces the hot
air out of the chassis. The thermal performance of the heatsink
can be maximized if it is located in the shaded area, where it
receives greatest benefit from this air exchange system.
Fan
P/S
Main Board
V
e
n
t
Drive Bays
s
Fan
Vents
Front
Figure 111. Airflow Path in a Dual-Fan System
296
Thermal Design
Chapter 16
Preliminary Information
22529B/0—January 2000
AMD-K6™-2E Processor Data Sheet
Figure 112 shows the airflow management in a system using the
ATX form-factor. The orientation of the power supply fan and
the motherboard are modified in the ATX platform design. The
power supply fan pulls cool air through the chassis and across
the processor. The processor is located near the power supply
fan, where it can receive adequate airflow without an auxiliary
fan. The arrangement significantly improves the airflow across
the processor with minimum installation cost.
Main Board
F
P/S
a
n
Drive Bays
Figure 112. Airflow Path in an ATX Form-Factor System
For more information about thermal design considerations, see
®
the AMD-K6 Processor Thermal Solution Design Application
Note, order #21085.
Chapter 16
Thermal Design
297
Preliminary Information
AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
298
Thermal Design
Chapter 16
Preliminary Information
22529B/0—January 2000
AMD-K6™-2E Processor Data Sheet
17
Pin Designation Diagrams
Figure 113. AMD-K6™-2E Processor Connection Diagram (Top-Side View CPGA)
Chapter 17
Pin Designation Diagrams
299
Preliminary Information
AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
Figure 114. AMD-K6™-2E Processor Connection Diagram (Bottom-Side View CPGA)
300
Pin Designation Diagrams
Chapter 17
Preliminary Information
22529B/0—January 2000
AMD-K6™-2E Processor Data Sheet
17.1
Pin Designations by Functional Grouping
Pin Name
Pin Number
Pin Name
Pin Number
Pin Name
Pin Number
Data
Pin Name
D52
Pin Number
Data
Control
Address
A20M#
ADS#
ADSC#
AHOLD
APCHK#
BE0#
BE1#
BE2#
BE3#
BE4#
AK-08
AJ-05
AM-02
V-04
AE-05
AL-09
AK-10
AL-11
AK-12
AL-13
AK-14
AL-15
AK-16
Y-33
X-34
W-35
Z-04
A3
A4
A5
A6
A7
A8
A9
AL-35
AM-34
AK-32
AN-33
AL-33
AM-32
AK-30
AN-31
AL-31
AL-29
AK-28
AL-27
AK-26
AL-25
AK-24
AL-23
AK-22
D0
K-34
G-35
J-35
E-03
G-05
E-01
G-03
H-04
J-03
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
G-33
F-36
F-34
E-35
E-33
D-34
C-37
C-35
B-36
D-32
B-34
C-33
A-35
B-32
C-31
A-33
D-28
B-30
C-29
A-31
D-26
C-27
C-23
D-24
C-21
D-22
C-19
D-20
C-17
C-15
D-16
C-13
D-14
C-11
D-12
C-09
D-10
D-08
A-05
E-09
B-04
D-06
C-05
E-07
C-03
D-04
E-05
D-02
F-04
J-05
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
K-04
L-05
L-03
M-04
N-03
BE5#
BE6#
BE7#
BF0
BF1
BF2
Test
TCK
TDI
TDO
TMS
TRST#
M-34
N-35
N-33
P-34
Q-33
BOFF#
BRDY#
BRDYC#
BREQ
CACHE#
CLK
X-04
Y-03
AJ-01
AL-21
AF-34
AH-36
D17
D18
D19
Parity
AP
AK-02
D-36
D-30
C-25
D-18
C-07
F-06
F-02
N-05
U-03
AE-33
AG-35
AJ-35
AH-34
AG-33
AK-36
AK-34
AM-36
AJ-33
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
DP0
DP1
DP2
DP3
DP4
DP5
DP6
DP7
AK-18
AK-04
AM-04
W-03
Q-05
AN-07
AK-06
AL-05
AJ-03
AB-04
AA-35
AA-33
AD-34
U-05
D/C#
EADS#
EWBE#
FERR#
FLUSH#
HIT#
HITM#
HLDA
HOLD
IGNNE#
INIT
INTR
INV
KEN#
LOCK#
M/IO#
NA#
NMI
PCD
W-05
AH-04
T-04
Y-05
AC-33
AG-05
AF-04
AL-03
AK-20
AL-17
AB-34
AG-03
V-34
AL-01
AN-05
AM-06
AA-05
PCHK#
PWT
RESET
SCYC
SMI#
SMIACT#
STPCLK#
VCC2DET
VCC2H/L#
W/R#
WB/WT#
Chapter 17
Pin Designation Diagrams
301
Preliminary Information
AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
Pin Numbers
VCC2
VCC3
VSS
VSS
No Connect (NC)
AJ-27
AJ-31
AJ-37
A-37
E-17
E-25
R-34
S-33
S-35
W-33
AJ-15
AJ-23
AL-19
AN-35
A-07
A-09
A-11
A-13
A-15
A-17
B-02
E-15
G-01
J-01
A-19
A-21
A-23
A-25
A-27
A-29
E-21
E-27
E-37
G-37
J-37
A-03
B-06
B-08
B-10
B-12
B-14
B-16
B-18
B-20
B-22
B-24
AL-37
AM-08
AM-10
AM-12
AM-14
AM-16
AM-18
AM-20
L-01
N-01
L-33
B-26
AM-22
Internal No Connect (INC)
Q-01
L-37
B-28
AM-24
C-01
H-34
Y-35
Z-34
AC-35
AL-07
AN-01
AN-03
S-01
N-37
Q-37
S-37
T-34
U-33
U-37
E-11
E-13
E-19
E-23
E-29
E-31
H-02
H-36
K-02
AM-26
AM-28
AM-30
AN-37
U-01
W-01
Y-01
AA-01
AC-01
AE-01
AG-01
AJ-11
W-37
Y-37
Reserved (RSVD)
J-33
AA-37
L-35
P-04
Q-03
Q-35
R-04
S-03
S-05
AA-03
AC-03
AC-05
AD-04
AE-03
AE-35
AN-09
AN-11
AN-13
AN-15
AN-17
AN-19
AC-37
AE-37
AG-37
AJ-19
AJ-29
AN-21
AN-23
AN-25
AN-27
AN-29
K-36
M-02
M-36
P-02
P-36
R-02
R-36
T-02
T-36
U-35
V-02
V-36
X-02
X-36
Z-02
Key
AH-32
Z-36
AB-02
AB-36
AD-02
AD-36
AF-02
AF-36
AH-02
AJ-07
AJ-09
AJ-13
AJ-17
AJ-21
AJ-25
302
Pin Designation Diagrams
Chapter 17
Preliminary Information
22529B/0—January 2000
AMD-K6™-2E Processor Data Sheet
18
Package Specifications
18.1
321-Pin Staggered CPGA Package Specification
1.940
1.960
1.795
1.805
A
B
.100
.050
1.940 1.795
1.960 1.805
.064 MAX
.060
.090
(45¡ Chamfer)
Index Corner
1.940
1.960
A
C
1.768
1.776
.005
F
1.221
1.295
B
.120
.130
.017
.020
321 x
M
M
M
B
.030
.010
C A
C
M
1.940 1.768 1.221
1.960 1.776 1.295
1.768
1.776
1.221
1.295
.100
Lid
.050
.051
.060
.115
.143
.060
.090
Index Corner
(45¡ Chamfer)
SIDE VIEW OF CPGA
16-038-CP-5_AC
CGF321
EU160
ALL MEASUREMENTS ARE IN INCHES UNLESS OTHERWISE NOTED.
4.27.99 lv
Figure 115. 321-Pin Staggered CPGA Package Specification
Chapter 18 Package Specifications
303
Preliminary Information
AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
304
Package Specifications
Chapter 18
Preliminary Information
22529B/0—January 2000
AMD-K6™-2E Processor Data Sheet
19
Ordering Information
AMD standard- and low-power products are available in several operating ranges. The
ordering part number (OPN) is formed by a combination of the elements below. See
Table 73 on page 306 for valid ordering part number combinations.
AMD-K6-2E/ 400
A F R
Case Temperature
R = 0°C–70°C
Z = 0°C–85°C
Operating Voltage
F = 2.1 V–2.3 V (Core) / 3.135 V–3.6 V (I/O)
M = 1.8 V–2.0 V (Core) / 3.135 V–3.6 V (I/O)
Package Type
A = 321-pin Ceramic Pin Grid Array (CPGA)
Performance Rating
/400 = 400 MHz
/350 = 350 MHz
/333 = 333 MHz
/300 = 300 MHz
/266 = 266 MHz
/233 = 233 MHz
Family/Core
AMD-K6-2E Embedded Processor
Chapter 19
Ordering Information
305
Preliminary Information
AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
Table 73. Valid Ordering Part Number Combinations1
Device
Case
Temperature
Maximum CPU/Bus
Frequency
OPN
Package Type Operating Voltage
Type
AMD-K6-2E/350AMZ
321-pin CPGA 1.8V–2.0V (Core)
3.135V–3.6V (I/O)
0°C–85°C
0°C–85°C
0°C–85°C
0°C–85°C
0°C–85°C
0°C–70°C
0°C–70°C
0°C–70°C
0°C–70°C
0°C–70°C
0°C–70°C
350 MHz/100 MHz
Low
Power
333 MHz/95 MHz2
300 MHz/100 MHz2
266 MHz/66 MHz
233 MHz/66 MHz
400 MHz/100 MHz2
350 MHz/100 MHz
333 MHz/95 MHz2
300 MHz/100 MHz2
266 MHz/66 MHz
233 MHz/66 MHz
AMD-K6-2E/333AMZ
AMD-K6-2E/300AMZ
AMD-K6-2E/266AMZ
AMD-K6-2E/233AMZ
AMD-K6-2E/400AFR
AMD-K6-2E/350AFR
AMD-K6-2E/333AFR
AMD-K6-2E/300AFR
AMD-K6-2E/266AFR
AMD-K6-2E/233AFR
321-pin CPGA 1.8V–2.0V (Core)
3.135V–3.6V (I/O)
321-pin CPGA 1.8V–2.0V (Core)
3.135V–3.6V (I/O)
321-pin CPGA 1.8V–2.0V (Core)
3.135V–3.6V (I/O)
321-pin CPGA 1.8V–2.0V (Core)
3.135V–3.6V (I/O)
321-pin CPGA 2.1V–2.3V (Core)
3.135V–3.6V (I/O)
Standard
Power
321-pin CPGA 2.1V–2.3V (Core)
3.135V–3.6V (I/O)
321-pin CPGA 2.1V–2.3V (Core)
3.135V–3.6V (I/O)
321-pin CPGA 2.1V–2.3V (Core)
3.135V–3.6V (I/O)
321-pin CPGA 2.1V–2.3V (Core)
3.135V–3.6V (I/O)
321-pin CPGA 2.1V–2.3V (Core)
3.135V–3.6V (I/O)
Notes:
1. This table lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm
availability of specific valid combinations and to check on newly-released combinations.
2. Also supports 66-MHz bus operation.
306
Ordering Information
Chapter 19
Preliminary Information
22529B/0—January 2000
AMD-K6™-2E Processor Data Sheet
Index
clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Numerics
0.25-Micron Process Technology . . . . . . . . . . . . . . . . . . . . . . . 4
100-MHz Bus
connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . 299–300
DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
decode logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
floating-point unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
low-power devices . . . . . . . . . . . . . . . . . . 255–256, 261, 306
microarchitecture overview . . . . . . . . . . . . . . . . . . . . . . . . 7
multimedia execution unit . . . . . . . . . . . . . . . . . . . . . . . 213
operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
package specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
pin connection requirements . . . . . . . . . . . . . . . . . . . . . 264
pin designations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
power-on initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . 179
process technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
signal switching characteristics . . . . . . . . . . . . . . . . . . . 267
Socket 7 platform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
software environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
standard-power devices. . . . . . . . . . . . . . 255–256, 260, 306
Super7 platform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
System Management Mode (SMM) . . . . . . . . . . . . . . . . 217
test and debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
thermal design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
write merge buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
AP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
APCHK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Application Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Asserted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
clock switching characteristics . . . . . . . . . . . . . . . . . . . . 268
input setup and hold timings. . . . . . . . . . . . . . . . . . . . . . 272
output delay timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
321-Pin Staggered CPGA
package specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
3DNow!™ Technology. . . . . . . . . . . . . . . . . . . . . . . . . .3, 15–20
data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–20
INIT state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
instruction compatibility, floating-point and. . . . . . . . . 216
instructions . . . . . . . . . . . . . . . . . . . . . . 13, 56, 81, 197, 216
PREFETCH instruction . . . . . . . . . . . . . . . . . . . . . . . . . . 197
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
RESET state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118, 179
software prefetching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
4-Kbyte Paging Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4-Mbyte Paging Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . 50
66-MHz Bus
clock switching characteristics . . . . . . . . . . . . . . . . . . . . 268
input setup and hold timings. . . . . . . . . . . . . . . . . . . . . . 276
output delay timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
A
A[31:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
A20M# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
masking cache accesses with. . . . . . . . . . . . . . . . . . . . . . 204
Absolute Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Accelerated Graphic Port (AGP). . . . . . . . . . . . . . . . . . . . . 4–5
Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
bus . . . . . . . . . . . . . . . . . . . .87–92, 101, 154, 158, 160, 199
generation sequence during bursts. . . . . . . . . . . . . . . . . 142
hold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
parity check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
ADS# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
ADSC# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
AGP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5
AHOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
-initiated inquire hit to modified line. . . . . . . . . . . 158–159
-initiated inquire hit to shared or exclusive line . . 156–157
-initiated inquire miss . . . . . . . . . . . . . . . . . . . . . . . 154–155
restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160–161
Airflow
consideration, layout and. . . . . . . . . . . . . . . . . . . . . . . . . 295
heatsink with fan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
path in a dual-fan system. . . . . . . . . . . . . . . . . . . . . . . . . 296
path in an ATX form-factor system. . . . . . . . . . . . . . . . . 297
Allocate, Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
AMD-K6™-2E Processor
3DNow!™ technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
absolute ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
bus cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
cache organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
B
Backoff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
BE[7:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
BF[2:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93, 179
BIST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
BOFF# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94, 162–163
locked operation with . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Boundary-Scan
bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
register (BSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
test access port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
BR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Branch
execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
history table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 3, 11, 20–21
target cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
BRDY#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
BRDYC# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
BREQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
BSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Built-In Self-Test (BIST) . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Index
307
Preliminary Information
AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
Burst
Capture-DR state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Capture-IR state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285, 297
extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
measuring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288–289
Centralized Scheduler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97, 269
switching characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 267
100-MHz bus operation . . . . . . . . . . . . . . . . . . . . . . . . 268
66-MHz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . 268
pipelined burst reads . . . . . . . . . . . . . . . . . . . . . . . . 142–143
reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142–143
ready. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
ready copy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
writeback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
writeback due to cache-line replacement. . . . . . . . . . . . 145
Bus
address. . . . . . . . . . . . . . . . .89–92, 101, 154, 158, 160, 199
arbitration cycles, inquire and . . . . . . . . . . . . . . . . . . . . 148
backoff (BOFF#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
order during misaligned I/O transfers . . . . . . . . . . . . 147
order during misaligned memory transfers . . . . . . . . 140
special . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97, 247
states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
stop clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173, 252
stop grant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173, 250
stop grant inquire . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
transitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
switching characteristics
100-MHz bus operation . . . . . . . . . . . . . . . . . . . . . . . . 268
66-MHz bus operation . . . . . . . . . . . . . . . . . . . . . . . . . 268
Coherency
cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
writethrough. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Configuration
power-on initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Control Register 0 (CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Control Register 1 (CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Control Register 2 (CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Control Register 3 (CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Control Register 4 (CR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Counter, Time Stamp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Customer Service. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii
Cycles
bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
hold and hold acknowledge . . . . . . . . . . . . . . . . . . . . . . 148
inquire. . . . 86–91, 101, 105–106, 122, 129, 144, 152, 154,
. . . 156–158, 160, 162, 166, 199, 202–204, 239, 247,
data. . . .92, 95, 99–100, 116, 120, 136–138, 154, 160, 164
enables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
hold request. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
lock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
states
address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
data-NA# requested . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
pipeline address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
pipeline data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
state machine diagram. . . . . . . . . . . . . . . . . . . . . . . . . 135
transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
BYPASS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Bypass Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
C
Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
cacheable access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
coherency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
writeback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
writethrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
disabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249–251
inquire and bus arbitration. . . . . . . . . . . . . . . . . . . . . . . 148
interrupt acknowledge . . . . . 87, 90, 92, 98, 114, 128, 132
locked . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
pipelined. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13, 88
pipelined write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
special . . . . . . . . . . . . . . . . . . . . . . . .132, 170, 223, 249–250
writeback . .86, 88–89, 102, 105, 129, 144, 152, 156, 158,
. . . . . . . . . . . . 160, 162, 166, 188–189, 240, 248, 251
flushing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104, 190
inhibit, L1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
instruction prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
L1 . . . . . . . . . . . . . . . . . . . 42, 185, 192, 196, 199, 204, 227
-line fills. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
-line replacement . . . . . . . . . . . . . . . . . . . . . . . . . . .192, 201
masking cache accesses with A20M# . . . . . . . . . . . . . . . 204
MESI states in the data cache . . . . . . . . . . . . . . . . . . . . . 186
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12, 185, 205
predecode bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
related signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
sector organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
snooping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
write allocate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
write to cacheable page . . . . . . . . . . . . . . . . . . . . . . . . . . 193
D
D/C#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
D[63:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
bus . . . . 92, 95, 99–100, 116, 120, 136–138, 154, 160, 164
cache, MESI states in the . . . . . . . . . . . . . . . . . . . . . . . . 186
parity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Data Types
3DNow!™ technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
floating-point register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
integer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
MMX technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
writeback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8, 12, 204
writethrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
CACHE#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97, 189
308
Index
Preliminary Information
22529B/0—January 2000
AMD-K6™-2E Processor Data Sheet
Data/Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Data-NA# Requested . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
in System Management Mode (SMM). . . . . . . . . . . . . . . 226
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37, 241
DR3, DR2, DR1, and DR0 . . . . . . . . . . . . . . . . . . .39, 243
DR3–DR0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
DR5 and DR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38, 242
DR5–DR4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
DR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38, 242, 244
DR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37, 241, 244
Execution Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1, 18
3DNow!™ technology. . . . . . . . . . . . . . . . . . . . . . . . . . 19–20
floating-point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
multimedia . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–20, 215
register X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–20
register Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19–20
Extended Feature Enable Register (EFER) .40, 43, 182, 206
External
address strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
write buffer empty. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
EXTEST Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 9
Decoupling Recommendations . . . . . . . . . . . . . . . . . . . . . . 263
Derating, Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Descriptors and Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Device Identification Register (DIR) . . . . . . . . . . . . . . . . . 234
Diagrams
key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
waveform definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
DIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Disabling
cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
DP[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
DR3–DR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
DR5–DR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
DR6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
DR7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
LEN and RW definitions . . . . . . . . . . . . . . . . . . . . . . . . . 245
Driven. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Dual Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
F
FEMMS Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
FERR#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103, 214, 216
Float Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Float Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
Floated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Floating-Point
and MMX/3DNow!™ instruction compatibility . . . . . . 216
and multimedia execution units. . . . . . . . . . . . . . . . . . . 213
error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
handling exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
register data types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
FLUSH# . . . . . . . . . . . . . . . . . . . . . . . . . . . .104, 179, 200, 228
FPU
control word register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
status word register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
tag word register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268, 280
multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
operating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93, 97, 179
E
EADS# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
EAX Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
EFER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40, 43, 182, 206
EFLAGS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
absolute ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
I/O buffer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 264
operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
power and grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
power derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Embedded Processor Features . . . . . . . . . . . . . . . . . . . . . . 1–2
EMMS Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
EWBE#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102, 205
EWBE# Control (EWBEC) . . . . . . . . . . . . . . . . . . . . . .205, 207
Exception. . . . . . . . 90–91, 100, 103, 116, 216, 226, 244–246
debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225, 245
flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28–29
floating-point. . . . . . . . . . . . . . . . . . 103, 108, 213–214, 216
handler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
machine-check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
MMX technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
shutdown cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
System Management Mode (SMM). . . . . . . . . . . . . . . . . 226
Execution Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
G
Gate Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52, 55
General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 24
data types in. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
doubleword, word, and byte names . . . . . . . . . . . . . . . . . 25
Global EWBE# Disable (GEWBED) . . . . . . . . . . . . . . . . . . 206
H
Halt
restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Hardware Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Heat Dissipation Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
Heatsink
examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
sample measured data. . . . . . . . . . . . . . . . . . . . . . . . . . . 289
thermal resistance calculation . . . . . . . . . . . . . . . . . . . . 287
HIGHZ Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Hit to
modified line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
modified line, AHOLD-initiated inquire . . . . . . . . . . . . 158
modified line, HOLD-initiated inquire . . . . . . . . . . . . . 152
shared or exclusive line, AHOLD-initiated inquire . . . 156
shared or exclusive line, HOLD-initiated inquire . . . . 150
HIT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
HITM#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Index
309
Preliminary Information
AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
HLDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
HOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
-initiated inquire hit to modified line. . . . . . . . . . . . . . . 152
-initiated inquire hit to shared or exclusive line . . . . . . 150
Hold
PREFETCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16, 197
RSM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
supported by the AMD-K6™-2E processor . . . . . . . . . . . 56
test access port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
WBINVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . .106, 148–150
timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267, 282
Integer
data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
01h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
03h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
10h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
I
I/O
buffer
AC and DC characteristics. . . . . . . . . . . . . . . . . . . . . . 265
characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
misaligned read and write . . . . . . . . . . . . . . . . . . . . . . . . 147
read and write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
acknowledge. . . . . . . . . . . . . . . . . . . 95, 110, 112, 116, 164
acknowledge cycle definition . . . . . . . . . . . . . . . . . . . . . 168
acknowledge cycles . . . . . . . . 87, 90, 92, 98, 114, 128, 132
clock grant state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
descriptor table register . . . . . . . . . . . . . . . . . . . . . . . . . . 47
trap doubleword . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223–224
trap restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
I/O Buffer Information Specification (IBIS). . . . . . . . . . . . 264
IBIS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
IDCODE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
IEEE 1149.1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34, 110, 121
floating-point exceptions . . . . . . . . . . . . . . . . . . . . 213–214
gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
INIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
INTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
IRQ13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
MMX instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114, 183
redirection bitmap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
service routine . . . . . . . . . . . . . . . . . . . . .110, 114, 214, 217
shutdown cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
STPCLK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
system management . . . . . . . . . . . . . . . . . . . . 121, 217, 219
System Management Mode (SMM) . . . . . . . . . . . . . . . . 226
type of . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
INTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
INV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Invalidation Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
INVD Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
IEEE 754 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27, 213
IEEE 854 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
IGNNE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108, 214, 216
Ignore Numeric Exception. . . . . . . . . . . . . . . . . . . . . . . . . . 108
INIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
-initiated transition from protected mode to real mode 176
state of processor after. . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
output signal state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
power-on configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . 179
processor state after INIT . . . . . . . . . . . . . . . . . . . . . . . . 183
processor state after RESET . . . . . . . . . . . . . . . . . . . . . . 180
register state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
RESET requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
signals sampled during RESET. . . . . . . . . . . . . . . . . . . . 179
Input
pin types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
setup and hold timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
setup and hold timings for 100-MHz bus operation. . . . 272
setup and hold timings for 66-MHz bus operation. . . . . 276
Inquire
K
KEN#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111, 192
and bus arbitration cycles . . . . . . . . . . . . . . . . . . . . . . . . 148
cycle hit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
cycle hit to modified line . . . . . . . . . . . . . . . . . . . . . . . . . 105
cycles 86–91, 101, 105–106, 122, 129, 144, 148, 151–158,
. . . . 160, 162, 166, 199, 202–204, 239, 247, 249–251
miss, AHOLD-initiated. . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Instruction
buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Instructions
L
L1 Cache . . . . . . . . . . . . . . . . . . . . 42, 185, 196, 199, 204, 227
inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Layout and Airflow Considerations . . . . . . . . . . . . . . . . . . 295
Literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii
LOCK#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Locked
cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
operation with BOFF# intervention. . . . . . . . . . . . 166–167
operation, basic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Logic
3DNow!™ technology . . . . . . . . . . . . . . . . . . . . . . . . .81, 215
compatibility of floating-point, MMX technology, and
3DNow!™. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
EMMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
FEMMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
floating-point. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
integer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
INVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
branch-prediction. . . . . . . . . . . . . . . . . . . . . . . . 3, 11, 20–21
external support of floating-point exceptions . . . . . . . 213
symbol diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Low-Power Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
valid ordering part numbers. . . . . . . . . . . . . . . . . . . . . . 306
MMX technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . .78, 215
310
Index
Preliminary Information
22529B/0—January 2000
AMD-K6™-2E Processor Data Sheet
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Ordering Part Number (OPN). . . . . . . . . . . . . . . . . . . . . . . 305
Output
delay timings for 100-MHz bus operation . . . . . . . . . . . 270
delay timings for 66-MHz bus operation . . . . . . . . . . . . 274
pin float conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
signal state after RESET. . . . . . . . . . . . . . . . . . . . . . . . . 180
signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
valid delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
M
M/IO# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Machine-Check Address Register (MCAR) . . . . . .40–41, 182
Machine-Check Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Machine-Check Type Register (MCTR) . . . . . . . . .40–41, 182
Maskable Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
MCAR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40–41, 182
MCTR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40–41, 182
Memory
management registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
or I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
read and write, misaligned single-transfer . . . . . . . . . . 140
read and write, single-transfer . . . . . . . . . . . . . . . . . . . . 138
reads and writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
type range registers (MTRR). . . . . . . . . . . . . . . . . . .45, 207
MESI. . . . . . . . . . . . . . . . . . . . . . . . .1, 148, 152, 198, 202, 204
P
Package
321-pin staggered CPGA . . . . . . . . . . . . . . . . . . . . . . . . . 303
Socket 7 platform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Super7™ platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
thermal specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Packed Decimal Data Register. . . . . . . . . . . . . . . . . . . . . . . 30
Page
bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12, 186, 188
states in the data cache . . . . . . . . . . . . . . . . . . . . . . . . . . 186
cache disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
directory entry (PDE) . . . . . . . . . . . . . . . . . . . . . 50–51, 188
flush/invalidate register (PFIR) . . . . .40, 46, 182, 200–201
table entry (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . 50, 52, 188
writethrough. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Parity. . . . . . . . . . . . . . . . . . . . . . . . . 83, 90, 92, 100, 116, 138
bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90, 100, 116
check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90–91, 100, 116
error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91, 116, 154, 231
flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
PCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115, 188–189, 196
PCHK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 7
branch prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
centralized scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
decoders. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
enhanced RISC86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
execution units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
instruction fetching and decode . . . . . . . . . . . . . . . . . . . . 13
instruction prefetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
predecode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Misaligned
I/O read and write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
I/O transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
single-transfer memory read and write . . . . . . . . . 140–141
MMX Technology . . . . . . . . . . . . . . . . . . . . . 15–16, 18–20, 23
3DNow!™ registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
INIT state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
instruction compatibility, floating-point and. . . . . . . . . 216
instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56, 78, 216
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
RESET state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118, 179
Model-Specific Registers (MSR) . . . . . . . . . . . . . . . . . . . . . . 40
MSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
MTRR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45, 207
Multimedia
and 3DNow!™ execution units . . . . . . . . . . . . . . . . . . . . 215
PFIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40, 46, 182, 200–201
Pins
connection requirements . . . . . . . . . . . . . . . . . . . . . . . . 264
designation diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
designations by functional grouping . . . . . . . . . . . . . . . 301
float conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Pipeline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136–137, 142
address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8, 10, 12, 19, 21
data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
register X and Y. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Pipelined. . . . . . . . . . . . . . . . 19, 114, 137, 142–143, 160, 185
burst reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
execution unit . . . . . . . . . . . . . . . . . . . . . . . . . . . .19–20, 215
functional unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13, 88, 99
design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Pointer, Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Power
and grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
consumption and thermal resistance. . . . . . . . . . . . . . . 287
derating based on lower CPU frequencies . . . . . . . . . . 260
dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
low-power devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
standard-power devices . . . . . . . . . . . . . . . . . . . . . . . 260
Power-on Configuration and Initialization . . . . . . . . . . . . 179
Precision Real Data Registers . . . . . . . . . . . . . . . . . . . . . . . 30
N
NA#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Negated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Next Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
NMI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
No-Connect Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Non-Maskable Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Non-Pipelined Single-Transfer Memory Read/Write and
Write Delayed by EWBE# . . . . . . . . . . . . . . . . . . . . 139
Predecode Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13, 187
PREFETCH Instruction . . . . . . . . . . . . . . . . . . . . . . . . 16, 197
O
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
OPN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Index
311
Preliminary Information
AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
PREFETCH instruction . . . . . . . . . . . . . . . . . . . . . . .16, 197
software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Processor
RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118, 180
and configuration signals for 100-MHz bus operation . 278
and configuration signals for 66-MHz bus operation . . 279
and test signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
signals sampled during . . . . . . . . . . . . . . . . . . . . . . . . . . 179
state of processor after . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Reset and Configuration Timing . . . . . . . . . . . . . . . . . . . . 283
Return Address Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
RISC86® Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . 8
heat dissipation path . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
state observability register (PSOR) . . . . . . . . . 40, 45, 182
PSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40, 45, 182
PWT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117, 188
RSM Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222, 225
RSVD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
R
Read and Write
basic I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
misaligned I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Reads, Burst Reads and Pipelined Burst . . . . . . . . . . . . . . 142
Register X and Y
functional units. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
pipelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
S
SAMPLE/PRELOAD Instruction . . . . . . . . . . . . . . . . . . . . 236
Sampled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Scheduler/Instruction Control Unit . . . . . . . . . . . . . . . . 10, 17
SCYC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Sector, Write to a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193, 197
Segment
descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26, 52–54
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
task state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Shift-DR state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Shift-IR state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Shutdown Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Signals
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10, 23, 44, 216
3DNow!™. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23, 31
boundary-scan (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
bypass (BR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
control 0 (CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
control 1 (CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
control 2 (CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
control 3 (CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
control 4 (CR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
data types, floating-point. . . . . . . . . . . . . . . . . . . . . . . . . . 30
A[31:3]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
A20M#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86, 218
ADS# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
ADSC#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
AHOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89, 249
AP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
APCHK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
BE[7:0]# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
BF[2:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93, 252
BOFF# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94, 162, 249
BRDY#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95, 224, 249–250
BRDYC# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
BREQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37, 241
descriptors and gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
device identification (DIR) . . . . . . . . . . . . . . . . . . . . . . . 234
DR3–DR0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
DR5–DR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
DR6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
DR7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
EAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
EFLAGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
extended feature enable (EFER) . . . . . . . . . . . . . . . . . . . 43
floating-point. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
general-purpose. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
machine-check address (MCAR) . . . . . . . . . . . . . . . . . . . . 41
machine-check type (MCTR) . . . . . . . . . . . . . . . . . . . . . . . 41
memory management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
memory type range (MTRR) . . . . . . . . . . . . . . . . . . . . . . . 45
MMX technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23, 31
model-specific (MSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
packed decimal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PFIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
precision real data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SYSCALL/SYSRET target address (STAR) . . . . . . . . . . . 44
System Management Mode (SMM) initial state . . . . . . 219
test (TR12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
test access port (TAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
TR12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
UC/WC cacheability control (UWCCR) . . . . . . . . . . . . . . 45
write handling control (WHCR) . . . . . . . . . . . . . . . . . . . . 44
CACHE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97, 189
cache-related . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
CLK . . . . . . . . . . . . . . . . . . . . . . 97, 247, 250, 252, 267–268
D/C#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
D[63:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
DP[7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
EADS#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101, 251
EWBE# . . . . . . . . . . . . . . . . . . . . . . . . . . . 102, 205, 249–250
FERR#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103, 216
FLUSH# . . . . . . . . . 104, 132, 179, 200, 226, 228, 249–251
HIT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105, 251
HITM#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105, 251
HLDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
HOLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107, 249
IGNNE#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108, 216
INIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109, 218, 249–250
INTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110, 249–250
INV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
KEN#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
LOCK#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
X and Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18–19
Regulator, Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
312
Index
Preliminary Information
22529B/0—January 2000
AMD-K6™-2E Processor Data Sheet
logic symbol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
M/IO# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
NA#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
NMI. . . . . . . . . . . . . . . . . . . . . . . . . . 114, 218, 226, 249–250
output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
PCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
PCHK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
pin connection requirements. . . . . . . . . . . . . . . . . . . . . . 264
pin designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
PWT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Stop
clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
clock state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173, 252
grant inquire state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
grant state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173, 250
STPCLK# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Super7™ Platform
enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
initiative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Switching Characteristics
RESET . . . . . . . . . . . . . . . . . . . . . . . 118, 249–250, 252, 267
reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
RSVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
sampled during RESET . . . . . . . . . . . . . . . . . . . . . . . . . . 179
SCYC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
SMI# . . . . . . . . . . . . . . . . . . . . . . . . . 121, 217, 224, 249–250
SMIACT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122, 217
CLK switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
diagram key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
float delay timing diagram . . . . . . . . . . . . . . . . . . . . . . . 282
input setup and hold timing diagram . . . . . . . . . . . . . . 282
input setup and hold timings for 100-MHz bus. . . . . . . 272
input setup and hold timings for 66-MHz bus. . . . . . . . 276
output delay timings for 100-MHz bus. . . . . . . . . . . . . . 270
output delay timings for 66-MHz bus. . . . . . . . . . . . . . . 274
output valid delay timing diagram. . . . . . . . . . . . . . . . . 281
RESET and configuration signals for 100-MHz bus . . . 278
RESET and configuration signals for 66-MHz bus . . . . 279
RESET and configuration timing diagram . . . . . . . . . . 283
TCK timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
test signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 280, 284
TRST# timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
valid delay, float, setup, and hold timings. . . . . . . . . . . 269
SYSCALL Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . 44, 73
SYSCALL/SYSRET Target Address Register (STAR) .40, 44,
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
STPCLK# . . . . . . . . . . . . . . . . . . . . . . . . . 123, 247, 250–251
switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 267
TCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124, 267
TDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
TDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
test access port (TAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
TMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
TRST# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
VCC2DET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
VCC2H/L# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
VCC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
W/R#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
WB/WT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
SIMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Single Instruction Multiple Data (SIMD) Operations. . . . . 11
Single-Transfer Memory Read and Write. . . . . . . . . . . . . . 138
SMI# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
SMIACT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Snoop . . . . . . . . . . . . . . . . . . . . . . 122, 129, 144, 200, 202–203
cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
internal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Software Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
application segment types . . . . . . . . . . . . . . . . . . . . . . . . . 53
descriptors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
exceptions (summary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
instructions supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
interrupts (summary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
model-specific registers (MSR) . . . . . . . . . . . . . . . . . . . . . 41
paging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Software Prefetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
SYSRET Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44, 73
System
design
airflow management . . . . . . . . . . . . . . . . . . . . . . . . . . 296
component placement . . . . . . . . . . . . . . . . . . . . . . . . . 263
decoupling recommendations. . . . . . . . . . . . . . . . . . . 263
I/O buffer characteristics . . . . . . . . . . . . . . . . . . . . . . 264
pin connection requirements . . . . . . . . . . . . . . . . . . . 264
power connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . 285
segment and gate types. . . . . . . . . . . . . . . . . . . . . . . . . . . 54
segment descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
System Management Mode (SMM)
base address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
debugging in. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
default register values. . . . . . . . . . . . . . . . . . . . . . . . . . . 217
exceptions in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
halt restart slot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
I/O trap doubleword. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
I/O trap restart slot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
initial register state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
interrupt active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
interrupts in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
revision identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
state-save area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Special Bus Cycles . . .95, 102, 104, 123, 170–173, 190, 223,
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249–250
definition (table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
encodings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
summary (table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Speculative EWBE# Disable (SEWBED) . . . . . . . . . . . . . . 206
Split Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Standard-Power Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
valid ordering part numbers . . . . . . . . . . . . . . . . . . . . . . 306
State
cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
machine diagram, bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
processor
after INIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
after RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
T
TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Task State Segment (TSS). . . . . . . . . . . . . . . . . . . . . . . . . . . 48
TCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124, 280, 284
TDI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
TDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Technical Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii
Index
313
Preliminary Information
AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
Technical Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
ambient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
TRST# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125, 280, 284
TSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40, 42, 182, 249–250
TSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48, 54–55, 244
case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285, 288
case-to-ambient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
extended rating for low-power devices. . . . . . . . . . . . . . 285
Test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
boundary-scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
built-in self-test (BIST). . . . . . . . . . . . . . . . . . . . . . . . . . . 227
clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
L1 cache inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
-logic-reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
mode select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
register 12 (TR12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
switching characteristics of signals. . . . . . . . . . . . . . . . . 280
test access port (TAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
three-state test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Test Access Port (TAP)
instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
BYPASS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
EXTEST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
HIGHZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
IDCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
SAMPLE/PRELOAD. . . . . . . . . . . . . . . . . . . . . . . . . . . 236
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
boundary-scan (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . 231
bypass (BR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
device identification (DIR) . . . . . . . . . . . . . . . . . . . . . 234
instruction register (IR). . . . . . . . . . . . . . . . . . . . . . . . 231
signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
states
Typical and Maximum Power Dissipation . . . . . . . . . 258–259
low-power devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
standard-power devices. . . . . . . . . . . . . . . . . . . . . . . . . . 260
U
UC/WC Cacheability Control Register (UWCCR)40, 45, 180,
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182, 191, 208
Uncacheable Memory . . . . . . . . . . . . . . . . . . . . . . 45, 206–207
UWCCR. . . . . . . . . . . . . . . . . . . . . . 40, 45, 180, 182, 191, 208
V
Valid
delay, float, setup, and hold timings . . . . . . . . . . . . . . . 269
masks and range sizes . . . . . . . . . . . . . . . . . . . . . . . . . . 210
ordering part number combinations . . . . . . . . . . . . . . . 306
VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
VCC2DET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
VCC2H/L#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
VCC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Voltage . . . . . . . . . . . . . . . . . . . . 126–127, 134, 254, 256, 264
dual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
W
W/R# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Waveform Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
WB/WT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
WBINVD Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
WC/UC Memory Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
WCDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
capture-DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
capture-IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
shift-DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
shift-IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236–237
test-logic-reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
update-DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
update-IR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Test Signal
WHCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40, 44, 182, 196
Write
handling control register (WHCR). . . . . . .40, 44, 182, 196
to a cacheable page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
to a sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193, 197
Write Allocate . . . . . . . . . . . . . . . . . . . . . . . 187, 192–193, 196
enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
enable limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
limit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
logic mechanisms and conditions. . . . . . . . . . . . . . . . . . 196
Write Merge Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
EWBE# Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
memory type range registers (MTRR). . . . . . . . . . . . . . 207
Write/Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
timing at 25 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286, 295–296
design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
extended temperature rating. . . . . . . . . . . . . . . . . . . . . . 285
heat dissipation path . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
heatsink sample data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
layout and airflow consideration. . . . . . . . . . . . . . . . . . . 295
measuring case temperature . . . . . . . . . . . . . . . . . . . . . . 288
model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Third-Party Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
Three-State Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Writeback . . . 97, 99–100, 111, 117, 122, 129, 132, 144–145,
. . . . . . . . . . . . . . . . . . . . . . . . 170, 185, 191, 198, 204
burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8, 12
cycles. 86, 88–89, 102, 105, 129, 144, 152, 156, 158, 160,
. . . . . . . . . . . . . . . . 162, 166, 188–189, 240, 248, 251
or writethrough . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Write-Combining Memory. . . . . . . . . . . . . . . . . . . 45, 206–207
Writethrough and Writeback Coherency States. . . . . . . . 204
Time Stamp Counter (TSC) . . . . . . . . . . . . . . . . . . . . . .42, 250
Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . .133, 139–177
waveform definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
TLB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
TMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
TR12. . . . . . . . . . . . . . . . . . . . . . . . .40, 42, 182, 188, 195, 239
Transition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
from protected mode to real mode . . . . . . . . . . . . . . . . . 176
Translation Lookaside Buffer (TLB) . . . . . . . . . . . . . . . . . . 185
314
Index
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