AM79C940KI_技术文档

FINAL

Am79C940

Media Access Controller for Ethernet (MACE™)

DISTINCTIVE CHARACTERISTICS

ꢀ Integrated Controller with Manchester

encoder/decoder and 10BASE-T transceiver

and AUI port

ꢀ Arbitrary byte alignment and little/big endian

memory interface supported

ꢀ Internal/external loopback capabilities

ꢀ Supports IEEE 802.3/ANSI 8802-3 and Ethernet

ꢀ External Address Detection Interface (EADI )

for external hardware address filtering in

bridge/router applications

standards

ꢀ 84-pin PLCC and 100-pin PQFP Packages

ꢀ 80-pin Thin Quad Flat Pack (TQFP) package

available for space critical applications such as

PCMCIA

ꢀ JTAG Boundary Scan (IEEE 1149.1) test access

port interface for board level production test

ꢀ Integrated Manchester Encoder/Decoder

ꢀ Modular architecture allows easy tuning to

ꢀ Digital Attachment Interface (DAI ) allows

by-passing of differential Attachment Unit

Interface (AUI)

specific applications

ꢀ High speed, 16-bit synchronous host system

interface with 2 or 3 cycles/transfer

ꢀ Supports the following types of network

ꢀ Individual transmit (136 byte) and receive (128

byte) FlFOs provide increase of system latency

and support the following features:

interface:

— AUI to external 10BASE2, 10BASE5 or

10BASE-F MAU

— Automatic retransmission with no FIFO

reload

— DAI port to external 10BASE2, 10BASE5,

10BASE-T, 10BASE-F MAU

— Automatic receive stripping and transmit

padding (individually programmable)

— General Purpose Serial Interface (GPSI) to

external encoding/decoding scheme

— Automatic runt packet rejection

— Internal 10BASE-T transceiver with

— Automatic deletion of collision frames

automatic selection of 10BASE-T or AUI port

— Automatic retransmission with no FIFO

reload

ꢀ Sleep mode allows reduced power consump-

tion for critical battery powered applications

ꢀ Direct slave access to all on board

configuration/status registers and transmit/

receive FlFOs

ꢀ 5 MHz-25 MHz system clock speed

ꢀ Support for operation in industrial temperature

range (–40°C to +85°C) available in all three

packages

ꢀ Direct FIFO read/write access for simple

interface to DMA controllers or l/O processors

GENERAL DESCRIPTION

The Media Access Controller for Ethernet (MACE) chip

is a CMOS VLSI device designed to provide flexibility

in customized LAN design. The MACE device is specif-

ically designed to address applications where multiple

I/O peripherals are present, and a centralized or sys-

tem specific DMA is required. The high speed, 16-bit

synchronous system interface is optimized for an exter-

nal DMA or I/O processor system, and is similar to

many existing peripheral devices, such as SCSI and

serial link controllers.

The MACE device is a slave register based peripheral.

All transfers to and from the system are performed

using simple memory or I/O read and write commands.

In conjunction with a user defined DMA engine, the

MACE chip provides an IEEE 802.3 interface tailored

to a specific application. Its superior modular architec-

ture and versatile system interface allow the MACE

device to be configured as a stand-alone device or

as a connectivity cell incorporated into a larger,

integrated system.

Publication# 16235 Rev: E Amendment/0

Issue Date: May 2000

The MACE device provides a complete Ethernet node

solution with an integrated 10BASE-T transceiver, and

supports up to 25-MHz system clocks. The MACE

device embodies the Media Access Control (MAC)

and Physical Signaling (PLS) sub-layers of the IEEE

802.3 standard, and provides an IEEE defined Attach-

ment Unit Interface (AUI) for coupling to an external

Medium Attachment Unit (MAU). The MACE device is

compliant with 10BASE2, 10BASE5, 10BASE-T, and

10BASE-F transceivers.

The Am79C940 MACE chip is offered in a Plastic

Leadless Chip Carrier (84-pin PLCC), a Plastic Quad

Flat Package (100-pin PQFP), and a Thin Quad Flat

Package (TQFP 80-pin). There are several small func-

tional and physical differences between the 80-pin

TQFP and the 84-pin PLCC and 100-pin PQFP config-

urations. Because of the smaller number of pins in the

TQFP configuration versus the PLCC configuration,

four pins are not bonded out. Though the die is identical

in all three package configurations, the removal of

these four pins does cause some functionality differ-

ences between the TQFP and the PLCC and PQFP

configurations. Depending on the application, the

removal of these pins will or will not have an effect.

(See section: “Pins Removed for TQFP Package and

Their Effects.)

Additional features also enhance over-all system

design. The individual transmit and receive FIFOs

optimize system overhead, providing substantial

latency during packet transmission and reception, and

minimizing intervention during normal network error

recovery. The integrated Manchester encoder/decoder

eliminates the need for an external Serial Interface

Adapter (SIA) in the node system. If support for an

external encoding/decoding scheme is desired, the

General Purpose Serial Interface (GPSI) allows direct

access to/from the MAC. In addition, the Digital Attach-

ment Interface (DAI), which is a simplified electrical

attachment specification, allows implementation of

MAUs that do not require DC isolation between the

MAU and DTE. The DAI port can also be used to

indicate transmit, receive, or collision status by

connecting LEDs to the port. The MACE device also

provides an External Address Detection Interface

(EADI) to allow external hardware address filtering in

internet working applications.

With the rise of embedded networking applications op-

erating in harsh environments where temperatures

may exceed the normal commercial temperature (0°C

to +70°C) window, an industrial temperature (-40°C to

+85°C) version is available in all three packages; 84-

pin PLCC, 100-pin PQFP and 80-pin TQFP. The indus-

trial temperature version of the MACE Ethernet control-

ler is characterized across the industrial temperature

range (-40°C to +85°C) within the published power

supply specification (4.75 V to 5.25 V; i.e., ±5% V_CC).

Thus, conformance of MACE performance over this

temperature range is guaranteed by the design and

characterization monitor.

2

Am79C940

BLOCK DIAGRAM

XTAL1

XTAL2

DXCVR

CLSN

SRDCLK

SRD

EADI

Port

Control

EADI Port

AUI

SF/BD

EAM/R

DBUS 15–0

ADD 4–0

R/W

RCV FIFO

XMT FIFO

DO±

DI±

CI±

AUI

Port

802.3

MAC

Core

CS

FDS

DTV

TXD±

TXP±

RXD

LNKST

RXPOL

FIFO

10BASE-T

MAU

10BASE-T

DAI Port

Bus

Interface

Unit

Control

EOF

RDTREQ

TDTREQ

TXDAT±

TXEN

RXDAT

Command

& Status

Registers

BE 1–0

INTR

SCLK

DAI

Port

RXCRS

EDSEL

TC

STDCLK

TXDAT+

TXEN

SRDCLK

RXDAT

RXCRS

SLEEP

RESET

GPSI

Port

GPSI

JTAG

PORT CNTRL

CLSN

C16235D-1

TDI

TCK

TDO

TMS

Notes:

1. Only one of the network ports AUI, 10BASE-T, DAI port or GPSI can be active at any time. Some shared signals are

active regardless of which network port is active, and some are reconfigured.

2. The EADI port is active at all times.

Am79C940

3

TABLE OF CONTENTS

AM79C940 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

TABLE OF CONTENTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

CONNECTION DIAGRAMS PL 084 PLCC PACKAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

CONNECTION DIAGRAMS PQR100 PQFP PACKAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

CONNECTION DIAGRAMS PQT080 TQFP PACKAGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Standard Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

PIN/PACKAGE SUMMARY (PLCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

PIN DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Network Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Attachment Unit Interface (AUI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

CI+/CI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

DI+/DI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

DO+/DO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Digital Attachment Interface (DAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

TXDAT+/TXDAT–. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

TXEN/TXEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Transmit Enable (Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

RXDAT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

RXCRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

DXCVR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

10BASE-T INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

TXD+, TXD– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

TXP+, TXP–. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

RXD+, RXD– . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

LNKST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

RXPOL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

General Purpose Serial Interface (GPSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

STDCLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

CLSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

External Address Detection Interface (EADI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

SF/BD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

SRD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

EAM/R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

SRDCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

HOST SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

DBUS15-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

ADD4-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

R/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

RDTREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

TDTREQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

FDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

DTV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

EOF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

BE1–0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

CS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

INTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

SCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

EDSEL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

IEEE 1149.1 TEST ACCESS PORT (TAP) INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

TCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

4

Am79C940

TMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

TDI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

TDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

GENERAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

XTAL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

XTAL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

SLEEP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

DVDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

DVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

PIN FUNCTIONS NOT AVAILABLE WITH THE 80-PIN TQFP PACKAGE . . . . . . . . . . . . . . . . . .28

PINS REMOVED FOR TQFP PACKAGE AND THEIR EFFECTS . . . . . . . . . . . . . . . . . . . . . . . . . . .28

FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Network Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

DETAILED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Block Level Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Bus Interface Unit (BIU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

BIU to FIFO Data Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Byte Alignment For FIFO Read Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

BIU to Control and Status Register Data Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

FIFO Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Media Access Control (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Manchester Encoder/Decoder (MENDEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Attachment Unit Interface (AUI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Digital Attachment Interface (DAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

10BASE-T Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Twisted Pair Transmit Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Twisted Pair Receive Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Link Test Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Polarity Detection and Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Twisted Pair Interface Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Collision Detect Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Signal Quality Error (SQE) Test (Heartbeat) Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Jabber Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

External Address Detection Interface (EADI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Internal/External Address Recognition Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

General Purpose Serial Interface (GPSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

IEEE 1149.1 Test Access Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

SLAVE ACCESS OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Reinitialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

TRANSMIT OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Transmit FIFO Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Transmit Function Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Automatic Pad Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Transmit FCS Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Transmit Status Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Transmit Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

RECEIVE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Receive FIFO Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Receive Function Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Automatic Pad Stripping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Receive FCS Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Am79C940

5

Receive Status Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Receive Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

LOOPBACK OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

USER ACCESSIBLE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

8-Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Programmer’s Register Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Missing Table Title? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

SYSTEM APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Host System Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

NETWORK INTERFACES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

External Address Detection Interface (EADI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

MACE Compatible AUI Isolation Transformers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

MANUFACTURER CONTACT INFORMATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Commercial (C) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Industrial (I) Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

V_CCSupply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

DC CHARACTERISTICS (UNLESS OTHERWISE NOTED, PARAMETRIC VALUES ARE THE SAME

BETWEEN COMMERCIAL DEVICES AND INDUSTRIAL DEVICES.) . . . . . . . . . . . . . . . . . . . . . . .90

AC CHARACTERISTICS (UNLESS OTHERWISE NOTED, PARAMETRIC VALUES ARE THE SAME

BETWEEN COMMERCIAL DEVICES AND INDUSTRIAL DEVICES.) . . . . . . . . . . . . . . . . . . . . . . .93

KEY TO SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

SWITCHING TEST CIRCUITS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

PHYSICAL DIMENSIONS* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

PL 084 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

84-Pin Plastic Leaded Chip Carrier (measured in inches). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117

PHYSICAL DIMENSIONS* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

PQR100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118

100-Pin Plastic Quad Flat Pack; Trimmed and Formed (measured in millimeters) . . . . . . . . . . .118

PHYSICAL DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

PQR100 100-Pin Plastic Quad Flat Pack with Molded Carrier Ring (measured in millimeters) .119

PHYSICAL DIMENSIONS* PQT080 80-Pin Thin Quad Flat Package (measured in millimeters)120

LOGICAL ADDRESS FILTERING FOR ETHERNET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

BSDL DESCRIPTION OF AM79C940 MACE JTAG STRUCTURE . . . . . . . . . . . . . . . . . . . . . . . . .123

AM79C940 MACE REV C0 SILICON ERRATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

6

Am79C940

CONNECTION DIAGRAMS

PL 084

PLCC PACKAGE

11 10 9

12

8

7

6

5

4

3 2 1 84 83 82 81 80 79 78 77 76 75

SRDCLK

EAM/R

SRD

SF/BD

RESET

SLEEP

DV_DD

INTR

TC

DBUS0

DV_SS

DBUS1

DBUS2

DBUS3

DBUS4

DV_SS

DBUS5

DBUS6

DBUS7

DBUS8

DBUS9

74 XTAL2

73 AV_SS

72 XTAL1

71 AV_DD

70 TXD+

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

69

TXP+

68

TXD-

67

TXP-

66

AV_DD

Am79C940JC

MACE

65

RXD+

64

RXD-

63

DV_DD

62

TDI

61

DV_SS

60

TCK

59

TMS

58

TDO

57

LNKST

56

RXPOL

55

CS

RW/

54

35

39

43 44

48

49

52 53

50 51

33

37 38

41 42

45 46 47

36

40

34

16235D-2

Am79C940

7

CONNECTION DIAGRAMS

PQR100

PQFP PACKAGE

NC

1

2

3

4

5

6

7

8

80

79

78

77

76

75

74

73

72

71

70

69

68

67

NC

AV_SS

NC

XTAL2

AV_SS

XTAL1

AV_DD

TXD+

TXP+

TXD

NC

SRDCLK

EAM/R

SRD

SF/BD

RESET

SLEEP

DV_DD

INTR

TC

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

TXP

AV_DD

RXD+

RXD

DBUS0

DV_SS

MACE

Am79C940KC

66

65

64

63

DBUS1

DBUS2

DBUS3

DBUS4

DV_SS

DBUS5

DBUS6

DBUS7

DBUS8

DBUS9

NC

DV_DD

TDI

DV_SS

TCK

TMS

TDO

LNKST

RXPOL

CS

R/W

NC

62

61

60

59

58

57

56

55

54

53

52

51

NC

DBUS10

NC

16235D-3

8

Am79C940

CONNECTION DIAGRAMS

PQT080

TQFP PACKAGE

80 79 78 77 76 757473 72 717069 68 67 65 64 63 62 61

66

SRDCLK

EAM/R

SF/BD

1

2

3

4

60

59

58

57

XTAL2

AV_SS

XTAL1

AV^DD

RESET

SLEEP

DV

DD

5

6

56

55

TXD+

TXP+

INTR

TC

7

8

9

10

11

12

13

54

53

52

51

50

49

48

TXD-

TXP-

AV_DD

DBUS0

DV_SS

DBUS1

DBUS2

DBUS3

RXD+

RXD-

DV_DD

TDI

MACE

Am79C940VC

DV_SS

TCK

TMS

TD0

LNKST

CS

DBUS4

DV_SS

14

15

16

17

18

19

20

47

46

45

44

43

42

41

DBUS5

DBUS6

DBUS7

DBUS8

DBUS9

R/W

21 22 23 24 25 262728 29 303132 33 34 36 37 38 39 40

35

16235D-4

Notes: Four pin functions available on the PLCC and PQFP packages are not available with the TQFP package.

(See full data sheet for description of pins not included with the 80-pin TQFP package. In particular, see section

“Pin Functions not available with the 80-pin TQFP package.”)

Am79C940

9

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed

by a combination of:

AM79C940

V

C

\W

ALTERNATE PACKAGING OPTION

\W = Trimmed and Formed in a Tray

OPTIONAL PROCESSING

Blank

=

Standard Processing

TEMPERATURE RANGE

C

I

=

Commercial (0° to +70°C)

Industrial (-40°C to +85°C)

PACKAGE TYPE (per Prod. Nomenclature/16-038)

84-Pin Plastic Leaded Chip Carrier (PL 084)

J

=

K = 100-Pin Plastic Quad Flat Pack (PQR100)

V = 80-Pin Thin Quad Flat Package (PQT080)

SPEED

Not Applicable

DEVICE NUMBER/DESCRIPTION (include revision letter)

Am79C940

Media Access Controller for Ethernet

Valid Combinations

The Valid Combinations table lists configurations planned to

be supported in volume for this device. Consult the local AMD

sales office to confirm availability of specific valid

JC, KC,

KC\W, VC,

VC\W

AM79C940

combinations and to check on newly released combinations.

JI, KI,

AM79C940

KI\W, VI,

VI\W

Note:

Currently the silicon revision level of the MACE Ethernet controller is revision C0. This is designated by the marking on the package

as Am79C940Bxx, where “xx” indicate package type and temperature range.

10

Am79C940

PIN/PACKAGE SUMMARY (PLCC)

PLCC Pin #

1

Pin Name

DXCVR

EDSEL

DV_SS

Pin Function

Disable Transceiver

Edge Select

2

3

Digital Ground

Transmit Data +

Transmit Data –

Digital Ground

Serial Transmit Data Clock

Transmit Enable

Collision

4

TXDAT+

TXDAT–

DV_SS

5

6

7

STDCLK

TXEN/TXEN

CLSN

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

RXDAT

RXCRS

SRDCLK

EAM/R

SRD

Receive Data

Receive Carrier Sense

Serial Receive Data Clock

External Address Match/Reject

Serial Receive Data

Start Frame/Byte Delimiter

Reset

SF/BD

RESET

SLEEP

DV_DD

Sleep Mode

Digital Power

Interrupt

INTR

TC

Timing Control

Data Bus0

DBUS0

DV_SS

Digital Ground

Data Bus1

DBUS1

DBUS2

DBUS3

DBUS4

DV_SS

Data Bus2

Data Bus3

Data Bus4

Digital Ground

Data Bus5

DBUS5

DBUS6

DBUS7

DBUS8

DBUS9

DBUS10

DBUS11

DBUS12

DBUS13

DV_DD

Data Bus6

Data Bus7

Data Bus8

Data Bus9

Data Bus10

Data Bus11

Data Bus12

Data Bus13

Digital Power

Data Bus14

DBUS14

DBUS15

DV_SS

Data Bus15

Digital Ground

End Of Frame

Data Transfer Valid

FIFO Data Strobe

Byte Enable0

EOF

DTV

FDS

BE0

Am79C940

11

PIN/PACKAGE SUMMARY (continued)

PLCC Pin #

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

Pin Name

BE1

Pin Function

Byte Enable 1

System Clock

Transmit Data Transfer Request

Receive Data Transfer Request

Address0

SCLK

TDTREQ

RDTREQ

ADD0

ADD1

ADD2

ADD3

ADD4

R/W

Address1

Address2

Address3

Address4

Read/Write

CS

Chip Select

RXPOL

LNKST

TDO

Receive Polarity

Link Status

Test Data Out

Test Mode Select

Test Clock

TMS

TCK

DV_SS

TDI

Digital Ground

Test Data Input

Digital Power

Receive Data–

Receive Data+

Analog Power

Transmit Pre-distortion

Transmit Data–

Transmit Pre-distortion+

Transmit Data+

Analog Power

Crystal Output

Analog Ground

Crystal Output

Analog Ground

Data Out–

DV_DD

RXD–

RXD+

AV_DD

TXP–

TXD–

TXP+

TXD+

AV_DD

XTAL1

AV_SS

XTAL2

AV_SS

DO–

DO+

Data Out+

AV_DD

DI–

Analog Power

Data In–

DI+

Data In+

CI–

Control In–

CI+

Control In+

AV_DD

DV_DD

Analog Power

Digital Power

12

Am79C940

PIN/PACKAGE SUMMARY (PQFP) (continued)

PQFP Pin #

1

Pin Name

NC

Pin Function

No Connect

2

NC

No Connect

3

NC

No Connect

4

NC

No Connect

5

SHDCLK

EAM/R

SRD

Serial Receive Data Clock

External Address Match/Reject

Serial Receive Data

Start Frame/Byte Delimiter

Reset

6

7

8

SF/BD

RESET

SLEEP

DVDD

INTR

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

Sleep Mode

Digital Power

Interrupt

TC

Timing Control

Data Bus0

DBUS0

DV_SS

Digital Ground

Data Bus1

DBUS1

DBUS2

DBUS3

DBUS4

Data Bus2

Data Bus3

Data Bus4

DV

SS

Digital Ground

Data Bus5

DBUS5

DBUS6

DBUS7

DBUS8

DBUS9

NC

Data Bus6

Data Bus7

Data Bus8

Data Bus9

No Connect

NC

No Connect

NC

No Connect

DBUS10

NC

Data Bus10

No Connect

DBUS11

DBUS12

DBUS13

DV_DD

Data Bus11

Data Bus12

Data Bus13

Digital Power

Data Bus14

DBUS14

DBUS15

Data Bus15

DV

SS

Digital Ground

End of Frame

Data Transfer Valid

FIFO Data Strobe

Byte Enable0

Byte Enable1

EOF

DTV

FDS

BE0

BE1

Am79C940

13

PIN/PACKAGE SUMMARY (continued)

PQFP Pin #

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

Pin Name

SCLK

TDTREQ

RDTREQ

ADD0

ADD1

ADD2

ADD3

ADD4

NC

Pin Function

System Clock

Transmit Data Transfer Request

Receive Data Transfer Request

Address0

Address1

Address2

Address3

Address4

No Connect

NC

No Connect

NC

No Connect

NC

No Connect

R/W

Read/Write

CS

Chip Select

RXPOL

LNKST

TDO

Receive Polarity

Link Status

Test Data Out

Test Mode Select

Test Clock

TMS

TCK

DV_SS

TDI

Digital Ground

Test Data Input

Digital Power

Receive Data–

Receive Data+

Analog Power

Transmit Pre-distortion–

Transmit Data–

Transmit Pre-distortion+

Transmit Data+

Analog Power

Crystal Input

DV_DD

RXD–

RXD+

AV_DD

TXP–

TXD–

TXP+

TXD+

AV_DD

XTAL1

AV_SS

XTAL2

NC

Analog Ground

Crystal Output

No Connect

NC

No Connect

NC

No Connect

AV_SS

NC

Analog Ground

No Connect

DO–

Data Out–

DO+

Data Out+

AV_DD

DI–

Analog Power

Data In–

DI+

Data In+

14

Am79C940

PIN/PACKAGE SUMMARY (continued)

PQFP Pin #

Pin Name

CI–

Pin Function

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

Control In–

CI+

Control In+

AV_DD

Analog Power

Digital Power

DV_DD

DXCVR

EDSEL

DV_SS

Disable Transceiver

Edge Select

Digital Ground

Transmit Data +

Transmit Data–

Digital Ground

Serial Transmit Data Clock

Transmit Enable

Collision

TXDAT+

TXDAT–

DV_SS

STDCLK

TXEN/TXEN

CLSN

RXDAT

RXCRS

Receive Data

Receive Carrier Sense

Am79C940

15

PIN/PACKAGE SUMMARY (TQFP) (continued)

TQFP

TQFP #

1

Pin Name

Pin Function

Pin Number

41

42

43

44

45

46

47

48

49

Pin Name

R/W

Pin Function

Read/Write

SRDCLK Serial Receive Data Clock

2

EAM/R

SF/BD

External Address Match/Reject

Start Frame/Byte Delimiter

CS

Chip/Select

3

LNKST

TDO

Link Status

4

RESET Reset

Test Data Out

Test Mode Select

Text Clock

5

SLEEP

DVDD

INTR

TC

Sleep Mode

TMS

6

Digital Power

Interrupt

TCK

7

DVSS

TDI

Digital Ground

Test Data Input

Digital Power

Receive Data–

Receive Data+

Analog Power

Transmit Pre-distortion–

Transmit Data–

Transmit Pre-distortion+

Transmit Data+

Analog Power

Crystal Output

Analog Ground

Crystal Output

Analog Ground

Data Out–

8

Timing Control

9

DBUS0 Data Bus0

DVDD

RXD–

RXD+

AVDD

TXP–

TXD–

TXP+

TXD+

AVDD

XTAL1

AVSS

XTAL2

AVSS

DO–

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

DVSS

Digital Ground

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

DBUS1 Data Bus1

DBUS2 Data Bus2

DBUS3 Data Bus3

DBUS4 Data Bus4

DVSS

Digital Ground

DBUS5 Data Bus5

DBUS6 Data Bus6

DBUS7 Data Bus7

DBUS8 Data Bus8

DBUS9 Data Bus9

DBUS10 Data Bus10

DBUS11 Data Bus11

DBUS12 Data Bus12

DBUS13 Data Bus13

DO+

Data Out+

AVDD

DI–

Analog Power

Data In–

DVDD

Digital Power

DBUS14 Data Bus14

DBUS15 Data Bus15

DI+

Data Out+

CI–

Control In–

DVSS

EOF

FDS

BE0

Digital Ground

End of Frame

FIFO Data Strobe

Byte Enable0

Byte Enable1

System Clock

CI+

Control In+

AVDD

DVDD

DXCVR

EDSEL

DVSS

TXDAT+

DVSS

STDCLK

Analog Power

Digital Power

Disable Transceiver

Edge Select

BE1

SCLK

Digital Ground

Transmit Data+

Digital Ground

Serial Transmit Data Clock

TDTREQ Transmit Data Transfer Request

RDTREQ Receive Data Transfer Request

ADD0

ADD1

ADD2

ADD3

ADD4

Address0

Address1

Address2

Address3

Address4

TXEN/TXEN Transmit Enable

78

79

80

CLSN

RXDAT

RXCRS

Collision

Receive Data

Receive Carrier Sense

16

Am79C940

PIN SUMMARY

Pin Name

Pin Function

Type

Active

Comment

Attachment Unit Interface (AUI)

DO+/DO–

DI+/DI–

CI+/CI–

RXCRS

TXEN

Data Out

O

I

Pseudo-ECL

Data In

Control In

I

Receive Carrier Sense

Transmit Enable

Collision

I/O

O

High

Low

TTL output. Input in DAI, GPSI port

TTL. TXEN in DAI port

TTL output. Input in GPSI

TTL low

CLSN

I/O

O

DXCVR

STDCLK

SRDCLK

Disable Transceiver

Serial Transmit Data Clock

Serial Receive Data Clock

I/O

Output. Input in GPSI

Digital Attachment Interface (DAI)

TXDAT+

TXDAT–

TXEN

Transmit Data +

O

High

Low

TTL. See also GPSI

TTL

Transmit Data–

Transmit Enable

O

TTL. See TXEN in GPSI

TTL. See also GPSI

TTL input. Output in AUI

TTL output. Input in GPSI

TTL high

RXDAT

Receive Data

I

RXCRS

Receive Carrier Sense

Collision

I/O

O

High

CLSN

DXCVR

Disable Transceiver

Serial Transmit Data Clock

Serial Receive Data Clock

STDCLK

SRDCLK

10BASE-T Interface

TXD+/TXD–

TXP+/TXP–

RXD+/RXD–

LNKST

I/O

Output. Input in GPSI

Transmit Data

O

Transmit Pre-distortion

Receive Data

I

Link Status

O

Low

High

Open Drain

RXPOL

Receive Polarity

O

Open Drain

TXEN

Transmit Enable

O

TTL. TXEN in DAI port

TTL output. Input in DAI, GPSI port

TTL output. Input in GPSI

TTL high

RXCRS

Receive Carrier Sense

Collision

I/O

O

CLSN

DXCVR

Disable Transceiver

Serial Transmit Data Clock

Serial Receive Data Clock

STDCLK

SRDCLK

I/O

Output. Input in GPSI

General Purpose Serial Interface (GPSI)

STDCLK

TXDAT+

TXEN

Serial Transmit Data Clock

Transmit Data +

I/O

O

Input

High

TTL. See also DAI port

TTL. TXEN in DAI port

Input. See also EADI port

TTL. See also DAI port

TTL input. Output in AUI

TTL input

Transmit Enable

O

SRDCLK

RXDAT

RXCRS

CLSN

Serial Receive Data Clock

Receive Data

I/O

I

Receive Carrier Sense

Collision

I/O

O

High

Low

DXCVR

Disable Transceiver

TTL low

Am79C940

17

PIN SUMMARY (continued)

Pin Name

Pin Function

Type

Active

Comment

External Address Detection Interface (EADI)

SF/BD

SRD

Start Frame/Byte Delimiter

Serial Receive Data

O

High

Low

EAM/R

SRDCLK

External Address Match/Reject

Serial Receive Data Clock

I

I/O

Output except in GPSI

Host System Interface

DBUS 15–0 Data Bus

I/O

High

High/Low

Low

ADD4–0

R/W

Address

I

Read/Write

RDTREQ

TDTREQ

DTV

Receive Data Transfer Request

Transmit Data Transfer Request

Data Transfer Valid

End Of Frame

Byte Enable 0

Byte Enable 1

Chip Select

O

I/O

I

Low

Tristate

EOF

Low

BE0

Low

BE1

I

Low

CS

I

Low

FDS

FIFO Data Strobe

Interrupt

I

Low

INTR

EDSEL

TC

O

I

Low

Open Drain

Edge Select

High

Low

Timing Control

System Clock

I

Internal pull-up

SCLK

RESET

I

High

Low

Reset

I

IEEE 1149.1 Test Access Port (TAP) Interface

TCK

TMS

TDI

Test Clock

I

Internal pull-up

Test Mode Select

Test Data Input

Test Data Out

I

TDO

O

General Interface

XTAL1

XTAL2

SLEEP

DV_DD

DV_SS

Crystal Input

I

CMOS

TTL

Crystal Output

O

I

Sleep Mode

Low

Digital Power (4 pins)

Digital Power (6 pins)

Analog Power (4 pins)

Analog Power (2 pins)

P

AV_DD

AV_SS

18

Am79C940

PIN DESCRIPTION

DI+/DI

Network Interfaces

Data In (Input)

The MACE device has five potential network inter-

faces. Only one of the interfaces that provides physical

network attachment can be used (active) at any time.

Selection between the AUI, 10BASE-T, DAI or GPSI

ports is provided by programming the PHY Configura-

tion Control register. The EADI port is effectively active

at all times. Some signals, primarily used for status

reporting, are active for more than one single interface

(the CLSN pin for instance). Under each of the descrip-

tions for the network interfaces, the primary signals

which are unique to that interface are described.

Where signals are active for multiple interfaces, they

are described once under the interface most appropri-

ate.

A differential input pair to the MACE device for receiv-

ing Manchester encoded data from the network.

Operates at pseudo-ECL levels.

DO+/DO

Data Out (Output)

A differential output pair from the MACE device for

transmitting Manchester encoded data to the network.

Operates at pseudo-ECL levels.

Digital Attachment Interface (DAI)

TXDAT+/TXDAT–

Transmit Data (Output)

When the DAI port is selected, TXDAT± are configured

as a complementary pair for Manchester encoded data

output from the MACE device, used to transmit data to

a local external network transceiver. During valid trans-

mission (indicated by TXEN low), a logical 1 is indi-

cated by the TXDAT+ pin being in the high state and

TXDAT– in the low state; and a logical 0 is indicated by

the TXDAT+ pin being in the low state and TXDAT– in

the high state. During idle (TXEN high), TXDAT+ will be

in the high state, and TXDAT– in the low state. When

the GPSI port is selected, TXDAT+ will provide NRZ

data output from the MAC core, and TXDAT– will be

held in the LOW state. Operates at TTL levels. The

operations of TXDAT+ and TXDAT– are defined in the

following tables:

Attachment Unit Interface (AUI)

CI+/CI

Control In (Input)

A differential input pair, signaling the MACE device that

a collision has been detected on the network media, in-

dicated by the CI± inputs being exercised with 10 MHz

pattern of sufficient amplitude and duration. Operates

at pseudo-ECL levels.

TXDAT + Configuration

PORTSEL

[1-0]

SLEEP

ENDPLSIO

Interface Description

Sleep Mode

AUI

Pin Function

High Impedance

0

1

XX

00

01

10

11

X

1

0

High Impedance (Note 2)

TXDAT+ Output

10BASE–T

DAI Port

GPSI

TXDAT+ Output

XX

Status Disabled

High Impedance (Note 2)

TXDAT – Configuration

PORTSEL

[1-0]

SLEEP

ENDPLSIO

Interface Description

Sleep Mode

AUI

Pin Function

High Impedance

TXDAT– Output

LOW

0

1

XX

00

01

10

11

X

1

0

10BASE–T

DAI Port

GPSI

XX

Status Disabled

High Impedance

Notes:

1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).

2. This pin should be externally terminated, if unused, to reduce power consumption.

Am79C940

19

decoded data input to the MAC core of the MACE

device, from an external Manchester encoder/decoder.

Operates at TTL levels.

TXEN/TXEN

Transmit Enable (Output)

When the AUI port is selected (PORTSEL [1-0] = 00),

an output indicating that the AUI DO± differential output

has valid Manchester encoded data is presented.

When the 10BASE-T port is selected (PORTSEL [1-0]

= 01), indicates that Manchester data is being output

on the TXD±/TXP± complementary outputs. When the

DAI port is selected (PORTSEL [1–0] = 10), indicates

that Manchester data is being output on the DAI port

TXDAT± complementary outputs. When the GPSI port

is selected (PORTSEL [1–0] =11), indicates that NRZ

data is being output from the MAC core of the MACE

device, to an external Manchester encoder/decoder, on

the TXDAT+ output. Active low when the DAI port is

selected, active high when the AUI, 10 BASE-T or

GPSI is selected. Operates at TTL levels.

RXCRS

Receive Carrier Sense (Input/Output)

When the AUI port is selected (PORTSEL [1–0] = 00),

an output indicating that the DI± input pair is receiving

valid Manchester encoded data from the external

transceiver which meets the signal amplitude and

pulse width requirements. When the 10BASE-T port is

selected (PORTSEL [1–0] = 01), an output indicating

that the RXD± input pair is receiving valid Manchester

encoded data from the twisted pair cable which meets

the signal amplitude and pulse width requirements.

RXCRS will be asserted high for the entire duration of

the receive message. When the DAI port is selected

(PORTSEL [1-0] = 10), an input signaling the MACE

device that a receive carrier condition has been

detected on the network, and valid Manchester

encoded data is being presented to the MACE device

on the RXDAT line. When the GPSI port is selected

(PORTSEL [1-0] = 11), an input signalling the internal

MAC core that valid NRZ data is being presented on

the RXDAT input. Operates at TTL levels.

RXDAT

Receive Data (Input)

When the DAI port is selected (PORTSEL [1–0] = 10),

the Manchester encoded data input to the integrated

clock recovery and Manchester decoder of the MACE

device, from an external network transceiver. When the

GPSI port is selected (PORTSEL [1–0] =11), the NRZ

TXEN/TXEN Configuration

PORTSEL

[1-0]

SLEEP

ENDPLSIO

Interface Description

Sleep Mode

AUI

Pin Function

High Impedance

0

1

XX

00

01

10

11

X

1

0

TXEN Output

10BASE-T

DAI Port

TXEN Output

GPSI

TXEN Output

XX

Status Disabled

High Impedance (Note 3)

Notes:

1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).

2. When the GPSI port is selected, TXEN should have an external pull-down attached (e.g. 3.3k Ω) to ensure the output is held

inactive before ENPLSIO is set.

3. This pin should be externally terminated, if unused, to reduce power consumption.

20

Am79C940

RXDAT Configuration

PORTSEL

SLEEP

[1–0]

ENPLSIO

Interface Description

Sleep Mode

AUI

Pin Function

0

1

XX

00

01

10

11

X

1

0

High Impedance

High Impedance (Note 2)

RXDAT Input

10BASE-T

DAI Port

GPSI

RXDAT Input

XX

Status Disabled

High Impedance (Note 2)

Notes:

1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).

2. This pin should be externally terminated, if unused, to reduce power consumption.

RXCRS Configuration

PORTSEL

SLEEP

[1-0]

XX

00

ENDPLSIO

Interface Description

Sleep Mode

AUI

Pin Function

High Impedance

0

1

X

1

0

RXCRS Output

01

10BASE-T

DAI Port

RXCRS Output

10

RXCRS Output

11

GPSI

RXCRS Output

XX

Status Disabled

High Impedance (Note 2)

Notes:

1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).

2. This pin should be externally terminated, if unused, to reduce power consumption.

dependent only on the status of the 10BASE-T link. If

DXCVR

the link is active (LNKST pin driven LOW) the

10BASE-T port will be used as the active network inter-

face. If the link is inactive (LNKST pin pulled HIGH) the

AUI port will be used as the active network interface.

Auto Select will continue to operate even when the

SLEEP pin is asserted if the RWAKE bit has been set.

The AWAKE bit does not allow the Auto Select func-

tion, and only the receive section of 10BASE-T port will

be active (DXCVR = HIGH).

Disable Transceiver (Output)

An output from the MACE device to indicate the net-

work port in use, as programmed by the ASEL bit or the

PORTSEL [1–0] bits. The output is provided to allow

power down of an external DC-to-DC converter, typi-

cally used to provide the voltage requirements for an

external 10BASE2 transceiver.

When the Auto Select (ASEL) feature is enabled, the

state of the PORTSEL [1–0] bits is overridden, and the

network interface will be selected by the MACE device,

Active (HIGH) when either the 10BASE-T or DAI port

is selected. Inactive (LOW) when the AUI or GPSI port

is selected.

Am79C940

21

DXCVR Configuration—SLEEP Operation

Sleep

RWAKE AWAKE

ASEL

Bit

LNKST

PORTSEL

[1–0] Bits

Interface

Description

Function

Bit

High

Sleep

Mode

High

0

X

0

1

XX

00

01

10

11

Impedance

High

1

0

AUI with EADI port

10BASE-T with EADI port

Invalid

LOW

HIGH

LOW

HIGH

Impedance

High

Impedance

High

Impedance

High

Invalid

Impedance

High

0X

AUI with EADI port

10BASE-T with EADI port

Impedance

High

Impedance

0

1

0

1

X

HIGH

LOW

X

0X

AUI with EADI port

10BASE-T with EADI port

10BASE-T

LOW

HIGH

Note:

1. RWAKE and ASEL are located in the PHY Configuration Control register (REG ADDR 15). PORTSEL [1–0] and ENPLSIO

are located in the PLS Configuration Control register (REG ADDR 14). All bits must be programmed prior to the assertion of

the SLEEP pin.

DXCVR Configuration—Normal Operation

SLEEP

ASEL

Bit

LNKST

PORTSEL

[1-0] Bits

ENPLSIO

BIT

Interface

Description

Function

High

1

X

XX

X

SIA Test Mode

Impedance

1

0

1

X

00

01

10

11

X

AUI

10BASE-T

DAI port

GPSI

LOW

HIGH

LOW

HIGH

X

HIGH

LOW

0X

AUI

10BASE-T

Note:

1. RWAKE and ASEL are located in the PHY Configuration Control register (REG ADDR 15). PORTSEL [1–0] and ENPLSIO

are located in the PLS Configuration Control register (REG ADDR 14).

22

Am79C940

10BASE-T INTERFACE

RXPOL

Receive Polarity (Output, Open Drain)

TXD+, TXD–

The twisted pair receiver is capable of detecting a

receive signal with reversed polarity (wiring error). The

RXPOL pin is normally in the LOW state, indicating

correct polarity of the received signal. If the receiver

detects a received packet with reversed polarity, then

this pin is not driven (requires external pull-up) and the

polarity of subsequent packets are inverted. In the

LOW output state, this pin is capable of sinking a

maximum of 12mA and can be used to drive an LED.

Transmit Data (Output)

10BASE–T port differential drivers.

TXP+, TXP–

Transmit Pre-Distortion (Output)

Transmit wave form differential driver for pre-distortion.

RXD+, RXD–

Receive Data (Input)

The polarity correction feature can be disabled by

setting the Disable Auto Polarity Correction (DAPC) bit

in the PHY Configuration Control register. In this case,

the Receive Polarity correction circuit is disabled and

the internal receive signal remains non-inverted,

irrespective of the received signal. Note that RXPOL

will continue to reflect the polarity detected by the

receiver.

10BASE–T port differential receiver. These pins should

be externally terminated to reduce power consumption

if the 10BASE–T interface is not used.

LNKST

Link Status (OutputOpen Drain)

This pin is driven LOW if the link is identified as func-

tional. If the link is determined to be nonfunctional, due

to missing idle link pulses or data packets, then this pin

is not driven (requires external pull-up). In the LOW

output state, the pin is capable of sinking a maximum

of 12 mA and can be used to drive an LED.

General Purpose Serial Interface (GPSI)

STDCLK

Serial Transmit Data Clock (Input/Output)

When either the AUI, 10BASE–T or DAI port is

selected, STDCLK is an output operating at one half the

crystal or XTAL1 frequency. STDCLK is the encoding

clock for Manchester data transferred to the output of

either the AUI DO± pair, the 10BASE-T TXD±/TXP±

pairs, or the DAI port TXDAT± pair. When using the

GPSI port, STDCLK is an input at the network data rate,

provided by the external Manchester encode/decoder,

to strobe out the NRZ data presented on the TXDAT+

output. This is also required for internal loopbacks while

in GPSI mode.

This feature can be disabled by setting the Disable Link

Test (DLNKTST) bit in the PHY Configuration Control

register. In this case the internal Link Test Receive

function is disabled, the LNKST pin will be driven LOW,

and the Transmit and Receive functions will remain

active regardless of arriving idle link pulses and data.

The internal 10BASE-T MAU will continue to generate

idle link pulses irrespective of the status of the

DLNKTST bit.

STDCLK Configuration

PORTSEL

[1-0]

SLEEP

ENDPLSIO

Interface Description

Sleep Mode

AUI

Pin Function

High Impedance

0

1

XX

00

01

10

11

X

1

0

STDCLK Output

10BASE-T

DAI Port

STDCLK Output

GPSI

STDCLK Output

XX

Status Disabled

High Impedance (Note 2)

Notes:

1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).

2. This pin should be externally terminated, if unused, to reduce power consumption.

Am79C940

23

CLSN

External Address Detection Interface

(EADI)

Collision (Input/Output)

SF/BD

An external indication that a collision condition has

been detected by the (internal or external) Medium

Attachment Unit (MAU), and that signals from two or

more nodes are present on the network. When the AUI

port is selected (PORTSEL [1–0] = 00), CLSN will be

activated when the CI± input pair is receiving a collision

indication from the external transceiver. CLSN will be

asserted high for the entire duration of the collision

detection, but will not be asserted during the SQE Test

message following a transmit message on the AUI.

When the 10BASE-T port is selected (PORTSEL [1–0]

= 01), CLSN will be asserted high when simultaneous

transmit and receive activity is detected (logically

detected when TXD±/TXP± and RXD± are both active).

When the DAI port is selected (PORTSEL [1–0] = 10),

CLSN will be asserted high when simultaneous trans-

mit and receive activity is detected (logically detected

when RXCRS and TXEN are both active). When the

GPSI port is selected (PORTSEL [1–0] = 11), an input

from the external Manchester encoder/decoder signal-

ing the MACE device that a collision condition has

been detected on the network, and any receive frame

in progress should be aborted.

Start Frame/Byte Delimiter (Output)

The external indication that a start of frame delimiter

has been received. The serial bit stream will follow on

the Serial Receive Data pin (SRD), commencing with

the destination address field. SF/BD will go high for 4

bit times (400 ns) after detecting the second 1 in the

SFD of a received frame. SF/BD will subsequently

toggle every 400 ns (1.25 MHz frequency) with the

rising edge indicating the start (first bit) in each

subsequent byte of the received serial bit stream.

SF/BD will be inactive during frame transmission.

SRD

Serial Receive Data (Output)

SRD is the decoded NRZ data from the network. It is

available for external address detection. Note that

when the 10BASE-T port is selected, transition on SRD

will only occur during receive activity. When the AUI or

DAI port is selected, transition on SRD will occur

dur ing both transmit and receive activity.

CLSN Configuration

PORTSEL

[1-0]

SLEEP

ENDPLSIO

Interface Description

Sleep Mode

AUI

Pin Function

High Impedance

0

1

XX

00

01

10

11

X

1

0

CLSN Output

10BASE-T

DAI Port

CLSN Output

GPSI

CLSN Output

XX

Status Disabled

High Impedance (Note 2)

Notes:

1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).

2. This pin should be externally terminated, if unused, to reduce power consumption.

EAM/R

SRDCLK

External Address Match/Reject(Input)

Serial Receive Data Clock (Input/Output)

The incoming frame will be received dependent on the

receive operational mode of the MACE device, and the

polarity of the EAM/R pin. The EAM/R pin function is

programmed by use of the M/R bit in the Receive

Frame Control register. If the bit is set, the pin is config-

ured as EAM. If the bit is reset, the pin is configured as

EAR. EAM/R can be asserted during packet reception

to accept or reject packets based on an external

address comparison.

The Serial Receive Data (SRD) output is synchronous

to SRDCLK running at the 10MHz receive data clock

frequency. The pin is configured as an input, only when

the GPSI port is selected. Note that when the

10BASE–T port is selected, transition on SRDCLK will

only occur during receive activity. When the AUI or DAI

port is selected, transition on SRDCLK will occur during

both transmit and receive activity.

24

Am79C940

SRD Configuration

ENDPLSIO Interface Description

PORTSEL

[1-0]

SLEEP

Pin Function

High Impedance

0

1

XX

00

01

10

11

X

1

0

Sleep Mode

AUI

SRD Output

High Impedance

10BASE-T

DAI Port

GPSI

XX

Status Disabled

Note:

1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).

SRDCLK Configuration

PORTSEL

SLEEP

[1-0]

XX

00

ENDPLSIO

Interface Description

Sleep Mode

AUI

Pin Function

High Impedance

0

1

X

1

0

SRDCLK Output

01

10BASE-T

DAI Port

SRDCLK Output

10

SRDCLK Output

11

GPSI

SRDCLK Output

XX

Status Disabled

High Impedance (Note 2)

Notes:

1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).

2. This pin should be externally terminated, if unused, to reduce power consumption.

Am79C940

25

request transmit data transfer when 16, 32 or 64 bytes

are available in the Transmit FIFO, by programming the

Transmit FIFO Watermark (XMTFW bits) in the FIFO

Configuration Control register. TDTREQ will be

asserted only when Enable Transmit (ENXMT) is set in

the MAC Configuration Control register.

HOST SYSTEM INTERFACE

DBUS15-0

Data Bus (Input/Output/3-state)

DBUS contains read and write data to and from internal

registers and the Transmit and Receive FIFOs.

ADD4-0

Address Bus (Input)

FDS

FIFO Data Select (Input)

FIFO Data Select allows direct access to the transmit

or Receive FIFO without use of the ADD address bus.

FDS must be activated in conjunction with R/W. When

the MACE device samples R/W as high and FDS low,

a read cycle from the Receive FIFO will be initiated.

When the MACE chip samples R/W and FDS low, a

write cycle to the Transmit FIFO will be initiated. The

CS line should be inactive (high) when FIFO access is

requested using the FDS pin. If the MACE device sam-

ples both CS and FDS as active simultaneously, no

cycle will be executed, and DTV will remain inactive.

ADD is used to access the internal registers and FIFOs

to be read or written.

R/W

Read/Write (Input)

Indicates the direction of data flow during the MACE

device register, Transmit FIFO, or Receive FIFO

accesses.

RDTREQ

Receive Data Transfer Request(Output)

Receive Data Transfer Request indicates that there is

data in the Receive FIFO to be read. When RDTREQ

is asserted there will be a minimum of 16 bytes to be

read except at the completion of the frame, in which

case EOF will be asserted. RDTREQ can be pro-

grammed to request receive data transfer when 16, 32

or 64 bytes are available in the Receive FIFO, by pro-

gramming the Receive FIFO Watermark (RCVFW bits)

in the FIFO Configuration Control register. The first

assertion of RDTREQ will not occur until at least 64

bytes have been received, and the frame has been ver-

ified as non runt. Runt packets will normally be deleted

from the Receive FIFO with no external activity on

RDTREQ. When Runt Packet Accept is enabled (RPA

bit) in the User Test Register, RDTREQ will be asserted

when the runt packet completes, and the entire frame

resides in the Receive FIFO. RDTREQ will be asserted

only when Enable Receive (ENRCV) is set in the MAC

Configuration Control register.

DTV

Data Transfer Valid (Output/3-state)

When asserted, indicates that the read or write opera-

tion has completed successfully. The absence of DTV

at the termination of a host access cycle on the MACE

device indicates that the data transfer was unsuccess-

ful. DTV need not be used if the system interface can

guarantee that the latency to TDTREQ and RDTREQ

assertion and de-assertion will not cause the Transmit

FIFO to be over-written or the Receive FIFO to be

over-read. In this case, the latching or strobing of read

or write data can be synchronized to the SCLK input

rather than to the DTV output.

EOF

End Of Frame (Input/Output/3-state)

End Of Frame will be asserted by the MACE device

when the last byte/word of frame data is read from the

Receive FIFO, indicating the completion of the frame

data field for the receive message. End Of Frame must

be asserted low to the MACE device when the last

byte/word of the frame is written into the Transmit

FIFO.

The RCVFW can be overridden by enabling the Low

Latency Receive function (setting LLRCV bit) in the

Receive Frame Control register, which allows

RDTREQ to be asserted after only 12 bytes have been

received. Note that use of this function exposes the

system interface to premature termination of the

receive frame, due to network events such as collisions

or runt packets. It is the responsibility of the system

designer to provide adequate recovery mechanisms for

these conditions.

BE1–0

Byte Enable (Input)

Used to indicate the active portion of the data transfer

to or from the internal FIFOs. For word (16-bit) trans-

fers, both BE0 and BE1 should be activated by the

external host/controller. Single byte transfers are per-

formed by identifying the active data bus byte and acti-

vating only one of the two signals. The function of the

BE1-0 pins is programmed using the BSWP bit (BIU

Configuration Control register, bit 6). BE1-0 are not

required for accesses to MACE device registers.

TDTREQ

Transmit Data Transfer Request (Output)

Transmit Data Transfer Request indicates there is

room in the Transmit FIFO for more data. TDTREQ is

asserted when there are a minimum of 16 empty bytes

in the Transmit FIFO. TDTREQ can be programmed to

26

Am79C940

CS

IEEE 1149.1 TEST ACCESS PORT (TAP)

INTERFACE

Chip Select (Input)

TCK

Used to access the MACE device FIFOs and internal

registers locations using the ADD address bus. The

FIFOs may alternatively be directly accessed without

supplying the FIFO address, by using the FDS and

R/W pins.

Test Clock (Input)

The clock input for the boundary scan test mode oper-

ation. TCK can operate up to 10 MHz. TCK has an in-

ternal (not SLEEP disabled) pull up.

INTR

TMS

Interrupt (Output, Open Drain)

Test Mode Select (Input)

An attention signal indicating that one or more of the

following status flags are set: XMTINT, RCVINT,

MPCO, RPCO, RCVCCO, CERR, BABL, or JAB. Each

interrupt source can be individually masked. No inter-

rupt condition can take place in the MACE device

immediately after a hardware or software reset.

A serial input bit stream used to define the specific

boundary scan test to be executed. TMS has an inter-

nal (not SLEEP disabled) pull up.

TDI

Test Data Input (Input)

RESET

The test data input path to the MACE device. TDI has

an internal (not SLEEP disabled) pull up.

Reset (Input)

Reset clears the internal logic. Reset can be asynchro-

nous to SCLK, but must be asserted for a minimum

duration of 15 SCLK cycles.

TDO

Test Data Out (Output)

The test data output path from the MACE device.

SCLK

System Clock (Input)

GENERAL INTERFACE

XTAL1

Crystal Connection (Input)

The system clock input controls the operational fre-

quency of the slave interface to the MACE device and

the internal processing of frames. SCLK is unrelated to

the 20 MHz clock frequency required for the 802.3/

Ethernet interface. The SCLK frequency range is

1 MHz-25 MHz.

The internal clock generator uses a 20 MHz crystal that

is attached to pins XTAL1 and XTAL2. Internally, the

20 MHz crystal frequency is divided by two which

determines the network data rate. Alternatively, an

external 20 MHz CMOS-compatible clock signal can be

used to drive this pin. The MACE device supports the

use of 50 pF crystals to generate a 20 MHz frequency

which is compatible with the IEEE 802.3 network

fre quency tolerance and jitter specifications.

EDSEL

System Clock Edge Select (Input)

EDSEL is a static input that allows System Clock

(SCLK) edge selection. If EDSEL is tied high, the bus

interface unit will assume falling edge timing. If EDSEL

is tied low, the bus interface unit will assume rising

edge timing, which will effectively invert the SCLK as it

enters the MACE device, i.e., the address, control lines

(CS, R/_W, FDS, etc) and data are all latched on the ris-

ing edge of SCLK, and data out is driven off the rising

edge of SCLK.

XTAL2

Crystal Connection (Output)

The internal clock generator uses a 20 MHz crystal that

is attached to pins XTAL1 and XTAL2. If an external

clock generator is used on XTAL1, then XTAL2 should

be left unconnected.

TC

Timing Control (Input)

SLEEP

Sleep Mode (Input)

The Timing Control input conditions the minimum num-

ber of System Clocks (SCLK) cycles taken to read or

write the internal registers and FIFOs. TC can be used

as a wait state generator, to allow additional time for

data to be presented by the host during a write cycle,

or allow additional time for the data to be latched during

a read cycle. TC has an internal (SLEEP disabled)

pull up.

The optimal power savings made is extracted by

asserting the SLEEP pin with both the Auto Wake

(AWAKE bit) and Remote Wake (RWAKE bit) functions

disabled. In this “deep sleep” mode, all outputs will be

forced into their inactive or high impedance state, and

all inputs will be ignored except for the SLEEP, RESET,

SCLK, TCK, TMS, and TDI pins. SCLK must run for 5

cycles after the assertion of SLEEP. During the “Deep

Sleep”, the SCLK input can be optionally suspended

for maximum power savings. Upon exiting “Deep

Sleep”, the hardware RESET pin must be asserted and

the SCLK restored. The system must delay the setting

Timing Control

Number of

TC

Clocks

1

2

3

0

Am79C940

27

of the bits in the MAC configuration Control Register of

the internal analog circuits by 1 ns to allow for

stabilization.

power and ground pins are not deleted. The MACE

device does have several sets of media interfaces

which typically go unused in most designs, however.

Pins from some of these interfaces are deleted instead.

Removed are the following:

If the AWAKE bit is set prior to the activation of SLEEP,

the 10BASE–T receiver and the LNKST output pin

remain operational.

ꢀ TXDAT– (previously used for the DAI interface)

ꢀ SRD (previously used for the EADI interface)

ꢀ DTV (previously used for the host interface)

If the RWAKE bit is set prior to SLEEP being asserted,

the Manchester encoder/decoder, AUI and 10BASE-T

cells remain operational, as do the SRD, SRDCLK and

SF/BD outputs.

ꢀ RXPOL (previously used as a receive frame polarity

LED driver)

The input on XTAL1 must remain active for the AWAKE

or RWAKE features to operate. After exit from the Auto

Wake or Remote Wake modes, activation of hardware

RESET is not required when SLEEP is reasserted.

Note that pins from four separate interfaces are

removed rather than removing all the pins from a single

interface. Each of these pins comes from one of the

four sides of the device. This is done to maintain sym-

metry, thus avoiding bond out problems.

On deassertion of SLEEP, the MACE device will go

through an internally generated hardware reset

sequence, requiring re-initialization of MACE registers.

In general, the most critical of the four removed pins

are TXDAT– and SRD. Depending on the application,

either the DAI or the EADI interface may be important.

In most designs, however, this will not be the case.

Power Supply

DV_DD

PINS REMOVED FOR TQFP PACKAGE

AND THEIR EFFECTS

TXDAT–

Digital Power

There are four Digital V

pins.

DD

DV_SS

The removal of TXDAT– means that the DAI interface is

no longer usable. The DAI interface was designed to be

used with media types that do not require DC isolation

between the MAU and the DTE. Media which do not re-

quire DC isolation can be implemented more simply

using the DAI interface, rather than the AUI interface. In

most designs this is not a problem because most media

requires DC isolation (10BASE-T, 10BASE2, 10BASE5)

and will use the AUI port. About the only media which

does not require DC isolation is 10BASE-F.

Digital Ground

There are six Digital V pins.

SS

AV_DD

Analog Power

There are four analog VDD pins. Special attention

should be paid to the printed circuit board layout to

avoid excessive noise on the supply to the PLL in the

Manchester encoder/decoder (pins 66 and 83 in PLCC,

pins 67 and 88 in PQFP). These supply lines should be

SRD

kept separate from the DV

lines as far back to the

DD

The SRD pin is an output pin used by the MACE device

to transfer a receive data stream to external address

detection logic. It is part of the EADI interface. This pin

is used to help interface the MACE device to an exter-

nal CAM device. Use of an external CAM is typically

required when an application will operate in promiscu-

ous mode and will need perfect filtering (i.e., the inter-

nal hash filter will not suffice). Example applications for

this sort of operation are bridges and routers. Lack of

perfect filtering in these applications forces the CPU to

be more involved in filtering and thus either slows the

forwarding rates achieved or forces the use of a more

powerful CPU.

power supply as is practically possible.

AV_SS

Analog Ground

There are two analog VSS pins. Special attention

should be paid to the printed circuit board layout to

avoid excessive noise on the PLL supply in Manches-

ter encoder/decoder (pin 73 in PLCC, pin 74 in PQFP).

These supply lines should be kept separate from the

DV

lines as far back to the power supply as is

SS

practically possible.

PIN FUNCTIONS NOT AVAILABLE WITH

THE 80-PIN TQFP PACKAGE

DTV

In the 84-pin PLCC configuration, ALL the pins are

used while in the 100-pin PQFP version, 16 pins are

specified as No Connects. Moving to the 80-pin TQFP

configuration requires the removal of 4 pins. Since

Ethernet controllers with integrated 10BASE-T have

analog portions which are very sensitive to noise,

The DTV pin is part of the host interface to the MACE

device. It is used to indicate that a read or write cycle

to the MACE device was successful. If DTV is not as-

serted at the end of a cycle, the data transfer was not

successful. Basically, this will happen on a write to a

full transmit FIFO or a read from an empty receive

28

Am79C940

FIFO. In general, there are ways to ensure that a

transfer is always valid; so this pin is not required in

many designs. For instance, the TDTREQ and

RDTREQ pins can be used to monitor the state of the

FIFOs to ensure that data transfer only occurs at the

correct times.

RXPOL

RXPOL is typically used to drive an LED indicating the

polarity of receive frames. This function is not

necessary for correct operation of the Ethernet and

serves strictly as a status indication to a user. The sta-

tus of the receive polarity is still available through the

PHYCC register.

Am79C940

29

ing CS and R/W. An alternative FIFO access

mechanism allows the use of the FDS and the R/W

lines, ignoring the address lines (ADD4-0). The state of

the R/W line in conjunction with the FDS input deter-

mines whether the Receive FIFO is read (R/W high) or

the Transmit FIFO written (R/W low). The MACE de-

vice system interface permits interleaved transmit and

receive bus transfers, allowing the Transmit FIFO to be

filled (primed) while a frame is being received from the

network and/or read from the Receive FIFO.

FUNCTIONAL DESCRIPTION

The Media Access Controller for Ethernet (MACE) chip

embodies the Media Access Control (MAC) and Phys-

ical Signaling (PLS) sub-layers of the 802.3 Standard.

The MACE device provides the IEEE defined Attach-

ment Unit Interface (AUI) for coupling to remote Media

Attachment Units (MAUs) or on-board transceivers.

The MACE device also provides a Digital Attachment

Interface (DAI), by-passing the differential

AUI interface.

In receive operation, the MACE device asserts Receive

Data Transfer Request (RDTREQ) when the FIFO con-

tains adequate data. For the first indication of a new

receive frame, 64 bytes must be received, assuming

normal operation. Once the initial 64 byte threshold has

been reached, RDTREQ assertion and de-assertion is

dependent on the programming of the Receive FIFO

Watermark (RCVFW bits in the BIU Configuration Con-

trol register). The RDTREQ can be programmed to

activate when there are 16, 32 or 64 bytes of data avail-

able in the Receive FIFO. Enable Receive (ENRCV bit

in MAC Configuration Control register) must be set to

assert RDTREQ. If the Runt Packet Accept feature is

invoked (RPA bit in User Test Register), RDTREQ will

be asserted for receive frames of less than 64 bytes on

the basis of internal and/or external address match

only. When RPA is set, RDTREQ will be asserted when

the entire frame has been received or when the initial

64 byte threshold has been exceeded. See the FIFO

Sub-Systems section for further details.

The system interface provides a fundamental data

conduit to and from an 802.3 network. The MACE de-

vice in conjunction with a user defined DMA engine,

provides an 802.3 interface tailored to a specific

application.

In addition, the MACE device can be combined with

similarly architected peripheral devices and a

multi-channel DMA controller, thereby providing the

system with access to multiple peripheral devices with

a single master interface to memory.

Network Interfaces

The MACE device can be connected to an 802.3 net-

work using any one of the AUI, 10 BASE-T, DAI and

GPSI network interfaces. The Attachment Unit Inter-

face (AUI) provides an IEEE compliant differential in-

terface to a remote MAU or an on-board transceiver.

An integrated 10BASE-T MAU provides a direct inter-

face for twisted pair Ethernet networks. The DAI port

can connect to local transceiver devices for 10BASE2,

10BASE-T or 10BASE-F connections. A General Pur-

pose Serial Interface (GPSI) is supported, which effec-

tively bypasses the integrated Manchester encoder/

decoder, and allows direct access to/from the integral

802.3 Media Access Controller (MAC) to provide sup-

port for external encoding/decoding schemes. The in-

terface in use is determined by the PORTSEL [1-0] bits

in the PLS Configuration Control register.

Note that the Receive FIFO may not contain 64 data

bytes at the time RDTREQ is asserted, if the automatic

pad stripping feature has been enabled (ASTRP RCV

bit in the Receive Frame Control register) and a mini-

mum length packet with pad is received. The MACE

device will check for the minimum received length from

the network, strip the pad characters, and pass only the

data frame through the Receive FIFO.

If the Low Latency Receive feature is enabled (LLRCV

bit set in Receive Frame Control Register), RDTREQ

will be asserted once a low watermark threshold has

been reached (12 bytes plus some additional synchro-

nization time). Note that the system interface will there-

fore be exposed to potential disruption of the receive

frame due to a network condition (see the FIFO

Sub-System description for additional details).

The EADI port does not provide network connectivity,

but allows an optional external circuit to assist in

receive packet accept/reject.

System Interface

The MACE device is a slave register based peripheral.

All transfers to and from the device, including data, are

performed using simple memory or I/O read and write

commands. Access to all registers, including the Trans-

mit and Receive FIFOs, are performed with identical

read or write timing. All information on the system inter-

face is synchronous to the system clock (SCLK), which

allows simple external logic to be designed to

interrogate the device status and control the network

data flow.

In transmit operation, the MACE device asserts Trans-

mit Data Transfer Request (TDTREQ) dependent on

the programming of the Transmit FIFO Watermark

(XMTFW bits in the BIU Configuration Control register).

TDTREQ will be permanently asserted when the

Transmit FIFO is empty. The TDTREQ can be pro-

grammed to activate when there are 16, 32 or 64 bytes

of space available in the Transmit FIFO. Enable Trans-

mit (ENXMT bit in MAC Configuration Control register)

must be set to assert TDTREQ. Write cycles to the

The Receive and Transmit FIFOs can be read or writ-

ten by driving the appropriate address lines and assert-

30

Am79C940

Transmit FIFO will not return DTV if ENXMT is dis-

abled, and no data will be written. The MACE device

will commence the preamble sequence once the

Transmit Start Point (XMTSP bits in BIU Configuration

Control register) threshold is reached in the Transmit

FIFO.

If byte operation is required, read/write transfers can be

performed on either the upper or lower data bus by

asserting the appropriate byte enable. For instance

with BSWP = 0, reading from or writing to DBUS15-8 is

accomplished by asserting BE1, and allows the data

stream to be read from or written to the appropriate

FIFO in byte order (byte 0, byte 1,....byte n). It is equally

valid to read or write the data stream using DBUS7–0

and by asserting BE0. For BSWP = 1, reading from or

writing to DBUS15-8 is accomplished by asserting BE0,

and allows the byte stream to be transferred in byte

order.

The Transmit FIFO data will not be overwritten until at

least 512 data bits have been transmitted onto the net-

work. If a collision occurs within the slot time (512 bit

time) window, the MACE device will generate a jam se-

quence (a 32-bit all zeroes pattern) before ceasing the

transmission. The Transmit FIFO will be reset to point

at the start of the transmit data field, and the message

will be retried after the random back-off interval has

expired.

When word operations are required, BSWP ensures

that the byte ordering of the target memory is compati-

ble with the 802.3 requirement to send/receive the data

stream in byte ascending order. With BSWP = 0, the

data transferred to/from the FIFO assumes that byte n

will be on DBUS7-0 (activated by BE0) and byte n+1

will be on DBUS15-8 (activated by BE1). With BSWP =

1, the data transferred to/from the FIFO assumes that

byte n will be presented on DBUS15-8 (activated by

BE0), and byte n+1 will be on DBUS7-0 (activated by

BE1).

DETAILED FUNCTIONS

Block Level Description

The following sections describe the major sub-blocks

of and the external interfaces to the MACE device.

Bus Interface Unit (BIU)

The BIU performs the interface between the host or

system bus and the Transmit and Receive FIFOs, as

well as all chip control and status registers. The BIU

can be configured to accept data presented in either lit-

tle-endian or big indian format, minimizing the external

logic required to access the MACE device internal

FIFOs and registers. In addition, the BIU directly

supports 8-bit transfers and incorporates features to

simplify interfacing to 32-bit systems using

external latches.

There are some additional special cases to the above

generalized rules, which are as follows:

(a) When performing byte read operations, both

halves of the data bus are driven with identical

data, effectively allowing the user to arbitrarily read

from either the upper or lower data bus, when only

one of the byte enables is activated.

(b) When byte write operations are performed, the

Transmit FIFO latency is affected. See the FIFO

Sub-System section for additional details.

Externally, the FIFOs appear as two independent reg-

isters located at individual addresses. The remainder

of the internal registers occupy 30 additional consecu-

tive addresses, and appear as 8-bits wide.

(c) If a word read is performed on the last data byte of

a receive frame (EOF is asserted), and the mes-

sage contained an odd number of bytes but the

host requested a word operation by asserting both

BE0 and BE1, then the MACE device will present

one valid and one non-valid byte on the data bus.

The placement of valid data for the data byte is de-

pendent on the target memory architecture. Re-

gardless of BSWP, the single valid byte will be read

from the BE0 memory bank. If BSWP = 0, BE0 cor-

responds to DBUS7-0; if BSWP = 1, BE0 corre-

sponds to DBUS15-8.

BIU to FIFO Data Path

The BIU operates assuming that the 16-bit data path

to/from the internal FIFOs is configured as two inde-

pendent byte paths, activated by the Byte Enable

sig nals BE0 and BE1.

BE0 and BE1 are only used during accesses to the

16-bit wide Transmit and Receive FIFOs. After hard-

ware or software reset, the BSWP bit will be cleared.

FIFO accesses to the MACE device will operate

assuming an Intel 80x86 type memory convention

(most significant byte of a word stored in the higher

addressed byte). Word data transfers to/from the

FIFOs over the DBUS15-0 lines will have the least sig-

nificant byte located on DBUS7-0 (activated by BE0)

and the most significant byte located on DBUS15-8

(activated by BE1).

(d) If a byte read is performed when the last data byte

is read for a receive frame (when the MACE device

activates the EOF signal), then the same byte will

be presented on both the upper and lower byte of

the data bus, regardless of which byte enable was

activated (as is the case for all byte read opera-

tions).

FIFO data can be read or written using either byte and/

or word operations.

(e) When writing the last byte in a transmit message

to the Transmit FIFO, the portion of the data bus

Am79C940

31

that the last byte is transferred over is irrelevant,

providing the appropriate byte enable is used. For

BSWP = 0, data can be presented on DBUS7-0

using BE0 or DBUS15-8 using BE1. For BSWP =

1, data can be presented on DBUS7-0 using BE1

or DBUS15-8 using BE0.

Byte Alignment For Register Write Operations

BE0

BE1

BSWP

DBUS7-0

Write

DBUS15-8

X

0

X

Data

X

1

Write

Data

(f) When neither BE0 nor BE1 are asserted, no data

transfer will take place. DTV will not be asserted.

X

FIFO Subsystem

Byte Alignment For FIFO Read Operations

The MACE device has two independent FIFOs, with

128-bytes for receive and 136-bytes for transmit oper-

ations. The FIFO sub-system contains both the FIFOs,

and the control logic to handle normal and exception

related conditions.

BE0

0

BE1

0

BSWP

DBUS7-0

DBUS15-8

0

1

n

n+1

n

0

1

0

n

The Transmit and Receive FIFOs interface on the net-

work side with the serializer/de-serializer in the MAC

engine. The BIU provides access between the FIFOs

and the host system to enable the movement of data to

and from the network.

1

X

n

0

n+1

n

0

1

n

1

0

n

Internally, the FIFOs appear to the BIU as independent

16-bit wide registers. Bytes or words can be written to

the Transmit FIFO (XMTFIFO), or read from the

Receive FIFO (RCVFIFO). Byte and word transfers

can be mixed in any order. The BIU will ensure correct

byte ordering dependent on the target host system, as

determined by the programming of the BSWP bit in the

BIU Configuration Control register.

1

X

Byte Alignment For FIFO Write Operations

BE0

0

BE1

0

BSWP

DBUS7-0

DBUS15-8

0

1

n

n+1

X

0

1

The XMTFIFO and RCVFIFO have three different

modes of operation. These are Normal (Default), Burst

and Low Latency Receive. Default operation will be

used after the hardware RESET pin or software

SWRST bit have been activated. The remainder of this

general description applies to all modes except where

specific differences are noted.

1

0

X

n

1

X

0

n+1

X

n

0

1

n

1

0

n

X

Transmit FIFO—General Operation

1

X

When writing bytes to the XMTFIFO, certain restric-

tions apply. These restrictions have a direct influence

on the latency provided by the FIFO to the host system.

When a byte is written to the FIFO location, the entire

word location is used. The unused byte is marked as a

hole in the XMTFIFO. These holes are skipped during

the serialization process performed by the MAC

engine, when the bytes are unloaded from the

XMTFIFO.

BIU to Control and Status

Register Data Path

All registers in the address range 2-31 are 8-bits wide.

When a read cycle is executed on any of these regis-

ters, the MACE device will drive data on both bytes of

the data bus, regardless of the programming of BSWP.

When a write cycle is executed, the MACE device

strobes in data based on the programming of BSWP as

shown in the tables below. All accesses to addresses

2-31 are independent of the BE0 and BE1 pins.

For instance, assume the Transmit FIFO Watermark

(XMTFW) is set for 32 write cycles. If the host writes

byte wide data to the XMTFIFO, after 36 write cycles

there will be space left in the XMTFIFO for only 32

more write cycles. Therefore TDTREQ will de-assert

even though only 36-bytes of data have been loaded

into the XMTFIFO. Transmission will not commence

until 64-bytes or the End-of-Frame are available in the

XMFIFO, so transmission would not start, and

Byte Alignment For Register Read Operations

BE0

BE1

BSWP

DBUS7-0

Read

DBUS15-8

Read

X

0

Data

X

1

Read

Data

32

Am79C940

TDTREQ would remain de-asserted. Hence for byte

wide data transfers, the XMTFW should be pro-

grammed to the 8 or 16 write cycle limit, or the host

should ensure that sufficient data will be written to the

XMTFIFO after TDTREQ has been de-asserted (which

is permitted), to guarantee that the transmission will

commence. A third alternative is to program the Trans-

mit Start Point (XMTSP) in the BIU Configuration Con-

trol register to below the 64-byte default; thereby

imposing a lower latency to the host system requiring

additional data to ensure the XMTFIFO does not

underflow during the transmit process, versus using

the default XMTSP value. Note that if 64 single byte

writes are executed on the XMTFIFO, and the XMTSP

is set to 64-bytes, the transmission will commence, and

all 64-bytes of information will be accepted by

the XMTFIFO.

The host must be aware that additional space exists in

the XMTFIFO although TDTREQ becomes inactive,

and must continue to write data to ensure the XMTSP

threshold is achieved. No transmit activity will com-

mence until the XMTSP threshold is reached.

Once 36 write cycles have been executed.

Note that write cycles can be performed to the XMT-

FIFO even if the TDTREQ is inactive. When TDTREQ

is asserted, it guarantees that a minimum amount of

space exists, when TDTREQ is deasserted, it does not

necessarily indicate that there is no space in the XMT-

FIFO. The DTV pin will indicate the successful accep-

tance of data by the Transmit FIFO.

As another example, assume again that the XMTFW is

programmed for 32 write cycles. If the host writes word

wide data continuously to the XMTFIFO, the TDTREQ

will deassert when 36 writes have executed on the

XMTFIFO, at which point 72-bytes will have been writ-

ten to the XMTFIFO, the 64-byte XMTSP will have

been exceeded and the transmission of preamble will

have commenced. TDTREQ will not re-assert until the

transmission of the packet data has commenced and

the possibility of losing data due to a collision within the

slot time is removed (512 bits have been transmitted

without a collision indication). Assuming that the host

actually stopped writing data after the initial 72-bytes,

there will be only 16-bytes of data remaining in the

XMTFIFO (8-bytes of preamble/SFD plus 56-bytes of

data have been transmitted), corresponding to 12.8 µs

of latency before an XMTFIFO underrun occurs. This

latency is considerably less than the maximum possi-

ble 57.6 µs the system may have assumed. If the host

had continued with the block transfer until 64 write

cycles had been performed, 128-bytes would have

been written to the XMTFIFO, and 72-bytes of latency

would remain (57.6 µs) when TDTREQ was re-as-

serted.

The number of write cycles that the host uses to write

the packet into the Transmit FIFO will also directly in-

fluence the amount of space utilized by the transmit

message. If the number of write cycles (n) required to

transfer a packet to the Transmit FIFO is even, the

number of bytes used in the Transmit FIFO will be 2*n.

If the number of write cycles required to transfer a

packet to the Transmit FIFO is odd, the number of

bytes used in the Transmit FIFO will be 2*n + 2 be-

cause the End Of Frame indication in the XMTFIFO is

always placed at the end of a 4-byte boundary. For ex-

ample, a 32-byte message written as bytes (n = 32 cy-

cles) will use 64-bytes of space in the Transmit FIFO

(2*n = 64), whereas a 65-byte message written as 32

words and 1 byte (n = 33 cycles) would use 68-bytes

(2*n + 2 = 68) .

The Transmit FIFO has been sized appropriately to

minimize the system interface overhead. However,

consideration must be given to overall system design if

byte writes are supported. In order to guarantee that

sufficient space is present in the XMTFIFO to accept

the number of write cycles programmed by the XMTFW

(including an End Of Frame delimiter), TDTREQ may

go inactive before the XMTSP threshold is reached

when using the non burst mode (XMTBRST = 0). For

instance, assume that the XMTFW is programmed to

allow 32 write cycles (default), and XMTSP is pro-

grammed to require 64 bytes (default) before starting

transmission. Assuming that the host bursts the trans-

mit data in a 32 cycle block, writing a single byte any-

where within this block will mean that XMTSP will not

have been reached. This would be a typical scenario if

the transmit data buffer was not aligned to a word

boundary. The MACE device will continue to assert

TDTREQ since an additional 36 write cycles can still be

executed. If the host starts a second burst, the XMTSP

will be reached, and TDTREQ will deassert when less

that 32 write cycle can be performed although the data

written by the host will continue to be accepted.

Transmit FIFO—Burst Operation

The XMTFIFO burst mode, programmed by the XMT-

BRST bit in the FIFO Configuration Control register,

modifies TDTREQ behavior. The assertion of TDTREQ

is controlled by the programming of the XMTFW bits,

such that when the specified number of write cycles

can be guaranteed (8, 16 or 32), TDTREQ will be as-

serted. TDTREQ will be de-asserted when the

XMT FIFO can only accept a single write cycle (one

word write including an End Of Frame delimiter) allow-

ing the external device to burst data into the XMTFIFO

when TDTREQ is asserted, and stop when TDTREQ

is deasserted.

Receive FIFO—General Operation

The Receive FIFO contains additional logic to ensure

that sufficient data is present in the RCVFIFO to allow

the specified number of bytes to be read, regardless of

the ordering of byte/word read accesses. This has an

Am79C940

33

impact on the perceived latency that the Receive FIFO

provides to the host system. The description and table

below outline the point at which RDTREQ will be

asserted when the first duration of the packet has been

received and when any subsequent transfer of the

packet to the host system is required.

ꢀ The RCVFW threshold is reached plus an additional

12 bytes. The additional 12 bytes are necessary to

ensure that any permutation of byte/word read

access is guaranteed. They are required for all

threshold values, but in the case of the 16 and

32-byte thresholds, the requirement that the slot time

criteria is met dominates. Any subsequent assertion

of RDTREQ necessary to complete the transfer of

the packet will occur after the RCVFW threshold is

reached plus an additional 12 bytes. The table below

also outlines the latency provided by the MACE de-

vice when the RDTREQ is asserted.

No preamble/SFD bytes are loaded into the Receive

FIFO. All references to bytes pass through the receive

FIFO. These references are received after the pream-

ble/SFD sequence.

The first assertion of RDTREQ for a packet will occur

after the longer of the following two conditions is met:

ꢀ 64-bytes have been received (to assure runt pack-

ets and packets experiencing collision within the

slot time will be rejected).

Receive FIFO Watermarks, RDTREQ Assertion and Latency

Bytes Required for Bytes of Latency Bytes Required for

After First Assertion Subsequent Assertion

Bytes of Latency After

Subsequent Assertion

of RDTREQ

RCVFW

[1-0]

First Assertion of

RDTREQ

of RDTREQ

00

01

10

11

64

76

XX

64

52

XX

28

44

76

XX

100

84

52

XX

Receive FIFO—Burst Operation

assertion of RDTREQ. An Ethernet-to-Ethernet bridge

employing the MACE device (on all the Ethernet

connections) with the XMTSP of all MACE controller

XMT FIFOs set to the minimum (4-bytes), forwarding of

a receive packet can be achieved within a sub 20 µs

delay including processing overhead.

The RCVFIFO also provides a burst mode capability,

programmed by the RCVBRST bit in the FIFO Config-

uration Control register, to modify the operation of

RDTREQ.The assertion of RDTREQ will occur accord-

ing to the programming of the RCVFW bits. RDTREQ

will be de-asserted when the RCVFIFO can only pro-

vide a single read cycle (one word read). This allows

the external device to burst data from the RCVFIFO

once RDTREQ is asserted, and stop when RDTREQ

is deasserted.

Note, however, that this mode places significant bur-

den on the host processor. The receiving MACE device

will no longer delete runt packets. A runt packet will

have the Receive Frame Status appended to the re-

ceive data which the host must read as normal. The

MACE device will not attempt to delete runt packets

from the RCVFIFO in the Low Latency Receive mode.

Collision fragments will also be passed to the host if

they are detected after the 12-byte threshold has been

reached. If a collision occurs, the Receive Frame Sta-

tus (RCVFS) will be appended to the data successfully

received in the RCVFIFO up to the point the collision

was detected. No additional receive data will be written

to the RCVFIFO. Note that the RCVFS will not become

available until after the receive activity ceases. The col-

lision indication (CLSN) in the Receive Status

(RCVSTS) will be set, and the Receive Message Byte

Count (RCVCNT) will be the correct count of the total

duration of activity, including the period that collision

was detected. The detection of normal (slot time) colli-

sions versus late collisions can only be made by

counting the number of bytes that were successfully re-

ceived prior to the termination of the packet data.

Receive FIFO—Low Latency Receive Operation

The LOW Latency Receive mode can be programmed

using the Low Latency Receive bit (LLRCV in the

Receive Frame Control register). This effectively

causes the assertion of RDTREQ to be directly coupled

to the low watermark of 12 bytes in the RCVFIFO.

Once the 12-byte threshold is reached (plus some

internal synchronization delay of less than 1 byte),

RDTREQ will be asserted, and will remain active until

the RCVFIFO can support only one read cycle

(one word of data), as in the burst operation

described earlier. The exception is the case where 4-8

bytes of padding is required by the FIFO design, unless

it is the end of the packet.

The intended use for the Low Latency Receive mode is

to allow fast forwarding of a received packet in a bridge

application. In this case, the receiving process is made

aware of the receive packet after only 9.6 µs, instead of

waiting up to 60.8 µs (76-bytes) necessary for the initial

In all cases where the reception ends prematurely (runt

or collision), the data that was successfully received

34

Am79C940

prior to the termination of reception must be read from

the RCVFIFO before the RCVFS bytes are available.

of packet data) messages to be transmitted

and/or received.

Media Access Control (MAC)

Framing (Frame Boundary Delimitation,

Frame Synchronization)

The Media Access Control engine is the heart of the

MACE device, incorporating the essential protocol

requirements for operation of a compliant Ethernet/

802.3 node, and providing the interface between the

FIFO sub-system and the Manchester Encoder/

Decoder (MENDEC).

The MACE device will autonomously handle the con-

struction of the transmit frame. When the Transmit

FIFO has been filled to the predetermined threshold

(set by XMTSP), and providing access to the channel

is currently permitted, the MACE device will commence

the 7 byte preamble sequence (10101010b, where first

bit transmitted is a 1). The MACE device will subse-

quently append the Start Frame Delimiter (SFD) byte

(10101011) followed by the serialized data from the

Transmit FIFO. Once the data has been completed, the

MACE device will append the FCS (most significant bit

first) computed on the entire data portion of the

message.

The MAC engine is fully compliant to Section 4 of ISO/

IEC 8802-3 (ANSI/IEEE Standard 1990 Second edi-

tion) and ANSI/IEEE 802.3 (1985).

The MAC engine provides enhanced features, pro-

grammed through the Transmit Frame Control and

Receive Frame Control registers, designed to minimize

host supervision and pre or post message processing.

These features include the ability to disable retries after

a collision, dynamic FCS generation on a

packet-by-packet basis, and automatic pad field

insertion and deletion to enforce minimum frame

size attributes.

Note that the user is responsible for the correct order-

ing and content in each of the fields in the frame,

including the destination address, source address,

length/type and packet data.

The receive section of the MACE device will detect an

incoming preamble sequence and lock to the encoded

clock. The internal MENDEC will decode the serial bit

stream and present this to the MAC engine. The MAC

will discard the first 8-bits of information before search-

ing for the SFD sequence. Once the SFD is detected,

all subsequent bits are treated as part of the frame. The

MACE device will inspect the length field to ensure

minimum frame size, strip unnecessary pad characters

(if enabled), and pass the remaining bytes through the

Receive FIFO to the host. If pad stripping is performed,

the MACE device will also strip the received FCS

bytes, although the normal FCS computation and

checking will occur. Note that apart from pad stripping,

the frame will be passed unmodified to the host. If the

length field has a value of 46 or greater, the MACE de-

vice will not attempt to validate the length against the

number of bytes contained in the message.

The two primary attributes of the MAC engine are:

ꢀ Transmit and receive message data encapsulation

— Framing (frame boundary delimitation, frame

synchronization)

— Addressing (source and destination address

handling)

— Error detection (physical medium transmission

errors)

ꢀ Media access management

— Medium allocation (collision avoidance)

— Contention resolution (collision handling)

Transmit and Receive Message Data

Encapsulation

Data passed to the MACE device Transmit FIFO will be

assumed to be correctly formatted for transmission

over the network as a valid packet. The user is required

to pass the data stream for transmission to the MACE

chip in the correct order, according to the byte ordering

convention programmed for the BIU.

If the frame terminates or suffers a collision before

64-bytes of information (after SFD) have been

received, the MACE device will automatically delete

the frame from the Receive FIFO, without host inter-

vention. Note however, that if the Low Latency Receive

option has been enabled (LLRCV = 1 in the Receive

Frame Control register), the MACE device will not

delete receive frames which experience a collision

once the 12-byte low watermark has been reached

(see the FIFO Sub-System section for additional

details).

The MACE device provides minimum frame size

enforcement for transmit and receive packets. When

APAD XMT = 1 (default), transmit messages will be

padded with sufficient bytes (containing 00h) to ensure

that the receiving station will observe an information

field (destination address, source address, length/type,

data and FCS) of 64-bytes. When ASTRP RCV = 1

(default), the receiver will automatically strip pad and

FCS bytes from the received message if the value in

the length field is below the minimum data size

(46-bytes). Both features can be independently

over-ridden to allow illegally short (less than 64-bytes

Addressing (Source and Destination

Address Handling)

The first 6-bytes of information after SFD will be inter-

preted as the destination address field. The MACE

device provides facilities for physical, logical and

Am79C940

35

broadcast address reception. In addition, multiple

physical addresses can be constructed (perfect

address filtering) using external logic in conjunction

with the EADI interface.

device will ignore up to seven additional bits at the end

of a message (dribbling bits), which can occur under

normal network operating conditions. The reception of

eight additional bits will cause the MACE device to

de-serialize the entire byte, and will result in the

received message and FCS being modified.

Error Detection (Physical Medium

Transmission Errors)

Received messages which suffer a collision after

64-byte times (after SFD) will be marked to indicate

they have suffered a late collision (CLSN). Additional

counters are provided to report the Receive Collision

Count and Runt Packet Count to be used for network

statistics and utilization calculations.

The MACE device provides several facilities which

report and recover from errors on the medium. In addi-

tion, the network is protected from gross errors due to

inability of the host to keep pace with the MACE

device activity.

On completion of transmission, the MACE device will

report the Transmit Frame Status for the frame. The

exact number of transmission retry attempts is reported

(ONE, MORE used with XMTRC, or RTRY), and

whether the MACE device had to Defer (DEFER) due

to channel activity. In addition, Loss of Carrier is

reported, indicating that there was an interruption in the

ability of the MACE device to monitor its own transmis-

sion. Repeated LCAR errors indicate a potentially

faulty transceiver or network connection. Excessive

Defer (EXDEF) will be reported in the Transmit Retry

Count register if the transmit frame had to wait for an

abnormally long period before transmission.

Note that if the MACE device detects a received packet

which has a 00b pattern in the preamble (after the first

8-bits which are ignored), the entire packet will be

ignored. The MACE device will wait for the network to

go inactive before attempting to receive additional

frames.

Media Access Management

The basic requirement for all stations on the network

is to provide fairness of channel allocation. The 802.3/

Ethernet protocols define a media access mechanism

which permits all stations to access the channel with

equality. Any node can attempt to contend for the chan-

nel by waiting for a predetermined time (Inter Packet

Gap interval) after the last activity, before transmitting

on the media. The channel is a bus or multidrop com-

munications medium (with various topological configu-

rations permitted) which allows a single station to

transmit and all other stations to receive. If two nodes

simultaneously contend for the channel, their signals

will interact causing loss of data, defined as a collision.

It is the responsibility of the MAC to attempt to avoid

and recover from a collision, to guarantee data integrity

for the end-to-end transmission to the receiving station.

Additional transmit error conditions are reported

through the Interrupt Register.

The Late Collision (LCOL) error indicates that the

transmission suffered a collision after the slot time.

This is indicative of a badly configured network. Late

collisions should not occur in normal operating net-

work.

The Collision Error (CERR) indicates that the trans-

ceiver did not respond with an SQE Test message

within the predetermined time after a transmission

completed. This may be due to a failed transceiver,

disconnected or faulty transceiver drop cable, or the

fact the transceiver does not support this feature (or it

is disabled).

Medium Allocation (Collision Avoidance)

The IEEE 802.3 Standard (ISO/IEC 8802-3 1990)

requires that the CSMA/CD MAC monitors the medium

for traffic by watching for carrier activity. When carrier

is detected, the media is considered busy, and the

MAC should defer to the existing message.

In addition to the reporting of network errors, the MACE

device will also attempt to prevent the creation of any

network error caused by inability of the host to service

the MACE device. During transmission, if the host fails

to keep the Transmit FIFO filled sufficiently, causing an

underflow, the MACE device will guarantee the

message is either sent as a runt packet (which will be

deleted by the receiving station) or has an invalid FCS

(which will also allow the receiving station to reject the

message).

The IEEE 802.3 Standard also allows optional two part

deferral after a receive message.

See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.1:

Note: “ It is possible for the PLS carrier sense indica-

tion to fail to be asserted during a collision on the

media. If the deference process simply times the inter-

Frame gap based on this indication it is possible for a

short interFrame gap to be generated, leading to a

potential reception failure of a subsequent frame. To

enhance system robustness the following optional

measures, as specified in 4.2.8, are recommended

when interFrameSpacing Part1 is other than zero:”

The status of each receive message is passed via the

Receive Frame Status bytes. FCS and Framing errors

(FRAM) are reported, although the received frame is

still passed to the host. The FRAM error will only be

reported if an FCS error is detected and there are a non

integral number of bytes in the message. The MACE

36

Am79C940

(1) Upon completing a transmission, start timing the

interpacket gap, as soon as transmitting and carrier

Sense are both false.

See ANS t42I/IEEE Std 802.3-1990 Edition,

7.2.4.6 (1)):

“At the conclusion of the output function, the DTE

opens a time window during which it expects to see

the signal_quality_error signal asserted on the

Control In circuit. The time window begins when the

CARRIER_STATUS becomes CARRIER_OFF. If

execution of the output function does not cause

CARRIER_ON to occur, no SQE test occurs in the

DTE. The duration of the window shall be at least

4.0 µs but no more than 8.0 µs. During the time win-

dow the Carrier Sense Function is inhibited.”

(2) When timing an interFrame gap following

reception, reset the interFrame gap timing if

carrierSense becomes true during the first 2/3 of the

interFrame gap timing interval. During the final 1/3 of

the interval the timer shall not be reset to ensure fair

access to the medium. An initial period shorter than 2/

3 of the interval is permissible including zero.“

The MAC engine implements the optional receive two

part deferral algorithm, with a first part in-

ter-frame-spacing time of 6.0 µs. The second part of

the inter-frame-spacing interval is therefore 3.6 µs.

The MACE device implements a carrier sense blinding

period within 0 µs-4.0 µs from deassertion of carrier

sense after transmission. This effectively means that

when transmit two part deferral is enabled (DXMT2PD

in the MAC Configuration Control register is cleared)

the IFS1 time is from 4 µs to 6 µs after a transmission.

However, since IPG shrinkage below 4 µs will not be

encountered on correctly configured networks, and

since the fragment size will be larger than the 4 µs

blinding window, then the IPG counter will be reset by

a worst case IPG shrinkage/fragment scenario and the

MACE device will defer its transmission. The MACE

chip will not restart the carrier sense blinding period if

carrier is detected within the 4.0-6.0 µs portion of IFS1,

but will restart timing of the entire IFS1 period.

The MACE device will perform the two part deferral

algorithm as specified in Section 4.2.8 (Process Defer-

ence). The Inter Packet Gap (IPG) timer will start timing

the 9.6 µs InterFrameSpacing after the receive carrier

is de-asserted. During the first part deferral

(InterFrameSpacingPart1-IFS1) the MACE device will

defer any pending transmit frame and respond to the

receive message. The IPG counter will be reset to zero

continuously until the carrier deasserts, at which point

the IPG counter will resume the 9.6 µs count once

again. Once the IFS1 period of 6.0µs has elapsed, the

MACE device will begin timing the second part deferral

(InterFrameSpacingPart2-IFS2) of 3.6µs. Once IFS1

has completed, and IFS2 has commenced, the MACE

chip will not defer to a receive packet if a transmit

packet is pending. This means that the MACE device

will not attempt to receive an incoming packet, and it

will start to transmit at 9.6 µs regardless of network

activity, forcing a collision if an existing transmission is

in progress. The MACE device will guarantee to com-

plete the preamble (64-bit) and jam (32-bit) sequence

before ceasing transmission and invoking the random

backoff algorithm.

Contention Resolution (Collision Handling)

Collision detection is performed and reported to the

MAC engine either by the integrated Manchester

Encoder/Decoder (MENDEC), or by use of an external

function (e.g. Serial Interface Adaptor, Am7992B)

utilizing the GPSI.

If a collision is detected before the complete preamble/

SFD sequence has been transmitted, the MACE de-

vice will complete the preamble/SFD before appending

the jam sequence. If a collision is detected after the

preamble/SFD has been completed, but prior to 512

bits being transmitted, the MACE device will abort the

transmission, and append the jam sequence immedi-

ately. The jam sequence is a 32-bit all zeroes pattern.

In addition to the deferral after receive process, the

MACE device also allows transmit two part deferral to

be implemented as an option. The option can be dis-

abled using the DXMT2PD bit in the MAC Configura-

tion Control register. Two part deferral after

transmission is useful for ensuring that severe IPG

shrinkage cannot occur in specific circumstances,

causing a transmit message to follow a receive mes-

sage so closely, as to make them indistinguishable.

The MACE device will attempt to transmit a frame a

total of 16 times (initial attempt plus 15 retries) due to

normal collisions (those within the slot time). Detection

of collision will cause the transmission to be re-sched-

uled, dependent on the backoff time that the MACE de-

vice computes. Each collision which occurs during the

transmission process will cause the value of XMTRC in

the Transmit Retry Count register to be updated. If a

single retry was required, the ONE bit will be set in the

Transmit Frame Status. If more than one retry was re-

quired, the MORE bit will be set, and the exact number

of attempts can be determined (XMTRC+1). If all 16 at-

tempts experienced collisions, the RTRY bit will be set

During the time period immediately after a transmission

has been completed, the external transceiver (in the

case of a standard AUI connected device), should gen-

erate the SQE Test message (a nominal 10 MHz burst

of 5-15 BT duration) on the CI± pair (within 0.6-1.6 µs

after the transmission ceases). During the time period

in which the SQE Test message is expected the MACE

device will not respond to receive carrier sense.

Am79C940

37

(ONE and MORE will be clear), and the transmit mes-

sage will be flushed from the XMTFIFO, either by reset-

ting the XMTFIFO (if no End-of-Frame tag exists) or by

moving the XMTFIFO read pointer to the next free lo-

cation (If an End-of-Frame tag is present). If retries

have been disabled by setting the DRTRY bit, the

MACE device will abandon transmission of the frame

on detection of the first collision. In this case, only the

RTRY bit will be set and the transmit message will be

flushed from the XMTFIFO. The RTRY condition will

cause the de-assertion of TDTREQ, and the assertion

of the INTR pin, providing the XMTINTM bit is cleared.

nel activity is reduced, the nodes resolving the collision

time-out their slot time counters as normal.

If a receive message suffers a collision, it will be either

a runt, in which case it will be deleted in the Receive

FIFO, or it will be marked as a receive late collision,

using the CLSN bit in the Receive Frame Status regis-

ter. All frames which suffer a collision within the slot

time will be deleted in the Receive FIFO without

requesting host intervention, providing that the LLRCV

bit (Receive Frame Control) is not set. Runt packets

which suffer a collision will be aborted regardless of the

state of the RPA bit (User Test Register). If the collision

commences after the slot time, the MACE device

receiver will stop sending collided packet data to the

Receive FIFO and the packet data read by the system

will contain the amount of data received to the point of

collision; the CLSN bit in the Receive Frame Status

register will indicate the receive late collision. Note that

the Receive Message Byte Count will report the total

number of bytes during the receive activity, including

the collision.

If a collision is detected after 512 bit times have been

transmitted, the collision is termed a late collision. The

MACE device will abort the transmission, append the

jam sequence and set the LCOL bit in the Transmit

Frame Status. No retry attempt will be scheduled on

detection of a late collision, and the XMTFIFO will be

flushed. The late collision condition will cause the

de-assertion of TDTREQ, and the assertion of the

INTR pin, providing the XMTINTM bit is cleared.

The IEEE 802.3 Standard requires use of a truncated

binary exponential backoff algorithm which provides a

controlled pseudo random mechanism to enforce the

collision backoff interval, before re-transmission is

attempted.

In all normal receive collision cases, the MACE device

eliminates the transfer of packet data across the host

bus. In a receive late collision condition, the MACE chip

minimizes the amount transferred. These functions

preserve bus bandwidth utilization.

See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.5:

Manchester Encoder/Decoder (MENDEC)

The integrated Manchester Encoder/Decoder provides

the PLS (Physical Signaling) functions required for a

fully compliant IEEE 802.3 station. The MENDEC block

contains the AUI, DAI interfaces, and supports the

10BASE-T interface; all of which transfer data to appro-

priate transceiver devices in Manchester encoded for-

mat. The MENDEC provides the encoding function for

data to be transmitted on the network using the high

accuracy on-board oscillator, driven by either the crys-

tal oscillator or an external CMOS level compatible

clock generator. The MENDEC also provides the

decoding function from data received from the network.

The MENDEC contains a Power On Reset (POR)

circuit, which ensures that all analog portions of the

MACE device are forced into their correct state during

power up, and prevents erroneous data transmission

and/or reception during this time.

“At the end of enforcing a collision (jamming),

the CSMA/CD sublayer delays before attempt-

ing to re-transmit the frame. The delay is an in-

teger multiple of slotTime. The number of slot

times to delay before the nth re-transmission

attempt is chosen as a uniformly distributed

random integer r in the range:

k

0 ≤ r ≤ 2 , where k = min (n,10).“

The MACE device implements a random number

generator, configured to ensure that nodes

experiencing a collision, will not have their retry inter-

vals track identically, causing retry errors.

The MACE device provides an alternative algorithm,

which suspends the counting of the slot time/IPG dur-

ing the time that receive carrier sense is detected. This

aids in networks where large numbers of nodes are

present, and numerous nodes can be in collision. It

effectively accelerates the increase in the backoff time

in busy networks, and allows nodes not involved in the

collision to access the channel whilst the colliding

nodes await a reduction in channel activity. Once chan-

External Crystal Characteristics

When using a crystal to drive the oscillator, the follow-

ing crystal specification should be used to ensure less

than ±0.5 ns jitter at DO±

38

Am79C940

Parameter

Min

Nom

Max

Units

1. Parallel Resonant Frequency

20

MHz

2. Resonant Frequency Error

(CL = 20 pF)

–50

–40

+50

PPM

3. Change in Resonant Frequency

+40

20

With Respect To Temperature (CL = 20

pF)*

4. Crystal Capacitance

pF

5. Motional Crystal Capacitance (C1)

6. Series Resistance

0.022

35

7

ohm

pF

7. Shunt Capacitance

* Requires trimming crystal spec; no trim is 50 ppm total

External Clock Drive Characteristics

also used as a stable bit rate clock by the receive

section of the SIA and controller.

When driving the oscillator from an external clock

source, XTAL2 must be left floating (unconnected). An

external clock having the following characteristics must

be used to ensure less than ±0.5 ns jitter at DO±.

The oscillator requires an external 0.005% crystal, or

an external 0.01% CMOS-level input as a reference.

The accuracy requirements if an external crystal is

used are tighter because allowance for the on-chip

oscillator must be made to deliver a final accuracy of

0.01%.

Clock Frequency:

20 MHz ±0.01%

< 6 ns from 0.5 V

Rise/Fall Time (tR/tF):

to V –0.5

DD

Transmission is enabled by the controller. As long as

the ITENA request remains active, the serial output of

the controller will be Manchester encoded and appear

at DO±. When the internal request is dropped by the

controller, the differential transmit outputs go to one of

two idle states, dependent on TSEL in the Mode

Register (CSR15, bit 9):

XTAL1 HIGH/LOW Time

(tHIGH/tLOW):

40 – 60%

duty cycle

XTAL1 Falling Edge to

Falling Edge Jitter:

< ±0.2 ns at

2.5 V input (V /2)

DD

MENDEC Transmit Path

TSEL LOW:

The idle state of DO± yields “zero”

differential to operate transformer-

The transmit section encodes separate clock and NRZ

data input signals into a standard Manchester encoded

serial bit stream. The transmit outputs (DO±) are

designed to operate into terminated transmission lines.

When operating into a 78 ohm terminated transmission

line, signaling meets the required output levels and

skew for Cheapernet, Ethernet and IEEE-802.3.

coupled loads.

TSEL HIGH:

In this idle state, DO+ is positive with

respect to DO– (logical\HIGH).

Receive Path

The principal functions of the Receiver are to signal the

MACE device that there is information on the receive

pair, and separate the incoming Manchester encoded

data stream into clock and NRZ data.

Transmitter Timing and Operation

A 20 MHz fundamental mode crystal oscillator provides

the basic timing reference for the SIA portion of the

MACE device. It is divided by two, to create the internal

transmit clock reference. Both clocks are fed into the

SIA’s Manchester Encoder to generate the transitions

in the encoded data stream. The internal transmit clock

is used by the SIA to internally synchronize the Internal

Transmit Data (ITXD) from the controller and Internal

Transmit Enable (ITENA). The internal transmit clock is

The Receiver section (see Receiver Block Diagram)

consists of two parallel paths. The receive data path is

a zero threshold, wide bandwidth line receiver. The

carrier path is an offset threshold bandpass detecting

line receiver. Both receivers share common bias net-

works to allow operation over a wide input common

mode range.

Am79C940

39

SRD

Manchester

Decoder

Data

Receiver

DI±

SRDCLK

Noise

Reject

Filter

Carrier

Detect

Circuit

RXCRS

16235D-5

Receiver Block Diagram

Input Signal Conditioning

the controller portion of the MACE device sees the first

SRDCLK transition. This also strobes in the incoming

fifth bit to the SIA as Manchester “1". SRD may make a

transition after the SRDCLK rising edge bit cell 5, but

its state is still undefined. The Manchester “1" at bit 5 is

clocked to SRD output at 1/4 bit time in bit cell 6.

Transient noise pulses at the input data stream

are rejected by the Noise Rejection Filter. Pulse width

rejection is proportional to transmit data rate. DC

inputs more negative than minus 100 mV are

also suppressed.

PLL Tracking

The Carrier Detection circuitry detects the presence of

an incoming data packet by discerning and rejecting

noise from expected Manchester data, and controls the

stop and start of the phase-lock loop during clock

acquisition. Clock acquisition requires a valid

Manchester bit pattern of 1010 to lock onto the

incoming message.

After clock acquisition, the phase-locked clock is com-

pared to the incoming transition at the bit cell center

(BCC) and the resulting phase error is applied to a

correction circuit. This circuit ensures that the

phase-locked clock remains locked on the received

signal. Individual bit cell phase corrections of the Volt-

age Controlled Oscillator (VCO) are limited to 10%

of the phase differencebetween BCCand phase-

locked clock.

When input amplitude and pulse width conditions are

met at DI±, the internal enable signal from the SIA to

controller (RXCRS) is asserted and a clock acquisition

cycle is initiated.

Carrier Tracking and End of Message

The carrier detection circuit monitors the DI± inputs

after RXCRS is asserted for an end of message.

RXCRS de-asserts 1 to 2 bit times after the last positive

transition on the incoming message. This initiates the

end of reception cycle. The time delay from the last ris-

ing edge of the message to RXCRS deassert allows

the last bit to be strobed by SRDCLK and transferred to

the controller section, but prevents any extra bit(s) at

the end of message. When IRENA de-asserts (see

Receive Timing-End of Reception (Last Bit = 0) and

Receive Timing-End of Reception (Last Bit = 1) wave-

form diagrams) an RXCRS hold off timer inhibits

RXCRS assertion for at least 2 bit times.

Clock Acquisition

When there is no activity at DI± (receiver is idle), the

receive oscillator is phase locked to TCK. The first neg-

ative clock transition (bit cell center of first valid

Manchester “0") after RXCRS is asserted interrupts the

receive oscillator. The oscillator is then restarted at the

second Manchester “0" (bit time 4) and is phase locked

to it. As a result, the SIA acquires the clock from the

incoming Manchester bit pattern in 4 bit times with a

“1010" Manchester bit pattern.

SRDCLK and SRD are enabled 1/4 bit time after clock

acquisition in bit cell 5 if the ENPLSIO bit is set in the

PLS configuration control register. SRD is at a HIGH

state when the receiver is idle (no SRDCLK). SRD

however, is undefined when clock is acquired and may

remain HIGH or change to LOW state whenever

SRDCLK is enabled. At 1/4 bit time through bit cell 5,

Data Decoding

The data receiver is a comparator with clocked output

to minimize noise sensitivity to the DI± inputs. Input

error is less than ± 35 mV to minimize sensitivity to

40

Am79C940

input rise and fall time. SRDCLK strobes the data

receiver output at 1/4 bit time to determine the value of

the Manchester bit and clocks the data out on SRD on

the following SRDCLK. The data receiver also gener-

ates the signal used for phase detector comparison to

the internal SIA voltage controlled oscillator (VCO).

and one optional common-mode bypass capacitor, as

shown in the Differential Input Termination diagram

below. The differential input impedance, ZIDF, and the

common-mode input impedance, ZICM, are specified

so that the Ethernet specification for cable termination

impedance is met using standard 1% resistor termina-

tors. If SIP devices are used, 39 ohms is also a suitable

value. The CI± differential inputs are terminated in

exactly the same way as the DI± pair.

Differential Input Terminations

The differential input for the Manchester data (DI±) is

externally terminated by two 40.2 ohm ±1% resistors

AUI Isolation

Transformer

DI+

CURIO

DI

40.2 Ω

0.01µF

16235D-6

Differential Input Termination

Collision Detection

data. With this as the criteria for an error, a definition of

“Jitter Handling” is:

A transceiver detects the collision condition on the net-

work and generates a differential signal at the CI±

inputs. This collision signal passes through an input

stage which detects signal levels and pulse duration.

When the signal is detected by the MENDEC, it sets

the CLSN line HIGH. The condition continues for ap-

proximately 1.5 bit times after the last LOW-to-HIGH

transition on CI±.

The peak deviation approaching or crossing 1/4 bit cell

position from nominal input transition, for which the SIA

section will properly decode data.

Attachment Unit Interface (AUI)

The AUI is the PLS (Physical Signaling) to PMA (Phys-

ical Medium Attachment) interface which effectively

connects the DTE to the MAU. The differential interface

provided by the MACE device is fully compliant to

Section 7 of ISO 8802-3 (ANSI/IEEE 802.3).

Jitter Tolerance Definition

The Receive Timing-Start of Reception Clock Acquisi-

tion waveform diagram shows the internal timing rela-

tionships implemented for decoding Manchester data

in the SIA module. The SIA utilizes a clock capture

circuit to align its internal data strobe with an incoming

bit stream. The clock acquisition circuitry requires four

valid bits with the values 1010. Clock is phase locked

to the negative transition at the bit cell center of the

second “0" in the pattern.

After the MACE device initiates a transmission it will

expect to see data looped-back on the DI± pair (AUI

port selected). This will internally generate a carrier

sense, indicating that the integrity of the data path to

and from the MAU is intact, and that the MAU is oper-

ating correctly. This carrier sense signal must be

asserted during the transmission when using the AUI

port (DO± transmitting). If carrier sense does not

become active in response to the data transmission, or

becomes inactive before the end of transmission, the

loss of carrier (LCAR) error bit will be set in the Trans-

Since data is strobed at 1/4 bit time, Manchester tran-

sitions which shift from their nominal placement

through 1/4 bit time will result in improperly decoded

Am79C940

41

mit Frame Status (bit 7) after the packet has been

transmitted.

which is externally connected via the DAI port, since this

will result in a condition where a collision is generated

during any transmit activity.

Digital Attachment Interface (DAI)

The transmit function of the DAI port is protected by a

jabber mechanism which will be invoked if the TXDAT±

and TXEN circuit is active for an excessive period (20 -

150 ms). This prevents a single node from disrupting

the network due to a stuck-on or faulty transmitter. If

this maximum transmit time is exceeded, the DAI port

transmitter circuitry is disabled, the CLSN pin is

asserted, the Jabber bit (JAB in the Interrupt Register)

is set and the INTR pin will be asserted providing the

JABM bit (Interrupt Mask Register) is cleared. Once the

internal transmit data stream from the MENDEC stops

(TXEN deasserts), an unjab time of 250 ms-750 ms will

elapse before the MACE device deasserts the CLSN

indication and re-enables the transmit circuitry.

The Digital Attachment Interface is a simplified electri-

cal attachment specification which allows MAUs which

do not require the DC isolation between the MAU and

DTE (e.g. devices compatible with the 10BASE-T Stan-

dard and 10BASE-FL Draft document) to be imple-

mented. All data transferred across the DAI port is

Manchester Encoded. Decoding and encoding is

performed by the MENDEC.

The DAI port will accept receive data on the basis that

the RXCRS input is active, and will take the data pre-

sented on the RXDAT input as valid Manchester data.

Transmit data is sent to the external transceiver by the

MACE device asserting TXEN and presenting compli-

mentary data on the TXDAT± pair. During idle, the

MACE device will assert the TXDAT+ line high, and the

TXDAT line low, while TXEN is maintained inactive

(high). The MACE device implements logical collision

detection and will use the simultaneous assertion of

TXEN and RXCRS to internally detect a collision con-

dition, take appropriate internal action (such as abort

the current transmit or receive activity), and provide

external indication using the CLSN pin. Any external

transceiver utilized for the DAI interface must not loop

back the transmit data (presented by the MACE de-

vice) on the TXDAT± pins to the RXDAT pin. Neither

should the transceiver assert the RXCRS pin when

transmitting data to the network. Duplication of these

functions by the external transceiver (unless the MACE

device is in the external loop back test configuration)

will cause false collision indications to be detected.

When jabber is detected, the MACE device will assert

the CLSN pin, de-assert the TXEN pin (regardless of

internal MENDEC activity) and set the TXDAT+ and

TXDAT pins to their inactive state.

10BASE-T Interface

Twisted Pair Transmit Function

Data transmission over the 10BASE-T medium

requires use of the integrated 10BASE-T MAU, and

uses the differential driver circuitry in the TXD± and

TXP± pins. The driver circuitry provides the necessary

electrical driving capability and the pre-distortion con-

trol for transmitting signals over maximum length

Twisted Pair cable, as specified by the 10BASE-T

supplement to the IEEE 802.3 Standard. The transmit

function for data output meets the propagation delays

and jitter specified by the standard. During normal

transmission, and providing that the 10BASE-T MAU is

not in a Link Fail or jabber state, the TXEN pin will

be driven HIGH and can be used indirectly to drive a

status LED.

In order to provide an integrity test of the connectivity

between the MACE device and the external transceiver

similar to the SQE Test Message provided as a part of

the AUI functionality, the MACE device can be pro-

grammed to operate the DAI port in an external loop-

back test. In this case, the external transceiver is

assumed to loopback the TXDAT± data stream to the

RXDAT pin, and assert RXCRS in response to the

TXEN request. When in the external loopback mode of

operation (programmed by LOOP [1-0] = 01), the

MACE device will not internally detect a collision condi-

tion. The external transceiver is assumed to take action

to ensure that this test will not disrupt the network. This

type of test is intended to be operated for a very limited

period (e.g. after power up), since the transceiver is as-

sumed to be located physically close to the MACE

device and with minimal risk of disconnection (e.g. con-

nected via printed circuit board traces).

Twisted Pair Receive Function

The receiver complies with the receiver specifications

of the IEEE 802.3 10BASE-T Standard, including noise

immunity and received signal rejection criteria (Smart

Squelch). Signals meeting this criteria appearing at the

RXD± differential input pair are routed to the internal

MENDEC. The receiver function meets the propaga-

tion delays and jitter requirements specified by the

10BASE-T Standard. The receiver squelch level drops

to half its threshold value after unsquelch to allow

reception of minimum amplitude signals and to mitigate

carrier fade in the event of worst case signal attenua-

tion and crosstalk noise conditions. During receive, the

RXCRS pin is driven HIGH and can be used indirectly

to drive a status LED.

Note that when the DAI port is selected, LCAR errors

will not occur, since the MACE device will internally loop

back the transmit data path to the receiver. This loop

back function must not be duplicated by a transceiver

Note that the 10BASE-T Standard defines the receive input

amplitude at the external Media Dependent Interface

42

Am79C940

(MDI). Filter and transformer loss are not specified. The

10BASE-T MAU receiver squelch levels are defined to ac-

count for a 1dB insertion loss at 10 MHz, which is typical for

the type of receive filters/transformers recommended (see

the Appendix for additional details).

The MACE devices integrated 10BASE-T transceiver

will mimic the performance of an externally connected

device (such as a 10BASE-T MAU connected using an

AUI). When the 10BASE-T transceiver is in link fail, the

receive data path of the transceiver must be disabled.

The MACE device will report a Loss of Carrier error

(LCAR bit in the Transmit Frame Status register) due to

the absence of the normal loopback path, for every

packet transmitted during the link fail condition. In ad-

dition, a Collision Error (CERR bit in the Transmit

Frame Status register) will also be reported (see the

section on Signal Quality Error Test Function for

additional details).

Normal 10BASE-T compatible receive thresholds are

employed when the LRT bit is inactive (PHY Configu-

ration Control register). When the LRT bit is set, the

Low Receive Threshold option is invoked, and the sen-

sitivity of the 10BASE-T MAU receiver is increased.

This allows longer line lengths to be employed, ex-

ceeding the 100m target distance of normal 10BASE-T

(assuming typical 24 AWG cable). The additional cable

distance attributes directly to increased signal attenua-

tion and reduced signal amplitude at the 10BASE-T

MAU receiver. However, from a system perspective,

making the receiver more sensitive means that it is also

more susceptible to extraneous noise, primarily caused

by coupling from co-resident services (crosstalk). For

this reason, it is recommended that when using the

Low Receive Threshold option that the service should

be installed on 4-pair cable only. Multi-pair cables

within the same outer sheath have lower crosstalk at-

tenuation, and may allow noise emitted from adjacent

pairs to couple into the receive pair, and be of sufficient

amplitude to falsely unsquelch the 10BASE-T

MAU receiver.

If the AWAKE bit is set in the PHY Configuration Con-

trol register prior to the assertion of the hardware

SLEEP pin, the 10BASE-T receiver remains operable,

and is able to detect and indicate (using the LNKST

output) the presence of legitimate Link Test pulses or

receive activity. The transmission of Link Test pulses is

suspended to reduce power consumption.

If the RWAKE bit is set in the PHY Configuration Con-

trol register prior to the assertion of the hardware

SLEEP pin, the 10BASE-T receiver and transmitter

functions remain active, the LNKST output is disabled,

and the EADI output pins are enabled. In addition the

AUI port (transmit and receive) remains active. Note

that since the MAC core will be in a sleep mode, no

transmit activity is possible, and the transmission of

Link Test pulses is also suspended to reduce

power consumption.

Link Test Function

The link test function is implemented as specified by

10BASE-T standard. During periods of transmit pair

inactivity, Link Test pulses will be periodically sentover

the twisted pair medium to constantly monitor

medium integrity.

Polarity Detection and Reversal

The Twisted Pair receive function includes the ability to

invert the polarity of the signals appearing at the RXD±

pair if the polarity of the received signal is reversed

(such as in the case of a wiring error). This feature al-

lows data packets received from a reverse wired RXD±

input pair to be corrected in the 10BASE-T MAU prior

to transfer to the MENDEC. The polarity detection func-

tion is activated following reset or Link Fail, and will

reverse the receive polarity based on both the polarity

of any previous Link Test pulses and the polarity of

subsequent packets with a valid End Transmit

Delimiter (ETD).

When the link test function is enabled, the absence of

Link Test pulses and receive data on the RXD± pair will

cause the 10BASE-T MAU to go into a Link Fail state.

In the Link Fail state, data transmission, data reception,

data loopback and the collision detection functions are

disabled, and remain disabled until valid data or >5

consecutive link pulses appear on the RXD± pair. Dur-

ing Link Fail, the LNKST pin is inactive (externally

pulled HIGH), and the Link Fail bit (LNKFL in the PHY

Configuration Control register) will be set. When the

link is identified as functional, the LNKST pin is driven

LOW (capable of directly driving a Link OK LED using

an integrated 12 mA driver) and the LNKFL bit will be

cleared. In order to inter-operate with systems which

do not implement link test, this function can be disabled

by setting the the Disable Link Test bit (DLNKTST in the

PHY Configuration Control register). With link test

disabled, the data driver, receiver and loopback func-

tions as well as collision detection remain enabled

irrespective of the presence or absence of data or link

pulses on the RXD± pair.

When in the Link Fail state, the internal 10BASE-T

receiver will recognize Link Test pulses of either posi-

tive or negative polarity. Exit from the Link Fail state is

made due to the reception of five to six consecutive

Link Test pulses of identical polarity. On entry to the

Link Pass state, the polarity of the last five Link Test

pulses is used to determine the initial receive polarity

configuration and the receiver is reconfigured to subse-

quently recognize only Link Test pulses of the previ-

ously recognized polarity. This link pulse algorithm is

employed only until ETD polarity determination is made

as described later inthis section.

Am79C940

43

Positive Link Test pulses are defined as received signal

with a positive amplitude greater than 520 mV (LRT =

LOW) with a pulse width of 60 ns-200 ns. This positive

excursion may be followed by a negative excursion.

This definition is consistent with the expected received

signal at a correctly wired receiver, when a Link Test

pulse which fits the template of Figure 14-12 in the

10BASE-T Standard is generated at a transmitter and

passed through 100 m of twisted pair cable.

Twisted Pair Interface Status

Three outputs (TXEN, RXCRS and CLSN) indicate

whether the MACE device is transmitting (MENDECto

Twisted Pair), receiving (Twisted Pair to MENDEC), or

in a collision state with both functions active

simultaneously.

The MACE device will power up in the Link Fail state.

The normal algorithm will apply to allow it to enter the

Link Pass state. On power up, the TXEN, RXCRS and

CLSN) pins will be in a high impedance state until they

are enabled by setting the Enable PLS I/O bit

(ENPLSIO in the PLS Configuration Control register)

and the 10BASE-T port enters the Link Pass state.

Negative Link Test pulses are defined as received sig-

nals with a negative amplitude greater than 520 mV

(LRT = LOW) with a pulse width of 60 ns-200 ns. This

negative excursion may be followed by a positive ex-

cursion. This definition is consistent with the expected

received signal at a reverse wired receiver, when a

Link Test pulse which fits the template of Figure 14-12

in the 10BASE–T Standard is generated at a transmit-

ter and passed through 100 m of twisted pair cable.

In the Link Pass state, transmit or receive activity which

passes the pulse width/amplitude requirements of the

DO± or RXD± inputs, will be indicated by the TXEN or

RXCRS pin respectively going active. TXEN, RXCRS

and CLSN are all asserted during a collision.

The polarity detection/correction algorithm will remain

armed until two consecutive packets with valid ETD of

identical polarity are detected. When armed, the

receiver is capable of changing the initial or previous

polarity configuration based on the most recent ETD

polarity.

In the Link Fail state, TXEN, RXCRS and CLSN

are inactive.

In jabber detect mode, the MACE device will activate

the CLSN pin, disable TXEN (regardless of Manches-

ter data output from the MENDEC), and allow the

RXCRS pin to indicate the current state of the RXD±

pair. If there is no receive activity on RXD±, only CLSN

will be active during jabber detect. If there is RXD± ac-

tivity, both CLSN and RXCRS will be active.

On receipt of the first packet with valid ETD following

reset or Link Fail, the MACE device will utilize the

inferred polarity information to configure its RXD±

input, regardless of its previous state. On receipt of a

second packet with a valid ETD with correct polarity,

the detection/correction algorithm will lock-in the

received polarity. If the second (or subsequent) packet

is not detected as confirming the previous polarity

decision, the most recently detected ETD polarity will

be used as the default. Note that packets with invalid

ETD have no effect on updating the previous polarity

decision. Once two consecutive packets with valid ETD

have been received, the MACE device will disable the

detection/correction algorithm until either a Link Fail

condition occurs or a hardware or software reset

occurs.

If the SLEEP pin is asserted (regardless of the pro-

gramming of the AWAKE or RWAKE bits in the PHY

Configuration Control register), the TXEN, RXCRS and

CLSN outputs will be placed in a high impedance state.

Collision Detect Function

Simultaneous activity (presence of valid data signals)

from both the internal MENDEC transmit function (indi-

cated externally by TXEN active) and the twisted pair

RXD± pins constitutes a collision, thereby causing an

external indication on the CLSN pin, and an internal

indication which is returned to the MAC core. The

TXEN, RXCRS and CLSN pins are driven high during

collision.

During polarity reversal, the RXPOL pin should be

externally pulled HIGH and the Reversed Polarity bit

(REVPOL in the PHY Configuration Control register)

will be set. During normal polarity conditions, the

RXPOL pin is driven LOW (capable of directly driving a

Polarity OK LED using an integrated 12 mA driver) and

the REVPOL bit will be cleared.

Signal Quality Error (SQE) Test (Heartbeat)

Function

The SQE Test message (a 10 MHz burst normally

returned on the AUI CI± pair at the end of every trans-

mission) is intended to be a self-test indication to the

DTE that the MAU collision circuitry is functional and

the AUI cable/connection is intact. This has minimal

relevance when the 10BASE-T MAU is embedded in

the LAN controller. A Collision Error (CERR bit in the In-

terrupt Register) will be reported only when the

10BASE-T port is in the link fail state, since the collision

circuit of the MAU will be disabled, causing the

absence of the SQE Test message. In GPSI mode the

If desired, the polarity correction function can be dis-

abled by setting the Disable Auto Polarity Correction bit

(DAPC bit in the PHY Configuration Control register).

However, the polarity detection portion of the algorithm

continues to operate independently, and the RXPOL

pin and the REVPOL bits will reflect the polarity state of

the receiver.

44

Am79C940

external encoder/decoder is responsible for asserting

the CLSN pin after each transmission. In DAI mode,

SEQ Test has no relevance.

Addressable Memory (CAM) or other address

detection device.

To allow simple serial to parallel conversion, SF/BD is

provided as a strobe and/or marker to indicate the

delineation of bytes, subsequent to the SFD. This fea-

ture provides a mechanism to allow not only capture

and/or decoding of the physical or logical (group)

address, but also facilitates the capture of header

information to determine protocol and or inter-network-

ing information. The EAM/R pin is driven by the exter-

nal address comparison logic, to either reject or accept

the packet. Two alternative modes are permitted, al-

lowing the external logic to either accept the packet

based on address match, or reject the packet if there is

no match. The two alternate methods are programmed

using the Match/Reject (M/_R) bit in the Receive Frame

Control register.

Jabber Function

The Jabber function inhibits the twisted pair transmit

function of the MACE device if the TXD±/TXP± circuits

are active for an excessive period (20-150 ms). This

prevents any one node from disrupting the network due

to a stuck-on or faulty transmitter. If this maximum

transmit time is exceeded, the data path through the

10BASE-T transmitter circuitry is disabled (although

Link Test pulses will continue to be sent), the CLSN pin

is asserted, the Jabber bit (JAB in the Interrupt Regis-

ter) is set and the INTR pin will be asserted providing

the JABM bit (Interrupt Mask Register) is cl eared.

Once the internal transmit data stream from the MEN-

DEC stops (TXEN deasserts), an unjab time of

250-750 ms will elapse before the MACE device

deasserts the CLSN indication and re-enables the

transmit circuitry.

If the M/R bit is set, the pin is configured as EAM

(External Address Match). The MACE device can be

configured with Physical, Logical or Broadcast Address

comparison operational. If an internal address match is

detected, the packet will be accepted regardless of the

condition of EAM. Additional addresses can be located

in the external address detection logic. If a match is

detected, EAM must go active within 600 ns of the last

bit in the destination address field (end of byte 6) being

presented on the SRD output, to guarantee frame

reception. In addition, EAM must go inactive after a

match has been detected on a previous packet, before

the next match can take place on any subsequent

packet. EAM must be asserted for a minimum pulse

width of 200 ns.

When jabber is detected, the MACE device will assert

the CLSN pin, de-assert the TXEN pin (regardless of

internal MENDEC activity), and allow the RXCRS pin to

indicate the current state of the RXD± pair. If there is no

receive activity on RXD±, only CLSN will be active dur-

ing jabber detect. If there is RXD± activity, both CLSN

and RXCRS will be active.

External Address Detection Interface

(EADI)

This interface is provided to allow external perfect ad-

dress filtering. This feature is typically utilized for termi-

nal server, bridge and/or router type products. The use

of external logic is required, to capture the serial bit

stream from the MACE device, and compare this with

a table of stored addresses or identifiers. See the EADI

port diagram in the Systems Applications section,

Network Interfaces sub-section, for details.

If the M/R bit is clear (default state after either the

RESET pin or SWRST bit have been activated), the pin

is configured as EAR (External Address Reject). The

MACE device can be configured with Physical, Logical

or Broadcast Address comparison operational. If an

internal address match is detected, the packet will be

accepted regardless of the condition of EAR. Incoming

packets which do not pass the internal address com-

parison will continue to be received by the MACE

device. EAR must be externally presented to the

MACE chip prior to the first assertion of RDTREQ, to

guarantee rejection of unwanted packets. This allows

approximately 58 byte times after the last destination

address bit is available to generate the EAR signal, as-

suming the MACE device is not configured to accept

runt packets. EAR will be ignored by the MACE device

from 64 byte times after the SFD, and the packet will be

accepted if EAR has not been asserted before this

time. If the MACE device is configured to accept runt

packets, the EAR signal must be generated prior to the

receive message completion, which could be as short

as 12 byte times (assuming six bytes for source

address, two bytes for length, no data, four bytes for

FCS) after the last bit of the destination address is

The EADI interface operates directly from the NRZ

decoded data and clock recovered by the Manchester

decoder. This allows the external address detection to

be performed in parallel with frame reception and

address comparison in the MAC Station Address

Detection (SAD) block.

SRDCLK is provided to allow clocking of the receive bit

stream from the MACE device, into the external

address detection logic. Once a received packet com-

mences and data and clock are available from the

decoder, the EADI interface logic will monitor the alter-

nating (1,0) preamble pattern until the two ones of the

Start Frame Delimiter (1,0,1,0,1,0,1,1) are detected, at

which point the SF/BD output will be driven high.

After SF/BD is asserted the serial data from SRD

should be de-serialized and sent to a Content

Am79C940

45

available. EAR must have a pulse width of at least

200 ns.

regardless of the programming of M/R or the state of

the EAM/R input. The following table summarizes the

operation of the EADI features.

Note that setting the PROM bit (MAC Configuration

Control) will cause all receive packets to be received,

Internal/External Address Recognition Capabilities

EAM/R Required Timing Received Messages

X No timing requirements All Received Frames

PROM

M/R

1

0

X

0

1

H

↓

No timing requirements

All Received Frames

Low for 200 ns within 512-bits after SFD

No timing requirements

Physical/Logical/Broadcast Matches

All Received Frames

H

↓

Low for 200 ns within 8-bits after DA field

ers DI±, CI±), and the crystal input (XTAL1/XTAL2)

pins, are not tested.

General Purpose Serial Interface (GPSI)

The GPSI port provides the signals necessary to

present an interface consistent with the non encoded

data functions observed to/from a LAN controller such

as the Am7990 Local Area Network Controller for

Ethernet (LANCE). The actual GPSI pins are function-

ally identical to some of the pins from the DAI and the

EADI ports, the GPSI replicates this type of interface.

The following is a brief summary of the IEEE 1149.1

compatible test functions implemented in the MACE

device. For additional details, consult the IEEE Stan-

dard Test Access Port and Boundary-Scan Architec-

ture document (IEEE Std 1149.1–1990).

The boundary scan test circuit requires four pins (TCK,

TMS, TDI and TDO ), defined as the Test Access Port

(TAP). It includes a finite state machine (FSM), an

instruction register, a data register array and a power

on reset circuit. Internal pull-up resistors are provided

for the TCK, TDI and TMS pins.

The GPSI allows use of an external Manchester

encoder/decoder, such as the Am7992B Serial Inter-

face Adapter (SIA). In addition, it allows the MACE

device to be used as a MAC sublayer engine in a

repeater based on the Am79C980 Integrated Multiport

Repeater (IMR). Simple connection to the IMR Expan-

sion Bus allows the MAC to view all packet data pass-

ing through a number of interconnected IMRs, allowing

statistics and network management information to

be collected.

The TAP engine is a 16 state FSM, driven by the Test

Clock (TCK) and the Test Mode Select (TMS) pins. An

independent power on reset circuit is provided to

ensure the FSM is in the TEST_LOGIC_RESET state

at power up.

The GPSI functional pins are duplicated as follows:

In addition to the minimum IEEE 1149.1 instruction

requirements (EXTEST, SAMPLE and BYPASS), three

additional instructions (IDCODE, TRI_ST and SET_I/

O) are provided to further ease board level testing. All

unused instruction codes are reserved.

Pin Configuration for GPSI Function

LANCE

MACE

Function

Type

Receive Data

Receive Clock

Receive Carrier Sense

Collision

I

RX

RXDAT

SRDCLK

RXCRS

CLSN

RCLK

RENA

CLSN

TX

I

IEEE 1149.1 Supported Instruction Summary

I

Inst

Selected

Reg

Inst

Transmit Data

Transmit Clock

Transmit Enable

O

I

TXDAT+

STDCLK

TXEN

ame

Description

Data Reg Mode Code

TCK

EXTEST External Test

BSR Test 0000

ID Reg Normal 0001

BSR Normal 0010

Bypass Normal 0011

O

TENA

IDCode ID Code Inspection

Sample Sample Boundary

TRI_ST Force Tristate

IEEE 1149.1 Test Access Port Interface

An IEEE 1149.1 compatible boundary scan Test

Access Port is provided for board level continuity test

and diagnostics. All digital input, output and input/out-

put and input/output pins are tested. Analog pins,

including the AUI differential driver (DO±) and receiv-

Control

SET_I/0

Bypass

Test

0100

BoundaryTo I/0

Bypass Bypass Scan

Bypass Normal 1111

46

Am79C940

After hardware or software reset, the IDCODE instruc-

tion is always invoked. The decoding logic provides

signals to control the data flow in the DATA registers

according to the current instruction.

TC can be dynamically changed on a cycle by cycle

basis to program the slave cycle execution for two (TC

= HIGH) or three (TC = LOW) SCLK cycles. TC must

be stable by the falling edge of SCLK (EDSEL = High)

in S0 at the start of a cycle, and should only be

changed in S0 in a multiple cycle burst.

Each Boundary Scan Register (BSR) cell also has two

stages. A flip-flop and a latch are used in the SERIAL

SHIFT STAGE and the PARALLEL OUTPUT STAGE

respectively.

A read cycle is initiated when either CS or FDS is sam-

pled low on the falling edge of SCLK at S0. FDS and

CS must be asserted exclusively. If they are active

simultaneously when sampled, the MACE device will

not execute any read or write cycle.

There are four possible operational modes in the BSR

cell:

1. CAPTURE

If CS is low, a Register Address read will take place.

The state of the ADD4–0 will be used to commence

decoding of the appropriate internal register/FIFO.

2. SHIFT

3. UPDATE

4. SYSTEM FUNCTION

Other Data Registers

If FDS is low, a FIFO Direct read will take place from

the RCVFIFO. The state of the ADD4-0 bus is irrele-

vant for the FIFO Direct mode.

ꢀ BYPASS REG (1 bit)

With either the CS or FDS input active, the state of the

ADD0-4 (for Register Address reads), R/W (high to

indicate a read cycle), BE0 and BE1 will also be latched

on the falling (EDSEL = HIGH) edge of SCLK at S0.

ꢀ Device Identification Register (32 bits)

Bits 31-28:Version (4 bits)

Bits 27-12:Part number (16 bits) is 9400H

Bits 11-1:Manufacturer ID (11 bits).

The manufacturer ID code for AMD is

00000000001 in accordance with

JEDEC Publication 106-A.

From the falling edge of SCLK in S1 (EDSEL = HIGH),

the MACE device will drive data on DBUS15-0 and

activate the DTV output (providing the read cycle com-

pleted successfully). If the cycle read the last byte/word

of data for a specific frame from the RCVFIFO, the

MACE device will also assert the EOF signal. DBUS15-

0, DTV and EOF will be guaranteed valid and can be

sampled on the falling (EDSEL = HIGH) edge of SCLK

at S2.

Bit 0:Always a logic 1

SLAVE ACCESS OPERATION

Internal register accesses are based on a 2 or 3 SCLK

cycle duration, dependent on the state of the TC input

pin. TC must be externally pulled low to force the

MACE device to perform a 3-cycle access. TC is inter-

nally pulled high if left unconnected, to configure the

2-cycle access by default.

If the Register Address mode is being used to access

the RCVFIFO, once EOF is asserted during the last

byte/word read for the frame, the Receive Frame Sta-

tus can be read in one of two ways. The Register Ad-

dress mode can be continued, by placing the

appropriate address (00110b) on the address bus and

executing four read cycles (CS active) on the Receive

Frame Status location. In this case, additional Register

Address read requests from the RCVFIFO will be ig-

nored, and no DTV returned, until all four bytes of the

Receive Frame Status register have been read. Alter-

natively, a FIFO Direct read can be performed, which

will effectively route the Receive Frame Status through

the RCVFIFO location. This mechanism is explained in

more detail below.

All register accesses are byte wide with the exception

of the data path to and from the internal FIFOs.

Data exchanges to/from register locations will take

place over the appropriate half of the data bus to suit

the host memory organization (as programmed by the

BSWP bit in the BIU Configuration Control register).

The BE0, BE1 and EOF signals are provided to allow

control of the data flow to and from the FIFOs. Byte

read operations from the Receive FIFO cause data to

be duplicated on both the upper and lower bytes of the

data bus. Byte write operations to the Transmit FIFO

must use the BE0 and BE1 inputs to define the active

data byte to the MACE device.

If the FIFO Direct mode is used, the Receive Frame

Status can be read directly from the RCVFIFO by con-

tinuing to execute read cycles (by asserting FDS low

and R/W high) after EOF is asserted indicating the last

byte/word read for the frame. Each of the four bytes of

Receive Frame Status will appear on both halves of the

data bus, as if the actual Receive Frame Status regis-

ter were being accessed. Alternatively, the status can

be read as normal using the Register Address mode by

Read Access

Details of the read access timing are located in the AC

Waveforms section, Host System Interface, figures:

Two-Cycle Receive FIFO/Register Read Timing and

Three-Cycle Receive FIFO/Register Read Timing.

Am79C940

47

placing the appropriate address (00110b) on the

address bus and executing four read cycles (CS

active).

ꢀ Write the BIU Configuration Control (BIUCC) regis-

ter to change the Byte Swap mode to big endian or

to change the Transmit Start Point.

ꢀ Write the FIFO Configuration Control (FIFOCC)

register to change the FIFO watermarks or to

enable the FIFO Burst Mode.

Either the FIFO Direct or Register Address modes can

be interleaved at any time to read the Receive Frame

Status, although this is considered unlikely due to the

additional overhead it requires. In either case, no addi-

tional data will be read from the RCVFIFO until the

Receive Frame Status has been read, as four bytes

appended to the end of the packet when using the

FIFO Direct mode, or as four bytes from the Receive

Frame Status location when using the Register

Address mode.

ꢀ Write the Interrupt Mask Register (IMR) to disable

unwanted interrupt sources.

ꢀ Write the PLS Configuration Control (PLSCC)

register to enable the active network port. If the

GPSI interface is used, the register must be written

twice. The first write access should only set

PORTSEL [1–0] = 11. The second access must

write again PORTSEL[1–0] = 11 and additionally set

ENPLSIO = 1. This sequence is required to avoid

contention on the clock, data and/or carrier indica-

tion signals.

EOF will only be driven by the MACE device when

reading received packet data from the RCVFIFO. At all

other times, including reading the Receive Frame Sta-

tus using the FIFO Direct mode, the MACE device will

place EOF in a high impedance state.

ꢀ Write the PHY Configuration Control (PHYCC) reg-

ister to configure any non-default mode if the

10BASE-T interface is used.

RDTREQ should be sampled on the falling edge of

SCLK. The assertion of RDTREQ is programmed by

RCVFW, and the de-assertion is modified dependent

on the state of the RCVBRST bit (both in the FIFO Con-

figuration Control register). See the section Receive

FIFO Read for additional details.

ꢀ Program the Logical Address Filter (LADRF) regis-

ter or the Physical Address Register (PADR). The

Internal Address Configuration (IAC) register must

be accessed first. Set the Address Change

(ADDRCHG) bit to request access to the internal

address RAM. Poll the bit until it is cleared by the

MACE device indicating that access to the internal

address RAM is permitted. In the case of an

address RAM access after hardware or software

reset (ENRCV has not been set), the MACE device

will return ADDRCHG = 0 right away. Set the

LOGADDR bit in the IAC register to select writing to

the Logical Address Filter register. Set the PHY-

ADDR bit in the IAC register to select writing to the

Physical Address Register. Either bit can be set to-

gether with writing the ADDRCHG bit. Initializing the

Logical Address Filter register requires 8 write

cycles. Initializing the Physical Address Register

requires 6 write cycles.

Write Access

Details of the write access timing are located in the AC

Waveforms section, Host System Interface, figures:

Two-Cycle Transmit FIFO/Register Write Timing and

Three-Cycle Transmit FIFO/Register Write Timing.

Write cycles are executed in a similar manner as the

read cycle previously described, but with the R/W input

low, and the host responsible to provide the data with

sufficient set up to the falling edge of SCLK after S2.

After a FIFO write, TDTREQ should be sampled on or

after the falling (EDSEL = HIGH) edge of SCLK after

S3 of the FIFO write. The state of TDTREQ at this time

will reflect the state of the XMTFIFO.

After going active (low), TDTREQ will remain low for

two or more XMTFIFO writes.

ꢀ Write the User Test Register (UTR) to set the MACE

device into any of the user diagnostic modes such

as loopback.

The minimum high (inactive) time of TDTREQ is one

SCLK cycle. When EOF is written to the Transmit

FIFO, TDTREQ will go inactive after one SCLK cycle,

for a minimum of one SCLK cycle.

ꢀ Write the MAC Configuration Control (MACCC) reg-

ister as the last step in the initialization sequence to

enable the receiver and transmitter. Note that the

system must guarantee a delay of 1 ms after

power-up before enabling the receiver and transmit-

ter to allow the MACE phase lock loop to stabilize.

Initialization

After power-up, RESET should be asserted for a mini-

mum of 15 SCLK cycles to set the MACE device into a

defined state. This will set all MACE registers to their

default values. The receive and transmit functions will

be turned off. A typical sequence to initialize the MACE

device could look like this:

ꢀ The Transmit Frame Control (XMTFC) and the

Receive Frame Control (RCVFC) registers can be

programmed on a per packet basis.

48

Am79C940

programmed, to provide flexibility in the

(re-)transmission of messages.

Reinitialization

The SWRST bit in the BIU Configuration Control

(BIUCC) register can be set to reset the MACE device

into a defined state for reinitialization. The same

sequence described in the initialization section can be

used. The 1 ms delay for the MACE phase lock loop

stabilization need not to be observed as it only applies

to a power-up situation.

The disable retry on collision (DRTRY bit) and auto-

matic pad field insertion (APAD XMT bit) features

should not be changed while data remains in the Trans-

mit FIFO. Writing to either the DRTRY or APAD XMT

bits in this case may have unpredictable results. These

bits are not internally latched or protected. When writ-

ing to the Transmit Frame Control register the DRTRY

and APAD XMT bits should be programmed consis-

tently. Once the Transmit FIFO is empty, DRTRY and

APAD XMT can be reprogrammed.

TRANSMIT OPERATION

The transmit operation and features of the MACE

device are controlled by programmable options. These

options are programmed through the BIU, FIFO and

MAC Configuration Control registers.

This can be achieved with no risk of transmit data loss

or corruption by clearing ENXMT after the packet data

for the current frame has been completely loaded. The

transmission will complete normally and the activation

of the INTR pin can be used to determine if the transmit

frame has completed (XMTINT will be set in the Inter-

rupt Register). Once the Transmit Frame Status has

been read, APAD XMT and/or DRTRY can be changed

and ENXMT set to restart the transmit process with the

new parameters.

Parameters controlled by the MAC Configuration Con-

trol register are generally programmed only once,

during initialization, and are therefore static during the

normal operation of the MACE device (see the Media

Access Control section for a detailed description). The

features controlled by the FIFO Configuration Control

register and the Transmit Frame Control register can

be re-programmed if the MACE device is not transmit-

ting.

APAD XMT is sampled if there are less than 60 bytes

in the transmit packet when the last bit of the last byte

is transmitted. If APAD XMT is set, a pad field of pattern

00h is added until the minimum frame size of 64 bytes

(excluding preamble and SFD) is achieved. If APAD

XMT is clear, no pad field insertion will take place and

runt packet transmission is possible. When APAD XMT

is enabled, the DXMTFCS feature is over-ridden and

the four byte FCS will be added to the transmitted

packet unconditionally.

Transmit FIFO Write

The Transmit FIFO is accessed by performing a host

generated write sequence on the MACE device. See

the Slave Access Operation-Write Access section and

the AC Waveforms section, Host System Interface, fig-

ures: Two-Cycle Transmit FIFO/Register Write Timing

and Three-Cycle Transmit FIFO/Register Write Timing

for details of the write access timing.

There are two fundamentally different access methods

to write data into the FIFO. Using the Register Address

mode, the FIFO can be addressed using the ADD0-4

lines, (address 00001b), initiating the cycle with the CS

and R/W (low) signals. The FIFO Direct mode allows

write access to the Transmit FIFO without use of the

address lines, and using only the FDS and R/W lines.

If the MACE device detects both signals active, it will

not execute a write cycle. The write cycle timing for the

Register Address or Direct FIFO modes are identical.

FDS and CS should be mutually exclusive.

The disable FCS generation/transmission feature can

be programmed dynamically on a packet by packet

basis. The current state of the DXMTFCS bit is

internally latched on the last write to the Transmit FIFO,

when the EOF indication is asserted by the

host/controller.

The programming of static transmit attributes are dis-

tributed between the BIU, FIFO and MAC Configura-

tion Control registers.

The point at which transmission begins in relation to

the number of bytes of a frame in the FIFO is controlled

by the XMTSP bits in the BIU Configuration Control

register. Depending on the bus latency of the system,

XMTSP can be set to ensure that the Transmit FIFO

does not underflow before more data is written to the

FIFO. When the entire frame is in the FIFO, or the FIFO

becomes full before the threshold is reached, transmis-

sion of preamble will commence regardless of the

value in XMTSP. The default value of XMTSP is 64

bytes after reset.

The data stream to the Transmit FIFO is written using

multiple byte and/or word writes. CS or FDS does not

have to be returned inactive to commence execution of

the next write cycle. If CS/FDS is detected low at the

falling edge of S0, a write cycle will commence. Note

that EOF must be asserted by the host/controller

during the last byte/word transfer.

Transmit Function Programming

The Transmit Frame Control register allows program-

ming of dynamic transmit attributes. Automatic transmit

features such as retry on collision, FCS generation/

transmission and pad field insertion can all be

The point at which TDTREQ is asserted in relation to

the number of empty bytes present in the Transmit

Am79C940

49

FIFO is controlled by the XMTFW bits in the FIFO Con-

figuration Control register. TDTREQ will be asserted

when one of the following conditions is true:

transmission will be terminated immediately, generat-

ing a runt packet which can be deleted at the receiving

station. If greater than 544 bits have been transmitted,

the messages will have the current CRC inverted and

appended at the next byte boundary, to guarantee an

error is detected at the receiving station. This feature

ensures that packets will not be generated with poten-

tial undetected data corruption. An explanation of the

544 bit derivation appears in the “Automatic Pad

Generation” section.

ꢀ The number of bytes free in the Transmit FIFO rel-

ative to the current Saved Read Pointer value is

greater than or equal to the threshold set by the

XMTFW (16, 32 or 64 bytes). The Saved Read

Pointer is the first byte of the current transmit frame,

either in progress or awaiting channel availability.

ꢀ The number of bytes free in the Transmit FIFO rel-

ative to the current Read Pointer value is greater

than or equal to the threshold set by the XMTFW

(16, 32 or 64 bytes). The Read Pointer becomes

available only after a minimum of 64 byte frame

length has been transmitted on the network (eight

bytes of preamble plus 56 bytes of data), and points

to the current byte of the frame being transmitted.

Automatic Pad Generation

Transmit frames can be automatically padded to ex-

tend them to 64 data bytes (excluding preamble) per-

mitting the minimum frame size of 64 bytes (512 bits)

for 802.3/Ethernet to be guaranteed, with no software

intervention from the host system.

APAD XMT = 1 enables the automatic padding feature.

The pad is placed between the LLC Data field and FCS

field in the 802.3 frame. The FCS is always added if

APAD XMT = 1, regardless of the state of DXMTFCS.

The transmit frame will be padded by bytes with the

value of 00h. The default value of APAD XMT will

enable auto pad generation after hardware or software

reset.

Depending on the bus latency of the system, XMTFW

can be set to ensure that the Transmit FIFO does not

underflow before more data is written into the FIFO.

When the entire frame is in the FIFO, TDTREQ will

remain asserted if sufficient bytes remain empty. The

default value of XMTFW is 64 bytes after hardware or

software reset. Note that if the XMTFW is set below the

64 byte limit, the transmit latency for the host to service

the MACE device is effectively increased, since

TDTREQ will occur earlier in the transmit sequence

and more bytes will be present in the Transmit FIFO

when the TDTREQ is de-asserted.

It is the responsibility of upper layer software to cor-

rectly define the actual length field contained in the

message to correspond to the total number of LLC

Data bytes encapsulated in the packet (length field as

defined in the IEEE 802.3 standard). The length value

contained in the message is not used by the MACE

device to compute the actual number of pad bytes to be

inserted. The MACE chip will append pad bytes depen-

dent on the actual number of bits transmitted onto the

network. Once the last data byte of the frame has com-

pleted, prior to appending the FCS, the MACE device

will check to ensure that 544 bits have been transmit-

ted. If not, pad bytes are added to extend the frame

size to this value, and the FCS is then added.

The transmit operation of the MACE device can be

halted at any time by clearing the ENXMT bit (bit 1) in

the MAC Configuration Control register. Note that any

complete transmit frame that is in the Transmit FIFO

and is currently in progress will complete, prior to the

transmit function halting. Transmit frames in the FIFO

which have not commenced will not be started. Trans-

mit frames which have commenced but which have not

been fully transferred into the Transmit FIFO will be

aborted, in one of two ways. If less than 544 bits

(68 bytes) have been transmitted onto the network, the

Preamble

1010....1010

SFD

10101011

Dest

Addr

Srce

Addr

Length

LLC

Data

Pad

FCS

56

Bits

8

Bits

6

2

4

46—1500

Bytes

IEEE 802.3 Format Data Frame

16235D-7

The 544 bit count is derived from the following:

50

Am79C940

Minimum frame size (excluding preamble,

At the point that FCS is to be appended, the transmitted

frame should contain:

including FCS)

Preamble/SFD size

FCS size

64 bytes

8 bytes

4 bytes

512 bits

64 bits

32bits

Preamble

64

+

(Min Frame Size – FCS) bits

(512 32) bits

–

A minimum length transmit frame from the MACE

device will therefore be 576 bits, after the FCS is

appended.

To be classed as a minimum size frame at the receiver,

the transmitted frame must contain:

Preamble

+

(Min Frame Size + FCS) bits

The Ethernet specification makes no use of the LLC

pad field, and assumes that minimum length messages

will be at least 64 bytes in length.

Preamble

1010....1010

SYNCH

11

Dest

Addr

Srce

Addr

Type

Data

FCS

4

46—1500

62

2

6

2

Bytes

Bits

Bytes

16235D-8

Ethernet Format Data Frame

XMT FIFO is full), the network medium is free, and the

IPG time has elapsed.

Transmit FCS Generation

Automatic generation and transmission of FCS for a

transmit frame depends on the value of DXMTFCS

(Disable Transmit FCS) when the EOF is asserted indi-

cating the last byte/word of data for the transmit frame

is being written to the FIFO. The action of writing the

last data byte/word of the transmit frame, latches the

current contents of the Transmit Frame Control regis-

ter, and therefore determines the programming of

DXMTFCS for the transmit frame. When DXMTFCS =

0 the transmitter will generate and append the FCS to

the transmitted frame. If the automatic padding feature

is invoked (APAD XMT in Transmit Frame Control), the

FCS will be appended regardless of the state of DXMT-

FCS. Note that the calculated FCS is transmitted most

significant bit first. The default value of DXMTFCS is 0

after hardware or software reset.

Indication of valid Transmit Frame Status can be

obtained by servicing the hardware interrupt and test-

ing the XMTINT bit in the Interrupt Register, or by poll-

ing the XMTSV bit in the Poll register if a continuous

polling mechanism is required. If the Transmit Retry

Count data is required (for loading, diagnostic, or man-

agement information), XMTRC must be read prior to

XMTFS. Reading the XMTFS register when the

XMTSV bit is set will clear both the XMTRC and

XMTFS values.

Transmit Exception Conditions

Exception conditions for frame transmission fall into

two distinct categories; those which are the result of

normal network operation and those which occur due

to abnormal network and/or host related events.

Transmit Status Information

Normal events which may occur and which are handled

autonomously by the MACE device are:

Although multiple transmit frames can be queued in the

Transmit FIFO, the MACE device will not permit loss of

Transmit Frame Status information. The Transmit

Frame Status and Transmit Retry Count can only be

buffered internally for a maximum of two frames. The

MACE device will therefore not commence a third

transmit frame, until the status from the first frame is

read. Once the Transmit Retry Count and Transmit

Frame Status for the first transmit packet is read, the

MACE device will autonomously begin the next trans-

mit frame, provided that a transmit frame is pending,

the XMTSP threshold has been exceeded (or the

(a) Collisions within the slot time with automatic retry

(b) Deletion of packets due to excessive transmis-

sion attempts.

(a) The MACE device will ensure that collisions which

occur within 512 bit times from the start of transmission

(including preamble) will be automatically retried with

no host intervention. The Transmit FIFO ensures this

by guaranteeing that data contained within the Trans-

Am79C940

51

mit FIFO will not be overwritten until at least 64 bytes

(512 bits) of data have been successfully transmitted

onto the network. This criteria will be met, regardless of

whether the transmit frame was the first (or only) frame

in the Transmit FIFO, or if the transmit frame was

queued pending completion of the preceding frame.

These should not occur on a correctly configured 802.3

network, but will be reported if the network has been

incorrectly configured or a fault condition exists.

(a) A loss of carrier condition will be reported if the

MACE device cannot observe receive activity while it is

transmitting. After the MACE device initiates a trans-

mission it will expect to see data looped-back on the

receive input path. This will internally generate a carrier

sense, indicating that the integrity of the data path to

and from the external MAU is intact, and that the MAU

is operating correctly.

(b) If 16 total attempts (initial attempt plus 15 retries)

have been made to transmit the frame, the MACE

device will abandon the transmit process for the partic-

ular frame, de-assert the TDTREQ pin, report a Retry

Error (RTRY) in the Transmit Frame Status, and set the

XMTINT bit in the Interrupt Register, causing activation

of the external INTR pin providing the interrupt is

unmasked.

When the AUI port is selected, if carrier sense does not

become active in response to the data transmission, or

becomes inactive before the end of transmission, the

loss of carrier (LCAR) error bit will be set in the Trans-

mit Frame Status (bit 7) after the packet has been

transmitted. The packet will not be re-tried on the basis

of an LCAR error.

Once the XMTINT condition has been externally recog-

nized, the Transmit Frame Counter (XMTFC) can be

read to determine whether the tail end of the frame that

suffers the RTRY error is still in the host memory (i.e.,

when XMTFC = 0). This XMTFC read should be

requested before the Transmit Frame Status read

since reading the XMTFS would cause the XMTFC to

decrement. If the tail end of the frame is indeed still in

the host memory, the host is responsible for ensuring

that the tail end of the frame does not get written into

the FIFO and does not get transmitted as a whole

frame. It is recommended that the host clear the tail

end of the frame from the host memory before request-

ing the XMTFS read so that after the XMTFS read,

when MACE device re-asserts TDTREQ, the tail end of

the frame does not get written into the FIFO. The

Transmit Frame Status read will indicate that the RTRY

error occurred. The read operation on the Transmit

Frame Status will update the FIFO read and write

pointers. If no End-of-Frame write (EOF pin assertion)

had occurred during the FIFO write sequence, the en-

tire transmit path will be reset (which will update the

Transmit FIFO watermark with the current XMTFW

value in the FIFO Configuration Control register). If a

whole frame does reside in the FIFO, the read pointer

will be moved to the start of the next frame or free loca-

tion in the FIFO, and the write pointer will be unaf-

fected. TDTREQ will not be re-asserted until the

Transmit Frame Status has been read.

When the 10BASE–T port is selected, LCAR will be

reported for every packet transmitted during the Link

fail condition.

When the GPSI port is selected, LCAR will be reported

if the RXCRS input pin fails to become active during a

transmission, or once active, goes inactive before the

end of transmission.

When the DAI port is selected, LCAR errors will not

occur, since the MACE device will internally loop back

the transmit data path to the receiver. The loop back

feature must not be performed by the external trans-

ceiver when the DAI port is used.

During internal loopback, LCAR will not be set, since

the MACE device has direct control of the transmit and

receive path integrity. When in external loopback,

LCAR will operate normally according to the specific

port which has been selected.

(b) A late collision will be reported if a collision condition

exists or commences 64 byte times (512 bit times) after

the transmit process was initiated (first bit of preamble

commenced). The MACE device will abandon the

transmit process for the particular frame, complete

transmission of the jam sequence (32-bit all zeroes

pattern), de-assert the TDTREQ pin, report the Late

Collision (LCOL) and Transmit Status Valid (XMTSV) in

the Transmit Frame Status, and set the XMTINT bit in

the Interrupt Register, causing activation of the external

INTR pin providing the interrupt is unmasked.

After a RTRY error, all further packet transmission will

be suspended until the Transmit Frame Status is read,

regardless of whether additional packet data exists in

the FIFO to be transmitted. Receive FIFO read opera-

tions are not impaired.

Packets experiencing 16 unsuccessful attempt to

transmit will not be re-tried. Recovery from this condi-

tion must be performed by upper layer software.

Once the XMTINT condition has been externally recog-

nized, the Transmit Frame Counter (XMTFC) can be

read to determine whether the tail end of the frame that

suffers the LCOL error is still in the host memory (i.e.,

when XMTFC = 0). This XMTFC read should be

requested before the Transmit Frame Status read

since reading the XMTFS would cause the XMTFC to

decrement. If the tail end of the frame is indeed still in

Abnormal network conditions include:

(a)

(b)

(c)

Loss of carrier.

Late collision.

SQE Test Error.

52

Am79C940

the host memory, the host is responsible for ensuring

that the tail end of the frame does not get written into

the FIFO and does not get transmitted as a whole

frame. It is recommended that the host clear the tail

end of the frame from the host memory before request-

ing the XMTFS read so that after the XMTFS

read,when the MACE device re-asserts TDTREQ, the

tail end of the frame does not get written into the FIFO.

The Transmit Frame Status read will indicate that the

LCOL error occurred. The read operation on the Trans-

mit Frame Status will update the FIFO read and write

pointers. If no End-of-Frame write (EOF pin assertion)

had occurred during the FIFO write sequence, the en-

tire transmit path will be reset (which will update the

Transmit FIFO watermark with the current XMTFW

value in the FIFO Configuration Control register). If a

whole frame resides in the FIFO, the read pointer will

be moved to the start of the next frame or free location

in the FIFO, and the write pointer will be unaffected.

TDTREQ will not be re-asserted until the Transmit

Frame Status has been read.

(a) The host may continue to write to the Transmit FIFO

after the TDTREQ has been de-asserted, and can

safely do so on the basis of knowledge of the number

of free bytes remaining (set by XMTFW in the FIFO

Configuration Control register). If however the host

system continues to write data to the point that no ad-

ditional FIFO space exists, the MACE device will not

return the DTV signal and hence will effectively not

acknowledge acceptance of the data. It is the host’s

responsibility to ensure that the data is re-presented at

a future time when space exists in the Transmit FIFO,

and to track the actual data written into the FIFO.

(b) If the host fails to respond to the TDTREQ from the

MACE device before the Transmit FIFO is emptied, a

FIFO underrun will occur. The MACE device will in this

case terminate the network transmission in an orderly

sequence. If less than 512 bits have been transmitted

onto the network the transmission will be terminated

immediately, generating a runt packet. If greater than

512 bits have been transmitted, the message will have

the current CRC inverted and appended at the next

byte boundary, to guarantee an FCS error is detected

at the receiving station. The MACE device will report

this condition to the host by de-asserting the TDTREQ

pin, setting the UFLO and XMTSV bits (in the Transmit

Frame Status) and the XMTINT bit (in the Interrupt

Register), and asserting the INTR pin providing the cor-

responding XMTINTM bit (in the Interrupt Mask

Regis ter) is cleared.

After an LCOL error, all further packet transmission will

be suspended until the Transmit Frame Status is read,

regardless of whether additional packet data exists in

the FIFO to be transmitted. Receive FIFO operations

are unaffected.

Packets experiencing a late collision will not be re-tried.

Recovery from this condition must be performed by

upper layer software.

(c) During the inter packet gap time following the com-

pletion of a transmitted message, the AUI CI± pair is

asserted by some transceivers as a self-test. When the

AUI port has been selected, the integral Manchester

Encoder/Decoder will expect the SQE Test Message

(nominal 10 MHz sequence) to be returned via the CI±

pair, within a 40 network bit time period after DI± goes

inactive. If the CI± input is not asserted within the 40

network bit time period following the completion of

transmission, then the MACE device will set the CERR

bit (bit 5) in the Interrupt Register. The INTR pin will be

activated if the corresponding mask bit CERRM = 0.

Once the XMTINT condition has been externally recog-

nized, the Transmit Frame Counter (XMTFC) can be

read to determine whether the tail end of the frame that

suffers the UFLO error is still in the host memory (i.e.,

when XMTFC = 0). In the case of FIFO underrun, this

will definitely be the case and the host is responsible for

ensuring that the tail end of the frame does not get writ-

ten into the FIFO and does not get transmitted as a

whole frame. It is recommended that the host clear the

tail end of the frame from the host memory before

requesting the XMTFS read so that after the XMTFS

read, when the MACE device re-asserts TDTREQ, the

tail end of the frame does not get written into the FIFO.

The Transmit Frame Status read will indicate that the

UFLO error occurred. The read operation on the Trans-

mit Frame Status will update the FIFO read and write

pointers and the entire transmit path will be reset

(which will update the Transmit FIFO watermark with

the current XMTFW value in the FIFO Configuration

Control register). TDTREQ will not be re-asserted until

the Transmit Frame Status has been read.

When the GPSI port is selected, the MACE device will

expect the CLSN input pin to be asserted 40 bit times

after the transmission has completed (after TXEN out-

put pin has gone inactive). When the DAI port has

been selected, the CERR bit will not be reported. A

transceiver connected via the DAI port is not expected

to support the SQE Test Message feature.

Host related transmit exception conditions include:

(a) Overflow caused by excessive writes to the

Transmit FIFO (DTV will not be issued if the Trans-

mit FIFO is full).

(c) The MACE device will internally store the Transmit

Frame Status for up to two packets. If the host fails to

read the Transmit Frame Status and both internal

entries become occupied, the MACE device will not

commence any subsequent transmit frames to prevent

overwriting of the internally stored values. This will

(b) Underflow caused by lack of host writes to the

Transmit FIFO.

(c) Not reading current Transmit Frame Status.

Am79C940

53

occur regardless of the number of bytes written to the

Transmit FIFO.

The point at which RDTREQ is asserted in relation to

the number of bytes of a frame that are present in the

Receive FIFO (RCVFIFO) is controlled by the RCVFW

bits in the FIFO Configuration Control register, or the

LLRCV bit in the Receive Frame Control register.

RDTREQ will be asserted when one of the following

conditions is true:

RECEIVE OPERATION

The receive operation and features of the MACE de-

vice are controlled by programmable options. These

options are programmed through the BIU, FIFO and

MAC Configuration Control registers.

(i) There are at least 64 bytes in the RCVFIFO.

Parameters controlled by the MAC Configuration Con-

trol register are generally programmed only once, dur-

ing initialization, and are therefore static during the

normal operation of the MACE device (see the Media

Access Control section for a detailed description). The

features controlled by the FIFO Configuration Control

register and the Receive Frame Control register can be

programmed without performing a reset on the part.

The host is responsible for ensuring that no data is

present in the Receive FIFO when re-programming the

receive attributes.

(ii) The received packet has passed the 64 byte mini-

mum criteria, and the number of bytes in the

RCVFIFO is greater than or equal to the threshold

set by the RCVFW (16 or 32 bytes).

(iii) A receive packet has completed, and part or all of

it is present in the RCVFIFO.

(iv) The LLRCV bit has been set and greater than

12-bytes of at least 8 bytes have been received.

Note that if the RCVFW is set below the 64-byte limit,

the MACE device will still require 64-bytes of data to be

received before the initial assertion of RDTREQ. Sub-

sequently, RDTREQ will be asserted at any time the

RCVFW threshold is exceeded. The only times that the

RDTREQ will be asserted when there are not at least

an initial 64-bytes of data in the RCVFIFO are:

Receive FIFO Read

The Receive FIFO is accessed by performing a host

generated read sequence on the MACE device. See

the Slave Access Operation-Read Access section and

the AC Waveforms section, Host System Interface, fig-

ures: “2 Cycle Receive FIFO/Register Read Timing”

and “3 Cycle Receive FIFO/Register Read Timing” for

details of the read access timing.

(i) When the ASTRP RCV bit has been set in the Re-

ceive Frame Control register, and the pad is auto-

matically stripped from a minimum length packet.

Note that EOF will be asserted by the MACE device

during the last data byte/word transfer.

(ii) When the RPA bit has been set in the User Test

Register, and a runt packet of at least 8 bytes has

been received.

Receive Function Programming

The Receive Frame Control register allows program-

ming of the automatic pad field stripping feature and

the configuration of the Match/Reject (M/R) pin.

ASTRP RCV and M/R must be static when the receive

function is enabled (ENRCV = 1). The receiver should

be disabled before (re-) programming these options.

(iii) When the LLRCV bit has been set in the Receive

Frame Control register, and at least 12-bytes (after

SFD) has been received.

No preamble/SFD bytes are loaded into the Receive

FIFO. All references to bytes past through the receive

FIFO are received after the preamble/SFD sequence.

The EADI port can be used to permit reception of

frames to commence whilst external address decoding

takes place. The M/R bit defines the function of the

EAM/R pin, and hence whether frames will be

accepted or rejected by the external address

comparison logic.

Depending on the bus latency of the system, RCVFW

can be set to ensure that the RCVFIFO does not over-

flow before more data is read. When the entire frame is

in the RCVFIFO, RDTREQ will be asserted regardless

of the value in RCVFW. The default value of RCVFW is

64-bytes after hardware or software reset.

The programming of additional receive attributes are

distributed between the FIFO and MAC Configuration

Control registers, and the User Test Register.

The receive operation of the MACE device can be

halted at any time by clearing the ENRCV bit in the

MAC Configuration Control register. Note that any

receive frame currently in progress will be accepted

normally, and the MACE device will disable the receive

process once the message has completed. The Missed

Packet Count (MPC) will be incremented for

All receive frames can be accepted by setting the

PROM bit (bit 7) in the MAC Configuration Control reg-

ister. When PROM is set, the MACE device will attempt

to receive all messages, subject to minimum frame

enforcement. Setting PROM will override the use of the

EADI port to force the rejection of unwanted messages.

See the sections External Address Detection Interface

for more details.

54

Am79C940

46–1500

Bytes

56

8

6

2

4

Bits

Bytes

Preamble

SYNCH

Dest.

SRCE.

ADDR.

Length

LLC

Pad

FCS

1010....1010

10101011

ADDR.

DATA

1–1500

45–0

Bytes

Start of Packet

at Time= 0

Bit

0

Bit Bit

Bit

7

0

Most

Significant

Byte

Least

Significant

Byte

Increasing Time

16235D-9

802.3 Packet and Length Field Transmission Order

subsequent packets that would have normally been

passed to the host, and are now ignored due to the

disabled state of the receiver.

field stripped. Receive frames which have a length field

of 46 bytes or greater will be passed to the host

unmodified.

Note that clearing the ENRCV bit disables the asser-

tion of RDTREQ. If ENRCV is cleared during receive

activity and remains cleared for a long time and if the

tail end of the receive frame currently in progress is

Since any valid Ethernet Type field value will always be

greater than a normal 802.3 Length field, the MACE

device will not attempt to strip valid Ethernet frames.

Note that for some network protocols, the value passed

in the Ethernet Type and/or 802.3 Length field is not

compliant with either standard and may cause

problems.

longer than the amount of space available in the

Receive FIFO, Receive FIFO overflow will occur. How-

ever, even with RDTREQ deasserted, if there is valid

data in the Receive FIFO to be read, successful slave

reads to the Receive FIFO can be executed (indicated

by valid DTV). It is the host’s responsibility to avoid the

overflow situation.

The diagram below shows the byte/bit ordering of the

received length field for an 802.3 compatible frame

format.

Receive FCS Checking

Automatic Pad Stripping

Reception and checking of the received FCS is per-

formed automatically by the MACE device. Note that if

the Automatic Pad Stripping feature is enabled,

the received FCS will be verified against the value

computed for the incoming bit stream including pad

characters, but it will not be passed through the Re-

ceive FIFO to the host. If an FCS error is detected, this

will be reported by the FCS bit (bit 4) in the Receive

Frame Status.

During reception of a frame, the pad field can be

stripped automatically. ASTRP RCV = 1 enables the

automatic pad stripping feature. The pad field will be

stripped before the frame is passed to the FIFO, thus

preserving FIFO space for additional frames. The FCS

field will also be stripped, since it is computed at the

transmitting station based on the data and pad field

characters, and will be invalid for a receive frame that

has the pad characters stripped.

Receive Status Information

The number of bytes to be stripped is calculated from

the embedded length field (as defined in the IEEE

802.3 definition) contained in the packet. The length

indicates the actual number of LLC data bytes con-

tained in the message. Any received frame which con-

tains a length field less than 46 bytes will have the pad

The EOF indication signals that the last byte/word of

data has been passed from the FIFO for the specific

frame. This will be accompanied by a RCVINT indica-

tion in the the Interrupt Register signaling that the

Receive Frame Status has been updated, and must be

Am79C940

55

read. The Receive Frame Status is a single location

which must be read four times to allow the four bytes of

status information associated with each frame to be

read. Further data read operations from the Receive

FIFO using the Register Address mode, will be ignored

by the MACE device (indicated by the MACE chip not

returning DTV) until all four bytes of the Receive Frame

Status have been read. Alternatively, the FIFO Direct

access mode may be used to read the Receive Frame

Status through the Receive FIFO. In either case, the

4-byte total must be read before additional receive data

can be read from the Receive FIFO. However, the

RDTREQ indication will continue to reflect the state of

the Receive FIFO as normal, regardless of whether the

Receive Frame Status has been read. DTV will not be

returned when a read operation is performed on the

Receive Frame Status location and no valid status is

present or ready.

(b)

(c)

Overflow caused by lack of host reads from the

Receive FIFO

Missed packets due to lack of host reads from

the Receive FIFO and/or the Receive Frame

Status

(a) Successive read operations from the Receive FIFO

after the final byte of data/status has been read, will

cause the DTV pin to remain de-asserted during the

read operation, indicating that no valid data is present.

There will be no adverse effect on the Receive FIFO.

(b) Data present in the Receive FIFO from packets

which completed before the overflow condition

occurred, can be read out by accessing the Receive

FIFO normally. Once this data (and the associated

Receive Frame Status) has been read, the EOF indica-

tion will be asserted by the MACE device during the

first read operation takes place from the Receive FIFO,

for the packet which suffered the overflow. If there were

no other packets in the FIFO when the overflow

occurred, the EOF will be asserted on the first read

from the FIFO. In either case, the EOF indication will be

accompanied by assertion of the INTR pin, providing

that the RCVINTM bit in the Interrupt Mask Register is

not set. If the Register Address mode is being used, the

host is required to access the Receive Frame Status

location using four separate read cycles. Further

access to the Receive FIFO will be ignored by the

MACE device until all four bytes of the Receive Frame

Status have been read. DTV will not be returned if a

Receive FIFO read is attempted. If the FIFO Direct

mode is being used, the host can read the Receive

Frame Status through the Receive FIFO, but the host

must be aware that the subsequent four cycles will

yield the receive status bytes, and not data from the

same or a new packet. Only the OFLO bit will be valid

in the Receive Frame Status, other error/status and the

RCVCNT fields are invalid.

Note that the Receive Frame Status can be read using

either the Register Address or FIFO Direct modes. For

additional details, see the section Receive FIFO Read.

Receive Exception Conditions

Exception conditions for frame reception fall into two

distinct categories; those which are the result of normal

network operation, and those which occur due to

abnormal network and/or host related events.

Normal events which may occur and which are handled

autonomously by the MACE device are basically colli-

sions within the slot time and automatic runt packet

deletion. The MACE device will ensure that any receive

packet which experiences a collision within 512 bit

times from the start of reception (excluding preamble)

will be automatically deleted from the Receive FIFO

with no host intervention (the state of the RPA bit in the

User Test Register; or the RCVFW bits in the FIFO

Configuration Control register have no effect on this).

This criteria will be met, regardless of whether the

receive frame was the first (or only) frame in the

Receive FIFO, or if the receive frame was queued

behind a previously received message.

While the Receive FIFO is in the overflow condition, it

is deaf to additional receive data on the network. How-

ever, the MACE device internal address detect logic

continues to operate and counts the number of packets

that would have been passed to the host under normal

(non overflow) conditions. The Missed Packet Count

(MPC) is an 8-bit count (in register 24) that maintains

the number of packets which pass the address match

criteria, and complete without collision. The MPC

counter will wrap around when the maximum count of

255 is reached, setting the MPCO (Missed Packet

Count Overflow) bit in the Interrupt Register, and

asserting the INTR pin providing that MPCOM (Missed

Packet Count Overflow Mask) in the Interrupt Mask

Register is clear. MPCO will be cleared (the interrupt

will be unmasked) after hardware or software reset.

However, until the first time that the receiver is enabled,

MPC will not increment, hence no interrupt will occur

due to missed packets after a reset.

Abnormal network conditions include:

ꢀ FCS errors

ꢀ Framing errors

ꢀ Dribbling bits

ꢀ Late collision

These should not occur on a correctly configured 802.3

network, but may be reported if the network has been

incorrectly configured or a fault condition exists.

Host related receive exception conditions include:

(a)

Underflow caused by excessive reads from the

Receive FIFO (DTV will not be issued if the

Receive FIFO is empty)

56

Am79C940

(c) Failure to read packet data from the Receive FIFO

will eventually cause an overflow condition. The FIFO

will maintain any previously completed packet(s), which

can be read by the host at its convenience. However,

packet data on the network will no longer be received,

regardless of destination address, until the overflow is

cleared by reading the remaining Receive FIFO data

and Receive Status. The MACE device will increment

the Missed Packet Count (MPC) register to indicate that

a packet which would have been normally passed to the

host, was dropped due to the error condition.

Receive FIFO (RCVFIFO)

(REG ADDR 0)

RCVFIFO [15–0]

This register provides a 16-bit data path from the

Receive FIFO. Reading this register will read one word/

byte from the Receive FIFO. The RCVFIFO should

only be read when Receive Data Transfer Request

(RDTREQ) is asserted. If the RCVFIFO location is read

before 64-bytes are available in the RCVFIFO (or

12-bytes in the case that LLRCV is set in the Receive

Frame Control register), DTV will not be returned.

Once the 64-byte threshold has been achieved and

RDTREQ is asserted, the de-assertion of RDTREQ

does not prevent additional data from being read from

the RCVFIFO, but indicates the number of additional

bytes which are present, before the RCVFIFO is emp-

tied, and subsequent reads will not return DTV (see

the FIFO Sub-System section for additional details).

Write operations to this register will be ignored and

DTV will not be returned.

Note: The moment a packet overflow is detected or

read, an EOF with INT is generated. On status read

(OFLOW), the FIFO pointers are reset to the first

location. This essentially flushes the FIFO.

LOOPBACK OPERATION

During loopback, the FCS logic can be allocated to the

receiver by setting RCVFCSE = 1 in User Test Regis-

ter. This permits both the transmit and receive FCS op-

erations to be verified during the loopback process.

The state of RCVFCSE is only valid during loopback

opera tion.

Byte transfers from the RCVFIFO are supported, and

will be fully aligned to the target memory architecture,

defined by the BSWP bit in the BIU Configuration Con-

trol register. The Byte Enable inputs (BE1-0) will define

which half of the data bus should be used for the trans-

fer. The external host/controller will be informed that

the last byte/word of data in a receive frame is being

read from the RCVFIFO, when the MACE device as-

serts the EOF signal.

If RCVFCSE = 0, the MACE device will calculate and

append the FCS to the transmitted message. The

receive message passed to the host will therefore con-

tain an additional four bytes of FCS. The Receive

Frame Status will indicate the result of the loopback

operation and the RCVCNT.

If RCVFCSE = 1, the last four bytes of the transmit

message must contain the FCS computed for the

transmit data preceding it. The MACE device will trans-

mit the data without addition of an FCS field, and the

FCS will be calculated and verified at the receiver.

Transmit FIFO (XMTFIFO)

(REG ADDR 1)

XMTFIFO [15–0]

This register provides a 16-bit data path to the Transmit

FIFO. Byte/word data written to this register will be

placed in the Transmit FIFO. The XMTFIFO can be

written at any time the Transmit Data Transfer Request

(TDTREQ) is asserted. The de-assertion of TDTREQ

does not prevent data being written to the XMTFIFO,

but indicates the number of additional write cycles

which can take place, before the XMTFIFO is filled, and

subsequent writes will not return DTV (see the FIFO

Sub-System section for additional details). Read oper-

ations to this register will be ignored and DTV will not

be returned.

The loopback facilities of the MACE device allow full

operation to be verified without disturbance to the net-

work. Loopback operation is also affected by the state

of the Loopback Control bits (LOOP [0–1]) in the User

Test Register. This affects whether the internal MEN-

DEC is considered part of the internal or external

loop-back path.

When in the loopback mode(s), the multicast address

detection feature of the MACE device, programmed by

the contents of the Logical Address Filter (LADR [63–

0]) can only be tested when RCVFCSE = 1, allocating

the CRC generator to the receiver. All other features

operate identically in loopback as in normal operation,

such as automatic transmit padding and receivepad

stripping.

Byte transfers to the XMTFIFO are supported, and

accept data from the source memory architecture to

ensure the correct byte ordering for transmission,

defined by the BSWP bit in the MAC Configuration

Control register. The Byte Enable inputs (BE1-0) will

define which half of the data bus should be used for the

transfer. The use of byte transfers have implications on

the latency time provided by the XMTFIFO (see the

FIFO Sub-System section for additional details). The

external host/controller must indicate the last byte/word

USER ACCESSIBLE REGISTERS

The following registers are provided for operation of the

MACE device. All registers are 8-bits wide unless

otherwise stated. Note that all reserved register bits

should be written as zero.

Am79C940

57

of data in a transmit frame is being written to the

XMTFIFO, by asserting the EOF signal.

asserted during a Transmit FIFO

write.

Bit

Bit 2-1 RES

Bit 0

Name

Description

Transmit Frame Control (XMTFC) (REG ADDR 2)

The Transmit Frame Control register is latched inter-

nally on the last write to the Transmit FIFO for each in-

dividual packet, when EOF is asserted. This permits

automatic transmit padding and FCS generation on a

packet-by-packet basis.

Reserved. Read as zeroes.

Always write as zeroes.

APAD XMT Auto Pad Transmit. APAD XMT

enables the automatic padding

feature. Transmit frames will be

padded to extend them to 64

bytes including FCS. The FCS is

calculated for the entire frame

including pad, and appended af-

ter the pad field. APAD XMT will

override the programming of the

DXMTFCS bit. APAD XMT is set

by activation of the RESET pin

or SWRST bit. APAD XMT is

sampled only when EOF is as-

serted during a Transmit FIFO

write.

DRTRY

RES

DXMTFCS

RES

APAD XMT

Bit

Name

Description

Bit 7

DRTRY

Disable Retry. When DRTRY is

set, the MACE device will pro-

vide a single transmission at-

tempt for the packet, all further

retries will be suspended. In the

case of a collision during the at-

tempt, a Retry Error (RTRY) will

be reported in the Transmit Sta-

tus. With DRTRY cleared, the

MACE device will attempt up to

15 retries (16 attempts total) be-

fore indicating a Retry Error.

DRTRY is cleared by activation

of the RESET pin or SWRST bit.

DRTRY is sampled during the

Transmit Frame Status (XMTFS)

(REG ADDR 3)

The Transmit Frame Status is valid when the XMTSV

bit is set. The register is read only, and is cleared when

XMTSV is set and a read operation is performed. The

XMTINT bit in the Interrupt Register will be set when

any bit is set in this register.

transmit process when

a

Note that if XMTSV is not set, the values in this register

can change at any time, including during a read opera-

tion. This register should be read after the Transmit

Retry Count (XMTRC). See the description of the

Transmit Retry Count (XMTRC) for additional details.

collision occurs. DRTRY should

not be changed whilst data

remains in the Transmit FIFO

since this may cause an unpre-

dictable retry response to a colli-

sion. Once the Transmit FIFO is

empty, DRTRY can be repro-

grammed.

XMTSV UFLO LCOL MORE ONE

DEFER

LCAR

RTRY

Bit 6-4 RES

Reserved. Read as zeroes.

Always write as zeroes.

Bit

Name

Description

Bit 3

DXMTFCS Disable Transmit FCS. When

DXMTFCS = 0 the transmitter

will generate and append an

FCS to the transmitted frame.

When DXMTFCS = 1, no FCS

will be appended to the transmit-

ted frame, providing that APAD

XMT is also clear. If APAD XMT

is set, the calculated FCS will be

appended to the transmitted

message regardless of the state

of DXMTFCS. The value of

DXMTFCS for each frame is

programmed when EOF is as-

serted to transfer the last byte/

word for the transmit packet to

the FIFO. DXMTFCS is cleared

by activation of the RESET pin

or SWRST bit. DXMTFCS is

sampled only when EOF is

Bit 7

Bit 6

XMTSV

Transmit Status Valid. Transmit

Status Valid indicates that this

status is valid for the last frame

transmitted. The value of

XMTSV will not change during a

read operation.

UFLO

LCOL

Underflow. Indicates that the

Transmit FIFO emptied before

the end of frame was reached.

The transmitted frame is truncat-

ed at that point. If UFLO is set,

TDTREQ will be de-asserted,

and will not be re-asserted until

the XMTFS has been read.

Bit 5

Late Collision. Indicates that a

collision occurred after the slot

time of the channel elapsed. If

LCOL is set, TDTREQ will be

de-asserted, and will not be

58

Am79C940

re-asserted until the XMTFS has

been read. The MACE device

does not retry after a late

collision.

Bit

Name

Description

Bit 3-0 EXDEF

Excessive Defer. The EXDEF bit

will be set if a transmit frame

waited for an excessive period

for transmission. An excessive

defer time is defined in accor-

dance with the following (from

page 34, section 5.2.4.1 of IEEE

Std 802.3h-1990 Layer Manage-

Bit 4

Bit 3

Bit 2

MORE

ONE

More. Indicates that more than

one retry was needed to transmit

the frame. ONE, MORE and

RTRY are mutually exclusive.

One. Indicates that exactly one

retry was needed to transmit the

frame. ONE, MORE and RTRY

are mutually exclusive.

ment):maxDeferTime

= {2 x

(max frame size x 8)} bits where

maxFrameSize = 1518 bytes

(from page 68, section 4.4.2.1 of

ANSI/IEEE Std 802.3-1990).

So, the maxDeferTime = 24288

DEFER

Defer. Indicates that MACE

device had to defer transmission

of the frame. This condition

results if the channel is busy

when the MACE device is ready

to transmit.

14

12

11

10

9

bits = 2 + 2 + 2 + 2 + 2

7

6

5

+2 +2 +2

Bit 1

LCAR

Loss of Carrier. Indicates that

the carrier became false during

Bit 6-4 RES

Reserved. Read as zeroes.

Always write as zeroes.

a

transmission. The MACE

Bit 3-0

[3-0]

XMTRCTransmit Retry Count.

Contains

device does not retry upon Loss

of Carrier. LCAR will not be set

when the DAI port is selected,

when the 10BASE-T port is se-

lected and in the link pass state,

or during any internal loopback

mode. When the 10BASE-T port

is selected and in the link fail

state, LCAR will will be reported

for any transmission attempt.

the count of the number of retry

attempts made by the MACE

device to transmit the current

transmit packet. The value of the

counter will be zero if the first

transmission attempt was suc-

cessful, and a maximum of 15 if

all retry attempts were utilized.

RTRY will be set in Transmit

Frame Status if all 16 attempts

were unsuccessful.

Bit 0

RTRY

Retry Error. Indicates that all

attempts to transmit the frame

were unsuccessful, and that fur-

ther attempts have been abort-

ed. If Disable Retry (DRTRY in

the Transmit Frame Control reg-

ister) is cleared, RTRY will be

set when a total of 16 unsuc-

cessful attempts were made to

transmit the frame. If DRTRY is

set, RTRY indicates that the first

and only attempt to transmit the

frame was unsuccessful. ONE,

MORE and RTRY are mutually

exclusive. If RTRY is set,

TDTREQ will be de-asserted,

and will not be re-asserted until

the XMTFS has been read.

Receive Frame Control (RCVFC) (REG ADDR 5)

RES RES RES RES

LLRCV M/R RES

ASTRPRCV

Bit

Bit 7-4 RES

Bit 3 LLRCV

Name

Description

Reserved. Read as zeroes.

Always write as zeroes.

Low Latency Receive.

A

programmable option to allow

access to the Receive FIFO

before the 64-byte threshold has

been reached. When set, data

can be read from the RCVFIFO

once a low threshold (12-bytes

after SFD plus synchronization)

has been exceeded, causing

RDTREQ to be asserted.

RDTREQ will remain asserted

as long as one read cycle can be

performed on the RCVFIFO

(identical to the burst mode).

Transmit Retry Count (XMTRC)

(REG ADDR 4)

The Transmit Retry Count should be read only in

response to a hardware interrupt request (INTR

asserted) when XMTINT is set in the Interrupt Register,

or after XMTSV is set in the Poll Register.The register

should be read before the Transmit Frame Status

register. Reading the Transmit Frame Status with

XMTSV set will cause the XMTRC value to be reset.

This register is read only.

Indication of a valid read cycle

from the RCVFIFO will return

DTV asserted. Reading the

RCVFIFO before data is avail-

able, or while waiting for addi-

EXDEF

RES

XMTRC[3-0]

Am79C940

59

tional data once a packet is in

progress will not cause the

RCVFIFO to underflow, and will

be indicated by DTV being

invalid. The MACE device will no

longer be able to reject runts in

this mode, this responsibility is

transferred to the host system.

In the case of a collided packet

(normal slot time collision or late

collision), the MACE device will

abort the reception, and return

the RCVFS. Note that all colli-

sions in this mode will appear as

late collisions and be reported

by the CLSN bit in the Receive

Status (RCVSTS) byte.

receive frame. Receive Frame Status can be read

using either the Register Direct or FIFO Direct access

modes.

In Register Direct mode, access to the Receive FIFO

will be denied until all four status bytes for the com-

pleted frame have been read from the Receive Frame

Status location. In FIFO Direct mode, the Receive

Frame Status is read through the Receive FIFO loca-

tion, by continuing to execute four read cycles after the

completion of packet data (and assertion of EOF). The

Receive Frame Status can be read using either mode,

or a combination of both modes, however each status

byte will be presented only once regardless of access

method. Other register reads and/or writes can be

interleaved at any time, during the Receive Frame

Sta tus sequence.

If the host does not keep up with

the incoming receive data, nor-

mal RCVFIFO overflow recovery

is provided.

The Receive Frame Status consists of the following

four bytes of information:

RFS0 Receive Message Byte Count

Bit 2

M/R

Match/Reject. The Match/Reject

option sets the criteria for the

External Address Detection

Interface. If set, the EAM/R pin is

configured as External Address

Match, and is used to signal the

acceptance of a receive frame to

the MACE device. If cleared, the

pin functions as External

Address Reject and is used to

flush unwanted packets from the

Receive FIFO prior to the first

assertion of RDTREQ. M/R is

cleared by activation of the

RESET pin or SWRST bit. When

the EADI feature is disabled, the

EAM/R pin must be tied active

(low) and all normal receive ad-

dress recognition configurations

are supported (physical, logical

and promiscuous). See the sec-

tion “External Address Detection

Interface” for additional details.

(RCVCNT) [11–0]

RFS1 Receive Status, (RCVSTS) [15–12]

RFS2 Runt Packet Count (RNTPC) [7–0]

RFS3 Receive Collision Count (RCVCC) [7–0]

RFS0—Receive Message Byte Count (RCVCNT)

RCVCNT [7:0]

Bit

Name

Description

Bit 7-0 RCVCNT

[7:0]

The Receive Message Byte

Count indicates the number of

whole bytes in the received mes-

sage. If pad bytes were stripped

from the received frame,

RCVCNT indicates the number

of bytes received less the num-

ber of pad bytes and less the

number of FCS bytes. RCVCNT

is 12 bits long. If a late collision

is detected (CLSN set in

RCVSTS), the count is an indi-

cation of the length (in byte

times) of the duration of the re-

ceive activity including the colli-

sion. RCVCNT [10:8] corre-

spond to bits 3-0 in RFS1 of the

Bit 1

RES

Reserved. Read as zero. Always

write as zero. Bit 0 ASTRP RCV

Auto Strip Receive. ASTRP

RCV enables the automatic pad

stripping feature. The pad and

FCS fields will be stripped from

receive frames and not placed in

the FIFO. ASTRP RCV is set by

activation of the RESET pin or

the SWRST bit.

Receive

RCVCNT [11–0] will be invalid

when OFLO is set.

Frame

Status.

RFS1—Receive Status (RCVSTS)

OFLO CLSN FRAM FCS RCVCNT [10:8]

Bit Name Description

Receive Frame Status (RCVFS)

(REG ADDR 6)

RCVFS [31–00]

The Receive Frame Status is a single byte location

which must be read by four read cycles to obtain the

four bytes (32-bits) of status associated with each

Bit 7

OFLO

Overflow flag. Indicates that the

Receive FIFO over flowed due

60

Am79C940

to the inability of the host/con-

troller to read data fast enough

to keep pace with the receive se-

rial bit stream and the latency

provided by the Receive FIFO it-

self. OFLO is indicated on the re-

ceive frame that caused the

overflow condition; complete

frames in the Receive FIFO are

not affected. While the Receive

FIFO is in the overflow condition,

it ignores additional receive data

on the network. The internal ad-

dress detect logic will continue

to operate and the Missed Pack-

et Count (MPC in register 24) will

be incremented for each packet

which passes the address match

criteria, and complete without

collision.

message from the network.

RCVCNT is 12 bits long, and

valid (accurate) only when there

are no errors reported in the

Receive Status (RCVSTS). If a

late collision is detected (CLSN

set in RCVSTS), the count is an

indication of the length (in byte

times) of the duration of the

receive activity including the

collision. RCVCNT [7:0] corre-

spond to bits 7-0 in RFS0 of the

Receive

Frame

Status.

RCVCNT [11–0} will be invalid

when OFLO is set.

RFS2—Runt Packet Count (RNTPC)

RNTPC [7–0]

Bit

Name

Description

Bit 6

CLSN

Collision Flag. Indicates that the

receive operation suffered a col-

lision during reception of the

frame. If CLSN is set, it indicates

that the receive frame suffered a

late collision, since a frame ex-

periencing collision within the

slot time will be automatically

deleted from the RCVFIFO (pro-

viding LLRCV in the Receive

Frame Control register is

cleared). Note that if the LLRCV

bit is enabled, the late collision

threshold is effectively moved

from the normal 64–byte (512–

bit) level to the 12-byte (96–bit)

level. Runt packets suffering a

collision will be flushed from the

RCVFIFO regardless of the

state of the RPA bit (User Test

Register). CLSN will not be set if

OFLO is set.

Bit 7-0 RNTPC

The

indicates

Runt

Packet

Count

[7–0]

the number of runt packets

received, addressed to this

node, since the last successfully

received packet. The value does

not roll over after 255 runt

packets have been detected,

and will remain frozen at the

maximum count.

RFS3—Receive Collision Count (RCVCC)

RCVCC [7–0]

Bit

Name

Description

Bit 7–0 RCVCC

[7–0]

The Receive Collision Count in-

dicates the number of collisions

detected on the network since

the last successfully received

packet. The value does not roll

over after 255 collisions have

been detected, and will remain

frozen at the maximum count.

Bit 5

FRAM

Framing Error flag. Indicates

that

the

received

frame

contained a non-integer multiple

of bytes and an FCS error. If

there was no FCS error then

FRAM will not be set. FRAM is

FIFO Frame Count (FIFOFC)

(REG ADDR 7)

not

valid

during

internal

RCVFC[3–0] XMTFC[3–0]

loopback. FRAM will not be set if

OFLO is set.

Bit

Name

Description

Bit 4

FCS

FCS Error flag. Indicates that

there is an FCS error in the

frame. The receive FCS is

computed and checked normally

when ASTRP RCV = 1, but is not

passed to the host. FCS will not

be set if OFLO is set.

Bit 7–4 RCVFC

[3–0]

Receive Frame Count. The

(read

only) count of the frames in the

Receive FIFO. A frame is count-

ed when the last byte is put in

the FIFO. The counter is decre-

mented when the last byte of the

frame is read. If the RCVFC

reaches its maximum value of

Bit 3-0 RCVCNT

[11:8]

The Receive Message Byte

Count indicates the number of

whole bytes in the received

Am79C940

61

15, additional receive frames will

be ignored, and the Missed

Packet Count (MPC) register will

be incremented for frames which

match the internal address(es)

of the MACE device.

corresponding

BABLM = 0.

mask

bit

BABL is READ/CLEAR only,

and is set by the MACE device

and reset when read. Writing

has no effect. It is also cleared

by activation of the RESET pin

or SWRST bit.

Bit 3–0 XMTFC

[3–0]

Transmit Frame Count. The

(read only) count of the frames in

the Transmit FIFO. A frame is

counted when the last byte is put

in the FIFO. The counter is dec-

remented when XMTSV (in the

Transmit Frame Status and Poll

Register) is set and the Transmit

Frame Status read access is

performed.

Bit 5

CERR

Collision Error. CERR indicates

the absence of the Signal Quali-

ty Error Test (SQE Test) mes-

sage after a packet transmis-

sion. The SQE Test message is

a transceiver test feature. Detec-

tion depends on the MACE net-

work interface selected. In all

cases, CERR will be set if the

MACE device failed to observe

the SQE Test message within 20

network bit times after the pack-

et transmission ended. When

CERR is set, the INTR pin will be

activated if the corresponding

mask bit CERRM = 0.

Interrupt Register (IR)

(REG ADDR 8)

All status bits are set upon occurrence of an event and

cleared when read. The resister is read only. In addition

all status bits are cleared by hardware or software

reset. Bit assignments for the register are as follows:

JAB BABL CERR RDVCCO RNTPCO MPCO RCVINT XMTINT

Bit

Name

JAB

Description

When the AUI port is selected,

the SQE Test message is

returned over the CI± pair as a

brief (5-15 bit times) burst of 10

Bit 7

Jabber Error. JAB indicates that

the MACE device attempted to

transmit for an excessive time

period (20–150 ms), when using

either the DAI port or the

10BASE–T port. If the internal

jabber timer expires during

transmission, the transmit bit

stream will be interrupted, until

the internal transmission ceases

and the unjab timer (0.5 s ±0.25

s) expires. The jabber function

will be disabled, and JAB will not

be set, regardless of transmis-

sion length, when either the AUI

or GPSI ports have been

selected.

MHz

activity.

When

the

10BASE–T port is selected,

CERR will be reported after a

transmission only when the

internal transceiver is in the link

fail state (LNKST pin = HIGH).

When the GPSI port is selected,

the CLSN pin must be asserted

by the external encoder/decoder

to provide the SQE Test func-

tion. When the DAI port is select-

ed, CERR will not be reported at

any time.

CERR is READ/CLEAR only. It

is set by the MACE and reset

when read. Writing has no

effect. It is also cleared by

activation of the RESET pin or

SWRST bit.

JAB is READ/CLEAR only, and

is set by the MACE device and

reset when read. Writing has no

effect. It is also cleared by acti-

vation of the RESET pin or

SWRST bit.

Bit 4

RCVCCO Receive Collision Count Over-

flow. Indicates that the Receive

Collision Count register rolled

over at a value of 255 receive

collisions. Receive collisions are

defined as received frames

which suffered a collision. The

INTR pin will be activated if the

corresponding mask bit RCVC-

COM = 0. Note that the RCVCC

value returned in the Receive

Frame Status (RFS3) will freeze

at a value of 255, whereas this

register based version of

Bit 6

BABL

Babble Error. BABL is the

transmitter time-out error. It in-

dicates that the transmitter has

been on the channel longer

than the time required to send

the maximum packet. It will be

set after 1519 bytes (or great-

er) have been transmitted. The

MACE device will continue to

transmit until the current pack-

et transmission is over. The

INTR pin will be activated if the

62

Am79C940

RCVCC (REG ADDR 27) is free

running.

the corresponding mask bit

RCVINTM = 0.

RCVCCO is READ/CLEAR only.

It is set by the MACE device and

reset when read. Writing has no

effect. It is also cleared by

asserting the RESET pin or

SWRST bit.

RCVINT is READ/CLEAR only.

It is set by the MACE device and

reset when read. Writing has no

effect. It is also cleared by acti-

vation of the RESET pin or

SWRST bit.

Bit 3

RNTPCO

Runt Packet Count Overflow.

Indicates that the Runt Packet

Count register rolled over at a

value of 255 runt packets. Runt

packets are defined as received

frames which passed the inter-

nal address match criteria but

did not contain a minimum of

64-bytes of data after SFD. The

INTR pin will be activated if

the corresponding mask bit

RNTPCOM = 0. Note that the

RNTPC value returned in the

Receive Frame Status (RFS2)

will freeze at a value of 255,

whereas this register based

version of RNTPC (REG ADDR

26) is free running.

Bit 0

XMTINT

Transmit Interrupt. Indicates that

the MACE device has completed

the transmission of a packet and

updated the Transmit Frame

Status. The INTR pin will be

activated if the corresponding

mask bit XMTINTM = 0.

XMTINT is READ/CLEAR only.

It is set by the MACE device and

reset when read. Writing has no

effect. It is also cleared by acti-

vation of the RESET pin or

SWRST bit.

Interrupt Mask Register (IMR)

(REG ADDR 9)

This register contains the mask bits for the interrupts.

Read/write operations are permitted. Writing a one into

a bit will mask the corresponding interrupt. Writing a

zero to any previously set bit will unmask the corre-

sponding interrupt. Bit assignments for the register are

as follows:

RNTPCO is READ/CLEAR only.

It is set by the MACE device and

reset when read. Writing has no

effect. It is also cleared by

asserting the RESET pin or

SWRST bit.

RES BABLM

CERRM

RCVCCOM RNTPCOM MPCOM

RCVINTM

XMTINTM

Bit

Name

Description

Bit 2

MPCO

Missed Packet Count Overflow.

Indicates that the Missed Packet

Count register rolled over at a

value of 255 missed frames.

Missed frames are defined as

received frames which passed

the internal address match

criteria but were missed due to a

Receive FIFO overflow, the

receiver being disabled (ENRCV

= 0) or an excessive receive

frame count (RCVFC > 15). The

INTR pin will be activated if the

corresponding mask bit MPCOM

= 0.

Bit 7

Bit 6

Bit 5

Bit 4

JABM

Jabber Error Mask. JABM is the

mask for JAB. The INTR pin will

not be asserted by the MACE

device regardless of the state of

the JAB bit, if JABM is set. It is

cleared by activation of the

RESET pin or SWRST bit.

BABLM

CERRM

Babble Error Mask. BABLM is

the mask for BABL. The INTR

pin will not be asserted by the

MACE device regardless of the

state of the BABL bit, if BABLM

is set. It is cleared by activation

of the RESET pin or SWRST bit.

MPCO is READ/CLEAR only. It

is set by the MACE device and

reset when read. Writing has no

effect. It is also cleared by

asserting the RESET pin or

SWRST bit.

Collision Error Mask. CERRM is

the mask for CERR. The INTR

pin will not be asserted by the

MACE device regardless of the

state of the CERR bit, if CERRM

is set. It is cleared by activation

of the RESET pin or SWRST bit.

Bit 1

RCVINT

Receive Interrupt. Indicates that

the host read the last byte/word

of a packet from the Receive

FIFO. The Receive Frame Sta-

tus is available immediately on

the next host read operation.

The INTR pin will be activated if

RCVCCOM Receive Collision Count Over-

flow Mask. RCVCCOM is the

mask for RCVCCO(Receive

Collision Count Overflow). The

INTR pin will not be asserted by

Am79C940

63

the MACE device regardless of

the state of the RCVCCO bit, if

RCVCCOM is set. It is cleared

by activation of the RESET pin

or SWRST bit.

Bit 6

Bit 5

TDTREQ

RDTREQ

Transmit

Data

Transfer

Request. An internal indication

of the current request status of

the Transmit FIFO. TDTREQ is

set when the external TDTREQ

signal is asserted.

Bit 3

RNTPCOM Runt Packet Count Overflow

Mask. RNTPCOM is the mask

for RNTPCO (Runt Packet

Count Overflow). The INTR pin

will not be asserted by the

MACE device regardless of the

state of the RNTPCO bit, if

RNTPCOM is set. It is cleared by

activation of the RESET pin or

SWRST bit.

Receive Data Transfer Request.

An internal indication of the cur-

rent request status of the

Receive FIFO. RDTREQ is set

when the external RDTREQ

signal is asserted.

Bit 4-0 RES

Reserved. Read as zeroes.

Always write as zeroes.

BIUConfigurationControl(BIUCC) (REGADDR11)

Bit 2

MPCOM

Missed Packet Count Overflow

Mask. MPCOM is the mask for

MPCO (Missed Packet Count

Overflow). The INTR pin will not

be asserted by the MACE device

regardless of the state of the

MPCO bit, if MPCOM is set. It is

cleared by activation of the

RESET pin or SWRST bit.

All bits within the BIU Configuration Control register will

be set to their default state upon a hardware or soft-

ware reset. Bit assignments are as follows:

RES

BSWP XMTSP [1-0]

RES

SWRST

Bit

Name

Description

Bit 1

Bit 0

.

RCVINTM Receive

Interrupt

Mask.

Bit 7

Bit 6

RES

Reserved. Read as zero. Always

write as zero.

RCVINTM is the mask for

RCVINT. The INTR pin will not

be asserted by the MACE device

regardless of the state of the

RCVINT bit, if RCVINTM is set. It

is cleared by activation of the

RESET pin or SWRST bit.

BSWP

Byte Swap. The BSWP function

allows data to and from the

FIFOs to be orientated accord-

ing to little endian or big endian

byte

ordering

conventions.

BSWP is cleared by by activa-

tion of the RESET pin or SWRST

bit, defaulting to Intel byte

ordering.

XMTINTM Transmit

Interrupt

Mask.

XMTINTM is the mask for

XMTINT. The INTR pin will not

be asserted by the MACE device

regardless of the state of the

XMTINT bit, if XMTINT is set. It

is cleared by activation of the

RESET pin or SWRST bit

Bit 5-4 XMTSP

[1-0]

Transmit Start Point. XMTSP

controls the point preamble

transmission commences in

relation to the number of bytes

written to the XMTFIFO. When

the entire frame is in the XMT-

FIFO (or the XMTFIFO becomes

full before the threshold is

achieved), transmission of pre-

amble will start regardless of the

value in XMTSP (once the IPG

time has expired). XMTSP is

given a value of 10 (64 bytes)

after hardware or software reset.

Regardless of XMTSP, the FIFO

will not internally over write its

data until at least 64 bytes, or the

entire frame, has been transmit-

ted onto the network. This

ensures that for collisions within

the slot time window, transmit

data need not be re-written to

the XMTFIFO, and re-tries will

be handled autonomously by the

MACE device.

XMTSV TDTREQ RDTREQ RES

RES

Poll Register (PR)

(REG ADDR 10)

This register contains copies of internal status bits to

simplify a host implementation which is non-interrupt

driven. The register is read only, and its status is unaf-

fected by read operations. All register bits are cleared

by hardware or software reset. Bit assignments are as

follows:

Bit

Name

Description

Bit 7

XMTSV

Transmit Status Valid. Transmit

Status Valid indicates that the

Transmit Frame Status is valid.

64

Am79C940

Transmit Start Point

XMTSP [1-0]

write cycles (including an

End-Of-Frame delimiter),

Bytes

4

TDTREQ may go inactive before

the XMTSP threshold is reached

when using the non burst mode

(XMTBRST = 0). The host must

be aware that despite TDTREQ

going inactive, additional space

exists in the XMTFIFO, and the

data write must continue to

ensure the XMTSP threshold is

achieved. No transmit activity

will commence until the XMTSP

threshold is reached. When

using the burst mode, TDTREQ

will not be de-asserted until only

a single write cycle can be per-

formed. See the FIFO Sub-sys-

tem section for additional de-

tails.

00

01

10

11

16

64

112

Bit 3-1 RES

Bit 0 SWRST

Reserved. Read as zeroes. Al-

ways write as zeroes.

Software Reset. When set, pro-

vides an equivalent of the hard-

ware RESET pin function. All

register bits will be set to their

default values. The MACE de-

vice will require re-initialization

after SWRST has been activat-

ed. The MACE device will clear

SWRST during its internal reset

sequence.

Bit 5-4 RCVFW

[1-0]

Receive FIFO Watermark.

RCVFW controls the point

RDTREQ is asserted in relation

to the number of bytes available

in the RCVFIFO. RCVFW speci-

fies the number of bytes which

must be present (once the pack-

FIFO Configuration Control

(FIFOCC)

(REG ADDR 12)

All bits within the FIFO Configuration Control register

will be set to their default state upon a hardware or soft-

ware reset. Bit assignments are as follows:

et has been verified as

a

non-runt), before the RDTREQ

is asserted. Note however that in

order for RDTREQ to be activat-

ed for a new frame, at least

64-bytes must have been

received. This effectively avoids

reacting to receive frames which

are runts or suffer a collision dur-

ing the slot time (512 bit times).

If the Runt Packet Accept fea-

ture (RPA in Receive Frame

XMTFW[1-0] RCVFW [1-0] XMTFWU RCVFWU XMTBRST RCVBRST

Bit

Name

Description

Bit 7-6 XMTFW

[1-0]

Transmit

FIFO Watermark.

XMTFW controls the point

TDTREQ is asserted in relation

to the number of write cycles to

the Transmit FIFO. TDTREQ will

be asserted at any time that the

number of write cycles specified

by XMTFW can be executed.

XMTFW is set to a value of 00 (8

cycles) after hardware or

software reset.

Control)

is

enabled,

the

RDTREQ pin will be activated as

soon as either 64-bytes are

received, or a complete valid

receive frame is detected

(regardless of length). RCVFW

is set to a value of 10 (64 bytes)

after hardware or software reset.

Transmit FIFO Watermarks

Receive FIFO Watermarks

XMTSP [1–0]

Bytes

8

00

01

10

11

XMTSP [1–0]

Bytes

16

00

01

10

11

32

XX

64

XX

The XMTFW value will only be

updated when the XMTFWU bit

is set.

The RCVFW value will only be

updated when the RCVFWU bit

is set.

To ensure that sufficient space

is present in the XMTFIFO to

accept the specified number of

Bit 3

XMTFWU Transmit

FIFO

Watermark

Update. Allows update of the

Am79C940

65

Transmit FIFO Watermark bits.

The XMTFW can be written at

any point, and will be read back

as written. However, the new

value in the XMTFW bits will be

ignored until XMTFWU is set (or

the transmit path is reset due to

a retry failure). The recommend-

ed procedure to change the

XMTFW is to write the new value

with XMTFWU set, in a single

write cycle. The XMTFIFO

should be empty and all transmit

activity complete before attempt-

ing a watermark update, since

the XMTFIFO will be reset to

allow the new pointer values to

be loaded. It is recommended

that the transmitter be disabled

by clearing the ENXMT bit.

XMTFWU will be cleared by the

MACE device after the new

XMTFW value has been loaded,

or by activation of the RESET

pin or SWRST bit.

asserted identically in both

normal and burst modes, when

there is sufficient space in the

XMTFIFO to allow the specified

number of write cycles to occur

(programmed by the XMTFW

bits).

Cleared by activation of the

RESET pin or SWRST bit.

Bit 0

RCVBRST Receive Burst. When set, the

receive burst mode is selected.

The behavior of the Receive

FIFO low watermark, and hence

the de-assertion of RDTREQ,

will be modified. RDTREQ will

de-assert when there are only

2-bytes of data available in the

RCVFIFO (so that a full word

read can still occur).

RDTREQ will be asserted identi-

cally in both normal and burst

modes, when a minimum of

64-bytes have been received for

a new frame (or a runt packet

has been received and RPA is

set). Once the 64-byte limit has

been exceeded, RDTREQ will

be asserted providing there is

sufficient data in the RCVFIFO

to exceed the threshold, as pro-

grammed by the RCVFW bits.

Bit 2

RCVFWU Receive

FIFO

Watermark

Update. Allows update of the

Receive FIFO Watermark bits.

The RCVFW bits can be written

at any point, and will read back

as written. However, the new

value in the RCVFW bits will be

ignored until RCVFWU is set.

The recommended procedure to

change the RCVFW is to write

the new value with RCVFWU

set, in a single write cycle. The

RCVFIFO should be empty

before attempting a watermark

update, since the RCVFIFO will

be reset to allow the new pointer

values to be loaded. It is recom-

mended that the receiver be dis-

abled by clearing the ENRCV

bit. RCVFWU will be cleared by

the MACE device after the new

RCVFW value has been loaded,

or by activation of the RESET

pin or SWRST bit.

Cleared by activation of the

RESET pin or SWRST bit.

MAC Configuration

Control (MACCC)

(REG ADDR 13)

This register programs the transmit and receive opera-

tion and behavior of the internal MAC engine. All bits

within the MAC Configuration Control register are

cleared upon hardware or software reset. Bit

assignments are as follows:

PROM DXMT2PD EMBA RES DRCVPA DRCVBC ENXMT ENRCV

Bit

Name

Description

Bit 7

PROM

Promiscuous. When PROM is

set all incoming frames are

received regardless of the desti-

nation address. PROM is

cleared by activation of the

RESET pin or SWRST bit.

Bit 1

XMTBRST Transmit Burst. When set, the

transmit burst mode is selected.

The behavior of the Transmit

FIFO high watermark, and

hence the de-assertion of

TDTREQ, will be modified.

TDTREQ will be deasserted if

there are only two bytes of space

available in the XMTFIFO (so

that a full word write can still

occur) or if four bytes of space

exist and the EOF pin is assert-

ed by the host.TDTREQ will be

Bit 6

Bit 5

DXMT2PD Disable Transmit Two Part

Deferral. When set, disables the

transmit two part deferral option.

DXMT2PD is cleared by

activation of the RESET pin or

SWRST bit.

EMBA

Enable Modified Back-off Algo-

rithm. When set, enables the

66

Am79C940

modified backoff algorithm.

EMBA is cleared by activation of

the RESET pin or SWRST bit.

ceive activity and remains

cleared for a long time and if the

tail end of the receive frame cur-

rently in progress is longer than

the amount of space available in

the Receive FIFO, Receive

FIFO overflow will occur. How-

ever, even with RDTREQ deas-

serted, if there is valid data in the

Receive FIFO to be read, suc-

cessful slave reads to the

Receive FIFO can be executed

(indicated by valid DTV). It is the

host’s responsibility to avoid the

overflow situation. ENRCV is

cleared by activation of the

RESET pin or SWRST bit.

Bit 4

Bit 3

RES

Reserved. Read as zeroes.

Always write as zeroes.

DRCVPA

Disable

Receive

Physical

Address. When set, the physical

address detection (Station or

node ID) of the MACE device will

be disabled. Packets addressed

to the nodes individual physical

address will not be recognized

(although the packet may be

accepted by the EADI mecha-

nism). DRCVPA is cleared by

activation of the RESET pin or

SWRST bit.

PLS Configuration

Control (PLSCC)

Bit 2

DRCVBC

Disable Receive Broadcast.

When set, disables the MACE

device from responding to

broadcast messages. Used for

protocols that do not support

broadcast addressing, except as

a function of multicast. DRCVBC

is cleared by activation of the

RESET pin or SWRST bit

(broadcast messages will be

received).

(REG ADDR 14)

All bits within the PLS Configuration Control register

are cleared upon a hardware or software reset. Bit

assignments are as follows:

RES RES RES RES

XMTSEL

PORTSEL [1-0]

ENPLSIO

Bit

Bit 7-4 RES

Bit 3 XMTSEL

Name

Description

Reserved. Read as zeroes.

Always write as zeroes.

Bit 1

ENXMT

Enable

Transmit.

Setting

ENXMT = 1 enables transmis-

sion. With ENXMT = 0, no trans-

mission will occur. If ENXMT is

written as 0 during frame trans-

mission, a packet transmission

which is incomplete will have a

Transmit Mode Select. XMTSEL

provides control over the AUI

DO+ and DO– operation while

the MACE device is not transmit-

ting. With XMTSEL = 0, DO+

and DO will be equal during

transmit idle state, providing

zero differential to operate trans-

former coupled loads. The turn

off and return to zero delays are

guaranteed

CRC

violation

appended before the internal

Transmit FIFO is cleared. No

subsequent attempts to load the

FIFO should be made until

ENXMT is set and TDTREQ is

asserted. ENXMT is cleared by

activation of the RESET pin or

SWRST bit.

controlled

internally.

With

XMTSEL = 1, DO+ is positive

with respect to DO during the

transmit idle state .

Bit 2-1 PORTSEL Port Select. PORTSEL is used

Bit 0

ENRCV

Enable Receive. Setting ENRCV

= 1 enables reception of frames.

With ENRCV = 0, no frames will

be received from the network

into the internal FIFO. When

ENRCV is written as 0, any

receive frame currently in

progress will be completed (and

valid data contained in the

RCVFIFO can be read by the

host) and the MACE device will

enter the monitoring state for

missed packets. Note that

clearing the ENRCV bit disables

the assertion of RDTREQ. If

ENRCV is cleared during re-

[1-0]

to select between the AUI,

10BASE–T, DAI or GPSI ports

of the MACE device. PORTSEL

is cleared by hardware or soft-

ware reset. PORTSEL will deter-

mine which of the interfaces is

used during normal operation, or

tested when utilizing the loop-

back options (LOOP [1-0]) in the

User Test Register. Note that

the PORTSEL [1–0] program-

ming will be overridden if the

ASEL bit in the PHY Configura-

tion Control register is set.

Am79C940

67

PORTSEL Interface Definition

DLNKTST bit. With Link Test

disabled (DLNKTST = 1), the

data driver, receiver and loop-

back functions as well as colli-

sion detection remain enabled

irrespective of the presence or

absence of data or link pulses on

the RXD± pair. The transmitter

will continue to generate link

beat pulses during periods of

transmit data inactivity. Set by

hardware or software reset.

PORTSEL

Active

[1–0]

Interface

DXCVR Pin

LOW

00

AUI

10BASE–T

DAI Port

GPSI

01

HIGH

10

HIGH

11

LOW

Bit 0

ENPLSIO Enable PLS I/O. ENPLSIO is

used to enable the optional I/O

functions from the PLS function.

The following pins are affected

by the ENPLSIO bit: RXCRS,

Bit 6

Bit 5

DLNKTST Disable Link Test. When set, the

integrated 10BASE–T transceiv-

er will be forced into the link pass

state, regardless of receive link

test pulses or receive packet

activity.

RXDAT,

TXDAT-,

TXEN,

CLSN,

TXDAT+,

STDCLK,

RDCLK and SRD. Note that if an

external SIA is being utilized via

the GPSI, PORTSEL [1–0] = 11

must be programmed before

ENPLSIO is set, to avoid con-

tention of clock, data and/or

carrier indicator signals.

REVPOL

Reversed Polarity. Indicates the

receive polarity of the RD± pair.

When normal polarity is detect-

ed, the REVPOL bit will be

cleared, and the RXPOL pin

(capable of driving a Polarity OK

LED) will be driven LOW. When

reverse polarity is detected, the

REVPOL bit will be set, and the

RXPOL pin should be externally

pulled HIGH.

PHY Configuration

Control (PHYCC)

(REG ADDR 15)

All bits within the PHY Configuration Control register

with the exception of LNKFL, are cleared by hardware

or software reset. Bit assignments are as follows:

Bit 4

DAPC

Disable Auto Polarity Correction.

When set, the automatic polarity

correction will be disabled.

Polarity detection and indication

will still be possible via the

RXPOL pin.

LNKFL DLNKTST REVPOL DAPC LRT ASEL RWAKE AWAKE

Bit

Name

Description

Bit 7

LNKFL

Link Fail. Reports the link integ-

rity of the 10BASE–T receiver.

When the link test function is

enabled (DLNKTST = 0), the

absence of link beat pulses on

the RXD± pair will cause the

integrated 10BASE–T transceiv-

er to go into the link fail state. In

the link fail state, data transmis-

sion, data reception, data loop-

back and the collision detection

functions are disabled, and

remain disabled until valid data

or >5 consecutive link pulses

appear on the RXD± pair. During

link fail, the LNKFL bit will be set

and the LNKST pin should be

externally pulled HIGH. When

the link is identified as function-

al, the LNKFL bit will be cleared

and the LNKST pin is driven

LOW, which is capable of direct-

ly driving a Link OK LED. In

order to inter-operate with sys-

tems which do not implement

Link Test, this function can be

Bit 3

Bit 2

LRT

Low Receive Threshold. When

set, the threshold of the twisted

pair receiver will be reduced by

4.5 dB, to allow extended dis-

tance operation.

ASEL

Auto Select. When set, the

PORTSEL [1-0] bits are overrid-

den, and the MACE device will

automatically select the operat-

ing media interface port. When

the 10BASE–T transceiver is in

the link pass state (due to receiv-

ing valid packet data and/or Link

Test pulses or the DLNKTST bit

is set), the 10BASE-T port will be

used. When the 10BASE–T port

is in the link fail state, the AUI

port will be used. Switching

between the ports will not occur

during transmission in order to

avoid any type of fragment

generation.

Bit 1

RWAKE

Remote Wake. When set prior to

the SLEEP pin being activated,

the AUI and 10BASE–T receiver

sections and the EADI port will

disabled

by

setting

the

68

Am79C940

continue to operate even during

SLEEP. Incoming packet activity

will be passed to the EADI port

pins permitting detection of spe-

cific frame contents used to ini-

ADDR or LOGADDR can be set in the same cycle as

ADDRCHG.

ADDRCHG RES RES RES RES PHYADDR LOGADDR RES

Bit

Name

Description

tiate

a

wake-up sequence.

RWAKE must be programmed

prior to SLEEP being asserted

for this function to operate.

RWAKE is not cleared by

SLEEP, only by activation of the

SWRST bit or RESET pin.

Bit 7

ADDRCHG Address Change. When set,

allows the physical and/or logi-

cal address to be read or pro-

grammed. When ADDRCHG is

set, ENRCV will be cleared, the

MPC will be stopped, and the

last or current in progress

receive frame will be received as

normal. After the frame com-

pletes, access to the internal

address RAM will be permitted,

indicated by the MACE device

clearing the ADDRCHG bit.

Please refer to the register

description of the ENRCV bit in

the MAC Configuration Control

register (REG ADDR 13) for the

effect of clearing the ENRCV bit.

Normal reception can be

resumed once the physical/logi-

cal address has been changed,

by setting ENRCV.

Bit 0

AWAKE

Auto Wake. When set prior to

the SLEEP pin being activated,

the 10BASE-T receiver section

will continue to operate even

during SLEEP, and will activate

the LNKST pin if Link Pass is

detected. AWAKE must be pro-

grammed prior to SLEEP being

asserted for this function to

operate. AWAKE is not cleared

by SLEEP, only by activation of

the SWRST bit or RESET pin.

Chip Identification Register

(CHIPID [15-00])

(REG ADDR 16 &17)

This 16-bit value corresponds to the specific version of

the MACE device being used. The value will be

programmed to X940h, where X is a value dependent

on version. [For the current version of the MACE de-

vice, X = 3 to denote Rev C0 silicon.]

Bit 6-3 RES

Reserved. Read as zeroes.

Always write as zeroes.

CHIPID [07–00]

CHIPID [15–08]

Bit 2

Bit 1

Bit 0

PHYADDR Physical Address Reset. When

set, successive reads or writes

to the Physical Address Register

will occur in the order PADR

[07–00], PADR [15–08],....,

PADR [47–40]. Each read or

write operation on the PADR

location will auto-increment the

internal pointer to access the

next most significant byte.

Internal Address

Configuration (IAC)

(REG ADDR 18)

This register allows access to and from the multi-byte

Physical Address and Logical Address Filter locations,

using only a single byte location.

The MACE device will reset the IAC register PHYADDR

and LOGADDR bits after the appropriate number of

read or write cycles have been executed on the Physical

Address Register or the Logical Address Filter. Once the

LOGADDR bit is set, the MACE device will reset the bit

after 8 read or write operations have been performed.

Once the PHYADDR bit is set, the MACE device will

reset the bit after 6 read or write operations have been

performed. The MACE device makes no distinction be-

tween read or write operations, advancing the internal

address RAM pointer with each access. If both PHY-

ADDR and LOGADDR bits are set, the MACE device

will accept only the LOGADDR bit. If the PHYADDR bit

is set and the Logical Address Filter location is ac-

cessed, a DTV will not be returned. Similarly, if the

LOGADDR bit is set and the Physical Address Register

location is accessed, DTV will not be returned. PHY-

LOGADDR Logical Address Reset. When

set, successive reads or writes

to the Logical Address Filter will

occur in the order LADRF [07–

00], LADRF [15-08],....,LADRF

[63–56]. Each read or write

operation on the LADRF location

will auto-increment the internal

pointer to access the next most

significant byte.

RES

Reserved. Read as zero. Always

write as zero.

Logical Address Filter

(LADRF [63–00])

(REG ADDR 20)

LADRF [63–00]

This 64-bit mask is used to accept incoming Logical

Addresses. The Logical Address Filter is expected to

be programmed at initialization (after hardware or

Am79C940

69

software reset). After a hardware or software reset and

before the ENRCV bit in the MAC Configuration Con-

trol register has been set, the Logical Address can be

accessed by setting the LOG ADDR bit in the Internal

Address Configuration register (REG ADDR 18) and

then by performing 8 reads or writes to the Logical

Address Filter. Once ENRCV has been set, the ADDR

CHG bit in the Internal Address Configuration register

must be set and be polled until it is cleared by the

MACE device before setting the LOGADDR bit and

before accessing of the Logical Address Filter is

allowed.

address and is compared against the value stored in

the Physical Address Register at initialization.

The Logical Address Filter is used in multicast address-

ing schemes. The acceptance of the incoming frame

based on the filter value indicates that the message

may be intended for the node. It is the user’s responsi-

bility to determine if the message is actually intended

for the node by comparing the destination address of

the stored message with a list of acceptable logical

addresses.

The Broadcast address, which is all ones, does not go

through the Logical Address Filter and is always

enabled provided the Disable Receive Broadcast bit

(DRCVBC in the MAC Configuration Control register) is

cleared. If the Logical Address Filter is loaded with all

zeroes (and PROM = 0), all incoming logical addresses

except broadcast will be rejected.

If the least significant address bit of a received

message is set (Destination Address bit 00 = 1), then

the address is deemed logical, and passed through the

FCS generator. After processing the 48-bit destination

address, a 32-bit resultant FCS is produced and

strobed into an internal register. The high order 6-bits

of this resultant FCS are used to select one of the 64-bit

positions in the Logical Address Filter (see diagram). If

the selected filter bit is a 1, the address is accepted and

the packet will be placed in memory.

Multicast addressing can only be performed when

using external loopback (LOOP [1–0] = 0) by pro-

gramming RCVFCSE = 1 in the User Test Register.

The FCS logic is internally allocated to the receiver

section, allowing the FCS to be computed on the in-

coming logical address.

The first bit of the incoming address must be a 1 for a

logical address. If the first bit is a 0, it is a physical

32-Bit Resultant CRC

Received Message

Destination Address

31

26

0

47

1

0

1

CRC

GEN

Logical

Address

Filter

(LADRF)

63

0

SEL

64

MATCH*

MUX

6

MATCH = 1:

MATCH = 0:

Packet Accepted

Packet Rejected

16235D-10

Logical Address Match Logic

70

Am79C940

ꢀ The packet must pass the internal address match to

be counted. Any of the following address match

conditions will increment MPC while the receiver is

deaf:

Physical Address

(PADR [47-00])

(REG ADDR 21)

PADR [47–00]

Physical Address match;

Logical Address match;

Broadcast reception;

Any receive in promiscuous mode (PROM = 1 in the

MAC Configuration Control register);

EADI feature match mode and EAM is asserted;

EADI feature reject mode and EAR is not asserted.

This 48-bit value represents the unique node value

assigned by the IEEE and used for internal address

comparison. After a hardware or software reset and

before the ENRCV bit in the MAC Configuration Con-

trol register has been set, the Physical Address can be

accessed by setting the PHYADDR bit in the Internal

Address Configuration register (REG ADDR 18) and

then by performing 6 reads or writes to the Physical

Address. Once ENRCV has been set, the ADDRCHG

bit in the Internal Address Configuration register must

be set and be polled until it is cleared by the MACE

device before setting the PHYADDR bit and before

accessing of the Physical Address is allowed. The first

bit of the incoming address must be a 0 for a physical

address. The incoming address is compared against

the value stored in the Physical Address register at ini-

tialization provided that the DRCVPA bit in the MAC

Configuration Control register is cleared.

ꢀ Any packet which suffers a collision within the slot

time will not be counted.

ꢀ Runt packets will not be counted unless RPA in the

User Test Register is enabled.

ꢀ Packets which pass the address match criteria but

experience FCS or Framing errors will be counted,

since they are normally passed to the host.

Runt Packet Count (RNTPC)

(REG ADDR 26)

RNTPC [7–0]

The Runt Packet Count (RNTPC) is a read only 8-bit

counter, incremented when the receiver detects a runt

packet that is addressed to this node. Runt packets are

defined as received frames which passed the internal

address match criteria but did not contain a minimum

of 64-bytes of data after SFD. Note that the RNTPC

value returned in the Receive Frame Status (RFS2) will

freeze at a value of 255, whereas this register based

version of RNTPC is free running. The value will roll

over after 255 runt packets have been detected, setting

the RNTPCO bit (in the Interrupt Register and assert-

ing the INTR pin if the corresponding mask bit (RNTP-

COM in the Interrupt Mask Register) is cleared.

RNTPC will be reset to zero when read.

Missed Packet Count (MPC)

(REG ADDR 24)

MPC [7–0]

The Missed Packet Count (MPC) is a read only 8-bit

counter. The MPC is incremented when the receiver is

unable to respond to a packet which would have nor-

mally been passed to the host. The MPC will be reset

to zero when read. The MACE device will be deaf to

receive traffic due to any of the following conditions:

ꢀ The host disabled the receive function by clearing

the ENRCV bit in the MAC Configuration Control

register.

ꢀ A Receive FIFO overflow condition exists, and must

be cleared by reading the Receive FIFO and the

Receive Frame Status.

Receive Collision Count (RCVCC)(REG ADDR 27)

RCVCC [7–0]

ꢀ The Receive Frame Count (RCVFC) in the FIFO

Frame Count register exceeds its maximum value,

indicating that greater than 15 frames are in the

Receive FIFO.

The Receive Collision Count (RCVCC) is a read only

8-bit counter, incremented when the receiver detects a

collision on the network. Note that the RCVCC value

returned in the Receive Frame Status (RFS3) will

freeze at a value of 255, whereas this register based

version of RCVCC is free running. The value will roll

over after 255 receive collisions have been detected,

setting the RCVCCO bit (in the Interrupt Register and

asserting the INTR pin if the corresponding mask bit

(RCVCCOM in the Interrupt Mask Register) is cleared.

RCVCC will be reset to zero when read.

If the number of received frames that have been

missed exceeds 255, the MPC will roll over and con-

tinue counting from zero, the MPCO (Missed Packet

Count Overflow) bit in the Interrupt Register will be set

(at the value 255), and the INTR pin will be asserted

providing that MPCOM (Missed Packet Count Overflow

Mask) in the Interrupt Mask Register is clear. MPCOM

will be cleared (the interrupt will be unmasked) after a

hardware or software reset.

Note that the following conditions apply to the MPC:

User Test Register (UTR)

(REG ADDR 29)

The User Test Register is used to put the chip into test

configurations. All bits within the Test Register are

cleared upon a hardware or software reset. Bit

assignments are as follows:

ꢀ After hardware or software reset, the MPC will not

increment until the first time the receiver is enabled

(ENRCV = 1). Once the receiver has been enabled,

the MPC will count all missed packet events,

regardless of the programming of ENRCV.

RTRE

RTRD RPA FCOLL RCVFCSE LOOP [1-0] FD_TEST

71

Bit

Name

Description

trol is clear), and received after

the loopback process through

the Receive FIFO. When set, the

hardware associated with the

FCS generation is allocated to

the receiver. A transmit packet

will be assumed to contain the

FCS in the last four bytes of the

frame passed through the

Transmit FIFO. The received

frame will have the FCS calcu-

lated on the data field and com-

pared with the last four bytes

contained in the received mes-

sage. An FCS error will be

flagged in the Received Status

(RFS1) if the received and cal-

culated values do not match.

RCVFCSE is only valid when in

any one of the loopback modes

as defined by LOOP [0–1]. Note

that if the receive frame is

expected to be recognized on

the basis of a multicast address

match, the FCS logic must be

Bit 7

RTRE

Reserved Test Register Enable.

Access to the Reserved Test

Registers should not be attempt-

ed by the user. Note that

access to the Reserved Test

Register may cause damage

to the MACE device if config-

ured in a system board appli-

cation. Access to the Reserved

Test Register is prevented,

regardless of the state of RTRE,

once RTRD has been set. RTRE

is cleared by activation of the

RESET pin or SWRST bit.

Bit 6

Bit 5

Bit 4

RTRD

Reserved Test Register Disable.

When set, access to the

Reserved Test Registers is

inhibited, and further writes to

the RTRD bit are ignored.

Access to the Reserved Test

Register is prevented, regard-

less of the state of RTRE, once

RTRD has been set. RTRD can

only be cleared by hardware or

software reset.

allocated

to

the

receiver

(RCVFCSE = 1). RCVFCSE is

cleared by activation of the

RESET pin or SWRST bit.

RPA

Runt Packet Accept. Allows

receive packets which are less

than the legal minimum as spec-

ified by IEEE 802.3/Ethernet, to

be passed to the host interface

via the Receive FIFO. The

receive packets must be at least

8 bytes (after SFD) in length to

be accepted. RPA is cleared by

activation of the RESET pin or

SWRST bit.

Bit 2-1 LOOP [1-0] Loopback Control. The loopback

functions allow the MACE

device to receive its own trans-

mitted frames. Three levels of

loopback are provided as shown

in the following table. During

loopback operation a multicast

address can only be recognized

if RCVFCSE = 1. LOOP [0-1] are

cleared by activation of the

RESET pin or SWRST bit

FCOLL

Force Collision. Allows the colli-

sion logic to be tested. The

MACE device should be in an

internal loopback test for the

FCOLL test. When FCOLL = 1, a

collision will be forced during the

next transmission attempt. This

will result in 16 total transmis-

sion attempts (if DRTRY = 0)

with the Retry Error reported in

the Transmit Frame Status reg-

ister. FCOLL is cleared by the

activation of the RESET pin or

SWRST bit.

Loopback Functions

Loop [1–0]

Function

00

01

10

No Loopback

External Loopback

Internal Loopback, excludes

MENDEC

11

Internal Loopback, includes

MENDEC

External loopback allow the

MACE device to transmit to the

physical medium, using either

the AUI, 10BASE–T, DAI or

GPSI port, dependent on the

PORTSEL [1–0] bits in the PLS

Configuration Control register.

Using the internal loopback test

will ensure that transmission

Bit3

RCVFCSE Receive FCS Enable. Allows the

hardware associated with the

FCS generation to be allocated

to the transmitter or receiver dur-

ing loopback diagnostics. When

clear, the FCS will be generated

and appended to the transmit

message (providing that DXMT-

FCS in the Transmit Frame Con-

72

does not disturb the physical

medium and will prohibit frame

reception from the network. One

Internal loopback function in-

cludes the MENDEC in the loop.

To activate Full Duplex Test mode, program the MACE

device into external loopback mode (EXLOOP=1,

INLOOP=0) and set FD_TEST=1. The code sequence

would be as follows:

write 2 08 ;register XMTFC, transmit FCS disable

Bit 0

FD_TEST Full Duplex Test. When set, will

allow the MACE device to

transmit back to back packets

with 9.6 µs IPG regardless of

receive activities. The setting of

this bit should also be in

conjunction with the setting of

Bit 0 of the Transmit Frame Con-

trol (XMTFC) (REG ADDR 2).

The setting of Bit 0 of the

XMTFC register will cause dis-

abling of transmit FCS.

write 29 0b ;register UTR, receive FCS enable external

loop enable, full duplex enable

Reserved Test Register 1 (RTR1) (REG ADDR 30)

Reserved for AMD internal use only.

Reserved Test Register 2 (RTR2) (REG ADDR 31)

Reserved for AMD internal use only.

73

Register Table Summary

Address

0

Mnemonic

RCVFIFO

XMTFIFO

XMTFC

XMTFS

XMTRC

RCVFC

RCVFS

FIFOFC

IR

Contents

Comments

Read only

Receive FIFO [15–00]

Transmit FIFO [15–00]

1

Write only

2

Transmit Frame Control

Transmit Frame Status

Transmit Retry Count

Receive Frame Control

Receive Frame Status (4-bytes)

FIFO Frame Count

Read/Write

Read only

3

4

Read only

5

Read/Write

Read only

6

7

Read only

8

Interrupt Register

Read only

9

IMR

Interrupt Mask Register

Poll Register

Read/Write

Read only

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

PR

BIUCC

FIFOCC

MACCC

PLSCC

PHYCC

CHIPID

IAC

BIU Configuration Control

FIFO Configuration Control

MAC Configuration Control

PLS Configuration Control

PHY Configuration Control

Chip Identification Register [07–00]

Chip Identification Register [15–08]

Internal Address Configuration

Reserved

Read/Write

Read only

Read/Write

Read/Write as 0

Read/Write

Read/Write as 0

Read only

LADRF

PADR

Logical Address Filter (8-bytes)

Physical Address (6-bytes)

Reserved

MPC

Missed Packet Count

Reserved

Read/Write as 0

Read only

RNTPC

RCVCC

Runt Packet Count

Receive Collision Count

Reserved

Read only

Read/Write as 0

Read/Write

Read/Write as 0

UTR

RTR1

RTR2

User Test Register

Reserved Test Register 1

Reserved Test Register 2

74

Register Bit Summary

16-Bit Registers

0

1

RCVFIFO [15–0]

XMTFIFO [15–0]

8-Bit Registers

Address

Mnemonic

2

DRTRY

XMTSV

EXDEF

RES

UFLO

RES

LCOL

RES

DXMTFCS

ONE

RES

APADXMT

3

MORE

RES

DEFER

LCAR

4

XMTRC [3–0]

5

RES

LLRCV

M/R

RES

ASTRPRCV

6

RCVFS [31–00]

7

RCVFC [3–0]

XMTFC [3–0]

8

JAB

JABM

XMTSV

RES

BABL

BABLM

TDTREQ

BSWP

CERR

CERRM

RDTREQ

RCVCCO

RNTPCO

MPCO

MPCOM

RES

RCVINT

RCVINTM

RES

XMTINT

XMTINTM

RES

9

RCVCCOM RNTPCOM

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

RES

XMTSP [1–0]

RCVFW [1–0]

RES

SWRST

RCVBRST

ENRCV

ENPLSIO

AWAKE

XMTFW [1–0]

XMTFWU

DRCVPA

XMTSEL

LRT

RCVFWU

DRCVBC

XMTBRST

ENXMT

PROM

RES

DXMT2PD

RES

EMBA

RES

PORTSEL [1–0]

LNKFL

DLNKTST

REVPOL

DAPC

ASEL

RWAKE

CHIPID [07–00]

CHIPID [15–08]

ADDRCHG

RES

RESERVED

LADRF [63–00]

PADR [47–00]

RESERVED

MPC [7–0]

PHYADDR

LOGADDR

RES

RESERVED

RNTPC [7–0]

RCVCC [7–0]

RESERVED

RTRE

RTRD

RPA

FCOLL

RCVFCSE

LOOP [1–0]

RES

RESERVED

Receive Frame Status

Address

Mnemonic

RFS0

RCVCNT [7:0]

RFS1

RFS2

RFS3

OFLO

CLSN

FRAM

FCS

RCVCNT [10:8]

RNTPC [7–0]

RCVCC [7–0]

75

Programmer’s Register Model

Addr Mnemonic

Contents

R/W

RO

0

1

2

RCVFIFO Receive FIFO–16 bits

XMTFIFO Transmit FIFO–16 bits

WO

XMTFC

XMTFS

Transmit Frame Control

80

08

01

DRTRY

Disable Retry

R/W

DXMTFC

APADXMT

Disable Transmit FCS

Auto Pad Transmit

3

Transmit Frame Status

80

40

20

10

08

04

02

01

XMTSV

UFLO

LCOL

MORE

ONE

Transmit Status Valid

Underflow

Late Collision

MORE than one retry was needed

Exactly ONE retry occurred

Transmission was deferred

Loss of Carrier

R/W

DEFER

LCAR

RTRY

Transmit aborted after 16 attempts

4

5

XMTRC

RCVFC

80

40

20

10

0F

EXDEF

Excessive Defer

–

RO

–

XMTRC [3:0]

4-bit Transmit Retry Count

Receive Frame Control

08

04

01

LLRCV

M/R

Low Latency Receive

Match/Reject for external address detection

Auto Strip Receive–Strips pad and FCS from

received frames

R/W

RO

ASTRPRCV

Receive Frame Status–4 bytes–read in 4 read cycles

6

RCVFS

RFS0 RCVCNT [7:0] Receive Message Byte Count

RFS1 RCVSTS, RCVCNT [11:8]–Receive Status & Receive Msg Byte Count MSBs

80

OFLO

CLSN

FRAM

FCS

Receive FIFO Overflow

Collision during reception

Framing Error

40

20

10

FCS (CRC) error

0F

RCVCNT [11:8] 4 MSBs of Receive Msg. Byte Count

Runt Packet Count (since last successful reception)

Receive Collision Count (since last successful

reception)

RFS2 RNTPC [7:0]

RFS3 RCVCC [7:0]

7

FIFOFC

FIFO Frame Count

RO

F0

0F

RCVFC

XMTFC

Receive Frame Count–# of RCV frames in FIFO

Transmit Frame Count–# of XMT frames in FIFO

76

Addr Mnemonic

Contents

R/W

8

IR

Interrupt Register

RO

80

40

20

10

08

04

02

01

JAB

Jabber Error–Excessive transmit during (20–150ms)

Babble Errorꢀ 1518 bytes transmitted

BABL

CERR

Collision Error–No SQE Test Message

RCVCCO

RNTPCO

MPCO

RCVINT

XMTINT

Receive Collision Count Overflow–Red Add 27 overflow

Runt Packet Count Overflow–Reg Addr 26 overflow

Missed Packet Count Overflow–Reg Addr 24 overflow

Receive Interrupt–Host has read last byte of packet

Transmit Interrupt–Transmission is complete

9

IMR

Interrupt Mask Register

80

40

20

10

08

04

02

01

JABM

Jabber Error Mask

BABLM

Babble Error Mask

CERRM

Collision Error Mask

R/W

RCVCCOM

RNTPCOM

MPCOM

RCVINTM

XMTINTM

Receive Collision Count Overflow Mask

Runt Packet Count Overflow Mask

Missed Packet Count Overflow Mask

Receive Interrupt Mask

Transmit Interrupt Mask

10

11

PR

Poll Register

RO

80

40

20

XMTSV

Transmit Status Valid

TDTREQ

RDTREQ

Transmit Data Transfer Request

Receive Data Transfer Request

BIUCC

Bus Interface Unit Configuration Control

80

40

30

–

BSWP

Byte Swap

XMTSP–Transmit Start Point (2 bits)

00

Transmit after 4 bytes have been loaded

R/W

01

Transmit after 16 bytes have been loaded

Transmit after 64 bytes have been loaded

Transmit after 112 bytes have been loaded

Software Reset

10

11

01

SWRST

77

Programmer’s Register Model (continued)

Addr Mnemonic

Contents

R/W

FIFO Configuration Control

12

FIFOCC

C0

XMTFW

Transmit FIFO Watermark (2 bits)

Assert TDTREQ after 8 write cycles can be made

Assert TDTREQ after 16 write cycles can be made

Assert TDTREQ after 32 write cycles can be made

XX

00

01

10

11

30

RCVFW

00

Receive FIFO Watermark (2 bits)

Assert RDTREQ after 16 bytes are present

Assert RDTREQ after 32 bytes are present

Assert RDTREQ after 64 bytes are present

XX

R/W

01

10

11

08

04

XMTFWU

RCVFWU

Transmit FIFO Watermark Update–loads XMTFW bits

Receive FIFO Watermark Update–loads

RCVFW bits

02

01

XMBRST

Select Transmit Burst mode

RCVBRST

Select Receive Burst mode

13

MACCC

Media Access Control (MAC) Configuration Control

80

40

20

10

08

04

02

01

PROM

DXMT2PD

EMBA

Promiscuous mode

Disable Transmit Two Part Deferral

Enable Modified Back-off Algorithm

–

R/W

DRCVPA

DRCVBC

ENXMT

ENRCV

Disable Receive Physical Address

Disable Receive Broadcast

Enable Transmit

Enable Receive

14

PLSCC

Physical Layer Signalling (PLS) Configuration Control

08

06

XMTSEL

Transmit Mode Select: 1ꢀ DO± =1 during IDLE

PORTSEL [1:0]–Port Select (2 bits)

00

AUI selected

01

10

10BASE-T selected

DAI port selected

GPSI selected

Enable Status

R/W

11

01

ENPLSIO

78

Programmer’s Register Model (continued)

Addr Mnemonic

Contents

R/W

15

PHYCC

R/W

Physical Layer (PHY) Configuration Control

80

40

20

10

08

04

LNKFL

DLNKTST

REVPOL

DAPC

LRT

ASEL

Link Fail–Reports 10BASE-T receive inactivity

Disable Link Test–Force 10BASE–T port into Link Pass

Reversed Polarity–Reports 10BASE-T receiver wiring error

Disable Auto Polarity Correction–Detection remains active

Low Receive Threshold–Extended distance capability

Auto Select–Select 10BASE-T port when active, otherwise

AUI

02

01

RWAKE

AWAKE

Remote Wake–10BASE-T, AUI and EADI features active during

sleep

Auto Wake–10BASE-T receive and LNKST active during sleep

16

17

18

CHIPID

IAC

Chip Identification Register LSB–CHIPID [7:0]

Chip Identification Register MSB–CHIPID [15:8]

Internal Address Configuration

RO

80

40

20

10

08

04

02

01

ADDRCHG Address Change–Write to PHYADDR or LOGADDR after ENRCV

–

R/W

–

PHYADDR Reset Physical Address pointer

LOGADDR Reset Logical Address pointer

–

19

20

–

Reserved

R/W as 0

LADRF

Logical Address Filter–8 bytes–8 reads or writes–LS Byte first

Physical 6 bytes–6 reads or writes–LS Byte

first

21

PADR

R/W as 0

22

23

24

25

26

27

28

–

Reserved

R/W as 0

Reserved

MPC

–

Missed Packet Counter–Number of receive packets missed

Reserved

RNTPC

Runt Packet Count–Number of runt packets addressed to this node

RCVCC Receive Collision Count–Number of receive collision frames on network

Reserved

–

79

Missing Table Title?

Addr Mnemonic

Contents

R/W

29

UTR

User Test Register

80

40

20

10

08

06

RTRE

RTRD

RPA

FCOLL

RCVFCSE

LOOP

00

Reserved Test Register Enable–must be 0

Reserved Test Register Disable

Runt Packet Accept

R/W

Force Collision

Receive FCS Enable

Loopback control (2 bits)

No loopback

01

External loopback

10

Internal loopback, excludes MENDEC

Internal loopback, includes MENDEC

–

11

01

R/W

30

31

–

Reserved

R/W as 0

SYSTEM APPLICATIONS

Host System Examples

Motherboard DMA Controller

The 8237 and the MACE device run synchronous to

the same SCLK. The 8237 is programmed to execute

a transfer in three clock cycles This requires an extra

wait state in the MACE device during FIFO accesses.

A system not using the same configuration as in the

IBM PC can minimize the bus bandwidth required by

the MACE device by programming the DMA controller

in the compressed timing mode.

The block diagram shows the MACE device interfacing

to a 8237 type DMA controller. Two external latches are

used to provide a 24 bit address capability. The first

latch stores the address bits A [15:8], which the 8237

will output on the data line DB [7:0], while the signal

ADSTB is active. The second latch is used as a page

register. It extends the addressing capability of the

8237 from 16–bit to 24–bit. This latch must be pro-

grammed by the system using an I/0 command to gen-

erate the signal LATCHHIGHADR.

Care must be taken with respect to the number of

transfers within a burst. The 8237 will drive the signal

EOP low every time the internal counter reaches the

zero. The MACE device however only expects EOF as-

serted on the last byte/word of a packet. This means,

that the word counter of the 8237 should be initially

loaded with the number of bytes/words in the whole

packet. If the application requires that the packet will be

constructed from several buffers at transmit time, some

extra logic is required to suppress the assertion of EOF

at the end of all but the last buffer transferred by the

DMA controller. Also note that the DMA controller can

only handle either bytes or words at any time. It re-

quires special handling if a packet is transferred to the

MACE device Transmit FIFO in word quantities and it

ends in an odd byte.

The MACE device uses two of the four DMA channels.

One is dedicated to fill the Transmit FIFO and the other

to empty the Receive FIFO. Both DMA channels

should be programmed in the following mode:

— Command Register:

Memory to memory disabled

DREQ sense active high

DACK sense active low

Normal timing

Late Write

Note:

The 8237 requires an extra clock cycle to update the

external address latch every 256 transfer cycles. This

example assumes that an update of the external

address latch occurs only at the beginning of the

block transfer.

This is the same configuration as used in the IBM PC.

80

VDD

CLK

SCLK

DREQ0

DREQ1

EOP

SCLK

RDTREQ

TDTREQ

EOF

DACK0

DACK1

FDS

8237

Am79C940

R/W

ADSTB

DB[7:0]

A[7:0]

CS

TC

DBUS[15:0]

ADD[4:0]

IOW

CSMACE

D[7:0]

Q[7:0]

’373

C

CC

D[7:0]

Q[7:0]

’373

C

CC

LATCHHIGHADR

D[15:0]

A[23:0]

16235D-11

System Interface - Motherboard DMA Example

81

PC/AT Ethernet Adapter Card

SA19-SA0

Remote

Boot

PROM

IEEE

Address

PROM

AUI

DB15

RJ45

I

S

A

SD7-SD0

D7-D0

Am79C940

TP

B

U

S

SD15-SD8

D15-D8

GPSI/DAI

Header

CAM

16235D-12

System Interface - Simple PC/AT Ethernet Adapter Card Example

82

The address matching, and the support logic neces-

sary to capture and present the relevant data to the ex-

ternal table of address is application specific. Note that

since the entire 802.3 packet after SFD is made avail-

able, recognition is not limited to the destination ad-

dress and/or type fields (Ethernet only).

Inter-networking protocol recognition can be performed

on specific header or LLC information fields.

NETWORK INTERFACES

External Address Detection Interface

(EADI)

The External Address Detection Interface can be used

to implement alternative address recognition schemes

outside the MACE device, to complement the physical,

logical and promiscuous detection supported internally.

CAM

Programming

Interface

EADI

Pins

74LS595

74LS245

SRD

SER

A8-A1

Databus

SRDCLK

SRCK

RCK

SF/BD

EAM/R

Q

H’

Q

B8-B1

H-A

74LS595

74LS245

SER

A8-A1

Databus

SRCK

RCK

Q

H’

B8-B1

Q

H-A

Logic

Block

D15-D0

MTCH

Am99C10

16235D-13

EADI Feature - Simple External CAM Interface

83

Attachment Unit Interface (AUI)

The AUI can drive up to 50 m of standard drop cable to

allow the transceiver to be remotely located, as is typi-

cally the case in IEEE 803.3 10BASE5 or thick Ether-

net® installations. For a locally mounted transceiver,

such as 802.3 10BASE2 or Cheapernet interface, the

isolation transformer requirements between the trans-

ceiver and the MACE device can be reduced.

When used with the Am79C98 TPEX (Twisted Pair

Ethernet Transceiver), the isolation requirements of the

AUI are completely removed providing that the trans-

ceiver is mounted locally. For remote location of the

TPEX via an AUI drop cable, the isolation requirement

is necessary to meet IEEE 802.3 specifications for fault

tolerance and recovery.

Ethernet

Coax

MAU

AUI

DTE

Cable

10BASE5/Ethernet

Am7996

Tap

Transceiver

CPU

Memory

Am79C940

Power

Supply

Local Bus

16235D-14

AUI-10BASE5/Ethernet Example

10BASE2/Cheapernet

Am7996

Transceiver

System

CPU

Local

Memory

RG58

BNC “T”

Am79C940

Cheapernet

Coax

Power

Supply

DMA

Engine

I/O Bus

16235D-15

AUI-10BASE2/Cheapernet Example

84

10BASE-T/Twisted-Pair Ethernet

RJ45

Other Slave

I/O Device(s)

i.e. SCSI

System

CPU

Am79C9416

Am79C940

MACE

Unshielded

Twisted-Pair

I/O

Processor

Slave Peripheral Bus

16235D-16

10BASE-T/Unshielded Twisted-Pair Interface

85

ANLG +5 V

0.1 µF

Filter &

Transformer

Module

ANLG GND

AVDD AVSS

RJ45

Connector

61.9 Ω

TXD+

TXP+

TXD-

TXP-

RXD+

RXD-

422 Ω

61.9 Ω

422 Ω

1:1

TD+

TD-

1

2

XMT

Filter

1.21KΩ

Note 2

Note 1

1:1

RD+ 3

RD- 6

RCV

Filter

100Ω

DGTL +5 V

LINK OK

LNKST

RXPOL

RX POL OK

Am79C940

Active Low

Active High

Note 4

DXCVR

Optional

Disable

10BASE2 DC/DC

Convertor

Pulse

Transformer

10BASE2 MAU

DO+

DO-

DI+

DI-

Note 3

Am7996

COAX

TAP

(BNC)

CI+

CI-

See Am7996 Data Sheet

for component and

implementation details

40.2Ω

40.2 Ω

0.1 µF

16235D-17

Optional

ANLG GND

Notes:

1. Compatible filter modules, with a brief description of package type and features are included in the following section.

2. The resistor values are recommended for general purpose use and should allow compliance to the 10BASE-T specification for template

fit and jitter performance. However, the overall performance of the transmitter is also affected by the transmit filter configuration. All

resistors are ± 1%.

3. Compatible AUI transformer modules, with a brief description of package type and features are included in the following section.

4. Active High indicates the external convertor should be turned off. The Disable Transceiver (DXCVR) output is used to indicate the active

network port. A high level indicates the 10BASE-T port is selected and the AUI port is disabled. A low level indicates the AUI port is

selected and the Twisted Pair interface is disabled.

Active Low: indicates the external converter should be turned off. The LNKST output can be used to indicate the active network

port. A high level indicates the 10BASE-T port is in the Link Fail state, and the external convertor should be on. A low level indicates the

10BASE-T port is in the Link Pass state, and the external convertor should be off.

10BASE–T and 10BASE2 Configuration of Am79C940

86

ANLG +5 V

0.1µF

Filter &

Transformer

Module

ANLG GND

AVDD AVSS

RJ45

Connector

61.9Ω

TXD+

TXP+

TXD-

TXP-

RXD+

RXD-

422Ω

61.9Ω

422Ω

1:1

1

2

TD+

TD-

XMT

Filter

1.21KΩ

Note 2

Note 1

1:1

3

6

RD+

RD-

RCV

Filter

100Ω

DGTL +5 V

LINK OK

LNKST

RXPOL

RX POL OK

Am79C940

DGTL GND

Pulse

AUI

Connector

Transformer

DO+

DO–

DI+

DI-

3

10

5

Note 3

12

2

CI+

CI-

9

40.2Ω

0.1µF

Optional

0.1µF

16235D-18

ANLG GND

Notes:

1. Compatible filter modules, with a brief description of package type and features are included in the following sec-

tion.

2. The resistor values are recommended for general purpose use and should allow compliance to the 10BASE-T

specification for template fit and jitter performance. However, the overall performance of the transmitter is also

affected by the transmit filter configuration. All resistors are ± 1%.

3. Compatible AUI transformer modules, with a brief description of package type and features are included in the

following section.

10BASE-T and AUI Implementation of Am79C940

87

MACE Compatible 10BASE-T Filters

and Transformers

The table below provides a sample list of MACE com-

patible 10BASE-T filter and transformer modules

available from various vendors. Contact the respective

manufacturer for a complete and updated listing of

components.

Filters

and

Filters

Transformers

Resistors

Transformers Transformers

Manufacturer

Bel Fuse

Part #

Package

Transformers

and Choke

Dual Chokes

A556-2006-DE 16–pin 0.3 DIL

0556-2006-00 14–pin SIP

0556-2006-01 14–pin SIP

0556-6392-00 16–pin 0.5 DIL

ꢀ

Bel Fuse

ꢀ

Bel Fuse

Halo Electronics

PCA Electronics

FD02-101G

FD12-101G

FD22-101G

EPA1990A

EPA2013D

EPA2162

16–pin 0.3 DIL

16–pin 0.3 SIP

16–pin 0.3 DIL

16–pin 0.3 SIL

16–pin 0.3 DIL

12–pin 0.5 SMT

16–pin 0.3 DIL

ꢀ

Pulse Engineering PE-65421

Pulse Engineering PE-65434

Pulse Engineering PE-65445

Pulse Engineering PE-65467

ꢀ

Valor Electronics

PT3877

FL1043

ꢀ

MACE Compatible AUI Isolation

Transformers

The table below provides a sample list of MACE com-

patible AUI isolation transformers available from

vendors. Contact the respective manufacturer for a

complete and updated listing of components

.

Manufacturer

Bel Fuse

Part #

A553-0506-AB

S553-0756-AE

TD01-0756K

TG01-0756W

EP9531-4

PE64106

Package

Description

16–pin 0.3 DIL

16–pin 0.3 SMD

16–pin 0.3 DIL

16–pin 0.3 SMD

16–pin 0.3 DIL

16–pin 0.3 SMT

16–pin 0.3 DIL

16–pin 0.3 SMD

50 µH

75 µH

50 µH

75 µH

Bel Fuse

Halo Electronics

PCA Electronics

Pulse Engineering

Valor Electronics

PE65723

LT6032

ST7032

88

MACE Compatible DC/DC Converters

The table below provides a sample list of MACE com-

patible DC/DC converters available from various ven-

dors. Contact the respective manufacturer for a

complete and updated listing of components.

Manufacturer

Halo Electronics

PCA Electronics

Valor Electronics

Part #

DCU0-0509D

DCU0-0509E

EPC1007P

EPC1054P

EPC1078

Package

24–pin DIP

Voltage

5/-9

Remote On/Off

No

Yes

No

5/-9

Yes

No

5/-9

PM7202

5/-9

PM7222

5/-9

Yes

MANUFACTURER CONTACT

INFORMATION

Contact the following companies for further information

on their products.

Company

US. and Domestic

Asia

Europe

Phone: (201) 432-0463

852-328-5515

852-352-3706

33-1-69410402

33-1-69413320

Bel Fuse

FAX:

Phone: (415) 969-7313

FAX: (415) 367-7158

Phone: (818) 892-0761

FAX: (818) 894-5791

Phone: (619) 674-8100

FAX: (619) 675-8262

Phone: (619) 537-2500

FAX: (619) 537-2525

(201) 432-9542

65-285-1566

65-284-9466

Halo Electronics

PCA Electronics

852-553-0165

852-873-1550

33-1-44894800

33-1-42051579

(HPC in Hong Kong)

852-425-1651

852-480-5974

353-093-24107

353-093-24459

Pulse Engineering

Valor Electronics

852-513-8210

852-513-8214

49-89-6923122

49-89-6926542

89

ABSOLUTE MAXIMUM RATINGS

OPERATING RANGES

Storage Temperature . . . . . . . . . . . . -65°C to +150°C

Commercial (C) Devices

Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . .

Under Bias . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Ambient Temperature (T_A) . . . . . . . . . . .0°C to +70°C

Industrial (I) Devices

Supply Voltage to AVSS

or DVss (AVDD, DVDD). . . . . . . . . . .-0.3 V to +6.0 V

Ambient Temperature (T_A) . . . . . . . . .–40°C to +85°C

V

_CCSupply Voltages

Stresses above those listed under Absolute Maximum Rat-

ings may cause permanent device failure. Functionality at or

above these limits is not implied. Exposure to Absolute Max-

imum Ratings for extended periods may affect device reliabil-

ity. Programming conditions may differ.

. . . . . . . . . . . . . . . . . . . . . . (AVDD, DVDD) 5 V ±5%

All inputs within the range: . . AVDD – 0.5 V ≤ Vin ≤

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . AVSS + 0.5 V, or

. . . . . . . . . . . . . . . . . . . . . . . . . DV_DD– 0.5 V ≤ Vin ≤

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DV_SS+ 0.5 V

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

DC CHARACTERISTICS (Unless otherwise noted, parametric values are the same

between Commercial devices and Industrial devices.)

Parameter

Symbol

Parameter Description

Input LOW Voltage

Test Conditions

Min

Max

Unit

V

V_IL

0.8

V_IH

Input HIGH Voltage

2.0

V

XTAL1 Input LOW Voltage

(External Clock Signal)

XTAL1 Input HIGH Voltage

(External Clock Signal)

Output LOW Voltage

V_SS= 0.0 V

V_ILX

V_IHX

–0.5

0.8

V

V_SS= 0.0 V

V_DD–

0.8

V_DD+

0.5

V_OL

V_OH

I_OL= 3.2 mA

0.45

V

Output HIGH Voltage

I_OH= -0.4 mA (Note 1)

2.4

V

_DD= 5 V, V_IN= 0 V

(Note 2)

_DD= 5 V, V_IN= 0 V

(Note 2)

_DD= 5 V, V_IN= 2.7 V

I_IL1

I_IL2

Input Leakage Current

–10

10

µA

mV

V

–200

200

V

I_IH

–100

+500

(Note 3)

Input Current at DI+

and DI–

I_IAXD

I_IAXC

I_ILXN

I_IHXN

I_ILXS

I_IHXS

I_OZ

–1 V < V_IN< AV_DD+ 0.5 V

–500

Input Current at CI+

and CI–

–1 V < V_IN< AV_DD+ 0.5 V

XTAL1 Input LOW Current

during normal operation

XTAL1 Input HIGH Current

during normal operation

XTAL1 Input LOW Current

during Sleep

V_IN= 0 V

–92

(Note 9)

SLEEP = HIGH

V_IN= 5.5 V

92

(Note 10)

SLEEP = HIGH

V_IN= 0 V

<10

410

10

SLEEP = LOW

V_IN= 5.5 V

XTAL1 Input HIGH Current

during Sleep

SLEEP = LOW

0.4 V < V_OUT< V_DD

(Note 4)

Output Leakage Current

–10

630

–40

Differential Output Voltage

|(DO+)–(DO–)|

V_AOD

V_AODOFF

R_L= 78 Ω

1200

+40

Transmit Differential Output

Idle Voltage

R_L= 78 Ω (Note 5)

90

DC CHARACTERISTICS (Continued)

Parameter

Symbol

Parameter Description

Transmit Differential

Output Idle Current

DO± Common Mode

Output Voltage

Test Conditions

R_L= 78 Ω

Min

Max

Unit

I_AODOFF

–1

+1

mA

V_AOCM

R_L= 78 Ω

2.5

–25

AVDD

25

V

DO± Differential Output

Voltage Imbalance

V_OD

V_ATH

V_ASQ

I

R_L= 78 Ω (Note 6)

mV

V

Receive Data Differential

Input Threshold

–35

35

DI± and CI± Differential

Input Threshold Squelch

DI± and CI± Differential

Mode Input Voltage Range

DI± and CI± Input Bias

Voltage

–160

–275

1.5

V_IRDVD

V_ICM

I_IN= 0 mA

(Note 5)

AV_DD–3.0

AV_DD–0.8

–100

V

V_OPD

mV

DI± Undershoot Voltage at Zero

Differential on Transmit Return

to Zero (ETD)

SCLK = 25 MHz

I_DD

Power Supply Current

75

100

10

mA

µA

XTAL1 = 20 MHz

SLEEP Asserted, AWAKE = 0

RWAKE = 1 (Note 7)

I_DDSLEEP

SLEEP Asserted, AWAKE = 1

RWAKE = 0 (Note 7)

mA

SLEEP Asserted, AWAKE = 0

RWAKE = 1 (Note 7)

20

Twisted Pair Interface

I_IRXD

Input Current at RXD±

AV_SS< V_IN< AV_DD

(Note 8)

–500

500

µA

RXD± Differential Input

Resistance

R_RXD

10

KΩ

RXD±, RXD– Open Circuit

Input Voltage (Bias)

Differential Mode Input

Voltage Range (RXD±)

RXD Positive Squelch

Threshold (Peak)

V_TIVB

V_TIDV

I_IN= 0 mA

AV_DD–3.0

–3.1

300

AV_DD–1.5

+3.1

V

AV_DD= +5V

V

Sinusoid

V_TSQ+

V_TSQ–

V_THS+

V_THS–

V_LTSQ+

V_LTSQ–

V_LTHS+

520

mV

5 MHz ≤ f ≤10 MHz

Sinusoid

RXD Negative Squelch

Threshold (Peak)

–520

150

–300

293

5 MHz ≤ f ≤10 MHz

Sinusoid

RXD Post-Squelch

Positive Threshold (Peak)

RXD Post-Squelch

5 MHz ≤ f ≤10 MHz

Sinusoid

–293

180

–150

312

Negative Threshold) (Peak)

RXD Positive Squelch

Threshold (Peak)

5 MHz ≤ f ≤10 MHz

LRT = LOW

RXD Negative Squelch

Threshold (Peak)

–312

90

–180

156

RXD Post-Squelch Positive

Threshold (Peak)

91

DC CHARACTERISTICS (Continued)

Parameter

Symbol

V_LTHS–

V_RXDTH

V_TXH

Parameter Description

RXD Post-Squelch

Test Conditions

LRT = LOW

Min

–156

Max

–90

Unit

mV

V

Negative Threshold (Peak)

RXD Switching Threshold

(Note 4)

–35

35

TXD± and TXD± Output

DV_SS= 0V

DV_DD–0.6

DV_DD

HIGH Voltage

TXD± and TXD± Output

V_TXL

DV_DD= +5V

DV_SS

DV_SS+ 0.6

V

LOW Voltage

TXD± and TXD± Differential

Output Voltage Imbalance

V_TXI

V_TXOFF

R_TX

–40

+40

40

mV

Ω

TXD± and TXD± Idle Output

Voltage

DV_DD= +5V

(Note 8)

TXD± Differential Driver Output

Impedance

40

TXD± Differential Driver Output

Impedance

(Note 8)

80

Ω

Notes:

1. V_OHdoes not apply to open-drain output pins.

2. I_IL1and I_IL2applies to all input only pins except DI±, CI±, and XTAL1.

I_IL1= ADD4–0, BE1–0, CS, EAM/R, FDS, RESET, RXDAT, R/W, SCLK.

I_IL2= TC, TDI, TCK, TMS.

3. Specified for input only pins with internal pull-ups: TC, TDI, TCK, TMS.

4. I_OZapplies to all three-state output pins and bi-directional pins.

5. Test not implemented to data sheet specification.

6. Tested, but to values in excess of limits. Test accuracy not sufficient to allow screening guard bands.

7. During the activation of SLEEP:

–The following pins are placed in a high impedance state: SRD, SF/BD, TXDAT, DXCVR, DTV, TDTREQ, RDTREQ, NTR

and TDO.

–The following I/O pins are placed in a high impedance mode and have their internal TTL level translators disabled:

DBUS15–0, EOF, SRDCLK, RXCRS, RXDAT, CLSN, TXEN, STDCLK and TXDAT+.

–The following input pin has its internal pull-up and TTL level translator disabled: TC.

–The following input pins have their internal TTL level translators disabled and do not have internal pull-ups: CS, FDS,

R/W, ADD4-0, SCLK, BE0, BE1 and EAM/R.

–The following pins are pulled low: XTAL1 (XTAL2 feedback is cut off from XTAL1), TXD+, TXD–, TXP+, TXP–, DO+

and DO.

–The following pins have their input voltage bias disabled: DI+, DI, CI+ and CI.

–AWAKE and RWAKE are reset to zero. I_DDSLEEP,with either AWAKE set or RWAKE set, will be much higher and its

value remains to be determined.

8. Parameter not tested.

9. For industrial temperature version, Max value is –150 µA.

10. For industrial temperature version, Max value is +150 µA.

92

AC CHARACTERISTICS (Unless otherwise noted, parametric values are the same

between Commercial devices and Industrial devices.)

Parameter

No.

Symbol

Parameter Description

Test Conditions

Min (ns)

Max (ns)

Clock and Reset Timing

1

2

3

4

5

6

7

t_SCLK

t_SCLKL

t_SCLKH

t_SCLKR

t_SCLKF

t_RST

SCLK period

40

1000

SCLK LOW pulse width

SCLK HIGH pulse width

SCLK rise time

0.4*t_SCLK

0.6*t_SCLK

5

SCLK fall time

RESET pulse width

15*t_SCLK

99

t_BT

Network Bit Time (BT)=2*tX1 or tSTDC

101

Internal MENDEC Clock Timing

9

t_X1

XTAL1 period

49.995

20

50.005

11

12

13

14

t_X1H

t_X1L

t_X1R

t_X1F

XTAL1 HIGH pulse width

XTAL1 LOW pulse width

XTAL1 rise time

20

5

XTAL1 fall time

BIU TIMING (Note 1)

31

32

t_ADDS

t_ADDH

Address valid setup to SCLK↓

Address valid hold after SCLK↓

CS or FDS and TC, BE1–0,

R/W setup to SCLK↓

9

2

1. 33

t_SLVS

t_SLVH

9

2

CS or FDS and TC, BE1–0,

R/W hold after SCLK↓

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

t_DATD

t_DATH

t_DTVD

t_DTVH

t_EOFD

t_EOFH

t_CSIS

Data out valid delay from SCLK↓

Data out valid hold from SCLK↓

DTV valid delay from SCLK↓

DTV valid hold after SCLK↓

C_L= 100 pF (Note 2)

32

6

EOF valid delay from SCLK↓

EOF output valid hold after SCLK↓

CS inactive prior to SCLK↓

6

9

2

t_EOFS

t_EOFH

t_RDTD

t_RDTH

t_TDTD

t_TDTH

t_DATS

t_DATIH

EOF input valid setup to SCLK↓

EOF input valid hold after SCLK↓

RDTREQ valid delay from SCLK↓

RDTREQ input valid hold after SCLK↓

TDTREQ valid delay from SCLK↓

TDTREQ input valid hold after SCLK↓

Data in valid setup to SCLK↓

Data in valid setup after SCLK↓

C_L= 100 pF (Note 2)

32

6

9

2

Data output enable delay from SCLK↓ (Note

3)

50

t_DATE

t_DATD

0

Data output disable delay from SCLK↓ (Note

3, 4)

51

25

Notes:

1. The following BIU timing assumes that EDSEL = 1. Therefore, these parameters are specified with respect to the falling edge

of SCLK (SCLK↓). If EDSEL = 0, the same parameters apply but should be referenced to the rising edge of SCLK ↑).

2. Tested with C_Lset at 100 pF and derated to support the Indicated distributed capacitive Load. See the BIU output valid delay

vs. Load Chart.

3. Guaranteed by design–not tested.

4. t_DATDis defined as the time required for outputs to turn high impedence and is not referred to as output voltage lead.

93

AC CHARACTERISTICS (continued)

Parameter

No.

Symbol

Parameter Description

Test Conditions

Min (ns)

Max (ns)

AUI Timing

53

54

55

56

57

58

t_DOTD

t_DOTR

XTAL1 (externally driven) to DO± ουτπυτ

DO± rise time (10% to 90%)

DO± fall time (10% to 90%)

DO± rise and fall mismatch

DO± End of Transmit Delimiter

DI± pulse width to reject

100

5.0

1

2.5

t_DOTF

t_DOETM

t_DOETD

t_PWRDI

200

375

15

|input| > |_VASQ

|

DI± pulse width to turn on internal DI carrier

sense

59

60

61

t_PWODI

t_PWMDI

t_PWKDI

|input| > |_VASQ

|

45

DI± pulse width to maintain internal DI carrier

sense on

|

136

DI± pulse width to turn internal DI carrier

sense off

|input| > |_VASQ

200

62

63

t_PWRCI

t_PWOCI

CI± pulse width to reject

|

10

90

CI± pulse width to turn on internal SQE sense |input| > |_VASQ

26

CI± pulse width to maintain internal SQE

|input| > |_VASQ

64

t_PWMCI

|

sense on

65

66

67

79

80

t_PWKCI

t_SQED

t_SQEL

t_CLSHI

t_TXH

CI± pulse width to turn internal SQE sense off |input| > |_VASQ

|

160

CI± SQE Test delay from O± inactive

CI± SQE Test length

|input| > |_VASQ

CLSN high time

t_STDC+ 30

32*t_STDC

TXEN or DO± hold time from CLSN↑

|input| > |_VASQ

|

96*t_STDC

DAI Port Timing

70

72

80

t_TXEND

t_TXDD

t_TXH

STDCLK↑ delay to TXEN↓

C_L= 50 pF

70

STDCLK↑ delay to TXDAT± change

TXEN or TXDAT± hold time from CLSN↑

32*t_STDC

96*t_STDC

Mismatch in STDCLK ≠ to TXEN↓ and

TXDAT± change

95

t_DOTF

15

96

97

t_TXDTR

t_TXDTF

TXDAT± rise time

See Note 1

5

TXDAT± fall time

5

98

t_TXDTM

TXDAT± rise and fall mismatch

TXEN End of Transmit Delimiter

First RXDAT↓ delay to RXCRS↑

Last RXDAT ≠ delay to RXCRS↓

RXCRS↑ delay to CLSN↑ (TXEN = 0)

1

99

t_TXENETD

t_FRXDD

250

350

100

120

100

101

102

t_LRXDD

t_CRSCLSD

94

AC CHARACTERISTICS (continued)

Parameter

No.

Symbol

Parameter Description

Test Conditions

Min (ns)

Max (ns)

GPSI Clock Timing

17

t_STDC

STDCLK period

99

45

101

18

t_STDCL

t_STDCH

t_STDCR

t_STDCF

t_SRDC

STDCLK low pulse width

STDCLK high pulse width

STDCLK rise time

See Note 1

19

20

See Note 1

5

21

STDCLK fall time

22

SRDCLK period

85

38

115

23

t_SRDCH

t_SRDCL

t_SRDCR

t_SRDCF

SRDCLK HIGH pulse width

SRDCLK LOW pulse width

SRDCLK rise time

24

25

See Note 1

5

26

SRDCLK fall time

GPSI Timing

70

71

72

73

74

75

t_TXEND

t_TXENH

t_TXDD

t_TXDH

t_RXDR

t_RXDF

STDCLK↑ delay to TXEN↑

(C_L= 50 pF)

70

TXEN hold time from STDCLK↑

5

STDCLK↑ delay to TXDAT+ change (C_L= 50 pF)

TXDAT+ hold time from STDCLK↑ (C_L= 50 pF)

RXDAT rise time

RXDAT fall time

See Note 1

8

RXDAT hold time (SRDCLK↑ to

RXDAT change)

76

77

t_RXDH

t_RXDS

25

0

RXDAT setup time (RXDAT stable

to SRDCLK↑)

78

79

t_CRSL

t_CLSHI

RXCRS low time

CLSN high time

t_STDC+ 20

t_STDC+ 30

TXEN or TXDAT± hold time from

CLSN↑

80

t_TXH

32*t_STDC

0

96*t_STDC

81

t_CRSH

RXCRS hold time from SRDCLK↑

EADI Feature Timing

85

86

t_DSFBDR

t_DSFBDF

SRDCLK↓ delay to SF/BD↑

20

EAM/R invalid setup prior to

SRDCLK↓ after SFD

87

t_EAMRIS

–150

EAM setup to SRDCLK↓ at bit 6 of

Source Address byte 1 (match

packet)

88

t_EAMS

0

89

90

t

_EAMRL

EAM/R low time

200

100

SF/BD high hold from last

SRDCLK↓

t_SFBDHIH

EAR setup SRDCLK↓ at bit 6 of

message byte 64

91

t_EARS

0

(reject normal packet)

Note:

1. Not tested but data available upon request.

95

AC CHARACTERISTICS (continued)

Parameter

No.

Parameter Description

Test Conditions

Min

Max

Symbol

IEEE 1149.1 Timing

109

t_TCLK

TCK Period, 50% duty cycle (+5%)

100

110

111

112

113

114

115

t_su1

t_su2

t_hd1

t_hd2

t_d1

TMS setup to TCK↑

8

5

TDI setup to TCK↑

TMS hold time from TCK↑

TDI hold time from TCK↑

TCK↓ delay to TDO

5

10

30

35

t_d2

TCK↓ delay to SYSTEM OUTPUT

10BASE–T Transmit Timing

Min

Max

350

5.5

1

125

126

127

128

129

130

131

132

133

134

135

136

t_TETD

t_TR

Transmit Start of Idle

250

Transmitter Rise Time

(10% to 90%)

(90% to 10%)

t_TF

Transmitter Fall Time

t_TM

Transmitter Rise and Fall Time Mismatch

XMT# Asserted Delay

t_XMTON

t_XMTOFF

t_PERLP

t_PWLP

t_PWPLP

t_JA

100

TBD

24

XMT# De-asserted Delay

Idle Signal Period

TBD

8

Idle Link Pulse Width

(Note 1)

75

120

55

Predistortion Idle Link Pulse Width

Transmit Jabber Activation Time

Transmit Jabber Reset Time

45

20

150

750

t_JR

250

1.0

t_JREC

Transmit Jabber Recovery Time(Minimum

TimeGapBetweenTransmittedPacketsto

Prevent Jabber Activation)

10BASE–T Receive Timing

RXD Pulse Width Not to Turn Off Internal VIN > VTHS

140

141

t_PWNRD

136

200

–

Carrier Sense

(min)

RXD Pulse Width to Turn Off VIN> VTHS

(min)

t_PWROFF

142

143

144

t_RETD

t_RCVON

t_RCVOFF

Receive Start of Idle

200

t_RON– 50

TBD

RCV# Asserted Delay

RCV# De-asserted Delay

t_RON– 100

TBD

Note:

1. Not tested but data available upon request.

96

BIU Output Valid Delay vs. Load Chart

nom+4

nom

BIU Output Valid Delay

from SCLK↓

(ns)

nom-4

nom-8

50

75

100

125

150

C (pF)

L

16235D-19

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Must be

Steady

Will be

Steady

May

Change

from H to L

Will be

Changing

from H to L

May

Will be

Change

from L to H

Changing

from L to H

Don’t Care,

Any Change

Permitted

Changing,

State

Unknown

Does Not

Apply

Center

Line is High-

Impedance

“Off” State

KS000010

97

SWITCHING TEST CIRCUITS

I

OL

Sense Point

V

THRESHOLD

C

L

I

OH

16235D-20

Normal and Three-State Outputs

AV

DD

52.3 Ω

DO+

DO-

Test Point

154 Ω

100 pF

AV

SS

16235D-21

AUI DO Switching Test Circuit

DV

DD

294 Ω

TXD+

TXD-

Test Point

294 Ω

100 pF

Includes Test

Jig Capacitance

DV

SS

16235D-22

TXD Switching Test Circuit

98

DV

DD

715 Ω

TXP+

TXP-

Test Point

715 Ω

100 pF

Includes Test

Jig Capacitance

DV

SS

16235D-23

TXP Outputs Test Circuit

AC WAVEFORMS

1

2

3

SCLK

4

5

6

RESET

9

11

12

XTAL1

14

13

Clock and Reset Timing

16235D-24

99

AC WAVEFORMS

SCLK

(EDSEL = 0)

TL TH S0 S1 S2 S3 S0 S1 S2 S3

S0 S1 S2 S3 S0

SCLK

(EDSEL = 1)

TL TH S0 S1 S2 S3 S0 S1 S2 S3

31

ADD[4:0]

R/W

32

34

33

41

CS or FDS

DBUS[15:0]

51

35

36

50

Word N

Last Byte

or Word

Word N+1

38

40

DTV

EOF

37

39

BE0-1

TC = 1

34

16235D-25

Host System Interface—2-Cycle Receive FIFO/Register Read Timing

100

AC WAVEFORMS

SCLK

(EDSEL = 0)

TL TH S0 S1 W0 W1 S2 S3 S0 S1 W0 W1 S2 S3 S0 S1 W0 W1 S2 S3 S0

SCLK

(EDSEL = 1)

TL TH S0 S1 W0 W1 S2 S3 S0 S1 W0 W1 S2 S3 S0 S1 W0 W1 S2 S3 S0

31

ADD[4:0]

R/W

32

33

34

41

CS or FDS

51

35

50

Last Byte

or Word

DBUS[15:0]

DTV

Word N

36

Word N+1

38

37

40

EOF

39

BE0-1

TC= 0

34

16235D-26

Host System Interface—3-Cycle Receive FIFO/Register Read Timing

101

AC WAVEFORMS

SCLK

(EDSEL = 0)

TL TH S0 S1 S2 S3 S0 S1 S2 S3

S0 S1 S2 S3 S0

SCLK

(EDSEL = 1)

TL TH S0 S1 S2 S3 S0 S1 S2 S3

31

ADD4–0

32

R/W

33

41

34

orFDS

CS

48

DBUS15–0

DTV

Word N

49

Last Byte

or Word

Word N+1

38

37

43

EOF

42

BE0-1

TC = 1

34

16235D-27

Host System Interface—2-Cycle Transmit FIFO/Register Write Timing

102

AC WAVEFORMS

SCLK

TL TH S0 S1 W0 W1 S2 S3 S0 S1 W0 W1 S2 S3 S0 S1 W0 W1 S2 S3 S0

(EDSEL = 0)

SCLK

(EDSEL = 1)

TL TH S0 S1 W0 W1 S2 S3 S0 S1 W0 W1 S2 S3 S0 S1 W0 W1 S2 S3 S0

31

ADD[4:0]

32

R/W

CS

33

34

41

48

DBUS[15:0]

DTV

Word N

49

Last Byte

or Word

Word N+1

38

37

43

34

EOF

42

BE0-1

TC = 0

16235D-28

Host System Interface—3-Cycle Transmit FIFO/Register Write Timing

SCLK

(EDSEL = 0)

S0 S1 S2 S3

S2 S3 S0 S1 S2

S0 S1 S2 S3 S0

SCLK

(EDSEL = 1)

S0 S1 S2 S3

S0 S1 S2 S3 S0

40

EOF

44

39

Note 1

RDTREQ

45

16235D-29

Note: Once the host detects the EOF output active from the MACE device (S2/S3 edge), if no other receive packet exists

in the RCVFIFO which meets the assert conditions for RDTREQ, the MACE device will deassert RDTREQ within 4 SCLK

cycles (S0/S1 edge). This is consistent for both 2 or 3 cycle read operations.

Host System Interface–RDTREQ Read Timing

103

AC WAVEFORMS

SCLK

(EDSEL = 0)

S1 S2 S3 S0 S1 S2 S3

S0 S1 S2 S3 S0 S1 S2 S3 S0

SCLK

(EDSEL = 1)

S0 S1 S2 S3 S0 S1 S2 S3 S0

43

EOF

46

42

TDTREQ

Note 1

47

Note 2

Note 3

Notes:

16235D-30

1. TDTREQ will be asserted for two write cycles (4 SCLK cycles) minimum.

2. TDTREQ will deassert 1 SCLK cycle after EOF is detected (S2/S3 edge).

3. When EOF is written, TDTREQ will go inactive for 1 SCLK cycle minimum.

Host System Interface–TDTREQ Write Timing

XTAL1

9

STDCLK

TXEN

1

TXDAT+

(Note 1)

0

54

55

DO+

DO–

1

DO±

53

16235D-31

Note: TXDAT+ is the internal version of the signal, and is shown for clarification only.

AUI Transmit Timing–Start of Packet

104

XTAL1

STDCLK

TXEN

1

TXDAT+

(Note 1)

0

DO+

DO–

DO±

57

1

0

bit (n–2)

bit (n)

> 200 ns

bit (n–1)

16235D-32

Note: TXDAT+ is the internal version of the signal, and is shown for clarification only.

AUI Transmit Timing–End of Packet (Last Bit = 0)

XTAL1

SRDCLK

TXEN

TXDAT+

1

0

(Note 1)

DO+

DO–

DO±

1

0

57

> 250 ns

bit (n–1)

bit (n–2)

bit (n)

Note: TXDAT+ is the internal version of the signal, and is shown for clarification only.

AUI Transmit Timing–End of Packet (Last Bit = 1)

16235D-33

105

57

40 mV

DO±

0 V

100 mV Max

80 Bit Times Max

16235D-34

AUI Transmit Timing—End Transmit Delimiter (ETD)

Bit Cell 1

1

Bit Cell 2

0

Bit Cell 3

Bit Cell 4

Bit Cell 5

1

0

(Note 1)

59

60

DI±

V

ASQ

BCC

BCB

BCC

BCB

BCC

BCB

BCC

BCB

RXCRS

IVCO_ENABLE

IVCO

SRDCLK

SRD

5 Bit Times Max

(Note 2)

(Note 3)

16235D-35

Notes:

1. Minimum pulse width>45 ns with amplitude >–160 mV.

2. SRD first decoded bit might not be defined until bit time 5.

3. First valid data bit.

4. IVCO and VCO ENABLE are internal signals shown for clarification only.

AUI Receive Timing–Start of Packet

106

Bit Cell (n–1)

Bit Cell (n)

0

1

61

60

DI±

V

ASQ

(Note 2)

BCC

BCB

BCC

BCB

RXCRS

(Note 1)

IVCO

SRDCLK

SRD

bit (n)

bit (n–1)

16235D-36

Notes:

1. RXCRS deasserts in less than 3 bit times after last DI± rising edge.

2. Start of next packet reception (2 bit times).

3. IVCO is an internal signal shown for clarification only.

AUI Receive Timing–End of Packet (Last Bit = 0)

Bit Cell (n)

1

Bit Cell (n–1)

0

DI±

RXCRS

IVCO

61

BCC

BCB

BCC

(Note 1)

SRDCLK

SRD

bit (n)

bit (n–1)

16235D-37

Notes:

1. RXCRS deassets in less than 3 bit times after last DI± rising edge.

2. IVCO is an internal signal shown for clarification only.

AUI Receive Timing–End of Packet (Last Bit = 1)

107

DO±

TXEN

CI+

CI-

80

CLSN

79

16235D-38

AUI Collision Timing

DO±

66

CI+

CI-

67

CLSN = 0

16235D-39

AUI SQE Test Timing

108

STDCLK

TXDAT±

BCB

72

99

97

96

TXDAT+

TXDAT-

TXEN

95

72

16235D-40

DAI Port Transmit Timing

RXDAT

100

101

RXCRS

16235D-41

DAI Port Receive Timing

109

TXDAT+

TXDAT-

TXEN

RXDAT

RXCRS

CLSN

102

79

16235D-42

DAI Port Collision Timing

Destination Address

Byte 2

Destination Address

Byte 1

SRDCLK

SRD

BIT

3

BIT

5

BIT

0

BIT

1

BIT

6

BIT

7

BIT

0

BIT

4

BIT

2

SFD

86

SF/BD

85

Note 1

EAM/R

87

89

NoteF: irstassertionofEAM/Rmustoccurafterbit2/3boundaryofpreamble.

EADI Feature Timing–Start of Address

16235D-43

110

Last Byte of Message

SRDCLK

SRD

90

86

SF/BD

85

EADI Feature–End of Packet Timing

16235D-44

Destination Address

Byte 6

Source Address

Byte 1

Source Address

Byte 2

SRDCLK

SRD

BIT BIT BIT BIT BIT BIT BIT BIT BIT

BIT BIT BIT

5

6

7

0

1

2

3

4

5

6

7

0

86

SF/BD

EAM

85

88

89

16235D-45

EADI Feature-Match Timing

111

Byte 64

Byte 65

Byte 66

(Data Byte 51)

(Data Byte 52)

(Data Byte 53)

RDCLK

SRD

BIT BIT BIT BIT BIT BIT

BIT BIT

BIT

5

BIT BIT BIT

BIT

1

BIT

4

5

6

7

0

1

2

3

6

7

0

85

86

SF/BD

EAR

91

89

16235D-46

EADI Feature Reject Timing

17

19

18

STDCLK

72

73

20

21

TXDAT+

TXEN

70

71

Note 1

RXCRS

16235D-47

Note: During transmit, the RXCRS input must be asserted (high) and remain active-high after TXEN goes active (high). If

RXCRS is deasserted before TXEN is deasserted, LCAR will be reported (Transmit Frame Status) after the transmission is

completed by the MACE device.

GPSI Transmit Timing

112

22

24

23

SRDCLK

RXDAT

RXCRS

26

75

74

25

77

76

81

78

16235D-48

GPSI Receive Timing

STDCLK

TXDAT+

72

70

73

TXEN

CLSN

80

79

16235D-49

GPSI Collision Timing

113

TCK

TMS

tsu1

td1

thd1

tsu2

TDI

thd2

TDO

td2

System Output

16235D-50

IEEE 1149.1 TAP Timing

t

TF

t

TETD

t

XMTOFF

16235D-51

Note:

1. Parameter is internal to the device.

10BASE-T Transmit Timing

114

V

RXD±

TSQ+

TSQ-

t

RCVON

RCVOFF

RXCRS

16235D-52

10BASE-T Receive Timing

TXD±

RXD±

t_COLON

t

COLOFF

CLSN

16235D-53

10BASE-T Collision Timing

115

t

PWPLP

TXD+

TXP+

TXD-

TXP-

t

PERLP

PWLP

16235D-54

10BASE-T Idle Link Test Pulse

V

TSQ+

V

THS+

RXD±

THS-

V

TSQ-

16235D-55

10BASE-T Receive Thresholds (LRT = 0)

V

LTSQ+

V

LTHS+

RXD±

V

LTHS-

V

LTSQ-

16235D-56

10BASE-T Receive Thresholds (LRT = 1)

116

PHYSICAL DIMENSIONS*

PL 084

84-Pin Plastic Leaded Chip Carrier (measured in inches)

.062

.083

1.185

1.195

.042

.056

1.150

1.156

1.090

1.130

1.000

REF

Pin 1 I.D.

1.185

1.195

1.150

1.156

.013

.021

.007

.013

.026

.032

.090

.130

.165

.180

.050 REF

SEATING PLANE

TOP VIEW

SIDE VIEW

117

PHYSICAL DIMENSIONS*

PQR100

100-Pin Plastic Quad Flat Pack; Trimmed and Formed (measured in millimeters)

17.10

17.30

13.90

14.10

12.35

REF

50

30

0.22

0.38

18.85

REF

19.90

20.10

23.00

23.40

0.65

BASIC

Pin 1 I.D.

80

100

TOP VIEW

2.70

2.90

3.35

MAX

0.70

0.90

0.25

MIN

SIDE VIEW

17198A

CG 47

7/14/92 SG

118

PHYSICAL DIMENSIONS

PQR100

100-Pin Plastic Quad Flat Pack with Molded Carrier Ring (measured in millimeters)

35.87

36.13

35.50

35.90

31.37

31.63

27.87

28.13

25.15

25.20

BSC

25.25

22.15

22.25

13.80

14.10

50

30

35.50 27.87 22.15

35.90 28.13 22.25

25.15

25.25

35.87 31.37

36.13 31.63

19.80

20.10

Pin 1 I.D.

100

80

0.22

0.38

.65 NOM

TOP VIEW

.45 Typ

.65 Pitch

2.00 4.80

1.80

.65 Typ

SIDE VIEW

17198A

CB 48

6/25/92 SG

119

PHYSICAL DIMENSIONS*

PQT080

80-Pin Thin Quad Flat Package (measured in millimeters)

80

1

13.80

14.20

11.80

12.20

11.80

12.20

13.80

14.20

11ϒ– 13ϒ

.95

1.05

1.20 MAX

0.50 BSC

11ϒ– 13ϒ

1.00 REF.

120

APPENDIX A

Logical Address Filtering

For Ethernet

The purpose of logical (or group or multicast)

ad dresses is to allow a group of nodes in a network to

receive the same message. Each node can maintain a

list of multicast addresses that it will respond to. The

logical address filter mechanism in AMD Ethernet con-

trollers is a hardware aide that reduces the average

amount of host computer time required to determine

whether or not an incoming packet with a multicast

des tination address should be accepted.

assigned so that each address maps into a different

category, and no software filtering will be needed at all.

In the latter case described above, a node can be made

a member of several groups by setting the appropriate

bits in the logical address filter register. The administra-

tor can use the table Mapping of Logical Address to

Fil ter Mask to find a multicast address that maps into a

particular address filter bit. For example address 0000

0000 00BB maps into bit 15. Therefore, any node that

has bit 15 set in its logical address filter register will

re ceive all packets addressed to 0000 0000 00BB.

(Addresses in this table are not shown in the standard

Ethernet format. In the table the rightmost byte is the

first byte to appear on the network with the least

signif icant bit appearing first).

The logical address filter hardware is an implementa-

tion of a hash code searching technique commonly

used by software programmers. If the multicast bit in

the destination address of an incoming packet is set,

the hardware maps this address into one of 64 catego-

ries then accepts or rejects the packet depending on

whether or not the bit in the logical address filter regis-

ter corresponding the selected category is set. For

ex ample, if the address maps into category 24, and bit

24 of the logical address filter register is set, the packet

is accepted.

Driver software that manages a list of multicast

ad dresses can work as follows. First the multicast

ad dress list and the logical address filter must be

ini tialized. Some sort of management function such as

the driver initialization routine passes to the driver a list

of addresses. For each address in the list the driver

uses a subroutine similar to the one listed in the

Am7990 LANCE data sheet to set the appropriate bit in

a software copy of the logical address filter register.

When the complete list of addresses has been

pro cessed, the register is loaded.

14

Since there are more than 10 possible multicast

ad dresses and only 64 categories, this scheme is far

from unambiguous. This means that the software will

still have to compare the address of a received packet

with its list of acceptable multicast addresses to make

the final decision whether to accept or discard the

packet. However, the hardware prevents the software

from having to deal with the vast majority of the

unac ceptable packets.

Later, when a packet is received, the driver first looks

at the Individual/Group bit of the destination address of

the packet to find out whether or not this is a multicast

address. If it is, the driver must search the multicast

ad dress list to see if this address is in the list. If it is not

in the list, the packet is discarded.

The efficiency of this scheme depends on the number

of multicast groups that are used on a particular net-

work and the number of groups to which a node

be longs. At one extreme if a node happens to belong

to 64 groups that map into 64 different categories, the

hardware will accept all multicast addresses, and all fil-

tering must be done by software. At the other extreme

(which is closer to a practical network), if multicast

ad dresses are assigned by the local administrator, and

fewer than 65 groups are set up, the addresses can be

The broadcast address, which consists of all ones is a

special multicast address. Packets addressed to the

broadcast address must be received by all nodes.

Since broadcast packets are usually more common

than other multicast packets, the broadcast address

should be the first address in the multicast address list.

Am79C940

121

MAPPING OF LOGICAL ADDRESS TO FILTER MASK

LADRF

Bit

Destination

Address Accepted

LADRF

Bit

Destination

Address Accepted

Byte #

Bit #

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

Byte #

Bit #

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

0

1

2

3

0

85 00 00 00 00 00

A5 00 00 00 00 00

E5 00 00 00 00 00

C5 00 00 00 00 00

45 00 00 00 00 00

65 00 00 00 00 00

25 00 00 00 00 00

05 00 00 00 00 00

2B 00 00 00 00 00

0B 00 00 00 00 00

4B 00 00 00 00 00

6B 00 00 00 00 00

EB 00 00 00 00 00

CB 00 00 00 00 00

8B 00 00 00 00 00

BB 00 00 00 00 00

C7 00 00 00 00 00

E7 00 00 00 00 00

A7 00 00 00 00 00

87 00 00 00 00 00

07 00 00 00 00 00

27 00 00 00 00 00

67 00 00 00 00 00

47 00 00 00 00 00

69 00 00 00 00 00

49 00 00 00 00 00

09 00 00 00 00 00

29 00 00 00 00 00

A9 00 00 00 00 00

89 00 00 00 00 00

C9 00 00 00 00 00

E9 00 00 00 00 00

4

5

6

7

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

21 00 00 00 00 00

01 00 00 00 00 00

41 00 00 00 00 00

71 00 00 00 00 00

E1 00 00 00 00 00

C1 00 00 00 00 00

81 00 00 00 00 00

A1 00 00 00 00 00

8F 00 00 00 00 00

BF 00 00 00 00 00

EF 00 00 00 00 00

CF 00 00 00 00 00

4F 00 00 00 00 00

6F 00 00 00 00 00

2F 00 00 00 00 00

0F 00 00 00 00 00

63 00 00 00 00 00

43 00 00 00 00 00

03 00 00 00 00 00

23 00 00 00 00 00

A3 00 00 00 00 00

83 00 00 00 00 00

C3 00 00 00 00 00

E3 00 00 00 00 00

CD 00 00 00 00 00

ED 00 00 00 00 00

AD 00 00 00 00 00

8D 00 00 00 00 00

0D 00 00 00 00 00

2D 00 00 00 00 00

6D 00 00 00 00 00

4D 00 00 00 00 00

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

122

Am79C940

APPENDIX B

BSDL DESCRIPTION OF

Am79C940 MACE JTAG

STRUCTURE

-- -------- 04 November 1996 -----------

-- JWB 13-AUG-1996 changed "TQFP_PACKAGE" to "TQFP"

-- 31-OCT-1996 corrected reversed bit subscripts for ADD, DBUS !

--

-- A separate file for TQFP only, had to be created due to the missing

-- four pins/functions on the TQFP version.

-- The compiler does not know how to handle the missing four pins/functions

and bumped chip rev version from 2 to 3

--

in the TQFP version while at the same time, available for the PQFP

and PLCC versions. We have no further plans for going back to

combining both files into a single BSDL file.

Network Products Division Product Marketing Group

-- -------------------------------------

-- BSDL File created/edited by AT&T BSD Editor

--

-- BSDE:Revision: Silicon Rev. C0; File REV A3

-- BSDE:Description: BSDL File for the AM79C940 MACE Rev C0 Product

-- BSDE:Comments: /* BSDL file for the TQFP Definition only.

--

* BSDL file checked by AT&T’s BCAD2 BSD Editor on 04/03/96

*/

entity AM79C940 is

generic (PHYSICAL_PIN_MAP : string := "TQFP" );

port (

ADD: in bit_vector (4 downto 0);

AVDD1: linkage bit;

AVDD2: linkage bit;

AVDD3: linkage bit;

AVDD4: linkage bit;

Am79C940

123

AVSS1: linkage bit;

AVSS2: linkage bit;

BE0_L: in bit;

BE1_L: in bit;

CI0: linkage bit;

CI1: in bit;

CLSN: inout bit;

CS_L: in bit;

DBUS: inout bit_vector (15 downto 0);

DI0: linkage bit;

DI1: in bit;

DO0: linkage bit;

DO1: out bit;

DVDD1: linkage bit;

DVDD2: linkage bit;

DVDDN: linkage bit;

DVDDP: linkage bit;

DVSS1: linkage bit;

DVSS2: linkage bit;

DVSSN1: linkage bit;

DVSSN2: linkage bit;

DVSSN3: linkage bit;

DVSSP: linkage bit;

DXRCV_L: out bit;

EAM_R_L: in bit;

EDSEL: in bit;

EOF_L: inout bit;

FDS_L: in bit;

INTR_L: out bit;

LNKST_L: out bit;

RDTREQ_L: out bit;

RESET_L: in bit;

RXCRS: inout bit;

RXD0: linkage bit;

RXD1: in bit;

RXDAT: inout bit;

R_W_L: in bit;

SCLK: in bit;

SF_BD: out bit;

124

Am79C940

SLEEP_L: in bit;

SRDCLK: inout bit;

STDCLK: inout bit;

TCK: in bit;

TC_L: in bit;

TDI: in bit;

TDO: out bit;

TDTREQ_L: out bit;

TMS: in bit;

TXD0: linkage bit;

TXD1: out bit;

TXDAT1: inout bit;

TXEN_L: inout bit;

TXP0: linkage bit;

TXP1: out bit;

XTAL1: in bit;

XTAL2: linkage bit

);

use STD_1149_1_1990.all;

attribute PIN_MAP of AM79C940 : entity is PHYSICAL_PIN_MAP;

constant TQFP: PIN_MAP_STRING:=

"ADD:(40,39,38,37,36)," &

"AVDD1:52," &

"AVDD2:57," &

"AVDD3:64," &

"AVDD4:69," &

"AVSS1:59," &

"AVSS2:61," &

"BE0_L:31," &

"BE1_L:32," &

"CI0:67," &

"CI1:68," &

"CLSN:78," &

"CS_L:42," &

"DBUS:(27,26,24,23,22,21,20,19,18,17," &

"16,14,13,12,11,9)," &

Am79C940

125

"DI0:65," &

"DI1:66," &

"DO0:62," &

"DO1:63," &

"DVDD1:49," &

"DVDD2:70," &

"DVDDN:25," &

"DVDDP:6," &

"DVSS1:47," &

"DVSS2:73," &

"DVSSN1:10," &

"DVSSN2:15," &

"DVSSN3:28," &

"DVSSP:75," &

"DXRCV_L:71," &

"EAM_R_L:2," &

"EDSEL:72," &

"EOF_L:29," &

"FDS_L:30," &

"INTR_L:7," &

"LNKST_L:43," &

"RDTREQ_L:35," &

"RESET_L:4," &

"RXCRS:80," &

"RXD0:50," &

"RXD1:51," &

"RXDAT:79," &

"R_W_L:41," &

"SCLK:33," &

"SF_BD:3," &

"SLEEP_L:5," &

"SRDCLK:1," &

"STDCLK:76," &

"TCK:46," &

"TC_L:8," &

"TDI:48," &

"TDO:44," &

"TDTREQ_L:34," &

"TMS:45," &

126

Am79C940

"TXD0:54," &

"TXD1:56," &

"TXDAT1:74," &

"TXEN_L:77," &

"TXP0:53," &

"TXP1:55," &

"XTAL1:58," &

"XTAL2:60";

attribute TAP_SCAN_IN

attribute TAP_SCAN_OUT

of TDI : signal is true;

of TDO : signal is true;

attribute TAP_SCAN_MODE of TMS : signal is true;

attribute TAP_SCAN_CLOCK of TCK : signal is (1.00e+07, BOTH);

attribute INSTRUCTION_LENGTH of AM79C940 : entity is 4;

attribute INSTRUCTION_OPCODE of AM79C940 : entity is

"BYPASS ( 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110," &

" 1111)," &

"EXTEST ( 0000)," &

"IDCODE ( 0001)," &

"SAMPLE ( 0010)," &

"SELFTST ( 0101)," &

"SETBYP ( 0100)," &

"TRIBYP ( 0011)" ;

attribute INSTRUCTION_CAPTURE of AM79C940 : entity is "0001";

attribute INSTRUCTION_DISABLE of AM79C940 : entity is "TRIBYP";

attribute INSTRUCTION_PRIVATE of AM79C940 : entity is

" SELFTST";

attribute IDCODE_REGISTER of AM79C940 : entity is

"0011" &---- version

31-OCT-1996 bumped version from 2 to 3 !

"1001010000000000" &--- part number

"00000000001" &---- manufacturer’s id

"1";----- required by standard

attribute REGISTER_ACCESS of AM79C940 : entity is

Am79C940

127

"BYPASS ( BYPASS, SETBYP, TRIBYP)," &

"BOUNDARY ( EXTEST, SAMPLE, SELFTST)," &

"IDCODE ( IDCODE)";

attribute BOUNDARY_CELLS of AM79C940 : entity is

" BC_1, BC_4";

attribute BOUNDARY_LENGTH of AM79C940 : entity is 99;

attribute BOUNDARY_REGISTER of AM79C940 : entity is

"

0 (BC_1, *, control, 0)," &

1 (BC_1, LNKST_L, output3, X, 0, 0, Weak1)," &

2 (BC_1, *, internal, 0)," &

3 (BC_1, CS_L, input, 1)," &

4 (BC_1, R_W_L, input, 1)," &

5 (BC_1, ADD(4), input, 0)," &

6 (BC_1, ADD(3), input, 0)," &

7 (BC_1, ADD(2), input, 0)," &

8 (BC_1, ADD(1), input, 0)," &

9 (BC_1, ADD(0), input, 0)," &

10 (BC_1, *, control, 0)," &

11 (BC_1, RDTREQ_L, output3, X, 10, 0, Z)," &

12 (BC_1, TDTREQ_L, output3, X, 10, 0, Z)," &

13 (BC_4, SCLK, clock, 1)," &

14 (BC_1, BE1_L, input, 1)," &

15 (BC_1, BE0_L, input, 1)," &

16 (BC_1, FDS_L, input, 1)," &

17 (BC_1, *, internal, 0)," &

18 (BC_1, *, internal, 0)," &

19 (BC_1, *, control, 0)," &

20 (BC_1, EOF_L, output3, X, 19, 0, Z)," &

21 (BC_1, EOF_L, input, 1)," &

22 (BC_1, *, control, 0)," &

23 (BC_1, DBUS(15), output3, X, 22, 0, Z)," &

24 (BC_1, DBUS(15), input, 0)," &

25 (BC_1, DBUS(14), output3, X, 22, 0, Z)," &

26 (BC_1, DBUS(14), input, 0)," &

27 (BC_1, DBUS(13), output3, X, 22, 0, Z)," &

28 (BC_1, DBUS(13), input, 0)," &

128

Am79C940

"

29 (BC_1, DBUS(12), output3, X, 22, 0, Z)," &

30 (BC_1, DBUS(12), input, 0)," &

31 (BC_1, DBUS(11), output3, X, 22, 0, Z)," &

32 (BC_1, DBUS(11), input, 0)," &

33 (BC_1, DBUS(10), output3, X, 22, 0, Z)," &

34 (BC_1, DBUS(10), input, 0)," &

35 (BC_1, *, control, 0)," &

36 (BC_1, DBUS(9), output3, X, 35, 0, Z)," &

37 (BC_1, DBUS(9), input, 0)," &

38 (BC_1, DBUS(8), output3, X, 35, 0, Z)," &

39 (BC_1, DBUS(8), input, 0)," &

40 (BC_1, DBUS(7), output3, X, 35, 0, Z)," &

41 (BC_1, DBUS(7), input, 0)," &

42 (BC_1, DBUS(6), output3, X, 35, 0, Z)," &

43 (BC_1, DBUS(6), input, 0)," &

44 (BC_1, DBUS(5), output3, X, 35, 0, Z)," &

45 (BC_1, DBUS(5), input, 0)," &

46 (BC_1, DBUS(4), output3, X, 35, 0, Z)," &

47 (BC_1, DBUS(4), input, 0)," &

48 (BC_1, DBUS(3), output3, X, 35, 0, Z)," &

49 (BC_1, DBUS(3), input, 0)," &

50 (BC_1, DBUS(2), output3, X, 35, 0, Z)," &

51 (BC_1, DBUS(2), input, 0)," &

52 (BC_1, DBUS(1), output3, X, 35, 0, Z)," &

53 (BC_1, DBUS(1), input, 0)," &

54 (BC_1, DBUS(0), output3, X, 35, 0, Z)," &

55 (BC_1, DBUS(0), input, 0)," &

56 (BC_1, TC_L, input, 1)," &

57 (BC_1, *, control, 0)," &

58 (BC_1, INTR_L, output3, 1, 57, 0, Weak1)," &

59 (BC_1, SLEEP_L, input, 1)," &

60 (BC_1, RESET_L, input, 1)," &

61 (BC_1, *, control, 0)," &

62 (BC_1, SF_BD, output3, X, 61, 0, Z)," &

63 (BC_1, *, internal, 0)," &

64 (BC_1, EAM_R_L, input, 0)," &

65 (BC_1, *, control, 0)," &

66 (BC_1, SRDCLK, output3, X, 65, 0, Z)," &

67 (BC_1, SRDCLK, input, 0)," &

Am79C940

129

"

68 (BC_1, *, control, 0)," &

69 (BC_1, RXCRS, output3, X, 68, 0, Z)," &

70 (BC_1, RXCRS, input, 0)," &

71 (BC_1, *, control, 0)," &

72 (BC_1, RXDAT, output3, X, 71, 0, Z)," &

73 (BC_1, RXDAT, input, 0)," &

74 (BC_1, *, control, 0)," &

75 (BC_1, CLSN, output3, X, 74, 0, Z)," &

76 (BC_1, CLSN, input, 0)," &

77 (BC_1, *, control, 0)," &

78 (BC_1, TXEN_L, output3, X, 77, 0, Z)," &

79 (BC_1, TXEN_L, input, 0)," &

80 (BC_1, *, control, 0)," &

81 (BC_1, STDCLK, output3, X, 80, 0, Z)," &

82 (BC_1, STDCLK, input, 0)," &

83 (BC_1, *, control, 0)," &

84 (BC_1, *, internal, 0)," &

85 (BC_1, TXDAT1, output3, X, 83, 0, Z)," &

86 (BC_1, TXDAT1, input, 1)," &

87 (BC_1, EDSEL, input, 1)," &

88 (BC_1, *, control, 0)," &

89 (BC_1, DXRCV_L, output3, X, 88, 0, Z)," &

90 (BC_4, XTAL1, clock, 0)," &

91 (BC_1, RXD1, input, 1)," &

92 (BC_1, *, control, 0)," &

93 (BC_1, TXP1, output3, X, 92, 0, Z)," &

94 (BC_1, TXD1, output3, X, 92, 0, Z)," &

95 (BC_1, *, control, 0)," &

96 (BC_1, DO1, output3, X, 95, 0, Z)," &

97 (BC_4, DI1, input, 1)," &

98 (BC_4, CI1, input, 1)";

end AM79C940;

=============================================================================

130

Am79C940

--

BSDL File created/edited by AT&T BSD Editor

BSDE:Revision: Silicon Rev. C0; File REV A3

BSDE:Description: BSDL File for the AM79C940 MACE Product;

84-Pin PLCC and 100-Pin PQFP packages.

Separate file for 80-Pin TQFP package.

BSDE:Comments: /* TQFP Definition has been deleted.

* BSDL file checked by AT&T’s BCAD2 BSD Editor on 9/7/95

*/

entity AM79C940 is

generic (PHYSICAL_PIN_MAP : string := "PLCC_PACKAGE" );

port (

ADD: in bit_vector (0 to 4);

AVDD1: linkage bit;

AVDD2: linkage bit;

AVDD3: linkage bit;

AVDD4: linkage bit;

AVSS1: linkage bit;

AVSS2: linkage bit;

BE0_L: in bit;

BE1_L: in bit;

CI0: linkage bit;

CI1: in bit;

CLSN: inout bit;

CS_L: in bit;

DBUS: inout bit_vector (0 to 15);

DI0: linkage bit;

DI1: in bit;

DO0: linkage bit;

DO1: out bit;

DTV_L: out bit;

DVDD1: linkage bit;

DVDD2: linkage bit;

DVDDN: linkage bit;

DVDDP: linkage bit;

Am79C940

131

DVSS1: linkage bit;

DVSS2: linkage bit;

DVSSN1: linkage bit;

DVSSN2: linkage bit;

DVSSN3: linkage bit;

DVSSP: linkage bit;

DXRCV_L: out bit;

EAM_R_L: in bit;

EDSEL: in bit;

EOF_L: inout bit;

FDS_L: in bit;

INTR_L: out bit;

LNKST_L: out bit;

RDTREQ_L: out bit;

RESET_L: in bit;

RXCRS: inout bit;

RXD0: linkage bit;

RXD1: in bit;

RXDAT: inout bit;

RXPOL_L: out bit;

R_W_L: in bit;

SCLK: in bit;

SF_BD: out bit;

SLEEP_L: in bit;

SRD: out bit;

SRDCLK: inout bit;

STDCLK: inout bit;

TCK: in bit;

TC_L: in bit;

TDI: in bit;

TDO: out bit;

TDTREQ_L: out bit;

TMS: in bit;

TXD0: linkage bit;

TXD1: out bit;

TXDAT0: out bit;

TXDAT1: inout bit;

TXEN_L: inout bit;

TXP0: linkage bit;

132

Am79C940

TXP1: out bit;

XTAL1: in bit;

XTAL2: linkage bit

);

use STD_1149_1_1990.all;

attribute PIN_MAP of AM79C940 : entity is PHYSICAL_PIN_MAP;

constant PLCC_PACKAGE: PIN_MAP_STRING:=

"ADD:(49,50,51,52,53)," &

"AVDD1:66," &

"AVDD2:71," &

"AVDD3:78," &

"AVDD4:83," &

"AVSS1:73," &

"AVSS2:75," &

"BE0_L:44," &

"BE1_L:45," &

"CI0:81," &

"CI1:82," &

"CLSN:9," &

"CS_L:55," &

"DBUS:(21,23,24,25,26,28,29,30,31,32," &

"33,34,35,36,38,39)," &

"DI0:79," &

"DI1:80," &

"DO0:76," &

"DO1:77," &

"DTV_L:42," &

"DVDD1:63," &

"DVDD2:84," &

"DVDDN:37," &

"DVDDP:18," &

"DVSS1:61," &

"DVSS2:3," &

"DVSSN1:22," &

"DVSSN2:27," &

"DVSSN3:40," &

Am79C940

133

"DVSSP:6," &

"DXRCV_L:1," &

"EAM_R_L:13," &

"EDSEL:2," &

"EOF_L:41," &

"FDS_L:43," &

"INTR_L:19," &

"LNKST_L:57," &

"RDTREQ_L:48," &

"RESET_L:16," &

"RXCRS:11," &

"RXD0:64," &

"RXD1:65," &

"RXDAT:10," &

"RXPOL_L:56," &

"R_W_L:54," &

"SCLK:46," &

"SF_BD:15," &

"SLEEP_L:17," &

"SRD:14," &

"SRDCLK:12," &

"STDCLK:7," &

"TCK:60," &

"TC_L:20," &

"TDI:62," &

"TDO:58," &

"TDTREQ_L:47," &

"TMS:59," &

"TXD0:68," &

"TXD1:70," &

"TXDAT0:5," &

"TXDAT1:4," &

"TXEN_L:8," &

"TXP0:67," &

"TXP1:69," &

"XTAL1:72," &

"XTAL2:74";

constant PQFP_PACKAGE: PIN_MAP_STRING:=

134

Am79C940

"ADD:(46,47,48,49,50)," &

"AVDD1:67," &

"AVDD2:72," &

"AVDD3:83," &

"AVDD4:88," &

"AVSS1:74," &

"AVSS2:79," &

"BE0_L:41," &

"BE1_L:42," &

"CI0:86," &

"CI1:87," &

"CLSN:98," &

"CS_L:56," &

"DBUS:(14,16,17,18,19,21,22,23,24,25," &

"29,31,32,33,35,36)," &

"DI0:84," &

"DI1:85," &

"DO0:81," &

"DO1:82," &

"DTV_L:39," &

"DVDD1:64," &

"DVDD2:89," &

"DVDDN:34," &

"DVDDP:11," &

"DVSS1:62," &

"DVSS2:92," &

"DVSSN1:15," &

"DVSSN2:20," &

"DVSSN3:37," &

"DVSSP:95," &

"DXRCV_L:90," &

"EAM_R_L:6," &

"EDSEL:91," &

"EOF_L:38," &

"FDS_L:40," &

"INTR_L:12," &

"LNKST_L:58," &

"RDTREQ_L:45," &

"RESET_L:9," &

Am79C940

135

"RXCRS:100," &

"RXD0:65," &

"RXD1:66," &

"RXDAT:99," &

"RXPOL_L:57," &

"R_W_L:55," &

"SCLK:43," &

"SF_BD:8," &

"SLEEP_L:10," &

"SRD:7," &

"SRDCLK:5," &

"STDCLK:96," &

"TCK:61," &

"TC_L:13," &

"TDI:63," &

"TDO:59," &

"TDTREQ_L:44," &

"TMS:60," &

"TXD0:69," &

"TXD1:71," &

"TXDAT0:94," &

"TXDAT1:93," &

"TXEN_L:97," &

"TXP0:68," &

"TXP1:70," &

"XTAL1:73," &

"XTAL2:75";

attribute TAP_SCAN_IN

attribute TAP_SCAN_OUT

of TDI : signal is true;

of TDO : signal is true;

attribute TAP_SCAN_MODE of TMS : signal is true;

attribute TAP_SCAN_CLOCK of TCK : signal is (1.00e+07, BOTH);

attribute INSTRUCTION_LENGTH of AM79C940 : entity is 4;

attribute INSTRUCTION_OPCODE of AM79C940 : entity is

"BYPASS ( 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110," &

" 1111)," &

"EXTEST ( 0000)," &

"IDCODE ( 0001)," &

136

Am79C940

"SAMPLE ( 0010)," &

"SELFTST ( 0101)," &

"SETBYP ( 0100)," &

"TRIBYP ( 0011)" ;

attribute INSTRUCTION_CAPTURE of AM79C940 : entity is "0001";

attribute INSTRUCTION_DISABLE of AM79C940 : entity is "TRIBYP";

attribute INSTRUCTION_PRIVATE of AM79C940 : entity is

" SELFTST";

attribute IDCODE_REGISTER of AM79C940 : entity is

"0011" &-- version

"1001010000000000" &-- part number

"00000000001" &-- manufacturer’s id

"1";-- required by standard

attribute REGISTER_ACCESS of AM79C940 : entity is

"BYPASS ( BYPASS, SETBYP, TRIBYP)," &

"BOUNDARY ( EXTEST, SAMPLE, SELFTST)," &

"IDCODE ( IDCODE)";

attribute BOUNDARY_CELLS of AM79C940 : entity is

" BC_1, BC_4";

attribute BOUNDARY_LENGTH of AM79C940 : entity is 99;

attribute BOUNDARY_REGISTER of AM79C940 : entity is

"

0 (BC_1, *, control, 0)," &

1 (BC_1, LNKST_L, output3, X, 0, 0, Weak1)," &

2 (BC_1, RXPOL_L, output3, X, 0, 0, Weak1)," &

3 (BC_1, CS_L, input, 1)," &

4 (BC_1, R_W_L, input, 1)," &

5 (BC_1, ADD(4), input, 0)," &

6 (BC_1, ADD(3), input, 0)," &

7 (BC_1, ADD(2), input, 0)," &

8 (BC_1, ADD(1), input, 0)," &

9 (BC_1, ADD(0), input, 0)," &

Am79C940

137

"

10 (BC_1, *, control, 0)," &

11 (BC_1, RDTREQ_L, output3, X, 10, 0, Z)," &

12 (BC_1, TDTREQ_L, output3, X, 10, 0, Z)," &

13 (BC_4, SCLK, clock, 1)," &

14 (BC_1, BE1_L, input, 1)," &

15 (BC_1, BE0_L, input, 1)," &

16 (BC_1, FDS_L, input, 1)," &

17 (BC_1, *, control, 0)," &

18 (BC_1, DTV_L, output3, X, 17, 0, Z)," &

19 (BC_1, *, control, 0)," &

20 (BC_1, EOF_L, output3, X, 19, 0, Z)," &

21 (BC_1, EOF_L, input, 1)," &

22 (BC_1, *, control, 0)," &

23 (BC_1, DBUS(15), output3, X, 22, 0, Z)," &

24 (BC_1, DBUS(15), input, 0)," &

25 (BC_1, DBUS(14), output3, X, 22, 0, Z)," &

26 (BC_1, DBUS(14), input, 0)," &

27 (BC_1, DBUS(13), output3, X, 22, 0, Z)," &

28 (BC_1, DBUS(13), input, 0)," &

29 (BC_1, DBUS(12), output3, X, 22, 0, Z)," &

30 (BC_1, DBUS(12), input, 0)," &

31 (BC_1, DBUS(11), output3, X, 22, 0, Z)," &

32 (BC_1, DBUS(11), input, 0)," &

33 (BC_1, DBUS(10), output3, X, 22, 0, Z)," &

34 (BC_1, DBUS(10), input, 0)," &

35 (BC_1, *, control, 0)," &

36 (BC_1, DBUS(9), output3, X, 35, 0, Z)," &

37 (BC_1, DBUS(9), input, 0)," &

38 (BC_1, DBUS(8), output3, X, 35, 0, Z)," &

39 (BC_1, DBUS(8), input, 0)," &

40 (BC_1, DBUS(7), output3, X, 35, 0, Z)," &

41 (BC_1, DBUS(7), input, 0)," &

42 (BC_1, DBUS(6), output3, X, 35, 0, Z)," &

43 (BC_1, DBUS(6), input, 0)," &

44 (BC_1, DBUS(5), output3, X, 35, 0, Z)," &

45 (BC_1, DBUS(5), input, 0)," &

46 (BC_1, DBUS(4), output3, X, 35, 0, Z)," &

47 (BC_1, DBUS(4), input, 0)," &

48 (BC_1, DBUS(3), output3, X, 35, 0, Z)," &

138

Am79C940

"

49 (BC_1, DBUS(3), input, 0)," &

50 (BC_1, DBUS(2), output3, X, 35, 0, Z)," &

51 (BC_1, DBUS(2), input, 0)," &

52 (BC_1, DBUS(1), output3, X, 35, 0, Z)," &

53 (BC_1, DBUS(1), input, 0)," &

54 (BC_1, DBUS(0), output3, X, 35, 0, Z)," &

55 (BC_1, DBUS(0), input, 0)," &

56 (BC_1, TC_L, input, 1)," &

57 (BC_1, *, control, 0)," &

58 (BC_1, INTR_L, output3, 1, 57, 0, Weak1)," &

59 (BC_1, SLEEP_L, input, 1)," &

60 (BC_1, RESET_L, input, 1)," &

61 (BC_1, *, control, 0)," &

62 (BC_1, SF_BD, output3, X, 61, 0, Z)," &

63 (BC_1, SRD, output3, X, 61, 0, Z)," &

64 (BC_1, EAM_R_L, input, 0)," &

65 (BC_1, *, control, 0)," &

66 (BC_1, SRDCLK, output3, X, 65, 0, Z)," &

67 (BC_1, SRDCLK, input, 0)," &

68 (BC_1, *, control, 0)," &

69 (BC_1, RXCRS, output3, X, 68, 0, Z)," &

70 (BC_1, RXCRS, input, 0)," &

71 (BC_1, *, control, 0)," &

72 (BC_1, RXDAT, output3, X, 71, 0, Z)," &

73 (BC_1, RXDAT, input, 0)," &

74 (BC_1, *, control, 0)," &

75 (BC_1, CLSN, output3, X, 74, 0, Z)," &

76 (BC_1, CLSN, input, 0)," &

77 (BC_1, *, control, 0)," &

78 (BC_1, TXEN_L, output3, X, 77, 0, Z)," &

79 (BC_1, TXEN_L, input, 0)," &

80 (BC_1, *, control, 0)," &

81 (BC_1, STDCLK, output3, X, 80, 0, Z)," &

82 (BC_1, STDCLK, input, 0)," &

83 (BC_1, *, control, 0)," &

84 (BC_1, TXDAT0, output3, X, 83, 0, Z)," &

85 (BC_1, TXDAT1, output3, X, 83, 0, Z)," &

86 (BC_1, TXDAT1, input, 1)," &

87 (BC_1, EDSEL, input, 1)," &

Am79C940

139

"

88 (BC_1, *, control, 0)," &

89 (BC_1, DXRCV_L, output3, X, 88, 0, Z)," &

90 (BC_4, XTAL1, clock, 0)," &

91 (BC_1, RXD1, input, 1)," &

92 (BC_1, *, control, 0)," &

93 (BC_1, TXP1, output3, X, 92, 0, Z)," &

94 (BC_1, TXD1, output3, X, 92, 0, Z)," &

95 (BC_1, *, control, 0)," &

96 (BC_1, DO1, output3, X, 95, 0, Z)," &

97 (BC_4, DI1, input, 1)," &

98 (BC_4, CI1, input, 1)";

end AM79C940;

140

Am79C940

APPENDIX C

Am79C940 MACE Rev C0 Silicon

Errata

The items below are the known errata for Rev C0 silicon. Rev C0 is the production silicon.

The enclosed is a list of known errata’s encountered with the MACE Rev C0 device. Each of these errata’s is pro-

vided with description, implication, and workaround (if possible). Where the errata was published in a previous er-

rata list, is so noted. Other than those listed exceptions below that have not been fixed, the MACE Rev C0

production device is fully functional.

The "Description" section of the errata gives a brief description of the problem. The "Implication" section of the

errata describes the effects of the problem in a system configuration. The "Workaround" section of the errata de-

scribes methods to minimize the system effects. The “Status” section of the errata describes when and how the

problem will be corrected.

Current package marking for this revision: Line 1: <Logo>

Line 2: Am79C940BKC (Assuming package is PQFP)

Line 3: <Date Code>

Value of CHIPID register for this revision: CHIPID[15:00] = 3940h

1) Receive Fragment Frame Treated as a New Packet Even After Receive FIFO Overflows:

Description: The MACE device continues to receive the remains of a long packet even after the receive FIFO

overflows. If this data stream has the ’Start of Frame’ (SFD) bit pattern "10101011" (and no "00" bit pattern

before the "SFD" pattern) and the destination address field of the packet matches the station address after

the SFD bit pattern, or if the MACE device is in promiscuous mode, the remaining portion of the long packet

will be received and treated by the MACE device as a new packet even though the receive status will show

an FCS error.

Implication: There is no impact of any kind if the receive FIFO overflow is not permitted by the system design.

The likelihood of such an occurrence of the above conditions is extremely remote. Should this condition occur,

this will impact performance only in products using the “cut-through” method. This is because the "cut-

through" method will not look at the FCS field, which would indicate an error in the packet received.

Workaround: Check for FCS error after the packet is received.

Status: No current plan to fix this item.

2) In Low Latency Receive Mode, Loses Synchronization When Connected to a Coaxial Transceiver via the

AUI Port:

Description: In low latency receive mode, the MACE device loses synchronization when connected to a co-

axial (10BASE2) transceiver. The problem occurs when connecting the MACE to a coaxial transceiver via the

AUI interface, and at the same time the MACE device is programmed into low latency receive mode. When

a collision occurs in the media and if MACE device continues to receive data, after the collision is ended, the

MACE device loses synchronization.

Implication: No performance impact to the MACE device if the 10BASE-T port is used instead of a 10BASE2

coaxial transceiver connected to the AUI port of the MACE device.

Workaround: This condition is being validated at this time. In the meantime, it is recommended that if the

product is to be used in a network topology where a 10BASE2 coaxial transceiver is connected to the AUI

port, care must be exercised to avoid using the MACE device in low latency receiver mode.

Am79C940

141

Status: No current plan to fix this item.

3) Flashing LED for Link Status:

Description: When TMAU receiver is receiving negative polarity link pulse, and the automatic polarity correc-

tion algorithm (DAPC bit in PHY Configuration Control Register) is disabled, link test state machine will loop

between ’link fail’ and ’link pass’ state causing the Link Status LED to flash.

Implication: There is no impact to system performance. However, the Link Status LED flashing may cause

an erroneous interpretation by the user.

Workaround: There is no workaround.

Status: No current plan to fix this item.

4) Incorrect Runt Packet Count in Low Latency Receive Mode:

Description: In Low Latency Receive mode, the MACE Runt Packet count is incremented when the receive

packet is less than 12 bytes. The correct runt packet count should always be incremented when the receive

packet is less than 64 bytes.

Implication: There is no impact on system performance if the runt packet count is not being utilized by the

system.

Workaround: This condition is being validated at this time. Therefore, a workaround for this is to be deter-

mined.

5) Device Failure at 1.25 MHz System Clock:

Description: MACE device does not function reliability at system clock speed of less than 5MHz due to ar-

chitecture constraints.

Implication: There is no performance impact since the serial clock is still running at the IEEE specified

10MHz.

Workarounds:

1. Avoid operating the MACE device at speeds of less than 5MHz.

2. Send one packet at a time. Essentially, write one packet to the transmit FIFO, let the Mace device

transmit that packet, wait for the transmit complete interrupt, before writing another packet to the

transmit FIFO.

Status: No current plan to fix this item.

6) False BABL errors generated:

Description: The MACE device will intermittenly give BABL error indications when the network traffic has

frames equal to or greater than 1518 bytes.

Implication: False BABL errors on the receiving station can be passed up to the upper layer software if MACE

device is just coming out of deferral and the multi-purpose counter used to count the number of bytes recevied

reaches 1518 at the same time. If the network is heavily loaded with full-size frames, then the probability of

a false BABL error is high.

Workaround: There are two possible workarounds.

1. If the user has no intention to transmit frames larger than 1518 bytes, then the BABL bit may be

masked to ignore babble errors. In this case the false babble error will not cause an interrupt, nor will

it be passed to the higher level software.

2. Check to see if the device is transmitting in ISR (Interrupt Service Routine), which is induced by the

BABL error. The BCRs which control the LED settings can be programmed to indicate a transmit ac-

tivity, assuming the interrupt latency is not longer than one mininum IFG (inter-frame gap) time.

142

Am79C940

If (ISR_LATENCY < 9.6 us)

True_bable_err = BABL * ( TINT + XMT_LED)

{ i.e. False_bable_err = ~ (BABL * ( TINT + XMT_LED))}

else

Cannot tell if the BABL error is true or false just by reading BABL, TINT,

XMT_LED bits in ISR.

Status: No current plan to fix this item.

Am79C940

143

144

Am79C940


型号：	AM79C940KI
厂家：	ETC
描述：	LAN Node Controller 局域网节点控制器\n 外围集成电路数据传输控制器 PC 局域网时钟
文件：	总144页 (文件大小：1334K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AM79C940KI [ETC]

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