AM79C940VCW [AMD]
Media Access Controller for Ethernet (MACE); 媒体访问控制器以太网（ MACE ）
| 型号： | AM79C940VCW |
| 厂家： | 
AMD |
| 描述： | Media Access Controller for Ethernet (MACE) |
| 文件： | 总122页 (文件大小：831K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FINAL
Advanced
Micro
Am79C940
Media Access Controller for Ethernet (MACETM)
Devices
DISTINCTIVE CHARACTERISTICS
■ Integrated Controller with 10BASE-T
■ Arbitrary byte alignment and little/big endian
transceiver and AUI port
memory interface supported
■ Supports IEEE 802.3/ANSI 8802-3 and Ethernet
■ Internal/external loopback capabilities
standards
■ External Address Detection Interface (EADI )
for external hardware address filtering in
bridge/router applications
■ JTAG Boundary Scan (IEEE 1149.1 ) test
access port interface for board level
production test
■ 84-pin PLCC and 100-pin PQFP Packages
■ 80-pin Thin Quad Flat Pack (TQFP) package
available for space critical applications such
as PCMCIA
■ Modular architecture allows easy tuning to
specific applications
■ Integrated Manchester Encoder/Decoder
■ High speed, 16-bit synchronous host system
■ Digital Attachment Interface (DAI ) allows
by-passing of differential Attachment Unit
Interface (AUI)
interface with 2 or 3 cycles/transfer
■ Individual transmit (136 byte) and receive (128
byte) FlFOs provide increase of system
■ Supports the following types of network
latency and support the following features:
interface:
– Automatic retransmission with no FIFO
reload
– AUI to external 10BASE2, 10BASE5 or
10BASE-F MAU
– Automatic receive stripping and transmit
padding (individually programmable)
– DAI port to external 10BASE2, 10BASE5,
10BASE-T, 10BASE-F MAU
– Automatic runt packet rejection
– General Purpose Serial Interface (GPSI) to
external encoding/decoding scheme
– Automatic deletion of collision frames
– Internal 10BASE-T transceiver with
– Automatic retransmission with no FIFO
reload
automatic selection of 10BASE-T or AUI port
■ Sleep mode allows reduced power consump-
■ Direct slave access to all on board
configuration/status registers and transmit/
receive FlFOs
tion for critical battery powered applications
■ 1 MHz – 25 MHz system clock speed
■ Direct FIFO read/write access for simple
interface to DMA controllers or l/O processors
GENERAL DESCRIPTION
The Media Access Controller for Ethernet (MACE) chip
is a CMOS VLSI device designed to provide flexibility in
customized LAN design. The MACE device is specifi-
cally designed to address applications where multiple
I/O peripherals are present, and a centralized or system
specific DMA is required. The high speed, 16-bit syn-
chronous system interface is optimized for an external
DMA or I/O processor system, and is similar to many ex-
isting peripheral devices, such as SCSI and serial
link controllers.
specific application. Its superior modular architecture
and versatile system interface allow the MACE device to
be configured as a stand-alone device or as a connec-
tivity cell incorporated into a larger, integrated system.
The MACE device provides a complete Ethernet node
solution with an integrated 10BASE-T transceiver, and
supports up to 25-MHz system clocks. The MACE de-
vice embodies the Media Access Control (MAC) and
Physical Signaling (PLS) sub-layers of the IEEE 802.3
standard, and provides an IEEE defined Attachment
Unit Interface (AUI) for coupling to an external Medium
Attachment Unit (MAU). The MACE device is
compliant with 10BASE2, 10BASE5, 10BASE-T, and
10BASE-F transceivers.
The MACE device is a slave register based peripheral.
All transfers to and from the system are performed using
simple memory or I/O read and write commands. In con-
junction with a user defined DMA engine, the MACE
chip provides an IEEE 802.3 interface tailored to a
Publication#16235
Rev. C Amendment/0
Issue Date: June 1994
AMD
Additional features also enhance over-all system
design. The individual transmit and receive FIFOs
optimize system overhead, providing substantial
latency during packet transmission and reception, and
minimizing intervention during normal network error
recovery. The integrated Manchester encoder/decoder
eliminates the need for an external Serial Interface
Adapter (SIA) in the node system. If support for an
external encoding/decoding scheme is desired, the
General Purpose Serial Interface (GPSI) allows direct
access to/from the MAC. In addition, the Digital Attach-
ment Interface (DAI), which is a simplified electrical
attachment specification, allows implementation of
MAUs that do not require DC isolation between the MAU
and DTE. The DAI port can also be used to indicate
transmit, receive, or collision status by connecting LEDs
to the port. The MACE device also provides an External
Address Detection Interface (EADI) to allow external
hardware address filtering in internetworking
applications.
The Am79C940 MACE chip is offered in a Plastic Lead-
less Chip Carrier (84-pin PLCC), a Plastic Quad Flat
Package (100-pin PQFP), and a Thin Quad Flat Pack-
age (TQFP 80-pin). There are several small functional
and physical differences between the 80-pin TQFP and
the 84-pin PLCC and 100-pin PQFP configurations.
Because of the smaller number of pins in the TQFP con-
figuration versus the PLCC configuration, four pins are
not bonded out. Though the die is identical in all three
package configurations, the removal of these four pins
does cause some functionality differences between the
TQFP and the PLCC and PQFP configurations. De-
pendingontheapplication, theremovalofthesepinswill
or will not have an effect.
BLOCK DIAGRAM
XTAL1
XTAL2
ENCODER/
DECODER
(PLS)
DXCVR
CLSN
SRDCLK
SRD
SF/BD
EAM/R
EADI
Port
Control
EADI Port
AUI
DBUS 15-0
RCV FIFO
XMT FIFO
ADD 4-0
R/W
DO±
DI±
CI±
AUI
Port
802.3
MAC
Core
CS
FDS
TXD±
TXP±
DTV
FIFO
Control
RXD±
LNKST
RXPOL
10BASE-T
DAI Port
10BASE-T
MAU
EOF
Bus
Interface
Unit
RDTREQ
TDTREQ
BE 1–0
INTR
TXDAT±
TXEN
Command
& Status
Registers
DAI
Port
RXDAT
RXCRS
SCLK
EDSEL
TC
STDCLK
TXDAT+
TXEN
SLEEP
RESET
GPSI
Port
GPSI
SRDCLK
RXDAT
RXCRS
CLSN
JTAG
PORT CNTRL
TDO
TDI
16235C-1
TMS
TCK
Notes:
1. Only one of the network ports AUI, 10BASE-T, DAI port or GPSI can be active at any time. Some shared signals are active
regardless of which network port is active, and some are reconfigured.
2. The EADI port is active at all times.
2
Am79C940
AMD
RELATED PRODUCTS
Part No.
Description
Am7996
IEEE 802.3/Ethernet/Cheapernet Transceiver
CMOS Local Area Network Controller for Ethernet (C-LANCE)
Twisted Pair Ethernet Transceiver (TPEX)
Am79C90
Am79C98
Am79C100
Am79C981
Am79C987
Am79C900
Twisted Pair Ethernet Transceiver Plus (TPEX+)
Integrated Multiport Repeater Plus (IMR+ )
Hardware Implemented Management Information Base (HIMIB )
Integrated Local Area Communications Controller (ILACC )
Am79C961
Am79C965
Am79C970
Am79C974
PCnet-ISA+ Single-Chip Ethernet Controller for ISA (with Microsoft Plug n’ PlaySupport)
PCnet-32 Single-Chip 32-Bit Ethernet Controller
PCnet-PCI Single-Chip Ethernet Controller (for PCI bus)
PCnet-SCSI Combination Ethernet and SCSI Controller for PCI Systems
Am79C940
3
AMD
TABLE OF CONTENTS
DISTINCTIVE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-64
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-64
BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-65
RELATED PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-66
CONNECTION DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-70
PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-70
PQR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-71
PQT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-72
ORDERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-73
PIN/PACKAGE SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-74
PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-82
Network Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-82
Attachment Unit Interface (AUI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-82
Digital Attachment Interface (DAI ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-82
10BASE-T Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-85
General Purpose Serial Interface (GPSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-85
External Address Detection Interface (EADI ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-86
Host System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-88
IEEE 1149.1 Test Access Port (TAP) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-89
General Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-89
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-90
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-92
Network Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-92
System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-92
DETAILED FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-93
Block Level Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-93
Bus Interface Unit (BIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-93
BIU to FIFO Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-93
BIU to Control and Status Register Data Path . . . . . . . . . . . . . . . . . . . . . . . . . 1-94
FIFO Sub-System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-94
Media Access Control (MAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-96
Manchester Encoder/Decoder (MENDEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-100
Attachment Unit Interface (AUI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-103
Digital Attachment Interface (DAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-103
10BASE-T Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-104
Twisted Pair Transmit Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-104
Twisted Pair Receive Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-104
Link Test Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-105
Polarity Detection and Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-105
Twisted Pair Interface Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-106
Collision Detect Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-106
Signal Quality Error (SQE) Test (Heartbeat) Function . . . . . . . . . . . . . . . . . . 1-106
Jabber Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-106
4
Am79C940
AMD
External Address Detection Interface (EADI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-107
General Purpose Serial Interface (GPSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-108
IEEE 1149.1 Test Access Port Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-108
Slave Access Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-109
Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-109
Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-110
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-110
Reinitialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-110
Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-110
Transmit FIFO Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-111
Transmit Function Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-111
Automatic Pad Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-112
Transmit FCS Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-113
Transmit Status Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-113
Transmit Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-113
Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-115
Receive FIFO Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-115
Receive Function Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-116
Automatic Pad Stripping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-116
Receive FCS Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-117
Receive Status Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-117
Receive Exception Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-117
Loopback Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-118
USER ACCESSIBLE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-120
Receive FIFO (RCVFIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-120
Transmit FIFO (XMTFIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-120
Transmit Frame Control (XMTFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-120
Transmit Frame Status (XMTFS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-121
Transmit Retry Count (XMTRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-122
Receive Frame Control (RCVFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-122
Receive Frame Status (RCVFS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-123
RFS0—Receive Message Byte Count (RCVCNT) . . . . . . . . . . . . . . . . . . . . . . . . . 1-123
RFS1—Receive Status (RCVSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-123
RFS2—Runt Packet Count (RNTPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-124
RFS3—Receive Collision Count (RCVCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-124
FIFO Frame Count (FIFOFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-124
Interrupt Register (IR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-124
Interrupt Mask Register (IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-126
Poll Register (PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-126
BIU Configuration Control (BIUCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-127
FIFO Configuration Control (FIFOCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-127
MAC Configuration Control (MACCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-129
PLS Configuration Control (PLSCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-130
PHY Configuration Control (PHYCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-130
Chip Identification Register (CHIPID [15–00]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-131
Internal Address Configuration (IAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-131
Logical Address Filter (LADRF [63–00]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-132
Am79C940
5
AMD
Physical Address (PADR [47–00]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-134
Missed Packet Count (MPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-134
Runt Packet Count (RNTPC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-134
Receive Collision Count (RCVCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-135
User Test Register (UTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-135
Reserved Test Register 1 (RTR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-136
Reserved Test Register 2 (RTR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-136
Register Table Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-137
Register Bit Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-138
16-Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-138
8-Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-138
Receive Frame Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-138
Programmer’s Register Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-139
SYSTEM APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-142
HOST SYSTEM EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-142
Motherboard DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-142
System Interface-Motherboard DMA Example . . . . . . . . . . . . . . . . . . . . . . . . 1-143
PC/AT Ethernet Adapter Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-144
System Interface-Simple PC/AT Ethernet Hypercard Example . . . . . . . . . . . 1-145
NETWORK INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-145
External Address Detection Interface (EADI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-145
Attachment Unit Interface (AUI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-146
10BASE-T Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-147
10BASE -T and 10BASE2 Configuration of Am79C940 . . . . . . . . . . . . . . . . . . . . . 1-148
10BASE -T and AUI Implementation of Am79C940 . . . . . . . . . . . . . . . . . . . . . . . . 1-149
MACE Device Compatible AUI Isolation Transformers . . . . . . . . . . . . . . . . . . . . . 1-150
MACE Device Compatible 10BASE-T Media Interface Modules . . . . . . . . . . . . . . 1-150
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-152
OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-152
DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-152
AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-155
BIU Output Valid Delay vs. Load Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-159
KEY TO SWITCHING WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-159
SWITCHING TEST CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-160
AC WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-161
APPENDIX A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-179
LOGICAL ADDRESS FILTERING FOR ETHERNET . . . . . . . . . . . . . . . . . . . . . . . . . . 1-179
MAPPING OF LOGICAL ADDRESS TO FILTER MASK . . . . . . . . . . . . . . . . . . . . . . . 1-180
APPENDIX B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-181
BSDL DESCRIPTION OF Am79C940 MACE JTAG STRUCTURE . . . . . . . . . . . . . . . 1-181
6
Am79C940
AMD
CONNECTION DIAGRAMS
PL 084
PLCC Package
9
11
10
8
5
2
1
82
84 83
81
6
4
3
78 77 76 75
80 79
7
SRDCLK
EAM/R
SRD
SF/BD
RESET
SLEEP
DVDD
INTR
TC
DBUS0
DVSS
DBUS1
DBUS2
DBUS3
DBUS4
DVSS
DBUS5
DBUS6
DBUS7
DBUS8
DBUS9
12
74
XTAL2
AVSS
XTAL1
AVDD
TXD+
TXP+
TXD-
TXP-
AVDD
RXD+
RXD-
DVDD
TDI
13
14
15
16
17
18
73
72
71
70
69
68
67
19
20
21
22
23
24
66
65
64
63
62
61
60
59
58
MACE
Am79C940JC
25
26
27
28
29
30
31
32
DVSS
TCK
TMS
TDO
57
56
55
54
LNKST
RXPOL
CS
R/W
35
39
43 44
48
49
52 53
50 51
33
37 38
41 42
45 46 47
36
40
34
16235C-2
Am79C940
7
AMD
CONNECTION DIAGRAMS
PQR 100
PQFP Package
NC
NC
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
NC
AVSS
NC
NC
NC
NC
SRDCLK
XTAL2
AVSS
XTAL1
AVDD
TXD+
TXP+
TXD-
TXP-
AVDD
RXD+
RXD-
DVDD
TDI
EAM/R
SRD
SF/BD
RESET
SLEEP
DVDD
INTR
TC
DBUS0
DVSS
DBUS1
DBUS2
DBUS3
DBUS4
DVSS
9
10
11
12
13
14
15
16
17
18
19
20
MACE
Am79C940KC
DVSS
TCK
21
22
23
24
25
26
27
28
29
30
TMS
TDO
LNKST
RXPOL
CS
DBUS5
DBUS6
DBUS7
DBUS8
DBUS9
NC
NC
NC
DBUS10
NC
60
59
58
57
56
55
54
53
52
51
R/W
NC
NC
NC
NC
16235C-3
8
Am79C940
AMD
CONNECTION DIAGRAMS
PQT 080
TQFP Package
80 79 78 77 76 757473 72 717069 68 67 65 64 63 62 61
66
SRDCLK
EAM/R
SF/BD
RESET
SLEEP
DVDD
1
2
3
4
5
6
60
59
58
57
56
55
XTAL2
AVSS
XTAL1
AVDD
TXD+
TXP+
INTR
TC
DBUS0
DVSS
DBUS1
DBUS2
DBUS3
7
8
9
10
11
12
13
54
53
52
51
50
49
48
TXD-
TXP-
AVDD
RXD+
RXD-
DVDD
TDI
MACE
Am79C940VC
DBUS4
DVSS
14
15
16
17
18
19
20
47
46
45
44
43
42
41
DVSS
TCK
TMS
TD0
LNKST
CS
DBUS5
DBUS6
DBUS7
DBUS8
DBUS9
R/W
21 22 23 24 25 262728 29 303132 33 34 36 37 38 39 40
35
16235C-4
Note: Four pin functions available on the PLCC and PQFP packages are not available with the TQFP package.
(See page 27 “Pin Functions not available with the 80-pin TQFP Package”).
Am79C940
9
AMD
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of:
AM79C940
V
C
/W
ALTERNATE PACKAGING OPTION
/W = Trimmed and Formed in a Tray
OPTIONAL PROCESSING
Blank = Standard Processing
TEMPERATURE RANGE
C = Commercial (0° to +70°C)
PACKAGE TYPE (per Prod. Nomenclature/16-038)
J = 84-Pin Plastic Leaded Chip Carrier (PL 084)
K = 100-Pin Plastic Quad Flat Pack (PQR100)
V = 80-Pin Thin Quad Flat Package (PQT080)
SPEED
Not Applicable
DEVICE NUMBER/DESCRIPTION (include revision letter)
Am79C940
Media Access Controller for Ethernet
Valid Combinations
Valid Combinations
The Valid Combinations table lists configurations
planned to be supported in volume for this device.
Consult the local AMD sales office to confirm
availability of specific valid combinations and to
check on newly released combinations.
JC, KC,
AM79C940
KC/W, VC,
VC/W
10
Am79C940
AMD
PIN/PACKAGE SUMMARY
PLCC Pin #
Pin Name
Pin Function
Disable Transceiver
1
2
DXCVR
EDSEL
Edge Select
3
4
5
DVSS
Digital Ground
Transmit Data +
Transmit Data –
TXDAT+
TXDAT–
6
DVSS
STDCLK
TXEN/TXEN
CLSN
Digital Ground
7
Serial Transmit Data Clock
Transmit Enable
8
9
Collision
10
11
12
13
14
15
16
17
RXDAT
RXCRS
SRDCLK
EAM/R
Receive Data
Receive Carrier Sense
Serial Receive Data Clock
External Address Match/Reject
Serial Receive Data
Start Frame/Byte Delimiter
Reset
SRD
SF/BD
RESET
SLEEP
Sleep Mode
18
19
20
21
DVDD
INTR
TC
Digital Power
Interrupt
Timing Control
Data Bus0
DBUS0
22
23
24
25
26
DVSS
Digital Ground
Data Bus1
Data Bus2
Data Bus3
Data Bus4
DBUS1
DBUS2
DBUS3
DBUS4
27
28
29
30
31
32
33
34
35
36
DVSS
Digital Ground
Data Bus5
Data Bus6
Data Bus7
Data Bus8
Data Bus9
Data Bus10
Data Bus11
Data Bus12
Data Bus13
DBUS5
DBUS6
DBUS7
DBUS8
DBUS9
DBUS10
DBUS11
DBUS12
DBUS13
37
38
39
DVDD
Digital Power
Data Bus14
Data Bus15
DBUS14
DBUS15
40
41
42
DVSS
EOF
DTV
Digital Ground
End Of Frame
Data Transfer Valid
Am79C940
11
AMD
PIN/PACKAGE SUMMARY (continued)
PLCC Pin #
Pin Name
Pin Function
FIFO Data Strobe
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
FDS
BE0
Byte Enable0
Byte Enable1
System Clock
Transmit Data Transfer Request
Receive Data Transfer Request
Address0
BE1
SCLK
TDTREQ
RDTREQ
ADD0
ADD1
ADD2
ADD3
ADD4
R/W
Address1
Address2
Address3
Address4
Read/Write
CS
Chip Select
RXPOL
LNKST
TDO
Receive Polarity
Link Status
Test Data Out
Test Mode Select
Test Clock
TMS
TCK
61
62
DVSS
TDI
Digital Ground
Test Data Input
63
64
65
DVDD
RXD–
RXD+
Digital Power
Receive Data–
Receive Data+
66
67
68
69
70
AVDD
TXP–
TXD–
TXP+
TXD+
Analog Power
Transmit Pre-distortion
Transmit Data–
Transmit Pre–distortion+
Transmit Data+
71
72
AVDD
Analog Power
Crystal Input
XTAL1
73
74
AVSS
Analog Ground
Crystal Output
XTAL2
75
76
77
AVSS
DO–
DO+
Analog Ground
Data Out–
Data Out+
78
79
80
81
82
AVDD
DI–
Analog Power
Data In–
DI+
Data In+
CI–
Control In–
Control In+
CI+
83
84
AVDD
DVDD
Analog Power
Digital Power
12
Am79C940
AMD
PIN/PACKAGE SUMMARY (continued)
PQFP Pin #
Pin Name
Pin Function
1
2
NC
NC
No Connect
No Connect
No Connect
No Connect
3
NC
4
NC
5
SRDCLK
EAM/R
SRD
Serial Receive Data Clock
External Address Match/Reject
Serial Receive Data
Start Frame/Byte Delimiter
Reset
6
7
8
SF/BD
RESET
SLEEP
DVDD
INTR
9
10
11
12
13
14
Sleep Mode
Digital Power
Interrupt
TC
Timing Control
DBUS0
Data Bus0
15
16
17
18
19
DVSS
Digital Ground
Data Bus1
Data Bus2
Data Bus3
Data Bus4
DBUS1
DBUS2
DBUS3
DBUS4
20
21
22
23
24
25
26
27
28
29
30
31
32
33
DVSS
DBUS5
DBUS6
DBUS7
DBUS8
DBUS9
NC
Digital Ground
Data Bus5
Data Bus6
Data Bus7
Data Bus8
Data Bus9
No Connect
No Connect
No Connect
Data Bus10
No Connect
Data Bus11
Data Bus12
Data Bus13
NC
NC
DBUS10
NC
DBUS11
DBUS12
DBUS13
34
35
36
DVDD
Digital Power
Data Bus14
Data Bus15
DBUS14
DBUS15
37
38
39
40
41
42
DVSS
EOF
DTV
FDS
BE0
BE1
Digital Ground
End Of Frame
Data Transfer Valid
FIFO Data Strobe
Byte Enable0
Byte Enable1
Am79C940
13
AMD
PIN/PACKAGE SUMMARY (continued)
PQFP Pin #
Pin Name
Pin Function
System Clock
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
SCLK
TDTREQ
RDTREQ
ADD0
ADD1
ADD2
ADD3
ADD4
NC
Transmit Data Transfer Request
Receive Data Transfer Request
Address0
Address1
Address2
Address3
Address4
No Connect
NC
No Connect
NC
No Connect
NC
No Connect
R/W
Read/Write
CS
Chip Select
RXPOL
LNKST
TDO
Receive Polarity
Link Status
Test Data Out
Test Mode Select
Test Clock
TMS
TCK
62
63
DVSS
TDI
Digital Ground
Test Data Input
64
65
66
DVDD
RXD–
RXD+
Digital Power
Receive Data–
Receive Data+
67
68
69
70
71
AVDD
TXP–
TXD–
TXP+
TXD+
Analog Power
Transmit Pre-distortion–
Transmit Data–
Transmit Pre-distortion+
Transmit Data+
72
73
AVDD
Analog Power
Crystal Input
XTAL1
74
75
76
77
78
AVSS
XTAL2
NC
Analog Ground
Crystal Output
No Connect
No Connect
No Connect
NC
NC
79
80
81
82
AVSS
NC
Analog Ground
No Connect
Data Out–
DO–
DO+
Data Out+
83
84
85
AVDD
DI–
Analog Power
Data In–
DI+
Data In+
14
Am79C940
AMD
PIN/PACKAGE SUMMARY (continued)
PQFP Pin #
Pin Name
Pin Function
86
87
CI–
CI+
Control In–
Control In+
88
AVDD
Analog Power
89
90
91
DVDD
DXCVR
EDSEL
Digital Power
Disable Transceiver
Edge Select
92
93
94
DVSS
Digital Ground
Transmit Data +
Transmit Data –
TXDAT+
TXDAT–
95
96
DVSS
STDCLK
TXEN/TXEN
CLSN
Digital Ground
Serial Transmit Data Clock
Transmit Enable
Collision
97
98
99
RXDAT
Receive Data
100
RXCRS
Receive Carrier Sense
Am79C940
15
AMD
PIN/PACKAGE SUMMARY (continued)
TQFP
TQFP
Pin Number Pin Name
Pin Function
Pin Number Pin Name
Pin Function
Read/Write
1
SRDCLK Serial Receive Data Clock
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
R/W
CS
2
EAM/R
SF/BD
RESET
SLEEP
DVDD
INTR
External Address Match/Reject
Start Frame/Byte Delimiter
Reset
Chip/Select
3
LNKST
TDO
Link Status
4
Test Data Out
Test Mode Select
Test Clock
5
Sleep Mode
Digital Power
Interrupt
TMS
6
TCK
7
DVSS
TDI
Digital Ground
Test Data Input
Digital Power
Receive Data–
Receive Data+
Analog Power
Transmit Pre-distortion–
Transmit Data–
Transmit Pre-distortion+
Transmit Data+
Analog Power
Crystal Output
Analog Ground
Crystal Output
Analog Ground
Data Out–
8
TC
Timing Control
Data Bus0
9
DBUS0
DVSS
DVDD
RXD–
RXD+
AVDD
TXP–
TXD–
TXP+
TXD+
AVDD
XTAL1
AVSS
XTAL2
AVSS
DO–
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Digital Ground
Data Bus1
DBUS1
DBUS2
DBUS3
DBUS4
DVSS
Data Bus2
Data Bus3
Data Bus4
Digital Ground
Data Bus5
DBUS5
DBUS6
DBUS7
DBUS8
DBUS9
Data Bus6
Data Bus7
Data Bus8
Data Bus9
DBUS10 Data Bus10
DBUS11 Data Bus11
DBUS12 Data Bus12
DBUS13 Data Bus13
DO+
Data Out+
AVDD
DI–
Analog Power
Data In–
DVDD
Digital Power
DBUS14 Data Bus14
DBUS15 Data Bus15
DI+
Data Out+
CI–
Control In–
DVSS
EOF
FDS
BE0
Digital Ground
End of Frame
FIFO Data Strobe
Byte Enable0
Byte Enable1
System Clock
CI+
Control In+
AVDD
DVDD
DXCVR
EDSEL
DVSS
TXDAT+
DVSS
STDCLK
Analog Power
Digital Power
Disable Transceiver
Edge Select
BE1
SCLK
Digital Ground
Transmit Data+
Digital Ground
Serial Transmit Data Clock
TDTREQ Transmit Data Transfer Request
RDTREQ Receive Data Transfer Request
ADD0
ADD1
ADD2
ADD3
ADD4
Address0
Address1
Address2
Address3
Address4
TXEN/TXEN Transmit Enable
CLSN
RXDAT
RXCRS
Collision
Receive Data
Receive Carrier Sense
16
Am79C940
AMD
PIN SUMMARY
Pin Name
Pin Function
Type
Active
Comment
Attachment Unit Interface (AUI)
DO+/DO–
DI+/DI–
CI+/CI–
RXCRS
TXEN
Data Out
O
I
Pseudo-ECL
Data In
Pseudo-ECL
Pseudo-ECL
Control In
I
Receive Carrier Sense
Transmit Enable
Collision
I/O
O
High
High
High
Low
TTL output. Input in DAI, GPSI port
TTL. TXEN in DAI port
TTL output. Input in GPSI
TTL low
CLSN
I/O
O
DXCVR
STDCLK
SRDCLK
Disable Transceiver
Serial Transmit Data Clock
Serial Receive Data Clock
I/O
I/O
Output. Input in GPSI
Output. Input in GPSI
Digital Attachment Interface (DAI)
TXDAT+
TXDAT–
TXEN
Transmit Data +
O
O
High
Low
Low
TTL. See also GPSI
TTL
Transmit Data –
Transmit Enable
O
TTL. See TXEN in GPSI
TTL. See also GPSI
TTL input. Output in AUI
TTL output. Input in GPSI
TTL high
RXDAT
RXCRS
CLSN
Receive Data
I
Receive Carrier Sense
Collision
I/O
I/O
O
High
High
High
DXCVR
STDCLK
SRDCLK
Disable Transceiver
Serial Transmit Data Clock
Serial Receive Data Clock
I/O
I/O
Output. Input in GPSI
Output. Input in GPSI
10BASE–T Interface
TXD+/TXD–
TXP+/TXP–
RXD+/RXD–
LNKST
Transmit Data
O
O
Transmit Pre-distortion
Receive Data
I
Link Status
O
Low
Low
High
High
High
High
Open Drain
RXPOL
Receive Polarity
O
Open Drain
TXEN
Transmit Enable
O
TTL. TXEN in DAI port
TTL output. Input in DAI, GPSI port
TTL output. Input in GPSI
TTL high
RXCRS
Receive Carrier Sense
Collision
I/O
I/O
O
CLSN
DXCVR
Disable Transceiver
Serial Transmit Data Clock
Serial Receive Data Clock
STDCLK
SRDCLK
I/O
I/O
Output. Input in GPSI
Output. Input in GPSI
General Purpose Serial Interface (GPSI)
STDCLK
TXDAT+
TXEN
Serial Transmit Data Clock
Transmit Data +
I/O
O
Input
High
High
TTL. See also DAI port
TTL. TXEN in DAI port
Input. See also EADI port
TTL. See also DAI port
TTL input. Output in AUI
TTL input
Transmit Enable
O
SRDCLK
RXDAT
RXCRS
CLSN
Serial Receive Data Clock
Receive Data
I/O
I
Receive Carrier Sense
Collision
I/O
I/O
O
High
High
Low
DXCVR
Disable Transceiver
TTL low
Am79C940
17
AMD
PIN SUMMARY (continued)
Pin Name
Pin Function
Type
Active
Comment
External Address Detection Interface (EADI)
SF/BD
SRD
Start Frame/Byte Delimiter
Serial Receive Data
O
O
High
High
Low
EAM/R
SRDCLK
External Address Match/Reject
Serial Receive Data Clock
I
I/O
Output except in GPSI
Host System Interface
DBUS15–0
ADD4–0
R/W
Data Bus
I/O
High
High
High/Low
Low
Address
I
I
Read/Write
RDTREQ
TDTREQ
DTV
Receive Data Transfer Request
Transmit Data Transfer Request
Data Transfer Valid
End Of Frame
Byte Enable 0
Byte Enable 1
Chip Select
O
O
O
I/O
I
Low
Low
Tristate
EOF
Low
BE0
Low
BE1
I
Low
CS
I
Low
FDS
FIFO Data Strobe
Interrupt
I
Low
INTR
O
I
Low
Open Drain
EDSEL
TC
Edge Select
High
Low
Timing Control
System Clock
I
Internal pull-up
SCLK
RESET
I
High
Low
Reset
I
IEEE 1149.1 Test Access Port (TAP) Interface
TCK
TMS
TDI
Test Clock
I
I
Internal pull-up
Internal pull-up
Internal pull-up
Test Mode Select
Test Data Input
Test Data Out
I
TDO
O
General Interface
XTAL1
XTAL2
SLEEP
Crystal Input
I
O
I
CMOS
CMOS
TTL
Crystal Output
Sleep Mode
Low
DVDD
DVSS
AVDD
AVSS
Digital Power (4 pins)
Digital Ground (6 pins)
Analog Power (4 pins)
Analog Ground (2 pins)
P
P
P
P
18
Am79C940
AMD
PIN DESCRIPTION
Network Interfaces
DO+/DO
Data Out (Output)
The MACE device has five potential network interfaces.
Only one of the interfaces that provides physical net-
work attachment can be used (active) at any time. Se-
lection between the AUI, 10BASE-T, DAI or GPSI ports
is provided by programming the PHY Configuration
Control register. The EADI port is effectively active at all
times. Some signals, primarily used for status reporting,
are active for more than one single interface (the CLSN
pin for instance). Under each of the descriptions for the
network interfaces, the primary signals which are
unique to that interface are described. Where signals
are active for multiple interfaces, they are described
once under the interface most appropriate.
A differential output pair from the MACE device for
transmitting Manchester encoded data to the network.
Operates at pseudo-ECL levels.
Digital Attachment Interface (DAI)
TXDAT+/TXDAT–
Transmit Data (Output)
When the DAI port is selected, TXDAT± are configured
as a complementary pair for Manchester encoded data
output from the MACE device, used to transmit data to a
local external network transceiver. During valid trans-
mission (indicated by TXEN low), a logical 1 is indicated
by the TXDAT+ pin being in the high state and TXDAT–
in the low state; and a logical 0 is indicated by the
TXDAT+ pin being in the low state and TXDAT– in the
high state. During idle (TXEN high), TXDAT+ will be in
the high state, and TXDAT– in the low state. When the
GPSI port is selected, TXDAT+ will provide NRZ data
output from the MAC core, and TXDAT– will be held in
the LOW state. Operates at TTL levels. The operations
of TXDAT+ and TXDAT– are defined in the following
tables:
Attachment Unit Interface (AUI)
CI+/CI
Control In (Input)
A differential input pair, signalling the MACE device that
a collision has been detected on the network media, in-
dicated by the CI± inputs being exercised with 10 MHz
pattern of sufficient amplitude and duration. Operates at
pseudo-ECL levels.
DI+/DI
Data In (Input)
A differential input pair to the MACE device for receiving
Manchester encoded data from the network. Operates
at pseudo-ECL levels.
TXDAT+ Configuration
PORTSEL
[1–0]
SLEEP
ENPLSIO
Interface Description
Pin Function
0
1
1
1
1
1
XX
00
01
10
11
XX
X
1
1
1
1
0
Sleep Mode
AUI
High Impedance
High Impedance (Note 2)
High Impedance (Note 2)
TXDAT+ Output
10BASE-T
DAI Port
GPSI
TXDAT+ Output
Status Disabled
High Impedance (Note 2)
TXDAT– Configuration
PORTSEL
[1–0]
SLEEP
ENPLSIO
Interface Description
Pin Function
0
1
1
1
1
1
XX
00
01
10
11
XX
X
1
1
1
1
0
Sleep Mode
AUI
High Impedance
High Impedance
High Impedance
TXDAT– Output
LOW
10BASE-T
DAI Port
GPSI
Status Disabled
High Impedance
Notes:
1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).
2. This pin should be externally terminated, if unused, to reduce power consumption.
Am79C940
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decoded data input to the MAC core of the MACE de-
vice, from an external Manchester encoder/decoder.
Operates at TTL levels.
TXEN/TXEN
Transmit Enable (Output)
When the AUI port is selected (PORTSEL [1–0] = 00),
an output indicating that the AUI DO± differential output
has valid Manchester encoded data is presented. When
the 10BASE-T port is selected (PORTSEL [1–0] = 01),
indicates that Manchester data is being output on the
TXD±/TXP± complementary outputs. When the DAI
port is selected (PORTSEL [1–0] = 10), indicates that
Manchester data is being output on the DAI port
TXDAT± complementary outputs. When the GPSI port
is selected (PORTSEL [1–0] =11), indicates that NRZ
data is being output from the MAC core of the MACE de-
vice, to an external Manchester encoder/decoder, on
the TXDAT+ output. Active low when the DAI port is se-
lected, active high when the AUI, 10 BASE-T or GPSI is
selected. Operates at TTL levels.
RXCRS
Receive Carrier Sense (Input/Output)
When the AUI port is selected (PORTSEL [1–0] = 00),
an output indicating that the DI± input pair is receiving
valid Manchester encoded data from the external trans-
ceiverwhichmeetsthesignalamplitudeandpulsewidth
requirements. When the 10BASE-T port is selected
(PORTSEL [1–0] = 01), an output indicating that the
RXD± input pair is receiving valid Manchester encoded
data from the twisted pair cable which meets the signal
amplitude and pulse width requirements. RXCRS will be
asserted high for the entire duration of the receive mes-
sage. When the DAI port is selected (PORTSEL [1–0] =
10), an input signaling the MACE device that a receive
carrier condition has been detected on the network, and
valid Manchester encoded data is being presented to
the MACE device on the RXDAT line. When the GPSI
port is selected (PORTSEL [1–0] = 11), an input signall-
ing the internal MAC core that valid NRZ data is being
presented on the RXDAT input. Operates at TTL levels.
RXDAT
Receive Data (Input)
When the DAI port is selected (PORTSEL [1–0] = 10),
the Manchester encoded data input to the integrated
clock recovery and Manchester decoder of the MACE
device, from an external network transceiver. When the
GPSI port is selected (PORTSEL [1–0] =11), the NRZ
TXEN/TXEN Configuration
PORTSEL
[1–0]
SLEEP
ENPLSIO
Interface Description
Pin Function
0
1
1
1
1
1
XX
00
01
10
11
XX
X
1
1
1
1
0
Sleep Mode
AUI
High Impedance
TXEN Output
10BASE-T
DAI Port
GPSI
TXEN Output
TXEN Output
TXEN Output
Status Disabled
High Impedance (Note 3)
Notes:
1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).
2. When the GPSI port is selected, TXEN should have an external pull-down attached (e.g. 3.3kΩ) to ensure the output is held
inactivebefore ENPLSIO is set.
3. This pin should be externally terminated, if unused, to reduce power consumption.
RXDAT Configuration
PORTSEL
SLEEP
[1–0]
ENPLSIO
Interface Description
Pin Function
0
1
1
1
1
1
XX
00
01
10
11
XX
X
1
1
1
1
0
Sleep Mode
AUI
High Impedance
High Impedance (Note 2)
High Impedance (Note 2)
RXDAT Input
10BASE-T
DAI Port
GPSI
RXDAT Input
Status Disabled
High Impedance (Note 2)
Notes:
1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).
2. This pin should be externally terminated, if unused, to reduce power consumption.
20
Am79C940
AMD
RXCRS Configuration
Interface Description
PORTSEL
[1–0]
SLEEP
ENPLSIO
Pin Function
0
1
1
1
1
1
XX
00
01
10
11
XX
X
1
1
1
1
0
Sleep Mode
AUI
High Impedance
RXCRS Output
RXCRS Output
RXCRS Input
RXCRS Input
10BASE-T
DAI Port
GPSI
Status Disabled
High Impedance (Note 2)
Notes:
1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).
2. This pin should be externally terminated, if unused, to reduce power consumption.
link is active (LNKST pin driven LOW) the 10BASE-T
DXCVR
port will be used as the active network interface. If the
link is inactive (LNKST pin pulled HIGH) the AUI port will
be used as the active network interface. Auto Select will
continue to operate even when the SLEEP pin is as-
serted if the RWAKE bit has been set. The AWAKE bit
does not allow the Auto Select function, and only the re-
ceive section of 10BASE-T port will be active (DXCVR =
HIGH).
Disable Transceiver (Output)
An output from the MACE device to indicate the network
port in use, as programmed by the ASEL bit or the
PORTSEL [1–0] bits. The output is provided to allow
power down of an external DC-to-DC converter, typi-
cally used to provide the voltage requirements for an ex-
ternal 10BASE2 transceiver.
When the Auto Select (ASEL) feature is enabled, the
state of the PORTSEL [1–0] bits is overridden, and the
network interface will be selected by the MACE device,
dependentonlyonthestatusofthe10BASE-Tlink. Ifthe
Active (HIGH) when either the 10BASE-T or DAI port is
selected. Inactive (LOW) when the AUI or GPSI port is
selected.
DXCVR Configuration—SLEEP Operation
LNKST PORTSEL
SLEEP RWAKE AWAKE
ASEL
Bit
Interface
Description
Pin
Function
Pin
Bit
Bit
Pin [1–0] Bits
0
0
0
X
High
Impedance
XX
00
01
10
11
0X
0X
Sleep
Mode
High
Impedance
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
High
Impedance
AUI with EADI port
10BASE-T with EADI port
Invalid
LOW
HIGH
HIGH
LOW
LOW
HIGH
High
Impedance
High
Impedance
High
Impedance
Invalid
High
Impedance
AUI with EADI port
10BASE-T with EADI port
High
Impedance
0
0
0
1
1
0
1
1
1
1
1
X
HIGH
LOW
X
0X
0X
0X
AUI with EADI port
10BASE-T with EADI port
10BASE-T
LOW
HIGH
HIGH
Note: RWAKE and ASEL are located in the PHY Configuration Control register (REG ADDR 15). PORTSEL [1–0] and
ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14). All bits must be programmed prior to the
assertion of the SLEEP pin.
Am79C940
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DXCVR Configuration—Normal Operation
SLEEP
Pin
ASEL
Bit
LNKST
Pin
PORTSEL
[1–0] Bits
ENPLSIO
Bit
Interface
Description
Pin
Function
1
X
X
XX
X
SIA Test Mode
High
Impedance
1
1
1
1
1
1
0
0
0
0
1
1
X
X
00
01
10
11
0X
0X
X
X
X
X
X
X
AUI
10BASE-T
DAI Port
GPSI
LOW
HIGH
HIGH
LOW
LOW
HIGH
X
X
HIGH
LOW
AUI
10BASE-T
Note: RWAKE and ASEL are located in the PHY Configuration Control register (REG ADDR 15). PORTSEL [1–0] and
ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).
10BASE-T Interface
RXPOL
Receive Polarity (Output, Open Drain)
TXD+, TXD–
Transmit Data (Output)
The twisted pair receiver is capable of detecting a re-
ceive signal with reversed polarity (wiring error). The
RXPOL pin is normally in the LOW state, indicating cor-
rect polarity of the received signal. If the receiver detects
a received packet with reversed polarity, then this pin is
not driven (requires external pull–up) and the polarity of
subsequent packets are inverted. In the LOW output
state, this pin is capable of sinking a maximum of 12mA
and can be used to drive an LED.
10BASE-T port differential drivers.
TXP+, TXP–
Transmit Pre-Distortion (Output)
Transmit wave form differential driver for pre-distortion.
RXD+, RXD–
Receive Data (Input)
The polarity correction feature can be disabled by set-
ting the Disable Auto Polarity Correction (DAPC) bit in
the PHY Configuration Control register. In this case, the
Receive Polarity correction circuit is disabled and the in-
ternal receive signal remains non-inverted, irrespective
of the received signal. Note that RXPOL will continue to
reflect the polarity detected by the receiver.
10BASE-T port differential receiver. These pins should
beexternallyterminatedtoreducepowerconsumptionif
the 10BASE-T interface is not used.
LNKST
Link Status (OutputOpen Drain)
This pin is driven LOW if the link is identified as func-
tional. If the link is determined to be nonfunctional, due
to missing idle link pulses or data packets, then this pin
is not driven (requires external pull-up). In the LOW out-
put state, the pin is capable of sinking a maximum of
12 mA and can be used to drive an LED.
General Purpose Serial Interface (GPSI)
STDCLK
Serial Transmit Data Clock (Input/Output)
When either the AUI, 10BASE-T or DAI port is selected,
STDCLK is an output operating at one half the crystal or
XTAL1 frequency. STDCLK is the encoding clock for
Manchester data transferred to the output of either the
AUI DO± pair, the 10BASE-T TXD±/TXP± pairs, or the
DAI port TXDAT± pair. When using the GPSI port,
STDCLK is an input at the network data rate, provided
by the external Manchester encode/decoder, to strobe
out the NRZ data presented on the TXDAT+ output.
This feature can be disabled by setting the Disable Link
Test (DLNKTST) bit in the PHY Configuration Control
register. In this case the internal Link Test Receive func-
tion is disabled, the LNKST pin will be driven LOW, and
the Transmit and Receive functions will remain active
regardless of arriving idle link pulses and data. The in-
ternal 10BASE-T MAU will continue to generate idle link
pulses irrespective of the status of the DLNKTST bit.
22
Am79C940
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STDCLK Configuration
Interface Description
PORTSEL
[1–0]
SLEEP
ENPLSIO
Pin Function
0
1
1
1
1
1
XX
00
01
10
11
XX
X
1
1
1
1
0
Sleep Mode
AUI
High Impedance
STDCLK Output
STDCLK Output
STDCLK Output
STDCLK Input
10BASE-T
DAI Port
GPSI
Status Disabled
High Impedance (Note 2)
Notes:
1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).
2. This pin should be externally terminated, if unused, to reduce power consumption.
CLSN
Collision (Input/Output)
External Address Detection Interface
(EADI )
An external indication that a collision condition has been
detected by the (internal or external) Medium Attach-
ment Unit (MAU), and that signals from two or more
nodes are present on the network. When the AUI port is
selected (PORTSEL [1–0] = 00), CLSN will be activated
when the CI± input pair is receiving a collision indication
from the external transceiver. CLSN will be asserted
high for the entire duration of the collision detection, but
will not be asserted during the SQE Test message fol-
lowing a transmit message on the AUI. When the
10BASE-T port is selected (PORTSEL [1–0] = 01),
CLSN will be asserted high when simultaneous transmit
and receive activity is detected (logically detected when
TXD±/TXP± and RXD± are both active). When the DAI
port is selected (PORTSEL [1–0] = 10), CLSN will be as-
serted high when simultaneous transmit and receive ac-
tivity is detected (logically detected when RXCRS and
TXEN are both active). When the GPSI port is selected
(PORTSEL [1–0] = 11), an input from the external
Manchester encoder/decoder signaling the MACE de-
vice that a collision condition has been detected on the
network, and any receive frame in progress should be
aborted.
SF/BD
Start Frame/Byte Delimiter (Output)
The external indication that a start of frame delimiter has
been received. The serial bit stream will follow on the
Serial Receive Data pin (SRD), commencing with the
destination address field. SF/BD will go high for 4 bit
times (400 ns) after detecting the second 1 in the SFD of
a received frame. SF/BD will subsequently toggle every
400 ns (1.25 MHz frequency) with the rising edge indi-
cating the start (first bit) in each subsequent byte of the
received serial bit stream. SF/BD will be inactive during
frame transmission.
SRD
Serial Receive Data (Output)
SRD is the decoded NRZ data from the network. It is
available for external address detection. Note that when
the 10BASE-T port is selected, transition on SRD will
only occur during receive activity. When the AUI or DAI
port is selected, transition on SRD will occur during both
transmit and receive activity.
CLSN Configuration
PORTSEL
[1–0]
SLEEP
ENPLSIO
Interface Description
Pin Function
0
1
1
1
1
1
XX
00
01
10
11
XX
X
1
1
1
1
0
Sleep Mode
AUI
High Impedance
CLSN Output
10BASE-T
DAI Port
GPSI
CLSN Output
CLSN Output
CLSN Input
Status Disabled
High Impedance (Note 2)
Notes:
1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).
2. This pin should be externally terminated, if unused, to reduce power consumption.
Am79C940
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AMD
EAM/R
SRDCLK
Serial Receive Data Clock (Input/Output)
External Address Match/Reject (Input)
The incoming frame will be received dependent on the
receive operational mode of the MACE device, and the
polarity of the EAM/R pin. The EAM/R pin function is
programmed by use of the M/R bit in the Receive Frame
Control register. If the bit is set, the pin is configured as
EAM. If the bit is reset, the pin is configured as EAR.
EAM/R can be asserted during packet reception to ac-
cept or reject packets based on an external address
comparison.
The Serial Receive Data (SRD) output is synchronous
toSRDCLKrunningatthe10MHzreceivedataclockfre-
quency. The pin is configured as an input, only when the
GPSI port is selected. Note that when the 10BASE-T
port is selected, transition on SRDCLK will only occur
during receive activity. When the AUI or DAI port is se-
lected, transition on SRDCLK will occur during both
transmit and receive activity.
SRD Configuration
PORTSEL
[1–0]
SLEEP
ENPLSIO
Interface Description
Pin Function
0
1
1
1
1
1
XX
00
01
10
11
XX
X
1
1
1
1
0
Sleep Mode
AUI
High Impedance
SRD Output
10BASE-T
DAI Port
GPSI
SRD Output
SRD Output
SRD Output
Status Disabled
High Impedance
Note: PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).
SRDCLK Configuration
PORTSEL
SLEEP
[1–0]
ENPLSIO
Interface Description
Pin Function
0
1
1
1
1
1
XX
00
01
10
11
XX
X
1
1
1
1
0
Sleep Mode
AUI
High Impedance
SRDCLK Output
SRDCLK Output
SRDCLK Output
SRDCLK Input
10BASE-T
DAI Port
GPSI
Status Disabled
High Impedance (Note 2)
Notes:
1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).
2. This pin should be externally terminated, if unused, to reduce power consumption.
24
Am79C940
AMD
asserted only when Enable Transmit (ENXMT) is set in
the MAC Configuration Control register.
HOST SYSTEM INTERFACE
DBUS15–0
Data Bus (Input/Output/3-state)
FDS
FIFO Data Select (Input)
DBUS contains read and write data to and from internal
registers and the Transmit and Receive FIFOs.
FIFO Data Select allows direct access to the transmit or
Receive FIFO without use of the ADD address bus. FDS
must be activated in conjunction with R/W. When the
MACEdevicesamplesR/WashighandFDSlow, aread
cycle from the Receive FIFO will be initiated. When the
MACE chip samples R/W and FDS low, a write cycle to
the Transmit FIFO will be initiated. The CS line should
be inactive (high) when FIFO access is requested using
the FDS pin. If the MACE device samples both CS and
FDS as active simultaneously, no cycle will be exe-
cuted, and DTV will remain inactive.
ADD4–0
Address Bus (Input)
ADD is used to access the internal registers and FIFOs
to be read or written.
R/W
Read/Write (Input)
Indicates the direction of data flow during the MACE de-
vice
register, Transmit FIFO, or Receive FIFO
accesses.
DTV
Data Transfer Valid (Output/3-state)
RDTREQ
When asserted, indicates that the read or write opera-
tion has completed successfully. The absence ofDTVat
the termination of a host access cycle on the MACE de-
vice indicates that the data transfer was unsuccessful.
DTV need not be used if the system interface can guar-
antee that the latency to TDTREQ and RDTREQ asser-
tion and de-assertion will not cause the Transmit FIFO
to be over-written or the Receive FIFO to be over-read.
In this case, the latching or strobing of read or write data
canbesynchronizedtotheSCLKinputratherthantothe
DTV output.
Receive Data Transfer Request (Output)
Receive Data Transfer Request indicates that there is
data in the Receive FIFO to be read. When RDTREQ is
asserted there will be a minimum of 16 bytes to be read
except at the completion of the frame, in which case
EOF will be asserted. RDTREQ can be programmed to
request receive data transfer when 16, 32 or 64 bytes
are available in the Receive FIFO, by programming the
Receive FIFO Watermark (RCVFW bits) in the FIFO
Configuration Control register. The first assertion of
RDTREQ will not occur until at least 64 bytes have been
received, and the frame has been verified as non runt.
Runt packets will normally be deleted from the Receive
FIFO with no external activity on RDTREQ. When Runt
Packet Accept is enabled (RPA bit) in the User Test
Register, RDTREQ will be asserted when the runt pack-
et completes, and the entire frame resides in the
Receive FIFO. RDTREQ will be asserted only when En-
able Receive (ENRCV) is set in the MAC Configuration
Control register.
EOF
End Of Frame (Input/Output/3–state)
End Of Frame will be asserted by the MACE device
when the last byte/word of frame data is read from the
Receive FIFO, indicating the completion of the frame
data field for the receive message. End Of Frame must
be asserted low to the MACE device when the last byte/
word of the frame is written into the Transmit FIFO.
BE1–0
The RCVFW can be overridden by enabling the Low La-
tency Receive function (setting LLRCV bit) in the Re-
ceive Frame Control register, which allows RDTREQ to
be asserted after only 12 bytes have been received.
Note that use of this function exposes the system inter-
face to premature termination of the receive frame, due
to network events such as collisions or runt packets. It is
the responsibility of the system designer to provide ade-
quate recovery mechanisms for these conditions.
Byte Enable (Input)
Used to indicate the active portion of the data transfer to
or from the internal FIFOs. For word (16-bit) transfers,
both BE0 and BE1 should be activated by the external
host/controller. Single byte transfers are performed by
identifying the active data bus byte and activating only
one of the two signals. The function of the BE1–0 pins is
programmed using the BSWP bit (BIU Configuration
Control register, bit 6). BE1–0 are not required for ac-
cesses to MACE device registers.
TDTREQ
Transmit Data Transfer Request (Output)
CS
Transmit Data Transfer Request indicates there is room
in the Transmit FIFO for more data. TDTREQ is as-
serted when there are a minimum of 16 empty bytes in
the Transmit FIFO. TDTREQ can be programmed to re-
quest transmit data transfer when 16, 32 or 64 bytes are
available in the Transmit FIFO, by programming the
Transmit FIFO Watermark (XMTFW bits) in the FIFO
Configuration Control register. TDTREQ will be
Chip Select (Input)
Used to access the MACE device FIFOs and internal
registers locations using the ADD address bus. The
FIFOs may alternatively be directly accessed without
supplying the FIFO address, by using the FDS and
R/W pins.
Am79C940
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AMD
INTR
IEEE 1149.1 TEST ACCESS PORT (TAP)
INTERFACE
Interrupt (Output, Open Drain)
An attention signal indicating that one or more of the fol-
lowing status flags are set: XMTINT, RCVINT, MPCO,
RPCO, RCVCCO, CERR, BABL or JAB. Each interrupt
source can be individually masked. No interrupt condi-
tion can take place in the MACE device immediately af-
ter a hardware or software reset.
TCK
Test Clock (Input)
The clock input for the boundary scan test mode
operation. TCK can operate up to 10 MHz. TCK has an
internal (not SLEEP disabled) pull up.
TMS
RESET
Reset (Input)
Test Mode Select (Input)
A serial input bit stream used to define the specific
boundary scan test to be executed. TMS has an internal
(not SLEEP disabled) pull up.
Reset clears the internal logic. Reset can be asynchro-
nous to SCLK, but must be asserted for a minimum
duration of 15 SCLK cycles.
TDI
SCLK
System Clock (Input)
Test Data Input (Input)
The test data input path to the MACE device. TDI has an
internal (not SLEEP disabled) pull up.
The system clock input controls the operational fre-
quency of the slave interface to the MACE device and
the internal processing of frames. SCLK is unrelated to
the 20 MHz clock frequency required for the
802.3/Ethernet interface. The SCLK frequency range is
1 MHz–25 MHz.
TDO
Test Data Out (Output)
The test data output path from the MACE device.
GENERAL INTERFACE
XTAL1
Crystal Connection (Input)
EDSEL
System Clock Edge Select (Input)
EDSEL is a static input that allows System Clock
(SCLK) edge selection. If EDSEL is tied high, the bus in-
terface unit will assume falling edge timing. If EDSEL is
tied low, the bus interface unit will assume rising edge
timing, which will effectively invert the SCLK as it enters
the MACE device, i.e., the address, control lines (CS,
R/W, FDS, etc) and data are all latched on the rising
edge of SCLK, and data out is driven off the rising edge
of SCLK.
The internal clock generator uses a 20 MHz crystal that
is attached to pins XTAL1 and XTAL2. Internally, the
20 MHz crystal frequency is divided by two which deter-
mines the network data rate. Alternatively, an external
20 MHz CMOS-compatible clock signal can be used to
drive this pin. The MACE device supports the use of 50
pF crystals to generate a 20 MHz frequency which is
compatible with the IEEE 802.3 network frequency
tolerance and jitter specifications.
TC
Timing Control (Input)
XTAL2
Crystal Connection (Output)
The Timing Control input conditions the minimum num-
ber of System Clocks (SCLK) cycles taken to read or
write the internal registers and FIFOs. TC can be used
as a wait state generator, to allow additional time for
data to be presented by the host during a write cycle, or
allow additional time for the data to be latched during a
read cycle. TChas an internal (SLEEPdisabled) pull up.
The internal clock generator uses a 20 MHz crystal that
is attached to pins XTAL1 and XTAL2. If an external
clock generator is used on XTAL1, then XTAL2 should
be left unconnected.
SLEEP
Sleep Mode (Input)
Timing Control
Number of
The optimal power savings made is extracted by assert-
ingtheSLEEPpinwithboththeAutoWake(AWAKEbit)
and Remote Wake (RWAKE bit) functions disabled. In
this “deep sleep” mode, all outputs will be forced into
their inactive or high impedance state, and all inputs will
be ignored except for the SLEEP, RESET, SCLK, TCK,
TC
1
Clocks
2
3
0
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TMS, and TDI pins. SCLK must run for 5 cycles after the
assertion of SLEEP. During the “Deep Sleep”, the SCLK
input can be optionally suspended for maximum power
savings. Upon exiting “Deep Sleep”, the hardware
RESET pin must be asserted and the SCLK restored.
The system must delay the setting of the bits in the MAC
configuration Control Register of the internal analog
circuits by 1 ns to allow for stabilization.
PIN FUNCTIONS NOT AVAILABLE WITH
THE 80-PIN TQFP PACKAGE
In the 84-pin PLCC configuration, ALL the pins are used
while in the 100-pin PQFP version, 16 pins are specified
as No Connects. Moving to the 80-pin TQFP configura-
tion requires the removal of 4 pins. Since Ethernet con-
trollers with integrated 10BASE-T have analog portions
which are very sensitive to noise, power and ground
pins are not deleted. The MACE device does have
several sets of media interfaces which typically go un-
used in most designs, however. Pins from some of
these interfaces are deleted instead. Removed are
the following:
If the AWAKE bit is set prior to the activation of SLEEP,
the 10BASE-T receiver and the LNKST output pin re-
main operational.
If the RWAKE bit is set prior to SLEEP being asserted,
the Manchester encoder/decoder, AUI and 10BASE-T
cells remain operational, as do the SRD, SRDCLK and
SF/BD outputs.
■ TXDAT– (previously used for the DAI interface)
■ SRD (previously used for the EADI interface)
■ DTV (previously used for the host interface)
The input on XTAL1 must remain active for the AWAKE
or RWAKE features to operate. After exit from the Auto
Wake or Remote Wake modes, activation of hardware
RESET is not required when SLEEP is reasserted.
■ RXPOL (previously used as a receive frame
polarity LED driver)
Note that pins from four separate interfaces are re-
moved rather than removing all the pins from a single in-
terface. Each of these pins comes from one of the four
sides of the device. This is done to maintain symmetry,
thus avoiding bond out problems.
On deassertion of SLEEP, the MACE device will go
through an internally generated hardware reset se-
quence, requiring re-initialization of MACE registers.
Power Supply
In general, the most critical of the four removed pins are
TXDAT– and SRD. Depending on the application, either
the DAI or the EADI interface may be important. In most
designs, however, this will not be the case.
DVDD
Digital Power
There are four Digital VDD pins.
PINS REMOVED AND THEIR EFFECTS
TXDAT–
DVSS
Digital Ground
The removal of TXDAT– means that the DAI interface is
no longer usable. The DAI interface was designed to be
used with media types that do not require DC isolation
between the MAU and the DTE. Media which do not
require DC isolation can be implemented more simply
using the DAI interface, rather than the AUI interface. In
most designs this is not a problem because most
media requires DC isolation (10BASE-T, 10BASE2,
10BASE5) and will use the AUI port. About the only me-
dia which does not require DC isolation is 10BASE-F.
There are six Digital VSS pins.
AVDD
Analog Power
There are four analog VDD pins. Special attention
should be paid to the printed circuit board layout to avoid
excessive noise on the supply to the PLL in the
Manchester encoder/decoder (pins 66 and 83 in PLCC,
pins 67 and 88 in PQFP). These supply lines should be
kept separate from the DVDD lines as far back to the
power supply as is practically possible.
SRD
The SRD pin is an output pin used by the MACE device
to transfer a receive data stream to external address
detection logic. It is part of the EADI interface. This pin is
used to help interface the MACE device to an external
CAM device. Use of an external CAM is typically re-
quired when an application will operate in promiscuous
mode and will need perfect filtering (i.e., the internal
hash filter will not suffice). Example applications for this
AVSS
Analog Ground
There are two analog VSS pins. Special attention
should be paid to the printed circuit board layout to avoid
excessive noise on the PLL supply in Manchester en-
coder/decoder (pin 73 in PLCC, pin 74 in PQFP). These
supplylinesshouldbekeptseparatefromtheDVSS lines
as far back to the power supply as is practically possible.
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sort of operation are bridges and routers. Lack of
perfect filtering in these applications forces the CPU to
be more involved in filtering and thus either slows the
forwarding rates achieved or forces the use of a more
powerful CPU.
there are ways to ensure that a transfer is always valid
and so this pin is not required in many designs. For in-
stance, the TDTREQ and RDTREQ pins can be used to
monitor the state of the FIFOs to ensure that data trans-
fer only occurs at the correct times.
DTV
RXPOL
The DTV pin is part of the host interface to the MACE
device. It is used to indicate that a read or write cycle to
theMACEdevicewassuccessful. IfDTVisnotasserted
at the end of a cycle, the data transfer was not success-
ful. Basically, this will happen on a write to a full transmit
FIFO or a read from an empty receive FIFO. In general,
RXPOL is typically used to drive an LED indicating the
polarity of receive frames. This function is not neces-
sary for correct operation of the Ethernet and serves
strictly as a status indication to a user. The status of the
receive polarity is still available through the PHYCC
register.
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Receive FIFO is read (R/W high) or the Transmit FIFO
written (R/W low). The MACE device system interface
permits interleaved transmit and receive bus transfers,
allowing the Transmit FIFO to be filled (primed) while a
frame is being received from the network and/or read
from the Receive FIFO.
FUNCTIONAL DESCRIPTION
The Media Access Controller for Ethernet (MACE) chip
embodies the Media Access Control (MAC) and Physi-
cal Signaling (PLS) sub-layers of the 802.3 Standard.
The MACE device provides the IEEE defined Attach-
ment Unit Interface (AUI) for coupling to remote Media
Attachment Units (MAUs) or on-board transceivers.
The MACE device also provides a Digital Attachment In-
terface (DAI), by-passing the differential AUI interface.
In receive operation, the MACE device asserts Receive
Data Transfer Request (RDTREQ) when the FIFO con-
tains adequate data. For the first indication of a new re-
ceive frame, 64 bytes must be received, assuming
normal operation. Once the initial 64 byte threshold has
been reached, RDTREQ assertion and de-assertion is
dependent on the programming of the Receive FIFO
Watermark (RCVFW bits in the BIU Configuration Con-
trol register). The RDTREQ can be programmed to acti-
vate when there are 16, 32 or 64 bytes of data available
in the Receive FIFO. Enable Receive (ENRCV bit in
MAC Configuration Control register) must be set to as-
sert RDTREQ. If the Runt Packet Accept feature is in-
voked (RPA bit in User Test Register), RDTREQ will be
asserted for receive frames of less than 64 bytes on the
basis of internal and/or external address match only.
When RPA is set, RDTREQ will be asserted when the
entire frame has been received or when the initial 64
byte threshold has been exceeded. See the FIFO Sub-
Systems section for further details.
The system interface provides a fundamental data con-
duit to and from an 802.3 network. The MACE device in
conjunction with a user defined DMA engine, provides
an 802.3 interface tailored to a specific application.
In addition, the MACE device can be combined with
similarly architected peripheral devices and a multi-
channel DMA controller, thereby providing the system
with access to multiple peripheral devices with a single
master interface to memory.
Network Interfaces
The MACE device can be connected to an 802.3 net-
work using any one of the AUI, 10 BASE-T, DAI and
GPSI network interfaces. The Attachment Unit Inter-
face (AUI) provides an IEEE compliant differential inter-
face to a remote MAU or an on-board transceiver. An
integrated 10BASE-T MAU provides a direct interface
for twisted pair Ethernet networks. The DAI port can
connect to local transceiver devices for 10BASE2,
10BASE-T or 10BASE-F connections. A General Pur-
pose Serial Interface (GPSI) is supported, which effec-
Note that the Receive FIFO may not contain 64 data
bytes at the time RDTREQ is asserted, if the automatic
pad stripping feature has been enabled (ASTRP RCV
bit in the Receive Frame Control register) and a mini-
mum length packet with pad is received. The MACE de-
vice will check for the minimum received length from the
network, strip the pad characters, and pass only the
data frame through the Receive FIFO.
tively
bypasses
the
integrated
Manchester
encoder/decoder, and allows direct access to/from the
integral 802.3 Media Access Controller (MAC) to pro-
vide support for external encoding/decoding schemes.
The interface in use is determined by the PORTSEL
[1–0] bits in the PLS Configuration Control register.
If the Low Latency Receive feature is enabled (LLRCV
bit set in Receive Frame Control Register), RDTREQ
will be asserted once a low watermark threshold has
beenreached(12bytesplussomeadditionalsynchroni-
zation time). Note that the system interface will there-
fore be exposed to potential disruption of the receive
frame due to a network condition (see the FIFO Sub-
System description for additional details).
The EADI port does not provide network connectivity,
but allows an optional external circuit to assist in receive
packet accept/reject.
System Interface
In transmit operation, the MACE device asserts Trans-
mitDataTransferRequest(TDTREQ)dependentonthe
programming of the Transmit FIFO Watermark
(XMTFW bits in the BIU Configuration Control register).
TDTREQ will be permanently asserted when the Trans-
mit FIFO is empty. The TDTREQ can be programmed to
activate when there are 16, 32 or 64 bytes of space
available in the Transmit FIFO. Enable Transmit
(ENXMT bit in MAC Configuration Control register)
must be set to assert TDTREQ. Write cycles to the
Transmit FIFO will not return DTV if ENXMT is disabled,
and no data will be written. The MACE device will com-
mence the preamble sequence once the Transmit Start
Point (XMTSP bits in BIU Configuration Control regis-
ter) threshold is reached in the Transmit FIFO.
The MACE device is a slave register based peripheral.
All transfers to and from the device, including data, are
performed using simple memory or I/O read and write
commands. Access to all registers, including the Trans-
mit and Receive FIFOs, are performed with identical
read or write timing. All information on the system inter-
face is synchronous to the system clock (SCLK), which
allows simple external logic to be designed to interro-
gate the device status and control the network data flow.
The Receive and Transmit FIFOs can be read or written
by driving the appropriate address lines and asserting
CSandR/W. AnalternativeFIFOaccessmechanismal-
lows the use of the FDS and the R/W lines, ignoring the
address lines (ADD4–0). The state of the R/W line in
conjunction with the FDS input determines whether the
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The Transmit FIFO data will not be overwritten until at
least 512 data bits have been transmitted onto the net-
work. If a collision occurs within the slot time (512 bit
time) window, the MACE device will generate a jam se-
quence (a 32-bit all zeroes pattern) before ceasing the
transmission. The Transmit FIFO will be reset to point at
the start of the transmit data field, and the message will
beretriedaftertherandomback-offintervalhasexpired.
and by asserting BE0. For BSWP = 1, reading from or
writing to DBUS15–8 is accomplished by asserting BE0,
and allows the byte stream to be transferred in byte
order.
When word operations are required, BSWP ensures
thatthebyteorderingofthetargetmemoryiscompatible
with the 802.3 requirement to send/receive the data
stream in byte ascending order. With BSWP = 0, the
data transferred to/from the FIFO assumes that byte n
will be on DBUS7–0 (activated by BE0) and byte n+1 will
be on DBUS15–8 (activated by BE1). With BSWP = 1,
the data transferred to/from the FIFO assumes that byte
n will be presented on DBUS15–8 (activated by BE0),
and byte n+1 will be on DBUS7–0 (activated by BE1).
DETAILED FUNCTIONS
Block Level Description
The following sections describe the major sub-blocks of
and the external interfaces to the MACE device.
Bus Interface Unit (BIU)
There are some additional special cases to the above
generalized rules, which are as follows:
The BIU performs the interface between the host or sys-
tembusandtheTransmitandReceiveFIFOs, aswellas
all chip control and status registers. The BIU can be con-
figured to accept data presented in either little-endian or
big endianformat, minimizingtheexternallogicrequired
to access the MACE device internal FIFOs and regis-
ters. In addition, the BIU directly supports 8-bit transfers
andincorporatesfeaturestosimplifyinterfacingto32-bit
systems using external latches.
(a) When performing byte read operations, both halves
of the data bus are driven with identical data, effec-
tively allowing the user to arbitrarily read from either
the upper or lower data bus, when only one of the
byte enables is activated.
(b) When byte write operations are performed, the
Transmit FIFO latency is affected. See the FIFO
Sub-System section for additional details.
Externally, the FIFOs appear as two independent regis-
ters located at individual addresses. The remainder of
the internal registers occupy 30 additional consecutive
addresses, and appear as 8-bits wide.
(c) If a word read is performed on the last data byte of a
receive frame (EOF is asserted), and the message
contained an odd number of bytes but the host re-
quested a word operation by asserting both BE0
and BE1, then the MACE device will present one
valid and one non-valid byte on the data bus. The
placement of valid data for the data byte is depend-
ent on the target memory architecture. Regardless
of BSWP, the single valid byte will be read from the
BE0 memory bank. If BSWP = 0, BE0 corresponds
to DBUS7–0; if BSWP = 1, BE0 corresponds to
DBUS15–8.
BIU to FIFO Data Path
The BIU operates assuming that the 16-bit data path to/
from the internal FIFOs is configured as two independ-
entbytepaths, activatedbytheByteEnablesignalsBE0
and BE1.
BE0 and BE1 are only used during accesses to the
16-bit wide Transmit and Receive FIFOs. After hard-
ware or software reset, the BSWP bit will be cleared.
FIFO accesses to the MACE device will operate assum-
ing an Intel 80x86 type memory convention (most sig-
nificant byte of a word stored in the higher addressed
byte). Word data transfers to/from the FIFOs over the
DBUS15–0 lines will have the least significant byte lo-
cated on DBUS7–0 (activated by BE0) and the most sig-
nificant byte located on DBUS15–8 (activated by BE1).
(d) If a byte read is performed when the last data byte is
read for a receive frame (when the MACE device
activates the EOF signal), then the same byte will
be presented on both the upper and lower byte of
the data bus, regardless of which byte enable was
activated (as is the case for all byte read opera-
tions).
FIFOdatacanbereadorwrittenusingeitherbyteand/or
word operations.
(e) When writing the last byte in a transmit message to
the Transmit FIFO, the portion of the data bus that
the last byte is transferred over is irrelevant, provid-
ing the appropriate byte enable is used. For
BSWP = 0, data can be presented on DBUS7–0 us-
ing BE0 or DBUS15–8 using BE1. For BSWP = 1,
data can be presented on DBUS7–0 using BE1 or
DBUS15–8 using BE0.
If byte operation is required, read/write transfers can be
performed on either the upper or lower data bus by as-
serting the appropriate byte enable. For instance with
BSWP = 0, reading from or writing to DBUS15–8 is ac-
complished by asserting BE1, and allows the data
stream to be read from or written to the appropriate
FIFO in byte order (byte 0, byte 1,....byte n). It is equally
valid to read or write the data stream using DBUS7–0
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(f) When neither BE0 nor BE1 are asserted, no data
transfer will take place. DTV will not be asserted.
FIFO Sub-System
The MACE device has two independent FIFOs, with
128-bytes for receive and 136-bytes for transmit opera-
tions. The FIFO sub-system contains both the FIFOs,
and the control logic to handle normal and exception re-
lated conditions.
Byte Alignment For FIFO Read Operations
BE0
0
BE1
0
BSWP
DBUS7–0 DBUS15–8
0
0
0
0
1
1
1
1
n
n
n+1
n
0
1
The Transmit and Receive FIFOs interface on the net-
work side with the serializer/de-serializer in the MAC en-
gine. The BIU provides access between the FIFOs and
the host system to enable the movement of data to and
from the network.
1
0
n
n
1
1
X
X
n
0
0
n+1
n
0
1
n
Internally, the FIFOs appear to the BIU as independent
16-bit wide registers. Bytes or words can be written to
the Transmit FIFO (XMTFIFO), or read from the Re-
ceive FIFO (RCVFIFO). Byte and word transfers can be
mixed in any order. The BIU will ensure correct byte or-
dering dependent on the target host system, as deter-
mined by the programming of the BSWP bit in the BIU
Configuration Control register.
1
0
n
n
1
1
X
X
Byte Alignment For FIFO Write Operations
BE0
0
BE1
0
BSWP
DBUS7–0 DBUS15–8
0
0
0
0
1
1
1
1
n
n
n+1
X
0
1
The XMTFIFO and RCVFIFO have three different
modes of operation. These are Normal (Default), Burst
and Low Latency Receive. Default operation will be
used after the hardware RESETpin or software SWRST
bit have been activated. The remainder of this general
description applies to all modes except where specific
differences are noted.
1
0
X
n
1
1
X
X
0
0
n+1
X
n
0
1
n
1
0
n
X
1
1
X
X
Transmit FIFO—General Operation:
When writing bytes to the XMTFIFO, certain restrictions
apply. These restrictions have a direct influence on the
latency provided by the FIFO to the host system. When
a byte is written to the FIFO location, the entire word lo-
cation is used. The unused byte is marked as a hole in
the XMTFIFO. These holes are skipped during the seri-
alization process performed by the MAC engine, when
the bytes are unloaded from the XMTFIFO.
BIU to Control and Status
Register Data Path
All registers in the address range 2–31 are 8-bits wide.
Whenareadcycleisexecutedonanyoftheseregisters,
the MACE device will drive data on both bytes of the
data bus, regardless of the programming of BSWP.
When a write cycle is executed, the MACE device
strobes in data based on the programming of BSWP as
shown in the tables below. All accesses to addresses
2–31 are independent of the BE0 and BE1 pins.
For instance, assume the Transmit FIFO Watermark
(XMTFW) is set for 32 write cycles. If the host writesbyte
wide data to the XMTFIFO, after 36 write cycles there
will be space left in the XMTFIFO for only 32 more write
cycles. Therefore TDTREQ will de-assert even though
only 36-bytes of data have been loaded into the
XMTFIFO. Transmission will not commence until
64-bytes or the End-of-Frame are available in the
XMFIFO, so transmission would not start, and TDTREQ
would remain de-asserted. Hence for byte wide data
transfers, the XMTFW should be programmed to the 8
or 16 write cycle limit, or the host should ensure that suf-
ficient data will be written to the XMTFIFO after
TDTREQ has been de-asserted (which is permitted), to
guarantee that the transmission will commence. A third
alternative is to program the Transmit Start Point
(XMTSP) in the BIU Configuration Control register to
below the 64-byte default; thereby imposing a lower la-
tency to the host system requiring additional data to
Byte Alignment For Register Read Operations
BE0
BE1
BSWP
DBUS7–0 DBUS15–8
X
X
0
Read
Data
Read
Data
X
X
1
Read
Data
Read
Data
Byte Alignment For Register Write Operations
BE0
BE1
BSWP
DBUS7–0 DBUS15–8
X
X
0
Write
Data
X
X
X
1
X
Write
Data
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ensure the XMTFIFO does not underflow during the
transmit process, versus using the default XMTSP
value. Note that if 64 single byte writes are executed on
the XMTFIFO, and the XMTSP is set to 64-bytes, the
transmission will commence, and all 64-bytes of infor-
mation will be accepted by the XMTFIFO.
The DTV pin will indicate the successful acceptance of
data by the Transmit FIFO.
As another example, assume again that the XMTFW is
programmed for 32 write cycles. If the host writes word
wide data continuously to the XMTFIFO, the TDTREQ
will deassert when 36 writes have executed on the
XMTFIFO, at which point 72-bytes will have been writ-
ten to the XMTFIFO, the 64-byte XMTSP will have been
exceeded and the transmission of preamble will have
commenced. TDTREQ will not re-assert until the trans-
missionofthepacketdatahascommencedandthepos-
sibility of losing data due to a collision within theslot time
is removed (512 bits have been transmitted without a
collision indication). Assuming that the host actually
stopped writing data after the initial 72-bytes, there will
be only 16-bytes of data remaining in the XMTFIFO
(8-bytes of preamble/SFD plus 56-bytes of data have
been transmitted), corresponding to 12.8 µs of latency
before an XMTFIFO underrun occurs. This latency is
considerably less than the maximum possible 57.6 µs
the system may have assumed. If the host had contin-
ued with the block transfer until 64 write cycles hadbeen
performed, 128-bytes would have been written to the
XMTFIFO, and 72-bytes of latency would remain
(57.6 µs) when TDTREQ was re-asserted.
Thenumberofwritecyclesthatthehostusestowritethe
packet into the Transmit FIFO will also directly influence
the amount of space utilized by the transmit message. If
the number of write cycles (n) required to transfer a
packet to the Transmit FIFO is even, the number of
bytes used in the Transmit FIFO will be 2*n. If the num-
ber of write cycles required to transfer a packet to the
Transmit FIFO is odd, the number of bytes used in the
TransmitFIFOwillbe2*n+2becausetheEndOfFrame
indication in the XMTFIFO is always placed at the end of
a 4-byte boundary. For example, a 32-byte message
written as bytes (n = 32 cycles) will use 64-bytes of
space in the Transmit FIFO (2*n = 64), whereas a
65-byte message written as 32 words and 1 byte (n = 33
cycles) would use 68-bytes (2*n + 2 = 68) .
The Transmit FIFO has been sized appropriately to
minimize the system interface overhead. However, con-
sideration must be given to overall system design if byte
writes are supported. In order to guarantee that suffi-
cient space is present in the XMTFIFO to accept the
number of write cycles programmed by the XMTFW (in-
cluding an End Of Frame delimiter), TDTREQ may go
inactive before the XMTSP threshold is reached when
usingthenonburstmode(XMTBRST=0). Forinstance,
assume that the XMTFW is programmed to allow 32
write cycles (default), and XMTSP is programmed to re-
quire64bytes(default)beforestartingtransmission. As-
suming that the host bursts the transmit data in a 32
cycle block, writing a single byte anywhere within this
block will mean that XMTSP will not have been reached.
This would be a typical scenario if the transmit data
buffer was not aligned to a word boundary. The MACE
device will continue to assert TDTREQ since an addi-
tional 36 write cycles can still be executed. If the host
starts a second burst, the XMTSP will be reached, and
TDTREQ will deassert when less that 32 write cycle can
be performed although the data written by the host will
continue to be accepted.
Transmit FIFO—Burst Operation:
The XMTFIFO burst mode, programmed by the
XMTBRST bit in the FIFO Configuration Control regis-
ter, modifies TDTREQ behavior. The assertion of
TDTREQ is controlled by the programming of the
XMTFW bits, such that when the specified number of
write cycles can be guaranteed (8, 16 or 32), TDTREQ
will be asserted. TDTREQ will be de-asserted when the
XMTFIFO can only accept a single write cycle (one word
write including an End Of Frame delimiter) allowing the
external device to burst data into the XMTFIFO when
TDTREQ is asserted, and stop when TDTREQ is
deasserted.
Receive FIFO—General Operation:
The Receive FIFO contains additional logic to ensure
that sufficient data is present in the RCVFIFO to allow
the specified number of bytes to be read, regardless of
the ordering of byte/word read accesses. This has an
impact on the perceived latency that the Receive FIFO
provides to the host system. The description and table
below outline the point at which RDTREQ will be as-
serted when the first duration of the packet has been re-
ceived and when any subsequent transfer of the packet
to the host system is required.
The host must be aware that additional space exists in
theXMTFIFOalthoughTDTREQbecomesinactive, and
must continue to write data to ensure the XMTSP
threshold is achieved. No transmit activity will com-
mence until the XMTSP threshold is reached. Once 36
write cycles have been executed.
No preamble/SFD bytes are loaded into the Receive
FIFO. All references to bytes pass through the receive
FIFO. These references are received after the pream-
ble/SFD sequence.
NotethatwritecyclescanbeperformedtotheXMTFIFO
even if the TDTREQ is inactive. When TDTREQ is as-
serted, it guarantees that a minimum amount of space
exists, when TDTREQ is deasserted, it does not neces-
sarily indicate that there is no space in the XMTFIFO.
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The first assertion of RDTREQ for a packet will occur af-
ter the longer of the following two conditions is met:
guaranteed. They are required for all threshold values,
but in the case of the 16 and 32-byte thresholds, the re-
quirement that the slot time criteria is met dominates.
Any subsequent assertion of RDTREQ necessary to
complete the transfer of the packet will occur after the
RCVFW threshold is reached plus an additional 12
bytes. The table below also outlines the latency pro-
vided by the MACE device when the RDTREQ is
asserted.
■ 64-bytes have been received (to assure runt pack-
ets and packets experiencing collision within the slot
time will be rejected).
■ TheRCVFWthresholdisreachedplusanadditional
12 bytes. The additional 12 bytes are necessary to en-
sure that any permutation of byte/word read access is
Receive FIFO Watermarks, RDTREQ Assertion and Latency
Bytes Required for Bytes of Latency Bytes Required for
Bytes of Latency After
Subsequent Assertion
of RDTREQ
RCVFW
[1–0]
First Assertion of
After First Assertion Subsequent Assertion
RDTREQ
of RDTREQ
of RDTREQ
00
01
10
11
64
64
76
XX
64
64
52
XX
28
44
76
XX
100
84
52
XX
Receive FIFO—Burst Operation:
Note however that this mode places significant burden
on the host processor. The receiving MACE device will
nolongerdeleteruntpackets. Aruntpacketwillhavethe
Receive Frame Status appended to the receive data
which the host must read as normal. The MACE device
will not attempt to delete runt packets from the
RCVFIFO in the Low Latency Receive mode. Collision
fragments will also be passed to the host if they are de-
tected after the 12-byte threshold has been reached. If a
collision occurs, the Receive Frame Status (RCVFS)
will be appended to the data successfully received in the
RCVFIFO up to the point the collision was detected. No
additional receive data will be written to the RCVFIFO.
Note that the RCVFS will not become available until af-
ter the receive activity ceases. The collision indication
(CLSN) in the Receive Status (RCVSTS) will be set, and
the Receive Message Byte Count (RCVCNT) will be the
correct count of the total duration of activity, including
the period that collision was detected. The detection of
normal (slot time) collisions versus late collisions can
only be made by counting the number of bytes that were
successfully received prior to the termination of the
packet data.
The RCVFIFO also provides a burst mode capability,
programmed by the RCVBRST bit in the FIFO Configu-
ration Control register, to modify the operation of
RDTREQ.The assertion of RDTREQ will occur accord-
ing to the programming of the RCVFW bits. RDTREQ
will be de-asserted when the RCVFIFO can only provide
a single read cycle (one word read). This allows the ex-
ternal device to burst data from the RCVFIFO once
RDTREQ is asserted, and stop when RDTREQ is
deasserted.
Receive FIFO—Low Latency Receive Operation:
The LOW Latency Receive mode can be programmed
using the Low Latency Receive bit (LLRCV in the Re-
ceive Frame Control register). This effectively causes
the assertion of RDTREQ to be directly coupled to the
low watermark of 12 bytes in the RCVFIFO. Once the
12-byte threshold is reached (plus some internal syn-
chronization delay of less than 1 byte), RDTREQ will be
asserted, and will remain active until the RCVFIFO can
support only one read cycle (one word of data), as in the
burst operation described earlier.
In all cases where the reception ends prematurely (runt
or collision), the data that was successfully received
prior to the termination of reception must be read from
the RCVFIFO before the RCVFS bytes are available.
The intended use for the Low Latency Receive mode is
to allow fast forwarding of a received packet in a bridge
application. In this case, the receiving process is made
aware of the receive packet after only 9.6 µs, instead of
waiting up to 60.8 µs (76-bytes) necessary for the initial
assertion of RDTREQ. An Ethernet-to-Ethernet bridge
employing the MACE device (on all the Ethernet con-
nections) with the XMTSP of all MACE controller
XMTFIFOs set to the minimum (4-bytes), forwarding of
a receive packet can be achieved within a sub 20 µs de-
lay including processing overhead.
Media Access Control (MAC)
The Media Access Control engine is the heart of the
MACE device, incorporating the essential protocol re-
quirements for operation of a compliant Ethernet/802.3
node, and providing the interface between the FIFO
Am79C940
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sub-system and the Manchester Encoder/Decoder
(MENDEC).
rently permitted, the MACE device will commence the
7 byte preamble sequence (10101010b, where first bit
transmitted is a 1). The MACE device will subsequently
append the Start Frame Delimiter (SFD) byte
(10101011) followed by the serialized data from the
Transmit FIFO. Once the data has been completed, the
MACE device will append the FCS (most significant bit
first) computed on the entire data portion of the
message.
The MAC engine is fully compliant to Section 4 of ISO/
IEC 8802-3 (ANSI/IEEE Standard 1990 Second edition)
and ANSI/IEEE 802.3 (1985).
The MAC engine provides enhanced features, pro-
grammed through the Transmit Frame Control and Re-
ceive Frame Control registers, designed to minimize
host supervision and pre or post message processing.
These features include the ability to disable retries after
a collision, dynamic FCS generation on a packet-by-
packetbasis, andautomaticpadfieldinsertionanddele-
tion to enforce minimum frame size attributes.
Note that the user is responsible for the correct ordering
and content in each of the fields in the frame, including
the destination address, source address, length/type
and packet data.
The receive section of the MACE device will detect an
incoming preamble sequence and lock to the encoded
clock. The internal MENDEC will decode the serial bit
stream and present this to the MAC engine. The MAC
will discard the first 8-bits of information before search-
ing for the SFD sequence. Once the SFD is detected, all
subsequent bits are treated as part of the frame. The
MACE device will inspect the length field to ensure mini-
mum frame size, strip unnecessary pad characters (if
enabled), and pass the remaining bytes through the Re-
ceive FIFO to the host. If pad stripping is performed, the
MACE device will also strip the received FCS bytes, al-
though the normal FCS computation and checking will
occur. Note that apart from pad stripping, the frame will
be passed unmodified to the host. If the length field has
a value of 46 or greater, the MACE device will not at-
tempt to validate the length against the number of bytes
contained in the message.
The two primary attributes of the MAC engine are:
■ Transmit and receive message data encapsulation
–
–
–
Framing (frame boundary delimitation, frame
synchronization)
Addressing (source and destination address
handling)
Error detection (physical medium transmission
errors)
■ Media access management
–
–
Medium allocation (collision avoidance)
Contention resolution (collision handling)
Transmit and Receive Message Data
Encapsulation
Data passed to the MACE device Transmit FIFO will be
assumed to be correctly formatted for transmission over
the network as a valid packet. The user is required to
pass the data stream for transmission to the MACE chip
in the correct order, according to the byte ordering con-
vention programmed for the BIU.
If the frame terminates or suffers a collision before
64-bytes of information (after SFD) have been received,
the MACE device will automatically delete the frame
from the Receive FIFO, without host intervention. Note
however, that if the Low Latency Receive option has
been enabled (LLRCV = 1 in the Receive Frame Control
register), the MACE device will not delete receive
frames which experience a collision once the 12-byte
low watermark has been reached (see the FIFO Sub-
System section for additional details).
The MACE device provides minimum frame size en-
forcement for transmit and receive packets. When
APADXMT=1(default), transmitmessageswillbepad-
ded with sufficient bytes (containing 00h) to ensure that
the receiving station will observe an information field
(destination address, source address, length/type, data
and FCS) of 64-bytes. When ASTRP RCV = 1 (default),
the receiver will automatically strip pad and FCS bytes
from the received message if the value in the length field
is below the minimum data size (46-bytes). Both fea-
tures can be independently over-ridden to allow illegally
short (less than 64-bytes of packet data) messages to
be transmitted and/or received.
Addressing (Source and Destination
Address Handling)
The first 6-bytes of information after SFD will be inter-
preted as the destination address field. The MACE de-
vice provides facilities for physical, logical and
broadcastaddressreception. Inaddition, multiplephysi-
cal addresses can be constructed (perfect address fil-
tering) using external logic in conjunction with the EADI
interface.
Framing (Frame Boundary Delimitation,
Frame Synchronization)
Error Detection (Physical Medium
Transmission Errors)
The MACE device will autonomously handle the con-
struction of the transmit frame. When the Transmit FIFO
has been filled to the predetermined threshold (set by
XMTSP), and providing access to the channel is cur-
The MACE device provides several facilities which
report and recover from errors on the medium. In addi-
tion, the network is protected from gross errors due to
34
Am79C940
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inability of the host to keep pace with the MACE device
activity.
and Runt Packet Count to be used for network statistics
and utilization calculations.
On completion of transmission, the MACE device will re-
port the Transmit Frame Status for the frame. The exact
number of transmission retry attempts is reported
(ONE, MORE used with XMTRC, or RTRY), and
whether the MACE device had to Defer (DEFER) due to
channel activity. In addition, Loss of Carrier is reported,
indicting that there was an interruption in the ability of
the MACE device to monitor its own transmission. Re-
peated LCAR errors indicate a potentially faulty trans-
ceiver or network connection. Excessive Defer
(EXDEF) will be reported in the Transmit Retry Count
register if the transmit frame had to wait for an abnor-
mally long period before transmission.
Note that if the MACE device detects a received packet
which has a 00b pattern in the preamble (after the first
8-bits which are ignored), the entire packet will be ig-
nored. The MACE device will wait for the network to go
inactive before attempting to receive additional frames.
Media Access Management
The basic requirement for all stations on the network
is to provide fairness of channel allocation. The
802.3/Ethernetprotocolsdefineamediaaccessmecha-
nism which permits all stations to access the channel
with equality. Any node can attempt to contend for the
channel by waiting for a predetermined time (Inter Pack-
et Gap interval) after the last activity, before transmitting
on the media. The channel is a bus or multidrop commu-
nications medium (with various topological configura-
tions permitted) which allows a single station to transmit
and all other stations to receive. If two nodes simultane-
ously contend for the channel, their signals will interact
causing loss of data, defined as a collision. It is the re-
sponsibility of the MAC to attempt to avoid and recover
from a collision, to guarantee data integrity for the end-
to-end transmission to the receiving station.
Additional transmit error conditions are reported
through the Interrupt Register.
The Late Collision (LCOL) error indicates that the trans-
mission suffered a collision after the slot time. This is
indicative of a badly configured network. Late collisions
should not occur in normal operating network.
The Collision Error (CERR) indicates that the trans-
ceiverdidnotrespondwithanSQETestmessagewithin
the predetermined time after a transmission completed.
This may be due to a failed transceiver, disconnected or
faulty transceiver drop cable, or the fact the transceiver
does not support this feature (or it is disabled).
Medium Allocation (Collision Avoidance)
The IEEE 802.3 Standard (ISO/IEC 8802-3 1990) re-
quires that the CSMA/CD MAC monitors the medium for
traffic by watching for carrier activity. When carrier is de-
tected, the media is considered busy, and the MAC
should defer to the existing message.
In addition to the reporting of network errors, the MACE
device will also attempt to prevent the creation of any
network error caused by inability of the host to service
the MACE device. During transmission, if the host fails
to keep the Transmit FIFO filled sufficiently, causing an
underflow, the MACE device will guarantee the
message is either sent as a runt packet (which will be
deleted by the receiving station) or has an invalid FCS
(which will also allow the receiving station to reject the
message).
The IEEE 802.3 Standard also allows optional two part
deferral after a receive message.
See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.1:
“NOTE : It is possible for the PLS carrier sense
indication to fail to be asserted during a collision
on the media. If the deference process simply
times the interFrame gap based on this indica-
tion it is possible for a short interFrame gap to
be generated, leading to a potential reception
failure of a subsequent frame. To enhance sys-
tem robustness the following optional meas-
ures, as specified in 4.2.8, are recommended
when interFrameSpacingPart1 is other than
zero:”
The status of each receive message is passed via the
Receive Frame Status bytes. FCS and Framing errors
(FRAM) are reported, although the received frame is still
passed to the host. The FRAM error willonly be reported
if an FCS error is detected and there are a non integral
number of bytes in the message. The MACE device will
ignore up to seven additional bits at the end of a mes-
sage (dribbling bits), which can occur under normal net-
work operating conditions. The reception of eight
additional bits will cause the MACE device to de-serial-
ize the entire byte, and will result in the received mes-
sage and FCS being modified.
(1) Upon completing a transmission, start timing the
interpacket gap, as soon as transmitting and
carrierSense are both false.
(2) When timing an interFrame gap following reception,
reset the interFrame gap timing if carrierSense
becomes true during the first 2/3 of the interFrame gap
timing interval. During the final 1/3 of the interval the
timer shall not be reset to ensure fair access to the me-
Received messages which suffer a collision after
64-byte times (after SFD) will be marked to indicate they
have suffered a late collision (CLSN). Additional count-
ers are provided to report the Receive Collision Count
Am79C940
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dium. An initial period shorter than 2/3 of the interval is
permissible including zero.”
to occur, no SQE test occurs in the DTE. The
duration of the window shall be at least 4.0 µs
but no more than 8.0 µs. During the time win-
dow the Carrier Sense Function is inhibited.”
The MAC engine implements the optional receive two
part deferral algorithm, with a first part inter-frame-
spacing time of 6.0 µs. The second part of the inter-
frame-spacing interval is therefore 3.6 µs.
The MACE device implements a carrier sense blinding
period within 0 µs–4.0 µs from deassertion of carrier
sense after transmission. This effectively means that
when transmit two part deferral is enabled (DXMT2PD
in the MAC Configuration Control register is cleared)the
IFS1 time is from 4 µs to 6 µs after a transmission. How-
ever, sinceIPGshrinkagebelow4µswillnotbeencoun-
tered on correctly configured networks, and since the
fragment size will be larger than the 4 µs blinding win-
dow, then the IPG counter will be reset by a worst case
IPG shrinkage/fragment scenario and the MACE device
will defer its transmission. The MACE chip will not re-
start the carrier sense blinding period if carrier is de-
tected within the 4.0–6.0 µs portion of IFS1, but will
restart timing of the entire IFS1 period.
The MACE device will perform the two part deferral al-
gorithm as specified in Section 4.2.8 (Process Defer-
ence). The Inter Packet Gap (IPG) timer will start timing
the 9.6 µs InterFrameSpacing after the receive carrier is
de-asserted. During the first part deferral (Inter-
FrameSpacingPart1–IFS1) the MACE device will defer
any pending transmit frame and respond to the receive
message. The IPG counter will be reset to zero continu-
ously until the carrier deasserts, at which point the IPG
counter will resume the 9.6 µs count once again. Once
the IFS1 period of 6.0µs has elapsed, the MACE device
will begin timing the second part deferral (Inter-
FrameSpacingPart2–IFS2) of 3.6µs. Once IFS1 has
completed, and IFS2 has commenced, the MACE chip
will not defer to a receive packet if a transmit packet is
pending. This means that the MACE device will not at-
tempt to receive an incoming packet, and it will start to
transmit at 9.6 µs regardless of network activity, forcing
a collision if an existing transmission is in progress. The
MACE device will guarantee to complete the preamble
(64-bit) and jam (32-bit) sequence before ceasing trans-
mission and invoking the random backoff algorithm.
Contention Resolution (Collision Handling)
Collision detection is performed and reported to the
MAC engine either by the integrated Manchester En-
coder/Decoder (MENDEC), or by use of an external
function (e.g. Serial Interface Adaptor, Am7992B) utiliz-
ing the GPSI.
If a collision is detected before the complete preamble/
SFD sequence has been transmitted, the MACE device
will complete the preamble/SFD before appending the
jam sequence. If a collision is detected after the pream-
ble/SFD has been completed, but prior to 512 bits being
transmitted, the MACE device will abort the transmis-
sion, and append the jam sequence immediately. The
jam sequence is a 32-bit all zeroes pattern.
In addition to the deferral after receive process, the
MACEdevicealsoallowstransmittwopartdeferraltobe
implemented as an option. The option can be disabled
using the DXMT2PD bit in the MAC Configuration Con-
trol register. Two part deferral after transmission is use-
ful for ensuring that severe IPG shrinkage cannot occur
in specific circumstances, causing a transmit message
to follow a receive message so closely, as to make them
indistinguishable.
The MACE device will attempt to transmit a frame a total
of 16 times (initial attempt plus 15 retries) due to normal
collisions (those within the slot time). Detection of colli-
sion will cause the transmission to be re-scheduled, de-
pendent on the backoff time that the MACE device
computes. Each collision which occurs during the trans-
mission process will cause the value of XMTRC in the
Transmit Retry Count register to be updated. If a single
retry was required, the ONE bit will be set in the Trans-
mit Frame Status. If more than one retry was required,
the MORE bit will be set, and the exact number of at-
tempts can be determined (XMTRC+1). If all 16 at-
tempts experienced collisions, the RTRY bit will be set
(ONE and MORE will be clear), and the transmit
message will be flushed from the XMTFIFO, either by
resetting the XMTFIFO (if no End-of-Frame tag exists)
or by moving the XMTFIFO read pointer to the next free
location (If an End-of-Frame tag is present). If retries
havebeendisabledbysettingtheDRTRYbit, theMACE
device will abandon transmission of the frame on detec-
tion of the first collision. In this case, only the RTRY bit
During the time period immediately after a transmission
has been completed, the external transceiver (in the
case of a standard AUI connected device), should gen-
eratetheSQETestmessage(anominal10MHzburstof
5-15 BT duration) on the CI± pair (within 0.6–1.6 µs after
the transmission ceases). During the time period in
whichtheSQETestmessageisexpectedtheMACEde-
vice will not respond to receive carrier sense.
See ANSI/IEEE Std 802.3-1990 Edition,
7.2.4.6 (1)):
“At the conclusion of the output function, the
DTE opens a time window during which it ex-
pects to see the signal_quality_error signal as-
serted on the Control In circuit. The time
window begins when the CARRIER_STATUS
becomes CARRIER_OFF. If execution of the
output function does not cause CARRIER_ON
36
Am79C940
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will be set and the transmit message will be flushed from
the XMTFIFO. The RTRY condition will cause the de-
assertion of TDTREQ, and the assertion of the INTRpin,
providing the XMTINTM bit is cleared.
or it will be marked as a receive late collision, using the
CLSN bit in the Receive Frame Status register. All
frames which suffer a collision within the slot time will be
deleted in the Receive FIFO without requesting host in-
tervention, providingthattheLLRCVbit(ReceiveFrame
Control) is not set. Runt packets which suffer a collision
will be aborted regardless of the state of the RPA bit
(User Test Register). If the collision commences after
the slot time, the MACE device receiver will stop send-
ing collided packet data to the Receive FIFO and the
packet data read by the system will contain the amount
of data received to the point of collision; the CLSN bit in
the Receive Frame Status register will indicate the re-
ceive late collision. Note that the Receive Message Byte
Count will report the total number of bytes during the re-
ceive activity, including the collision.
If a collision is detected after 512 bit times have been
transmitted, the collision is termed a late collision. The
MACE device will abort the transmission, append the
jam sequence and set the LCOL bit in the Transmit
Frame Status. No retry attempt will be scheduled on de-
tection of a late collision, and the XMTFIFO will be
flushed. The late collision condition will cause the de-as-
sertion of TDTREQ, and the assertion of the INTR pin,
providing the XMTINTM bit is cleared.
The IEEE 802.3 Standard requires use of a truncated bi-
nary exponential backoff algorithm which provides a
controlled pseudo random mechanism to enforce the
collision backoff interval, before re-transmission is
attempted.
In all normal receive collision cases, the MACE device
eliminates the transfer of packet data across the host
bus. In a receive late collision condition, the MACE chip
minimizes the amount transferred. These functions pre-
serve bus bandwidth utilization.
See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.5:
“At the end of enforcing a collision (jamming),
the CSMA/CD sublayer delays before attempt-
ing to re-transmit the frame. The delay is an in-
teger multiple of slotTime. The number of slot
times to delay before the nth re-transmission at-
tempt is chosen as a uniformly distributed ran-
dom integer r in the range:
Manchester Encoder/Decoder (MENDEC)
The integrated Manchester Encoder/Decoder provides
the PLS (Physical Signaling) functions required for a
fully compliant IEEE 802.3 station. The MENDEC block
contains the AUI, DAI interfaces, and supports the
10BASE-T interface; all of which transfer data to appro-
priate transceiver devices in Manchester encoded for-
mat. The MENDEC provides the encoding function for
data to be transmitted on the network using the high ac-
curacy on-board oscillator, driven by either the crystal
oscillator or an external CMOS level compatible clock
generator. The MENDEC also provides the decoding
function from data received from the network. The MEN-
DEC contains a Power On Reset (POR) circuit, which
ensures that all analog portions of the MACE device are
forced into their correct state during power up, and pre-
vents erroneous data transmission and/or reception
during this time.
0 ≤ r ≤ 2k, where k = min (n,10).”
The MACE device implements a random number gen-
erator, configured to ensure that nodes experiencing a
collision, will not have their retry intervals track identi-
cally, causing retry errors.
The MACE device provides an alternative algorithm,
which suspends the counting of the slot time/IPG during
the time that receive carrier sense is detected. This aids
in networks where large numbers of nodes are present,
andnumerousnodescanbeincollision. Iteffectivelyac-
celerates the increase in the backoff time in busy
networks, and allows nodes not involved in the collision
to access the channel whilst the colliding nodes await a
reduction in channel activity. Once channel activity is
reduced, the nodes resolving the collision time-out their
slot time counters as normal.
External Crystal Characteristics
When using a crystal to drive the oscillator, the following
crystal specification should be used to ensure less than
±0.5 ns jitter at DO±:
If a receive message suffers a collision, it will be either a
runt, in which case it will be deleted in the Receive FIFO,
Am79C940
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Parameter
Min
Nom
Max
Units
1. Parallel Resonant Frequency
20
MHz
2. Resonant Frequency Error
(CL = 20 pF)
–50
–40
+50
PPM
3. Change in Resonant Frequency
With Respect To Temperature (CL = 20 pF)*
+40
20
PPM
pF
4. Crystal Capacitance
5. Motional Crystal Capacitance (C1)
6. Series Resistance
0.022
pF
35
7
ohm
pF
7. Shunt Capacitance
* Requires trimming crystal spec; no trim is 50 ppm total
External Clock Drive Characteristics
alsousedasastablebitrateclockbythereceivesection
of the SIA and controller.
When driving the oscillator from an external clock
source, XTAL2 must be left floating (unconnected). An
external clock having the following characteristics must
be used to ensure less than ±0.5 ns jitter at DO±.
The oscillator requires an external 0.005% crystal, or an
external 0.01% CMOS-level input as a reference. The
accuracy requirements if an external crystal is used are
tighter because allowance for the on-chip oscillator
must be made to deliver a final accuracy of 0.01%.
Clock Frequency:
20 MHz ±0.01%
Rise/Fall Time (tR/tF):
< 6 ns from 0.5 V
to VDD–0.5
Transmissionisenabledbythecontroller. Aslongasthe
ITENA request remains active, the serial output of the
controller will be Manchester encoded and appear at
DO±. When the internal request is dropped by the con-
troller, the differential transmit outputs go to one of two
idle states, dependent on TSEL in the Mode Register
(CSR15, bit 9):
XTAL1 HIGH/LOW Time
(tHIGH/tLOW):
40 – 60%
duty cycle
XTAL1 Falling Edge to
Falling Edge Jitter:
< ±0.2 ns at
2.5 V input (VDD/2)
MENDEC Transmit Path
TSEL LOW: The idle state of DO± yields “zero”
differential to operate transformer-
coupled loads.
The transmit section encodes separate clock and NRZ
data input signals into a standard Manchester encoded
serial bit stream. The transmit outputs (DO±) are de-
signed to operate into terminated transmission lines.
When operating into a 78 ohm terminated transmission
line, signaling meets the required output levels and
skew for Cheapernet, Ethernet and IEEE-802.3.
TSEL HIGH: In this idle state, DO+ is positive
with respect to DO– (logical\HIGH).
Receive Path
The principal functions of the Receiver are to signal the
MACE device that there is information on the receive
pair, and separate the incoming Manchester encoded
data stream into clock and NRZ data.
Transmitter Timing and Operation
A 20 MHz fundamental mode crystal oscillator provides
the basic timing reference for the SIA portion of the
MACE device. It is divided by two, to create the internal
transmit clock reference. Both clocks are fed into the
SIA’s Manchester Encoder to generate the transitions in
the encoded data stream. The internal transmit clock is
used by the SIA to internally synchronize the Internal
Transmit Data (ITXD) from the controller and Internal
Transmit Enable (ITENA). The internal transmit clock is
The Receiver section (see Receiver Block Diagram)
consists of two parallel paths. The receive data path is a
zerothreshold, widebandwidthlinereceiver. Thecarrier
path is an offset threshold bandpass detecting line re-
ceiver. Both receivers share common bias networks to
allow operation over a wide input common mode range.
38
Am79C940
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SRD
Manchester
Decoder
Data
Receiver
DI±
SRDCLK
Noise
Reject
Filter
Carrier
Detect
Circuit
RXCRS
16235C-5
Receiver Block Diagram
PLL Tracking
Input Signal Conditioning
Transient noise pulses at the input data stream are re-
jected by the Noise Rejection Filter. Pulse width rejec-
tion is proportional to transmit data rate. DC inputs more
negative than minus 100 mV are also suppressed.
After clock acquisition, the phase-locked clock is com-
pared to the incoming transition at the bit cell center
(BCC) and the resulting phase error is applied to a cor-
rection circuit. This circuit ensures that the phase-
locked clock remains locked on the received signal.
Individual bit cell phase corrections of the Voltage Con-
trolled Oscillator (VCO) are limited to 10% of the phase
difference between BCC and phase-locked clock.
The Carrier Detection circuitry detects the presence of
an incoming data packet by discerning and rejecting
noise from expected Manchester data, and controls the
stop and start of the phase-lock loop during clock acqui-
sition. Clock acquisition requires a valid Manchester bit
pattern of 1010 to lock onto the incoming message.
Carrier Tracking and End of Message
The carrier detection circuit monitors the DI± inputs after
RXCRS is asserted for an end of message. RXCRS de-
asserts 1 to 2 bit times after the last positive transitionon
the incoming message. This initiates the end of recep-
tion cycle. The time delay from the last rising edge of the
message to RXCRS deassert allows the last bit to be
strobed by SRDCLK and transferred to the controller
section, but prevents any extra bit(s) at the end of mes-
sage. When IRENA de-asserts (see Receive Timing-
End of Reception (Last Bit = 0) and Receive Timing-End
of Reception (Last Bit = 1) waveform diagrams) an
RXCRS hold off timer inhibits RXCRS assertion for at
least 2 bit times.
When input amplitude and pulse width conditions are
met at DI±, the internal enable signal from the SIA to
controller (RXCRS) is asserted and a clock acquisition
cycle is initiated.
Clock Acquisition
When there is no activity at DI± (receiver is idle), the re-
ceive oscillator is phase locked to TCK. The first nega-
tive clock transition (bit cell center of first valid
Manchester “0”) after RXCRS is asserted interrupts the
receive oscillator. The oscillator is then restarted at the
second Manchester “0” (bit time 4) and is phase locked
to it. As a result, the SIA acquires the clock from the
incoming Manchester bit pattern in 4 bit times with a
“1010” Manchester bit pattern.
Data Decoding
The data receiver is a comparator with clocked output to
minimize noise sensitivity to the DI± inputs. Input error is
less than ± 35 mV to minimize sensitivity to input rise
and fall time. SRDCLK strobes the data receiver output
at 1/4 bit time to determine the value of the Manchester
bit, and clocks the data out on SRD on the following
SRDCLK. The data receiver also generates the signal
used for phase detector comparison to the internal SIA
voltage controlled oscillator (VCO).
SRDCLK and SRD are enabled 1/4 bit time after clock
acquisition in bit cell 5 if the ENPLSIO bit is set in the
PLS configuration control register. SRD is at a HIGH
state when the receiver is idle (no SRDCLK). SRD how-
ever, is undefined when clock is acquired and may re-
main HIGH or change to LOW state whenever SRDCLK
is enabled. At 1/4 bit time through bit cell 5, the controller
portion of the MACE device sees the first SRDCLK tran-
sition. This also strobes in the incoming fifth bit to the
SIA as Manchester “1”. SRD may make a transition after
the SRDCLK rising edge bit cell 5, but its state is still un-
defined. The Manchester “1” at bit 5 is clocked to SRD
output at 1/4 bit time in bit cell 6.
Differential Input Terminations
The differential input for the Manchester data (DI±) is
externally terminated by two 40.2 ohm ±1% resistors
and one optional common-mode bypass capacitor, as
shown in the Differential Input Termination diagram
Am79C940
39
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below. The differential input impedance, ZIDF, and the
common-mode input impedance, ZICM, are specified so
that the Ethernet specification for cable termination im-
pedance is met using standard 1% resistor terminators.
IfSIPdevicesareused, 39ohmsisalsoasuitablevalue.
The CI± differential inputs are terminated in exactly the
same way as the DI± pair.
AUI Isolation
Transformer
DI+
MACE
DI-
40.2 Ω
40.2 Ω
0.01µF
16235C-6
Differential Input Termination
Collision Detection
After the MACE device initiates a transmission it will ex-
pect to see data looped-back on the DI± pair (AUI port
selected). This will internally generate a carrier sense,
indicating that the integrity of the data path to and from
the MAU is intact, and that the MAU is operating cor-
rectly. This carrier sense signal must be asserted during
the transmission when using the AUI port (DO± trans-
mitting). If carrier sense does not become active in re-
sponse to the data transmission, or becomes inactive
before the end of transmission, the loss of carrier
(LCAR) error bit will be set in the Transmit Frame Status
(bit 7) after the packet has been transmitted.
A transceiver detects the collision condition on the net-
work and generates a differential signal at the CI± in-
puts. This collision signal passes through an input stage
which detects signal levels and pulse duration. When
the signal is detected by the MENDEC it sets the CLSN
line HIGH. The condition continues for approximately
1.5 bit times after the last LOW-to-HIGH transition on
CI±.
Jitter Tolerance Definition
The Receive Timing-Start of Reception Clock Acquisi-
tion waveform diagram shows the internal timing rela-
tionships implemented for decoding Manchester data in
the SIA module. The SIA utilizes a clock capture circuit
to align its internal data strobe with an incoming bit
stream. Theclockacquisitioncircuitryrequiresfourvalid
bits with the values 1010. Clock is phase locked to the
negative transition at the bit cell center of the second “0”
in the pattern.
Digital Attachment Interface (DAI )
The Digital Attachment Interface is a simplified electrical
attachment specification which allows MAUs which do
not require the DC isolation between the MAU and DTE
(e.g. devices compatible with the 10BASE-T Standard
and10BASE-FLDraftdocument)tobeimplemented. All
data transferred across the DAI port is Manchester En-
coded. Decoding and encoding is performed by the
MENDEC.
Since data is strobed at 1/4 bit time, Manchester transi-
tions which shift from their nominal placement through
1/4 bit time will result in improperly decoded data. With
this as the criteria for an error, a definition of “Jitter Han-
dling” is:
The DAI port will accept receive data on the basis that
the RXCRS input is active, and will take the data pre-
sented on the RXDAT input as valid Manchester data.
Transmit data is sent to the external transceiver by the
MACE device asserting TXEN and presenting compli-
mentary data on the TXDAT± pair. During idle, the
MACE device will assert the TXDAT+ line high, and the
TXDAT line low, while TXEN is maintained inactive
(high). The MACE device implements logical collision
detection and will use the simultaneous assertion of
TXEN and RXCRS to internally detect a collision condi-
tion, take appropriate internal action (such as abort the
current transmit or receive activity), and provide exter-
nal indication using the CLSN pin. Any external
The peak deviation approaching or crossing 1/4 bit cell
position from nominal input transition, for which the SIA
section will properly decode data.
Attachment Unit Interface (AUI)
The AUI is the PLS (Physical Signaling) to PMA (Physi-
cal Medium Attachment) interface which effectively con-
nects the DTE to the MAU. The differential interface
provided by the MACE device is fully compliant to Sec-
tion 7 of ISO 8802-3 (ANSI/IEEE 802.3).
40
Am79C940
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transceiver utilized for the DAI interface must not loop
back the transmit data (presented by the MACE device)
on the TXDAT± pins to the RXDAT pin. Neither should
the transceiver assert the RXCRS pin when transmitting
data to the network. Duplication of these functions by
the external transceiver (unless the MACE device is in
the external loop back test configuration) will cause
false collision indications to be detected.
10BASE-T Interface
Twisted Pair Transmit Function
Data transmission over the 10BASE-T medium requires
use of the integrated 10BASE-T MAU, and uses the dif-
ferential driver circuitry in the TXD± and TXP± pins. The
driver circuitry provides the necessary electrical driving
capability and the pre-distortion control for transmitting
signals over maximum length Twisted Pair cable, as
specified by the 10BASE-T supplement to the IEEE
802.3 Standard. The transmit function for data output
meets the propagation delays and jitter specified by the
standard. During normal transmission, and providing
that the 10BASE-T MAU is not in a Link Fail or jabber
state, the TXEN pin will be driven LOW and can be used
indirectly to drive a status LED.
Inordertoprovideanintegritytestoftheconnectivitybe-
tween the MACE device and the external transceiver
similar to the SQE Test Message provided as a part of
the AUI functionality, the MACE device can be pro-
grammed to operate the DAI port in an external loop-
back test. In this case, the external transceiver is
assumed to loopback the TXDAT± data stream to the
RXDAT pin, and assert RXCRS in response to the
TXEN request. When in the external loopback mode of
operation (programmed by LOOP [1–0] = 01), the
MACE device will not internally detect a collision condi-
tion. The external transceiver is assumed to take action
to ensure that this test will not disrupt the network. This
type of test is intended to be operated for a very limited
period (e.g. after power up), since the transceiver is as-
sumed to be located physically close to the MACE de-
vice and with minimal risk of disconnection (e.g.
connected via printed circuit board traces).
Twisted Pair Receive Function
The receiver complies with the receiver specifications of
the IEEE 802.3 10BASE-T Standard, including noise
immunity and received signal rejection criteria (Smart
Squelch). Signals meeting this criteria appearing at the
RXD± differential input pair are routed to the internal
MENDEC. The receiver function meets the propagation
delays and jitter requirements specified by the
10BASE-T Standard. The receiver squelch level drops
to half its threshold value after unsquelch to allow recep-
tion of minimum amplitude signals and to mitigate car-
rier fade in the event of worst case signal attenuation
and crosstalk noise conditions. During receive, the
RXCRS pin is driven HIGH and can be used indirectly to
drive a status LED.
Note that when the DAI port is selected, LCAR errors
will not occur, since the MACE device will internally loop
back the transmit data path to the receiver. This loop
back function must not be duplicated by a transceiver
whichisexternallyconnectedviatheDAI port, sincethis
will result in a condition where a collision is generated
during any transmit activity.
Note that the 10BASE-T Standard defines the receive
input amplitude at the external Media Dependent Inter-
face (MDI). Filter and transformer loss are not specified.
The 10BASE-T MAU receiver squelch levels are de-
fined to account for a 1dB insertion loss at 10 MHz,
which is typical for the type of receive filters/transform-
ers recommended (see the Appendix for additional
details).
The transmit function of the DAI port is protected by a
jabber mechanism which will be invoked if the TXDAT±
and TXEN circuit is active for an excessive period (20 –
150 ms). This prevents a single node from disrupting the
network due to a stuck-on or faulty transmitter. If this
maximum transmit time is exceeded, the DAI port trans-
mitter circuitry is disabled, the CLSN pin is asserted, the
Jabber bit (JAB in the Interrupt Register) is set and the
INTR pin will be asserted providing the JABM bit (Inter-
rupt Mask Register) is cleared. Once the internal
transmit data stream from the MENDEC stops (TXEN
deasserts), an unjab time of 250 ms–750 ms will elapse
before the MACE device deasserts the CLSN indication
and re-enables the transmit circuitry.
Normal 10BASE-T compatible receive thresholds are
employed when the LRT bit is inactive (PHY Configura-
tion Control register). When the LRT bit is set, the Low
Receive Threshold option is invoked, and the sensitivity
ofthe10BASE-TMAUreceiverisincreased. Thisallows
longer line lengths to be employed, exceeding the 100m
target distance of normal 10BASE-T (assuming typical
24 AWG cable). The additional cable distance attributes
directly to increased signal attenuation and reduced sig-
nalamplitudeatthe10BASE-TMAUreceiver. However,
from a system perspective, making the receiver more
sensitive means that it is also more susceptible to
When jabber is detected, the MACE device will assert
the CLSN pin, de-assert the TXEN pin (regardless of in-
ternal MENDEC activity) and set the TXDAT+ and
TXDAT pins to their inactive state.
Am79C940
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extraneous noise, primarily caused by coupling from co-
resident services (crosstalk). For this reason, it is rec-
ommended that when using the Low Receive Threshold
option that the service should be installed on 4-pair ca-
ble only. Multi-pair cables within the same outer sheath
have lower crosstalk attenuation, and may allow noise
emitted from adjacent pairs to couple into the receive
pair, and be of sufficient amplitude to falsely unsquelch
the 10BASE-T MAU receiver.
If the RWAKE bit is set in the PHY Configuration Control
register prior to the assertion of the hardware SLEEP
pin, the10BASE-Treceiverandtransmitterfunctionsre-
mainactive, theLNKSToutputisdisabled, andtheEADI
output pins are enabled. In addition the AUI port (trans-
mit and receive) remains active. Note that since the
MAC core will be in a sleep mode, no transmit activity is
possible, and the transmission of Link Test pulses is
also suspended to reduce power consumption.
Link Test Function
Polarity Detection and Reversal
The link test function is implemented as specified by
10BASE-T standard. During periods of transmit pair
inactivity, Link Test pulses will be periodically sent
over the twisted pair medium to constantly monitor
medium integrity.
The Twisted Pair receive function includes the ability to
invert the polarity of the signals appearing at the RXD±
pair if the polarity of the received signal is reversed
(such as in the case of a wiring error). This feature al-
lows data packets received from a reverse wired RXD±
input pair to be corrected in the 10BASE-T MAU prior to
transfer to the MENDEC. The polarity detection function
is activated following reset or Link Fail, and will reverse
the receive polarity based on both the polarity of any
previousLinkTestpulsesandthepolarityofsubsequent
packets with a valid End Transmit Delimiter (ETD).
When the link test function is enabled, the absence of
Link Test pulses and receive data on the RXD± pair will
cause the 10BASE-T MAU to go into a Link Fail state. In
the Link Fail state, data transmission, data reception,
data loopback and the collision detection functions are
disabled, and remain disabled until valid data or >5 con-
secutive link pulses appear on the RXD± pair. During
Link Fail, the LNKST pin is inactive (externally pulled
HIGH), and the Link Fail bit (LNKFL in the PHY Configu-
ration Control register) will be set. When the link is iden-
tified as functional, the LNKST pin is driven LOW
(capable of directly driving a Link OK LED using an inte-
grated 12 mA driver) and the LNKFL bit will be cleared.
In order to inter-operate with systems which do not im-
plement link test, this function can be disabled by setting
the the Disable Link Test bit (DLNKTST in the PHY Con-
figuration Control register). With link test disabled, the
data driver, receiver and loopback functions as well as
collision detection remain enabled irrespective of the
presence or absence of data or link pulses on the
RXD± pair.
When in the Link Fail state, the internal 10BASE-T re-
ceiver will recognize Link Test pulses of either positive
or negative polarity. Exit from the Link Fail state is made
due to the reception of five to six consecutive Link Test
pulses of identical polarity. On entry to the Link Pass
state, the polarity of the last five Link Test pulses is used
to determine the initial receive polarity configuration and
the receiver is reconfigured to subsequently recognize
onlyLinkTestpulsesofthepreviouslyrecognizedpolar-
ity. This link pulse algorithm is employed only until ETD
polarity determination is made as described later in
this section.
Positive Link Test pulses are defined as received signal
with a positive amplitude greater than 520 mV (LRT =
LOW) with a pulse width of 60 ns–200 ns. This positive
excursion may be followed by a negative excursion.
This definition is consistent with the expected received
signal at a correctly wired receiver, when a Link Test
pulse which fits the template of Figure 14-12 in the
10BASE-T Standard is generated at a transmitter and
passed through 100 m of twisted pair cable.
The MACE devices integrated 10BASE-T transceiver
will mimic the performance of an externally connected
device (such as a 10BASE-T MAU connected using an
AUI). When the 10BASE-T transceiver is in link fail, the
receive data path of the transceiver must be disabled.
The MACE device will report a Loss of Carrier error
(LCAR bit in the Transmit Frame Status register) due to
the absence of the normal loopback path, for every
packet transmitted during the link fail condition. In addi-
tion, a Collision Error (CERR bit in the Transmit Frame
Status register) will also be reported (see the section on
Signal Quality Error Test Function for additional details).
Negative Link Test pulses are defined as received sig-
nals with a negative amplitude greater than 520 mV
(LRT = LOW) with a pulse width of 60 ns–200 ns. This
negative excursion may be followed by a positive excur-
sion. This definition is consistent with the expected re-
ceived signal at a reverse wired receiver, when a Link
Test pulse which fits the template of Figure 14-12 in the
10BASE-T Standard is generated at a transmitter and
passed through 100 m of twisted pair cable.
If the AWAKE bit is set in the PHY Configuration Control
register prior to the assertion of the hardware SLEEP
pin, the 10BASE-T receiver remains operable, and is
able to detect and indicate (using the LNKST output) the
presence of legitimate Link Test pulses or receive activ-
ity. ThetransmissionofLinkTestpulsesissuspendedto
reduce power consumption.
The polarity detection/correction algorithm will remain
armed until two consecutive packets with valid ETD of
identical polarity are detected. When armed, the
42
Am79C940
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receiver is capable of changing the initial or previous po-
larity configuration based on the most recent ETD polar-
ity.
In jabber detect mode, the MACE device will activate the
CLSN pin, disable TXEN (regardless of Manchester
data output from the MENDEC), and allow the RXCRS
pin to indicate the current state of the RXD± pair. If there
is no receive activity on RXD±, only CLSN will be active
during jabber detect. If there is RXD± activity, both
CLSN and RXCRS will be active.
On receipt of the first packet with valid ETD following re-
set or Link Fail, the MACE device will utilize the inferred
polarity information to configure its RXD± input, regard-
less of its previous state. On receipt of a second packet
with a valid ETD with correct polarity, the detection/cor-
rection algorithm will lock-in the received polarity. If the
second (or subsequent) packet is not detected as con-
firming the previous polarity decision, the most recently
detected ETD polarity will be used as the default. Note
that packets with invalid ETD have no effect on updating
the previous polarity decision. Once two consecutive
packets with valid ETD have been received, the MACE
device will disable the detection/correction algorithm
until either a Link Fail condition occurs or a hardware or
software reset occurs.
If the SLEEP pin is asserted (regardless of the program-
ming of the AWAKE or RWAKE bits in the PHY Configu-
ration Control register), the TXEN, RXCRS and CLSN
outputs will be placed in a high impedance state.
Collision Detect Function
Simultaneous activity (presence of valid data signals)
from both the internal MENDEC transmit function (indi-
cated externally by TXEN active) and the twisted pair
RXD± pins constitutes a collision, thereby causing an
externalindicationontheCLSNpin, andaninternalindi-
cation which is returned to the MAC core. The TXEN,
RXCRS and CLSN pins are driven high during collision.
Duringpolarityreversal, theRXPOLpinshouldbeexter-
nally pulled HIGH and the Reversed Polarity bit
(REVPOL in the PHY Configuration Control register) will
be set. During normal polarity conditions, the RXPOL
pin is driven LOW (capable of directly driving a Polarity
OK LED using an integrated 12 mA driver) and the REV-
POL bit will be cleared.
Signal Quality Error (SQE) Test
(Heartbeat) Function
The SQE Test message (a 10 MHz burst normally re-
turned on the AUI CI± pair at the end of every transmis-
sion) is intended to be a self-test indication to the DTE
that the MAU collision circuitry is functional and the AUI
cable/connection is intact. This has minimal relevance
when the 10BASE-T MAU is embedded in the LAN con-
troller. A Collision Error (CERR bit in the Interrupt Regis-
ter) will be reported only when the 10BASE-T port is in
the link fail state, since the collision circuit of the MAU
will be disabled, causing the absence of the SQE Test
message. In GPSI mode the external encoder/decoder
is responsible for asserting the CLSN pin after each
transmission. In DAI mode SEQ Test has no relevance.
If desired, the polarity correction function can be dis-
abled by setting the Disable Auto Polarity Correction bit
(DAPC bit in the PHY Configuration Control register).
However, the polarity detection portion of the algorithm
continues to operate independently, and the RXPOLpin
and the REVPOL bits will reflect the polarity state of the
receiver.
Twisted Pair Interface Status
Three outputs (TXEN, RXCRS and CLSN) indicate
whether the MACE device is transmitting (MENDEC
to Twisted Pair), receiving (Twisted Pair to MENDEC),
or in a collision state with both functions active
simultaneously.
Jabber Function
The Jabber function inhibits the twisted pair transmit
function of the MACE device if the TXD±/TXP± circuits
are active for an excessive period (20–150 ms). This
prevents any one node from disrupting the network due
to a stuck-on or faulty transmitter. If this maximum trans-
mit time is exceeded, the data path through the
10BASE-T transmitter circuitry is disabled (although
Link Test pulses will continue to be sent), the CLSN pin
is asserted, the Jabber bit (JAB in the Interrupt Register)
is set and the INTR pin will be asserted providing the
JABM bit (Interrupt Mask Register) is cl eared. Once the
internal transmit data stream from the MENDEC stops
(TXEN deasserts), an unjab time of 250–750 ms will
elapse before the MACE device deasserts the CLSN in-
dication and re-enables the transmit circuitry.
The MACE device will power up in the Link Fail state.
The normal algorithm will apply to allow it to enter the
Link Pass state. On power up, the TXEN, RXCRS and
CLSN) pins will be in a high impedance state until they
are enabled by setting the Enable PLS I/O bit (ENPLSIO
in the PLS Configuration Control register) and the
10BASE-T port enters the Link Pass state.
In the Link Pass state, transmit or receive activity which
passes the pulse width/amplitude requirements of the
DO± or RXD± inputs, will be indicated by the TXEN or
RXCRS pin respectively going active. TXEN, RXCRS
and CLSN are all asserted during a collision.
When jabber is detected, the MACE device will assert
the CLSN pin, de-assert the TXEN pin (regardless of
In the Link Fail state, TXEN, RXCRS and CLSN are
inactive.
Am79C940
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internal MENDEC activity), and allow the RXCRS pin to
indicate the current state of the RXD± pair. If there is no
receive activity on RXD±, only CLSN will be active dur-
ing jabber detect. If there is RXD± activity, both CLSN
and RXCRS will be active.
alternate methods are programmed using the Match/
Reject (M/R) bit in the Receive Frame Control register.
If the M/R bit is set, the pin is configured as EAM (Exter-
nal Address Match). The MACE device can be config-
ured with Physical, Logical or Broadcast Address
comparison operational. If an internal address match is
detected, the packet will be accepted regardless of the
condition of EAM. Additional addresses can be located
in the external address detection logic. If a match is de-
tected, EAMmust go active within 600 ns of the last bit in
the destination address field (end of byte 6) being pre-
sented on the SRD output, to guarantee frame recep-
tion. In addition, EAMmust go inactive after a match has
been detected on a previous packet, before the next
match can take place on any subsequent packet. EAM
must be asserted for a minimum pulse width of 200 ns.
External Address Detection Interface
(EADI)
This interface is provided to allow external perfect ad-
dress filtering. This feature is typically utilized for termi-
nal server, bridge and/or router type products. The use
of external logic is required, to capture the serial bit
stream from the MACE device, and compare this with a
table of stored addresses or identifiers. See the EADI
port diagram in the Systems Applications section, Net-
work Interfaces sub-section, for details.
The EADI interface operates directly from the NRZ de-
coded data and clock recovered by the Manchester
decoder. This allows the external address detection to
be performed in parallel with frame reception and ad-
dress comparison in the MAC Station Address Detec-
tion (SAD) block.
If the M/R bit is clear (default state after either the
RESET pin or SWRST bit have been activated), the pin
is configured as EAR (External Address Reject). The
MACE device can be configured with Physical, Logical
or Broadcast Address comparison operational. If an in-
ternal address match is detected, the packet will be ac-
cepted regardless of the condition of EAR. Incoming
packetswhichdonotpasstheinternaladdresscompari-
son will continue to be received by the MACE device.
EAR must be externally presented to the MACE chip
prior to the first assertion of RDTREQ, to guarantee re-
jection of unwanted packets. This allows approximately
58 byte times after the last destination address bit is
available to generate the EAR signal, assuming the
MACE device is not configured to accept runt packets.
EAR will be ignored by the MACE device from 64 byte
times after the SFD, and the packet will be accepted if
EAR has not been asserted before this time. If the
MACE device is configured to accept runt packets, the
EAR signal must be generated prior to the receive mes-
sage completion, which could be as short as 12 byte
times (assuming six bytes for source address, twobytes
for length, no data, four bytes for FCS) after the last bit
ofthedestinationaddressisavailable. EARmusthavea
pulse width of at least 200 ns.
SRDCLK is provided to allow clocking of the receive bit
stream from the MACE device, into the external address
detection logic. Once a received packet commences
and data and clock are available from the decoder, the
EADI interface logic will monitor the alternating (1,0)
preamble pattern until the two ones of the Start Frame
Delimiter (1,0,1,0,1,0,1,1) are detected, at which point
the SF/BD output will be driven high.
After SF/BD is asserted the serial data from SRD should
be de-serialized and sent to a Content Addressable
Memory (CAM) or other address detection device.
To allow simple serial to parallel conversion, SF/BD is
provided as a strobe and/or marker to indicate the de-
lineation of bytes, subsequent to the SFD. This feature
provides a mechanism to allow not only capture and/or
decoding of the physical or logical (group) address, but
also facilitates the capture of header information to de-
termine protocol and or inter-networking information.
The EAM/R pin is driven by the external address com-
parison logic, to either reject or accept the packet. Two
alternative modes are permitted, allowing the external
logic to either accept the packet based on address
match, or reject the packet if there is no match. The two
Note that setting the PROM bit (MAC Configuration
Control) will cause all receive packets to be received, re-
gardless of the programming of M/R or the state of the
EAM/R input. The following table summarizes the op-
eration of the EADI features.
44
Am79C940
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Internal/External Address Recognition Capabilities
EAM/R Required Timing
No timing requirements
PROM
M/R
X
Received Messages
All Received Frames
All Received Frames
1
0
0
0
0
X
H
↓
0
No timing requirements
0
Low for 200 ns within 512-bits after SFD
No timing requirements
Physical/Logical/Broadcast Matches
Physical/Logical/Broadcast Matches
All Received Frames
1
H
↓
1
Low for 200 ns within 8-bits after DA field
The boundary scan test circuit requires four pins (TCK,
TMS, TDI and TDO ), defined as the Test Access Port
(TAP). It includes a finite state machine (FSM), an in-
struction register, a data register array and a power on
reset circuit. Internal pull-up resistors are provided for
the TCK, TDI and TMS pins.
General Purpose Serial Interface (GPSI)
The GPSI port provides the signals necessary to pre-
sent an interface consistent with the non encoded data
functions observed to/from a LAN controller such as the
Am7990 Local Area Network Controller for Ethernet
(LANCE). The actual GPSI pins are functionally identi-
cal to some of the pins from the DAI and the EADI ports,
the GPSI replicates this type of interface.
The TAP engine is a 16 state FSM, driven by the Test
Clock (TCK) and the Test Mode Select (TMS) pins. An
independent power on reset circuit is provided to ensure
the FSM is in the TEST_LOGIC_RESET state at
power up.
The GPSI allows use of an external Manchester en-
coder/decoder, such as the Am7992B Serial Interface
Adapter (SIA). In addition, it allows the MACE device to
be used as a MAC sublayer engine in a repeater based
on the Am79C980 Integrated Multiport Repeater (IMR).
Simple connection to the IMR Expansion Bus allows the
MAC to view all packet data passing through a number
of interconnected IMRs, allowing statistics and network
management information to be collected.
In addition to the minimum IEEE 1149.1 instruction re-
quirements (EXTEST, SAMPLE and BYPASS), three
additional instructions (IDCODE, TRI_ST and SET_I/O)
are provided to further ease board level testing. All
unused instruction codes are reserved.
IEEE 1149.1 Supported Instruction Summary
The GPSI functional pins are duplicated as follows:
Inst
Selected
Reg
Inst
Name
Description
Data Reg Mode
Code
Pin Configuration for GPSI Function
EXTEST External Test
BSR
Test
0000
0001
0010
0011
0100
1111
LANCE
Pin
MACE
Pin
ID Code ID Code Inspection
Sample Sample Boundary
TRI_ST Force Tristate
ID Reg
BSR
Normal
Normal
Function
Type
Receive Data
Receive Clock
Receive Carrier Sense
Collision
I
I
RX
RXDAT
SRDCLK
RXCRS
CLSN
Bypass Normal
RCLK
RENA
CLSN
TX
SET_I/0 Control Boundary To I/0 Bypass Test
Bypass Bypass Scan Bypass Normal
I
I
Transmit Data
Transmit Clock
Transmit Enable
O
I
TXDAT+
STDCLK
TXEN
After hardware or software reset, the IDCODE instruc-
tion is always invoked. The decoding logic provides sig-
nals to control the data flow in the DATA registers
according to the current instruction.
TCK
O
TENA
IEEE 1149.1 Test Access Port Interface
Each Boundary Scan Register (BSR) cell also has two
stages. A flip-flop and a latch are used in the SERIAL
SHIFT STAGE and the PARALLEL OUTPUT STAGE
respectively.
AnIEEE1149.1compatibleboundaryscanTestAccess
Port is provided for board level continuity test and diag-
nostics. All digital input, output and input/output and in-
put/output pins are tested. Analog pins, including the
AUI differential driver (DO±) and receivers DI±, CI±),
and the crystal input (XTAL1/XTAL2) pins, are not
tested.
There are four possible operational modes in the BSR
cell:
(1) CAPTURE
(2) SHIFT
The following is a brief summary of the IEEE 1149.1
compatible test functions implemented in the MACE de-
vice. For additional details, consult the IEEE Standard
Test Access Port and Boundary-Scan Architecture
document (IEEE Std 1149.1–1990).
(3) UPDATE
(4) SYSTEM FUNCTION
Am79C940
45
AMD
Other Data Registers
If FDS is low, a FIFO Direct read will take place from the
RCVFIFO. The state of the ADD4–0 bus is irrelevant for
the FIFO Direct mode.
■ BYPASS REG (1 bit)
■ Device Identification Register (32 bits)
Bits 31–28: Version (4 bits)
With either the CS or FDS input active, the state of the
ADD0-4 (for Register Address reads), R/W (high to indi-
cate a read cycle), BE0 and BE1 will also be latched on
the falling (EDSEL = HIGH) edge of SCLK at S0.
Bits 27–12: Part number (16 bits) is 9400H
Bits 11–1: Manufacturer ID (11 bits).
The manufacturer ID code for AMD is
00000000001 in accordance with
JEDEC Publication 106-A.
From the falling edge of SCLK in S1 (EDSEL = HIGH),
the MACE device will drive data on DBUS15–0 and acti-
vatetheDTVoutput(providingthereadcyclecompleted
successfully). If the cycle read the last byte/word of data
for a specific frame from the RCVFIFO, the MACE de-
vice will also assert the EOF signal. DBUS15–0, DTV
and EOF will be guaranteed valid and can be sampled
on the falling (EDSEL = HIGH) edge of SCLK at S2.
Bit 0:
Always a logic 1
SLAVE ACCESS OPERATION
Internal register accesses are based on a 2 or 3 SCLK
cycle duration, dependent on the state of the TC input
pin. TC must be externally pulled low to force the MACE
device to perform a 3-cycle access. TC is internally
pulled high if left unconnected, to configure the 2-cycle
access by default.
If the Register Address mode is being used to access
the RCVFIFO, once EOF is asserted during the last
byte/word read for the frame, the Receive Frame Status
can be read in one of two ways. The Register Address
mode can be continued, by placing the appropriate ad-
dress (00110b) on the address bus and executing four
read cycles (CSactive) on the Receive Frame Status lo-
cation. In this case, additional Register Address read re-
quests from the RCVFIFO will be ignored, and no DTV
returned, until all four bytes of the Receive Frame Status
register have been read. Alternatively, a FIFO Direct
read can be performed, which will effectively route the
Receive Frame Status through the RCVFIFO location.
This mechanism is explained in more detail below.
All register accesses are byte wide with the exception of
the data path to and from the internal FIFOs.
Data exchanges to/from register locations will take
place over the appropriate half of the data bus to suit the
host memory organization (as programmed by the
BSWP bit in the BIU Configuration Control register).
The BE0, BE1 and EOF signals are provided to allow
control of the data flow to and from the FIFOs. Byte read
operations from the Receive FIFO cause data to be du-
plicated on both the upper and lower bytes of the data
bus. Byte write operations to the Transmit FIFO must
use the BE0 and BE1 inputs to define the active data
byte to the MACE device.
If the FIFO Direct mode is used, the Receive Frame
Status can be read directly from the RCVFIFO by con-
tinuing to execute read cycles (by asserting FDS low
and R/W high) after EOF is asserted indicating the last
byte/word read for the frame. Each of the four bytes of
Receive Frame Status will appear on both halves of the
data bus, as if the actual Receive Frame Status register
were being accessed. Alternatively, the status can be
read as normal using the Register Address mode by
placing the appropriate address (00110b) on the ad-
dress bus and executing four read cycles (CS active).
Read Access
Details of the read access timing are located in the AC
Waveforms section, Host System Interface, figures:
Two-Cycle Receive FIFO/Register Read Timing and
Three-Cycle Receive FIFO/Register Read Timing.
TC can be dynamically changed on a cycle by cycle ba-
sis to program the slave cycle execution for two (TC =
HIGH) or three (TC = LOW) SCLK cycles. TC must be
stable by the falling edge of SCLK (EDSEL = High) in S0
at the start of a cycle, and should only be changed in S0
in a multiple cycle burst.
Either the FIFO Direct or Register Address modes can
be interleaved at any time to read the Receive Frame
Status, although this is considered unlikely due to the
additional overhead it requires. In either case, no addi-
tional data will be read from the RCVFIFO until the Re-
ceive Frame Status has been read, as four bytes
appended to the end of the packet when using the FIFO
Direct mode, or as four bytes from the Receive Frame
Status location when using the Register Address mode.
A read cycle is initiated when either CS or FDS is sam-
pled low on the falling edge of SCLK at S0. FDS and CS
must be asserted exclusively. If they are active simulta-
neously when sampled, the MACE device will not exe-
cute any read or write cycle.
If CSis low, a Register Address read will take place. The
state of the ADD4–0 will be used to commence decod-
ing of the appropriate internal register/FIFO.
EOF will only be driven by the MACE device when read-
ing received packet data from the RCVFIFO. At all other
times, including reading the Receive Frame Status
46
Am79C940
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using the FIFO Direct mode, the MACE device will place
EOF in a high impedance state.
Write the PHY Configuration Control (PHYCC) reg-
ister to configure any non-default mode if the 10BASE-T
interface is used.
RDTREQ should be sampled on the falling edge of
SCLK. The assertion of RDTREQ is programmed by
RCVFW, andthede-assertionismodifieddependenton
the state of the RCVBRST bit (both in the FIFO Configu-
ration Control register). See the section Receive FIFO
Read for additional details.
Program the Logical Address Filter (LADRF) regis-
ter or the Physical Address Register (PADR). The Inter-
nal Address Configuration (IAC) register must be
accessed first. Set the Address Change (ADDRCHG)
bit to request access to the internal address RAM. Poll
the bit until it is cleared by the MACE device indicating
that access to the internal address RAM is permitted. In
the case of an address RAM access after hardware or
software reset (ENRCV has not been set), the MACE
device will return ADDRCHG = 0 right away. Set the
LOGADDR bit in the IAC register to select writing to the
Logical Address Filter register. Set the PHYADDR bit in
the IAC register to select writing to the Physical Address
Register. Either bit can be set together with writing the
ADDRCHG bit. Initializing the Logical Address Filter
register requires 8 write cycles. Initializing the Physical
Address Register requires 6 write cycles.
Write Access
Details of the write access timing are located in the AC
Waveforms section, Host System Interface, figures:
Two-Cycle Transmit FIFO/Register Write Timing and
Three-Cycle Transmit FIFO/Register Write Timing.
Write cycles are executed in a similar manner as the
read cycle previously described, but with the R/W input
low, and the host responsible to provide the data with
sufficient set up to the falling edge of SCLK after S2.
After a FIFO write, TDTREQ should be sampled on or
after the falling (EDSEL = HIGH) edge of SCLK after S3
of the FIFO write. The state of TDTREQ at this time will
reflect the state of the XMTFIFO.
Write the User Test Register (UTR) to set the MACE
device into any of the user diagnostic modes such as
loopback.
After going active (low), TDTREQ will remain low for two
or more XMTFIFO writes.
WritetheMACConfigurationControl(MACCC)reg-
ister as the last step in the initialization sequence to en-
able the receiver and transmitter. Note that the system
must guarantee a delay of 1 ms after power-up before
enabling the receiver and transmitter to allow the MACE
phase lock loop to stabilize.
The minimum high (inactive) time of TDTREQ is one
SCLK cycle. When EOF is written to the Transmit FIFO,
TDTREQ will go inactive after one SCLK cycle, for a
minimum of one SCLK cycle.
The Transmit Frame Control (XMTFC) and the
Receive Frame Control (RCVFC) registers can be pro-
grammed on a per packet basis.
Initialization
After power-up, RESET should be asserted for a mini-
mum of 15 SCLK cycles to set the MACE device into a
defined state. This will set all MACE registers to their de-
fault values. The receive and transmit functions will be
turned off. A typical sequence to initialize the MACE de-
vice could look like this:
Reinitialization
The SWRST bit in the BIU Configuration Control
(BIUCC) register can be set to reset the MACE device
into a defined state for reinitialization. The same se-
quence described in the initialization section can be
used. The 1 ms delay for the MACE phase lock loop sta-
bilization need not to be observed as it only applies to a
power–up situation.
Write the BIU Configuration Control (BIUCC) regis-
ter to change the Byte Swap mode to big endian or to
change the Transmit Start Point.
Write the FIFO Configuration Control (FIFOCC)
register to change the FIFO watermarks or to enable the
FIFO Burst Mode.
TRANSMIT OPERATION
ThetransmitoperationandfeaturesoftheMACEdevice
are controlled by programmable options. These options
are programmed through the BIU, FIFO and MAC Con-
figuration Control registers.
Write the Interrupt Mask Register (IMR) to disable
unwanted interrupt sources.
Write the PLS Configuration Control (PLSCC) reg-
ister to enable the active network port. If the GPSI inter-
face is used, the register must be written twice. The first
write access should only set PORTSEL[1–0] = 11. The
second access must write again PORTSEL[1–0] = 11
and additionally set ENPLSIO = 1. This sequence is re-
quired to avoid contention on the clock, data and/or car-
rier indication signals.
Parameters controlled by the MAC Configuration Con-
trol register are generally programmed only once,
during initialization, and are therefore static during the
normal operation of the MACE device (see the Media
Access Control section for a detailed description). The
features controlled by the FIFO Configuration Control
Am79C940
47
AMD
register and the Transmit Frame Control register can be
re-programmed if the MACE device is not transmitting.
and ENXMT set to restart the transmit process with the
new parameters.
APAD XMT is sampled if there are less than 60 bytes in
the transmit packet when the last bit of the last byte is
transmitted. If APAD XMT is set, a pad field of pattern
00h is added until the minimum frame size of 64 bytes
(excluding preamble and SFD) is achieved. If APAD
XMT is clear, no pad field insertion will take place and
runt packet transmission is possible. When APAD XMT
isenabled, theDXMTFCSfeatureisover-riddenandthe
four byte FCS will be added to the transmitted packet
unconditionally.
Transmit FIFO Write
The Transmit FIFO is accessed by performing a host
generatedwritesequenceontheMACEdevice. Seethe
Slave Access Operation-Write Access section and the
AC Waveforms section, Host System Interface, figures:
Two-Cycle Transmit FIFO/Register Write Timing and
Three-Cycle Transmit FIFO/Register Write Timing for
details of the write access timing.
There are two fundamentally different access methods
to write data into the FIFO. Using the Register Address
mode, the FIFO can be addressed using the ADD0-4
lines, (address 00001b), initiating the cycle with the CS
and R/W (low) signals. The FIFO Direct mode allows
write access to the Transmit FIFO without use of the ad-
dress lines, and using only the FDS and R/W lines. If the
MACE device detects both signals active, it will not exe-
cute a write cycle. The write cycle timing for the Register
Address or Direct FIFO modes are identical. FDS and
CS should be mutually exclusive.
The disable FCS generation/transmission feature can
be programmed dynamically on a packet by packet ba-
sis. The current state of the DXMTFCS bit is internally
latched on the last write to the Transmit FIFO, when the
EOF indication is asserted by the host/controller.
The programming of static transmit attributes are dis-
tributed between the BIU, FIFO and MAC Configuration
Control registers.
The point at which transmission begins in relation to the
number of bytes of a frame in the FIFO is controlled by
the XMTSP bits in the BIU Configuration Control regis-
ter. Depending on the bus latency of the system,
XMTSP can be set to ensure that the Transmit FIFO
does not underflow before more data is written to the
FIFO. When the entire frame is in the FIFO, or the FIFO
becomes full before the threshold is reached, transmis-
sion of preamble will commence regardless of the value
in XMTSP. The default value of XMTSP is 64 bytes after
reset.
The data stream to the Transmit FIFO is written using
multiple byte and/or word writes. CS or FDS does not
have to be returned inactive to commence execution of
the next write cycle. If CS/FDSis detected low at the fall-
ing edge of S0, a write cycle will commence. Note that
EOF must be asserted by the host/controller during the
last byte/word transfer.
Transmit Function Programming
The Transmit Frame Control register allows program-
ming of dynamic transmit attributes. Automatic transmit
features such as retry on collision, FCS generation/
transmission and pad field insertion can all be pro-
grammed, to provide flexibility in the (re-)transmission
of messages.
The point at which TDTREQ is asserted in relation to the
number of empty bytes present in the Transmit FIFO is
controlled by the XMTFW bits in the FIFO Configuration
Control register. TDTREQ will be asserted when one of
the following conditions is true:
Thedisableretryoncollision(DRTRYbit)andautomatic
pad field insertion (APAD XMT bit) features should not
be changed while data remains in the Transmit FIFO.
Writing to either the DRTRY or APAD XMT bits in this
case may have unpredictable results. These bits are not
internally latched or protected. When writing to the
Transmit Frame Control register the DRTRY and APAD
XMT bits should be programmed consistently. Once the
TransmitFIFOisempty, DRTRYandAPADXMTcanbe
reprogrammed.
■ The number of bytes free in the Transmit FIFO
relative to the current Saved Read Pointer value is
greater than or equal to the threshold set by the
XMTFW (16, 32 or 64 bytes). The Saved Read
Pointer is the first byte of the current transmit
frame, either in progress or awaiting channel
availability.
■ The number of bytes free in the Transmit FIFO
relative to the current Read Pointer value is
greater than or equal to the threshold set by the
XMTFW (16, 32 or 64 bytes). The Read Pointer
becomes available only after a minimum of 64 byte
frame length has been transmitted on the network
(eight bytes of preamble plus 56 bytes of data),
and points to the current byte of the frame being
transmitted.
This can be achieved with no risk of transmit data loss or
corruption by clearing ENXMT after the packet data for
the current frame has been completely loaded. The
transmission will complete normally and the activation
of the INTR pin can be used to determine if the transmit
frame has completed (XMTINT will be set in the Inter-
rupt Register). Once the Transmit Frame Status has
been read, APAD XMT and/or DRTRY can be changed
48
Am79C940
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Depending on the bus latency of the system, XMTFW
can be set to ensure that the Transmit FIFO does not
underflow before more data is written into the FIFO.
When the entire frame is in the FIFO, TDTREQ will re-
main asserted if sufficient bytes remain empty. The
default value of XMTFW is 64 bytes after hardware or
software reset. Note that if the XMTFW is set below the
64 byte limit, the transmit latency for the host to service
the MACE device is effectively increased, since
TDTREQ will occur earlier in the transmit sequence and
more bytes will be present in the Transmit FIFO when
the TDTREQ is de-asserted.
derivation appears in the “Automatic Pad Generation”
section.
Automatic Pad Generation
Transmit frames can be automatically padded to extend
them to 64 data bytes (excluding preamble) permitting
the minimum frame size of 64 bytes (512 bits) for
802.3/Ethernet to be guaranteed, with no software inter-
vention from the host system.
APAD XMT = 1 enables the automatic padding feature.
The pad is placed between the LLC Data field and FCS
field in the 802.3 frame. The FCS is always added if
APAD XMT = 1, regardless of the state of DXMTFCS.
The transmit frame will be padded by bytes with the
valueof00h. ThedefaultvalueofAPADXMTwillenable
auto pad generation after hardware or software reset.
The transmit operation of the MACE device can be
halted at any time by clearing the ENXMT bit (bit 1) inthe
MAC Configuration Control register. Note that any com-
plete transmit frame that is in the Transmit FIFO and is
currently in progress will complete, prior to the transmit
function halting. Transmit frames in the FIFO which
have not commenced will not be started. Transmit
frames which have commenced but which have not
been fully transferred into the Transmit FIFO will be
aborted, in one of two ways. If less than 544 bits
(68 bytes) have been transmitted onto the network, the
transmission will be terminated immediately, generating
a runt packet which can be deleted at the receiving sta-
tion. If greater than 544 bits have been transmitted, the
messages will have the current CRC inverted and ap-
pended at the next byte boundary, to guarantee an error
is detected at the receiving station. This feature ensures
that packets will not be generated with potential unde-
tected data corruption. An explanation of the 544 bit
It is the responsibility of upper layer software to correctly
define the actual length field contained in the message
to correspond to the total number of LLC Data bytes en-
capsulated in the packet (length field as defined in the
IEEE 802.3 standard). The length value contained in the
message is not used by the MACE device to compute
the actual number of pad bytes to be inserted. The
MACE chip will append pad bytes dependent on the ac-
tual number of bits transmitted onto the network. Once
the last data byte of the frame has completed, prior to
appending the FCS, the MACE device will check to en-
sure that 544 bits have been transmitted. If not, pad
bytes are added to extend the frame size to this value,
and the FCS is then added.
Preamble
1010....1010
SFD
10101011
Dest
Addr
Srce
Addr
Length
LLC
Data
Pad
FCS
56
8
6
6
2
4
Bits
Bits
Bytes
Bytes
Bytes
Bytes
46—1500
Bytes
16235C-7
IEEE 802.3 Format Data Frame
The 544 bit count is derived from the following:
Minimum frame size (excluding preamble,
At the point that FCS is to be appended, the transmitted
frame should contain:
including FCS)
Preamble/SFD size
FCS size
64 bytes
8 bytes
4 bytes
512 bits
64 bits
32bits
Preamble
64
+
+
(Min Frame Size - FCS) bits
(512 32) bits
-
A minimum length transmit frame from the MACE
device will therefore be 576 bits, after the FCS is
appended.
To be classed as a minimum size frame at the receiver,
the transmitted frame must contain:
The Ethernet specification makes no use of the LLC pad
field, and assumes that minimum length messages will
be at least 64 bytes in length.
Preamble
+
(Min Frame Size + FCS) bits
Am79C940
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AMD
Preamble
1010....1010
SYNCH
11
Dest
Addr
Srce
Addr
Type
Data
FCS
62
Bits
2
Bits
6
6
2
46—1500
Bytes
4
Bytes
Bytes
Bytes
Bytes
16235C-8
Ethernet Format Data Frame
Normal events which may occur and which are handled
autonomously by the MACE device are:
Transmit FCS Generation
Automatic generation and transmission of FCS for a
transmit frame depends on the value of DXMTFCS (Dis-
ableTransmitFCS)whentheEOFisassertedindicating
the last byte/word of data for the transmit frame is being
written to the FIFO. The action of writing the last data
byte/word of the transmit frame, latches the current con-
tents of the Transmit Frame Control register, and there-
fore determines the programming of DXMTFCS for the
transmit frame. When DXMTFCS = 0 the transmitter will
generate and append the FCS to the transmitted frame.
If the automatic padding feature is invoked (APAD XMT
in Transmit Frame Control), the FCS will be appended
regardless of the state of DXMTFCS. Note that the cal-
culated FCS is transmitted most significant bit first. The
default value of DXMTFCS is 0 after hardware or soft-
ware reset.
(a) Collisions within the slot time with automatic retry
(b) Deletion of packets due to excessive transmission
attempts.
(a) The MACE device will ensure that collisions which
occur within 512 bit times from the start of transmission
(including preamble) will be automatically retried withno
host intervention. The Transmit FIFO ensures this by
guaranteeing that data contained within the Transmit
FIFO will not be overwritten until at least 64 bytes (512
bits)ofdatahavebeensuccessfullytransmittedontothe
network. This criteria will be met, regardless of whether
the transmit frame was the first (or only) frame in the
Transmit FIFO, or if the transmit frame was queued
pending completion of the preceding frame.
Transmit Status Information
(b) If 16 total attempts (initial attempt plus 15 retries)
have been made to transmit the frame, the MACE de-
vice will abandon the transmit process for the particular
frame, de-assert the TDTREQ pin, report a Retry Error
(RTRY) in the Transmit Frame Status, and set the
XMTINT bit in the Interrupt Register, causing activation
of the external INTR pin providing the interrupt is
unmasked.
Although multiple transmit frames can be queued in the
Transmit FIFO, the MACE device will not permit loss of
Transmit Frame Status information. The Transmit
Frame Status and Transmit Retry Count can only be
buffered internally for a maximum of two frames. The
MACE device will therefore not commence a third trans-
mit frame, until the status from the first frame is read.
Once the Transmit Retry Count and Transmit Frame
Status for the first transmit packet is read, the MACE
device will autonomously begin the next transmit frame,
provided that a transmit frame is pending, the XMTSP
threshold has been exceeded (or the XMTFIFO is full),
the network medium is free, and the IPG time has
elapsed.
Once the XMTINT condition has been externally recog-
nized, the Transmit Frame Counter (XMTFC) can be
read to determine whether the tail end of the frame that
suffers the RTRY error is still in the host memory (i.e.,
when XMTFC = 0). This XMTFC read should be re-
quested before the Transmit Frame Status read since
reading the XMTFS would cause the XMTFC to decre-
ment. If the tail end of the frame is indeed still in the host
memory, the host is responsible for ensuring that the tail
end of the frame does not get written into the FIFO and
does not get transmitted as a whole frame. It is recom-
mended that the host clear the tail end of the frame from
the host memory before requesting the XMTFS read so
that after the XMTFS read, when MACE device re-as-
serts TDTREQ, the tail end of the frame does not get
written into the FIFO. The Transmit Frame Status read
will indicate that the RTRY error occurred. The read op-
eration on the Transmit Frame Status will update the
FIFO read and write pointers. If no End-of-Frame write
(EOF pin assertion) had occurred during the FIFO write
sequence, the entire transmit path will be reset (which
will update the Transmit FIFO watermark with the
Indication of valid Transmit Frame Status can be ob-
tained by servicing the hardware interrupt and testing
the XMTINT bit in the Interrupt Register, or by polling the
XMTSV bit in the Poll register if a continuous polling
mechanism is required. If the Transmit Retry Count data
is required (for loading, diagnostic, or management in-
formation), XMTRC must be read prior to XMTFS.
Reading the XMTFS register when the XMTSV bit is set
will clear both the XMTRC and XMTFS values.
Transmit Exception Conditions
Exception conditions for frame transmission fall into two
distinct categories; those which are the result of normal
network operation and those which occur due to abnor-
mal network and/or host related events.
50
Am79C940
AMD
current XMTFW value in the FIFO Configuration Control
register). If a whole frame does reside in the FIFO, the
read pointer will be moved to the start of the next frame
or free location in the FIFO, and the write pointer will be
unaffected. TDTREQ will not be re-asserted until the
Transmit Frame Status has been read.
willoperatenormallyaccordingtothespecificportwhich
has been selected.
(b) A late collision will be reported if a collision condition
exists or commences 64 byte times (512 bit times) after
the transmit process was initiated (first bit of preamble
commenced). The MACE device will abandon the trans-
mit process for the particular frame, complete transmis-
sion of the jam sequence (32-bit all zeroes pattern),
de-assert the TDTREQ pin, report the Late Collision
(LCOL) and Transmit Status Valid (XMTSV) in the
Transmit Frame Status, and set the XMTINT bit in the
Interrupt Register, causing activation of the external
INTR pin providing the interrupt is unmasked.
After a RTRY error, all further packet transmission will
be suspended until the Transmit Frame Status is read,
regardless of whether additional packet data exists in
the FIFO to be transmitted. Receive FIFO read opera-
tions are not impaired.
Packets experiencing 16 unsuccessful attempt to trans-
mit will not be re-tried. Recovery from this condition
must be performed by upper layer software.
Once the XMTINT condition has been externally recog-
nized, the Transmit Frame Counter (XMTFC) can be
read to determine whether the tail end of the frame that
suffers the LCOL error is still in the host memory (i.e.,
when XMTFC = 0). This XMTFC read should be re-
quested before the Transmit Frame Status read since
reading the XMTFS would cause the XMTFC to decre-
ment. If the tail end of the frame is indeed still in the host
memory, the host is responsible for ensuring that the tail
end of the frame does not get written into the FIFO and
does not get transmitted as a whole frame. It is recom-
mended that the host clear the tail end of the frame from
the host memory before requesting the XMTFS read so
that after the XMTFS read,when the MACE device re-
asserts TDTREQ, the tail end of the frame does not get
written into the FIFO. The Transmit Frame Status read
will indicate that the LCOL error occurred. The read op-
eration on the Transmit Frame Status will update the
FIFO read and write pointers. If no End-of-Frame write
(EOF pin assertion) had occurred during the FIFO write
sequence, the entire transmit path will be reset (which
will update the Transmit FIFO watermark with the cur-
rent XMTFW value in the FIFO Configuration Control
register). If a whole frame resides in the FIFO, the read
pointer will be moved to the start of the next frame or free
location in the FIFO, and the write pointer will be unaf-
fected. TDTREQ will not be re-asserted until the Trans-
mit Frame Status has been read.
Abnormal network conditions include:
(a) Loss of carrier.
(b) Late collision.
(c) SQE Test Error.
These should not occur on a correctly configured 802.3
network, but will be reported if the network has been in-
correctly configured or a fault condition exists.
(a) A loss of carrier condition will be reported if the
MACE device cannot observe receive activity while it is
transmitting. After the MACE device initiates a transmis-
sion it will expect to see data looped-back on the receive
input path. This will internally generate a carrier sense,
indicating that the integrity of the data path to and from
theexternalMAUisintact, andthattheMAUisoperating
correctly.
When the AUI port is selected, if carrier sense does not
become active in response to the data transmission, or
becomes inactive before the end of transmission, the
loss of carrier (LCAR) error bit will be set in the Transmit
Frame Status (bit 7) after the packet has been transmit-
ted. The packet will not be re-tried on the basis of an
LCAR error.
When the 10BASE-T port is selected, LCAR will be re-
ported for every packet transmitted during the Link fail
condition.
After an LCOL error, all further packet transmission will
be suspended until the Transmit Frame Status is read,
regardless of whether additional packet data exists in
the FIFO to be transmitted. Receive FIFO operations
are unaffected.
When the GPSI port is selected, LCAR will be reported if
the RXCRS input pin fails to become active during a
transmission, or once active, goes inactive before the
end of transmission.
Packets experiencing a late collision will not be re-tried.
Recovery from this condition must be performed by up-
per layer software.
When the DAI port is selected, LCAR errors will not oc-
cur, since the MACE device will internally loop back the
transmit data path to the receiver. The loop back feature
must not be performed by the external transceiver when
the DAI port is used.
(c) During the inter packet gap time following the com-
pletion of a transmitted message, the AUI CI± pair is
asserted by some transceivers as a self-test. When the
AUIporthasbeenselected, theintegralManchesterEn-
coder/Decoder will expect the SQE Test Message
During internal loopback, LCAR will not be set, since the
MACE device has direct control of the transmit and re-
ceive path integrity. When in external loopback, LCAR
Am79C940
51
AMD
(nominal 10 MHz sequence) to be returned via the CI±
pair, within a 40 network bit time period after DI± goes
inactive. If the CI± input is not asserted within the 40 net-
work bit time period following the completion of trans-
mission, then the MACE device will set the CERR bit (bit
5) in the Interrupt Register. The INTR pin will be acti-
vated if the corresponding mask bit CERRM = 0.
when XMTFC = 0). In the case of FIFO underrun, this
will definitely be the case and the host is responsible for
ensuring that the tail end of the frame does not get writ-
ten into the FIFO and does not get transmitted as a
whole frame. It is recommended that the host clear the
tail end of the frame from the host memory before re-
questing the XMTFS read so that after the XMTFS read,
when the MACE device re-assertsTDTREQ, the tail end
of the frame does not get written into the FIFO. The
Transmit Frame Status read will indicate that the UFLO
error occurred. The read operation on the Transmit
Frame Status will update the FIFO read and write point-
ers and the entire transmit path will be reset (which will
update the Transmit FIFO watermark with the current
XMTFW value in the FIFO Configuration Control regis-
ter). TDTREQ will not be re-asserted until the Transmit
Frame Status has been read.
When the GPSI port is selected, the MACE device will
expect the CLSN input pin to be asserted 40 bit times af-
ter the transmission has completed (after TXEN output
pin has gone inactive). When the DAI port has been se-
lected, the CERR bit will not be reported. A transceiver
connected via the DAI port is not expected to support
the SQE Test Message feature.
Host related transmit exception conditions include:
(a) Overflow caused by excessive writes to the Trans-
mit FIFO (DTV will not be issued if the Transmit
FIFO is full).
(c) The MACE device will internally store the Transmit
Frame Status for up to two packets. If the host fails to
read the Transmit Frame Status and both internal
entries become occupied, the MACE device will not
commence any subsequent transmit frames to prevent
overwriting of the internally stored values. This will
occur regardless of the number of bytes written to the
Transmit FIFO.
(b) Underflow caused by lack of host writes to the
Transmit FIFO.
(c) Not reading current Transmit Frame Status.
(a) The host may continue to write to the Transmit FIFO
aftertheTDTREQhasbeende-asserted, andcansafely
do so on the basis of knowledge of the number of free
bytes remaining (set by XMTFW in the FIFO
Configuration Control register). If however the host sys-
tem continues to write data to the point that no additional
FIFO space exists, the MACE device will not return the
DTV signal and hence will effectively not acknowledge
acceptance of the data. It is the host’s responsibility to
ensure that the data is re-presented at a future time
when space exists in the Transmit FIFO, and to track the
actual data written into the FIFO.
RECEIVE OPERATION
The receive operation and features of the MACE device
are controlled by programmable options. These options
are programmed through the BIU, FIFO and MAC Con-
figuration Control registers.
Parameters controlled by the MAC Configuration Con-
trol register are generally programmed only once, dur-
ing initialization, and are therefore static during the
normal operation of the MACE device (see the Media
Access Control section for a detailed description). The
features controlled by the FIFO Configuration Control
register and the Receive Frame Control register can be
programmed without performing a reset on the part. The
host is responsible for ensuring that no data is present in
the Receive FIFO when re-programming the receive
attributes.
(b) If the host fails to respond to the TDTREQ from the
MACE device before the Transmit FIFO is emptied, a
FIFO underrun will occur. The MACE device will in this
case terminate the network transmission in an orderly
sequence. If less than 512 bits have been transmitted
onto the network the transmission will be terminated im-
mediately, generating a runt packet. If greater than 512
bits have been transmitted, the message will have the
current CRC inverted and appended at the next byte
boundary, to guarantee an FCS error is detected at the
receiving station. The MACE device will report this con-
dition to the host by de-asserting the TDTREQ pin, set-
ting the UFLO and XMTSV bits (in the Transmit Frame
Status) and the XMTINT bit (in the Interrupt Register),
and asserting the INTR pin providing the corresponding
XMTINTM bit (in the Interrupt Mask Register) is cleared.
Receive FIFO Read
The Receive FIFO is accessed by performing a host
generated read sequence on the MACE device. See the
Slave Access Operation-Read Access section and the
AC Waveforms section, Host System Interface, figures:
”2 Cycle Receive FIFO/Register Read Timing” and ”3
Cycle Receive FIFO/Register Read Timing” for details
of the read access timing.
Note that EOF will be asserted by the MACE device dur-
Once the XMTINT condition has been externally recog-
nized, the Transmit Frame Counter (XMTFC) can be
read to determine whether the tail end of the frame that
suffers the UFLO error is still in the host memory (i.e.,
ing the last data byte/word transfer.
52
Am79C940
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(ii) When the RPA bit has been set in the User Test
Register, and a runt packet of at least 8 bytes has
been received.
Receive Function Programming
The Receive Frame Control register allows program-
ming of the automatic pad field stripping feature and the
configuration of the Match/Reject (M/R) pin. ASTRP
RCV and M/R must be static when the receive function
is enabled (ENRCV = 1). The receiver should be dis-
abled before (re-) programming these options.
(iii) When the LLRCV bit has been set in the Receive
Frame Control register, and at least 12-bytes (after
SFD) has been received.
No preamble/SFD bytes are loaded into the Receive
FIFO. All references to bytes past through the receive
FIFO are received after the preamble/SFD sequence.
The EADI port can be used to permit reception of frames
to commence whilst external address decoding takes
place. TheM/RbitdefinesthefunctionoftheEAM/Rpin,
and hence whether frames will be accepted or rejected
by the external address comparison logic.
Depending on the bus latency of the system, RCVFW
can be set to ensure that the RCVFIFO does not over-
flow before more data is read. When the entire frame is
in the RCVFIFO, RDTREQ will be asserted regardless
of the value in RCVFW. The default value of RCVFW is
64-bytes after hardware or software reset.
The programming of additional receive attributes are
distributed between the FIFO and MAC Configuration
Control registers, and the User Test Register.
AllreceiveframescanbeacceptedbysettingthePROM
bit (bit 7) in the MAC Configuration Control register.
When PROM is set, the MACE device will attempt to re-
ceive all messages, subject to minimum frame enforce-
ment. Setting PROM will override the use of the EADI
port to force the rejection of unwanted messages. See
the sections External Address Detection Interface for
more details.
ThereceiveoperationoftheMACEdevicecanbehalted
at any time by clearing the ENRCV bit in the MAC Con-
figuration Control register. Note that any receive frame
currently in progress will be accepted normally, and the
MACE device will disable the receive process once the
message has completed. The Missed Packet Count
(MPC) will be incremented for subsequent packets that
would have normally been passed to the host, and are
now ignored due to the disabled state of the receiver.
The point at which RDTREQis asserted in relation to the
number of bytes of a frame that are present in the Re-
ceive FIFO (RCVFIFO) is controlled by the RCVFW bits
in the FIFO Configuration Control register, or the
LLRCV bit in the Receive Frame Control register.
RDTREQ will be asserted when one of the following
conditions is true:
Note that clearing the ENRCV bit disables the assertion
of RDTREQ. If ENRCV is cleared during receive activity
and remains cleared for a long time and if the tail end of
the receive frame currently in progress is longer than the
amountofspaceavailableintheReceiveFIFO, Receive
FIFO overflow will occur. However, even with RDTREQ
deasserted, if there is valid data in the Receive FIFO to
be read, successful slave reads to the Receive FIFO
can be executed (indicated by valid DTV). It is the host’s
responsibility to avoid the overflow situation.
(i) There are at least 64 bytes in the RCVFIFO.
(ii) The received packet has passed the 64 byte mini-
mum criteria, and the number of bytes in the
RCVFIFO is greater than or equal to the threshold
set by the RCVFW (16 or 32 bytes).
Automatic Pad Stripping
During reception of a frame the pad field can be stripped
automatically. ASTRP RCV = 1 enables the automatic
pad stripping feature. The pad field will be stripped be-
fore the frame is passed to the FIFO, thus preserving
FIFO space for additional frames. The FCS field will also
be stripped, since it is computed at the transmitting sta-
tion based on the data and pad field characters, and will
be invalid for a receive frame that has the pad charac-
ters stripped.
(iii) A receive packet has completed, and part or all of it
is present in the RCVFIFO.
(iv) The LLRCV bit has been set and greater than
12-bytes of at least 8 bytes have been received.
Note that if the RCVFW is set below the 64-byte limit, the
MACE device will still require 64-bytes of data to be re-
ceived before the initial assertion of RDTREQ. Subse-
quently, RDTREQ will be asserted at any time the
RCVFW threshold is exceeded. The only times that the
RDTREQ will be asserted when there are not at least an
initial 64-bytes of data in the RCVFIFO are:
The number of bytes to be stripped is calculated from
the embedded length field (as defined in the IEEE 802.3
definition) contained in the packet. The length indicates
the actual number of LLC data bytes contained in the
message. Any received frame which contains a length
field less than 46 bytes will have the pad field stripped.
(i) When the ASTRP RCV bit has been set in the Re-
ceive Frame Control register, and the pad is auto-
matically stripped from a minimum length packet.
Am79C940
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Receive frames which have a length field of 46 bytes or
greater will be passed to the host unmodified.
Note that for some network protocols, the value passed
in the Ethernet Type and/or 802.3 Length field is not
compliant with either standard and may cause
problems.
Since any valid Ethernet Type field value will always be
greater than a normal 802.3 Length field, the MACE de-
vice will not attempt to strip valid Ethernet frames.
The diagram below shows the byte/bit ordering of the re-
ceivedlengthfieldforan802.3compatibleframeformat.
46-1500
Bytes
56
8
6
6
2
4
Bits
Bits
Bytes
Bytes
Bytes
Bytes
Preamble
SYNCH
Dest.
SRCE.
ADDR.
Length
LLC
Pad
FCS
1010....1010
10101011
ADDR.
DATA
1-1500
Bytes
45-0
Bytes
Start of Packet
at Time= 0
Bit
0
Bit Bit
Bit
7
7
0
Increasing Time
Most
Significant
Byte
Least
Significant
Byte
16235C-9
802.3 Packet and Length Field Transmission Order
used to read the Receive Frame Status through the Re-
ceive FIFO. In either case, the 4-byte total must be read
before additional receive data can be read from the Re-
ceive FIFO. However, the RDTREQ indication will con-
tinue to reflect the state of the Receive FIFO as normal,
regardless of whether the Receive Frame Status has
been read. DTV will not be returned when a read opera-
tion is performed on the Receive Frame Status location
and no valid status is present or ready.
Receive FCS Checking
Reception and checking of the received FCS is per-
formed automatically by the MACE device. Note that if
the Automatic Pad Stripping feature is enabled, the re-
ceived FCS will be verified against the value computed
for the incoming bit stream including pad characters, but
it will not be passed through the Receive FIFO to the
host. If an FCS error is detected, this will be reported by
the FCS bit (bit 4) in the Receive Frame Status.
Note that the Receive Frame Status can be read using
either the Register Address or FIFO Direct modes. For
additional details, see the section Receive FIFO Read.
Receive Status Information
The EOF indication signals that the last byte/word of
data has been passed from the FIFO for the specific
frame. ThiswillbeaccompaniedbyaRCVINTindication
in the the Interrupt Register signaling that the Receive
Frame Status has been updated, and must be read. The
Receive Frame Status is a single location which must be
read four times to allow the four bytes of status informa-
tion associated with each frame to be read. Further data
read operations from the Receive FIFO using the Regis-
ter Address mode, will be ignored by the MACE device
(indicated by the MACE chip not returning DTV) until all
four bytes of the Receive Frame Status have been read.
Alternatively, the FIFO Direct access mode may be
Receive Exception Conditions
Exception conditions for frame reception fall into two
distinct categories; those which are the result of normal
network operation, and those which occur due to abnor-
mal network and/or host related events.
Normal events which may occur and which are handled
autonomously by the MACE device are basically colli-
sions within the slot time and automatic runt packet de-
letion. The MACE device will ensure that any receive
packet which experiences a collision within 512 bit times
54
Am79C940
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from the start of reception (excluding preamble) will be
automatically deleted from the Receive FIFO with no
host intervention (the state of the RPA bit in the User
Test Register; or the RCVFW bits in the FIFO Configu-
ration Control register have no effect on this). This crite-
ria will be met, regardless of whether the receive frame
was the first (or only) frame in the Receive FIFO, or if the
receive frame was queued behind a previously received
message.
the Receive Frame Status through the Receive FIFO,
but the host must be aware that the subsequent four cy-
cles will yield the receive status bytes, and not data from
the same or a new packet. Only the OFLO bit will be
valid in the Receive Frame Status, other error/status
and the RCVCNT fields are invalid.
While the Receive FIFO is in the overflow condition, it is
deaftoadditionalreceivedataonthenetwork. However,
the MACE device internal address detect logic contin-
ues to operate and counts the number of packets that
would have been passed to the host under normal (non
overflow) conditions. The Missed Packet Count (MPC)
is an 8–bit count (in register 24) that maintains the num-
ber of packets which pass the address match criteria,
and complete without collision. The MPC counter will
wrap around when the maximum count of 255 is
reached, setting the MPCO (Missed Packet Count
Overflow) bit in the Interrupt Register, and asserting the
INTR pin providing that MPCOM (Missed Packet Count
Overflow Mask) in the Interrupt Mask Register is clear.
MPCO will be cleared (the interrupt will be unmasked)
after hardware or software reset. However, until the first
time that the receiver is enabled, MPC will not
increment, hence no interrupt will occur due to missed
packets after a reset.
Abnormal network conditions include:
■ FCS errors
■ Framing errors
■ Dribbling bits
■ Late collision
These should not occur on a correctly configured 802.3
network, but may be reported if the network has been in-
correctly configured or a fault condition exists.
Host related receive exception conditions include:
(a) Underflow caused by excessive reads from the Re-
ceive FIFO (DTV will not be issued if the Receive
FIFO is empty)
(c) Failure to read packet data from the Receive FIFO
will eventually cause an overflow condition. The FIFO
will maintain any previously completed packet(s), which
can be read by the host at its convenience. However,
packet data on the network will no longer be received,
regardless of destination address, until the overflow is
cleared by reading the remaining Receive FIFO data
and Receive Status. The MACE device will increment
the Missed Packet Count (MPC) register to indicate that
a packet which would have been normally passed to the
host, was dropped due to the error condition.
(b) Overflow caused by lack of host reads from the Re-
ceive FIFO
(c) Missed packets due to lack of host reads from the
Receive FIFO and/or the Receive Frame Status
(a) Successive read operations from the Receive FIFO
after the final byte of data/status has been read, will
cause the DTV pin to remain de-asserted during the
read operation, indicating that no valid data is present.
There will be no adverse effect on the Receive FIFO.
(b) Data present in the Receive FIFO from packets
which completed before the overflow condition oc-
curred, can be read out by accessing the Receive FIFO
normally. Once this data (and the associated Receive
Frame Status) has been read, the EOF indication will be
asserted by the MACE device during the first read op-
eration takes place from the Receive FIFO, for the pack-
et which suffered the overflow. If there were no other
packets in the FIFO when the overflow occurred, the
EOF will be asserted on the first read from the FIFO. In
either case, the EOF indication will be accompanied by
assertion of the INTR pin, providing that the RCVINTM
bit in the Interrupt Mask Register is not set. If the Regis-
ter Address mode is being used, the host is required to
access the Receive Frame Status location using four
separate read cycles. Further access to the Receive
FIFO will be ignored by the MACE device until all four
bytesoftheReceiveFrameStatushavebeenread.DTV
will not be returned if a Receive FIFO read is attempted.
If the FIFO Direct mode is being used, the host can read
LOOPBACK OPERATION
During loopback, the FCS logic can be allocated to the
receiver by setting RCVFCSE = 1 in User Test Register.
This permits both the transmit and receive FCS opera-
tions to be verified during the loopback process. The
state of RCVFCSE is only valid during loopback
operation.
IfRCVFCSE=0, theMACEdevicewillcalculateandap-
pend the FCS to the transmitted message. The receive
message passed to the host will therefore contain an
additional four bytes of FCS. The Receive Frame Status
will indicate the result of the loopback operation and the
RCVCNT.
If RCVFCSE = 1, the last four bytes of the transmit mes-
sage must contain the FCS computed for the transmit
data preceding it. The MACE device will transmit the
Am79C940
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datawithoutadditionofanFCSfield, andtheFCSwillbe
calculated and verified at the receiver.
When in the loopback mode(s), the multicast address
detection feature of the MACE device, programmed by
the contents of the Logical Address Filter (LADR [63–0])
can only be tested when RCVFCSE = 1, allocating the
CRC generator to the receiver. All other features
operate identically in loopback as in normal operation,
such as automatic transmit padding and receive
pad stripping.
The loopback facilities of the MACE device allow full op-
eration to be verified without disturbance to the network.
Loopback operation is also affected by the state of the
Loopback Control bits (LOOP [0–1]) in the User Test
Register. This affects whether the internal MENDEC is
considered part of the internal or external loop-
back path.
56
Am79C940
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use of byte transfers have implications on the latency
time provided by the XMTFIFO (see the FIFO Sub-
Systemsectionforadditionaldetails). Theexternalhost/
controller must indicate the last byte/word of data in a
transmit frame is being written to the XMTFIFO, by as-
serting the EOF signal.
USER ACCESSIBLE REGISTERS
The following registers are provided for operation of the
MACE device. All registers are 8-bits wide unless other-
wise stated. Note that all reserved register bits should
be written as zero.
Receive FIFO (RCVFIFO)
(REG ADDR 0)
Transmit Frame Control (XMTFC) (REG ADDR 2)
RCVFIFO [15–0]
The Transmit Frame Control register is latched inter-
nally on the last write to the Transmit FIFO for each indi-
vidual packet, when EOF is asserted. This permits
automatic transmit padding and FCS generation on a
packet-by-packet basis.
This register provides a 16-bit data path from the Re-
ceive FIFO. Reading this register will read one word/
byte from the Receive FIFO. The RCVFIFO should only
be read when Receive Data Transfer Request
(RDTREQ) is asserted. If the RCVFIFO location is read
before 64-bytes are available in the RCVFIFO (or
12-bytes in the case that LLRCV is set in the Receive
Frame Control register), DTV will not be returned. Once
the 64-byte threshold has been achieved and RDTREQ
is asserted, the de-assertion of RDTREQ does not pre-
vent additional data from being read from the RCVFIFO,
but indicates the number of additional bytes which are
present, before the RCVFIFO is emptied, and
subsequent reads will not return DTV (see the FIFO
Sub-System section for additional details). Write opera-
tions to this register will be ignored and DTV will not be
returned.
DRTRY RES
RES
RES DXMTFCS RES
RES APAD XMT
Bit
Name
Description
Bit 7
DRTRY
Disable Retry. When DRTRY is
set, the MACE device will provide
a single transmission attempt for
the packet, all further retries will
be suspended. In the case of a
collision during the attempt, a
Retry Error (RTRY) will be re-
ported in the Transmit Status.
With DRTRY cleared, the MACE
device will attempt up to 15 re-
tries (16 attempts total) before in-
dicating a Retry Error. DRTRY is
cleared by activation of the RE-
SETpin or SWRST bit. DRTRY is
sampled during the transmit
process when a collision occurs.
DRTRY should not be changed
whilst data remains in the Trans-
mit FIFO since this may cause an
unpredictable retry response to a
collision. Once the Transmit
FIFO is empty, DRTRY can be
reprogrammed.
Byte transfers from the RCVFIFO are supported, and
will be fully aligned to the target memory architecture,
defined by the BSWP bit in the BIU Configuration Con-
trol register. The Byte Enable inputs (BE1–0) will define
which half of the data bus should be used for the trans-
fer. The external host/controller will be informed that the
last byte/word of data in a receive frame is being read
from the RCVFIFO, when the MACE device asserts the
EOF signal.
Transmit FIFO (XMTFIFO)
(REG ADDR 1)
XMTFIFO [15–0]
This register provides a 16-bit data path to the Transmit
FIFO. Byte/word data written to this register will be
placed in the Transmit FIFO. The XMTFIFO can be writ-
ten at any time the Transmit Data Transfer Request
(TDTREQ) is asserted. The de-assertion of TDTREQ
doesnotpreventdatabeingwrittentotheXMTFIFO, but
indicates the number of additional write cycles which
can take place, before the XMTFIFO is filled, and
subsequent writes will not return DTV (see the FIFO
Sub-System section for additional details). Read opera-
tions to this register will be ignored and DTV will not be
returned.
Bit 6–4 RES
Bit 3
Reserved. Read as zeroes. Al-
ways write as zeroes.
DXMTFCS Disable Transmit FCS. When
DXMTFCS = 0 the transmitter
will generate and append an FCS
to the transmitted frame. When
DXMTFCS = 1, no FCS will be
appended to the transmitted
frame, providing that APAD XMT
is also clear. If APAD XMT is set,
the calculated FCS will be ap-
pended to the transmitted mes-
sage regardless of the state of
DXMTFCS. The value of
DXMTFCS for each frame is pro-
grammed when EOF is asserted
to transfer the last byte/word for
the transmit packet to the FIFO.
DXMTFCS is cleared by
Byte transfers to the XMTFIFO are supported, and ac-
cept data from the source memory architecture to en-
sure the correct byte ordering for transmission, defined
by the BSWP bit in the MAC Configuration Control regis-
ter. The Byte Enable inputs (BE1–0) will define which
half of the data bus should be used for the transfer. The
Am79C940
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activation of the RESET pin or
SWRST bit. DXMTFCS is sam-
pled only when EOF is asserted
during a Transmit FIFO write.
Bit 5
LCOL
Late Collision. Indicates that a
collision occurred after the slot
time of the channel elapsed. If
LCOL is set, TDTREQ will be de-
asserted, and will not be
re-asserted until the XMTFS has
been read. The MACE device
does not retry after a late
collision.
Bit
Bit 2–1 RES
Bit 0
Name
Description
Reserved. Read as zeroes. Al-
ways write as zeroes.
Bit 4
Bit 3
Bit 2
MORE
ONE
More. Indicates that more than
one retry was needed to transmit
the frame. ONE, MORE and
RTRY are mutually exclusive.
APAD XMT Auto Pad Transmit. APAD XMT
enables the automatic padding
feature. Transmit frames will be
padded to extend them to 64
bytes including FCS. The FCS is
calculated for the entire frame in-
cluding pad, and appended after
the pad field. APAD XMT will
override the programming of the
DXMTFCS bit. APAD XMT is set
by activation of the RESET pin or
SWRST bit. APAD XMT is sam-
pled only when EOF is asserted
during a Transmit FIFO write.
One. Indicates that exactly one
retry was needed to transmit the
frame. ONE, MORE and RTRY
are mutually exclusive.
DEFER
Defer. Indicates that MACE de-
vice had to defer transmission of
the frame. This condition results
if the channel is busy when the
MACE device is ready to
transmit.
Transmit Frame Status (XMTFS)
(REG ADDR 3)
Bit 1
LCAR
Loss of Carrier. Indicates that the
carrier became false during a
transmission. The MACE device
does not retry upon Loss of Car-
rier. LCAR will not be set when
the DAI port is selected, when
the 10BASE-T port is selected
and in the link pass state, or dur-
ing any internal loopback mode.
When the 10BASE-T port is se-
lected and in the link fail state,
LCAR will will be reported for any
transmission attempt.
The Transmit Frame Status is valid when the XMTSV bit
is set. The register is read only, and is cleared when
XMTSV is set and a read operation is performed. The
XMTINT bit in the Interrupt Register will be set when any
bit is set in this register.
Note that if XMTSV is not set, the values in this register
can change at any time, including during a read opera-
tion. This register should be read after the Transmit Re-
try Count (XMTRC). See the description of the Transmit
Retry Count (XMTRC) for additional details.
Bit 0
RTRY
Retry Error. Indicates that all at-
tempts to transmit the frame
were unsuccessful, and that fur-
therattemptshavebeenaborted.
If Disable Retry (DRTRY in the
Transmit Frame Control register)
is cleared, RTRY will be set when
a total of 16 unsuccessful at-
tempts were made to transmit the
frame. If DRTRY is set, RTRY in-
dicates that the first and only at-
tempt to transmit the frame was
unsuccessful. ONE, MORE and
RTRY are mutually exclusive. If
RTRY is set, TDTREQ will be de-
asserted, and will not be re-
asserted until the XMTFS has
been read.
XMTSV UFLO
LCOL
MORE
ONE DEFER LCAR
RTRY
Bit
Name
XMTSV
Description
Bit 7
Transmit Status Valid. Transmit
Status Valid indicates that this
status is valid for the last frame
transmitted. The value of XMTSV
will not change during a read op-
eration.
Bit 6
UFLO
Underflow. Indicates that the
Transmit FIFO emptied before
the end of frame was reached.
The transmitted frame is trun-
cated at that point. If UFLO is set,
TDTREQ will be de-asserted,
and will not be re-asserted until
the XMTFS has been read.
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Transmit Retry Count (XMTRC)
(REG ADDR 4)
low threshold (12-bytes after
SFD plus synchronization) has
The Transmit Retry Count should be read only in re-
sponse to a hardware interrupt request (INTR asserted)
when XMTINT is set in the Interrupt Register, or after
XMTSV is set in the Poll Register.The register should be
read before the Transmit Frame Status register. Read-
ing the Transmit Frame Status with XMTSV set will
cause the XMTRC value to be reset. This register is
read only.
been
exceeded,
causing
RDTREQ to be asserted.
RDTREQ will remain asserted as
long as one read cycle can be
performed on the RCVFIFO
(identical to the burst mode).
Indication of a valid read cycle
from the RCVFIFO will return
DTV asserted. Reading the
RCVFIFO before data is avail-
able, or while waiting for addi-
tional data once a packet is in
progress will not cause the
RCVFIFO to underflow, and will
be indicated by DTV being inva-
lid. The MACE device will no
longer be able to reject runts in
this mode, this responsibility is
transferred to the host system. In
the case of a collided packet
(normal slot time collision or late
collision), the MACE device will
abort the reception, and return
the RCVFS. Note that all colli-
sions in this mode will appear as
late collisions and be reported by
the CLSN bit in the Receive
Status (RCVSTS) byte.
EXDEF RES
RES
RES XMTRC[3–0]
Bit
Name
Description
Bit 3-0 EXDEF
Excessive Defer. The EXDEF bit
will be set if a transmit frame
waited for an excessive period
for transmission. An excessive
defer time is defined in accor-
dance with the following (from
page 34, section 5.2.4.1 of IEEE
Std802.3h–1990LayerManage-
ment):maxDeferTime = {2 x (max
frame size x 8)} bits where
maxFrameSize = 1518 bytes
(from page 68, section 4.4.2.1 of
ANSI/IEEE Std 802.3–1990).
So, the maxDeferTime = 24288
bits = 214+ 212 + 211+ 210 + 29 +27
+26 +25
If the host does not keep up with
the incoming receive data, nor-
mal RCVFIFO overflow recovery
is provided.
Bit 6–4 RES
Reserved. Read as zeroes. Al-
ways write as zeroes.
Bit 3–0 XMTRC
[3–0]
Transmit Retry Count. Contains
the count of the number of retry
attempts made by the MACE de-
vice to transmit the current trans-
mit packet. The value of the
counter will be zero if the first
transmission attempt was suc-
cessful, and a maximum of 15 if
all retry attempts were utilized.
RTRY will be set in Transmit
Frame Status if all 16 attempts
were unsuccessful.
Bit 2
M/R
Match/Reject. The Match/Reject
option sets the criteria for the Ex-
ternal Address Detection Inter-
face. If set, the EAM/R pin is
configured as External Address
Match, and is used to signal the
acceptance of a receive frame to
the MACE device. If cleared, the
pin functions as External Ad-
dress Reject and is used to flush
unwanted packets from the Re-
ceive FIFO prior to the first asser-
tion of RDTREQ. M/R is cleared
by activation of the RESET pin or
SWRST bit. When the EADI fea-
ture is disabled, the EAM/R pin
must be tied active (low) and all
normal receive address recogni-
tion configurations are supported
(physical, logical and promiscu-
ous). See the section “External
Address Detection Interface” for
additional details.
Receive Frame Control (RCVFC)
(REG ADDR 5)
RES
RES
RES
RES
LLRCV
M/R
RES ASTRPRCV
Bit
Name
Description
Bit 7–4 RES
Bit 3 LLRCV
Reserved. Read as zeroes. Al-
ways write as zeroes.
Low Latency Receive. A pro-
grammable option to allow ac-
cess to the Receive FIFO before
the 64-byte threshold has been
reached. When set, data can be
read from the RCVFIFO once a
Bit 1
RES
Reserved. Read as zero. Always
write as zero.
Am79C940
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Bit 0 ASTRP RCV Auto Strip Receive. ASTRP RCV
enables the automatic pad strip-
ping feature. The pad and FCS
fields will be stripped from re-
ceive frames and not placed in
the FIFO. ASTRP RCV is set by
activation of the RESET pin or
the SWRST bit.
RFS1—Receive Status (RCVSTS)
OFLO CLSN FRAM FCS
RCVCNT [10:8]
Bit
Name
OFLO
Description
Bit 7
Overflow flag. Indicates that the
Receive FIFO over flowed due to
the inability of the host/controller
to read data fast enough to keep
pace with the receive serial bit
stream and the latency provided
by the Receive FIFO itself. OFLO
is indicated on the receive frame
that caused the overflow condi-
tion; complete frames in the Re-
ceive FIFO are not affected.
While the Receive FIFO is in the
overflow condition, it ignores ad-
ditional receive data on the net-
work. The internal address
detect logic will continue to oper-
ate and the Missed Packet Count
(MPC in register 24) will be incre-
mented for each packet which
passes the address match
criteria, and complete without
collision.
Receive Frame Status (RCVFS)
(REG ADDR 6)
RCVFS [31–00]
The Receive Frame Status is a single byte location
which must be read by four read cycles to obtain the four
bytes (32-bits) of status associated with each receive
frame. Receive Frame Status can be read using either
the Register Direct or FIFO Direct access modes.
InRegisterDirectmode, accesstotheReceiveFIFOwill
be denied until all four status bytes for the completed
frame have been read from the Receive Frame Status
location. In FIFO Direct mode, the Receive Frame
Status is read through the Receive FIFO location, by
continuing to execute four read cycles after the comple-
tion of packet data (and assertion of EOF). The Receive
Frame Status can be read using either mode, or a com-
binationofbothmodes, howevereachstatusbytewillbe
presented only once regardless of access method.
Other register reads and/or writes can be interleaved at
any time, during the Receive Frame Status sequence.
Bit 6
CLSN
Collision Flag. Indicates that the
receive operation suffered a colli-
sion during reception of the
frame. If CLSN is set, it indicates
that the receive frame suffered a
late collision, since a frame expe-
riencing collision within the slot
time will be automatically deleted
from the RCVFIFO (providing
LLRCV in the Receive Frame
Control register is cleared). Note
that if the LLRCV bit is enabled,
the late collision threshold is ef-
fectively moved from the normal
64-byte (512-bit) level to the
12-byte (96-bit) level. Runt pack-
ets suffering a collision will be
flushed from the RCVFIFO re-
gardless of the state of the RPA
bit (User Test Register). CLSN
will not be set if OFLO is set.
The Receive Frame Status consists of the following four
bytes of information:
RFS0 Receive Message Byte Count
(RCVCNT) [7–0]
RFS1 Receive Status, (RCVSTS) [11–8]
RFS2 Runt Packet Count (RNTPC) [7–0]
RFS3 Receive Collision Count (RCVCC) [7–0]
RFS0—Receive Message Byte Count (RCVCNT)
RCVCNT [7:0]
Bit
Name
Description
Bit 7-0 RCVCNT The Receive Message Byte
[7:0]
Count indicates the number of
whole bytes in the received mes-
sage. If pad bytes were stripped
from the received frame,
RCVCNT indicates the number
of bytes received less the num-
ber of pad bytes and less the
number of FCS bytes. RCVCNT
is 12 bits long. If a late collision is
detected (CLSN set in RCVSTS),
the count is an indication of the
length (in byte times) of the dura-
tion of the receive activity includ-
ing the collision. RCVCNT [10:8]
correspond to bits 3–0 in RFS1 of
the Receive Frame Status.
RCVCNT [11–0] will be invalid
when OFLO is set.
Bit 5
FRAM
Framing Error flag. Indicates that
the received frame contained a
non-integer multiple of bytes and
an FCS error. If there was no
FCS error then FRAM will not be
set. FRAM is not valid during in-
ternal loopback. FRAM will not
be set if OFLO is set.
Bit 4
FCS
FCS Error flag. Indicates that
there is an FCS error in the
frame. The receive FCS is com-
puted and checked normally
when ASTRP RCV = 1, but is not
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Am79C940
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passed to the host. FCS will not
be set if OFLO is set.
RCVFC reaches its maximum
value of 15, additional receive
frames will be ignored, and the
Missed Packet Count (MPC) reg-
ister will be incremented for
frames which match the internal
address(es) of the MACE device.
Bit 3–0 RCVCNT
[11:8]
The Receive Message Byte
Count indicates the number of
whole bytes in the received mes-
sage from the network. RCVCNT
is 12 bits long, and valid (accu-
rate) only when there are no er-
rors reported in the Receive
Status (RCVSTS). If a late colli-
sion is detected (CLSN set in
RCVSTS), the count is an indica-
tion of the length (in byte times) of
the duration of the receive activ-
ity including the collision.
RCVCNT [7:0] correspond to bits
7–0 in RFS0 of the Receive
Frame Status. RCVCNT [11–0}
will be invalid when OFLO is set.
Bit 3–0 XMTFC
[3–0]
Transmit Frame Count. The
(read only) count of the frames in
the Transmit FIFO. A frame is
counted when the last byte is put
in the FIFO. The counter is
decremented when XMTSV (in
the Transmit Frame Status and
Poll Register) is set and the
Transmit Frame Status read ac-
cess is performed.
Interrupt Register (IR)
(REG ADDR 8)
All status bits are set upon occurrence of an event and
cleared when read. The resister is read only. In addition
all status bits are cleared by hardware or software reset.
Bit assignments for the register are as follows:
RFS2—Runt Packet Count (RNTPC)
RNTPC [7–0]
Bit
Name
Description
JAB BABL CERR RCVCCO RNTPCO MPCO RCVINT XMTINT
Bit 7–0 RNTPC
[7–0]
The Runt Packet Count indicates
the number of runt packets re-
ceived, addressed to this node,
since the last successfully re-
ceived packet. The value does
not roll over after 255 runt pack-
ets have been detected, and will
remain frozen at the maximum
count.
Bit
Name
JAB
Description
Bit 7
Jabber Error. JAB indicates that
the MACE device attempted to
transmit for an excessive time
period (20–150 ms), when using
either the DAI port or the
10BASE-T port. If the internal
jabber timer expires during trans-
mission, the transmit bit stream
will be interrupted, until the inter-
nal transmission ceases and the
unjab timer (0.5 s ±0.25 s) ex-
pires. The jabber function will be
disabled, and JAB will not be
set, regardless of transmission
length, when either the AUI or
GPSI ports have been selected.
RFS3—Receive Collision Count (RCVCC)
RCVCC [7–0]
Bit
Name
Description
Bit 7–0 RCVCC
[7–0]
The Receive Collision Count in-
dicates the number of collisions
detected on the network since
the last successfully received
packet. The value does not roll
over after 255 collisions have
been detected, and will remain
frozen at the maximum count.
JAB is READ/CLEAR only, and is
set by the MACE device and re-
set when read. Writing has no ef-
fect. It is also cleared by
activation of the RESET pin or
SWRST bit.
FIFO Frame Count (FIFOFC)
(REG ADDR 7)
RCVFC[3–0] XMTFC[3–0]
Bit 6
BABL
Babble Error. BABL is the trans-
mitter time-out error. It indicates
that the transmitter has been on
the channel longer than the time
required to send the maximum
packet. It will be set after 1519
bytes (or greater) have been
transmitted. The MACE device
will continue to transmit until the
current packet transmission is
over. The INTR pin will be acti-
Bit
Name
Description
Bit 7–4 RCVFC
[3–0]
Receive Frame Count. The (read
only) count of the frames in the
Receive FIFO.
A
frame is
counted when the last byte is put
in the FIFO. The counter is
decremented when the last byte
of the frame is read. If the
Am79C940
61
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vated if the corresponding mask
bit BABLM = 0.
reset when read. Writing has no
effect. It is also cleared by assert-
ing the RESETpin or SWRST bit.
BABL is READ/CLEAR only, and
is set by the MACE device and
reset when read. Writing has no
effect. It is also cleared by activa-
tion of the RESET pin or SWRST
bit.
Bit 3
RNTPCO
Runt Packet Count Overflow. In-
dicates that the Runt Packet
Count register rolled over at a
value of 255 runt packets. Runt
packets are defined as received
frames which passed the internal
address match criteria but did not
contain a minimum of 64-bytes of
data after SFD. The INTR pin will
be activated if the correspond-
ing mask bit RNTPCOM = 0.
Note that the RNTPC value re-
turned in the Receive Frame
Status (RFS2) will freeze at a
value of 255, whereas this regis-
ter based version of RNTPC
(REG ADDR 26) is free running.
Bit 5
CERR
Collision Error. CERR indicates
the absence of the Signal Quality
Error Test (SQE Test) message
after a packet transmission. The
SQE Test message is a trans-
ceiver test feature. Detection de-
pends on the MACE network
interface selected. In all cases,
CERR will be set if the MACE de-
vice failed to observe the SQE
Test message within 20 network
bit times after the packet trans-
mission ended. When CERR is
set, the INTR pin will be activated
if the corresponding mask bit
CERRM = 0.
RNTPCO is READ/CLEAR only.
It is set by the MACE device and
reset when read. Writing has no
effect. It is also cleared by assert-
ing the RESETpin or SWRST bit.
When the AUI port is selected,
the SQE Test message is re-
turned over the CI± pair as a brief
(5–15 bit times) burst of 10 MHz
activity. When the 10BASE-T
port is selected, CERR will be re-
ported after a transmission only
when the internal transceiver is in
the link fail state (LNKST pin =
HIGH). When the GPSI port is
selected, the CLSN pin must be
asserted by the external en-
coder/decoder to provide the
SQE Test function. When the
DAI port is selected, CERR will
not be reported at any time.
Bit 2
MPCO
Missed Packet Count Overflow.
Indicates that the Missed Packet
Count register rolled over at a
value of 255 missed frames.
Missed frames are defined as re-
ceived frames which passed the
internal address match criteria
but were missed due to a Re-
ceive FIFO overflow, the receiver
being disabled (ENRCV = 0) or
an excessive receive frame
count (RCVFC > 15). The INTR
pin will be activated if the corre-
sponding mask bit MPCOM = 0.
MPCO is READ/CLEAR only. It
is set by the MACE device and
reset when read. Writing has no
effect. It is also cleared by assert-
ing the RESETpin or SWRST bit.
CERR is READ/CLEAR only. It is
set by the MACE and reset when
read. Writing has no effect. It is
also cleared by activation of the
RESET pin or SWRST bit.
Bit 1
RCVINT
Receive Interrupt. Indicates that
the host read the last byte/word
of a packet from the Receive
FIFO. The Receive Frame Status
is available immediately on the
next host read operation. The
INTR pin will be activated if the
Bit 4
RCVCCO Receive Collision Count Over-
flow. Indicates that the Receive
Collision Count register rolled
over at a value of 255 receive col-
lisions. Receive collisions are de-
fined as received frames which
suffered a collision. The INTR pin
will be activated if the corre-
sponding mask bit RCVCCOM =
0. Note that the RCVCC value re-
turned in the Receive Frame
Status (RFS3) will freeze at a
value of 255, whereas this regis-
ter based version of RCVCC
(REG ADDR 27) is free running.
corresponding
RCVINTM = 0.
mask
bit
RCVINT is READ/CLEAR only. It
is set by the MACE device and
reset when read. Writing has no
effect. It is also cleared by activa-
tion of the RESET pin or SWRST
bit.
Bit 0
XMTINT
Transmit Interrupt. Indicates that
the MACE device has completed
RCVCCO is READ/CLEAR only.
It is set by the MACE device and
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Am79C940
AMD
the transmission of a packet and
updated the Transmit Frame
Status. The INTR pin will be acti-
vated if the corresponding mask
bit XMTINTM = 0.
Bit 3
RNTPCOM Runt Packet Count Overflow
Mask. RNTPCOM is the mask for
RNTPCO (Runt Packet Count
Overflow). The INTR pin will not
be asserted by the MACE device
regardless of the state of the
RNTPCO bit, if RNTPCOM is set.
It is cleared by activation of the
RESET pin or SWRST bit.
XMTINT is READ/CLEAR only. It
is set by the MACE device and
reset when read. Writing has no
effect. It is also cleared by activa-
tion of the RESET pin or SWRST
bit.
Bit 2
MPCOM
Missed Packet Count Overflow
Mask. MPCOM is the mask for
MPCO (Missed Packet Count
Overflow). The INTR pin will not
be asserted by the MACE device
regardless of the state of the
MPCO bit, if MPCOM is set. It is
cleared by activation of the
RESET pin or SWRST bit.
Interrupt Mask Register (IMR)
(REG ADDR 9)
This register contains the mask bits for the interrupts.
Read/write operations are permitted. Writing a one into
a bit will mask the corresponding interrupt. Writing a
zero to any previously set bit will unmask the corre-
sponding interrupt. Bit assignments for the register are
as follows:
Bit 1
RCVINTM Receive
Interrupt
Mask.
RCVINTM is the mask for
RCVINT. The INTRpin will not be
asserted by the MACE device re-
gardless of the state of the
RCVINT bit, if RCVINTM is set. It
is cleared by activation of the
RESET pin or SWRST bit.
RES BABLM CERRM RCVCCOM RNTPCOM MPCOM RCVINTM XMTINTM
Bit
Name
JABM
Description
Bit 7
Jabber Error Mask. JABM is the
mask for JAB. The INTR pin will
not be asserted by the MACE de-
vice regardless of the state of the
JAB bit, if JABM is set. It is
cleared by activation of the RE-
SET pin or SWRST bit.
Bit 0
XMTINTM Transmit
Interrupt
Mask.
XMTINTM is the mask for
XMTINT. The INTRpin will not be
asserted by the MACE device re-
gardless of the state of the
XMTINT bit, if XMTINT is set. It is
cleared by activation of the RE-
SET pin or SWRST bit.
Bit 6
Bit 5
Bit 4
BABLM
CERRM
Babble Error Mask. BABLM is
the mask for BABL. The INTR pin
will not be asserted by the MACE
device regardless of the state of
the BABL bit, if BABLM is set. It is
cleared by activation of the
RESET pin or SWRST bit.
Poll Register (PR)
(REG ADDR 10)
This register contains copies of internal status bits to
simplify a host implementation which is non-interrupt
driven. The register is read only, and its status is unaf-
fected by read operations. All register bits are cleared by
hardware or software reset. Bit assignments are as fol-
lows:
Collision Error Mask. CERRM is
the mask for CERR. The INTR
pin will not be asserted by the
MACE device regardless of the
state of the CERR bit, if CERRM
is set. It is cleared by activation of
the RESET pin or SWRST bit.
XMTSV TDTREQ RDTREQ RES
RES
RES
RES
RES
Bit
Name
Description
RCVCCOM Receive Collision Count Over-
flow Mask. RCVCCOM is the
mask for RCVCCO(Receive Col-
lision Count Overflow). The INTR
pin will not be asserted by the
MACE device regardless of the
state of the RCVCCO bit, if
RCVCCOM is set. It is cleared by
activation of the RESET pin or
SWRST bit.
Bit 7
XMTSV
Transmit Status Valid. Transmit
Status Valid indicates that the
Transmit Frame Status is valid.
Bit 6
TDTREQ
Transmit Data Transfer Request.
An internal indication of the cur-
rent request status of the Trans-
mit FIFO. TDTREQ is set when
the external TDTREQ signal is
asserted.
Am79C940
63
AMD
RDTREQ
Bit 5
Receive Data Transfer Request.
An internal indication of the
current request status of the Re-
ceive FIFO. RDTREQ is set
when the external RDTREQ sig-
nal is asserted.
Bit 3-1 RES
Bit 0 SWRST
Reserved. Read as zeroes.
Always write as zeroes.
Software Reset. When set, pro-
vides an equivalent of the hard-
ware RESET pin function. All
register bits will be set to their de-
fault values. The MACE device
will require re-initialization after
SWRST has been activated. The
MACE device will clear SWRST
during its internal reset se-
quence.
Bit 4–0 RES
Reserved. Read as zeroes.
Always write as zeroes.
BIUConfigurationControl(BIUCC) (REGADDR11)
All bits within the BIU Configuration Control register will
be set to their default state upon a hardware or software
reset. Bit assignments are as follows:
FIFO Configuration Control
(FIFOCC)
(REG ADDR 12)
RES BSWP XMTSP [1–0]
RES
RES
RES
SWRST
All bits within the FIFO Configuration Control register
will be set to their default state upon a hardware or soft-
ware reset. Bit assignments are as follows:
Bit
Name
RES
BSWP
Description
Bit 7
Bit 6
Reserved. Read as zero. Always
write as zero.
XMTFW[1–0] RCVFW [1–0] XMTFWU RCVFWU XMTBRST RCVBRST
Byte Swap. The BSWP function
allows data to and from the
FIFOs to be orientated according
to little endian or big endian byte
ordering conventions. BSWP is
cleared by by activation of the
RESET pin or SWRST bit, de-
faulting to Intel byte ordering.
Bit
Name
Description
Bit 7-6 XMTFW
[1–0]
Transmit
FIFO Watermark.
XMTFW controls the point
TDTREQ is asserted in relation
to the number of write cycles to
the Transmit FIFO. TDTREQ will
be asserted at any time that the
number of write cycles specified
by XMTFW can be executed.
XMTFW is set to a value of 00 (8
cycles) after hardware or soft-
ware reset.
Bit 5-4 XMTSP
[1–0]
Transmit Start Point. XMTSP
controls the point preamble
transmission commences in rela-
tion to the number of bytes writ-
ten to the XMTFIFO. When the
entire frame is in the XMTFIFO
(or the XMTFIFO becomes full
Transmit FIFO Watermarks
before
the
threshold
is
XMTFW [1–0]
Write Cycles
achieved), transmission of pre-
amble will start regardless of the
value in XMTSP (once the IPG
time has expired). XMTSP is
given a value of 10 (64 bytes) af-
ter hardware or software reset.
Regardless of XMTSP, the FIFO
will not internally over write its
data until at least 64 bytes, or the
entire frame, has been transmit-
ted onto the network. This en-
sures that for collisions within the
slot time window, transmit data
need not be re-written to the
XMTFIFO, and re-tries will be
handled autonomously by the
MACE device.
00
01
10
11
8
16
32
XX
The XMTFW value will only be
updated when the XMTFWU bit
is set.
To ensure that sufficient space is
present in the XMTFIFO to ac-
cept the specified number of
write cycles (including an End-
Of-Frame delimiter), TDTREQ
may go inactive before the
XMTSP threshold is reached
when using the non burst mode
(XMTBRST = 0). The host must
be aware that despite TDTREQ
going inactive, additional space
exists in the XMTFIFO, and the
data write must continue to en-
sure the XMTSP threshold is
achieved. No transmit activity will
commence until the XMTSP
Transmit Start Point
XMTSP [1–0]
Bytes
4
00
01
10
11
16
64
112
64
Am79C940
AMD
threshold is reached. When us-
ing the burst mode, TDTREQ will
not be de-asserted until only a
single write cycle can be per-
formed. See the FIFO Sub-sys-
tem section for additional details.
retry failure). The recommended
proceduretochangetheXMTFW
is to write the new value with
XMTFWU set, in a single write
cycle. The XMTFIFO should be
empty and all transmit activity
complete before attempting a
watermark update, since the
XMTFIFO will be reset to allow
the new pointer values to be
loaded. It is recommended that
the transmitter be disabled by
Bit 5-4 RCVFW
[1–0]
Receive
FIFO
Watermark.
RCVFW controls the point
RDTREQ is asserted in relation
to the number of bytes available
in the RCVFIFO. RCVFW speci-
fies the number of bytes which
must be present (once the packet
has been verified as a non-runt),
before the RDTREQ is asserted.
Note however that in order for
RDTREQ to be activated for a
new frame, at least 64-bytes
must have been received. This
effectively avoids reacting to re-
ceive frames which are runts or
suffer a collision during the slot
time (512 bit times). If the Runt
Packet Accept feature (RPA in
Receive Frame Control) is en-
abled, the RDTREQ pin will be
activated as soon as either
64-bytes are received, or a com-
plete valid receive frame is de-
tected (regardless of length).
RCVFW is set to a value of 10 (64
bytes) after hardware or software
reset.
clearing
the
ENXMT
bit.
XMTFWU will be cleared by the
MACE device after the new
XMTFW value has been loaded,
or by activation of the RESET pin
or SWRST bit.
Bit 2
RCVFWU Receive FIFO Watermark Up-
date. Allows update of the Re-
ceive FIFO Watermark bits. The
RCVFW bits can be written at
any point, and will read back as
written. However, the new value
in the RCVFW bits will be ignored
until RCVFWU is set. The recom-
mendedproceduretochangethe
RCVFW is to write the new value
with RCVFWU set, in a single
write cycle. The RCVFIFO
should be empty before attempt-
ing a watermark update, since
the RCVFIFO will be reset to al-
low the new pointer values to be
loaded. It is recommended that
the receiver be disabled by clear-
ing the ENRCV bit. RCVFWU will
be cleared by the MACE device
after the new RCVFW value has
been loaded, or by activation of
the RESET pin or SWRST bit.
Receive FIFO Watermarks
RCVFW [1–0]
Bytes
16
00
01
10
11
32
64
XX
Bit 1
XMTBRST Transmit Burst. When set, the
transmit burst mode is selected.
The behavior of the Transmit
FIFO high watermark, and hence
the de-assertion of TDTREQ, will
be modified. TDTREQ will be
deasserted if there are only two
bytes of space available in the
XMTFIFO (so that a full word
write can still occur) or if four
bytes of space exist and the EOF
pin is asserted by the host.
The RCVFW value will only be
updated when the RCVFWU bit
is set.
Bit 3
XMTFWU Transmit FIFO Watermark Up-
date. Allows update of the Trans-
mit FIFO Watermark bits. The
XMTFW can be written at any
point, and will be read back as
written. However, the new value
in the XMTFW bits will be ignored
until XMTFWU is set (or the
transmit path is reset due to a
Am79C940
65
AMD
TDTREQ will be asserted identi-
cally in both normal and burst
modes, when there is sufficient
space in the XMTFIFO to allow
the specified number of write
cycles to occur (programmed by
the XMTFW bits).
Bit 5
EMBA
Enable Modified Back-off Algo-
rithm. When set, enables the
modified backoff algorithm.
EMBA is cleared by activation of
the RESET pin or SWRST bit.
Bit 4
Bit 3
RES
Reserved. Read as zeroes. Al-
ways write as zeroes.
Cleared by activation of the
RESET pin or SWRST bit.
DRCVPA
Disable Receive Physical Ad-
dress. When set, the physical ad-
dress detection (Station or node
ID) of the MACE device will be
disabled. Packets addressed to
the nodes individual physical ad-
dress will not be recognized (al-
though the packet may be
Bit 0
RCVBRST Receive Burst. When set, the re-
ceiveburstmodeisselected. The
behavior of the Receive FIFO low
watermark, and hence the de-
assertion of RDTREQ, will be
modified. RDTREQwillde-assert
when there are only 2-bytes of
data available in the RCVFIFO
(so that a full word read can still
occur).
accepted
mechanism).
by
the
DRCVPA
EADI
is
cleared by activation of the
RESET pin or SWRST bit.
RDTREQ will be asserted identi-
cally in both normal and burst
modes, when a minimum of
64-bytes have been received for
a new frame (or a runt packet has
been received and RPA is set).
Once the 64-byte limit has been
exceeded, RDTREQ will be as-
serted providing there is suffi-
cient data in the RCVFIFO to
exceed the threshold, as pro-
grammed by the RCVFW bits.
Bit 2
DRCVBC
Disable Receive Broadcast.
When set, disables the MACE
device from responding to broad-
cast messages. Used for proto-
cols that do not support
broadcast addressing, except as
a function of multicast. DRCVBC
is cleared by activation of the RE-
SET pin or SWRST bit (broad-
cast messages will be received).
Bit 1
ENXMT
Enable
Transmit.
Setting
ENXMT = 1 enables transmis-
sion. With ENXMT = 0, no trans-
mission will occur. If ENXMT is
written as 0 during frame trans-
mission, a packet transmission
which is incomplete will have a
guaranteed CRC violation ap-
pended before the internal
Transmit FIFO is cleared. No
subsequent attempts to load the
FIFO should be made until
ENXMT is set and TDTREQ is
asserted. ENXMT is cleared by
activation of the RESET pin or
SWRST bit.
Cleared by activation of the
RESET pin or SWRST bit.
MAC Configuration
Control (MACCC)
(REG ADDR 13)
This register programs the transmit and receive opera-
tion and behavior of the internal MAC engine. All bits
within the MAC Configuration Control register are
cleared upon hardware or software reset. Bit assign-
ments are as follows:
PROM DXMT2PD EMBA RES DRCVPA DRCVBC ENXMT ENRCV
Bit
Name
Description
Bit 0
ENRCV
Enable Receive. Setting ENRCV
= 1 enables reception of frames.
With ENRCV = 0, no frames will
be received from the network into
the internal FIFO. When ENRCV
is written as 0, any receive frame
currently in progress will be com-
pleted (and valid data contained
in the RCVFIFO can be read by
the host) and the MACE device
will enter the monitoring state for
missed packets. Note that clear-
ing the ENRCV bit disables the
Bit 7
PROM
Promiscuous. When PROM is
set all incoming frames are re-
ceived regardless of the destina-
tion address. PROM is cleared
by activation of the RESET pin or
SWRST bit.
Bit 6
DXMT2PD Disable Transmit Two Part De-
ferral. When set, disables the
transmit two part deferral option.
DXMT2PD is cleared by activa-
tion of the RESET pin or SWRST
bit.
66
Am79C940
AMD
assertion of RDTREQ. If ENRCV
is cleared during receive activity
and remains cleared for a long
time and if the tail end of the re-
ceive frame currently in progress
is longer than the amount of
space available in the Receive
FIFO, Receive FIFO overflow will
occur. However, even with
RDTREQ deasserted, if there is
valid data in the Receive FIFO to
be read, successful slave reads
to the Receive FIFO can be exe-
cuted (indicated by valid DTV). It
is the host’s responsibility to
avoid the overflow situation.
ENRCV is cleared by activation
of the RESET pin or SWRST bit.
PORTSEL Interface Definition
PORTSEL
Active
[1–0]
Interface
DXCVR Pin
LOW
00
AUI
01
10BASE-T
DAI Port
GPSI
HIGH
10
HIGH
11
LOW
Bit 0
ENPLSIO Enable PLS I/O. ENPLSIO is
used to enable the optional I/O
functions from the PLS function.
The following pins are affected
by the ENPLSIO bit: RXCRS,
RXDAT,
TXDAT–,
TXEN,
CLSN,
TXDAT+,
STDCLK,
SRDCLK and SRD. Note that if
an external SIA is being utilized
via the GPSI, PORTSEL [1–0] =
11 must be programmed before
ENPLSIO is set, to avoid conten-
tion of clock, data and/or carrier
indicator signals.
PLS Configuration
Control (PLSCC)
(REG ADDR 14)
All bits within the PLS Configuration Control register are
cleared upon a hardware or software reset. Bit assign-
ments are as follows:
PHY Configuration
Control (PHYCC)
RES
RES
RES
RES
XMTSEL PORTSEL [1–0] ENPLSIO
(REG ADDR 15)
All bits within the PHY Configuration Control register
withtheexceptionofLNKFL, areclearedbyhardwareor
software reset. Bit assignments are as follows:
Bit
Name
Description
Bit 7–4 RES
Bit 3 XMTSEL
Reserved. Read as zeroes.
Always write as zeroes.
LNKFL DLNKTST REVPOL DAPC LRT
ASEL RWAKE AWAKE
Transmit Mode Select. XMTSEL
provides control over the AUI
DO+ and DO– operation while
the MACE device is not transmit-
ting. With XMTSEL = 0, DO+ and
DO will be equal during transmit
idle state, providing zero differ-
ential to operate transformer
coupled loads. The turn off and
return to zero delays are con-
trolled internally. With XMTSEL =
1, DO+ is positive with respect to
DO during the transmit idle state .
Bit
Name
Description
Bit 7
LNKFL
Link Fail. Reports the link integ-
rity of the 10BASE-T receiver.
When the link test function is en-
abled (DLNKTST = 0), the ab-
sence of link beat pulses on the
RXD± pair will cause the inte-
grated 10BASE-T transceiver to
go into the link fail state. In the
link fail state, data transmission,
data reception, data loopback
and the collision detection func-
tions are disabled, and remain
disabled until valid data or >5
consecutive link pulses appear
on the RXD± pair. During link fail,
the LNKFL bit will be set and the
LNKST pin should be externally
pulled HIGH. When the link is
identified as functional, the
LNKFL bit will be cleared and the
LNKST pin is driven LOW, which
is capable of directly driving a
Link OK LED. In order to inter-
operate with systems which do
Bit 2–1 PORTSEL Port Select. PORTSEL is used to
[1–0] select between the AUI,
10BASE-T, DAI or GPSI ports of
the MACE device. PORTSEL is
cleared by hardware or software
reset. PORTSEL will determine
which of the interfaces is used
during normal operation, or
tested when utilizing the loop-
back options (LOOP [1–0]) in the
User Test Register. Note that the
PORTSEL [1–0] programming
will be overridden if the ASEL bit
in the PHY Configuration Control
register is set.
Am79C940
67
AMD
not implement Link Test, this
function can be disabled by set-
ting the DLNKTST bit. With Link
Test disabled (DLNKTST = 1),
the data driver, receiver and
loopback functions as well as col-
lision detection remain enabled
irrespective of the presence or
absence of data or link pulses on
the RXD± pair. The transmitter
will continue to generate link beat
pulses during periods of transmit
data inactivity. Set by hardware
or software reset.
continue to operate even during
SLEEP. Incoming packet activity
will be passed to the EADI port
pins permitting detection of spe-
cific frame contents used to
initiate a wake-up sequence.
RWAKE must be programmed
prior to SLEEP being asserted
for this function to operate.
RWAKE is not cleared by
SLEEP, only by activation of the
SWRST bit or RESET pin.
Bit 0
AWAKE
Auto Wake. When set prior to the
SLEEP pin being activated, the
10BASE-T receiver section will
continue to operate even during
SLEEP, and will activate the
LNKST pin if Link Pass is de-
tected. AWAKE must be pro-
grammed prior to SLEEP being
asserted for this function to oper-
ate. AWAKE is not cleared by
SLEEP, only by activation of the
SWRST bit or RESET pin.
Bit 6
Bit 5
DLNKTST Disable Link Test. When set, the
integrated 10BASE-T trans-
ceiver will be forced into the link
pass state, regardless of receive
link test pulses or receive packet
activity.
REVPOL
Reversed Polarity. Indicates the
receive polarity of the RD± pair.
When normal polarity is de-
tected, the REVPOL bit will be
cleared, and the RXPOL pin (ca-
pable of driving a Polarity OK
LED) will be driven LOW. When
reverse polarity is detected, the
REVPOL bit will be set, and the
RXPOL pin should be externally
pulled HIGH.
Chip Identification Register
(CHIPID [15–00])
(REG ADDR 16 &17)
This 16-bit value corresponds to the specific version of
the MACE device being used. The value will be pro-
grammed to X940h, where X is a value dependent on
version.
Bit 4
DAPC
Disable Auto Polarity Correction.
When set, the automatic polarity
correction will be disabled. Polar-
ity detection and indication will
still be possible via the RXPOL
pin.
CHIPID [07–00]
CHIPID [15–08]
Internal Address
Configuration (IAC)
(REG ADDR 18)
Bit 3
Bit 2
LRT
Low Receive Threshold. When
set, the threshold of the twisted
pair receiver will be reduced by
4.5 dB, to allow extended dis-
tance operation.
This register allows access to and from the multi-byte
Physical Address and Logical Address Filter locations,
using only a single byte location.
The MACE device will reset the IAC register PHYADDR
and LOGADDR bits after the appropriate number of
read or write cycles have been executed on the Physical
Address Register or the Logical Address Filter. Once
the LOGADDR bit is set, the MACE device will reset the
bitafter8readorwriteoperationshavebeenperformed.
Once the PHYADDR bit is set, the MACE device will re-
setthebitafter6readorwriteoperationshavebeenper-
formed. The MACE device makes no distinction
between read or write operations, advancing the inter-
nal address RAM pointer with each access. If both
PHYADDR and LOGADDR bits are set, the MACE de-
vice will accept only the LOGADDR bit. If the PHYADDR
bit is set and the Logical Address Filter location is ac-
cessed, a DTV will not be returned. Similarly, if the
LOGADDR bit is set and the Physical Address Register
location is accessed, DTV will not be returned.
PHYADDR or LOGADDR can be set in the same cycle
as ADDRCHG.
ASEL
Auto Select. When set, the
PORTSEL [1–0] bits are overrid-
den, and the MACE device will
automatically select the operat-
ing media interface port. When
the 10BASE-T transceiver is in
the link pass state (due to receiv-
ing valid packet data and/or Link
Test pulses or the DLNKTST bit
is set), the 10BASE-T port will be
used. When the 10BASE-T port
is in the link fail state, the AUI port
will be used. Switching between
the ports will not occur during
transmission in order to avoid
any type of fragment generation.
Bit 1
RWAKE
Remote Wake. When set prior to
the SLEEP pin being activated,
the AUI and 10BASE-T receiver
sections and the EADI port will
68
Am79C940
AMD
Logical Address Filter
(LADRF [63–00])
ADDRCHG RES RES RES RES PHYADDR LOGADDR RES
(REG ADDR 20)
Bit
Name
Description
LADRF [63–00]
This 64-bit mask is used to accept incoming Logical Ad-
dresses. The Logical Address Filter is expected to be
programmed at initialization (after hardware or software
reset). After a hardware or software reset and before the
ENRCV bit in the MAC Configuration Control register
has been set, the Logical Address can be accessed by
setting the LOG ADDR bit in the Internal Address Con-
figuration register (REG ADDR 18) and then by perform-
ing 8 reads or writes to the Logical Address Filter. Once
ENRCV has been set, the ADDR CHG bit in the Internal
Address Configuration register must be set and be
polled until it is cleared by the MACE device before set-
ting the LOGADDR bit and before accessing of the Logi-
cal Address Filter is allowed.
Bit 7
ADDRCHG Address Change. When set, al-
lows the physical and/or logical
address to be read or pro-
grammed. When ADDRCHG is
set, ENRCV will be cleared, the
MPC will be stopped, and the last
or current in progress receive
frame will be received as normal.
After the frame completes, ac-
cess to the internal address RAM
will be permitted, indicated by the
MACE device clearing the
ADDRCHG bit. Please refer to
the register description of the
ENRCV bit in the MAC Configu-
ration Control register (REG
ADDR 13) for the effect of clear-
ing the ENRCV bit. Normal re-
ception can be resumed once the
physical/logical address has
been changed, by setting
ENRCV.
If the least significant address bit of a received message
is set (Destination Address bit 00 = 1), then the address
is deemed logical, and passed through the FCS genera-
tor. After processing the 48-bit destination address, a
32-bit resultant FCS is produced and strobed into an in-
ternal register. The high order 6-bits of this resultant
FCS are used to select one of the 64-bit positions in the
Logical Address Filter (see diagram). If the selected fil-
ter bit is a 1, the address is accepted and the packet will
be placed in memory.
Bit 6–3 RES
Reserved. Read as zeroes.
Always write as zeroes.
Bit 2
Bit 1
Bit 0
PHYADDR Physical Address Reset. When
set, successive reads or writes to
the Physical Address Register
will occur in the order PADR
[07–00], PADR [15–08],....,
PADR [47–40]. Each read or
write operation on the PADR lo-
cation will auto-increment the in-
ternal pointer to access the next
most significant byte.
The first bit of the incoming address must be a 1 for a
logical address. If the first bit is a 0, it is a physical ad-
dress and is compared against the value stored in the
Physical Address Register at initialization.
The Logical Address Filter is used in multicast address-
ing schemes. The acceptance of the incoming frame
based on the filter value indicates that the message may
be intended for the node. It is the user’s responsibility to
determine if the message is actually intended for the
nodebycomparingthedestinationaddressofthestored
message with a list of acceptable logical addresses.
LOGADDR Logical Address Reset. When
set, successive reads or writes to
the Logical Address Filter will oc-
cur in the order LADRF [07–00],
LADRF
[15–08],....,LADRF
[63–56]. Each read or write op-
eration on the LADRF location
will auto-increment the internal
pointer to access the next most
significant byte.
The Broadcast address, which is all ones, does not go
through the Logical Address Filter and is always en-
abled providing that the Disable Receive Broadcast bit
(DRCVBC in the MAC Configuration Control register) is
cleared. If the Logical Address Filter is loaded with all
zeroes (and PROM = 0), all incoming logical addresses
except broadcast will be rejected.
RES
Reserved. Read as zero. Always
write as zero.
Multicast addressing can only be performed when using
external loopback (LOOP [1–0] = 0) by programming
RCVFCSE = 1 in the User Test Register. The FCS logic
is internally allocated to the receiver section, allowing
the FCS to be computed on the incoming logical
address.
Am79C940
69
AMD
32-Bit Resultant CRC
26
Received Message
Destination Address
31
0
47
1
0
1
CRC
GEN
Logical
Address
Filter
(LADRF)
63
0
SEL
64
MATCH*
MUX
6
MATCH = 1:
MATCH = 0:
Packet Accepted
Packet Rejected
16235C-10
Logical Address Match Logic
70
Am79C940
AMD
Physical Address
(PADR [47–00])
Interrupt Mask Register is clear. MPCOM will be cleared
(the interrupt will be unmasked) after a hardware or soft-
ware reset.
(REG ADDR 21)
PADR [47–00]
Note that the following conditions apply to the MPC:
This 48-bit value represents the unique node value as-
signed by the IEEE and used for internal address com-
parison. After a hardware or software reset and before
the ENRCV bit in the MAC Configuration Control regis-
ter has been set, the Physical Address can be accessed
by setting the PHYADDR bit in the Internal Address
Configuration register (REG ADDR 18) and then by per-
forming 6 reads or writes to the Physical Address. Once
ENRCV has been set, the ADDRCHG bit in the Internal
Address Configuration register must be set and be
polled until it is cleared by the MACE device before set-
ting the PHYADDR bit and before accessing of the
Physical Address is allowed. The first bit of the incoming
address must be a 0 for a physical address. The incom-
ing address is compared against the value stored in the
Physical Address register at initialization provided that
the DRCVPA bit in the MAC Configuration Control regis-
ter is cleared.
■ After hardware or software reset, the MPC will not
increment until the first time the receiver is enabled
(ENRCV = 1). Once the receiver has been enabled,
the MPC will count all missed packet events, re-
gardless of the programming of ENRCV.
■ The packet must pass the internal address match to
be counted. Any of the following address match
conditions will increment MPC while the receiver is
deaf:
Physical Address match;
Logical Address match;
Broadcast reception;
Any receive in promiscuous mode (PROM = 1 in the
MAC Configuration Control register);
EADI feature match mode and EAM is asserted;
EADI feature reject mode and EAR is not asserted.
■ Any packet which suffers a collision within the slot
Missed Packet Count (MPC)
(REG ADDR 24)
time will not be counted.
MPC [7–0]
■ Runt packets will not be counted unless RPA in the
The Missed Packet Count (MPC) is a read only 8-bit
counter. The MPC is incremented when the receiver is
unable to respond to a packet which would have nor-
mally been passed to the host. The MPC will be reset to
zero when read. The MACE device will be deaf to re-
ceive traffic due to any of the following conditions :
User Test Register is enabled.
■ Packets which pass the address match criteria but
experience FCS or Framing errors will be counted,
since they are normally passed to the host.
Runt Packet Count (RNTPC)
(REG ADDR 26)
■ The host disabled the receive function by clearing
the ENRCV bit in the MAC Configuration Control
register.
RNTPC [7–0]
The Runt Packet Count (RNTPC) is a read only 8-bit
counter, incremented when the receiver detects a runt
packet that is addressed to this node. Runt packets are
defined as received frames which passed the internal
address match criteria but did not contain a minimum of
64-bytes of data after SFD. Note that the RNTPC value
returned in the Receive Frame Status (RFS2) will freeze
at a value of 255, whereas this register based version of
RNTPC is free running. The value will roll over after 255
runt packets have been detected, setting the RNTPCO
bit (in the Interrupt Register and asserting the INTRpin if
the corresponding mask bit (RNTPCOM in the Interrupt
Mask Register) is cleared. RNTPC will be reset to zero
when read.
■ A Receive FIFO overflow condition exists, and must
beclearedbyreadingtheReceiveFIFOandtheRe-
ceive Frame Status.
■ The Receive Frame Count (RCVFC) in the FIFO
Frame Count register exceeds its maximum value,
indicating that greater than 15 frames are in the Re-
ceive FIFO.
If the number of received frames that have been missed
exceeds 255, the MPC will roll over and continue count-
ing from zero, the MPCO (Missed Packet Count Over-
flow) bit in the Interrupt Register will be set (at the value
255), and the INTR pin will be asserted providing that
MPCOM (Missed Packet Count Overflow Mask) in the
71
Am79C940
AMD
Receive Collision Count (RCVCC) (REG ADDR 27)
Bit 4
FCOLL
Force Collision. Allows the colli-
sion logic to be tested. The
MACE device should be in an in-
ternal loopback test for the
FCOLL test. When FCOLL = 1, a
collision will be forced during the
next transmission attempt. This
will result in 16 total transmission
attempts (if DRTRY = 0) with the
Retry Error reported in the Trans-
mit Frame Status register.
FCOLL is cleared by the activa-
tion of the RESET pin or SWRST
bit.
RCVCC [7–0]
The Receive Collision Count (RCVCC) is a read only
8-bit counter, incremented when the receiver detects a
collision on the network. Note that the RCVCC value re-
turnedintheReceiveFrameStatus(RFS3)willfreezeat
a value of 255, whereas this register based version of
RCVCC is free running. The value will roll over after 255
receive collisions have been detected, setting the
RCVCCO bit (in the Interrupt Register and asserting the
INTR pin if the corresponding mask bit (RCVCCOM in
the Interrupt Mask Register ) is cleared. RCVCC will be
reset to zero when read.
Bit3
RCVFCSE Receive FCS Enable. Allows the
hardware associated with the
FCS generation to be allocated
to the transmitter or receiver dur-
ing loopback diagnostics. When
clear, the FCS will be generated
and appended to the transmit
User Test Register (UTR)
(REG ADDR 29)
The User Test Register is used to put the chip into test
configurations. All bits within the Test Register are
cleared upon a hardware or software reset. Bit assign-
ments are as follows:
message
(providing
that
DXMTFCS in the Transmit
Frame Control is clear), and re-
ceived after the loopback proc-
ess through the Receive FIFO.
When set, the hardware associ-
ated with the FCS generation is
allocated to the receiver. A trans-
mit packet will be assumed to
contain the FCS in the last four
bytes of the frame passed
through the Transmit FIFO. The
received frame will have the FCS
calculated on the data field and
compared with the last four bytes
contained in the received mes-
sage. An FCS error will be
flagged in the Received Status
(RFS1) if the received and calcu-
lated values do not match.
RCVFCSE is only valid when in
any one of the loopback modes
as defined by LOOP [0–1]. Note
that if the receive frame is ex-
pected to be recognized on the
basis of a multicast address
match, the FCS logic must be al-
RTRE
RTRD
RPA
FCOLL RCVFCSE LOOP [1–0] RES
Bit
Name
Description
Bit 7
RTRE
Reserved Test Register Enable.
Access to the Reserved Test
Registers should not be at-
tempted by the user. Note that
access to the Reserved Test
Register may cause damage to
the MACE device if configured
in a system board application.
Access to the Reserved Test
Register is prevented, regard-
less of the state of RTRE, once
RTRD has been set. RTRE is
cleared by activation of the RE-
SET pin or SWRST bit.
Bit 6
RTRD
Reserved Test Register Disable.
When set, access to the Re-
served Test Registers is inhib-
ited, and further writes to the
RTRD bit are ignored. Access to
the Reserved Test Register is
prevented, regardless of the
state of RTRE, once RTRD has
been set. RTRD can only be
cleared by hardware or software
reset.
located
to
the
receiver
(RCVFCSE = 1). RCVFCSE is
cleared by activation of the
RESET pin or SWRST bit.
Bit 5
RPA
Runt Packet Accept. Allows re-
ceivepacketswhicharelessthan
the legal minimum as specified
by IEEE 802.3/Ethernet, to be
passed to the host interface via
the Receive FIFO. The receive
packets must be at least 8 bytes
(after SFD) in length to be
accepted. RPA is cleared by acti-
vation of the RESET pin or
SWRST bit.
Bit 2–1 LOOP [1–0] Loopback Control. The loopback
functions allow the MACE device
to receive its own transmitted
frames. Three levels of loopback
are provided as shown in the fol-
lowing table. During loopback
operation a multicast address
can only be recognized if
RCVFCSE = 1. LOOP [0–1] are
cleared by activation of the
RESET pin or SWRST bit.
72
Am79C940
AMD
Loopback Functions
Function
Configuration Control register.
Using the internal loopback test
will ensure that transmission
does not disturb the physical me-
dium and will prohibit frame re-
ception from the network. One
Internal loopback function in-
cludes the MENDEC in the loop.
Loop [1–0]
00
01
10
No Loopback
External Loopback
Internal Loopback, excludes
MENDEC
11
Internal Loopback, includes
MENDEC
Bit 0
RES
Reserved. Read as zero. Always
write as zero.
Reserved Test Register 1 (RTR1) (REG ADDR 30)
External loopback allow the
MACE device to transmit to the
physical medium, using either
the AUI, 10BASE-T, DAI or GPSI
Reserved for AMD internal use only.
Reserved Test Register 2 (RTR2) (REG ADDR 31)
port,
dependent
on
the
Reserved for AMD internal use only.
PORTSEL [1–0] bits in the PLS
Am79C940
73
AMD
Register Table Summary
Address
0
Mnemonic
Contents
Receive FIFO [15–00]
Comments
Read only
RCVFIFO
XMTFIFO
XMTFC
XMTFS
XMTRC
RCVFC
RCVFS
FIFOFC
IR
1
Transmit FIFO [15–00]
Transmit Frame Control
Transmit Frame Status
Transmit Retry Count
Receive Frame Control
Receive Frame Status (4-bytes)
FIFO Frame Count
Write only
2
Read/Write
Read only
3
4
Read only
5
Read/Write
Read only
6
7
Read only
8
Interrupt Register
Read only
9
IMR
Interrupt Mask Register
Poll Register
Read/Write
Read only
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
PR
BIUCC
FIFOCC
MACCC
PLSCC
PHYCC
CHIPID
CHIPID
IAC
BIU Configuration Control
FIFO Configuration Control
MAC Configuration Control
PLS Configuration Control
PHY Configuration Control
Chip Identification Register [07–00]
Chip Identification Register [15–08]
Internal Address Configuration
Reserved
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read only
Read only
Read/Write
Read/Write as 0
Read/Write
Read/Write
Read/Write as 0
Read/Write as 0
Read only
LADRF
PADR
Logical Address Filter (8-bytes)
Physical Address (6-bytes)
Reserved
Reserved
MPC
Missed Packet Count
Reserved
Read/Write as 0
Read only
RNTPC
RCVCC
Runt Packet Count
Receive Collision Count
Reserved
Read only
Read/Write as 0
Read/Write
Read/Write as 0
Read/Write as 0
UTR
RTR1
RTR2
User Test Register
Reserved Test Register 1
Reserved Test Register 2
74
Am79C940
AMD
Register Bit Summary
16-Bit Registers
0
1
RCVFIFO [15–0]
XMTFIFO [15–0]
8-Bit Registers
Address
Mnemonic
2
DRTRY
XMTSV
EXDEF
RES
RES
UFLO
RES
RES
LCOL
RES
RES
MORE
RES
DXMTFCS
ONE
RES
RES
APADXMT
RTRY
3
DEFER
LCAR
4
XMTRC [3–0]
5
RES
RES
RES
LLRCV
M/R
RES
ASTRPRCV
6
RCVFS [31–00]
RCVFC [3–0]
XMTFC [3–0]
7
8
JAB
JABM
XMTSV
RES
BABL
BABLM
TDTREQ
BSWP
CERR
CERRM
RDTREQ
RCVCCO
RCVCCOM
RES
RNTPCO
RNTPCOM
RES
MPCO
MPCOM
RES
RCVINT
RCVINTM
RES
XMTINT
XMTINTM
RES
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
XMTSP [1–0]
RCVFW [1–0]
RES
RES
RES
SWRST
RCVBRST
ENRCV
ENPLSIO
AWAKE
XMTFW [1–0]
XMTFWU
DRCVPA
XMTSEL
LRT
RCVFWU
DRCVBC
XMTBRST
ENXMT
PROM
RES
DXMT2PD
RES
EMBA
RES
RES
RES
PORTSEL [1–0]
LNKFL
DLNKTST
REVPOL
DAPC
ASEL
RWAKE
CHIPID [07–00]
CHIPID [15–08]
RES RES
ADDRCHG
RES
RES
PHYADDR
LOGADDR
RES
RESERVED
LADRF [63–00]
PADR [47–00]
RESERVED
RESERVED
MPC [7–0]
RESERVED
RNTPC [7–0]
RCVCC [7–0]
RESERVED
RTRE
RTRD
RPA
FCOLL
RCVFCSE
LOOP [1–0]
RES
RESERVED
RESERVED
Receive Frame Status
Address
Mnemonic
RCVCNT [7:0]
FCS
RFS0
RFS1
RFS2
RFS3
OFLO
CLSN
FRAM
RCVCNT [10:8]
RNTPC [7–0]
RCVCC [7–0]
Am79C940
75
AMD
Programmer’s Register Model
Addr
Mnemonic
RCVFIFO
XMTFIFO
XMTFC
Contents
R/W
RO
0
1
2
Receive FIFO—16 bits
Transmit FIFO—16 bits
Transmit Frame Control
WO
80
08
01
DRTRY
Disable Retry
R/W
RO
DXMTFCS
APADXMT
Disable Transmit FCS
Auto Pad Transmit
3
XMTFS
Transmit Frame Status
80
40
20
10
08
04
02
01
80
40
20
10
0F
XMTSV
UFLO
LCOL
MORE
ONE
Transmit Status Valid
Underflow
Late Collision
MORE than one retry was needed
Exactly ONE retry occurred
Transmission was deferred
Loss of Carrier
DEFER
LCAR
RTRY
EXDEF
—
Transmit aborted after 16 attempts
Excessive Defer
4
XMTRC
RO
—
—
XMTRC [3:0] 4-bit Transmit Retry Count
5
6
RCVFC
RCVFS
Receive Frame Control
08
04
01
LLRCV
Low Latency Receive
R/W
RO
M/R
Match/Reject for external address detection
ASTRPRCV Auto Strip Receive—Strips pad and FCS from received frames
Receive Frame Status—4 bytes—read in 4 read cycles
RFS0 RCVCNT [7:0] Receive Message Byte Count
RFS1 RCVSTS, RCVCNT [11:8]—Receive Status & Receive Msg Byte Count MSBs
80
40
20
10
0F
OFLO
CLSN
FRAM
FCS
Receive FIFO Overflow
Collision during reception
Framing Error
FCS (CRC) error
RCVCNT [11:8] 4 MSBs of Receive Msg. Byte Count
RFS2 RNTPC [7:0] Runt Packet Count (since last successful reception)
RFS3 RCVCC [7:0] Receive Collision Count (since last successful reception)
FIFO Frame Count
7
8
FIFOFC
IR
RO
F0
0F
RCVFC
XMTFC
Receive Frame Count—# of RCV frames in FIFO
Transmit Frame Count—# of XMT frames in FIFO
RO
RO
Interrupt Register
80
40
20
10
08
04
02
01
JAB
Jabber Error—Excessive transmit duration (20–150ms)
Babble Error→1518 bytes transmitted
BABL
CERR
Collision Error—No SQE Test Message
RCVCCO
RNTPCO
MPCO
RCVINT
XMTINT
Receive Collision Count Overflow—Reg Addr 27 overflow
Runt Packet Count Overflow—Reg Addr 26 overflow
Missed Packet Count Overflow—Reg Addr 24 overflow
Receive Interrupt—Host has read last byte of packet
Transmit Interrupt—Transmission is complete
76
Am79C940
AMD
Programmer’s Register Model (continued)
Addr
Mnemonic
Contents
R/W
9
IMR
Interrupt Mask Register
80
40
20
10
08
04
02
01
JABM
Jabber Error Mask
BABLM
Babble Error Mask
CERRM
Collision Error Mask
R/W
RCVCCOM
RNTPCOM
MPCOM
RCVINTM
XMTINTM
Receive Collision Count Overflow Mask
Runt Packet Count Overflow Mask
Missed Packet Count Overflow Mask
Receive Interrupt Mask
Transmit Interrupt Mask
10
11
PR
Poll Register
80
40
20
XMTSV
Transmit Status Valid
RO
TDTREQ
RDTREQ
Transmit Data Transfer Request
Receive Data Transfer Request
BIUCC
Bus Interface Unit Configuration Control
80
40
30
—
BSWP
Byte Swap
XMTSP—Transmit Start Point (2 bits)
00
Transmit after 4 bytes have been loaded
R/W
R/W
R/W
01
Transmit after 16 bytes have been loaded
Transmit after 64 bytes have been loaded
Transmit after 112 bytes have been loaded
Software Reset
10
11
01
SWRST
12
FIFOCC
FIFO Configuration Control
C0
XMTFW
00
Transmit FIFO Watermark (2 bits)
Assert TDTREQ after 8 write cycles can be made
Assert TDTREQ after 16 write cycles can be made
Assert TDTREQ after 32 write cycles can be made
XX
01
10
11
30
RCVFW
00
Receive FIFO Watermark (2 bits)
Assert RDTREQ after 16 bytes are present
Assert RDTREQ after 32 bytes are present
Assert RDTREQ after 64 bytes are present
XX
01
10
11
08
04
02
01
XMTFWU
RCVFWU
XMTBRST
RCVBRST
Transmit FIFO Watermark Update—loads XMTFW bits
Receive FIFO Watermark Update—loads RCVFW bits
Select Transmit Burst mode
Select Receive Burst mode
13
MACCC
Media Access Control (MAC) Configuration Control
80
40
20
10
08
04
02
01
PROM
Promiscuous mode
DXMT2PD
EMBA
Disable Transmit Two Part Deferral
Enable Modified Back-off Algorithm
—
DRCVPA
DRCVBC
ENXMT
ENRCV
Disable Receive Physical Address
Disable Receive Broadcast
Enable Transmit
Enable Receive
Am79C940
77
AMD
Programmer’s Register Model (continued)
Addr
Mnemonic
Contents
R/W
14
PLSCC
Physical Layer Signalling (PLS) Configuration Control
08
06
XMTSEL Transmit Mode Select: 1→DO± = 1 during IDLE
PORTSEL [1:0]—Port Select (2 bits)
00
01
10
11
AUI selected
R/W
R/W
10BASE-T selected
DAI port selected
GPSI selected
01
ENPLSIO Enable Status
15
PHYCC
Physical Layer (PHY) Configuration Control
80
40
20
10
08
04
02
01
LNKFL
Link Fail—Reports 10BASE-T receive inactivity
DLNKTST Disable Link Test—Force 10BASE-T port into Link Pass
REVPOL Reversed Polarity—Reports 10BASE-T receiver wiring error
DAPC
LRT
Disable Auto Polarity Correction—Detection remains active
Low Receive Threshold—Extended distance capability
ASEL
Auto Select—Select 10BASE-T port when active, otherwise AUI
Remote Wake—10BASE-T, AUI and EADI features active during sleep
Auto Wake—10BASE-T receive and LNKST active during sleep
RWAKE
AWAKE
16
17
18
CHIPID
CHIPID
IAC
Chip Identification Register LSB—CHIPID [7:0]
Chip Identification Register MSB—CHIPID [15:8]
Internal Address Configuration
RO
RO
80
ADDRCHGAddress Change—Write to PHYADDR or LOGADDR after ENRCV
40
20
10
08
04
04
—
—
—
—
R/W
—
PHYADDR Reset Physical Address pointer
02
LOGADDR Reset Logical Address pointer
01
—
19
—
Reserved
R/W
as 0
20
21
22
LADRF
PADR
—
Logical Address Filter—8 bytes—8 reads or writes—LS Byte first
Physical 6 bytes—6 reads or writes—LS Byte first
Reserved
R/W
R/W
R/W
as 0
23
—
Reserved
R/W
as 0
24
25
MPC
—
Missed Packet Counter—Number of receive packets missed
Reserved
RO
R/W
as 0
26
27
28
RNTPC
RCVCC
—
Runt Packet Count—Number of runt packets addressed to this node
Receive Collision Count—Number of receive collision frames on network
Reserved
RO
RO
R/W
as 0
29
UTR
User Test Register
R/W
80
40
20
10
08
06
RTRE
RTRD
RPA
Reserved Test Register Enable—must be 0
Reserved Test Register Disable
Runt Packet Accept
FCOLL
Force Collision
RCVFCSE Receive FCS Enable
LOOP
00
Loopback control (2 bits)
No loopback
01
External loopback
10
Internal loopback, excludes MENDEC
Internal loopback, includes MENDEC
—
11
01
R/W
78
Am79C940
AMD
Programmer’s Register Model (continued)
Addr
Mnemonic
Contents
R/W
30
—
Reserved
Reserved
R/W
as 0
31
—
R/W
as 0
The 8237 and the MACE device run synchronous to the
same SCLK. The 8237 is programmed to execute a
transfer in three clock cycles This requires an extra wait
state in the MACE device during FIFO accesses. A sys-
tem not using the same configuration as in the IBM PC
can minimize the bus bandwidth required by the MACE
device by programming the DMA controller in the com-
pressed timing mode.
SYSTEM APPLICATIONS
Host System Examples
Motherboard DMA Controller
The block diagram shows the MACE device interfacing
to a 8237 type DMA controller. Two external latches are
used to provide a 24 bit address capability. The first
latchstorestheaddressbitsA[15:8], whichthe8237will
output on the data line DB [7:0], while the signal ADSTB
is active. The second latch is used as a page register. It
extends the addressing capability of the 8237 from
16-bit to 24-bit. This latch must be programmed by the
system using an I/0 command to generate the signal
LATCHHIGHADR.
Care must be taken with respect to the number of trans-
fers within a burst. The 8237 will drive the signal EOP
low every time the internal counter reaches the zero.
The MACE device however only expects EOF asserted
on the last byte/word of a packet. This means, that the
word counter of the 8237 should be initially loaded with
thenumberofbytes/wordsinthewholepacket. Iftheap-
plication requires that the packet will be constructed
from several buffers at transmit time, some extra logic is
required to suppress the assertion of EOF at the end of
all but the last buffer transferred by the DMA controller.
Also note that the DMA controller can only handle either
bytes or words at any time. It requires special handling if
a packet is transferred to the MACE device Transmit
FIFO in word quantities and it ends in an odd byte.
The MACE device uses two of the four DMA channels.
One is dedicated to fill the Transmit FIFO and the other
to empty the Receive FIFO. Both DMA channels should
be programmed in the following mode:
Command Register:
Memory to memory disabled
DREQ sense active high
DACK sense active low
Normal timing
The 8237 requires an extra clock cycle to update the ex-
ternal address latch every 256 transfer cycles. This ex-
ample assumes that an update of the external address
latch occurs only at the beginning of the block transfer.
Late Write
Note:
This is the same configuration as used in the IBM PC.
Am79C940
79
AMD
VDD
CLK
SCLK
DREQ0
DREQ1
EOP
SCLK
RDTREQ
TDTREQ
EOF
FDS
DACK0
DACK1
8237
Am79C940
R/W
ADSTB
DB[7:0]
A[7:0]
CS
TC
DBUS[15:0]
ADD[4:0]
IOW
CSMACE
D[7:0]
Q[7:0]
’373
C
CC
D[7:0]
Q[7:0]
’373
C
CC
LATCHHIGHADR
D[15:0]
A[23:0]
16235C-11
System Interface – Motherboard DMA Example
80
Am79C940
AMD
PC/AT Ethernet Adapter Card
SA19–SA0
Remote
Boot
PROM
IEEE
Address
PROM
AUI
DB15
RJ45
I
S
A
SD7–SD0
D7–D0
Am79C940
B
U
S
TP
SD15–SD8
D15–D8
GPSI/DAI
Header
CAM
16235C-12
System Interface – Simple PC/AT Ethernet Adapter Card Example
Am79C940
81
AMD
The address matching, and the support logic necessary
to capture and present the relevant data to the external
table of address is application specific. Note that since
the entire 802.3 packet after SFD is made available, rec-
ognition is not limited to the destination address and/or
type fields (Ethernet only). Inter-networking protocol
recognition can be performed on specific header or LLC
information fields.
NETWORK INTERFACES
External Address Detection Interface
(EADI)
The External Address Detection Interface can be used
to implement alternative address recognition schemes
outside the MACE device, to complement the physical,
logical and promiscuous detection supported internally.
CAM
Programming
Interface
EADI
Pins
74LS595
74LS245
SRD
SER
A8–A1
Databus
SRDCLK
SRCK
RCK
SF/BD
EAM/R
Q
H’
B8–B1
QH–A
74LS595
74LS245
SER
A8–A1
Databus
SRCK
RCK
Q
H’
B8–B1
QH–A
Logic
Block
D15–D0
MTCH
Am99C10
EADI Feature – Simple External CAM Interface
16235C-13
82
Am79C940
AMD
When used with the Am79C98 TPEX (Twisted Pair
Ethernet Transceiver), the isolation requirements of the
AUI are completely removed providing that the trans-
ceiver is mounted locally. For remote location of the
TPEX via an AUI drop cable, the isolation requirementis
necessary to meet IEEE 802.3 specifications for fault
tolerance and recovery.
Attachment Unit Interface (AUI)
The AUI can drive up to 50 m of standard drop cable to
allow the transceiver to be remotely located, as is typi-
cally the case in IEEE 803.3 10BASE5 or thick Ether-
net installations. For a locally mounted transceiver,
such as 802.3 10BASE2 or Cheapernet interface, the
isolation transformer requirements between the trans-
ceiver and the MACE device can be reduced.
Ethernet
Coax
MAU
AUI
DTE
Cable
10BASE5/Ethernet
Am7996
Tap
Transceiver
CPU
Memory
Am79C940
Power
Supply
Local Bus
16235C-14
AUI-10BASE5/Ethernet Example
10BASE2/Cheapernet
Am7996
Transceiver
System
CPU
Local
Memory
RG58
BNC “T”
Am79C940
Cheapernet
Coax
Power
Supply
DMA
Engine
I/O Bus
16235C-15
AUI-10BASE2/Cheapernet Example
Am79C940
83
AMD
10BASE-T/Twisted-Pair Ethernet
RJ45
Other Slave
I/O Device(s)
i.e. SCSI
System
CPU
Am79C940
Unshielded
Twisted-Pair
I/O
Processor
Slave Peripheral Bus
16235C-16
AUI-10BASE-T/Unshielded Twisted-Pair Interface
84
Am79C940
AMD
ANLG +5 V
0.1 µF
0.1 µF
Filter &
Transformer
Module
ANLG GND
AVDD
AVSS
RJ45
Connector
61.9 Ω
422 Ω
61.9 Ω
422 Ω
TXD+
TXP+
TXD–
TXP–
RXD+
RXD–
1:1
TD+
TD–
1
2
XMT
Filter
1.21KΩ
Note 2
Note 1
1:1
RD+
RD–
3
6
RCV
Filter
100Ω
DGTL +5 V
LINK OK
LNKST
RXPOL
RX POL OK
Am79C940
Active Low
Active High
Note 4
DXCVR
Optional
Disable
10BASE2 DC/DC
Convertor
Pulse
Transformer
10BASE2 MAU
DO+
DO–
DI+
DI–
Note 3
Am7996
COAX
TAP
(BNC)
CI+
CI–
See Am7996 Data Sheet
for component and
implementation details
40.2Ω
40.2 Ω
40.2 Ω
40.2 Ω
0.1 µF
Optional
0.1 µF
16235C-17
ANLG GND
Notes:
1. Compatible filter modules, with a brief description of package type and features are included in the following section.
2. The resistor values are recommended for general purpose use and should allow compliance to the 10BASE-T specification for template fit and
jitter performance. However, the overall performance of the transmitter is also affected by the transmit filter configuration. All resistors are
± 1%.
3. Compatible AUI transformer modules, with a brief description of package type and features are included in the following section.
4. Active High indicates the external convertor should be turned off. The Disable Transceiver (DXCVR) output is used to indicate the active
network port. A high level indicates the 10BASE-T port is selected and the AUI port is disabled. A low level indicates the AUI port is selected
and the Twisted Pair interface is disabled.
Active Low: indicates the external converter should be turned off. The LNKST output can be used to indicate the active network
port. A high level indicates the 10BASE-T port is in the Link Fail state, and the external convertor should be on. A low level indicates the
10BASE-T port is in the Link Pass state, and the external convertor should be off.
10BASE-T and 10BASE2 Configuration of Am79C940
Am79C940
85
AMD
ANLG +5 V
0.1µF
0.1µF
Filter &
Transformer
Module
ANLG GND
AVDD
AVSS
RJ45
Connector
61.9Ω
422Ω
61.9Ω
422Ω
TXD+
TXP+
TXD–
TXP–
RXD+
RXD–
1:1
TD+
TD–
1
2
XMT
Filter
1.21KΩ
Note 2
Note 1
1:1
RD+
RD–
3
6
RCV
Filter
100Ω
DGTL +5 V
LINK OK
LNKST
RXPOL
RX POL OK
Am79C940
DGTL GND
Pulse
AUI
Connector
Transformer
DO+
DO–
DI+
DI–
3
10
5
Note 3
12
2
CI+
CI–
9
40.2Ω
40.2Ω
40.2Ω
40.2Ω
0.1µF
Optional
0.1µF
ANLG GND
16235C-18
Notes:
1. Compatible filter modules, with a brief description of package type and features are included in the following section.
2. The resistor values are recommended for general purpose use and should allow compliance to the 10BASE-T specification
for template fit and jitter performance. However, the overall performance of the transmitter is also affected by the transmit filter
configuration. All resistors are ± 1%.
3. Compatible AUI transformer modules, with a brief description of package type and features are included in the
following section.
10BASE-T and AUI Implementation of Am79C940
86
Am79C940
AMD
MACE Compatible 10BASE-T Filters
and Transformers
The table below provides a sample list of MACE com-
patible 10BASE-T filter and transformer modules avail-
able from various vendors. Contact the respective
manufacturer for a complete and updated listing of
components.
Filters
Filters
and
Filters
Filters
Transformers
Resistors
Transformers Transformers
Manufacturer
Bel Fuse
Part #
Package
Transformers
and Choke
Dual Chokes
Dual Chokes
A556-2006-DE 16-pin 0.3 DIL
0556-2006-00 14-pin SIP
0556-2006-01 14-pin SIP
0556-6392-00 16-pin 0.5 DIL
√
√
Bel Fuse
Bel Fuse
√
√
Bel Fuse
Halo Electronics
Halo Electronics
Halo Electronics
PCA Electronics
PCA Electronics
PCA Electronics
FD02-101G
FD12-101G
FD22-101G
EPA1990A
EPA2013D
EPA2162
16-pin 0.3 DIL
16-pin 0.3 DIL
16-pin 0.3 DIL
16-pin 0.3 DIL
16-pin 0.3 DIL
16-pin 0.3 SIP
16-pin 0.3 DIL
16-pin 0.3 SIL
16-pin 0.3 DIL
12-pin 0.5 SMT
16-pin 0.3 DIL
16-pin 0.3 DIL
√
√
√
√
√
√
√
Pulse Engineering PE-65421
Pulse Engineering PE-65434
Pulse Engineering PE-65445
Pulse Engineering PE-65467
√
√
√
Valor Electronics
Valor Electronics
PT3877
FL1043
√
√
MACE Compatible AUI Isolation
Transformers
The table below provides a sample list of MACE com-
patible AUI isolation transformers available from vari-
ous vendors. Contact the respective manufacturer for
a complete and updated listing of components.
Manufacturer
Bel Fuse
Part #
A553-0506-AB
S553-0756-AE
TD01-0756K
TG01-0756W
EP9531-4
Package
Description
16-pin 0.3 DIL
16-pin 0.3 SMD
16-pin 0.3 DIL
16-pin 0.3 SMD
16-pin 0.3 DIL
16-pin 0.3 DIL
16-pin 0.3 SMT
16-pin 0.3 DIL
16-pin 0.3 SMD
50 µH
75 µH
75 µH
75 µH
50 µH
50 µH
75 µH
75 µH
75 µH
Bel Fuse
Halo Electronics
Halo Electronics
PCA Electronics
Pulse Engineering
Pulse Engineering
Valor Electronics
Valor Electronics
PE64106
PE65723
LT6032
ST7032
Am79C940
87
AMD
MACE Compatible DC/DC Converters
The table below provides a sample list of MACE com-
patible DC/DC converters available from various ven-
dors. Contact the respective manufacturer for a
complete and updated listing of components.
Manufacturer
Halo Electronics
Part #
DCU0-0509D
DCU0-0509E
EPC1007P
EPC1054P
EPC1078
Package
24-pin DIP
24-pin DIP
24-pin DIP
24-pin DIP
24-pin DIP
24-pin DIP
24-pin DIP
Voltage
5/-9
Remote On/Off
No
Yes
No
Halo Electronics
PCA Electronics
PCA Electronics
PCA Electronics
Valor Electronics
Valor Electronics
5/-9
5/-9
5/-9
Yes
Yes
No
5/-9
PM7202
5/-9
PM7222
5/-9
Yes
MANUFACTURER CONTACT
INFORMATION
Contact the following companies for further informa-
tion on their products.
Company
U.S. and Domestic
Asia
Europe
Bel Fuse
Phone:
FAX:
(201) 432-0463
(201) 432-9542
852-328-5515
852-352-3706
33-1-69410402
33-1-69413320
Halo Electronics
Phone:
FAX:
(415) 969-7313
(415) 367-7158
65-285-1566
65-284-9466
PCA Electronics
(HPC in Hong Kong)
Phone:
FAX:
(818) 892-0761
(818) 894-5791
852-553-0165
852-873-1550
33-1-44894800
33-1-42051579
Pulse Engineering
Valor Electronics
Phone:
FAX:
(619) 674-8100
(619) 675-8262
852-425-1651
852-480-5974
353-093-24107
353-093-24459
Phone:
FAX:
(619) 537-2500
(619) 537-2525
852-513-8210
852-513-8214
49-89-6923122
49-89-6926542
88
Am79C940
AMD
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature . . . . . . . . . . . –65°C to +150°C
Commercial (C) Devices
Ambient Temperature
Temperature (TA) . . . . . . . . . . . . . . 0°C to +70°C
Under Bias . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Supply Voltages
Supply Voltage to AVSS
(AVDD, DVDD) . . . . . . . . . . . . . . . . . . . . . 5 V ±5%
or DVss (AVDD, DVDD) . . . . . . . . . . . –0.3 V to +6.0 V
All inputs within the range: . . AVDD + 0.5 V ≤ Vin ≤
. . . . . . . . . . . . . . . . . . . . . . . . . . AVSS – 0.5 V, or
. . . . . . . . . . . . . . . . . . . . . . DVDD = 0.5 V ≤ Vin ≤
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . DVSS – 0.5 V
Stresses above those listed under Absolute Maximum Rat-
ings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to Absolute Maxi-
mum Ratings for extended periods may affect device reliabil-
ity. Programming conditions may differ.
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified
Parameter
Symbol
Parameter Description
Input LOW Voltage
Test Conditions
Min
Max
Unit
V
VIL
0.8
VIH
Input HIGH Voltage
2.0
V
VILX
XTAL1 Input LOW Voltage
(External Clock Signal)
VSS = 0.0 V
–0.5
0.8
V
VIHX
XTAL1 Input HIGH Voltage
(External Clock Signal)
VSS = 0.0 V
VDD –
0.8
VDD +
0.5
V
VOL
VOH
IIL1
Output LOW Voltage
Output HIGH Voltage
Input Leakage Current
IOL = 3.2 mA
0.45
V
V
IOH = –0.4 mA (Note 1)
2.4
VDD = 5 V, VIN = 0 V
–10
10
µA
(Note 2)
IIL2
IIH
Input Leakage Current
Input Leakage Current
VDD = 5 V, VIN = 0 V
(Note 2)
–200
200
µA
µA
µA
µA
VDD = 5 V, VIN = 2.7 V
(Note 3)
–100
+500
+500
IIAXD
IIAXC
IILXN
Input Current at DI+
and DI–
–1 V < VIN < AVDD + 0.5 V
–1 V < VIN < AVDD + 0.5 V
–500
–500
Input current at
CI+ and CI–
XTAL1 Input LOW Current
during normal operation
VIN = 0 V
SLEEP = HIGH
–92
92
µA
µA
µA
IIHXN
IILXS
XTAL1 Input HIGH Current
during normal operation
VIN = 5.5 V
SLEEP = HIGH
XTAL1 Input LOW Current
during Sleep
VIN = 0 V
SLEEP = LOW
<10
IIHXS
IOZ
XTAL1 Input HIGH Current
during Sleep
VIN = 5.5 V
SLEEP = LOW
410
10
µA
µA
Output Leakage Current
0.4 V < VOUT < VDD
(Note 4)
–10
630
–40
–1
VAOD
VAODOFF
IAODOFF
Differential Output Voltage
|(DO+)–(DO–)|
RL = 78 Ω
1200
+40
+1
mV
mV
mA
Transmit Differential Output
Idle Voltage
RL = 78 Ω (Note 5)
RL = 78 Ω
Transmit Differential
Output Idle Current
Am79C940
89
AMD
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified (continued)
Parameter
Symbol
Parameter Description
Test Conditions
RL = 78 Ω
Min
Max
Unit
VAOCM
DO± Common Mode
2.5
AVDD
V
Output Voltage
VODI
VATH
VASQ
VIRDVD
VICM
DO± Differential Output
Voltage Imbalance
RL = 78 Ω (Note 6)
RL = 78 Ω (Note 6)
–25
–35
25
35
mV
mV
mV
V
Receive Data Differential
Input Threshold
DI± and CI± Differential
Input Threshold Squelch
–160
–275
1.5
RL = 78 Ω (Note 6)
DI± and CI± Differential
Mode Input Voltage Range
DI± and CI± Input Bias
Voltage
IIN = 0 mA
AVDD–3.0
AVDD–0.8
–100
V
VOPD
DO± Undershoot Voltage
at Zero Differential on
Transmit Return to
Zero (ETD)
(Note 5)
mV
IDD
Power Supply Current
Power Supply Current
Power Supply Current
Power Supply Current
SCLK = 25 MHz
XTAL1 = 20 MHz
75
100
10
mA
µA
IDDSLEEP
IDDSLEEP
IDDSLEEP
SLEEP Asserted, AWAKE = 0
RWAKE = 0 (Note 7)
SLEEP Asserted, AWAKE = 1
RWAKE = 0 (Note 7)
mA
mA
SLEEP Asserted, AWAKE = 0
20
RWAKE = 1 (Note 7)
Twisted Pair Interface
IIRXD
Input Current at RXD±
AVSS < VIN < AVDD
–500
10
500
µA
RRXD
RXD± Differential Input
(Note 8)
KΩ
Resistance
VTIVB
VTIDV
RXD+, RXD– Open Circuit
Input Voltage (Bias)
IIN = 0 mA
AVDD – 3.0
AVDD – 1.5
V
V
Differential Mode Input
AVDD = +5 V
–3.1
+3.1
Voltage Range (RXD±)
VTSQ+
VTSQ-
VTHS+
VTHS-
RXD Positive Squelch
Threshold (Peak)
Sinusoid
5 MHz ≤ f ≤10 MHz
300
–520
150
520
–300
293
mV
mV
mV
RXD Negative Squelch
Threshold (Peak)
Sinusoid
5 MHz ≤ f ≤10 MHz
RXD Post-Squelch
Positive Threshold (Peak)
Sinusoid
5 MHz ≤ f ≤10 MHz
RXD Post-Squelch
Sinusoid
Negative Threshold (Peak)
5 MHz ≤ f ≤10 MHz
–293
180
–150
312
mV
mV
VLTSQ+
VLTSQ-
VLTHS+
VLTHS-
RXD Positive Squelch
Threshold (Peak)
LRT = LOW
LRT = LOW
LRT = LOW
LRT = LOW
RXD Negative Squelch
Threshold (Peak)
–312
90
–180
156
mV
mV
mV
RXD Post-Squelch Positive
Threshold (Peak)
RXD Post-Squelch
–156
–90
Negative Threshold (Peak)
90
Am79C940
AMD
DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise
specified (continued)
Parameter
Symbol
VRXDTH
VTXH
Parameter Description
Test Conditions
(Note 4)
Min
Max
Unit
RXD Switching Threshold
–35
35
mV
TXD± and TXP± Output
HIGH Voltage
DVSS = 0 V
DVDD – 0.6
DVSS
DVDD
V
VTXL
VTXI
TXD± and TXP± Output
LOW Voltage
DVDD = +5 V
DVSS + 0.6
V
TXD± and TXP±
Differential Output
Voltage Imbalance
–40
+40
40
mV
mV
Ω
VTXOFF
RTX
TXD± and TXP± Idle
Output Voltage
DVDD = +5 V
(Note 8)
TXD± Differential Driver
Output Impedance
40
TXP± Differential Driver
Output Impedance
(Note 8)
80
Ω
Notes:
1. VOH does not apply to open-drain output pins.
2. IIL1 and IIL2 applies to all input only pins except DI±, CI±, and XTAL1.
IIL1 = ADD4–0, BE1–0, CS, EAM/R, FDS, RESET, RXDAT, R/W, SCLK.
IIL2 = TC, TDI, TCK, TMS.
3. Specified for input only pins with internal pull-ups: TC, TDI, TCK, TMS.
4. IOZ applies to all three-state output pins and bi-directional pins.
5. Test not implemented to data sheet specification.
6. Tested, but to values in excess of limits. Test accuracy not sufficient to allow screening guard bands.
7. During the activation of SLEEP:
–
The following pins are placed in a high impedance state: SRD, SF/BD, TXDAT, DXCVR, DTV, TDTREQ, RDTREQ, NTR
and TDO.
–
The following I/O pins are placed in a high impedance mode and have their internal TTL level translators disabled:
DBUS15–0, EOF, SRDCLK, RXCRS, RXDAT, CLSN, TXEN, STDCLK and TXDAT+.
–
–
The following input pin has its internal pull-up and TTL level translator disabled: TC.
The following input pins have their internal TTL level translators disabled and do not have internal pull-ups: CS, FDS,
R/W, ADD4–0, SCLK, BE0, BE1 and EAM/R.
–
The following pins are pulled low: XTAL1 (XTAL2 feedback is cut off from XTAL1), TXD+, TXD–, TXP+, TXP–, DO+
and DO.
–
–
The following pins have their input voltage bias disabled: DI+, DI, CI+ and CI.
AWAKE and RWAKE are reset to zero. IDDSLEEP, with either AWAKE set or RWAKE set, will be much higher and its value
remains to be determined.
8. Parameter not tested.
Am79C940
91
AMD
AC CHARACTERISTICS
Parameter
No.
Symbol
Parameter Description
Test Conditions
Min (ns)
Max (ns)
Clock and Reset Timing
1
2
3
4
5
6
7
tSCLK
tSCLKL
tSCLKH
tSCLKR
tSCLKF
tRST
SCLK period
40
1000
0.6*tSCLK
0.6*tSCLK
5
SCLK LOW pulse width
SCLK HIGH pulse width
SCLK rise time
0.4*tSCLK
0.4*tSCLK
SCLK fall time
5
RESET pulse width
15*tSCLK
tBT
Network Bit Time (BT)
=2*tX1 or tSTDC)
99
101
Internal MENDEC Clock Timing
9
tX1
XTAL1 period
49.995
20
50.005
11
12
13
14
tX1H
tX1L
tX1R
tX1F
XTAL1 HIGH pulse width
XTAL1 LOW pulse width
XTAL1 rise time
20
5
5
XTAL1 fall time
BIU Timing (Note 1)
31
32
33
tADDS
tADDH
tSLVS
Address valid setup to SCLK↓
Address valid hold after SCLK↓
9
2
CS or FDS and TC, BE1–0,
R/W setup to SCLK↓
9
2
34
tSLVH
CS or FDS and TC, BE1–0,
R/W hold after SCLK↓
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
tDATD
tDATH
tDTVD
tDTVH
tEOFD
tEOFH
tCSIS
Data out valid delay from SCLK↓
Data out valid hold after SCLK↓
DTV valid delay from SCLK↓
DTV valid hold after SCLK↓
CL = 100 pF (Note 2)
CL = 100 pF (Note 2)
CL = 100 pF (Note 2)
32
32
32
6
6
EOF valid delay from SCLK↓
EOF output valid hold after SCLK↓
CS inactive prior to SCLK↓
6
9
9
2
tEOFS
tEOFH
tRDTD
tRDTH
tTDTD
tTDTH
tDATS
tDATIH
tDATE
EOF input valid setup to SCLK↓
EOF input valid hold after SCLK↓
RDTREQ valid delay from SCLK↓
RDTREQ valid hold after SCLK↓
TDTREQ valid delay from SCLK↓
TDTREQ valid hold after SCLK↓
Data in valid setup to SCLK↓
Data in valid setup after SCLK↓
CL = 100 pF (Note 2)
CL = 100 pF (Note 2)
32
32
6
6
9
2
0
Data output enable delay from
SCLK↓ (Note 3)
51
tDATD
Data output disable delay from
25
SCLK↓ (Notes 3, 4)
Notes:
1. The following BIU timing assumes that EDSEL = 1. Therefore, these parameters are specified with respect to the falling edge
of SCLK (SCLK↓). If EDSEL = 0, the same parameters apply but should be referenced to the rising edge of SCLK (SCLK↑).
2. Tested with CL set at 100 pF and derated to support the Indicated distributed capacitive Load. See the BIU output valid delay
vs. Load Chart.
3. Guaranteed by design—not tested.
4. tDATD is defined as the time required for outputs to turn high impedence and is not referred to as output voltage lead.
92
Am79C940
AMD
AC CHARACTERISTICS (continued)
Parameter
No.
AUI Timing
53
Symbol
Parameter Description
Test Conditions
Min (ns)
Max (ns)
tDOTD
XTAL1 (externally driven) to
DO± output
100
5.0
5.0
1
54
55
56
57
58
59
tDOTR
DO± rise time (10% to 90%)
DO± fall time (10% to 90%)
DO± rise and fall mismatch
DO± End of Transmit Delimiter
DI± pulse width to reject
2.5
2.5
tDOTF
tDOETM
tDOETD
tPWRDI
tPWODI
200
375
15
|input| > |VASQ|
DI± pulse width to turn on
internal DI carrier sense
|input| > |VASQ|
|input| > |VASQ|
|input| > |VASQ|
45
45
60
61
tPWMDI
tPWKDI
DI± pulse width to maintain
internal DI carrier sense on
136
DI± pulse width to turn internal
200
DI carier sense off
62
63
tPWRCI
tPWOCI
CI± pulse width to reject
|input| > |VASQ|
|input| > |VASQ|
10
90
CI± pulse width to turn on
internal SQE sense
26
26
64
65
66
tPWMCI
tPWKCI
tSQED
CI± pulse width to maintain
internal SQE sense on
|input| > |VASQ|
|input| > |VASQ|
|input| > |VASQ|
|input| > |VASQ|
CI± pulse width to turn internal
SQE sense off
160
CI± SQE Test delay from
O± inactive
67
79
80
tSQEL
tCLSHI
tTXH
CI± SQE Test length
CLSN high time
tSTDC+30
32*tSTDC
TXEN or DO± hold time from
CLSN↑
|input| > |VASQ|
96*tSTDC
DAI Port Timing
70
72
tTXEND
tTXDD
STDCLK↑ delay to TXEN↓
CL = 50 pF
CL = 50 pF
70
70
STDCLK↑ delay to TXDAT±
change
80
95
tXH
TXEN or TXDAT± hold time
from CLSN↑
32*tSTDC
96*tSTDC
tDOTF
Mismatch in STDCLK≠ to TXEN↓
and TXDAT± change
15
96
97
tTXDTR
TXDAT± rise time
See Note 1
See Note 1
See Note 1
5
tTXDTF
TXDAT± fall time
5
98
tTXDTM
tTXENETD
tFRXDD
tLRXDD
tCRSCLSD
TXDAT± rise and fall mismatch
TXEN End of Transmit Delimiter
First RXDAT↓ delay to RXCRS↑
Last RXDAT≠ delay to RXCRS↓
1
99
250
350
100
120
100
100
101
102
RXCRS↑ delay to CLSN↑
(TXEN = 0)
Am79C940
93
AMD
AC CHARACTERISTICS (continued)
Parameter
No.
Symbol
Parameter Description
Test Conditions
Min (ns)
Max (ns)
GPSI Clock Timing
17
18
19
20
21
22
23
24
25
26
tSTDC
STDCLK period
99
45
45
101
tSTDCL
tSTDCH
tSTDCR
tSTDCF
tSRDC
STDCLK low pulse width
STDCLK high pulse width
STDCLK rise time
See Note 1
See Note 1
See Note 1
5
5
STDCLK fall time
SRDCLK period
85
38
38
115
tSRDCH
tSRDCL
tSRDCR
tSRDCF
SRDCLK HIGH pulse width
SRDCLK LOW pulse width
SRDCLK rise time
See Note 1
See Note 1
5
5
SRDCLK fall time
GPSI Timing
70
71
72
tTXEND
STDCLK↑ delay to TXEN↑
(CL=50 pF)
(CL=50 pF)
(CL=50 pF)
70
70
tTXENH
tTXDD
TXEN hold time from STDCLK↑
5
5
STDCLK↑ delay to TXDAT+
change
73
tTXDH
TXDAT+ hold time from
(CL=50 pF)
STDCLK↑
74
75
76
tRXDR
tRXDF
tRXDH
RXDAT rise time
RXDAT fall time
See Note 1
See Note 1
8
8
RXDAT hold time (SRDCLK↑ to
RXDAT change)
25
0
77
tRXDS
RXDAT setup time
(RXDAT stable to SRDCLK↑)
78
79
80
tCRSL
tCLSHI
tTXH
RXCRS low time
CLSN high time
tSTDC+20
tSTDC+30
32*tSTDC
TXEN or TXDAT± hold time from
CLSN↑
96*tSTDC
81
tCRSH
RXCRS hold time from
0
SRDCLK↑
EADI Feature Timing
85
86
87
tDSFBDR
tDSFBDF
tEAMRIS
SRDCLK↓ delay to SF/BD↑
SRDCLK↓ delay to SF/BD↓
20
20
EAM/R invalid setup prior to
SRDCLK↓ after SFD
–150
0
88
tEAMS
EAM setup to SRDCLK↓ at bit 6
of Source Address byte 1
(match packet)
89
90
tEAMRL
EAM/R low time
200
100
tSFBDHIH
SF/BD high hold from last
SRDCLK↓
91
tEARS
EAR setup to SRDCLK↓ at bit 6
of message byte 64
0
(reject normal packet)
Note:
1. Not tested but data available upon request.
94
Am79C940
AMD
Max
AC CHARACTERISTICS (continued)
Parameter
No.
Symbol
Parameter Description
Test Conditions
Min
IEEE 1149.1 Timing
109
tTCLK
TCK Period, 50% duty
cycle (+5%)
100
110
111
112
113
114
115
tsu1
tsu2
thd1
thd2
td1
TMS setup to TCK↑
8
5
TDI setup to TCK↑
TMS hold time from TCK↑
TDI hold time from TCK↑
TCK↓ delay to TDO
5
10
30
35
td2
TCK↓ delay to SYSTEM OUTPUT
10BASE-T Transmit Timing
Min
Max
350
5.5
Unit
125
126
127
128
tTETD
tTR
Transmit Start of Idle
Transmitter Rise Time
Transmitter Fall Time
250
ns
ns
ns
(10% to 90%)
tTF
(90% to 10%)
5.5
tTM
Transmitter Rise and Fall
Time Mismatch
1
ns
ns
129
130
131
132
133
134
135
136
tXMTON
tXMTOFF
tPERLP
tPWLP
tPWPLP
tJA
XMT# Asserted Delay
100
TBD
24
XMT# De-asserted Delay
Idle Signal Period
TBD
8
ms
ms
ns
Idle Link Pulse Width
(Note 1)
(Note 1)
75
120
55
Predistortion Idle Link Pulse Width
Transmit Jabber Activation Time
Transmit Jabber Reset Time
45
ns
20
150
750
ms
ms
µs
tJR
250
1.0
tJREC
Transmit Jabber Recovery Time
(Minimum Time Gap Between
Transmitted Packets to Prevent
Jabber Activation)
10BASE-T Receive Timing
140
tPWNRD
RXD Pulse Width Not to
Turn Off Internal
Carrier Sense
VIN > VTHS (min)
136
–
ns
141
tPWROFF
RXD Pulse Width to Turn Off
VIN > VTHS (min)
200
200
ns
ns
ns
ms
142
143
tRETD
Receive Start of Idle
tRCVON
tRCVOFF
RCV# Asserted Delay
RCV# De-asserted Delay
tRON–50 tRON+100
TBD TBD
144
Note:
1. Not tested but data available upon request.
Am79C940
95
AMD
BIU Output Valid Delay vs. Load Chart
nom+4
nom
BIU Output Valid Delay
from SCLK↓
(ns)
nom–4
nom–8
50
75
100
125
150
CL (pF)
16235C-19
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is High-
Impedance
“Off” State
KS000010
96
Am79C940
AMD
SWITCHING TEST CIRCUITS
IOL
Sense Point
VTHRESHOLD
CL
IOH
16235C-20
Normal and Three-State Outputs
AVDD
52.3 Ω
DO+
DO–
Test Point
154 Ω
100 pF
AVSS
16235C-21
AUI DO Switching Test Circuit
DVDD
294 Ω
TXD+
TXD–
Test Point
294 Ω
100 pF
Includes Test
Jig Capacitance
DVSS
16235C-22
TXD Switching Test Circuit
Am79C940
97
AMD
DVDD
715 Ω
TXP+
TXP–
Test Point
715 Ω
100 pF
Includes Test
Jig Capacitance
DVSS
16235C-23
TXP Outputs Test Circuit
AC WAVEFORMS
1
2
3
SCLK
4
5
6
RESET
9
11
12
XTAL1
14
13
16235C-24
Clock and Reset Timing
98
Am79C940
AMD
AC WAVEFORMS
SCLK
(EDSEL = 0)
TL TH S0 S1 S2 S3 S0 S1 S2 S3
S0 S1 S2 S3 S0
SCLK
(EDSEL = 1)
TL TH S0 S1 S2 S3 S0 S1 S2 S3
S0 S1 S2 S3 S0
31
ADD[4:0]
32
R/W
34
33
41
CS or FDS
51
35
36
DBUS[15:0]
50
Word N
Last Byte
or Word
Word N+1
38
40
DTV
EOF
37
39
BE0-1
34
TC = 1
16235C-25
Host System Interface—2-Cycle Receive FIFO/Register Read Timing
Am79C940
99
AMD
AC WAVEFORMS
SCLK
(EDSEL = 0)
TL TH S0 S1 W0 W1 S2 S3 S0 S1 W0 W1 S2 S3 S0 S1 W0 W1 S2 S3 S0
SCLK
(EDSEL = 1)
TL TH S0 S1 W0 W1 S2 S3 S0 S1 W0 W1 S2 S3 S0 S1 W0 W1 S2 S3 S0
31
ADD[4:0]
32
R/W
33
34
41
CS or FDS
51
35
50
Last Byte
or Word
DBUS[15:0]
Word N
36
Word N+1
38
DTV
37
40
EOF
39
BE0-1
34
TC= 0
16235C-26
Host System Interface—3-Cycle Receive FIFO/Register Read Timing
100
Am79C940
AMD
AC WAVEFORMS
SCLK
(EDSEL = 0)
TL TH S0 S1 S2 S3 S0 S1 S2 S3
S0 S1 S2 S3 S0
SCLK
(EDSEL = 1)
TL TH S0 S1 S2 S3 S0 S1 S2 S3
31
S0 S1 S2 S3 S0
ADD4–0
32
R/W
33
41
34
orFDS
CS
48
DBUS15–0
DTV
Word N
49
Last Byte
or Word
Word N+1
38
37
43
EOF
42
BE0-1
34
TC = 1
16235C-27
Host System Interface—2-Cycle Transmit FIFO/Register Write Timing
Am79C940
101
AMD
AC WAVEFORMS
SCLK
TL TH S0 S1 W0 W1 S2 S3 S0 S1 W0 W1 S2 S3 S0 S1 W0 W1 S2 S3 S0
(EDSEL = 0)
SCLK
(EDSEL = 1)
TL TH S0 S1 W0 W1 S2 S3 S0 S1 W0 W1 S2 S3 S0 S1 W0 W1 S2 S3 S0
31
ADD[4:0]
32
R/W
33
34
41
CS
48
DBUS[15:0]
Word N
49
Last Byte
or Word
Word N+1
38
DTV
37
43
34
EOF
42
BE0-1
TC = 0
16235C-28
Host System Interface—3-Cycle Transmit FIFO/Register Write Timing
SCLK
(EDSEL = 0)
S0 S1 S2 S3
S0 S1 S2 S3
S2 S3 S0 S1 S2
S2 S3 S0 S1 S2
S0 S1 S2 S3 S0
SCLK
(EDSEL = 1)
S0 S1 S2 S3 S0
40
EOF
44
39
Note 1
RDTREQ
45
16235C-29
Note: Once the host detects the EOF output active from the MACE device (S2/S3 edge), if no other receive packet exists in
the RCVFIFO which meets the assert conditions for RDTREQ, the MACE device will deassert RDTREQ within 4 SCLK cycles
(S0/S1 edge). This is consistent for both 2 or 3 cycle read operations.
Host System Interface—RDTREQ Read Timing
102
Am79C940
AMD
AC WAVEFORMS
SCLK
(EDSEL = 0)
S1 S2 S3 S0 S1 S2 S3
S0 S1 S2 S3 S0 S1 S2 S3 S0
SCLK
(EDSEL = 1)
S1 S2 S3 S0 S1 S2 S3
S0 S1 S2 S3 S0 S1 S2 S3 S0
43
EOF
46
42
TDTREQ
Note 1
47
Note 2
Note 3
16235C-30
Notes:
1. TDTREQ will be asserted for two write cycles (4 SCLK cycles) minimum.
2. TDTREQ will deassert 1 SCLK cycle after EOF is detected (S2/S3 edge).
3. When EOF is written, TDTREQ will go inactive for 1 SCLK cycle minimum.
Host System Interface—TDTREQ Write Timing
XTAL1
9
STDCLK
TXEN
1
1
1
1
TXDAT+
(Note 1)
0
0
54
55
DO+
DO–
1
DO±
53
16235C-31
Note: TXDAT+ is the internal version of the signal, and is shown for clarification only.
AUI Transmit Timing—Start of Packet
Am79C940
103
AMD
XTAL1
STDCLK
TXEN
1
1
TXDAT+
(Note 1)
0
0
DO+
DO–
DO±
57
1
0
0
bit (n–2)
bit (n)
> 200 ns
bit (n–1)
16235C-32
Note: TXDAT+ is the internal version of the signal, and is shown for clarification only.
AUI Transmit Timing—End of Packet (Last Bit = 0)
XTAL1
SRDCLK
TXEN
1
1
1
0
TXDAT+
(Note 1)
DO+
DO–
DO±
57
1
0
bit (n–2)
> 250 ns
bit (n–1)
bit (n)
16235C-33
Note: TXDAT+ is the internal version of the signal, and is shown for clarification only.
AUI Transmit Timing—End of Packet (Last Bit = 1)
104
Am79C940
AMD
57
40 mV
DO±
0 V
100 mV Max
80 Bit Times Max
16235C-34
AUI Transmit Timing—End Transmit Delimiter (ETD)
Bit Cell 1
1
Bit Cell 2
0
Bit Cell 3
Bit Cell 4
Bit Cell 5
1
1
0
0
(Note 1)
59
60
DI±
V
ASQ
BCC
BCB
BCC
BCB
BCC
BCC
BCB
BCC
BCB
RXCRS
IVCO_ENABLE
IVCO
SRDCLK
SRD
5 Bit Times Max
(Note 2)
(Note 3)
16235C-35
Notes:
1. Minimum pulse width >45 ns with amplitude > –160 mV.
2. SRD first decoded bit might not be defined until bit time 5.
3. First valid data bit.
4. IVCO and VCO ENABLE are internal signals shown for clarification only.
AUI Receive Timing—Start of Packet
Am79C940
105
AMD
Bit Cell (n–1)
60
Bit Cell (n)
0
1
61
DI±
V
ASQ
(Note 2)
BCC
BCB
BCC
BCB
RXCRS
(Note 1)
IVCO
SRDCLK
SRD
bit (n)
bit (n–1)
16235C-36
Notes:
1. RXCRS deasserts in less than 3 bit times after last DI± rising edge.
2. Start of next packet reception (2 bit times).
3. IVCO is an internal signal shown for clarification only.
AUI Receive Timing—End of Packet (Last Bit = 0)
Bit Cell (n)
1
Bit Cell (n–1)
0
DI±
RXCRS
IVCO
61
BCC
BCB
BCC
(Note 1)
SRDCLK
SRD
bit (n)
bit (n–1)
16235C-37
Notes:
1. RXCRS deasserts in less than 3 bit times after last DI± rising edge.
2. IVCO is an internal signal shown for clarification only.
AUI Receive Timing—End of Packet (Last Bit = 1)
Am79C940
106
AMD
DO±
TXEN
CI+
CI-
80
CLSN
79
16235C-38
AUI Collision Timing
DO±
66
CI+
CI-
67
CLSN = 0
16235C-39
AUI SQE Test Timing
Am79C940
107
AMD
STDCLK
BCB
BCB
BCB
BCB
BCB
BCB
BCB
BCB
72
TXDAT±
99
97
96
TXDAT+
TXDAT-
TXEN
95
72
16235C-40
DAI Port Transmit Timing
RXDAT
100
101
RXCRS
16235C-41
DAI Port Receive Timing
108
Am79C940
AMD
TXDAT+
TXDAT-
TXEN
RXDAT
RXCRS
CLSN
102
79
16235C-42
DAI Port Collision Timing
Destination Address
Byte 1
Destination Address
Byte 2
SRDCLK
BIT
2
BIT
0
BIT BIT
BIT BIT BIT BIT BIT
SRD
SFD
0
1
3
4
5
6
7
86
SF/BD
85
Note 1
EAM/R
87
89
16235C-43
Note: First assertion of EAM/R must occur after bit 2/3 boundary of preamble.
EADI Feature Timing—Start of Address
Am79C940
109
AMD
Last Byte of Message
SRDCLK
SRD
90
86
SF/BD
85
16235C-44
EADI Feature—End of Packet Timing
Destination Address
Byte 6
Source Address
Byte 1
Source Address
Byte 2
SRDCLK
SRD
BIT
3
BIT BIT BIT BIT BIT BIT
BIT BIT
BIT BIT BIT
5
6
7
0
1
2
4
5
6
7
0
86
SF/BD
85
88
EAM
89
16235C-45
EADI Feature-Match Timing
110
Am79C940
AMD
Byte 64
Byte 65
Byte 66
(Data Byte 51)
(Data Byte 52)
(Data Byte 53)
SRDCLK
SRD
BIT BIT BIT BIT BIT BIT
BIT BIT
BIT
5
BIT BIT BIT
BIT
1
BIT
4
4
5
6
7
0
1
2
3
6
7
0
85
86
SF/BD
91
EAR
89
16235C-46
EADI Feature Reject Timing
17
19
18
STDCLK
TXDAT+
72
70
73
20
21
TXEN
71
Note 1
RXCRS
16235C-47
Note: During transmit, the RXCRS input must be asserted (high) and remain active-high after TXEN goes active (high). If
RXCRS is deasserted before TXEN is deasserted, LCAR will be reported (Transmit Frame Status) after the transmission is
completed by the MACE device.
GPSI Transmit Timing
Am79C940
111
AMD
22
24
25
23
SRDCLK
26
75
74
77
RXDAT
RXCRS
76
81
78
16235C-48
GPSI Receive Timing
STDCLK
TXDAT+
72
70
73
TXEN
CLSN
80
79
16235C-49
GPSI Collision Timing
112
Am79C940
AMD
TCK
TMS
tsu1
td1
thd1
tsu2
TDI
thd2
TDO
td2
System Output
16235C-50
IEEE 1149.1 TAP Timing
tTR
tTF
TXD+
TXP+
TXD–
TXP–
tTETD
tXMTON
tXMTOFF
TXEN
Note 1
Note:
1. Parameter is internal to the device.
16235C-51
10BASE-T Transmit Timing
Am79C940
113
AMD
VTSQ+
VTSQ–
RXD±
tRCVON
tRCVOFF
RXCRS
16235C-52
10BASE-T Receive Timing
TXD±
RXD±
tCOLON
tCOLOFF
CLSN
16235C-53
10BASE-T Collision Timing
114
Am79C940
AMD
tPWPLP
TXD+
TXP+
TXD–
TXP–
tPWLP
tPERLP
16235C-54
10BASE-T Idle Link Test Pulse
VTSQ+
VTHS+
VTHS–
RXD±
VTSQ–
16235C-55
10BASE-T Receive Thresholds (LRT = 0)
VLTSQ+
VLTHS+
VLTHS–
RXD±
VLTSQ–
16235C-56
10BASE-T Receive Thresholds (LRT = 1)
Am79C940
115
APPENDIX A
Logical Address Filtering
For Ethernet
The purpose of logical (or group or multicast) addresses
is to allow a group of nodes in a network to receive the
same message. Each node can maintain a list of multi-
cast addresses that it will respond to. The logical ad-
dress filter mechanism in AMD Ethernet controllers is a
hardware aide that reduces the average amount of host
computer time required to determine whether or not an
incoming packet with a multicast destination address
should be accepted.
In the latter case described above, a node can be made
a member of several groups by setting the appropriate
bits in the logical address filter register. The administra-
tor can use the table Mapping of Logical Address to Fil-
ter Mask to find a multicast address that maps into a par-
ticularaddressfilterbit. Forexampleaddress00000000
00BB maps into bit 15. Therefore, any node that has bit
15 set in its logical address filter register will receive all
packets addressed to 0000 0000 00BB. (Addresses in
this table are not shown in the standard Ethernet format.
In the table the rightmost byte is the first byte to appear
on the network with the least significant bit appearing
first).
The logical address filter hardware is an implementation
of a hash code searching technique commonly used by
software programmers. If the multicast bit in the destina-
tion address of an incoming packet is set, the hardware
maps this address into one of 64 categories then ac-
cepts or rejects the packet depending on whether or not
the bit in the logical address filter register corresponding
the selected category is set. For example, if the address
maps into category 24, and bit 24 of the logical address
filter register is set, the packet is accepted.
Driver software that manages a list of multicast ad-
dresses can work as follows. First the multicast address
list and the logical address filter must be initialized.
Some sort of management function such as the driver
initialization routine passes to the driver a list of ad-
dresses. For each address in the list the driver uses a
subroutine similar to the one listed in the Am7990
LANCE data sheet to set the appropriate bit in a soft-
ware copy of the logical address filter register. When the
complete list of addresses has been processed, the reg-
ister is loaded.
Since there are more than 1014 possible multicast ad-
dresses and only 64 categories, this scheme is far from
unambiguous. This means that the software will still
have to compare the address of a received packet with
its list of acceptable multicast addresses to make the fi-
nal decision whether to accept or discard the packet.
However, the hardware prevents the software from hav-
ing to deal with the vast majority of the unacceptable
packets.
Later, when a packet is received, the driver first looks at
the Individual/Group bit of the destination address of the
packet to find out whether or not this is a multicast ad-
dress. If it is, the driver must search the multicast ad-
dress list to see if this address is in the list. If it is not in
the list, the packet is discarded.
The efficiency of this scheme depends on the number of
multicast groups that are used on a particular network
and the number of groups to which a node belongs. At
one extreme if a node happens to belong to 64 groups
that map into 64 different categories, the hardware will
accept all multicast addresses, and all filtering must be
done by software. At the other extreme (which is closer
to a practical network), if multicast addresses are as-
signed by the local administrator, and fewer than 65
groups are set up, the addresses can be assigned so
thateachaddressmapsintoadifferentcategory, andno
software filtering will be needed at all.
The broadcast address, which consists of all ones is a
special multicast address. Packets addressed to the
broadcast address must be received by all nodes. Since
broadcast packets are usually more common than other
multicast packets, the broadcast address should be the
first address in the multicast address list.
A-1
Am79C940
AMD
MAPPING OF LOGICAL ADDRESS TO FILTER MASK
LADRF
Bit
Destination
Address Accepted
LADRF
Bit
Destination
Address Accepted
Byte #
Bit #
Byte #
Bit #
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
85 00 00 00 00 00
A5 00 00 00 00 00
E5 00 00 00 00 00
C5 00 00 00 00 00
45 00 00 00 00 00
65 00 00 00 00 00
25 00 00 00 00 00
05 00 00 00 00 00
4
4
4
4
4
4
4
4
0
1
2
3
4
5
6
7
32
33
34
35
36
37
38
39
21 00 00 00 00 00
01 00 00 00 00 00
41 00 00 00 00 00
71 00 00 00 00 00
E1 00 00 00 00 00
C1 00 00 00 00 00
81 00 00 00 00 00
A1 00 00 00 00 00
1
1
1
1
1
1
1
1
0
1
2
3
4
5
6
7
8
2B 00 00 00 00 00
0B 00 00 00 00 00
4B 00 00 00 00 00
6B 00 00 00 00 00
EB 00 00 00 00 00
CB 00 00 00 00 00
8B 00 00 00 00 00
BB 00 00 00 00 00
5
5
5
5
5
5
5
5
0
1
2
3
4
5
6
7
40
41
42
43
44
45
46
47
8F 00 00 00 00 00
BF 00 00 00 00 00
EF 00 00 00 00 00
CF 00 00 00 00 00
4F 00 00 00 00 00
6F 00 00 00 00 00
2F 00 00 00 00 00
0F 00 00 00 00 00
9
10
11
12
13
14
15
2
2
2
2
2
2
2
2
0
1
2
3
4
5
6
7
16
17
18
19
20
21
22
23
C7 00 00 00 00 00
E7 00 00 00 00 00
A7 00 00 00 00 00
87 00 00 00 00 00
07 00 00 00 00 00
27 00 00 00 00 00
67 00 00 00 00 00
47 00 00 00 00 00
6
6
6
6
6
6
6
6
0
1
2
3
4
5
6
7
48
49
50
51
52
53
54
55
63 00 00 00 00 00
43 00 00 00 00 00
03 00 00 00 00 00
23 00 00 00 00 00
A3 00 00 00 00 00
83 00 00 00 00 00
C3 00 00 00 00 00
E3 00 00 00 00 00
3
3
3
3
3
3
3
3
0
1
2
3
4
5
6
7
24
25
26
27
28
29
30
31
69 00 00 00 00 00
49 00 00 00 00 00
09 00 00 00 00 00
29 00 00 00 00 00
A9 00 00 00 00 00
89 00 00 00 00 00
C9 00 00 00 00 00
E9 00 00 00 00 00
7
7
7
7
7
7
7
7
0
1
2
3
4
5
6
7
56
57
58
59
60
61
62
63
CD00 00 00 00 00
ED 00 00 00 00 00
AD 00 00 00 00 00
8D 00 00 00 00 00
0D 00 00 00 00 00
2D 00 00 00 00 00
6D 00 00 00 00 00
4D 00 00 00 00 00
A-2
Am79C940
APPENDIX B
BSDL Description of Am79C940
MACE JTAG Structure
entity Am79C940 is
generic (PHYSICAL_PIN_MAP : string := ”undefined”);
port (
DO0,DO1,DTV_L,INTR_L,LNKST_L,DXRCV_L,RDTREQ_L,RXPOL_L,SF_BD,SRD,
TDO,TDTREQ_L,TXD0,TXD1,TXDAT0,TXP0,TXP1,XTAL2 : out bit;
BE0_L,BE1_L,CI0,CI1,CS_L,DI0,DI1,EAM_R_L,EDSEL,FDS_L,RESET_L,RXD0,
RXD1,R_W_L,SCLK,SLEEP_L,TCLK,TC_L,TDI,TMS,XTAL1 : in bit;
ADD : in bit_vector (4 downto 0);
CLSN,EOF_L,RXCRS,RXDAT,SRDCLK,STDCLK,TXDAT1,TXEN_L : inout bit;
DBUS : inout bit_vector (15 downto 0);
AVDD1,AVDD2,AVDD3,AVDD4,AVSS1,AVSS2,
DVDD1,DVDD2,DVDDN,DVDDP,DVSS1,DVSS2,DVSSN1,DVSSN2,DVSSN3,DVSSP : linkage bit
);
use STD_1149_1_1990.all; – get std 1149.1 1990 attributes and definitions
attribute PIN_MAP of am79c940 : entity is PHYSICAL_PIN_MAP;
constant PQFP_PACKAGE : PIN_MAP_STRING :=
“SRDCLK:5, EAM_R_L:6, SRD:7, SF_BD:8, RESET_L:9, SLEEP_L:10,” &
“DVDDP:11,” &
“INTR_L:12, TC_L:13,” &
“DBUS:(36, 35, 33, 32, 31, 29, 25, 24, 23, 22, 21, 19, 18, 17, 16, 14),” &
“DVSSN1:15, DVSSN2:20, DVDDN:34, DVSSN3:37,” &
“EOF_L:38, DTV_L:39, FDS_L:40, BE0_L:41, BE1_L:42, SCLK:43,” &
“TDTREQ_L:44, RDTREQ_L:45, ADD: (50, 49, 48, 47, 46),” &
“R_W_L:55, CS_L:56, RXPOL_L:57, LNKST_L:58,” &
“TDO:59, TMS:60, TCK:61,” &
“DVSS1:62,” &
“TDI:63,” &
“DVDD1:64,” &
“RXD0:65, RXD1:66,” &
“AVDD1:67,” &
“TXP0:68, TXD0:69, TXP1:70, TXD1:71,” &
“AVDD2:72,” &
“XTAL1:73,” &
“AVSS1:74,” &
“XTAL2:75,” &
“AVSS2:79,” &
“DO0:81, DO1:82,” &
“AVDD3:83,” &
“DI0:84, DI1:85, CI0:86, CI1:87,” &
“AVDD4:88,” &
“DVDD2:89,” &
“DXRCV_L:90, EDSEL:91,” &
B-1
Am79C940
AMD
“DVSS2:92,” &
“TXDAT1:93, TXDAT0:94,” &
“DVSSP:95,” &
“STDCLK:96, TXEN_L:97, CLSN:98, RXDAT:99, RXCRS:100);
constant PLCC_PACKAGE : PIN_MAP_STRING :=
“SRDCLK:12, EAM_R_L:13, SRD:14, SF_BD:15, RESET_L:16, SLEEP_L:17,” &
“DVDDP:18,” &
“INTR_L:19, TC_L:20,” &
“DBUS:(39, 38, 36, 35, 34, 33, 32, 31, 30, 29, 28, 26, 25, 24, 23, 21),” &
“DVSSN1:22, DVSSN2:27, DVDDN:37, DVSSN3:39,” &
“EOF_L:41, DTV_L:42, FDS_L:43, BE0_L:44, BE1_L:45, SCLK:46,” &
“TDTREQ_L:47, RDTREQ_L:48, ADD: (53, 52, 51, 50, 49),” &
“R_W_L:54, CS_L:55, RXPOL_L:56, LNKST_L:57,” &
“TDO:58, TMS:59, TCK:60,” &
“DVSS1:61,” &
“TDI:62,” &
“DVDD1:63,” &
“RXD0:64, RXD1:65,” &
“AVDD1:66,” &
“TXP0:67, TXD0:68, TXP1:69, TXD1:70,” &
“AVDD2:71,” &
“XTAL1:72,” &
“AVSS1:73,” &
“XTAL2:74,” &
“AVSS2:75,” &
“DO0:76, DO1:77,” &
“AVDD3:78,” &
“DI0:79, DI1:80, CI0:81, CI1:82,” &
“AVDD4:83,” &
“DVDD2:84,” &
“DXRCV_L:1, EDSEL:2,” &
“DVSS2:3,” &
“TXDAT1:4, TXDAT0:5,” &
“DVSSP:6,” &
“STDCLK:7, TXEN_L:8, CLSN:9, RXDAT:10, RXCRS:11);
attribute TAP_SCAN_IN of TDI : signal is true;
attribute TAP_SCAN_MODE of TMS : signal is true;
attribute TAP_SCAN_OUT of TDO : signal is true;
attribute TAP_SCAN_CLOCK of TCK : signal is (10.0e6, BOTH);
attribute INSTRUCTION_LENGTH of am79c940 : entity is 4;
attribute INSTRUCTION_OPCODE of am79c940 : entity is
“Extest
“Idcode
“Sample
“Tribyp
“Setbyp
(0000),” &
(0001),” &
(0010),” &
(0011),” &
(0100),” &
“Selftst (0101),” &
“Bypass
(0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111)”;
attribute INSTRUCTION_CAPTURE of am79c940 : entity is “0001”;
attribute INSTRUCTION_DISABLE of am79c940 : entity is “Tribyp”;
B-2
Am79C940
AMD
attribute INSTRUCTION_PRIVATE of am79c940 : entity is “Selftst”;
attribute IDCODE_REGISTER of am79c940 : entity is
“0000” &
– 4 bit version
“1001010000000000” & – 16 bit part number
”00000000001” & – 11 bit manufacturer
“1”;
– mandatory LSB
attribute REGISTER_ACCESS of am79c940 : entity is
“Boundary (Extest, Sample, Selftst),” &
“Bypass (Bypass, Tribyp, Setbyp),” &
“Idcode (Idcode)”;
attribute BOUNDARY_CELL of am79c940 : entity is “BC_1,BC_4”;
attribute BOUNDARY_LENGTH of am79c940 : entity is 99
– num cell port
“98 (BC_1,
“97 (BC_1,
“96 (BC_1,
“95 (BC_1,
“94 (BC_1,
“93 (BC_1,
“92 (BC_1,
“91 (BC_1,
“90 (BC_1,
“89 (BC_1,
“88 (BC_1,
“87 (BC_1,
“86 (BC_1,
“85 (BC_1,
“84 (BC_1,
“83 (BC_1,
“82 (BC_1,
“81 (BC_1,
“80 (BC_1,
“79 (BC_1,
“78 (BC_1,
“77 (BC_1,
“76 (BC_1,
“75 (BC_1,
“74 (BC_1,
“73 (BC_1,
“72 (BC_1,
“71 (BC_1,
“70 (BC_1,
“69 (BC_1,
“68 (BC_1,
“67 (BC_1,
“66 (BC_1,
“65 (BC_1,
“64 (BC_1,
“63 (BC_1,
“62 (BC_1,
function
internal,
internal,
safe (ccell
disval
rslt)
*,
*,
*,
*,
*,
*,
*,
*,
0),” &
0),” &
0),” &
0),” &
0),” &
0),” &
0),” &
0),” &
0),” &
X,
– COL_SQL
– AUI_NSQ
– XMTD
– AUIEN
– TXD0L
– TXP0L
– TXEN
internal,
internal,
internal,
internal,
internal,
internal,
internal,
output3,
control,
– PSQ_O xor FIXPOL
– CLK20
*,
DXRCV_L,
*,
88,
0,
Z),” &
0),” &
– TRI PWDNBAR
1),” &
1),” &
EDSEL,
TXDAT1,
TXDAT1,
TXDAT0,
*,
input,
input,
output3,
output3,
X,
X,
0),” &
83,
83,
0,
0,
Z),” &
Z),” &
control,
– TRI TXDAT+/TXDAT–
0),” &
STDCLK,
STDCLK,
*,
input,
output3,
control,
X,
0),” &
80,
0,
Z),” &
– TRI STDCLK
0),” &
TXEN_L,
TXEN_L,
*,
input,
output3,
control,
X,
0),” &
77,
0,
Z),” &
– TRI TXEN_L
CLSN,
CLSN,
*,
RXDAT,
RXDAT,
*,
RXCRS,
RXCRS,
*,
input,
output3,
control,
input,
output3,
control, 0),” &
input,
output3,
control,
0),” &
74,
X,
0,
Z),” &
0),” &
– TRI CLSN
0),” &
X,
X,
X,
71,
0,
Z),” &
Z),” &
Z),” &
– TRI RXDAT
0),” &
68,
0,
0),” &
– TRI RXCRS
0),” &
SRDCLK,
SRDCLK,
*,
input,
output3,
control,
input,
output3, X,
65,
0,
0),” &
– TRI SRDCLK
0),” &
EAM_R,
SRD,
SF_BD,
61,
X,
0,
61,
Z),” &
0,
output3,
Z),” &
Am79C940
B-3
AMD
“61 (BC_1,
“60 (BC_1,
“59 (BC_1,
“58 (BC_1,
“57 (BC_1,
“56 (BC_1,
“55 (BC_1,
“54 (BC_1,
“53 (BC_1,
“52 (BC_1,
“51 (BC_1,
“50 (BC_1,
“49 (BC_1,
“48 (BC_1,
“47 (BC_1,
“46 (BC_1,
“45 (BC_1,
“44 (BC_1,
“43 (BC_1,
“42 (BC_1,
“41 (BC_1,
“40 (BC_1,
“39 (BC_1,
“38 (BC_1,
“37 (BC_1,
“36 (BC_1,
“35 (BC_1, *,
“34 (BC_1,
“33 (BC_1,
“32 (BC_1,
“31 (BC_1,
“30 (BC_1,
“29 (BC_1,
“28 (BC_1,
“27 (BC_1,
“26 (BC_1,
“25 (BC_1,
“24 (BC_1,
“23 (BC_1,
“22 (BC_1,
“21 (BC_1,
“20 (BC_1,
“19 (BC_1,
“18 (BC_1,
“17 (BC_1,
“16 (BC_1,
“15 (BC_1,
“14 (BC_1,
“13 (BC_4,
“12 (BC_1,
“11 (BC_1,
“10 (BC_1,
“9 (BC_1,
*,
control,
input,
input,
output3,
control,
input,
input,
output3,
input,
output3,
input,
output3,
input,
output3,
input,
output3,
input,
output3,
input,
output3,
input,
output3,
input,
output3,
input,
0),” &
0),” &
– TRI SF_BD/SRD
RESET_L,
SLEEP_L,
INTR_L,
*,
1),” &
1),” &
1,
57,
0, Weak1),” &
– TRI INTR_L
TC_L,
1),” &
0),” &
35,
0),” &
35,
0),” &
35,
0),” &
35,
0),” &
35,
0),” &
35,
0),” &
35,
0),” &
35,
DBUS(0),
DBUS(0),
DBUS(1),
DBUS(1),
DBUS(2),
DBUS(2),
DBUS(3),
DBUS(3),
DBUS(4),
DBUS(4),
DBUS(5),
DBUS(5),
DBUS(6),
DBUS(6),
DBUS(7),
DBUS(7),
DBUS(8),
DBUS(8),
DBUS(9),
DBUS(9),
X,
X,
X,
X,
X,
X,
X,
X,
X,
X,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
Z); &
Z); &
Z); &
Z); &
Z); &
Z); &
Z); &
Z); &
Z); &
Z); &
0),” &
35,
0),” &
35,
output3,
control,
0),” &
– TRI DBUS(9:0)
0),” &
DBUS(10),
DBUS(10),
DBUS(11),
DBUS(11),
DBUS(12),
DBUS(12),
DBUS(13),
DBUS(13),
DBUS(14),
DBUS(14),
DBUS(15),
DBUS(15),
*,
EOF_L,
EOF_L,
*,
DTV_L,
*,
FDS_L,
BE0_L,
BE1_L,
input,
output3,
input,
output3,
input,
output3,
input,
output3,
input,
output3,
input,
output3,
control,
X,
X,
X,
X,
X,
22,
0),” &
22,
0),” &
22,
0),” &
22,
0,
0,
0,
0,
0,
0,
Z); &
Z); &
Z); &
Z); &
Z); &
Z); &
0),” &
22,
0),” &
22,
X,
0),” &
– TRI DBUS(15:10)
1),” &
input,
output3,
control, 0),” &
output3,
control, 0),” &
X,
X,
19,
– TRI EOF_L
17, 0,
0,
Z); &
Z); &
– TRI DTV_L
1),” &
1),” &
input,
input,
input,
1),” &
SCLK,
clock,
1),” &
10,
TDTREQ_L,
RDTREQ_L,
*,
output3,
output3,
control,
X,
0,
0,
Z); &
Z); &
X,
10,
0),” &
– TRI TDTREQ_L/RDTREQ_L
0),” &
ADD(0),
input,
B-4
Am79C940
AMD
“8 (BC_1,
“7 (BC_1,
“6 (BC_1,
“5 (BC_1,
“4 (BC_1,
“3 (BC_1,
“2 (BC_1,
“1 (BC_1,
“0 (BC_1,
ADD(1),
ADD(2),
ADD(3),
ADD(4),
R_W_L,
CS_L,
RXPOL_L,
LNKST_L,
*,
input,
input,
input,
input,
input,
0),” &
0),” &
0),” &
0),” &
1),” &
input,
1),” &
0,
output3,
output3,
control,
X,
X,
0, Weak1),” &
0, Weak1),” &
0,
–
0)”;
TRI RXPOL_L/LNKST_L
end am79c940
Am79C940
B-5
相关型号：
AM79C961/AM79C961A
Using the Am79C961/Am79C961A (PCnet-ISA+/PCnet-ISA II) Survival Guide? 134KB (PDF)
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