74VCXH16244MTDX [ETC]
BUFFER/DRIVER|QUAD|4-BIT|VCX-CMOS|TSSOP|48PIN|PLASTIC ;
| 型号： | 74VCXH16244MTDX |
| 厂家： | 
ETC |
| 描述： | BUFFER/DRIVER|QUAD|4-BIT|VCX-CMOS|TSSOP|48PIN|PLASTIC 逻辑集成电路 光电二极管 驱动 |
| 文件： | 总10页 (文件大小：143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1999
Revised March 2002
74VCXH16244
Low Voltage 16-Bit Buffer/Line Driver with Bushold
General Description
The VCXH16244 contains sixteen non-inverting buffers
with 3-STATE outputs to be employed as a memory and
Features
■ 1.4V to 3.6V VCC supply operation
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
■ 3.6V tolerant control inputs and outputs
■ Bushold on data inputs eliminating the need for external
pull-up/pull-down resistors
The VCXH16244 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
■ tPD
2.5 ns max for 3.0V to 3.6V VCC
The 74VCXH16244 is designed for low voltage (1.4V to
3.6V) VCC applications with output capability up to 3.6V.
■ Static Drive (IOH/IOL
)
±24 mA @ 3.0V VCC
The 74VCXH16244 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
■ Uses patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 300 mA
■ ESD performance:
Human body model > 2000V
Machine model > 200V
■ Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Ordering Code:
Order Number
Package Number
Package Description
74VCXH16244GX
(Note 1)
BGA54A
(Preliminary)
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
[TAPE and REEL]
74VCXH16244MTD
(Note 2)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1: BGA package available in Tape and Reel only.
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
© 2002 Fairchild Semiconductor Corporation
DS500230
www.fairchildsemi.com
Connection Diagrams
Pin Descriptions
Pin Assignment for TSSOP
Pin Names
Description
OEn
Output Enable Input (Active LOW)
Bushold Inputs
I0–I15
O0–O15
NC
Outputs
No Connect
FBGA Pin Assignments
1
2
3
4
5
6
A
B
C
D
E
F
O0
O2
NC
O1
OE1
NC
OE2
NC
NC
I1
I0
I2
O4
O3
VCC
GND
GND
GND
VCC
NC
VCC
GND
GND
GND
VCC
NC
I3
I4
O6
O5
I5
I6
O8
O7
I7
I8
O10
O12
O14
O9
I9
I10
I12
I14
G
H
O11
O13
I11
I13
J
O15
NC
OE4
OE3
NC
I15
Truth Tables
Inputs
OE1
Outputs
O0–O3
I0–I3
L
L
L
H
X
L
H
Z
Pin Assignment for FBGA
H
Inputs
OE2
Outputs
O4-O7
I4-I7
L
L
L
H
X
L
H
Z
H
Inputs
OE3
Outputs
O8–O11
I8-I11
(Top Thru View)
L
L
L
H
X
L
H
Z
H
Inputs
OE4
Outputs
O12-O15
I12-I15
L
L
L
H
X
L
H
Z
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
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2
Functional Description
The 74VCXH16244 contains sixteen non-inverting buffers
with 3-STATE outputs. The device is nibble (4 bits) con-
trolled with each nibble functioning identically, but indepen-
dent of each other. The control pins may be shorted
together to obtain full 16-bit operation.The 3-STATE out-
puts are controlled by an Output Enable (OEn) input. When
OEn is LOW, the outputs are in the 2-state mode. When
OEn is HIGH, the standard outputs are in the high imped-
ance mode but this does not interfere with entering new
data into the inputs.
Logic Diagram
3
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Absolute Maximum Ratings(Note 3)
Recommended Operating
Conditions (Note 5)
Supply Voltage (VCC
)
−0.5V to +4.6V
−0.5V to +4.6V
DC Input Voltage (VI)
Power Supply
Output Voltage (VO)
Operating
1.4V to 3.6V
Outputs 3-STATED
−0.5V to +4.6V
−0.5V to VCC +0.5V
−50 mA
Input Voltage
−0.3V to +3.6V
Outputs Active (Note 4)
DC Input Diode Current (IIK) VI < 0V
Output Voltage (VO)
Output in Active States
Output in 3-STATE
Output Current in IOH/IOL
0V to VCC
DC Output Diode Current (IOK
)
0.0V to 3.6V
V
V
O < 0V
−50 mA
+50 mA
O > VCC
V
V
V
V
CC = 3.0V to 3.6V
CC = 2.3V to 2.7V
CC = 1.65V to 2.3V
CC = 1.4V to 1.6V
±24 mA
±18 mA
DC Output Source/Sink Current
(IOH/IOL
)
±50 mA
±6 mA
DC VCC or GND Current per
Supply Pin (ICC or GND)
±2 mA
±100 mA
Free Air Operating Temperature (TA)
−40°C to +85°C
Storage Temperature Range (TSTG
)
−65°C to +150°C
Minimum Input Edge Rate (∆t/∆V)
V
IN = 0.8V to 2.0V, VCC = 3.0V
10 ns/V
Note 3: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
Note 4: IO Absolute Maximum Rating must be observed.
Note 5: Floating or unused control inputs must be held HIGH or LOW.
DC Electrical Characteristics
VCC
Symbol
VIH
Parameter
HIGH Level Input Voltage
Conditions
Min
Max
Units
(V)
2.7 - 3.6
2.3 - 2.7
2.0
1.6
V
1.65 - 2.3 0.65 x VCC
1.4 - 1.6
2.7 - 3.6
2.3 - 2.7
1.65 - 2.3
1.4 - 1.6
2.7 - 3.6
2.7
0.65 x VCC
VIL
LOW Level Input Voltage
HIGH Level Output Voltage
0.8
0.7
V
0.35 x VCC
0.35 x VCC
VOH
I
OH = −100 µA
OH = −12 mA
OH = −18 mA
OH = −24 mA
OH = −100 µA
OH = −6 mA
OH = −12 mA
OH = −18 mA
OH = −100 µA
OH = −6 mA
OH = −100 µA
OH = −2 mA
VCC - 0.2
2.2
I
I
3.0
2.4
I
3.0
2.2
I
2.3 - 2.7
2.3
VCC - 0.2
2.0
I
V
I
2.3
1.8
I
2.3
1.7
I
1.65 - 2.3
1.65
VCC - 0.2
1.25
I
I
1.4 - 1.6
1.4
VCC - 0.2
1.05
I
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4
DC Electrical Characteristics (Continued)
VCC
Symbol
VOL
Parameter
Conditions
OL = 100 µA
Min
Max
Units
(V)
2.7 - 3.6
2.7
LOW Level Output Voltage
I
I
I
I
I
I
I
I
I
I
I
0.2
0.4
OL = 12 mA
OL = 18 mA
OL = 24 mA
OL = 100 µA
OL = 12 mA
OL = 18 mA
OL = 100 µA
OL = 6 mA
3.0
0.4
3.0
0.55
0.2
2.3 - 2.7
2.3
0.4
V
2.3
0.6
1.65 - 2.3
1.65
1.4 - 1.6
1.4
0.2
0.3
OL = 100 µA
OL = 2 mA
0.2
0.35
±5.0
±5.0
II
Input Leakage Current
Control Pins
Data Pins
0 ≤ VI ≤ 3.6V
1.4 - 3.6
1.4 - 3.6
3.0
µA
µA
VI = VCC or GND
II(HOLD)
Bushold Input Minimum
Drive Hold Current
VIN = 0.8V
VIN = 2.0V
VIN = 0.7V
VIN = 1.6V
VIN = 0.57V
VIN = 1.07V
75
−75
45
3.0
2.3
µA
2.3
−45
25
1.65
1.65
3.6
−25
450
−450
300
−300
200
−200
II(OD)
Bushold Input Over-Drive
Current to Change State
(Note 6)
(Note 7)
3.6
(Note 6)
2.7
µA
µA
(Note 7)
2.7
(Note 6)
1.95
1.95
(Note 7)
IOZ
3-STATE Output Leakage
0 ≤ VO ≤ 3.6V
VI = VIH or VIL
0 ≤ (VO) ≤ 3.6V
VI = VCC or GND
2.7 - 3.6
±10
IOFF
ICC
Power-OFF Leakage Current
Quiescent Supply Current
0
10
20
µA
µA
µA
µA
2.7 - 3.6
2.7 - 3.6
2.7 - 3.6
V
CC ≤ (VO) ≤ 3.6V (Note 8)
IH = VCC − 0.6V
±20
750
∆ICC
Increase in ICC per Input
V
Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 8: Outputs disabled or 3-STATE only.
5
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AC Electrical Characteristics (Note 9)
VCC
TA = −40°C to +85°C
Figure
Symbol
Parameter
Propagation Delay
Conditions
Units
(V)
Min
0.8
1.0
1.5
Max
2.5
Number
tPHL
C
L = 30 pF, RL = 500Ω
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
Figures
1, 2
tPLH
3.0
ns
6.0
Figures
5, 6
C
L = 15 pF, RL = 2 kΩ
L = 30 pF, RL = 500Ω
1.5 ± 0.1
1.0
12.0
tPZL
tPZH
Output Enable Time
Output Disable Time
C
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
0.8
1.0
1.5
3.5
4.1
8.2
Figures
1, 3, 4
ns
Figures
5, 7, 8
C
L = 15 pF, RL = 2 kΩ
L = 30 pF, RL = 500Ω
1.5 ± 0.1
1.0
16.4
tPLZ
tPHZ
C
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
0.8
1.0
1.5
3.5
3.8
6.8
Figures
1, 3, 4
ns
ns
Figures
5, 7, 8
C
L = 15 pF, RL = 2 kΩ
L = 30 pF, RL = 500Ω
1.5 ± 0.1
1.0
13.6
tOSHL
tOSLH
Output to Output Skew
(Note 10)
C
3.3 ± 0.3
2.5 ± 0.2
1.8 ± 0.15
1.5 ± 0.1
0.5
0.5
0.75
1.5
CL = 15 pF, RL = 2 kΩ
Note 9: For CL = 50PF, add approximately 300 ps to the AC maximum specification.
Note 10: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Dynamic Switching Characteristics
VCC
T
A = +25°C
Symbol
VOLP
Parameter
Conditions
Units
(V)
1.8
2.5
3.3
1.8
2.5
3.3
1.8
2.5
3.3
Typical
0.25
0.6
Quiet Output Dynamic Peak VOL
C
C
C
L = 30 pF, VIH = VCC, VIL = 0V
V
0.8
VOLV
Quiet Output Dynamic Valley VOL
Quiet Output Dynamic Valley VOH
L = 30 pF, VIH = VCC, VIL = 0V
L = 30 pF, VIH = VCC, VIL = 0V
−0.25
−0.6
−0.8
1.5
V
V
VOHV
1.9
2.2
Capacitance
T
A = +25°C
Symbol
Parameter
Conditions
CC = 1.8, 2.5V or 3.3V, VI = 0V or VCC
Units
Typical
CIN
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
V
6
7
pF
pF
pF
COUT
CPD
VI = 0V or VCC, VCC = 1.8V, 2.5V or 3.3V
VI = 0V or VCC, f = 10 MHz, VCC = 1.8V, 2.5V or 3.3V
20
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6
AC Loading and Waveforms (V 3.3V ± 0.3V to 1.8V ± 0.15V)
CC
TEST
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
6V at VCC = 3.3 ± 0.3V;
V
CC x 2 at VCC = 2.5 ± 0.2V; 1.8V ± 0.15V
tPZH, tPHZ
GND
FIGURE 1. AC Test Circuit
FIGURE 2. Waveform for Inverting and Non-Inverting Functions
FIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
VCC
Symbol
3.3V ± 0.3V
1.5V
2.5V ± 0.2V
VCC/2
1.8V ± 0.15V
VCC/2
Vmi
Vmo
VX
1.5V
VCC/2
VCC/2
V
OL + 0.3V
V
OL + 0.15V
V
OL + 0.15V
VY
V
OH − 0.3V
V
OH − 0.15V
VOH − 0.15V
7
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AC Loading and Waveforms (V 1.5 ± 0.1V)
CC
TEST
SWITCH
tPLH, tPHL
Open
VCC x 2 at VCC = 1.5 ± 0.1V
GND
tPZL, tPLZ
tPZH, tPHZ
FIGURE 5. AC Test Circuit
FIGURE 6. Waveform for Inverting and Non-Inverting Functions
FIGURE 7. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 8. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
VCC
Symbol
1.5V ± 0.1V
Vmi
Vmo
VX
VCC/2
VCC/2
V
OL + 0.1V
VY
VOH − 0.1V
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8
Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Package Number BGA54A
Preliminary
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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10
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