74VCXH16245 [ONSEMI]
Low-Voltage 1.8/2.5/3.3V 16-Bit Transceiver; 低电压1.8 / 2.5 / 3.3V 16位收发器
| 型号： | 74VCXH16245 |
| 厂家： | 
ONSEMI |
| 描述： | Low-Voltage 1.8/2.5/3.3V 16-Bit Transceiver |
| 文件： | 总8页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74VCXH16245
Low−Voltage 1.8/2.5/3.3V
16−Bit Transceiver
With 3.6 V−Tolerant Inputs and Outputs
(3−State, Non−Inverting)
The 74VCXH16245 is an advanced performance, non−inverting
16−bit transceiver. It is designed for very high−speed, very low−power
operation in 1.8 V, 2.5 V or 3.3 V systems.
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When operating at 2.5 V (or 1.8 V) the part is designed to tolerate
voltages it may encounter on either inputs or outputs when interfacing
to 3.3 V busses. It is guaranteed to be over−voltage tolerant to 3.6 V.
The VCXH16245 is designed with byte control. It can be operated
as two separate octals, or with the controls tied together, as a 16−bit
wide function. The Transmit/Receive (T/Rn) inputs determine the
direction of data flow through the bi−directional transceiver. Transmit
(active−HIGH) enables data from A ports to B ports; Receive
(active−LOW) enables data from B to A ports. The Output Enable
inputs (OEn), when HIGH, disable both A and B ports by placing them
in a HIGH Z condition. The data inputs include active bushold
circuitry, eliminating the need for external pull−up resistors to hold
unused or floating inputs at a valid logic state.
TSSOP−48
DT SUFFIX
CASE 1201
48
1
MARKING DIAGRAM
48
VCXH16245
AWLYYWW
Features
• Designed for Low Voltage Operation: V = 1.65−3.6 V
CC
1
• 3.6 V Tolerant Inputs and Outputs
• High Speed Operation: 2.5 ns max for 3.0 to 3.6 V
3.0 ns max for 2.3 to 2.7 V
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
6.0 ns max for 1.65 to 1.95 V
• Static Drive: ±24 mA Drive at 3.0 V
±18 mA Drive at 2.3 V
±6 mA Drive at 1.65 V
ORDERING INFORMATION
• Supports Live Insertion and Withdrawal
• Includes Active Bushold to Hold Unused or Floating Inputs at a Valid
†
Device
Package
Shipping
39 / Rail
Logic State
74VCXH16245DT
74VCXH16245DTR
TSSOP
*
• I
Specification Guarantees High Impedance When V = 0 V
CC
OFF
TSSOP 2500/Tape & Reel
• Near Zero Static Supply Current in All Three Logic States (20 mA)
Substantially Reduces System Power Requirements
74VCXH16245DTRG TSSOP 2500/Tape & Reel
(Pb−Free)
• Latchup Performance Exceeds ±250 mA @ 125°C
• ESD Performance: Human Body Model >2000 V;
Machine Model >200 V
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
• Pb−Free Package is Available*
*NOTE: To ensure the outputs activate in the 3−state condition,
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
the output enable pins should be connected to V through a
CC
pull−up resistor. The value of the resistor is determined by the
current sinking capability of the output connected to the OE pin.
Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
May, 2004 − Rev. 3
74VCXH16245/D
74VCXH16245
1
24
T/R1
T/R2
T/R1
B0
1
2
3
4
5
6
7
8
9
48 OE1
47 A0
46 A1
45 GND
44 A2
43 A3
48
25
OE1
OE2
B1
GND
B2
A0:7
B0:7
A8:15
B8:15
B3
V
CC
42 V
CC
B4
B5
41 A4
40 A5
39 GND
38 A6
37 A7
36 A8
35 A9
34 GND
33 A10
32 A11
One of Eight
GND 10
B6 11
Figure 2. Logic Diagram
B7 12
B8 13
1
B9 14
EN1
EN2
EN3
EN4
T/R1
OE1
OE2
T/R2
48
25
24
GND 15
B10 16
B11 17
2
3
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1
1
1
2
B0
A0
A1
V
18
31 V
CC
CC
B1
5
B12 19
B13 20
GND 21
B14 22
B15 23
T/R2 24
30 A12
29 A13
28 GND
27 A14
26 A15
25 OE2
B2
A2
6
B3
B4
A3
A4
8
9
B5
A5
11
12
13
14
16
17
19
20
22
23
B6
A6
1
1
3
4
B7
B8
A7
A8
B9
A9
B10
B11
B12
B13
B14
B15
A10
A11
A12
A13
A14
A15
Figure 1. 48−Lead Pinout
(Top View)
PIN NAMES
Pins
Function
Figure 3. IEC Logic Diagram
OEn
Output Enable Inputs
T/Rn
Transmit/Receive Inputs
A0−A15
B0−B15
Side A Inputs or 3−State Outputs
Side B Inputs or 3−State Outputs
Inputs
Inputs
Outputs
Outputs
OE1
T/R1
L
OE2
L
T/R2
L
L
L
Bus B0:7 Data to Bus A0:7
Bus A0:7 Data to Bus B0:7
High Z State on A0:7, B0:7
Bus B8:15 Data to Bus A8:15
Bus A8:15 Data to Bus B8:15
High Z State on A8:15, B8:15
H
L
H
H
X
H
X
H = High Voltage Level; L = Low Voltage Level; X = High or Low Voltage Level and Transitions Are Acceptable
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2
74VCXH16245
ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
Value
Condition
Unit
V
V
V
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
−0.5 to +4.6
CC
−0.5 ≤ V ≤ +4.6
V
I
I
−0.5 ≤ V ≤ +4.6
Output in 3−State
V
O
O
−0.5 ≤ V ≤ V + 0.5
Note 1.; Outputs Active
V
O
CC
I
I
DC Input Diode Current
DC Output Diode Current
−50
V < GND
mA
mA
mA
mA
mA
mA
°C
IK
I
−50
+50
V < GND
O
OK
V
O
> V
CC
I
I
I
DC Output Source/Sink Current
DC Supply Current Per Supply Pin
DC Ground Current Per Ground Pin
Storage Temperature Range
±50
O
±100
±100
CC
GND
T
−65 to +150
STG
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute−maximum−rated conditions
is not implied.
1. I absolute maximum rating must be observed.
O
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Typ
Max
Unit
V
CC
Supply Voltage
Operating
Data Retention Only
1.65
1.2
3.3
3.3
3.6
3.6
V
V
V
Input Voltage
−0.3
3.6
V
V
I
Output Voltage
(Active State)
(3−State)
0
0
V
CC
O
3.6
−24
24
I
I
I
I
I
I
HIGH Level Output Current, V = 3.0 V − 3.6 V
mA
mA
mA
mA
mA
mA
°C
OH
CC
LOW Level Output Current, V = 3.0 V − 3.6 V
OL
OH
OL
OH
OL
CC
HIGH Level Output Current, V = 2.3 V − 2.7 V
−18
18
CC
LOW Level Output Current, V = 2.3 V − 2.7 V
CC
HIGH Level Output Current, V = 1.65 − 1.95 V
−6
CC
LOW Level Output Current, V = 1.65 − 1.95 V
6
CC
T
A
Operating Free−Air Temperature
−40
0
+85
10
Dt/DV
Input Transition Rise or Fall Rate, V from 0.8 V to 2.0 V, V = 3.0 V
ns/V
IN
CC
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3
74VCXH16245
DC ELECTRICAL CHARACTERISTICS
T
A
= −40°C to +85°C
Symbol
Characteristic
Condition
Min
0.65 x V
1.6
Max
Unit
V
IH
HIGH Level Input Voltage (Note 2.)
V
1.65 V ≤ V < 2.3 V
CC
CC
2.3 V ≤ V ≤ 2.7 V
CC
2.7 V < V ≤ 3.6 V
2.0
CC
V
LOW Level Input Voltage (Note 2.)
HIGH Level Output Voltage
V
V
1.65 V ≤ V < 2.3 V
0.35 x V
0.7
IL
CC
CC
2.3 V ≤ V ≤ 2.7 V
CC
2.7 V < V ≤ 3.6 V
0.8
CC
V
OH
1.65 V ≤ V ≤ 3.6 V; I = −100mA
V
CC
− 0.2
CC
OH
V
CC
= 1.65 V; I = −6mA
1.25
OH
V
= 2.3 V; I = −6mA
2.0
1.8
1.7
2.2
2.4
2.2
CC
CC
CC
CC
CC
CC
OH
V
V
V
V
V
= 2.3 V; I = −12mA
OH
= 2.3 V; I = −18mA
OH
= 2.7 V; I = −12mA
OH
= 3.0 V; I = −18mA
OH
= 3.0 V; I = −24mA
OH
V
LOW Level Output Voltage
1.65 V ≤ V ≤ 3.6 V; I = 100mA
0.2
0.3
V
OL
CC
OL
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V; I = 6mA
OL
= 2.3 V; I = 12mA
0.4
OL
= 2.3 V; I = 18mA
0.6
OL
= 2.7 V; I = 12mA
0.4
OL
= 3.0 V; I = 18mA
0.4
OL
= 3.0 V; I = 24mA
0.55
±5.0
OL
I
I
Input Leakage Current
1.65 V ≤ V ≤ 3.6 V; 0V ≤ V ≤ 3.6 V
mA
mA
I
CC
I
Minimum Bushold Input Current
V
CC
V
CC
V
CC
V
CC
= 3.0 V, V = 0.8V
75
−75
45
I(HOLD)
I (OD)
OZ
IN
= 3.0 V, V = 2.0V
IN
= 2.3 V, V = 0.7V
IN
= 2.3 V, V = 1.6V
−45
25
IN
V
CC
= 1.65 V, V = 0.57V
IN
V
CC
= 1.65 V, V = 1.07V
−25
450
−450
300
−300
200
−200
IN
I
Minimum Bushold Over−Drive
Current Needed to Change State
mA
V
CC
= 3.6 V, (Note 3.)
V
V
V
= 3.6 V, (Note 4.)
= 2.7 V, (Note 3.)
= 2.7 V, (Note 4.)
= 1.95 V, (Note 3.)
= 1.95 V, (Note 4.)
CC
CC
CC
V
CC
V
CC
I
3−State Output Current
1.65 V ≤ V ≤ 3.6 V; 0 V ≤ V ≤ 3.6 V;
±10
mA
CC
O
V = V or V
IL
I
IH
I
I
Power−Off Leakage Current
V
= 0 V; V or V = 3.6 V
10
20
mA
mA
mA
mA
OFF
CC
I
O
Quiescent Supply Current (Note 5.)
1.65 V ≤ V ≤ 3.6 V; V = GND or V
CC
CC
CC
I
1.65 V ≤ V ≤ 3.6 V; 3.6 V ≤ V , V ≤ 3.6 V
±20
750
CC
I
O
DI
Increase in I per Input
2.7 V < V ≤ 3.6 V; V = V − 0.6 V
CC IH CC
CC
CC
2. These values of V are used to test DC electrical characteristics only.
I
3. An external driver must source at least the specified current to switch from LOW−to−HIGH.
4. An external driver must source at least the specified current to switch from HIGH−to−LOW.
5. Outputs disabled or 3−state only.
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4
74VCXH16245
AC CHARACTERISTICS (Note 6.; tR = tF = 2.0ns; CL = 30pF; RL = 500W)
Limits
T
A
= −40°C to +85°C
V
CC
= 3.0 V to 3.6 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 1.65 to1.95 V
Symbol
Parameter
Waveform
Min
Max
Min
Max
Min
1.5
1.5
Max
Unit
t
t
Propagation Delay
Input to Output
1
0.8
0.8
2.5
2.5
1.0
1.0
3.0
3.0
6.0
6.0
ns
PLH
PHL
t
t
Output Enable Time to
High and Low Level
2
2
0.8
0.8
3.8
3.8
1.0
1.0
4.9
4.9
1.5
1.5
9.3
9.3
ns
ns
ns
PZH
PZL
t
t
Output Disable Time From
High and Low Level
0.8
0.8
3.7
3.7
1.0
1.0
4.2
4.2
1.5
1.5
7.6
7.6
PHZ
PLZ
t
t
Output−to−Output Skew
(Note 7.)
0.5
0.5
0.5
0.5
0.75
0.75
OSHL
OSLH
6. For C = 50pF, add approximately 300ps to the AC maximum specification.
L
7. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (t
guaranteed by design.
) or LOW−to−HIGH (t
); parameter
OSHL
OSLH
DYNAMIC SWITCHING CHARACTERISTICS
T
A
= +25°C
Symbol
Characteristic
Dynamic LOW Peak Voltage
(Note 8.)
Condition
= 1.8 V, C = 30pF, V = V , V = 0 V
Typ
Unit
V
OLP
V
OLV
V
OHV
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
0.25
0.6
V
L
IH
CC
IL
= 2.5 V, C = 30pF, V = V , V = 0 V
L
IH
CC
IL
= 3.3 V, C = 30pF, V = V , V = 0 V
0.8
L
IH
CC
IL
Dynamic LOW Valley Voltage
(Note 8.)
= 1.8 V, C = 30pF, V = V , V = 0 V
−0.25
−0.6
−0.8
1.5
V
V
L
IH
CC
IL
= 2.5 V, C = 30pF, V = V , V = 0 V
L
IH
CC
IL
= 3.3 V, C = 30pF, V = V , V = 0 V
L
IH
CC
IL
Dynamic HIGH Valley Voltage
(Note 9.)
= 1.8 V, C = 30pF, V = V , V = 0 V
L IH CC IL
= 2.5 V, C = 30pF, V = V , V = 0 V
1.9
L
IH
CC
IL
= 3.3 V, C = 30pF, V = V , V = 0 V
2.2
L
IH
CC
IL
8. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is
measured in the LOW state.
9. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is
measured in the HIGH state.
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Input Capacitance
Condition
Note 10.
Typical
Unit
pF
C
C
C
6
7
IN
Output Capacitance
Note 10.
pF
OUT
PD
Power Dissipation Capacitance
Note 10., 10MHz
20
pF
10.V = 1.8, 2.5 or 3.3 V; V = 0 V or V .
CC
CC
I
AC CHARACTERISTICS (tR = tF = 2.0ns; CL = 50pF; RL = 500W)
Limits
= −40°C to +85°C
T
A
V
CC
= 3.0 V to 3.6 V
V
CC
= 2.7 V
Symbol
Parameter
Waveform
Min
1.0
1.0
Max
Min
Max
Unit
t
t
Propagation Delay
Input to Output
3
3.0
3.0
3.6
3.6
ns
ns
ns
ns
PLH
PHL
t
t
Output Enable Time to
High and Low Level
4
4
1.0
1.0
4.4
4.4
5.4
5.4
PZH
PZL
t
t
Output Disable Time From
High and Low Level
1.0
1.0
4.1
4.1
4.6
4.6
PHZ
PLZ
t
t
Output−to−Output Skew
(Note 11.)
0.5
0.5
0.5
0.5
OSHL
OSLH
11. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (t
guaranteed by design.
) or LOW−to−HIGH (t
); parameter
OSHL
OSLH
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5
74VCXH16245
V
IH
Vm
Vm
An, Bn
Bn, An
0V
t
t
PHL
PLH
V
OH
OL
Vm
Vm
V
WAVEFORM 1 − PROPAGATION DELAYS
= t = 2.0ns, 10% to 90%; f = 1MHz; t = 500ns
t
R
F
W
V
IH
Vm
Vm
OEn, T/Rn
0V
t
t
PHZ
PZH
V
OH
Vy
Vm
Vm
An, Bn
An, Bn
≈ 0V
t
t
PLZ
PZL
≈ V
CC
Vx
V
OL
WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES
= t = 2.0ns, 10% to 90%; f = 1MHz; t = 500ns
t
R
F
W
Figure 4. AC Waveforms
V
CC
3.3 V ±0.3 V
2.5V ±0.2 V
1.8 V ±0.15 V
Symbol
V
IH
2.7 V
V
CC
V
CC
V
m
1.5 V
V
CC
/2
V
CC
/2
V
V
+ 0.3 V
− 0.3 V
V
+ 0.15 V
− 0.15 V
V
+ 0.15 V
− 0.15 V
x
OL
OL
OL
V
y
V
OH
V
OH
V
OH
V
CC
6V or V × 2
CC
OPEN
R
L
PULSE
GENERATOR
GND
DUT
R
T
C
L
R
L
TEST
SWITCH
t
t
, t
Open
PLH PHL
, t
6 V at V = 3.3 ±0.3 V;
CC
× 2 at V = 2.5 ±0.2 V; 1.8 V ±0.15 V
PZL PLZ
V
CC
CC
t
, t
GND
PZH PHZ
C = 30pF or equivalent (Includes jig and probe capacitance)
L
R = 500W or equivalent
L
R = Z
of pulse generator (typically 50W)
T
OUT
Figure 5. Test Circuit
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6
74VCXH16245
V
IH
Vm
Vm
An, Bn
Bn, An
0V
t
t
PHL
PLH
V
OH
OL
Vm
Vm
V
WAVEFORM 3 − PROPAGATION DELAYS
= t = 2.0ns, 10% to 90%; f = 1MHz; t = 500ns
t
R
F
W
V
IH
Vm
Vm
OEn, T/Rn
0V
t
t
PHZ
PZH
V
OH
Vy
Vm
Vm
An, Bn
An, Bn
≈ 0V
t
t
PLZ
PZL
≈ V
CC
Vx
V
OL
WAVEFORM 4 − OUTPUT ENABLE AND DISABLE TIMES
= t = 2.0ns, 10% to 90%; f = 1MHz; t = 500ns
t
R
F
W
Figure 6. AC Waveforms
V
CC
3.3V ±0.3 V
2.7 V
Symbol
V
IH
2.7 V
2.7 V
V
m
1.5 V
1.5 V
V
V
+ 0.3 V
− 0.3 V
V
+ 0.3 V
x
OL
OL
V
y
V
OH
V
OH
− 0.3 V
V
CC
6V or V × 2
CC
OPEN
GND
R
L
PULSE
GENERATOR
DUT
R
T
C
L
R
L
TEST
SWITCH
t
t
, t
Open
PLH PHL
, t
6 V at V = 3.3 ±0.3V;
CC
× 2 at V = 2.5 ±0.2 V; 1.8 ±0.15 V
PZL PLZ
V
CC
CC
t
, t
GND
PZH PHZ
C = 50pF or equivalent (Includes jig and probe capacitance)
L
R = 500W or equivalent
L
R = Z
of pulse generator (typically 50W)
T
OUT
Figure 7. Test Circuit
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7
74VCXH16245
PACKAGE DIMENSIONS
TSSOP
DT SUFFIX
CASE 1201−01
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
48X K REF
K
K1
M
S
S
V
0.12 (0.005)
T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
J
J1
48
25
SECTION N−N
B
−U−
L
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSIONS A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
1
24
MILLIMETERS
INCHES
DIM MIN
MAX
12.60
6.20 0.236
1.10 −−−
0.15 0.002
0.75 0.020
MIN
0.488
MAX
0.496
0.244
0.043
0.006
0.030
A
B
C
12.40
6.00
−−−
A
−V−
PIN 1
IDENT.
N
D
F
0.05
0.50
M
F
G
H
0.50 BSC
0.0197 BSC
0.37
0.09
0.09
0.17
0.17
7.95
0
−−−
0.015
−−−
0.008
0.006
0.011
0.009
0.325
8
0.25 (0.010)
DETAIL E
J
J1
K
K1
L
M
0.20 0.004
0.16 0.004
0.27 0.007
0.23 0.007
8.25 0.313
D
C
8
0
_
_
_
_
−W−
0.076 (0.003)
DETAIL E
−T−
SEATING
PLANE
H
G
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