74ACTQ273SCX [ETC]
Octal D-Type Flip-Flop ; 八D型触发器\n
| 型号： | 74ACTQ273SCX |
| 厂家： | 
ETC |
| 描述： | Octal D-Type Flip-Flop
|
| 文件： | 总9页 (文件大小：109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1989
Revised August 2001
74ACTQ273
Quiet Series Octal D-Type Flip-Flop
General Description
Features
The ACTQ273 has eight edge-triggered D-type flip-flops
with individual D inputs and Q outputs. The common buff-
ered Clock (CP) and Master Reset (MR) input load and
reset (clear) all flip-flops simultaneously.
■ ICC reduced by 50%
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Guaranteed pin-to-pin skew AC performance
■ Improved latch-up immunity
The register is fully edge-triggered. The state of each D-
type input, one setup time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop’s Q
output.
■ Buffered common clock and asynchronous master reset
■ Outputs source/sink 24 mA
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements.
■ 4 kV minimum ESD immunity
The ACTQ utilizes Fairchild Quiet Series technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series features
GTO output control and undershoot corrector in addition
to a split ground bus for superior performance.
Ordering Code:
Order Number Package Number
Package Description
74ACTQ273SC
74ACTQ273SJ
74ACTQ273MTC
74ACTQ273PC
M20B
M20D
MTC20
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D0–D7
MR
Description
Data Inputs
Master Reset
CP
Clock Pulse Input
Data Outputs
Q0–Q7
FACT , FACT Quiet Series , and GTO are trademarks of Fairchild Semiconductor Corporation.
© 2001 Fairchild Semiconductor Corporation
DS010585
www.fairchildsemi.com
Logic Symbols
IEEE/IEC
Mode Select-Function Table
Inputs
Outputs
Operating Mode
Dn
Qn
MR
CP
Reset (Clear)
Load “1”
L
X
X
H
L
L
H
L
H
H
Load “0”
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.fairchildsemi.com
2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
4.5V to 5.5V
0V to VCC
−20 mA
+20 mA
Input Voltage (VI)
VI = VCC + 0.5V
Output Voltage (VO)
0V to VCC
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
Operating Temperature (TA)
−40°C to +85°C
DC Output Diode Current (IOK
)
Minimum Input Edge Rate ∆V/∆t
V
V
O = −0.5V
−20 mA
+20 mA
V
IN from 0.8V to 2.0V
O = VCC + 0.5V
VCC @ 4.5V, 5.5V
125 mV/ns
DC Output Voltage (VO)
DC Output Source
−0.5V to VCC + 0.5V
or Sink Current (IO)
±50 mA
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
±50 mA
Storage Temperature (TSTG
DC Latch-up Source or
Sink Current
)
−65°C to +150°C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
±300 mA
140°C
Junction Temperature (TJ)
PDIP
DC Electrical Characteristics
VCC
T
A = +25°C
TA = −40°C to +85°C
Symbol
Parameter
Units
Conditions
(V)
4.5
5.5
4.5
5.5
4.5
5.5
Typ
1.5
Guaranteed Limits
VIH
Minimum HIGH Level
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
V
OUT = 0.1V
or VCC − 0.1V
OUT = 0.1V
or VCC − 0.1V
V
V
V
Input Voltage
1.5
VIL
Maximum LOW Level
Input Voltage
1.5
V
1.5
VOH
Minimum HIGH Level
Output Voltage
4.49
5.49
I
OUT = −50 µA
IN = VIL or VIH
V
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
V
I
I
OH = −24 mA
OH = −24 mA (Note 2)
VOL
Maximum LOW Level
Output Voltage
0.001
0.001
I
OUT = 50 µA
0.1
0.1
V
IN = VIL or VIH
4.5
5.5
5.5
5.5
5.5
5.5
5.5
0.36
0.36
±0.1
0.44
0.44
± 1.0
1.5
I
I
OL = 24 mA
OL = 24 mA (Note 2)
IIN
Maximum Input Leakage Current
Maximum ICC/Input
µA
mA
mA
mA
µA
VI = VCC, GND
VI = VCC − 2.1V
ICCT
IOLD
IOHD
ICC
0.6
Minimum Dynamic
75
V
V
V
OLD = 1.65V Max
OHD = 3.85V Min
IN = VCC or GND
Output Current (Note 3)
−75
40.0
Maximum Quiescent Supply Current
Quiet Output
4.0
1.5
VOLP
Figures 1, 2
(Note 4)
5.0
5.0
1.1
V
V
Maximum Dynamic VOL
VOLV
Quiet Output
Figures 1, 2
(Note 4)
−0.6
−1.2
Minimum Dynamic VOL
VIHD
VILD
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
5.0
5.0
1.9
1.2
2.2
0.8
V
V
(Note 5)
(Note 5)
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: Max number of outputs defined as (n). n − 1 Data inputs are driven 0V to 3V; one output @ GND.
Note 5: Max number of Data Inputs (n) switching. (n − 1) Inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (VILD), 0V to thresh-
old (VIHD) f = 1 MHz.
3
www.fairchildsemi.com
AC Electrical Characteristics
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
Symbol
Parameter
C
L = 50 pF
C
Units
(V)
(Note 6)
Min
Typ
Max
Min
fMAX
Maximum Clock
Frequency
5.0
5.0
5.0
5.0
125
189
6.5
7.0
0.5
110
1.5
1.5
MHz
ns
tPLH
tPHL
tPHL
Propagation Delay
CP to Qn
1.5
1.5
8.5
9.0
1.0
9.0
9.5
1.0
Propagation Delay
MR to Qn
ns
tOSHL
,
Output to Output
Skew (Note 7)
ns
tOSLH
Note 6: Voltage Range 5.0 is 5.0V ± 0.5V
Note 7: Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs within the same packaged device.
The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by
design. Not tested.
AC Operating Requirements
VCC
TA = +25°C
TA = −40°C to +85°C
Symbol
Parameter
CL = 50 pF
CL = 50 pF
Units
(V)
(Note 8)
Typ
Guaranteed Minimum
tS
Setup Time, HIGH or LOW
5.0
5.0
5.0
1.0
−0.5
2.0
3.5
3.5
ns
ns
ns
Dn to CP
tH
Hold Time, HIGH or LOW
1.5
4.0
1.5
4.0
Dn to CP
tW
Clock Pulse Width
HIGH or LOW
tW
MR Pulse Width
HIGH or LOW
Recovery Time
MR to CP
5.0
5.0
1.5
0.5
4.0
3.0
4.0
3.0
ns
ns
tW
Note 8: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
pF
V
CC = OPEN
CC = 5.0V
CPD
Power Dissipation Capacitance
40.0
V
www.fairchildsemi.com
4
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
VOLP/VOLV and VOHP/V OHV:
•
Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50Ω coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
•
•
Measure VOLP and VOLV on the quiet output during the
Tektronics Model 7854 Oscilloscope
Procedure:
worst case transition for active and enable. Measure
VOHP and VOHV on the quiet output during the worst
1. Verify Test Fixture Loading: Standard Load 50 pF,
case active and enable transition.
500Ω.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
V
ILD and VIHD:
•
Monitor one of the switching outputs using a 50Ω coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are at the
correct voltage.
•
•
•
First increase the input LOW voltage level, VIL, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measure-
ment.
exceed VIH limits. The input LOW voltage level at which
oscillation occurs is defined as VILD
.
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
Next decrease the input HIGH voltage level, VIH, until
the output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input HIGH voltage level at which
oscillation occurs is defined as VIHD
.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
FIGURE 1. Quiet Output Noise Voltage Waveforms
Note 9: VOHV and VOLP are measured with respect to ground reference.
Note 10: Input pulses have the following characteristics: f = 1 MHz, tr
3 ns, tf = 3 ns, skew < 150 ps.
=
FIGURE 2. Simultaneous Switching Test Circuit
5
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
www.fairchildsemi.com
6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
7
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
www.fairchildsemi.com
8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
9
www.fairchildsemi.com
相关型号：
74ACTQ273SCX_NL
D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20, 0.300 INCH, MS-013, SOIC-20
FAIRCHILD
74ACTQ273SC_NL
D Flip-Flop, ACT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, PDSO20, 0.300 INCH, LEAD FREE, MS-013, SOIC-20
FAIRCHILD
74ACTQ273SJQR
ACT SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, EIAJ, SOIC-20
TI
©2020 ICPDF网 联系我们和版权申明