5962F9466311VYC [ETC]
Controller Miscellaneous - Datasheet Reference ; 控制器杂项 - 数据表参考\n
| 型号： | 5962F9466311VYC |
| 厂家： | 
ETC |
| 描述： | Controller Miscellaneous - Datasheet Reference
|
| 文件： | 总41页 (文件大小：291K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
REVISIONS
LTR
A
DESCRIPTION
DATE (YR-MO-DA)
96-03-13
APPROVED
Add device types 04, 05, and 06. Modify boilerplate to include rad hard
requirements. Editorial changes throughout.
Monica L. Poelking
B
C
Add device types 07, 08, and 09. Update boilerplate. Editorial changes
throughout. – TVN
98-08-27
99-04-28
Monica L. Poelking
Monica L. Poelking
In table I, change IIN limits; add footnote to IDDQ; add tc in power-up master reset
timing section; add footnote to VOS and VDIS. Correct the JTAG timing waveforms.
Change footnote 3/ in table III. – TVN
D
E
Add device types 10 and 11. Editorial changes throughout. - TVN
00-06-27
01-03-13
Monica L. Poelking
Thomas M. Hess
Add notes to memory write and memory read waveforms. Editorial changes
throughout. – TVN
F
Correct dimension L for case outline Y in figure 1. Also, correct footnote 1/ for
radiation exposure connections in figure 6. – TVN
01-07-27
Thomas M. Hess
REV
B
35
D
B
36
D
B
37
B
D
SHEET
REV
38
B
B
F
D
21
F
D
22
D
B
23
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D
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E
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E
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C
28
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B
29
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B
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SHEET
15
16
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REV
19
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D
REV STATUS
OF SHEETS
SHEET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PREPARED BY
Thomas M. Hess
PMIC N/A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216
CHECKED BY
http://www.dscc.dla.mil
STANDARD
MICROCIRCUIT
Thomas M. Hess
APPROVED BY
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
MICROCIRCUIT, DIGITAL, CMOS, SERIAL
MICROCODED MULTI-MODE INTELLIGENT TERMINAL
AND TRANSCEIVER, SILICON
Monica L. Poelking
DRAWING APPROVAL DATE
95-03-31
REVISION LEVEL
SIZE
CAGE CODE
5962-94663
AMSC N/A
A
67268
F
SHEET
1
OF
38
DSCC FORM 2233
APR 97
5962-E538-01
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and
M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the
Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the
PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
H
94663
01
V
X
X
Federal
stock class
designator
\
RHA
designator
(see 1.2.1)
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and
are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
Generic number
69151-LX15
69151-DX
Circuit function
01
02
03
04
05
06
07
08
09
10
11
Serial microcoded multi-mode intelligent terminal with
15-volt transceiver
Serial microcoded multi-mode intelligent terminal with
5-volt transceiver
Serial microcoded multi-mode intelligent terminal with
12-volt transceiver
Enhanced serial microcoded multi-mode intelligent
terminal with 15-volt transceiver radiation hardened
Enhanced serial microcoded multi-mode intelligent
terminal with 5-volt transceiver radiation hardened
Enhanced serial microcoded multi-mode intelligent
terminal with 12-volt transceiver
Enhanced serial microcoded multi-mode intelligent
terminal with 15-volt transceiver
Enhanced serial microcoded multi-mode intelligent
terminal with 5-volt transceiver
69151-LX12
69151-LXE15
69151-DXE
69151-LXE12
69151-LXE15
69151-DXE
69151-LXE12
69151-LXE15
69151-DXE
Enhanced serial microcoded multi-mode intelligent
terminal with 12-volt transceiver
Enhanced serial microcoded multi-mode intelligent
terminal with 15-volt transceiver radiation hardened
Enhanced serial microcoded multi-mode intelligent
terminal with 5-volt transceiver radiation hardened
SIZE
STANDARD
5962-94663
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
D
2
DSCC FORM 2234
APR 97
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
M
Device requirements documentation
Vendor self-certification to the requirements for MIL-STD-883 compliant,
non-JAN class level B microcircuits in accordance with MIL-PRF-38535,
appendix A
Q or V
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
Descriptive designator
Terminals
Package style
X
Y
See figure 1
See figure 1
100
100
Pin grid array 1/
Leaded chip carrier with
nonconductive tier bar
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
1.3 Absolute maximum ratings. 2/
Storage temperature range (TSTG) .................................................................... -65°C to +150°C
Operating case temperature range (TC) ............................................................ -55°C to +125°C
Transceiver supply voltage (VEE):
Device types 01, 03, 04, 06, 07, 09, 10 ......................................................... -22 V dc
Transceiver supply voltage range (VCC):
Device types 02, 05, 08, 11 .......................................................................... -0.3 V dc to +7.0 V dc
Logic supply voltage range (VDD)....................................................................... -0.3 V dc to +7.0 V dc
Input voltage range (VDR):
Device types 01, 03, 04, 06, 07, 09, 10 ......................................................... 42 VP,L-L
Device types 02, 05, 08, 11 .......................................................................... 10 VP,L-L
Maximum power dissipation (PD)....................................................................... 5 W
Logic voltage on any pin range (VI/O)................................................................. -0.3 V dc to VDD + 0.3 V dc
Logic latch-up immunity (ILU)............................................................................. ±150 mA
Logic input current (II) ...................................................................................... ±10 mA
Output current (IO):
Device types 01, 03, 04, 06, 07, 09, 10 ......................................................... 190 mA
Device types 02, 05, 08, 11 .......................................................................... 1000 mA
Maximum junction temperature (TJ) ................................................................. +150°C
Receiver common mode input voltage range (VIC):
Device types 01, 03, 04, 06, 07, 09, 10 ......................................................... -11 V dc to +11 V dc
Device types 02, 05, 08, 11 .......................................................................... -5 V dc to +5 V dc
Lead temperature (soldering, 5 seconds)........................................................... +300°C
Thermal resistance junction-to-case (QJC): 3/
Cases X and Y ............................................................................................. 7°C/W
1/ This package contains 96 terminals on the bottom and 4 terminals on top of the package, see figure 1.
2/ Stress outside the listed absolute maximum rating may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational
sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods
affect device reliability.
3/ Per MIL-STD-883, Method 1012.
SIZE
STANDARD
5962-94663
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
D
3
DSCC FORM 2234
APR 97
1.4 Recommended operating conditions.
Transceiver supply voltage range (VCC):
Device types 01, 03, 04, 06, 07, 09, 10 ......................................................... +4.75 V dc to +5.5 V dc
Device type 02 .............................................................................................. +4.75 V dc to +5.25 V dc
Device types 05, 08, 11 ................................................................................ +4.5 V dc to +5.5 V dc
Logic supply voltage range (VDD) ...................................................................... +4.5 V dc to +5.5 V dc
Transceiver supply voltage range (VEE):
Device types 01, 04, 07, 10 .......................................................................... -15 V dc
Device types 03, 06, 09 ................................................................................ -12 V dc
Receiver differential voltage (VDR):
Device types 01, 03, 04, 06, 07, 09, 10 ......................................................... 40 VP-P
Device types 02, 05, 08, 11 .......................................................................... 8.0 VP-P
Logic dc input voltage range (VIN)...................................................................... 0 V dc to VDD
Receiver common mode input voltage (VIC):
Device types 01, 03, 04, 06, 07, 09, 10 ......................................................... ±10 V dc
Device types 02, 05, 08, 11 .......................................................................... ±5.0 V dc
Driver peak output current (IO):
Device types 01, 03, 04, 06, 07, 09, 10 ......................................................... 180 mA
Device types 02, 05, 08, 11 .......................................................................... 700 mA
Serial data rate range (SD) ............................................................................... 0 to 1 MHz
Clock duty cycle (DC) ....................................................................................... 50 ± 5%
Case operating temperature range (TC) ............................................................ -55°C to +125°C
Operating frequency (FIN) ................................................................................. 24 MHz ± 0.01%
Radiation features:
Total dose
Device type 04, 10 .................................................................................. £ 100k Rads (Si)
Device type 05 ........................................................................................ £ 1M Rads (Si)
Device type 11 ........................................................................................ £ 300k Rads (Si)
Single event phenomenon (SEP) effective
linear energy threshold, no upsets............................................................ 1/
Neutron fluence (TM 1017) ........................................................................... 1/
1.5 Digital logic testing for device classes Q and V.
Fault coverage measurement of manufacturing
logic tests (MIL-STD-883, test method 5012) ................................................ 95.12 percent
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a
part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed
in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in
the solicitation.
1/ Values will be added when they become available. Rad hard devices have not yet been tested for neutron or SEP.
SIZE
STANDARD
5962-94663
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
D
4
DSCC FORM 2234
APR 97
SPECIFICATION
DEPARTMENT OF DEFENSE
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
STANDARDS
DEPARTMENT OF DEFENSE
MIL-STD-883
-
Test Methods Standard Microcircuits.
MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.
HANDBOOKS
DEPARTMENT OF DEFENSE
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization
Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of the documents which are DOD adopted are those listed in the issue of the DODISS
cited in the solicitation. Unless otherwise specified, the issues of documents not listed in the DODISS are the issues of the
documents cited in the solicitation.
INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS (IEEE)
IEEE Standard 1149.1 - IEEE Standard Test Access Port and Boundary Scan Architecture.
(Applications for copies should be addressed to the Institute of Electrical and Electronics Engineers, 445 Hoes Lane,
Piscataway, NJ 08854-4150.)
(Non-Government standards and other publications are normally available from the organizations that prepare or distribute
the documents. These documents may also be available in or through libraries or other informational services.)
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as
specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class
M.
SIZE
STANDARD
5962-94663
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
F
5
DSCC FORM 2234
APR 97
3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 and figure 1 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.
3.2.3 Block diagram. The block diagram shall be as specified on figure 3.
3.2.4 Boundary scan instruction codes. The boundary scan instruction codes shall be as specified on figure 4.
3.2.5 Timing waveforms. The timing waveforms shall be as specified on figure 5.
3.2.6 Radiation exposure connections. The radiation exposure connections shall be as specified on figure 6.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the
full case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The
electrical tests for each subgroup are defined in table IA.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not feasible due to space
limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the
RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535.
Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required
in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate
of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103
(see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for
this drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of
MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or
for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2
herein) involving devices acquired to this drawing is required for any change as defined in MIL-PRF-38535, appendix A.
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain
the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number H (see MIL-PRF-38535, appendix A).
3.11 IEEE 1149.1 compliance. These devices shall be compliant to IEEE 1149.1.
SIZE
STANDARD
5962-94663
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
D
6
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics.
Test
Symbol
Test conditions 1/
-55°C £ TC £ +125°C
4.5 V £ VDD £ 5.5 V
Device
type
Group A
subgroups
Limits
Unit
V
Min
Max
unless otherwise specified
Low level input voltage
VIL1
VIL2
All
1, 2, 3
1, 2, 3
0.8
0.8
Low level input voltage,
TCK only
01, 02
03, 04
05, 06
10, 11
07, 08
09
1, 2, 3
0.7
High level input voltage
VIH
All
All
1, 2, 3
1, 2, 3
2.2
V
V
Low level input voltage
2/
VILC
0.3VDD
High level input voltage
2/
VIHC
VOL
All
All
1, 2, 3
1, 2, 3
0.7VDD
V
V
Low level output
voltage
Output loads
IOL = 4.0 mA
0.4
0.05
IOL = 1.0 mA 3/
IOH = 4.0 mA
IOH = 1.0 mA 3/
High level output
voltage
VOH
Output loads
All
All
1, 2, 3
1, 2, 3
1, 2, 3
2.4
V
VDD-0.05
mA
Input leakage current
IIN
TTL driven
inputs
VIN = VDD
or VSS
-10
+10
Inputs with
pull-up resistors
VIN = VDD
VIN = VSS
-10
+10
01, 02,
03, 04,
05, 06
10, 11
-900
-150
07, 08,
09
-167
-10
-27
Three-state output
leakage current, TTL
loaded outputs,
IOZ
VO = VDD or VSS
All
All
1, 2, 3
1, 2, 3
+10
mA
single-drive buffer
Short-circuit output
current, output loads
IOS
VDD = 5.5 V, VO = 0 V
VDD = 5.5 V, VO = VDD
-100
+100
mA
4/ 5/
Input capacitance
CIN
COUT
CIO
f = 1 MHz at 0 V
See 4.4.1c
All
All
All
4
4
4
45
45
45
pF
Output capacitance
Bi-directional
capacitance 6/
Standby operating
current
IDDS
f = 24 MHz
All
1, 2, 3
40
mA
See footnotes at end of table.
SIZE
STANDARD
5962-94663
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
D
7
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics - Continued.
Test
Symbol
Test conditions 1/
-55°C £ TC £ +125°C
4.5 V £ VDD £ 5.5 V
Device
type
Group A
subgroups
Limits
Unit
Min
Max
unless otherwise specified
Quiescent current
7/ 8/
IDDQ
f = 0 MHz
01 – 10
11
1, 3
2
35
1
mA
mA
mA
1, 3
2
35
1
Pre-irradiation level
R
mA
mA
11
1, 3
2
35
5
Pre-irradiation level
F
mA
mA
VCC supply current
ICC
VEE = -12 V
VCC = 5 V
0% duty cycle
(non-transmitting)
03, 06
09
1, 2, 3
140
50% duty cycle
(f = 1 MHz) 9/
140
140
140
140
140
55
100% duty cycle
(f = 1 MHz) 9/
VEE = -15 V
VCC = 5 V
0% duty cycle
(non-transmitting)
01, 04
07, 10
50% duty cycle
(f = 1 MHz) 10/
100% duty cycle
(f = 1 MHz) 10/
VCC = 5 V
0% duty cycle
(non-transmitting)
02, 05
08, 11
1, 2, 3
25% duty cycle 10/
250
410
50% duty cycle
(f = 1 MHz) 10/
87.5% duty cycle
(f = 1 MHz) 10/
650
855
80
100% duty cycle
(f = 500 kHz)
02
IEE supply current
IEE
VEE = -12 V
VCC = 5 V
0% duty cycle
(non-transmitting)
03, 06
09
1, 2, 3
mA
50% duty cycle
(f = 1 MHz) ) 9/
180
270
80
100% duty cycle
(f = 1 MHz) ) 9/
VEE = -15 V
VCC = 5 V
0% duty cycle
(non-transmitting)
01, 04
07, 10
50% duty cycle
(f = 1 MHz) ) 10/
180
270
100% duty cycle
(f = 1 MHz) ) 10/
See footnotes at end of table.
SIZE
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
5962-94663
A
REVISION LEVEL
SHEET
D
8
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics - Continued.
Test
Symbol
Test conditions 1/
-55°C £ TC £ +125°C
4.5 V £ VDD £ 5.5 V
Device
type
Group A
subgroups
Limits
Unit
Min
Max
unless otherwise specified
Functional tests
See 4.4.1b
All
7, 8
Register write timing
Address setup time 9/
Data setup time 9/
Data hold time 9/
ta
tb
tc
td
te
VCC = minimum
See figure 5
All
All
All
All
All
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
0
10
8
ns
Address hold time 9/
8
105
CS ¯ to CS • 9/
Access delay 9/ 11/ 12/
tf
All
All
9, 10, 11
9, 10, 11
85
0
tg
RD/ WR assertion to
CS assertion 10/
th
All
9, 10, 11
0
CS negation to
RD/ WR negation 10/
tI
tj
All
All
9, 10, 11
9, 10, 11
0
5
40
35
CS assertion to output
enable 9/
CS negation to output
three-state 10/
Register read timing
Address setup time 9/
ta
tb
VCC = minimum
See figure 5
All
All
9, 10, 11
9, 10, 11
0
5
ns
95
35
CS assertion to output
enable data valid 9/
tc
All
9, 10, 11
CS negation to output
disabled 10/
Address hold time 9/
td
te
All
All
9, 10, 11
9, 10, 11
0
0
40
CS assertion to output
enable data invalid 9/
Access delay 9/ 11/ 12/
tf
All
All
9, 10, 11
9, 10, 11
45
tg
105
CS ¯ to CS • 9/
Memory write timing
Address propagation
delay
ta
01 – 06
10, 11
9, 10, 11
9, 10, 11
9, 10, 11
0
0
18
21
35
ns
VCC = minimum
See figure 5
07, 08
09
tb
All
15
Address valid to RCS ,
RWR assertion 9/
See footnotes at end of table.
SIZE
STANDARD
5962-94663
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
D
9
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics - Continued.
Test
Symbol
Test conditions 1/
-55°C £ TC £ +125°C
4.5 V £ VDD £ 5.5 V
Device
type
Group A
subgroups
Limits
Unit
ns
Min
Max
50
unless otherwise specified
Memory write timing – Continued
tc
td
All
9, 10, 11
9, 10, 11
10
20
VCC = minimum
See figure 5
DTACK setup time 9/
All
RCS and RWR hold
time 9/ 13/
Data propagation delay
9/
te
All
9, 10, 11
20
60
30
Address hold time 9/
DTACK hold time 9/
RWR and RCS pulse
tg
th
All
All
9, 10, 11
9, 10, 11
10
10
ti
01 – 06
10, 11
9, 10, 11
9, 10, 11
9, 10, 11
34
32
15
width (DTACK tied to
ground)
07, 08
09
tj
All
125
40
RWR and RCS • to
DMACK • 10/
Data hold time 10/
tk
ta
All
9, 10, 11
10
Memory read timing
Address propagation
delay
01 – 06
10, 11
9, 10, 11
9, 10, 11
9, 10, 11
0
0
18
21
35
ns
VCC = minimum
See figure 5
07, 08
09
tb
All
15
Address valid to RCS ,
RRD assertion 9/
tc
td
All
All
9, 10, 11
9, 10, 11
10
20
DTACK setup time 9/
50
RCS and RRD hold
time 9/ 13/
Data setup delay 9/
te
9, 10, 11
9, 10, 11
12
10
01 - 06
07, 08
09
9, 10, 11
9, 10, 11
14
0
10, 11
Data hold delay
tf
01 – 06
10, 11
07, 08
09
9, 10, 11
9, 10, 11
2
Address hold time 9/
tg
All
10
30
See footnotes at end of table.
SIZE
STANDARD
5962-94663
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
D
10
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics - Continued.
Test
Symbol
Test conditions 1/
-55°C £ TC £ +125°C
4.5 V £ VDD £ 5.5 V
Device
type
Group A
subgroups
Limits
Unit
ns
Min
Max
unless otherwise specified
Memory read timing - Continued
th
ti
All
9, 10, 11
9, 10, 11
10
34
VCC = minimum
See figure 5
DTACK hold time
01 – 06
10, 11
RRD and RCS pulse
width (DTACK tied to
ground)
07, 08
09
9, 10, 11
9, 10, 11
32
15
tj
All
45
RRD and RCS • to
DMACK • 10/
DMA timing
ta
tb
All
9, 10, 11
5
VCC = minimum
See figure 5
ms
TERACT assertion to
DMAR assertion 10/
Bus controller
01, 02
03
9, 10, 11
9, 10, 11
7
DMAR assertion to
DMACK negation 10/
16
04 - 11
All
Remote terminal
9, 10, 11
9, 10, 11
7
7
Remote terminal
with monitor
All
Monitor
All
9, 10, 11
9, 10, 11
7
tc
01 – 06
10, 11
0
5
0
30
ns
DMAG assertion to
DMACK assertion
10/
07, 08
09
9, 10, 11
9, 10, 11
30
35
td
te
All
DMAG assertion to
DMAR negation 10/
01 – 06
10, 11
9, 10, 11
9, 10, 11
9, 10, 11
0
5
5
DMACK assertion to
address bus active
07, 08
09
-5
10
tf
All
DMACK assertion to
DMAG negation 9/
tg
All
9, 10, 11
500
DMACK negation to
DMAR assertion 10/
See footnotes at end of table.
SIZE
STANDARD
5962-94663
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
D
11
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics - Continued.
Test
Symbol
Test conditions 1/
-55°C £ TC £ +125°C
4.5 V £ VDD £ 5.5 V
Device
type
Group A
subgroups
Limits
Unit
ns
Min
Max
unless otherwise specified
DMA timing - Continued
th
01 – 06
10, 11
9, 10, 11
0
5
5
5
VCC = minimum
See figure 5
DMACK assertion to
RAM control active
(negated)
07, 08
09
-5
ti
tj
All
9, 10, 11
9, 10, 11
DMACK negation to
address three-state 10/
All
5
DMACK negation to RAM
control disabled 10/
Power-up master reset timing
ta
tb
VCC = minimum
See figure 5
All
All
9, 10, 11
9, 10, 11
500
ns
MRST pulse width 10/
5
ms
MRST negation to
ROMEN assertion 10/
tc
td
All
All
9, 10, 11
9, 10, 11
10
ms
MRST negation to
READY assertion 10/
500
ns
DMACK negation to
ROMEN negation 10/
JTAG timing
TCK frequency
TCK period
See figure 5
All
All
All
All
All
All
All
All
All
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
1
MHz
ns
ta
tb
tc
td
te
tf
1000
1/2ta
1/2ta
TCK high time
TCK low time
TCK rise time
5
5
TCK fall time
TDI, TMS setup time
TDI, TMS hold time
TDO valid delay
250
250
250
tg
th
Receiver electrical characteristics
Differential (receiver)
input impedance 10/
RIZ
VCC = minimum, see figure 5
Input f = 1 MHz (no transformer
in circuit)
01, 03
04, 06
07, 09
10
1, 2, 3
1, 2, 3
1, 2, 3
15
-10
-5
kW
Common mode input
voltage 10/
VIC
VCC = minimum, see figure 5
Direct-coupled stub, input
1.2 VPP , 200 ns rise/fall
time ±25 ns, f = 1 MHz
01, 03
04, 06
07, 09
10
+10
+5
V
02, 05
08, 11
See footnotes at end of table.
SIZE
STANDARD
5962-94663
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
D
12
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics - Continued.
Test
Symbol
Test conditions 1/
-55°C £ TC £ +125°C
4.5 V £ VDD £ 5.5 V
Device
type
Group A
subgroups
Limits
Min
Unit
Max
0.20
unless otherwise specified
Receiver electrical characteristics - Continued
Common mode
rejection ratio 10/
CMRR VCC = minimum, see figure 5
All
1, 2, 3
Pass/Fail
14/
N/A
Input threshold voltage
(no response)
VTH1
VCC = minimum, see figure 5
Transformer-coupled stub, input
at f = 1 MHz, rise/fall time
200 ns (receiver output 0 ® 1
transition) 10/
All
1, 2, 3
VPP,L-L
VCC = minimum, see figure 5
Direct-coupled stub, input at
f = 1 MHz, rise/fall time 200 ns
(receiver output 0 ® 1 transition)
All
All
1, 2, 3
1, 2, 3
0.28
14.0
Input threshold voltage
(response)
VTH2
VCC = minimum, see figure 5
Transformer-coupled stub, input
at f = 1 MHz, rise/fall time
200 ns (receiver output 0 ® 1
transition) 10/
0.86
1.20
VPP,L-L
VCC = minimum, see figure 5
Direct-coupled stub, input at
f = 1 MHz, rise/fall time 200 ns
(receiver output 0 ® 1transition)
All
02
1, 2, 3
20.0
10/
Differential input
voltage level
VIDR
VCC = minimum, see figure 5
1, 2, 3
1, 2, 3
8.0
27
VP-P
Transmitter electrical characteristics
Output voltage swing
VO
VCC = minimum, see figure 5
All
18
VPP,L-L
Transformer-coupled stub,
point A, input f = 1 MHz,
RL = 70W 10/
VCC = minimum, see figure 5
Direct-coupled stub, point A,
input f = 1 MHz, RL = 35W
All
All
All
1, 2, 3
1, 2, 3
1, 2, 3
6.0
6.0
9
VCC = minimum, see figure 5
Point A, input f = 1 MHz,
RL = 35W 10/
20
14
Output noise voltage
differential 10/
VNS
VCC = minimum, see figure 5
Transformer-coupled stub,
point A, input f = DC to 10 MHz,
RL = 70W
mV-
RMSL-L
VCC = minimum, see figure 5
Direct-coupled stub,
All
1, 2, 3
5
point A, input f = DC to 10 MHz,
RL = 35W
See footnotes at end of table.
SIZE
STANDARD
5962-94663
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
D
13
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics - Continued.
Test
Symbol
Test conditions 1/
-55°C £ TC £ +125°C
4.5 V £ VDD £ 5.5 V
Device
type
Group A
subgroups
Limits
Unit
Min
Max
unless otherwise specified
Transmitter electrical characteristics - Continued
Output symmetry 15/
VOS
VCC = minimum
All
All
1, 2, 3
1, 2, 3
1, 2, 3
-250
-90
+250
mVPP,L-L
Transformer-coupled stub,
point A, RL = 70W, measurement
taken 2.5 ms after end of
transmission 10/
VCC = minimum
+90
Direct-coupled stub, point A,
RL = 35W, measurement
taken 2.5 ms after end of
transmission 16/
Output voltage
distortion (overshoot
or ring)
VDIS
VCC = minimum, see figure 5
Transformer-coupled stub,
point A, RL = 70W 10/
01
03 – 11
-900
+900
mVpeak,L-L
02
1, 2, 3
1, 2, 3
-2.0
+2.0
Vpeak,L-L
VCC = minimum, see figure 5
Direct-coupled stub, point A,
RL = 35W 16/
01
03 – 11
-300
+300
mVpeak,L-L
02
All
1, 2, 3
1, 2, 3
-1.0
1
+1.0
Vpeak,L-L
kW
Terminal input
impedance 10/
TIZ
VCC = minimum, see figure 5
Transformer-coupled stub,
point A, input f = 75 kHz to 1 MHz,
(power on or power off, non-
transmitting, RL removed from
circuit)
All
VCC = minimum, see figure 5
Direct-coupled stub,
1, 2, 3
2
point A, input f = 75 kHz to 1 MHz,
(power on or power off, non-
transmitting, RL removed from
circuit)
AC electrical characteristics
Transmitter output
rise/fall time
tR, tF
VCC = minimum, see figure 5
Input f = 1 MHz 50% duty cycle:
direct-coupled, RL = 35W,
output at 10% through 90%
All
9, 10, 11
9, 10, 11
100
300
ns
points TXOUT, TXOUT
Zero crossing
distortion
tRZCD
VCC = minimum, see figure 5
Direct-coupled stuff,
All
-150
+150
Input f = 1 MHz, 3 VPP (skew
input ±150 ns), rise/fall time
200 ns
See footnotes at end of table.
SIZE
STANDARD
5962-94663
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
D
14
DSCC FORM 2234
APR 97
TABLE IA. Electrical performance characteristics - Continued.
Test
Symbol
Test conditions 1/
-55°C £ TC £ +125°C
4.5 V £ VDD £ 5.5 V
Device
type
Group A
subgroups
Limits
Unit
ns
Min
-25
Max
+25
unless otherwise specified
AC electrical characteristics - Continued
Zero crossing stability
tTZCS
VCC = minimum, see figure 5
All
9, 10, 11
Input TXIN and TXIN should
create transmitter output zero
crossings at 500 ns, 1000 ns,
1500 ns, and 2000 ns. These
zero crossings should not
deviate more than ±25 ns
1/ Device type 04 supplied to this drawing will meet all levels M, D, P, L, R of irradiation. Device type 05 supplied to this
drawing will meet all levels M, D, P, L, R, F, G, and H of irradiation. However, these devices are only tested at the 'R' and
'H' level, respectively. Device type 10 supplied to this drawing will meet level R of irradiation and will only be tested at level
R. Device type 11 supplied to this drawing will meet levels R and F of irradiation and will only be tested at level supplied.
Pre and post irradiation values are identical unless otherwise specified in table IA. When performing post irradiation
electrical measurements for any RHA level, TA = +25°C. All testing to be performed using worst case test conditions
unless otherwise specified. GND may not vary from 0 V by more than ±50 mV. Unless otherwise specified,
VCC = 5.0 V ±5% for device type 02; VCC = 5.0 V ±10% for device types 05, 08, and 11; VCC = 5.0 V +10%, -5% and
VEE = -12.0 V or -15.0 V ±5% for device types 01, 03, 04, 06, 07, 09, and 10.
2/ 24 MHz input only.
3/ The worst case test condition is when IOL and IOH = 4.0 mA.
4/ Supplied as a design limit but not guaranteed or tested.
5/ Not more than one output may be shorted at a time for maximum duration of one second.
6/ For all pins except CHA, CHA , CHB, CHB .
7/ All inputs tied to VDD
.
8/ Post irradiation limit is 1.0 mA. Device type 11 post irradiation limit is 1.0 mA level R of irradiation and 5.0 mA level F of
irradiation.
9/ For device types 07, 08, and 09, this parameter is guaranteed, but not tested.
10/ Guaranteed by characterization but not tested.
11/ Read cycle followed by a read cycle - minimum 45 ns.
Read cycle followed by a write cycle - minimum 45 ns.
Write cycle followed by a read cycle - minimum 85 ns.
Write cycle followed by a write cycle - minimum 85 ns.
12/ Minimum pulse width from latter rising edge of RD/ WR or CS to first falling edge.
13/ Pulse width duration is measured with respect to the device recognizing DTACK assertion.
14/ Pass/fail criteria per the test method described in MIL-STD-1553, appendix A. RT validation test plan, section 5.1.2.2,
common mode rejection.
15/ Test in accordance with the method described in MIL-STD-1553B output symmetry, section 4.5.2.1.1.4.
16/ Tested on deivce types 07, 08, and 09 only.
SIZE
STANDARD
5962-94663
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
D
15
DSCC FORM 2234
APR 97
TABLE IB. SEP test limits. 1/ 2/ 3/
VDD = 4.5 V
Device
type
TA =
Temperature
±10°C
Bias for
latch-up test
VDD = 5.5 V
no latch-up
LET = 4/
Effective LET
no upsets
Maximum device
cross section
LET = 120
[MeV/(mg/cm2)]
4/
(mm2)
04, 05
10, 11
5/
5/
5/
+25°C
1/ Devices that contain cross-coupled resistance must be tested at the maximum rated TA.
2/ For SEP test conditions, see 4.4.4.5 herein.
3/ Technology characterization and model verification supplemented by in-line data may be used in lieu of
end-of-line testing. Test plan must be approved by TRB and qualifying activity.
4/ Worst case temperature TA = +125°C.
5/ Values will be added when they become available. These devices have not yet been tested for SEP.
SIZE
STANDARD
5962-94663
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
D
16
DSCC FORM 2234
APR 97
Case X
FIGURE 1. Case outlines.
SIZE
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
5962-94663
A
REVISION LEVEL
SHEET
B
17
DSCC FORM 2234
APR 97
Case X
Millimeters
Symbol
Inches
Min
6.85
2.54
0.40
32.89
Max
8.00
3.17
0.50
33.66
Min
.270
.100
.016
1.295
Max
.315
.125
.020
1.325
A
A1
b
D
D1
E
29.21 BSC
1.150 BSC
1.045 1.075
.050 BSC
26.54
4.37
27.30
e
1.27 BSC
4.77
L
.172
.188
NOTE: The US Government preferred system of measurement is the metric SI system. However, this
item was originally designed using inch-pound units of measurements. In the event of conflict
between the metric and inch-pound units, the inch-pound units shall take precedence.
FIGURE 1. Case outlines - Continued.
SIZE
STANDARD
5962-94663
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
B
18
DSCC FORM 2234
APR 97
Case Y
FIGURE 1. Case outlines - Continued.
SIZE
STANDARD
5962-94663
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
B
19
DSCC FORM 2234
APR 97
Case Y
Millimeters
Symbol
Inches
Min
Max
2.66
Min
Max
.105
A
A1
b
2.28
0.152
0.1270
3.30
.090
.006
.130
0.254
0.1905
65.532
34.67
.010
c
.0050
.0075
2.580
1.365
D/E
D1
D2/E2
E1
e
33.91
1.335
15.24 BSC
.600 BSC
1.000
.025 BSC
24.64
25.40
.970
.350
0.635 BSC
8.89
L
NOTE: The US Government preferred system of measurement is the metric SI system. However, this
item was originally designed using inch-pound units of measurements. In the event of conflict
between the metric and inch-pound units, the inch-pound units shall take precedence.
FIGURE 1. Case outlines - Continued.
SIZE
STANDARD
5962-94663
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
F
20
DSCC FORM 2234
APR 97
Device
type
All
X
Case
outline
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
A2
A4
A15
A14
C2
C4
A12
VDD
T1
T3
A3
A4
V1
V3
VSS
RRD
D14
A6
A8
A13
C6
C8
A8
T5
T7
VDD
A6
V5
V7
VSS
ROMEN
DTACK
D13
A10
A12
C10
C12
T9
24 MHz
VSS
V9
CS
DMAG
YF_INT
TMS
MSEL0
T11
V11
D15
A14
A16
A18
TCK
TDI
C14
C16
C18
T13
T15
T17
V13
V15
V17
D9
D10
D8
LOCK
A/B STD
READY
GND
TDO
CHB
GND
CHB
VCC
A9
A20
A22
A24
B1
RTA2
RTA0
GND
VDD
C20
C22
C24
D1
T19
T21
T23
U2
VCC
VEE 1/
VEE 1/
A1
V19
V21
V23
W2
W4
D1
D2
D0
A5
B3
A11
D3
A7
U4
VDD
RWR
A0
B5
B7
A10
D5
D7
VSS
VDD
U6
U8
A2
W6
W8
VSS
TCLK
DMACK
AUTOEN
B9
D9
U10
D12
D11
W10
VDD
MSG_INT
VSS
B11
B13
B15
B17
D11
D13
D15
D17
U12
U14
U16
U18
W12
W14
W16
W18
RD/ WR
MSEL1
RCS
D5
DMAR
SSYSF
D6
D7
TRST
RTA4
MRST
GND
TERACT
CHA
GND
CHA
VCC
B19
B21
B23
RTA3
RTA1
D19
D21
D23
VCC
U20
U22
U24
W20
W22
W24
D4
D3
VEE 1/
VEE 1/
RTPTY
GND
Terminal located on top of package
VSSQ CP3
CP1
VDDQ
CP2
VDD
CP4
VSS
1/ Device types 01, 03, 04, 06, 07, 09, and 10 only. For device types 02, 05, 08, and 11, this is a N/C (no connection).
FIGURE 2. Terminal connections.
SIZE
STANDARD
5962-94663
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
D
21
DSCC FORM 2234
APR 97
Device
type
All
Y
Case
outline
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
1
2
3
4
5
6
7
8
26
27
28
29
30
31
32
33
A15
VEE 1/
VEE 1/
GND
VCC
51
52
53
54
55
56
57
58
TDI
76
77
78
79
80
81
82
83
VDD
VSS
DMACK
DMAG
DMAR
TDO
TRST
ROMEN
AUTOEN
CS
RTPTY
DTACK
VSS
RTA0
RTA1
RTA2
RTA3
GND
CHA
RRD
RD/ WR
D0
RWR
D1
RCS
VDD
VSS
A0
CHA
GND
VCC
9
34
35
36
37
38
59
60
61
62
63
RTA4
VDD
84
85
86
87
88
D2
D3
D4
D5
D6
10
11
12
13
VCC
VSS
A1
GND
GND
VDD
A2
TERACT
READY
14
15
A3
A4
39
40
VCC
VCC
64
65
89
90
D7
D8
MSG_INT
16
A5
41
GND
CHB
66
91
D9
YF_INT
17
18
A6
A7
42
43
67
68
VSS
92
93
D10
D11
TCLK
CHB
GND
19
20
A8
A9
44
45
69
70
94
95
D12
D13
LOCK
VCC
A/B STD
MSEL0
MSEL1
21
22
23
A10
A11
A12
46
47
48
GND
VEE 1/
VEE 1/
71
72
73
96
97
98
D14
D15
VSS
MRST
24
25
A13
A14
49
50
TCK
TMS
74
75
24 MHz
99
VDD
VDD
100
SSYSF
1/ Device types 01, 03, 04, 06, 07, 09, and 10 only. For device types 02, 05, 08, and 11, this is a N/C (no connection).
FIGURE 2. Terminal connections - Continued.
SIZE
STANDARD
5962-94663
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
D
22
DSCC FORM 2234
APR 97
FIGURE 3. Block diagram.
SIZE
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
5962-94663
A
REVISION LEVEL
SHEET
B
23
DSCC FORM 2234
APR 97
Device types 01, 02, 03, 04, 05, 06, 10, 11
Instruction name
BYPASS
Instruction code
1111
SAMPLE/PRELOAD
EXTEST
0010
0000
INTEST
0001
RUNBIST
0111
IDCODE
0100
GL-TRISTATE
INTERNAL-SCAN
PRIVATE
0011
0101
0110
USER-SELECTABLE
1000 ® 1110
Device types 07, 08, 09
Instruction name
BYPASS
Instruction code
1111
SAMPLE/PRELOAD
EXTEST
0010
0000
FIGURE 4. Boundary scan instruction codes.
SIZE
STANDARD
5962-94663
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216-5000
REVISION LEVEL
SHEET
D
24
DSCC FORM 2234
APR 97
FIGURE 5. Timing waveforms.
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NOTE: The memory read and write timing diagrams are applicable for reads and writes resulting from the
auto-initialization sequence.
FIGURE 5. Timing waveforms - Continued.
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( S E E N O T E B E L O W )
NOTE: The memory read and write timing diagrams are applicable for reads and writes resulting from the
auto-initialization sequence.
FIGURE 5. Timing waveforms - Continued.
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24 MHz
TRANSCEIVER TEST CIRCUIT MIL-STD-1553B
NOTES:
1. Transformer coupled stub:
Terminal is defined as transceiver plus isolation transformer.
2. Direct coupled stub:
Terminal is defined as transceiver plus isolation transformer and fault resistors.
FIGURE 5. Timing waveforms - Continued.
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FIGURE 5. Timing waveforms - Continued.
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FIGURE 5. Timing waveforms - Continued.
Case
outline
Open
VCC = 5.5 V
VDD = 5.5 V
VEE = -15 V
1/
Ground
A2, A4, A6, A8,
A18, B3, B5, B7,
C2, C6, C12, C18,
C22, D1, D3, D9,
D13, T7, T15,
C24, D19,
T19, U24
A10, A12, A14, A16, A20, A22,
B1, B9, B11, B13, B15, B17, B19,
B21, B23, C4, C10, C14, C16,
D7, D15, T1, T3, T5, T9, T13, U2,
U4, U6, U10, U12, U14, V5, V7,
V9, V11, V13, V15, V17, V19,
V21, V23, W6, W8, W10, W14,
W16, W18, W20, W22
D21, D23,
T21, T23
A24, C8,
C20, D5,
D11, D17,
T11, T17,
U8, U20,
V1, W24
X
Y
U16, U18, U22,
V3, W2, W4, W12
1, 3, 6, 7, 8, 16,
17, 18, 19, 20, 21,
22, 23, 24, 25, 26,
32, 33, 42, 43, 52,
63, 64, 65, 66, 78
30, 35, 36,
39, 40, 45
2, 4, 9, 11, 12, 13, 14, 15, 49, 50,
51, 53, 54, 55, 56, 57, 58, 59, 60,
62, 68, 69, 70, 71, 72, 73, 74, 75,
76, 79, 80, 81, 82, 83, 84, 85, 86,
87, 88, 89, 90, 91, 92, 93, 94, 95,
96, 97, 99, 100
27, 28, 47,
48
5, 10, 29,
31, 34, 37,
38, 41, 44,
46, 61, 67,
77, 98
1/ For device types 01, 03, 04, 06, 07, 09, and 10 only. For device types 02, 05, 08, and 11, these pins are open.
FIGURE 6. Radiation exposure connections.
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4. QUALITY ASSURANCE PROVISIONS
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be
in accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a. Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision
level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
test method 1015.
(2) TA = +125°C, minimum.
b. Interim and final electrical test parameters shall be as specified in table IIA herein.
4.2.2 Additional criteria for device classes Q and V.
a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained
under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance
with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit
shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified
in test method 1015 of MIL-STD-883.
b. Interim and final electrical test parameters shall be as specified in table IIA herein.
c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for
groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified. Quality conformance inspection for device
class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed for
device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections
(see 4.4.1 through 4.4.4).
4.4.1 Group A inspection.
a. Tests shall be as specified in table IIA herein.
b. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the functionality of the device. For device
classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device; these tests shall have been
fault graded in accordance with MIL-STD-883, test method 5012 (see 1.5 herein).
c. Subgroup 4 (CIN, COUT, and CIO) shall be measured only for the initial test and after process or design changes which
may affect input capacitance. A minimum sample of 5 devices with zero failures shall be required.
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TABLE IIA. Electrical test requirements.
Subgroups
Test requirements
Subgroups
(in accordance with
MIL-STD-883,
(in accordance with
MIL-PRF-38535, table III)
method 5005, table I)
Device
class M
Device
class Q
Device
class V
Interim electrical
---
---
---
parameters (see 4.2)
Final electrical
parameters (see 4.2)
1, 2, 3, 7, 8, 9,
10, 11 1/
1, 2, 3, 7, 8, 9,
10, 11 1/
1, 2, 3, 7, 8, 9,
10, 11 2/ 3/
Group A test
requirements (see 4.4)
1, 2, 3, 4, 7, 8, 9,
10, 11
1, 2, 3, 4, 7, 8, 9,
10, 11
1, 2, 3, 4, 7, 8, 9,
10, 11
Group C end-point electrical
parameters (see 4.4)
1, 7, 9
1, 7, 9
1, 7, 9
1, 7, 9
1, 7, 9
1, 7, 9
1, 7, 9
1, 7, 9
1, 7, 9
Group D end-point electrical
parameters (see 4.4)
Group E end-point electrical
parameters (see 4.4)
1/ PDA applies to subgroup 1.
2/ PDA applies to subgroups 1 and 7.
3/ Delta limits, as specified in table IIB herein, shall be required when specified and the delta values shall be
completed with reference to the zero hour electrical parameters.
TABLE IIB. Burn-in and operating life test, delta parameters (+25°C).
Parameter
Symbol
IDDQ
Delta limits
Quiescent current
±10% of measured values or
35 mA whichever is greater
NOTE: If the device is tested at or below 35 mA, no deltas are required.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a. Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify
the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test
method 1005 of MIL-STD-883.
b. TA = +125°C, minimum.
c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
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4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test
temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with
MIL-PRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturer's TRB
in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test
circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
test method 1005 of MIL-STD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness
assured (see 3.5 herein). RHA levels for device classes M, Q and V shall be as specified in MIL-PRF-38535. End-point
electrical parameters shall be as specified in table IIA herein.
4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883
method 1019 and as specified herein.
4.4.4.1.1 Accelerated aging test. Accelerated aging tests shall be performed on all devices requiring a RHA level greater
than 5k rads(Si). The post-anneal end-point electrical parameter limits shall be as specified in table IA herein and shall be the
pre-irradiation end-point electrical parameter limit at 25°C ±5°C. Testing shall be performed at initial qualification and after
any design or process changes which may affect the RHA response of the device.
4.4.4.2 Neutron testing. Neutron testing shall be performed in accordance with test method 1017 of MIL-STD-883 and
herein (see 1.4). All device classes must meet the post irradiation end-point electrical parameter limits as defined in table IA,
for the subgroups specified in table IIA herein at TA = +25°C ± 5°C after an exposure of 2 x 1012 neutron/cm2 (minimum).
4.4.4.3 Dose rate induced latchup testing. Dose rate induced latchup testing shall be performed in accordance with test
method 1020 of MIL-STD-883 and as specified herein (see 1.4). Tests shall be performed on devices, SEC, or approved test
structures at technology qualification and after any design or process changes which may effect the RHA capability of the
process.
4.4.4.4 Dose rate upset testing. Dose rate upset testing shall be performed in accordance with test method 1021 of
MIL-STD-883 and herein (see 1.4).
a. Transient dose rate upset testing shall be performed at initial qualification and after any design or process changes
which may effect the RHA performance of the devices. Test 10 devices with 0 defects unless otherwise specified.
b. Transient dose rate upset testing for class Q and V devices shall be performed as specified by a TRB approved
radiation hardness assurance plan and MIL-PRF-38535.
4.4.4.5 Single event phenomena (SEP). SEP testing shall be required on class V devices (see 1.4). SEP testing shall be
performed on the Standard Evaluation Circuit (SEC) or alternate SEP test vehicle as approved by the qualifying activity at
initial qualification and after any design or process changes which may affect the upset or latchup characteristics. The
recommended test conditions for SEP are as follows:
a. The ion beam angle of incidence shall be between normal to the die surface and 60° to the normal, inclusive (i.e. 0° £
angle £ 60°). No shadowing of the ion beam due to fixturing or package related effects is allowed.
b. The fluence shall be ³ 100 errors or ³ 106 ions/cm2.
c. The flux shall be between 102 and 105 ions/cm2/s. The cross-section shall be verified to be flux independent by
measuring the cross-section at two flux rates which differ by at least an order of magnitude.
d. The particle range shall be ³ 20 microns in silicon.
e. The test temperature shall be +25°C and the maximum rated operating temperature ±10°C.
f. Bias conditions shall be defined by the manufacturer for latchup measurements.
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g. Test four devices with zero failures.
h. For SEP test limits, see table IB herein.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device
classes Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a
contractor-prepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus when a system
application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of
users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering
microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.
6.4 Comments. Comments on this drawing should be directed to DSCC-VA , Columbus, Ohio 43216-5000, or telephone
(614) 692-0547.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535, MIL-HDBK-1331, and table III herein.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in
QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and
have agreed to this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DSCC-VA.
6.7 Additional information. A copy of the following additional data shall be maintained and available from the device
manufacturer:
a. RHA upset levels.
b. Test conditions (SEP).
c. Number of upsets (SEP).
d. Number of transients (SEP).
e. Occurrence of latchup (SEP).
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TABLE III. Pin descriptions.
Description
Name
Type 1/
Active 2/
Data bus
D0
TTB
TTB
TTB
TTB
TTB
TTB
TTB
TTB
TTB
TTB
TTB
TTB
TTB
TTB
TTB
TTB
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Bit 0 (LSB) of the bi-directional Data bus.
Bit 1 of the bi-directional Data bus.
Bit 2 of the bi-directional Data bus.
Bit 3 of the bi-directional Data bus.
Bit 4 of the bi-directional Data bus.
Bit 5 of the bi-directional Data bus.
Bit 6 of the bi-directional Data bus.
Bit 7 of the bi-directional Data bus.
Bit 8 of the bi-directional Data bus.
Bit 9 of the bi-directional Data bus.
Bit 10 of the bi-directional Data bus.
Bit 11 of the bi-directional Data bus.
Bit 12 of the bi-directional Data bus.
Bit 13 of the bi-directional Data bus.
Bit 14 of the bi-directional Data bus.
Bit 15 (MSB) of the bi-directional Data bus.
Address bus
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A0
TTB
TTB
TTB
TTB
TTB
TTO
TTO
TTO
TTO
TTO
TTO
TTO
TTO
TTO
TTO
TTO
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Bit 0 (LSB) of the bi-directional Address bus.
Bit 1 of the bi-directional Address bus.
Bit 2 of the bi-directional Address bus.
Bit 3 of the bi-directional Address bus.
Bit 4 of the bi-directional Address bus.
Bit 5 of the Address bus.
A1
A2
A3
A4
A5
A6
Bit 6 of the Address bus.
A7
Bit 7 of the Address bus.
A8
Bit 8 of the Address bus.
A9
Bit 9 of the Address bus.
A10
A11
A12
A13
A14
A15
Bit 10 of the Address bus.
Bit 11 of the Address bus.
Bit 12 of the Address bus.
Bit 13 of the Address bus.
Bit 14 of the Address bus.
Bit 15 (MSB) of the Address bus.
See footnotes at end of table.
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TABLE III. Pin descriptions - Continued.
Description
Name
RTA0
Type 1/
TUI
Active 2/
--
Remote terminal address inputs
Remote Terminal Address bit 0. This is bit 0 of the RT address. This is the least
significant bit for the RT address.
RTA1
RTA2
RTA3
RTA4
RTPTY
TUI
TUI
TUI
TUI
TUI
--
--
--
--
--
Remote Terminal Address bit 1. This is bit 1 of the RT address.
Remote Terminal Address bit 2. This is bit 2 of the RT address.
Remote Terminal Address bit 3. This is bit 3 of the RT address.
Remote Terminal Address bit 4. This is the most significant bit of the RT address.
Remote Terminal Parity. This is an odd parity input for the RT address.
JTAG testability pins
TDO
TCK
TMS
TDI
TTO
TI
--
--
TDO. This output performs the operation of Test Data Output as defined in the IEEE
Standard 1149.1. This cell provides the output signal for the Test Access Port (TAP).
This non-inverting output buffer is optimized for driving TTL loads.
TCK. This input performs the operation of Test Clock input as defined in the IEEE
Standard 1149.1. This cell provides the input clock for non-inverting input buffer that is
optimized for driving TTL input levels.
TUI
TUI
TUI
--
TMS. This input performs the operation of Test Mode Select as defined in the IEEE
Standard 1149.1. This cell provides the input signal for the Test Access Port (TAP).
This non-inverting input buffer is optimized for driving TTL input levels.
--
TDI. This input performs the operation of Test Data In as defined in the IEEE Standard
1149.1. This cell provides the input signal for the Test Access Port (TAP). This non-
inverting input buffer is optimized for driving TTL input levels.
AL
TRST
TRST . This input provides the RESET to the TAP controller as defined in the IEEE
Standard 1149.1. This non-inverting input buffer is optimized for driving TTL input
levels. When not exercising JTAG, tie TRST to a logical 0.
Biphase inputs/outputs
CHA
CHA
DIO
DIO
--
--
Channel A (true). This is the Manchester-encoded true signal for channel A.
Channel A (complement). This is the Manchester-encoded complement signal for
channel A.
CHB
CHB
DIO
DIO
--
--
Channel B (true). This is the Manchester-encoded true signal for channel B.
Channel B (complement). This is the Manchester-encoded complement signal for
channel B.
DMA signals
TTO 3/
AL
DMA Request. This signal is asserted when access to RAM is required. It goes inactive
upon request of the DMAG signal.
DMAR
TI
AL
AL
DMA Grant. Once this input is received, the device is allowed to access RAM.
DMAG
TTO 3/
DMA Acknowledge. This signal is asserted by the device to indicate the receipt of
DMAG . The signal remains active until all RAM bus activity is completed.
DMACK
TI
AL
Data Transfer Acknowledge. This pin indicates that a data transfer is to occur and that
the device may complete the memory cycle.
DTACK
See footnotes at end of table.
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TABLE III. Pin descriptions - Continued.
Description
Name
Type 1/
TI
Active 2/
--
Control signals
Read/Write. This indicates the direction of data flow with respect to the host. A
logic high signal means the host is trying to read data from the device, and a logic
low signal means the host is trying to write data to the device.
RD/ WR
TI
AL
AL
AL
AL
Chip Select. This pin selects the device when accessing the internal registers.
RAM Read. This signal is generated by the device to read data from RAM.
RAM Write. This signal is generated by the device to write data to RAM.
CS
TTO
TTO
TTO
RRD
RWR
RCS
RAM Chip Select. This signal is used in conjunction with the RRD /RWR signal to
access RAM.
TI
AL
AL
Auto Enable. This pin, when active, enables automatic initialization.
AUTOEN
ROMEN
TTO 3/
ROM Enable. This pin, when active enables the ROM for automatic initialization
applications.
TI
CI
AL
--
Subsystem Fail. Upon receipt, this signal propagates directly to the RT 1553 status
word.
SSYSF
24 MHz
24 MHz Clock. This 24 MHz input clock requires a 50% ±10% duty cycle with an
accuracy of ±0.01%.
TUI
TI
AL
--
Master Reset. This input pin resets the internal encoders, decoders, all register,
and associated logic.
MRST
MSEL1
Mode Select 1. This pin is the most significant bit for the mode select. For proper
mode selection, see below:
MSEL1
MSEL0
Mode of Operation
Bus Controller = SBC
Remote Terminal = SRT
Monitor Terminal = SMT
SMT/SRT
0
0
1
1
0
1
0
1
MSEL0
TCLK
TI
TI
--
--
Mode Select 0. This pin is the least significant bit for the mode select. (See
MSEL1 for proper logic states.)
Timer Clock. This internal timer is a 16-bit counter with a 64 ms resolution when
using the 24 MHz input clock. For different applications, the user may input a
clock (0-60 MHz) to establish the timer resolution. (Duty Cycle = 50% ±10%).
TI
TI
--
Military Standard A or B. This pin defines whether the device will be used a
MIL-STD-1553A or 1553B mode of operation.
A/B STD
LOCK
AL
Lock. This pin, when set active, prevents software changes to both the RT
address, A/B STD, and mode select.
See footnotes at end of table.
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TABLE III. Pin descriptions - Continued.
Description
Name
Type 1/
Active 2/
Status signals
TO
TTO 3/
TTO 3/
TO
AL
AL
AL
AL
Terminal Active. This output pin indicates that the terminal is actively processing a
1553 command.
TERACT
MSG_INT
YF_INT
READY
Message Interrupt. This pin is active for three clock cycles (i. e., 125 ns pulse) upon
the occurrence of interrupt events which are enabled.
You Failed Interrupt. This pin is active for three clock cycles (i. e., 125 ns pulse)
upon the occurrence of interrupt events which are enabled.
Ready. This signal indicates the device has completed initialization or BIT, and
regular execution may begin.
Power/Ground
VDD
VCC
--
--
--
--
+5 volt logic power (± 10%)
Device types 01, 03, 04, 06, 07, 09, and 10: +5 volt transceiver power (+10%, -5%).
Recommended de-coupling capacitors: 4.7 mF and 0.1 mF.
Device type 02: +5 volt transceiver power (±5%).
Device types 05, 08, and 11: +5 volt transceiver power (±10%).
Recommended de-coupling capacitors: 4.7 mF and 0.1 mF.
VEE
--
--
Device types 01, 03, 04, 06, 07, 09, and 10 only: -12 or -15 volt transceiver power
(±5%).
Recommended de-coupling capacitors: 4.7 mF and 0.1 mF.
VSS
--
--
--
--
Digital ground.
GND
Transceiver ground.
1/ TO = TTL output
TTB = Three-state TTL bi-directional
CI = CMOS input
TUI = TTL input (internally pulled high)
TI = TTL input
TTO = Three-state TTL output
DIO = Differential input/output
All pins specified as TTL are actually CMOS transistor pairs designed for TTL compatibility.
2/ AH = Active high
AL = Active low
3/ High impedance and active low.
SIZE
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
5962-94663
A
REVISION LEVEL
SHEET
COLUMBUS, OHIO 43216-5000
D
38
DSCC FORM 2234
APR 97
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 01-07-27
Approved sources of supply for SMD 5962-94663 are listed below for immediate acquisition information only and
shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a
certificate of compliance has been submitted to and accepted by DSCC-VA. This bulletin is superseded by the next
dated revision of MIL-HDBK-103 and QML-38535.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-9466301QXA
5962-9466301QYA
5962-9466301QXC
5962-9466301QYC
5962-9466302QXA
5962-9466302QYA
5962-9466302QXC
5962-9466302QYC
5962-9466303QXA
5962-9466303QYA
5962-9466303QXC
5962-9466303QYC
5962-9466304QXA
5962-9466304QYA
5962-9466304QXC
5962-9466304QYC
5962R9466304QXA
5962R9466304QYA
5962R9466304QXC
5962R9466304QYC
5962R9466304VXA
5962R9466304VYA
5962R9466304VXC
5962R9466304VYC
5962-9466305QXA
5962-9466305QYA
5962-9466305QXC
5962-9466305QYC
3/
3/
3/
3/
3/
3/
3/
3/
3/
3/
3/
3/
3/
3/
3/
3/
3/
3/
3/
3/
3/
3/
3/
3/
3/
3/
3/
3/
UT69151LX15/GA
UT69151LX15/WA
UT69151LX15/GC
UT69151LX15/WC
UT69151DX/GA
UT69151DX/WA
UT69151DX/GC
UT69151DX/WC
UT69151LX12/GA
UT69151LX12/WA
UT69151LX12/GC
UT69151LX12/WC
UT69151LXE15/GQA
UT69151LXE15/WQA
UT69151LXE15/GQC
UT69151LXE15/WQC
UT69151LXE15/GQAR
UT69151LXE15/WQAR
UT69151LXE15/GQCR
UT69151LXE15/WQCR
UT69151LXE15/GVAR
UT69151LXE15/WVAR
UT69151LXE15/GVCR
UT69151LXE15/WVCR
UT69151DXE/GQA
UT69151DXE/WQA
UT69151DXE/GQC
UT69151DXE/WQC
See footnotes at end of table.
STANDARD MICROCIRCUIT DRAWING BULLETIN - Continued.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962H9466305QXA
5962H9466305QYA
5962H9466305QXC
5962H9466305QYC
5962H9466305VXA
5962H9466305VYA
5962H9466305VXC
5962H9466305VYC
5962-9466306QXA
5962-9466306QYA
5962-9466306QXC
5962-9466306QYC
5962-9466307QXA
5962-9466307QYA
5962-9466307QXC
5962-9466307QYC
5962-9466308QXA
5962-9466308QYA
5962-9466308QXC
5962-9466308QYC
5962-9466309QXA
5962-9466309QYA
5962-9466309QXC
5962-9466309QYC
5962R9466310QYA
5962R9466310QYC
5962R9466310VYA
5962R9466310VYC
5962R9466311QYA
5962R9466311QYC
5962R9466311VYA
5962R9466311VYC
3/
UT69151DXE/GQAH
UT69151DXE/WQAH
UT69151DXE/GQCH
UT69151DXE/WQCH
UT69151DXE/GVAH
UT69151DXE/WVAH
UT69151DXE/GVCH
UT69151DXE/WVCH
UT69151LXE12/GQA
UT69151LXE12/WQA
UT69151LXE12/GQC
UT69151LXE12/WQC
UT69151LXE15/GQA
UT69151LXE15/WQA
UT69151LXE15/GQC
UT69151LXE15/WQC
UT69151DXE/GQA
3/
3/
3/
3/
3/
3/
3/
3/
3/
3/
3/
65342
65342
65342
65342
65342
65342
65342
65342
65342
65342
65342
65342
65342
65342
65342
65342
65342
65342
65342
65342
UT69151DXE/WQA
UT69151DXE/GQC
UT69151DXE/WQC
UT69151LXE12/GQA
UT69151LXE12/WQA
UT69151LXE12/GQC
UT69151LXE12/WQC
UT69151LXE15/WQAR
UT69151LXE15/WQCR
UT69151LXE15/WVAR
UT69151LXE15/WVCR
UT69151DXE/WQAR
UT69151DXE/WQCR
UT69151DXE/WVAR
UT69151DXE/WVCR
See footnotes at end of table.
STANDARD MICROCIRCUIT DRAWING BULLETIN - Continued.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962F9466311QYA
5962F9466311QYC
5962F9466311VYA
5962F9466311VYC
65342
65342
65342
65342
UT69151DXE/WQAF
UT69151DXE/WQCF
UT69151DXE/WVAF
UT69151DXE/WVCF
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed, contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may not
satisfy the performance requirements of this drawing.
3/ No longer available from an approved source of supply.
Vendor CAGE
number
Vendor name
and address
65342
Aeroflex UTMC Microelectronics System Inc.
4350 Centennial Boulevard
Colorado Springs, Colorado 80907-3486
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.
相关型号：
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