54ACT11238FK [ETC]
3-To-8-Line Demultiplexer ; 3-至8行解复用器\n
| 型号： | 54ACT11238FK |
| 厂家： | 
ETC |
| 描述： | 3-To-8-Line Demultiplexer
|
| 文件： | 总10页 (文件大小：187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1998
54AC138 • 54ACT138
1-of-8 Decoder/Demultiplexer
General Description
Features
n ICC reduced by 50%
The ’AC/’ACT138 is
a
high-speed 1-of-8 decoder/
demultiplexer. This device is ideally suited for high-speed bi-
polar memory chip select address decoding. The multiple in-
put enables allow parallel expansion to a 1-of-24 decoder
using just three ’AC/’ACT138 devices or a 1-of-32 decoder
using four ’AC/’ACT138 devices and one inverter.
n Demultiplexing capability
n Multiple input enable for easy expansion
n Active LOW mutually exclusive outputs
n Outputs source/sink 24 mA
n ’ACT138 has TTL-compatible inputs
n Standard Microcircuit Drawing (SMD)
— ’AC138: 5962-87622
— ’ACT138: 5962-87554
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP and Flatpak
DS100268-1
IEEE/IEC
DS100268-2
Pin Assignment
for LCC
DS100268-7
Pin Names
A0–A2
E1–E2
E3
Description
Address Inputs
Enable Inputs
Enable Input
Outputs
DS100268-3
O0–O7
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100268
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Functional Description
The ’AC/’ACT138 high-speed 1-of-8 decoder/demultiplexer
accepts three binary weighted inputs (A0, A1, A2) and, when
enabled, provides eight mutually exclusive active-LOW out-
puts (O0–O7). The ’AC/’ACT138 features three Enable in-
puts, two active-LOW (E1, E2) and one active-HIGH (E3). All
outputs will be HIGH unless E1 and E2 are LOW and E3 is
HIGH. This multiple enable function allows easy parallel ex-
pansion of the device to a 1-of-32 (5 lines to 32 lines) de-
coder with just four ’AC/’ACT138 devices and one inverter
(see Figure 1). The ’AC/’ACT138 can be used as an 8-output
demultiplexer by using one of the active LOW Enable inputs
as the data input and the other Enable inputs as strobes. The
Enable inputs which are not used must be permanently tied
to their appropriate active-HIGH or active-LOW state.
Truth Table
Inputs
Outputs
E1
H
X
E2
X
E3
X
A0
X
A1
X
A2
X
O0
H
O1
H
O2
H
O3
H
O4
H
O5
H
O6
H
O7
H
H
X
X
X
X
X
H
H
H
H
H
H
H
H
X
L
X
X
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
H
L
L
L
L
L
L
L
L
H
H
H
H
L
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
H
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
L
H
H
H
L
H
H
H
H
H
H
=
=
=
H
L
X
HIGH Voltage Level
LOW Voltage Level
Immaterial
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2
Logic Diagram
DS100268-4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Logic Diagram (Continued)
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4
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Recommended Operating
Conditions
Supply Voltage (VCC
)
’AC
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
Supply Voltage (VCC
)
−0.5V to +7.0V
’ACT
DC Input Diode Current (IIK
)
Input Voltage (VI)
=
VI −0.5V
−20 mA
+20 mA
=
VI VCC + 0.5V
Output Voltage (VO
)
0V to VCC
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
Operating Temperature (TA)
54AC/ACT
DC Output Diode Current (IOK
)
−55˚C to +125˚C
125 mV/ns
=
VO −0.5V
−20 mA
+20 mA
Minimum Input Edge Rate (∆V/∆t)
’AC Devices
=
VO VCC + 0.5V
DC Output Voltage (VO
DC Output Source
or Sink Current (IO
)
−0.5V to VCC + 0.5V
% to 70% of V
VIN from 30
CC
@
VCC 3.3V, 4.5V, 5.5V
±
±
)
50 mA
Minimum Input Edge Rate (∆V/∆t)
’ACT Devices
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
50 mA
VIN from 0.8V to 2.0V
Storage Temperature (TSTG
)
−65˚C to +150˚C
@
VCC 4.5V, 5.5V
125 mV/ns
Junction Temperature (TJ)
CDIP
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT® circuits outside databook specifications.
175˚C
DC Characteristics for ’AC Family Devices
54AC
=
Symbol
Parameter
VCC
(V)
TA
Units
Conditions
−55˚C to +125˚C
Guaranteed Limits
=
VIH
Minimum High
Level Input Voltage
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
2.1
3.15
3.85
0.9
VOUT 0.1V
V
V
V
or VCC − 0.1V
=
VIL
Maximum Low
Level Input Voltage
VOUT 0.1V
1.35
1.65
2.9
or VCC − 0.1V
=
IOUT −50 µA
VOH
Minimum High
Level Output
Voltage
4.4
5.4
=
(Note 2) VIN VIL or VIH
3.0
4.5
5.5
3.0
4.5
5.5
2.4
3.7
4.7
0.1
0.1
0.1
−12 mA
IOH −24 mA
−24 mA
V
V
=
IOUT 50 µA
VOL
Maximum Low
Level Output
Voltage
=
(Note 2) VIN VIL or VIH
3.0
4.5
5.5
5.5
0.50
0.50
0.50
12 mA
V
IOL 24 mA
24 mA
=
±
IIN
Maximum Input
Leakage Current
1.0
µA
VI VCC, GND
=
VOLD 1.65V Max
IOLD
IOHD
(Note 3) Minimum
Dynamic Output
Current
5.5
5.5
50
mA
mA
=
VOHD 3.85V Min
−50
5
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DC Characteristics for ’AC Family Devices (Continued)
54AC
=
Symbol
Parameter
VCC
(V)
TA
Units
Conditions
−55˚C to +125˚C
Guaranteed Limits
=
VIN VCC or GND
ICC
Maximum
Quiescent Supply
Current
5.5
80.0
µA
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
@
@
@ @
3.0V are guaranteed to be less than or equal to the respective limit 5.5V V . I for 54AC 25˚C is identical to 74AC 25˚C.
CC CC
Note 4:
I
and I
CC
IN
DC Characteristics for ’ACT Family Devices
54ACT
=
Symbol
Parameter
VCC
(V)
TA
Units
Conditions
−55˚C to +125˚C
Guaranteed Limits
=
VIH
VIL
Minimum High
Level Input Voltage
4.5
5.5
4.5
5.5
4.5
5.5
2.0
2.0
0.8
0.8
4.4
5.4
V
V
V
VOUT 0.1V
or VCC − 0.1V
=
Maximum Low
Level Input Voltage
VOUT 0.1V
or VCC − 0.1V
=
IOUT −50 µA
VOH
Minimum High
Level Output
Voltage
=
(Note 5) VIN VIL or VIH
4.5
5.5
4.5
5.5
3.70
4.70
0.1
V
V
IOH −24 mA
−24 mA
=
IOUT 50 µA
VOL
Maximum Low
Level Output
Voltage
0.1
=
(Note 5) VIN VIL or VIH
4.5
5.5
5.5
0.50
0.50
V
IOL 24 mA
24 mA
=
±
IIN
Maximum Input
Leakage Current
Maximum
1.0
µA
mA
VI VCC, GND
=
VI VCC − 2.1V
ICCT
5.5
1.6
I
CC/Input
=
VOLD 1.65V Max
IOLD
IOHD
ICC
(Note 6) Minimum
Dynamic Output
Current
5.5
5.5
50
mA
mA
=
VOHD 3.85V Min
−50
=
VIN VCC or GND
Maximum
Quiescent Supply
Current
5.5
80.0
µA
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
@ @
I for 54ACT 25˚C is identical to 74ACT 25˚C.
CC
Note 7:
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6
AC Electrical Characteristics
54AC
=
VCC
(V)
TA −55˚C
Fig.
No.
Symbol
Parameter
to +125˚C
Units
=
(Note 8)
CL 50 pF
Min
1.0
1.5
1.0
1.5
1.0
1.5
1.0
1.5
1.0
1.5
1.0
1.5
Max
16.0
12.0
15.0
11.5
16.5
13.0
15.5
12.0
17.0
13.5
15.0
11.0
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Propagation Delay
An to On
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
ns
ns
ns
ns
ns
ns
Propagation Delay
An to On
Propagation Delay
E1 or E2 to On
Propagation Delay
E1 or E2 to On
Propagation Delay
E3 to On
Propagation Delay
E3 to On
±
Note 8: Voltage Range 3.3 is 3.3V 0.3V
±
Voltage Range 5.0 is 5.0V 0.5V
AC Electrical Characteristics
54ACT
=
VCC
(V)
TA −55˚C
Fig.
No.
Symbol
Parameter
to +125˚C
Units
=
CL 50 pF
(Note 9)
Min
Max
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Propagation Delay
An to On
5.0
5.0
5.0
5.0
5.0
5.0
1.5
12.5
ns
ns
ns
ns
ns
ns
Propagation Delay
An to On
1.5
1.5
1.5
1.5
1.5
12.5
13.5
12.5
14.0
12.0
Propagation Delay
E1 or E2 to On
Propagation Delay
E1 or E2 to On
Propagation Delay
E3 to O n
Propagation Delay
E3 to O n
±
Note 9: Voltage Range 5.0 is 5.0V 0.5V
Capacitance
Symbol
Parameter
Input Capacitance
Power Dissipation
Capacitance
Typ
4.5
Units
pF
Conditions
=
VCC OPEN
CIN
CPD
=
VCC 5.0V
60.0
pF
7
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8
Physical Dimensions inches (millimeters) unless otherwise noted
20 Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
16 Lead Ceramic Dual-In-Line Package (D)
NS Package Number J16A
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16 Lead Ceramic Flatpak (F)
NS Package Number W16A
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ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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