ML7344E_技术文档

FEDL7344C/E/J-04

Issue Date: Oct 2, 2014

ML7344C/E/J

Sub-GHz(160MHz to 510MHz) band short range wireless transceiver IC

■Overview

ML7344C/E/J is a narrow band sub-GHz IC that integrates RF part, IF part, MODEM part and HOST interface

part in single-chip. It supports various frequency band from 160MHz to 510MHz. ML7344C can output 100mW

(20dBm) transimittion power and it suits for the smart-meter in Chinese market. ML7344E is suitable for Fmode

(434MHz) or N mode (169MHz) of Wireless M-Bus system. ML7344J is suitable for security radio system type III

or IV of the RCR STD-30 and specified low-power radio station in 426 MHz operation of the ARIB STD-T67.

ML7406 and ML7344 have the same package, pins assignment and

major registers.

(32pin WQFN)

ML7406 series

RF: 750MHz to 960MHz

ML7344 series

RF: 160MHz to 510MHz

Rate: 1.2kbps to 500kbps (FSK/GFSK)

Rate: 1.2kbps to 15kbps (FSK/GFSK)

Channel Spacing: 100 kHz to 1.6MHz

Channel Spacing: 25 kHz

Wireless M-Bus

IEEE802.15.4g (FEC not supported)

ARIB STD-T67

ARIB STD-T108

1000

100

10

ML7406 series

IEEE802.15.4g

(780 to 960MHz)

Wireless

M-Bus

(868MHz)

ML7344 series

Wireless

ARIB

STD T67

(426/429

MHz)

M-Bus

(169MHz)

1

0

1000

250

500

Frequency [MHz]

750

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■Features

• Frequency Range: 160 – 510MHz

• ML7344C is able to use as communication unit of Q_GDW374.3 (China)

ML7344E is able to use as F mode or N mode of the wirelss M-bus system.

ML7344J is able to use as type III or IV security radio of RCR STD-30 and ARIB STD-T67 in 426 MHz

operation. (Japan)

• High accurate modulation implemented by direct modulation scheme using fractional-N PLL.

• Multiple modulation scheme : GFSK/GMSK, FSK/MSK

• Configurable data ratres from 1.2kbps to 15 kbps

• Supports NRZ code, Manchester code and 3 out of 6 code.

• Programmable modulation frequency deviation

• Polarity conversion for TX and RX data bits

• On chip 26MHz oscillation circuit implemented (ML7344xC x=C, E or J)

Supports 26MHz TCXO input. (ML7344xT, x=C, E or J)

Note: The ordering product name is different from supporting clock source.

• On chip low speed RC oscillation circuit.

• Oscillation frequecy tuning function implemented. (ML7344xC x=C, E or J)

• Frequency tuning function (frequency fine tuning by oscillation circuit and fractional-N PLL)

• Built in Power Amp (PA) and power control function

Programmable from 100mW, 20mW and 10mW (ML7344C)

Programable from 20mW,10mW and 1mW (ML7344E/J)

• Fine output power tuning function implemented. (Tune ±0.2dB)

• TX ramp control function implemented

• High speed carrier checking function

• Support external PA

• Receive Signal Strength Indicator (RSSI) reporting function and threshold comparison function

• Built-in AFC function

• Synchronous serial peripheral interface (SPI)

• Auto wake-up and auto sleep function are implemented

• 2 genral purpose timers are implemented

• Test Pattern generation (PN9, CW, 0/1, all-1, all-0 pattern)

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• Packet mode function

• Support 2 wireless M-bus packet format. (Format A and B)

• Support general packet format (Format C)

•

Max packet length 255 bytes (Format A and B)and 2047 bytes (Format C)

64 byte TX and RX buffer are implemented

• Preamble pattern detection function (Preamble length can be prgrammable between 1 to 4 Byte)

• Programmable TX preamble length (Max 16383 Byte)

• ID code or SFD detection function (Max 4 Byte x 2codes, available for TX and RX)

• Progrmable CRC generate function for CRC32, CRC16 and CRC8

• Whitenning function

• Address filtering function

Checking C-Fieled, M-Field and A field of wireless M-bus packet (EN13575-4:2011)

• Supply voltage

1.8V to 3.6V Outpur power is set at 1mW

2.1V to 3.6V Output power is set at 10mW

2.6V to 3.6V Output power is set at 20mW

3.3V to 3.6V Output power is set at 100mW

• Operating temperature -40 to +85 ˚C

• Current consumption (operation at 400MHz band)

Deep Sleep Mode:

Sleep Mode1

Sleep Mode2

Idle Mode

0.1 uA (Typ)

0.4 uA (Typ) (Maintain Register values)

0.53 uA (Typ) (Maintain Register values and FIFO data)

0.6 mA (Typ)

TX 100mW

20mW

90 mA (Typ.)

28 mA (Typ.) (ML7344E/J)

45 mA (Typ.) (ML7344C)

22 mA (Typ.)

10mW

1mW

8.8 mA (Typ.)

RX

6.2 mA (Typ.)

• Package

32 pin WQFN 5.0mm x 5.0mm x 0.8mm

Pb free, RoHS compliant

■Ordering Guide

ML7344 x y GDZ05BL

y =C: Crystal Input

T: TCXO Input

x=C: 470MHz to 510MHz

E: 160MHz to 180MHz

J: 426MHz to 434MHz

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■Description Convention

1) Numbers description

‘0xnn’ indicates hexadecimal and ‘0bnn’ indicates binary

Example: 0x11=17 (decimal), 0b11=3 (decimal)

2) Register description

[<register name>: B<Bank No.> <register address>] register

Example: [RF_STATUS: B0 0x0B] register

Register name: RF_STATUS

Bank No.: 0

Register address: 0x0B

3) Bit name description

<bit name> ([<register name>: B<Bank No.> <register address> (<bit location>)])

Example: SET_TRX[3:0]([RF_STATUS: B0 0x0B(3-0)])

Bit name: SET_TRX

Register name: RF_STATUS

Bank No.: 0

Register address: 0x0B

Bit location: bit3 to bit0

4) In this documet

“TX” stands for transmittion.

“RX” stands for reception.

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■Block Diagram

A_MON

RESETN

ML7344C/E/J

RF

BB

ED_VAL

RSSI

PHY

SCLK

SDO

S

P

I

LNA_P

Limiter

LNA

MIX

BPF

DEMOD

SDI

SCEN

FIFO

RF_Manager

LO PLL

VCO

PA

PA_OUT

REG_PA

100mW/20mW

or

I

R

C

GPIO0

20mW/1mW

Digital

MOD

FMAP

GPIO1-3

Reg.(PA)

OSC

EXT_CLK

General

TIMER1/2

WakeUp

TIMER

REGPDIN

Reg.

VBG

TCXO

XIN XOUT

LP VB_EXT IND1

IND2

REG_OUT

REG_CORE

Fig.1 Block diagram

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■PIN Configuration

Package: 32pin WQFN

24

23

22

21

20

19

18

17

VDD_RF

LP

25

26

27

28

29

30

31

32

16

15

14

13

12

11

10

9

GPIO0

SDI

VDD_CP

IND1

SCEN

SCLK

裏面PKGꢀGND

(T.B.D.)

GND PAD

裏面PKGꢀGND

GND_VCO

IND2

SDO

REGPDIN

EXT_CLK

VDDIO

VB_EXT

VDD_VCO

1

2

3

4

5

6

7

8

Fig.2 Pin Assignment

NOTE: Pattern shown in the centre of the chip is located at bottom side of the chip (GND PAD)

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■PIN Definitions

Symbols

I

: Digital input

O

: Digital output

Is

IO

I_A

: Shmidt Trigger input

: Digital input/output

: Analog input

O_A

O_AH

IO_A

O_RF

: Analog output 1

: Analog output 2

: Analog input/output

: RF output

V_DDIO: I/O power supply

V_DDRF: RF power supply

GND

: Ground

●RF and Analog pins

Reset

state

Active

Level

20

23

24

26

28

30

31

Pin name

PA_OUT

A_MON

LNA_P

LP

I/O

O_RF

O_A

function

−

RF antenna output

Temperature information output (*1)

RF antenna input

I_A

IO_A

Pin for loop filter

IND1

Pin for VCO tankl inductor

Pin for VCO tank inductor

IND2

VB_EXT

Pin for smothing capacitor for internal bias

*1 This pin can be configured by [MON_CTRL:B0 0x4D] register, no signal assigned as default setting.

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●SPI Interface pins

Reset

state

Active

Level

Pin name

I/O

function

12

SDO

O/L

I

O

H or L SPI data output or DCLK (*1)

13

14

15

SCLK

SCEN

SDI

I_S

P or N SPI clock input

SPI chip enable

I

L

L: enable

H: disable

H or L SPI data input or DIO (*1)

*1 Please refer to “DIO function”

●Regulator pins

Reset

state

Active

Level

2

Pin name

I/O

O_AH

O_A

function

VBG (*1)

−

Pin for decouppling capacitor

Requlator1 ouput (typ. 1.5V)

REG_OUT

(*1)

3

−

I

−

H

−

4

REG_CORE

REGPDIN

Requlator2 ouput (typ. 1.5V)

Power down control pin for regulator

Fix to ‘L’ for nomal use. “H” is for deep sleep mode.

11

I

21 REG_PA (*1)

−

O_AH

Regulator output for PA block

*1 These pin will output 0V in the sleep state.

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●Miscellaneous pins

Reset

state

Active

Level

Pin name

I/O

function

XIN

N.C.(*2)

I

−

I_A

−

P or N 26MHz crystal pin1

5

−

(Note) In case of TCXO, it must be open.

O_A

I_A

I

XOUT

TCXO(*2)

6

O

P or N 26MHz crystal pin 2 or TCXO input

Reset

8

RESETN

EXT_CLK

GPIO0

I

I_S

L

L: Hardware reset enable (Forcing reset state)

H: Normal operation

Digital I/O (*3)

Reset state: External RTC (32kHz) input.

10

16

IO

P or N

H or L

IO

or

OD(*1)

IO

or

OD(*1)

IO

or

OD(*1)

IO

or

OD(*1)

Digital GPIO (*4)

Reset state: interrupt indication signal output

O/H

Digital GPIO (*5)

Reset state: clock output

17

18

19

GPIO1

O/L

H or L

ANT_SW/

GPIO2

Digital GPIO (*6)

Reset state: Antenna diversity selection control signal

TRX_SW/

GPIO3

Digital GPIO (*7)

Reset state: TX –RX selection signal control

(Note)

*1 OD is open drain output.

*2 The following pin names are different depend on products.

Pin No.

ML7344C

ML7344T

5

XIN

N.C.

6

XOUT

TCXO

(Note)

*1 In case of using TCXO, set TCXO_EN=0b1. Please make sure only one of the register TCXO_EN,

XTAL_EN is set to 0b1.

*2 For ML7344Jy, the initial value of the register TCXO_EN is 0b1. In case of using ML7344JC, the register

XTAL_EN([CLK_SET2: B0 0x03(4)])=0b1 must be programmed first.

*3 For ML7344Cy, the initial value of the register XTAL_EN is 0b1. In case of using ML7344CT, the

register TCXO_EN([CLK_SET2: B0 0x03(6)])=0b1 must be programmed first.

*4 Please refer to [EXTCLK_CTR: B0 0x52] register.

*5 Please refer to [GPIO0_CTRL: B0 0x4E] register

*6 Please refer to [GPIO1_CTRL: B0 0x4F] register

*7 Please refer to [GPIO2_CTRL: B0 0x50] register

*8 Please refer to [GPIO3_CTRL: B0 0x51] register

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●Power supply/GND pins

Reset

state

Active

Level

1

Pin name

VDD_REG

VDDIO

I/O

function

Power supply pin for Regulator

(input voltage: 1.8V to 3.3V)

Power supply for digital I/O

(input voltage: 1.8 to 3.6V)

Power supply for PA block

−

V_DDIO

−

9

22

VDD_PA

(input voltage: 18 to 3.6V, depending on TX mode)

Power supply for RF blocks

(REG-OUT is connected, typ.1.5V)

25

VDD_RF

−

V_DDRF

−

Power supply for charge pump

(REG-OUT is connected, typ.1.5V)

27

32

29

VDD_CP

VDD_VCO

GND_VCO

−

V_DDRF

GND

−

Power supply for VCO

(REG_OUT is connected, typ.1.5V)

GND for VCO

●Unused pins treatment

Unused pins treatments are as follows:

Unused pins treatment

Pins number Recommended treatment

Pin name

N.C.

5

Open

N.C.

7

GND or Open

GND

EXT_CLK

A_MON

GPIO0

GPIO1

GPIO2

GPIO3

10

23

16

17

18

19

GND

Open

(Note)

*1 If input pins are high-impedence state and leave open, excess current could be drawn. Care must be taken

that unused input pins and unused I/O pins should not be left open.

*2 After reset, GPIO1 pin is CLK_OUT function. If this function is not used, the clock must to be disabled by

setting 0b000 to GPIO1_IO_CFG[2:0] ([GPIO1_CTRL: B0 0x4F (2-0)]). If this pin is left open while

outputing clock signal, it may affect RX sensitivity.

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■Electrical Characteristics

●Absolute Maximum Ratings

Ta=-40˚C to +85˚C and GND=0V is the typical conditoin if not defined specific condition.

item

I/O Power supply

RF Power supply

symbol

V_DDIO

condition

Rating

unit

V

-0.3 to +4.6

-0.3 to +2.0

V_DDRF

V

RF input power

P_RFI

Antenna input in RX

PA_OUT(#20)

0

dBm

V

RF output Voltage

V_RFO

-0.3 to +4.6

PA_OUT(#20)

Duty Cycle of

transmission at

RF output Voltage[ML7344C]

V_RFO

-0.3 to +7.7

V

+20dBm output <1 %

Voltage on Analog Pins 1

V_A

-0.3 to +2.0

V

Voltage on Analog Pins 2

Voltage on Digital Pins

Digital Input Current

Digital Output Current

Power Dissipation

V_AH

V_D

-1.0 to +4.6

-0.3 to +4.6

-10 to +10

-8 to +8

V

IDI

mA

W

IDO

Pd

Ta= +25˚C

1.2

Storage Temperature

Tstg

−

-55 to +150

˚C

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●Recommended Operating Conditions

Item

Symbol

Conditions

Min

Typ.

Max

Unit

Power Supply (I/O)

V_DDIO

VDD_IO, VDD_REG pins

1.8

3.3

3.6

V

VDD_PA pin

TX power = 1mW

1.8

2.1

2.6

3.3

-

3.6

V

VDD_PA pin

TX power = 10mW

Power Supply (PA)

V_DDPA

VDD_PA pin

TX power = 20mW

VDD_PA pin

TX power = 100mW

Ambient Temperature

Digital input rising time

Digital input falling time

T_a

T_IR

T_IF

-

-40

+25

+85

20

ºC

ns

Digital input pins (*1)

Digital Input pins (*1)

-

20

Digital output loads

C_DL

All Digital Output pins

-

20

-

pF

Master clock frequency

Master clock accuracy

F_MCK1

A_CMCK

(*2)

(*3)

26

MHz

ppm

-10

+10

DC cut

(ML7344xT)

TCXO Input voltage

V_TCXO

0.8

-

1.5

Vpp

SPI clock frequency

SPI clock duty ratio

F_SCLK

D_SCLK

SCLK pin

0.032

45

2

16

55

MHz

%

50

ML7344C

ML7344E

ML7344J

470

160

315

-

510

180

450

RF channel frequency

F_RF

MHz

(*1) Those pins with symbol I, Is at pin definition section

(*2) XIN and XOUT pin (ML7344xC), TCXO pin (ML7344xT)

(*3) This difinition is the specification of RF communication availability, not the system requirement.

Use the appropriate frequency accuracy under each specificaton requirement as below.

Specification

Required accuracy

RCR STD-30 type III (Japan)

±10 ppm

RCR STD-30 type IV (Japan)

Wireless M-bus N mode

Wireless M-bus F mode

±4 ppm

±1.5kHz (±8.5 ppm, 4.8kbps)

±2.0kHz (±11.803 ppm, 2.4kbps)

±16 ppm

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●Power Consumption

Item

Symbol

Conditions

Deep Sleep mode

Min

Typ. (*2) Max(*3) Unit

11

I_{DD_DSLP}

-

0.1

0.4

µA

mA

(0.8)

23

(1.6)

I_{DD_SLP1}

I_{DD_SLP2}

I_{DD_SLP3}

I_{DD_SLP4}

I_{DD_IDLE}

I_{DD_RX}

Sleep mode 1 (*4)

Sleep mode 2 (*4)

Sleep mode 3 (*4)

Sleep mode 4 (*4)

Idle mode(*5)

-

25.8

(1.9)

0.53

0.7

26

(2.1)

28

(4.1)

2.14

0.6

-

RF RX mode (*6)(*7)

LOW_RATE_EN([CLK_SET2:

5.9

Power Consumption

(*1)

RF TX mode (1mW) (*6)

For ML7344E/J

I_{DD_TX1}

-

8.8

-

mA

I_{DD_TX10}

RF TX mode (10mW) (*6)

For ML7344E/J

-

22.0

28.0

45.0

90

-

mA

(*6)

RF TX mode

(20mW)

I_{DD_TX20}

For ML7344C

(*7)

RF TX mode (100mW) (*7)

For ML7344C

I_{DD_TX100}

I_{DD_XTAL}

X’tal Oscillator Circuit (*8)

0.3

(*1) Power consumption is sum of current consumption of all power supply pins

(*2) “Typ” value is centre value under condition of VDDIO=3.3V, 25˚C.

(*3) () is a reference maximum value under condition of 25˚C

(*4) The definition od each sleep mode is shown in following table.

RC Osc.

(32kHz)

Low clock

timer

Mode.

Register

FIFO

Sleep mode 1

Sleep mode 2

Sleep mode 3

Sleep mode 4

Not retain

Retain

Not retain

Retain

OFF

-

OFF

External Input

ON

-

Retain

ON

Retain

(*5) Under condition of using TCXO.

(*6) Under condition of data receiving speed at 9.6 kbps and 426 MHz operation.

(*7) Under condition of data receiving speed at 9.6 kbps and 490 MHz operation.

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(*8) When using ML7344xC, power consumptions of each mode exluded Deep Sleep and Sleep are added

I_{DD_XTAL}

.

●DC characteristics

Item

Symbol

Conditions

Min

Typ. (*2)

Max

Unit

V_DDIO

*0.75

VIH1

Digital input/inout pins

V_DDIO

V

-

Voltage Input High

VIH2

VIL1

VIL2

VT+

XIN pin

1.35

1.5

V

-

V_DDIO

*0.18

Digital input/inout pins

XIN pin

0

-

Voltage Input Low

0.15

-

Schmit Trigger

Threshold High level

Digital pins with shmitt trigger

gate

V_DDIO

*0.75

1.2

Schmit Trigger

Threshold Low level

Digital pins with shmitt trigger

gate

V_DDIO

*0.18

VT-

0.8

V

-

IIH1

IIL1

IIL2

Digital input pins

XIN pin

-1

1

μA

-

Input leakage current

-0.3

0.3

IOZH

IOZL

VOH

VOL

EXT_CLK, GPIO0-3 pins

IOH=-4mA

-1

1

μA

V

-

Tri-state output

leakage current

V_DDIO

*0.8

Voltage ouput level H

Voltage ouput evel L

V_DDIO

0.3

IOL=4mA

0

V

REG_CORE and

REG_OUTpin

When in mode other than

MAIN_REG

SUB_REG

1.4

1.5

1.6

V

Regulator output

voltage

REG_CORE pin

When in sleep mode

0.95

1.65

CIN

Input pins

6

9

pF

-

COUT

CRFIO

Output pins

RF inout pins

Pin capacitance

CAI

Analog input pins

9

pF

-

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●RF characteristics

Data Rate

:

1.2 kbps to 15 kbps

2-GFSK/ 2-FSK

25kHz

Modulation scheme

Channel spacing

Definisiton Point

ANT connector of ML7344 RF board.

[RF frequency]

Item

Condition

Min

Typ.

Max

Unit

ML7344C

470

-

510

MHz

LNA_P,PA_OUT pins

ML7344E

ML7344J

160

315

-

180

450

MHz

NOTE:1) Support 160 MHz to 510 MHz by changing L and C components between IND1 and IND2 pins

2) Integer multiples of the master clock frequency and its around frequency can not be used. Please refer

section of “Programing Channel Frequency ”

[TX characteristics]

170MHz and 426MHz Band (160MHz to 180MHz, 315MHz to 450MHz) [ML7344E/J]

Item

Condition

Min

Typ.

Max

Unit

20mW(13dBm) mode

10

13

13.8

dBm

TX Power

10mW(10dBm) mode

1mW(0dBm) mode

7

-3

10

0

-

10.8

0.8

dBm

kHz

Frequency deviation setting

range [Fdev]

0.025

8.5

400

11.8

Occupied bandwidth

9600 bps (PN9), Fdev=3 kHz

Band including 99% power

Offset:25 kHz ±8 kHz band

-

Adjacent Channel Power

9600bps (PN9), Fdev=3 kHz

-

-40

-26

dB

+10dBm output

9600 bps (PN9). Fdev = 3 kHz

Total power from 62.5 kHz to

162.5kHz offset

dBm

Spurious emission level

Harmonics

+10dBm output with LC trap

filter

-

-26

dBm

9600 bps (PN9). Fdev = 3 kHz

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470MHz BAND(470MHz to 510MHz) [ML7344C]

Item Condition

Min

Typ.

Max

Unit

100mW(20dBm) mode

18.5

20

23

dBm

TX Power

20mW(13dBm) mode

10

0.025

8.5

-

13

-

16

400

11.8

-36

dBm

kHz

dBm

Frequency Deviation (Fdev)

Range

Occupied bandwidth

9600 bps (PN9), Fdev=3 kHz

Spurious emission level

Band including 99% power

-

Harmonics

+20dBm output with LC trap filter

-

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[RX characteristics]

426MHz Band (315MHz to 450MHz) [ML7344J]

Item

Condition

Min

Typ.

Max

Unit

4.8 kbps, Fdev=3kHz

9.6 kbps, Fdev=3kHz

-

-115

-108

dBm

-

-114

-118

-107

-111

dBm

Minimum RX sensitivity

BER<0.1%

4.8 kbps, Fdev=3kHz

High Gain Mode

9.6 kbps, Fdev=3kHz

High Gain Mode

-

-117

3

-110

dBm

dB

±12.5 kHz

-

Adjacent channel rejection

±25 kHz

30

-

33

36

69

72

75

80

±50 kHz

1 MHz offset

2 MHz offset

6 MHz offset

10 MHz offset

-

Blocking (426MHz operation)

-

-400kHz offset (image

frequency), Ta=25 ºC

After I/Q adjustment

30

40

-

dB

RFmin in Figure of

RSSI

characteristics*1

-

-115

-120

40

-

dBm

dB

Minimum power detection level

High Gain

Mode

-

Dynamic Range in

Figure of RSSI

characteristics*1

Power detection range

Spurious Emission level

High Gain

Mode

35

-

dB

Compliant with FCC, ARIB,

ETSI standard

-

-54

dBm

*1. RSSI characteristics as shown follow.

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ED

EDmax

Measured Point

Calculated Point

EDmin

No Input

-60

-100

-80

RF input level

RFmax

RFmin

Dynamic Range

470MHz BAND(470MHz to 510MHz) [ML7344C] High Gain Mode

Item

Condition

4.8 kbps, Fdev=3kHz

(BER<0.1%)

Min

Typ.

Max

Unit

-

-116

-115

-118

-

dBm

9.6 kbps, Fdev=3kHz

(BER<0.1%)

-

dBm

Minimum RX sensitivity

4.8 kbps, Fdev=3kHz

(BER<1%)

9.6 kbps, Fdev=3kHz

(BER<1%)

-

-117

55

65

-

dBm

dB

Adjacent channel rejection

±200kHz

1 MHz offset

2 MHz offset

6 MHz offset

10 MHz offset

dB

66

dB

71

dB

Blocking

73

dB

-400kHz offset (image

frequency),

Ta=25 ºC After I/Q adjustment

-

40

-

dB

RFmin in Figure of RSSI

characteristics*1

Minimum power detection level

-120

dBm

Dynamic Range in Figure of

RSSI characteristics*1

Power detection range

Spurious Emission level

-

35

-

dB

Compliant with FCC, ARIB,

ETSI standard

-54

dBm

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170MHz Band [ML7344E]

Item

Condition

Min

Typ.

Max

Unit

4.8 kbps, Fdev=3kHz

-

-115

-

dBm

9.6 kbps, Fdev=3kHz

-

-114

-118

-

dBm

Minimum RX sensitivity

BER<0.1%

4.8 kbps, Fdev=3kHz

High Gain Mode

9.6 kbps, Fdev=3kHz

High Gain Mode

-

-117

3

-

dBm

dB

±12.5 kHz

Adjacent channel rejection

±25 kHz

33

36

69

72

75

80

±50 kHz

1 MHz offset

2 MHz offset

6 MHz offset

10 MHz offset

Blocking (426MHz operation)

-400kHz offset (image

frequency), Ta=25 ºC

After I/Q adjustment

-

40

-

dB

RFmin in Figure of

RSSI

characteristics*1

-

-115

-120

40

-

dBm

dB

Minimum power detection level

High Gain

Mode

-

Dynamic Range in

Figure of RSSI

characteristics*1

Power detection range

Spurious Emission level

High Gain

Mode

35

-

dB

Compliant with FCC, ARIB, ETSI

standard

-

-54

dBm

●RC oscillator circuit characteristics

Item

Symbol

Condition

Min

Typ.

Max

Unit

Oscillation Frequency

F_RCOSC

-

44

-

kHz

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●SPI interface characteristics

Item

Symbol

Condition

Min

0.032

30

Typ.

2

Max

16

−

Unit

MHz

ns

SCLK clock frequency

SCEN input setup time

SCEN input hold time

SCLK high pulse width

SCLK low pulse width

SDI input setup time

SDI input hold time

SCEN negate time

FSCLK

TSCENSU

TSCENH

TSCLKH

TSCLKL

TSDISU

−

30

−

ns

28

−

ns

Load capacitance

CL=20pF

28

−

ns

5

−

ns

TSDIH

15

−

ns

TSCENNI

TSDODLY

200

−

ns

SDO output delay time

−

22

ns

NOTE: All timing parameter is defined at voltage level of V_DDIO* 20% and V_DDIO* 80%.

SCEN

T_SCENH

F_SCLK

T_SCENSU

T_SCLKL

SCLK

T_SCLKH

T_SDIH

MSB IN

T_SDISU

SDI

BITS6-1

LSB IN

LSB

T_SDODLY

MSB OUT

SDO

T_SCENNI

SCEN

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●DIO interface characteristics

Item

Symbol

T_DISU

Condition

Min

Typ.

Max

Unit

DIO Input setup time

1

-

µs

DIO Input hold time

DIO Output hold time

T_DIH

0

-

ns

T_DOH

20

DCLK frequency

accuracy in TX (*1)

F_{DCLK_TX}

Load capacitance

CL=20pF

(*3)

-30

-

(*3)

+30

kHz

%

DCLK frequency

accuracy in RX (*2)

F_{DCLK_RX}

DCLK output duty ratio

(TX)

D_{DCLK_TX}

D_{DCLK_RX}

45

30

-

55

70

%

DCLK output duty ratio

(RX)

(*1) DCLK clock frequency in TX mode will be varied depending on the variance of master clock frequency.

(*2) DCLK clock frequency in RX mode will be varied by reproduced clock and its jitter.

(*3) These values are equal to the accuracy of the master clock frequency

NOTE: All timing parameter is defined at voltage level of V_DDIO* 20% and V_DDIO* 80%.

F_{DCLK_TX}/ F_{DCLK_RX}

DCLK

T_DISU

T_DIH

DIO(input)

VALID

T_DOH

VALID

DIO(output)

VALID

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●Clock output characteristics

ML7344x has configurable clock output function. It is controlled by [MON_CNTRL: B0 0x4D] register and

[GPIOn_CTRL: B0 0x4E-0x51)] registers (n=0 to 3),. Default settign is the 3.33MHz clock is output from

GPIO1.

Item

Symbol

Condition

Min

Typ.

Max

Unit

Clock output frequency

F_CLKOUT

0.0064

3.33

26

MHz

Load

8.66 MHz

33

48

-

67

52

%

capacitance

CL=20pF

Clock output duty ratio

D_CLKOUT

Other than

8.66 MHz

50

F_CLKOUT

GPIOn

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ML7344C/E/J

●Reset characteristics

Symbo

Item

Condition

Min

Typ.

Max

Unit

RESETN delay time

(Power on)

All power supply pins

(After power on)

T_RDL1

0.5

-

ms

RESETN pulse period

When starting from

VDDIO=0V

T_RPW1

200

1.5

-

ns

RESETN pulse period 2

When starting from

VDDIO≠0V

VDDIO > 1.8V should be

required.

T_RPW2

ms

RESETN input delay time

(When ML7344 start up

from VDDIO≠0V)

T_RDL2

VDDIO > 1.8V

1

-

µs

RESETN rising time

T_RRST

1

ms

VDD level

GND level

1.8V

VDDIO

Less than 1.8V

TRDL2

TRPW1

TRPW2

TRDL1

RESET

TRRST

NOTE: When ML7344 start up from VDDIO≠0V, RESETN pulse should be asserted after VDDIO becomes over

1.8V.

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●Deep Sleep mode characteristics

Item

Symbol

Condition

Min

Typ.

Max

Unit

REGPDIN assert delay

time

T_RPFD

0

-

µs

REGPDIN assert time

T_RPASS

T_REFD

VDDIO = “H”

1.2

0.5

-

ms

RESETN release delay

time

VDD level

GND level

VDDIO

T_RPFD

T_REFD

RESETN

T_RPASS

REGPDIN

●Power-on characteristics

Item

Symbol

T_PWON

Condition

Min

Typ.

Max

Unit

Power on state

(All power supply pins)

Power on time

-

5

ms

T_PWON

80%

VDD level

GND level

VDD

20%

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ML7344C/E/J

■Function description

●HOST Interface

●Serial Peripheral Interface (SPI)

ML7344 has a SPI, which supports slave mode. Host MCU can read/write to the ML7344 registers and

on-chip FIFO using MCU clock. Single access and burst access are also supported.

[Single Access Mode Timing Chart]

In write operation, data will be stored into internal register at rising edge of clock which is capturing D0 data.

During write operation, if setting SCEN line to “H”, the data will not be stored into register. For more details of

SCEN negate timing, please refer to the “SPI interface characteristics”. Afetr the internal clock is stabilized,

data will be written into the register in syncrohonization with the internal clock.

[Write]

SCLK

SCEN

A

6

A

0

D

7

D

0

SDI

“1”

W

Write data field

Address field

(Register write timing)

Before clock stable

After clock stable

D7-0

Up to 0.45 µs

[Read]

SCLK

SCEN

A

6

A

0

SDI

“0”

R

Address field

SDO

D

0

D

7

Data read field

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[Burst Access Mode Timing Chart]

By maintaining SCEN line as “L”, burst access mode will be active. By setting SCEN line to “H”, exiting

from the burst access mode. During burst access mode, address will be automatically incremented.

When SCEN line becomes “H” before Clock for D0 is input, data transaction will be aborted.

NOTE:

If destination is [WR_TX_FIFO:B0 0x7C] or [RD_FIFO:B0 0x7F], address will not be increment. And

continuous FIFO access is possible.

[Write]

SCLK

SCEN

A

6

A

0

D

7

D

0

SDI

“1”

W

Write data field

Address field

(Register write timing)

Before clock stable

After clock stable

D7-0

Up to 0.45µs

[Read]

SCLK

SCEN

A

0

“0”

R

SDI

6

Address field

SDO

D

7

D

0

Read data field

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●LSI state transition control

●LSI State transition instruction

State can be controlled from MCU by setting registers below.

State transition command

TX_ON

Instruction

SET_TRX([RF_STATUS:B0 0x0B(3-0)])=0b1001

SET_TRX([RF_STATUS:B0 0x0B(3-0)])=0b0110

SET_TRX([RF_STATUS:B0 0x0B(3-0)])=0b1000

SET_TRX([RF_STATUS:B0 0x0B(3-0)])=0b0011

SLEEP_EN([SLEEP/WU_SET:B0 0x2D(0)])=0b1

VCO_CAL_START([VCO_CAL_START:B0 0x6F(0)])=0b1

RX_ON

TRX_OFF

Force_TRX_OFF

SLEEP_EN

VCO_CAL_EN

State can be changed without command from MCU. If one of the following condition is met, state is changed

automatically according to the following table. In order to enable these functions, the following registers must

be programmed.

Function

Control bit name

Automatic TX_ON after FIFO write completion (AUTO_TX)

Automatic TX_ON during FIFO write (FAST_TX)

RF state setting after packet transmission completion

RF state setting after packet reception completion

AUTO_TX_EN([RF_STATUS_CTRL:B0 0x0A(4)])

FAST_TX_EN([RF_STATUS_CTRL:B0 0x0A(5)])

TXDONE_MODE[1:0]([RF_STATUS_CTRL:B0 0x0A(1-0)])

RXDONE_MODE[1:0]([RF_STATUS_CTRL:B0 0x0A(3-2)])

WAKEUP_MODE([SLEEP/WU_SET:B0 0x2D(6)])

WAKEUP_EN([SLEEP/WU_SET:B0 0x2D(4)])

Automatic RX_ON/TX_ON by Wake-up timer

Automatic VCO calibration after exit from SLEEP

Automatic SLEEP by timer

AUTO_VCOCAL_EN([VCO_CAL_START:B0 0x6F(4)])

WU_DURATION_EN([SLEEP/WU_SET:B0 0x2D(5)])

FAST_DET_MODE_EN([CCA_CTRL:B0 0x39(3)])

PLL_LD_EN([PLL_LOCK_DETECT:B1 0x0B(7)])

Automatic SLEEP by high speed carrier checking mode

Force_TRX_OFF after PLL unlock detection during TX

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●State Diagram

Each state transition control is described in the following state diagram.

TRX_OFF

Force_TRX_OFF

SLEEP

TRX_OFF

Force_TRX_OFF

SLEEP

RECEIVE

TRASMIT

Force_TRX_OFF

SLEEP

Force_TRX_OFF

SLEEP

RX completion

(TRX_OFF)

RX start

(SyncWord detection)

TX completion

(TRX_OFF)

TX start

TRX_OFF

Force_TRX_OFF

SLEEP

TX_ON

TRX_OFF

Force_TRX_OFF

SLEEP

TRX_OFF

Force_TRX_OFF

SLEEP

RX_ON

TX_ON

RX_ON

TX_ON

TRX_OFF

Force_TRX_OFF

SLEEP

RX_ON

TX_ON

RX_ON

TX_ON

RX_ON

PLLWAIT

TX_ON

RX_ON

VCO_CAL

SLEEP

Start VCO_CAL

VCO_CAL

completion

TRX_OFF

IDLE

Force_TRX_OFF

VCO_CAL completion

SLEEP

Start VCO_CAL

Exit from

DEEP SLEEP

VCOCAL

Exit from SLEEP

DEEP

SLEEP

DEEP

SLEEP

Exit from

SLEEP

Exit from

DEEP SLEEP

State transition instruction

Pins control

[STATE]

DEEP SLEEP

SLEEP

: DEEP SLEEP

: SLEEP

TRX_OFF/IDLE

PLL_WAIT

TX_ON

TRANSMIT

RX_ON

: IDLE (TX-RX stand-by)

: PLL stand-by

: TX ready (TX data waiting)

: TX on-going

: RX stand-by (RX data waiting)

: RX on-going

: VCO calibration

Normal sequence

(state transition)

Command from

Higher layer state

RECEIVE

VCO_CAL

ML7344 Self controlled state transition

Fig.3 LSI state diagram

28/151

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●SLEEP setting

Deep SLEEP mode: Powers for all blocks except for IO pins are turned off.

SLEEP mode: Main regulator and 26MHz oscillation circuits are turned off. But sub-regulator is turned-on.

The following registers can be programmed to control SLEEP state

Function

Power control

Wake-up setting

Control bit name

PDN_EN([SLEEP?WU_SET:B0 0x2D(1)])

WAKEUP_EN([SLEEP/WU_SET:B0 0x2D(4)])

Wake-up timer clock source setting WUT_CLK_SOURCE([SLEEP/WU_SET:B0 0x2D(2)])

Internal RC oscillator control RC32K_EN([CLK_SET2:B0 0x03(3)])

Setting method and internal state for DEEP_SLEEP and various SLEEP modes are as follows:

SLEEP mode

Setting method

RESETN pin=”L”

DEEP_SLEEP

SLEEP1

OFF OFF OFF OFF OFF OFF

REGPDIN pin=”H”

[SLEEP/WU_SET: B0 0x2D(4-0)] = 0b0_1011 (*2)

[CLK_SET2: B0 0x03(3)] = 0b0 (default)

[SLEEP/WU_SET: B0 0x2D(4-0)] = 0b0_1001 (*2)

[CLK_SET2: B0 0x03(3)] = 0b0 (default)

[SLEEP/WU_SET: B0 0x2D(4-0)] = 0b1_1001 (*2)

[CLK_SET2: B0 0x03(3)] = 0b0 (default)

[SLEEP/WU_SET: B0 0x2D(4-0)] = 0b1_1101 (*2)

[CLK_SET2: B0 0x03(3)] = 0b1

OFF

ON

OFF OFF OFF OFF

OFF

SLEEP2

OFF

ON

(*1)

SLEEP3

OFF OFF

ON

SLEEP4

OFF

ON

(*1) Low speed clock is supplied from EXT_CLK pin.

(*2) Please set proper value to [SLEEP/WU_SET: B0 0x2D(3)].

NOTE: Contents of registers are not kept during DEEP_SLEEP. Contents of registers are kept during SLEEP1, SLEEP2,

SLEEP3 and SLEEP4.

However, in SLEEP1 mode, contents of TX FIFO and RX FIFO are not kept, because power to FIFO is turned off.

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●Notes to set RF state

ML7344 is able to change the internal RF state transition autonomously (without commands from MCU) as

well as RF state change commands from MCU. (please refer to ”LSI state transition instruction”). If both

timing of operation (autonomous state and state change from MCU command) overlapped, unintentional RF

state may occur. Timing of autonomous state RF change is described in the following table.

Care must be taken not to overlap the conditions.

RF state change

(before → after)

RF state transition timing (not from

Host MCU command)

Function

Recommended process

Automatic TX

After TX data transfer completion interrupt

occurs, {value [TX_RATE_H/L: B1 0x02/03)] ×

2 / 26}[μs] period

TRX_OFF/RX_ON

FAST_TX

mode

When FIFO write access exceed trigger level

+1, {value [RX_RATE1_H/L:B1 0x04/05] × 5 /

26}[μs] period.

→TX_ON

Write access to [RF_STATUS:B0

0x0B] is possible after RF state

transition completion interrupt

(INT[3] group1), or move to the

state defined by GET_TRX

([RF_STATUS:B0 0x0B(7-4)]).

RF state setting

after

TX_ON→TRX_OFF

TX_ON→RX_ON

TX_ON→SLEEP

RX_ON→TRX_OFF

RX_ON→TX_ON

RX_ON→SLEEP

After TX completion interrupt (INT[16] group3),

{value [TX_RATE_H/L:B1 0x02/03] × 2 / 26}

[μs] period

TX completion

RF state setting

after

After RX completion interrupt (INT[8] group2),

{value [RX_RATE1_H/L:B1 0x04/05] × 2 /

26}[μs] period

RX completion

Wake-up timer

After wake-up timer completion interrupt

(INT[6] group1), 1 clock cycle period defined by

WUT_CLK_SET[3:0] ([WUT_CLK_SET: B0

0x2E(3-0)]).

SLEEP→TX_ON

SLEEP→RX_ON

SLEEP→VCO_CAL

→TX_ON

After wake-up timer completion interrupt

(INT[6] group1), before VCO calibration

completion interrupt (INT[1] group1).

Write access to [RF_STATUS:B0

0x0B] and BANK2 is possible

after VCO calibration completion

interrupt (INT[1] group1).

SLEEP→VCO_CAL

→RX_ON

Continuous

After continuous operation timer completion, 1 Write access to [RF_STATUS:B0

TX_ON→SLEEP

RX_ON→SLEEP

operation timer

clock cycle period defined by WUT_CLK_SET

[3:0] ([WUT_CLK_SET: B0 0x2E(3-0)]).

0x0B] is possible after RF state

transition completion interrupt

(INT[3] group1), or move to the

state defined by GET_TRX

High speed

After CCA completion interrupt (INT[18]

RX_ON→SLEEP

([RF_STATUS:B0 0x0B(7-4)]).

carrier checking

group3), duration 6.3[μs].

PLL unlock

detection

After PLL unlock detection interrupt (INT[2]

Write access to [RF_STATUS:B0

0x0B] is possible 147μs after PLL

unlock interrupt (INT[2] group1)

detected.

group1) occurs, duration 147[μs].

TX_ON→TRX_OFF

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●Packet Handling Function

●Packet format

ML7344 supports Wireless M-BUS frame FormatA/B, and Format C which is non Wireless M-BUS universal

format. The following packet handling are supported in FIFO mode or DIO mode

1) Preamble and SyncWord automatic insertion (TX)

2) Preamble and SyncWord automatic detection (RX)

3) Preamble and SyncWord automatic deletion (RX)

4) CRC data insertion (TX)

--- DIO/FIFO mode

--- DIO/FIFOmode

--- DIO/FIFO mode

--- FIFO mode

5) CRC check and error notification (RX)

--- DIO/FIFO mode

The following table shows the control bit relating with Packet format function.

Function

Packet format setting

Control bit name

PKT_FORMAT[1:0] ([PKT_CTRL1: B0 0x04(1-0)])

RX_EXTPKT_OFF ([PKT_CTRL1: B0 0x04(3)])

DAT_LF_EN ([PKT_CTRL1: B0 0x04(4)])

LEN_LF_EN ([PKT_CTRL1: B0 0x04(5)])

RX extended link layer mode disable

Data area bit order setting

Length area bit order setting

Extended link layer mode setting

Length field setting

EXT_PKT_MODE[1:0] ([PKT_CTRL1: B0 0x04(7-6)])

LENGTH_MODE ([PKT_CTRL2: B0 0x05(0)])

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(1) Format A (Wireless M-BUS)

By setting PKT_FORMAT[1:0] ([PKT_CTRL1: B0 0x04(1-0)])=0b00, Wireless M-BUS Format A is selected.

Format A consists of 1^stBlock, 2^ndBlock and Optional Block(s). Each block has 2 bytes of CRC. “L-field” (1^st

byte of 1^stBlock) indicates packet length, which includes subsequenct user data bytes from “C-field”. However,

CRC bytes and postanble are excluded. Depending on “L-field” value, 2^ndBlock and Optional Block(s) are added.

The following [] indicates register address [bank #, address].

Manchester/3-out-of-6 applicable [B0 0x07(3-2, 1-0)]

CRC applicable

1st Block

CRC applicable

2nd Block

CRC applicable

LSB

MSB

Length

Optional Block

Sync

Word

Preamble

Postamble

L

C

M

A

CRC

Data

field

CRC

field

CI

field

Data

field

CRC

field

field field field field field

> n*2(*1)

bits

Max.15

bytes

0/2-8

bits

10/18/

32bits

1

byte

2

Max.16

bytes

1

2

6

2

bytes

byte byte bytes bytes bytes

bytes

[B0 0x07] [B0 0x08]

(*2)

[B0 0x44]

[B1 0x25-2E]

[B0 0x42]

[B0 0x43]

(*3)

(*4)

[B0 0x05]

[B0 0x7A/7B, 7D/7E]

TX: automatic insertion

RX: automatic detection, deletion

*1: Each mode has different minimum value of n.

*2: Indicates TX FIFO data storage area size.

*3: Indicates RX FIFO data storage area size.

*4: When RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)])=0b10, indicates DCLK/DIO output area.

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Extended Link Layer Format

If “CI-field” (1^stbyte of 2^ndBlock)=0x8C or 0x8D, Extended Link Layer is applied. The packet format is as

follows:

(1) CI-field = 0x8C

For TX, if 2 bytes extention format is used, set EXT_PKT_MODE[1:0] ([PKT_CTRL1: B0 0x04(7-6)])=0b01.

For RX, if RX_EXTPKT_OFF([PKT_CTRL1: B0 0x04(3)])=0b0, ML7344 recognizes “CI-field” and RX

operation is processed.

Manchester/3-out-of-6 applicable [B0 0x07(3-2,1-0)]

CRC applicable

LSB

MSB

Extended

Length

1st Block

(*1)

2nd Block

Optional Block

Block

Sync

Word

Preamble

Postamble

L

C to CRC CI CC ACC

Data CRC

field

CI

field

Data

field

CRC

field

field field field

field

> n*2(*1)

bits

Max.12

bytes

0/2-8

bits

10/18/

32bits

1

byte

2

Max.16

bytes

1

byte

11

bytes

1

2

bytes

byte byte byte

bytes

(*2)

[B0 0x07]

[B0 0x42]

[B0 0x43]

[B0 0x08]

[B1 0x25-2E]

[B0 0x44]

(*3)

(*4)

[B0 0x05]

[B0 0x7A/7B, 7D/7E]

TX: automatic insertion

RX: automatic detection, deletion

*1: 1^stBlock is identical to normal Format A.

*2: Indicates TX FIFO data storage area size.

*3: Indicates RX FIFO data storage area size.

*4: When RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)])=0b10, indicates DCLK/DIO output area.

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(2) CI-field = 0x8D

For TX, if 8 bytes extention format is used, set EXT_PKT_MODE[1:0] ([PKT_CTRL1: B0 0x04(7-6)])=0b10.

For RX, if RX_EXTPKT_OFF([PKT_CTRL1: B0 0x04(3)])=0b0, ML7344 recognizes “CI-field” and RX

operation is processed.

Manchester/3-out-of-6 applicable [B0 0x07(3-2,1-0)]

CRC applicable

LSB

MSB

Extended

Block

Optional

Block

1st Block

(*1)

2nd Block

Length

Sync

Word

Preamble

Postamble

CC

field

L

C - CRC CI

ACC

field

Data CRC

field field

CI

field

Data

field

SN CRC

field field

CRC

field

field field field

> n*2(*1)

bits

Max.15

2

0/2-8

bits

10/18/

32bits

1

byte

1

byte

Max.16

1

11

1

byte

4

2

bytes

bytes bytes

byte bytes byte

bytes bytes

bytes

(*2)

[B0 0x07]

[B0 0x42] [B1 0x25-2E]

[B0 0x08]

[B0 0x44]

[B0 0x43]

(*3)

(*4)

[B0 0x05]

[B0 0x7A/7B, 7D/7E]

TX: automatic insertion

RX: automatic detection, deletion

*1: 1^stBlock is identical to normal Format A.

*2: Indicates TX FIFO data storage area size.

*3: Indicates RX FIFO data storage area size.

*4: When RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)])=0b10, indicates DCLK/DIO output area.

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(2) Format B (Wireless M-BUS)

By setting PKT_FORMAT[1:0] ([PKT_CTRL1: B0 0x04(1-0)])=0b00, Wireless M-BUS Format B is selected.

Format B consists of 1^stBlock, 2^ndBlock and Optional Block(s). Each block has 2 bytes of CRC. “L-field” (1^st

byte of 1^stBlock) indicates packet length, which includes subsequenct user data bytes from “C-field”. However,

unlike Format A, CRC bytes are included. (postanble are excluded.) Depending on “L-field” value, 2^ndBlock and

Optional Block(s) are added.

The following [] indicates register address [bank #, address].

Manchester/3-out-of-6 applicable [B0 0x07(3-2,1-0)]

CRC applicable

LSB

MSB

2nd Block

Length

Optional Block

1st Block

Sync

Word

Preamble

Postamble

L

C

M

A

CRC

field

CI

Data

field

Data

field

CRC

field

field field field

field

> n*2(*1)

bits

10/18/

32bits

2

Max.126

bytes

0/2-8

bits

1

byte

Max.115

bytes

1

2

6

2

bytes

byte byte bytes bytes

bytes

(*2)

[B0 0x07]

[B0 0x42]

[B0 0x43]

[B0 0x08]

[B1 0x25-2E]

[B0 0x44]

(*3)

(*4)

[B0 0x05]

[B0 0x7A/7B, 7D/7E]

TX: automatic insertion

RX: automatic detection, deletion

*1: Each mode has different minimum value of n.

*2: Indicates TX FIFO data storage area size.

*3: Indicates RX FIFO data storage area size.

*4: When RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)])=0b10, indicates DCLK/DIO output area.

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Extended Link Layer Format

If “CI-field” (1^stbyte of 2^ndBlock)=0x8C or 0x8D, Extended Link Layer is applied. The packet format is as

follows:

(1) CI-field = 0x8C

For TX, if 2 bytes extention format is used, set EXT_PKT_MODE[1:0] ([PKT_CTRL1: B0 0x04(7-6)])=0b01.

For RX, if RX_EXTPKT_OFF([PKT_CTRL1: B0 0x04(3)])=0b0, ML7344 recognizes “CI-field” and RX

operation is processed.

Manchester/3-out-of-6 applicable [B0 0x07(3-2,1-0)]

CRC applicable

LSB

MSB

Extended

Block

1st Block

(*1)

2nd Block

Length

Optional Block

Sync

Word

Preamble

Postamble

L

field

C, M, A

field

CI CC ACC

field field field

Data CRC

CI

field

Data

field

CRC

field

> n*2(*1)

bits

Max.112

bytes

0/2-8

bits

10/18/

32bits

1

byte

2

Max.126

bytes

1

byte

9

1

2

bytes

byte byte byte

bytes

(*2)

[B0 0x07]

[B0 0x42]

[B0 0x43]

[B0 0x08]

[B1 0x25-2E]

[B0 0x44]

(*3)

(*4)

[B0 0x05]

[B0 0x7A/7B, 7D/7E]

TX: automatic insertion

RX: automatic detection, deletion

*1: 1^stBlock is identical to normal Format B.

*2: Indicates TX FIFO data storage area size.

*3: Indicates RX FIFO data storage area size.

*4: When RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)])=0b10, indicates DCLK/DIO output area.

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(2) CI-field = 0x8D

For TX, if 8 bytes extention format is used, set EXT_PKT_MODE[1:0] ([PKT_CTRL1: B0 0x04(7-6)])=0b10.

For RX, if RX_EXTPKT_OFF([PKT_CTRL1: B0 0x04(3)])=0b0, ML7344 recognizes “CI-field” and RX

operation is processed.

Manchester/3-out-of-6 applicable [B0 0x07(3-2,1-0)]

CRC applicable

2nd Block

CRC applicable

LSB

MSB

Extended

Length

Optional

Block

1st Block

(*1)

Block

Sync

Word

Preamble

Postamble

CC

field

L

C,M,A CI

field field field

ACC

field

Data CRC

CI

Data

field

SN CRC

field field

CRC

field

> n*2(*1)

bits

Max.106

bytes

0/2-8

bits

10/18/

32bits

1

byte

1

byte

2

Max.126

1

9

1

byte

4

2

bytes bytes

byte bytes byte

bytes bytes

bytes

(*2)

[B0 0x08]

[B1 0x25-2E]

[B0 0x07]

[B0 0x42]

[B0 0x43]

(*2)

[B0 0x44]

(*3)

(*4)

[B0 0x05]

[B0 0x7A/7B, 7D/7E]

TX: automatic insertion

RX: automatic detection, deletion

*1: 1^stBlock is identical to normal Format B.

*2: Indicates TX FIFO data storage area size.

*3: Indicates RX FIFO data storage area size.

*4: When RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)])=0b10, indicates DCLK/DIO output area.

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(3) Format C (non Wireless M-BUS, general purpose format)

By setting PKT_FORMAT([PKT_CTRL1: B0 0x04(1-0)])=0b10, Format C, which is non Wireless M-BUS

format, is selected. Format C consists of 1^stBlock only, which has 2 bytes of CRC. “L-field” indicates packet

length, which includes subsequent user data bytes, including CRC bytes. The length of “L-field” is defined by

LENGTH_MODE ([PKT_CTRL2:B0 0x5(0]). Data Whitening function is supported.

The following [] indicates register address [bank #, address].

Manchester/3-out-of-6 applicable [B0 0x07(3-2,1-0)]

Whitening applicable [B0 0x08(0)]

CRC applicable

LSB

MSB

Length

1st Block

Sync

Word

Preamble

Postamble

Data

field

L

field

CRC

field

> n*2(*1)

bits

Max.2047

bytes

0/2-8

bits

Max.

32bits

1/2

byte

0/1/2/4

bytes

[B0 0x07] [B0 0x08]

[B0 0x42] [B1 0x25-2E]

[B0 0x43]

(*2)

[B0 0x05]

[B0 0x7A/7B]

[B0 0x7D/7E]

[B0 0x44]

(*3)

(*4)

TX: automatic insertion

RX: automatic detection, deletion

*1: Preamble length (n) is programable by [TXPR_LEN_H/L: B0 0x42/43] registers.

*2: Indicates TX FIFO data storage area size.

*3: Indicates RX FIFO data storage area size.

*4: When RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)])=0b10, indicates DCLK/DIO output area.

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●CRC function

ML7344 has CRC32,CRC16 and CRC8 function. CRC is calculated and appended to TX data. CRC is

checked for RX data. The following modes are used for automatic CRC function.

●FIFO mode:

●DIO mode:

RXDIO_CTRL ([DIO_SET: B0 0x0C(7-6)]) = 0b00

RXDIO_CTRL ([DIO_SET: B0 0x0C(7-6)]) = 0b11

Function

Control bit name / Register

TX CRC setting

RX CRC setting

TX_CRC_EN([PKT_CTRL2: B0 0x05(2)])

RX_CRC_EN([PKT_CTRL2: B0 0x05(3)])

CRC_LEN([PKT_CTRL2: B0 0x05(5-4)])

CRC_COMP_OFF([PKT_CTRL2: B0 0x05(6)])

[CRC_POLY3/2/1/0: B1 0x16/17/18/19] registers

[CRC_ERR_H/M/L: B0 0x13/14/15] registers

CRC length setting

CRC complement value OFF setting

CRC polynomial setting

CRC error status

Any CRC polynomials for CRC32/CRC16/CRC8 can be specified. Reset value is as follows:

CRC16 polynomial = x¹⁶+ x¹³+ x¹²+ x¹¹+ x¹⁰+ x⁸+ x⁶+ x⁵+ x²+ 1 (reset value)

NOTE: CRC result data can be inverted by CRC complement value OFF setting,

CRC data will be generated by the following circuits. By programming [CRC_POLY3/2/1/0] registers, any

CRC polynomials can be supported. Generated CRC will be transfer from the most left bit (S15). If data length

is shorter than CRC length (3 bytes of CRC32 only), data “0”s will be added for CRC calculation. CRC check

result is stored in [CRC_ERR_H/M/L] registers.

Unlike Format C, Format A/B can include multiple CRC fields in one packet. For multiple CRCs check results,

CRC value closest to L-field will be stored in CRC_ERR[0] ([CRC_ERR_L:B0 0x15(0)]). Subsequent bit will

be stored in CRC_ERR from MSB order.

CRC_POLY

[13]

CRC_POLY

[14]

CRC_POLY

[0]

CRC_POLY

[1]

Input

Data

S15

S14

S2

S1

S0

NOTE:

exclusive OR

Fig.4 CRC16 polynomial circuits

General CRC polynomial can be programmed by below [CRC_POLY3/2/1/0] register setting.

CRC length can be set by CRC_LEN.

[CRC_POLY3/2/1/0]

(B1 0x17) (B1 0x18) (B1 0x19)

CRC polynomial

(B1 0x16)

0x00

CRC8

x⁸+ x²+ x + 1

x¹⁶+ x¹²+ x⁵+ 1

x¹⁶+ x¹⁵+ x²+ 1

0x00

0x08

0x40

0x1E

0x03

0x10

0x02

0xB2

0x00

CRC16

CRC32

0x00

x

¹⁶+ x¹³+ x¹²+ x¹¹+ x¹⁰+ x⁸+ x⁶+ x⁵+ x²+ 1

0x00

x³²+ x²⁶+ x²³+ x²²+ x¹⁶+ x¹²+ x¹¹+ x¹⁰+ x⁸+ x⁷

+ x⁵+ x⁴+ x²+ x + 1

0x02

0x60

0x8E

0xDB

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●Data whitening function (non Wireless M-BUS standard)

ML7344 supports Data whitening function. In packet format A/B, subsequent data followed by C-field can be

processed data whitening. In packet format C, data Whitening is applied from data field. Data generated by the

following 9 bit pseudo random sequence (PN9) will be “XOR” with TX data (encoded data if Manchester or

3-out-of 6 coding is selected) before transmission. Intialization value of the PN9 generation shift register can be

defined by [WHT_INIT_H/L: B1 0x64/65] registers. PN9 polynomial can be programmed with [WHT_CFG:

B1 0x66] register.

Function

Data whitening setting enable

Data whitening initialization value

Whitening polynomial

Control bit name

WHT_SET ([DATA_SET2: B0 0x08(0)])

WHT_INIT[8:0] ([WHT_INIT_H/L: B1 0x64(0)/65(7-0)])

WHT_CFG[7:0] ([WHT_CFG: B1 0x66(7-0)])

In order to make feedback from S1 register, setting 0b1 to WHT_CFG0 ([WHT_CFG: B1 0x66(0)]). Similaly

in order to make feedback from S2 register, setting 0b1 to WHT_CFG1 ([WHT_CFG: B1 0x66(1)]). Other bits

of [WHT_CFG: B1 0x66] register has same function. Two or more bits can be also set to 0b1. Therefore any

type of PN9 polinominal can be programmed.

Whitening

data

S8

S7

S6

S5

S4

S3

S2

S1

S0

NOTE:

exclusive OR

Fig.5 Whitening data generation circuits

(generator polynomial: x⁹+ x⁵+ 1)

General PN9 polynomial can be defined by WHT_CFG[7:0].

WHT_CFG[7:0]

[WHT_CFG: B1 0x66]

0x08

PN9 polynomial

x⁹+ x⁴+ 1

x⁹+ x⁵+ 1

0x10

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●SyncWord detection function

ML7344 supports automatic SyncWord recognition function. By having two sets of SyncWord pattern storage

area, it is possible to detect two different packet format (Format A/B) which are defined by Wireless M-Bus.

(For details, please refer to Wireless M-BUS standard) Receiving packet format is indicated by

SW_DET_RSLT([STM_STATE:B0 0x77(5)]). In Format C, it is possible to search for two SyncWords but

detected result is not indicated.

1) TX

SyncWord pattern defined by SYNCWORD_SEL ([DATA_SET2: B0 0x08(4)]) will be selected. SyncWord

length for TX is defined by SYNC_WORD_LEN[5:0] ([SYNC_WORD_LEN: B1 0x25(5-0)]). From high bit

of each SyncWord pattern will be transmitted.

SYNCWORD_SEL

TX SyncWord pattern

SYNC_WORD1[31:0]

([SYNCWORD1_SET3/2/1/0: B1 0x27/28/29/2A])

SYNC_WORD2[31:0]

0

1

([SYNCWORD2_SET3/2/1/0: B1 0x2B/2C/2D/2E])

[Example] SyncWord patten and SyncWord length

If the follwing registers are programmed, from higher bit of SYNC_WORD1[17:0] will be transmitted

sequencially.

[SYNC_WORD_LEN: B1 0x25]=0x12

SYNCWORD_SEL ([DATA_SET2: B0 0x08(4)]) = 0b0

If the following registers are programmed, from higher bit of SYNC_WORD2[23:0] will be transmitted

sequencially.

[SYNC_WORD_LEN: B1 0x25]=0x18

SYNCWORD_SEL ([DATA_SET2: B0 0x08(4)]) = 0b1

2) RX

By setting SYNCWORD_SEL and 2SW_DET_EN ([DATA_SET2: B0 0x08(4,3)]), One SyncWord pattern

waiting or two SyncWord patterns waiting can be selected as follows: Packet format automatic detection is

valid if 2SW_DET_EN=0b1 and Format A or Fromat B is selected by PKT_FORMAT[1:0] ([PKT_CTRL1:B0

0x04(1-0)]).

Automatic

packet

format

SyncWord pattern SyncWord

2SW_

DET_EN

SYNCWORD

_SEL

During Sync

Detection

operation

Data process after SyncWord

detection

Waiting for

1 pattern

Process according to each

Format setting

0

1

SYNC_WORD1[31:0]

SYNC_WORD2[31:0]

no

Waiting for

1 pattern

Process according to each

Format setting

[Format A or Format B setting]

If matched with SYNC_WORD1,

then process as Format A.

If matched with SYNC_WORD2,

then process as Format B.

[Format C setting]

SYNC_WORD1[31:0]

SYNC_WORD2[31:0]

Waiting for

2 patterns

1

−

yes

Process as Format C

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Length of SyncWord pattern can be defined by SYNC_WORD_LEN[5:0] ([SYNC_WORD_LEN: B1

0x25(5-0)]). In this case, SyncWord pattern defined by the length from low bit of SYNC_WORD1[31:0] or

SYNC_WORD2[31:0] will be the pattern for checking.

[Example] SyncWord length

If the following registers are set, 18 bit of SYNC_WORD1[17:0] or SYNC_WORD2[17:0] will be reference

pattern for the SyncWord detection. Higher bits (bit31-18) are not checked.

[SYNC_WORD_LEN: B1 0x25]=0x12

[SYNC_WORD_EN: B1 0x26]=0x0F

32bit SyncWord pattern can be controlled by enabling/disabling by each 8bit, when receiving SyncWord. The

following table describes enable/disable control and SyncWord pattern.

[SYNC_WORD_EN]

(B1 0x26)

SYNC_WORD*

[23:16] [15:8]

SyncWord detection operation

No SyncWord detection

[31:24]

[7:0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Only [7:0] are valid.