ML7406_技术文档

FEDL7406-06

Issue Date: Apr. 12, 2019

ML7406

868MHz SRD RF transceiver IC

■Overview

ML7406 is a low power consumption sub GHz RF transceiver, which includes RF, IF, MODEM, baseband processor, HOST

interface. ML7406 can be used for mainly ISM(Industrial, Scientific and Medical) or SRD(Short Range Device).

(EN13757-4:2011: Wireless M-BUS) packet format can be processed by on-chip hardware.

ML7406 and ML7344 have the same package, pins assignment and

major registers.

(32pin WQFN)

ML7406 series

RF: 750MHz to 960MHz

ML7344 series

RF: 160MHz to 510MHz

Rate: 1.2kbps to 500kbps (FSK/GFSK)

Rate: 1.2kbps to 15kbps (FSK/GFSK)

Channel Spacing: 100 kHz to 1.6MHz

Channel Spacing: 25 kHz

Wireless M-Bus

IEEE802.15.4g (FEC not supported)

ARIB STD-T67

ARIB STD-T108

1000

ML7406 series

IEEE802.15.4g

(780 to 950MHz)

100

Wireless

M-Bus

(868MHz)

ML7344 series

10

Wireless

ARIB

STD T67

M-Bus

(169MHz)

(426/429

MHz)

1

0

1000

250

500

750

Frequency [MHz]

1/230

FEDL7406-06

ML7406

■Features

 Supported standard

 ETSI EN 300 220 (Europe)

 EN 13757-4:2011 (Wireless M-BUS)

 IEEE802.15.4g

 ARIB STD T108 (Japan)

 RF frequency: 750MHz to 960MHz

 Realized high resolution modulation by using fractional N type PLL direct GFSK modulation

 Modulation: GFSK/GMSK/FSK/MSK (MSK is a case that FSK modulation index = 0.5)

 Data transmission rate: 1.2 to 500 kbps

 Data encoding/decoding by HW: NRZ, Manchester, 3 out of 6

 Data whitening by HW

 Programmable frequency channel filters

 Programmable frequency deviation function

 TX/RX data inverse function

 26 MHz oscillator circuits version (ML7406C)

 TCXO (26 MHz) direct input version (ML7406T)

 Oscillator capacitance fine tuning function

 On chip low speed RC oscillation circuit

 Low speed clock adjustment function

 frequency fine tuning function (using fractional N type PLL)

 Synchronous serial peripheral interface(SPI)

 On-chip TX PA. (20 mW / 10 mW / 1 mW selectable)

 TX power fine tuning function (±0.2 dB)

 TX power automatic ramping control

 External TX PA control function

 RSSI indicator and threshold judgment function

 High speed carrier checking function

 AFC function (IF frequency automatic adjustment by Fractional N type PLL adjustment)

 Antenna diversity function

 Automatic Wake UP, auto SLEEP function (external RTC input or internal RC oscillator selectable)

 General purpose timer (2ch)

 Test pattern generator (PN9 ,CW, 01 PATTERN, ALL”1”, ALL”0” OUTPUT)

 Packet mode function

 Wireless M-BUS packet format (Format A/B)

 General purpose packet format (Format C)

 Max.255 byte (Format A/B), 204t byte (Format C)

 TX FIFO (64 byte), RX FIFO (64 byte)

 RX Preamble pattern detection (Max.4 byte)

 Automatic TX preamble length generation (Max.length 16383 byte)

 SyncWord setting function (Max. 4byte × 2 type)

 Program CRC function (CRC32/CRC16/CRC8 selectable, fully programmable polynomial)

 Wireless M-BUS field checking function (C-field/M-field/A-field can be detected automatically)

(Note) Proprietary packet format is possible depending on setting

 Supply voltage

1.8 V to 3.6 V (TX power 1 mW mode)

2.3 V to 3.6 V (TX power 10 mW mode)

2.6 V to 3.6 V (TX power 20 mW mode)

 Operational temperature

-40 ˚C to 85 ˚C

2/230

FEDL7406-06

ML7406

 Current consumption (868 MHz)

Deep sleep mode

Sleep mode2

Idle mode

TX 20 mW

10 mW

0.1 μA (Typ.)

0.56 μA (Typ.)

1.4 mA (Typ.)

34 mA (Typ.)

24 mA (Typ.)

13 mA (Typ.)

15 mA (Typ.)

(retains registers, FIFO)

1 mW

RX

(@100kbps)

 Package

32pins WQFN (5mm × 5mm)

Lead free, RoHS compliance

P-WQFN32-0505-0.50

3/230

FEDL7406-06

ML7406

■Product Name

ML7406 y GDZ05BL

y = C: Crystal Input

T: TCXO input

■Description Convention

1) Numbers description

‘0xnn’ indicates hexa decimal. ‘0bnn’ indicates binary.

Example: 0x11= 17(decimal), 0b11= 3(decimal)

2) Registers description

[<register name>: B<Bank No> <register address>] register

Example: [RF_STATUS: B0 0x0B] register

Register name: RF_STATUS

Bank No:

0

Register address: 0x0B

3) Bir name description

<bit name> ([<register name>: B<Bank No> <register address>(<bit location>)])

Example: SET_TRX[3:0] ([RF_STATUS: B0 0x0B(3-0)])

Bit name: SET_TRX

Register name: RF_STATUS

Bank No:

0

Register address: 0x0B

Bit location: bit3 to bit0

4) In this document

“TX” stands for transmittion.

“RX” stands for reception.

4/230

FEDL7406-06

ML7406

■Block Diagram

ML7406

A_MON

RESETN

RF

BB

ED_VAL

TEMP

RSSI

PHY

SCLK

SDO

SDI

S

P

I

LNA_P

Limiter

LNA

PA

MIX

BPF

DEMOD

SCEN

FIFO

RF_Manager

LO PLL

VCO

20mW/

1mW

PA_OUT

I

R

C

Digital

MOD

GPIO0

FMAP

GPIO1/2/3

EXT_CLK

General

TIMER1/2

Reg(PA)

REG_PA

Wakeup

TIMER

RC

OSC

26MHz Xtal OSC

Reg

CLK

CAL

REGPDIN

VB_EXT

IND1,2

VBG

XIN

LP

XOUT

REG_OUT

REG_CORE

L C

5/230

FEDL7406-06

ML7406

■PIN Configuration

32 pin WQFN

24

23

22

21

20

19

18

17

VDD_RF

LP

25

26

27

28

29

30

31

32

16

15

14

13

12

11

10

9

GPIO0

SDI

VDD_CP

IND1

SCEN

SCLK

裏面PKGꢀGND

GND PAD

(T.B.D.)

GND_VCO

IND2

SDO

REGPDIN

EXT_CLK

VDDIO

VB_EXT

VDD_VCO

1

2

3

4

5

6

7

8

NOTE: GND pad in the middle of the LSI is reverse side (name:reversed side GND)

6/230

FEDL7406-06

ML7406

■PIN Definitions

Definiion of Symbols

I/O

Reset state

Digital Input

Digital Ouput

High-Impedance

Active Level

High Level

Low Level

Open Drain

Positive Edge

Negative Edge

I

:

Digital input

I

O

Hi-Z

:

H

L

OD

P

N

:

O

IS

IO

IA

Digital output

Shmidt Trigger input

Digital input/output

Analog input

OA

Analog output 1

Analog output 2

Analog input/output

RF input

OAH

IOA

IRF

ORF

VDDIO

VDDRF

GND

RF output

I/O power supply

RF power supply

Ground

●RF and Analog pins

Reset

state

Active

Level

20

Pin name

PA_OUT

I/O

function

−

O_RF

O_A

−

RF antenna output

23

24

26

28

30

31

A_MON

LNA_P

LP

Temperature information output (*1)

RF antenna input

I_A

IO_A

Pin for loop filter

IND1

Pin for VCO tankl inductor

Pin for VCO tank inductor

Pin for smothing capacitor for internal bias

IND2

VB_EXT

*1 This pin can be configured by [MON_CTRL:B0 0x4D] register, no signal assigned as default setting.

●SPI Interface pins

Reset

state

Active

Level

12

Pin name

SDO

I/O

O

function

Hi-Z

H or L SPI data output or DCLK (*1)

13

14

15

SCLK

SCEN

SDI

IS

P or N SPI clock input

SPI chip enable

L

L: enable

H: disable

H or L SPI data input or DIO (*1)

*1 Please refer to “DIO function”

7/230

FEDL7406-06

ML7406

●Regulator pins

Reset

state

Active

Level

2

Pin name

I/O

function

VBG

−

I

O_AH

−

H

−

Pin for decouppling capacitor

Requlator1 ouput (typ. 1.5V)

Requlator2 ouput (typ. 1.5V)

3

4

REG_OUT

REG_CORE

REGPDIN

REG_PA

O_AH

O_A

I

Power down control pin for regulator

Fix to ‘L’ for nomal use. “H” is for deep sleep mode.

11

21

−

O_AH

Regulator output for PA block

●Miscellaneous pins

Reset

state

Active

Level

5

Pin name

I/O

function

XIN

N.C. (*2)

26MHz crystal pin1

I

−

I_A

−

P or N

−

(Note) In case of TCXO, it must be open.

O_A

I_A

I

XOUT

TCXO (*2)

6

O

P or N 26MHz crystal pin 2 or TCXO input

Reset

8

RESETN

EXT_CLK

GPIO0

I

I_S

L

L: Hardware reset enable (Forcing reset state)

H: Normal operation

Digital I/O (*3)

Reset state: External RTC (32kHz) input.

10

16

17

18

19

Hi-Z

IO

P or N

H or L

IO

or

OD(*1)

IO

or

OD(*1)

IO

or

OD(*1)

Digital GPIO (*4)

Reset state: interrupt indication signal output

Digital GPIO (*5)

Reset state: clock output

GPIO1

ANT_SW/

GPIO2

Digital GPIO (*6)

Reset state: Antenna diversity selection control signal

IO

or

OD(*1)

TRX_SW/

GPIO3

Digital GPIO (*7)

Reset state: TX –RX selection signal control

(Note)

*1 OD is open drain output.

*2 The following pin names are different depend on products.

Pin No.

ML7406C

ML7406T

5

XIN

N.C.

6

XOUT

TCXO

(Note)

In case of using TCXOset TCXO_EN([CLK_SET2: B0 0x03(6)])=0b1. Please make sure only one of the register

TCXO_EN, XTAL_EN([CLK_SET2: B0 0x03(4)]) is set to 0b1.

*3 Please refer to [EXTCLK_CTR: B0 0x52] register.

*4 Please refer to [GPIO0_CTRL: B0 0x4E] register

*5 Please refer to [GPIO1_CTRL: B0 0x4F] register. In case of ML7406T, clock doesn’t output until TCXO_EN is set to

0b1.

*6 Please refer to [GPIO2_CTRL: B0 0x50] register

*7 Please refer to [GPIO3_CTRL: B0 0x51] register

8/230

FEDL7406-06

ML7406

●Power supply/GND pins

Reset

state

Active

Level

1

Pin name

I/O

function

Power supply pin for Regulator

−

VDD_REG

V_DDIO

(input voltage: 1.8V to 3.3V)

Power supply for digital I/O

(input voltage: 1.8 to 3.6V)

−

9

VDDIO

VDD_PA

VDD_RF

V_DDIO

V_DDRF

Power supply for PA block

(input voltage: 18 to 3.6V, depending on TX mode)

22

25

−

Power supply for RF blocks

(REG-OUT is connected, typ.1.5V)

Power supply for charge pump

(REG-OUT is connected, typ.1.5V)

27

32

29

VDD_CP

VDD_VCO

GND_VCO

−

V_DDRF

GND

−

Power supply for VCO

(REG_OUT is connected, typ.1.5V)

GND for VCO

●Unused pins treatment

Unused pins treatments are as follows:

Unused pins treatment

Pin name

N.C.

Pins number

Recommended treatment

5

Open

N.C.

7

GND or Open

GND

EXT_CLK

A_MON

GPIO0

GPIO1

GPIO2

GPIO3

10

23

16

17

18

19

GND

Open

(Note)

*1 If input pins are high-impedence state and leave open, excess current could be drawn. Care must be taken that unused

input pins and unused I/O pins should not be left open.

*2 Upon reset, GPIO1 pin is CLK_OUT function. If this function is not used, the clock must to be disabled by setting

0b000 to GPIO1_IO_CFG[2:0] ([GPIO1_CTRL: B0 0x4F (2-0)]). If this pin is left open while outputing clock signal,

it may affect RX sensitivity.

9/230

FEDL7406-06

ML7406

■Electrical Characteristics

●Absolute Maximum Rating

Ta=-40˚C to +85˚C and GND=0V is the typical conditoin if not defined specific condition.

item

symbol

condition

Rating

unit

V

I/O Power supply

V_DDIO

-0.3 to +4.6

-0.3 to +2.0

RF Power supply

V_DDRF

V

RF input power

P_RFI

V_RFO

V_A

Antenna input in RX

PA_OUT(#20)

0

dBm

V

RF output Voltage

Voltage on Analog Pins 1

-0.3 to +4.6

-0.3 to +2.0

V

Voltage on Analog Pins 2

Voltage on Digital Pins

Digital Input Current

Digital Output Current

Power Dissipation

V_AH

V_D

-1.0 to +4.6

-0.3 to +4.6

-10 to +10

-8 to +8

V

IDI

mA

W

IDO

Pd

Ta= +25˚C

1.2

Storage Temperature

Tstg

−

-55 to +150

˚C

10/230

FEDL7406-06

ML7406

●Recommended Operation Conditions

Item

Symbol

VDDIO

Condition

VDDIO pin and

Min

1.8

Typ

3.3

Max

3.6

Unit

Power Supply (I/O)

V

VDD_REG pin (*1)

VDD_PA pin

TX power 1mW mode

1.8

2.3

2.6

3.3

3.6

V

VDD_PA pin

TX Power 10mW mode

Power Supply (PA)

VDDPA

VDD_PA pin

TX Power 20mW mode

Operational Temperature

Digital Input Rising Time

Digital Input Falling Time

Digital Output Load

Ta

TIR

TIF

−

-40

−

+25

−

+85

20

˚C

ns

pF

Digital Input pins (*1)

All Digital Output pins

−

20

CDL

−

20

Master Clock Frequency

(XIN,XOUT,TCXO pins)

FMCK1

−

(*2)

26

(*2)

MHz

Master Clock Accuracy (*2)

TCXO Input Voltage

ACMCK1

VTCXO

-85

0.8

−

+85

1.5

ppm

Vpp

DC Cutoff

TCXO Optionis selected

SPI Clock Input Frequency

FSCLK

DSCLK

SCLK pin

0.032

45

2

50

−

16

55

MHz

%

SPI Clock Input

Duty Cycle Ratio

RF Frequency

FRF

750

960

MHz

*1 In the pin description, I or Is are specified as the I/O.

*2 Indicating frequency deviation during TX-RX operation. In order to support various standards, please apply the

frequency accuracy for each standard to meet the requirements.

Specification

Required accuracy

±60 ppm(Meter)

±25 ppm(Other)

±60 ppm(Meter)

±25 ppm(Other)

Wireless M-Bus S mode

Wireless M-Bus T mode

Wireless M-Bus C mode

ARIB STD-T108

±25 ppm

±20 ppm

11/230

FEDL7406-06

ML7406

(Note) Below values are not taking individual LSI variations into consideration.

●Power Consumption

Item

Synbol

Condition

Deep Sleep mode

Min

Typ (*2)

0.1

Max (*5)

Unit

µA

9

(0.8)

IDD_DSLP

−

(Not retaining Registers, all function halt)

20

(3.2)

IDD_SLP2

IDD_SLP3

IDD_SLP4

Sleep mode 2 (*3)

−

0.56

0.7

µA

20.2

(3.2)

Sleep mode 3 (*3)

Sleep mode 4 (*3)

22

(5.1)

2.5

Power Consumption

(*1)

IDD_IDLE

IDD_RX

Idle state

−

1.4

15

−

mA

RF RX state (*4)

IDD_TX1

RF TX state (1mW)(*4)

−

13

−

mA

IDD_TX10

IDD_TX20

RF TX state (10mW) (*4)

RF TX state (20mW) (*4)

−

24

34

−

mA

*1 Power consumption is sum of current consumption of all power supply pins.

*2 “Typ” value is centre value under condition of VDDIO=3.3V, 25˚C.

*3 The definition od each sleep stae is shown in following table.

RC Osc.

(32kHz)

State.

Register

FIFO

Low clock timer

Sleep mode 1

Sleep mode 2

Sleep mode 3

Sleep mode 4

ML7406 does not support Sleep mode 1

Retain

OFF

External Input

ON

-

ON

*4 Current consumption when RF Frequency is 868MHz.

*5 () means maximum value (reference value) under condition of 25˚C.

(Note)

It is inhibited the trnasiton from sleep modes to deep sleep mode in one power supply cycle.

12/230

FEDL7406-06

ML7406

●DC characteristics

Item

Symbol

VIH1

Condition

Digital Input pins

Min

Typ

−

Max

Unit

V

VDDIO * 0.75

VDDIO

1.5

Voltage Input High

VIH2

XIN pin

1.35

0

−

V

VIL1

Digital Input pins

XIN pin

−

VDDIO * 0.18

0.15

V

Voltage Input Low

VIL2

0

−

V

RESETN pin

SDI, SCLK, SCEN pins

EXT_CLK pin

Schmit Trigger

Threshold High Level

VT+

−

1.2

VDDIO * 0.75

V

RESETN pin

SDI, SCLK, SCEN pins

EXT_CLK pin

Schmit Trigger

Threshold Low Level

VT-

VDDIO * 0.18

-1

0.8

−

V

IIH1

Digital input pins

−

1

µA

IIH2

IIL1

IIL2

XIN pin

-0.3

-1

−

0.3

1

µA

Input Leakage Current

Digital input pins

XIN pin

-0.3

0.3

IOZH

IOZL

VOH

VOL

EXT_CLK, GPIO0-3 pins,

IOH=-4mA

-1

−

1

µA

V

Tri-state Output

Leakage Current

-1

Voltage Output Level H

Voltage Output Level L

VDDIO * 0.8

0

VDDIO

0.3

IOL=4mA

V

REG_CORE pin, REG_OUT pin,

applicable to all states except SLEEP

state

REGMAIN

REGSUB

1.4

1.5

1.3

1.6

V

Regulator Output

Voltage

REG_CORE pin

Sleep state

0.95

1.65

CIN

Input pins

−

6

9

−

pF

COUT

Output pins

Pin Capacitance

CRFIO

CAI

RF inout pins

−

9

−

pF

Analog input pins

13/230

FEDL7406-06

ML7406

●RF characteristics

Modulated Data Rate

Modulation fomats

Channel spacing

:

1.2kbps to 500kbps

2GFSK/2FSK

60kHz to 1.6MHz

The measurement point is at antenna end specified in the recommended circuits.

[RF Frequency]

Item

Condition

LNA_P, PA_OUT pins

Min

750

Typ

Max

960

Unit

RF frequency

−

MHz

(Note)

1)Frequency range can be adjusted from 750MHz to 960MHz by changing external components parameters.

2)If channel frequency is similar frequency range of Integral multiple of the master clock, it may not be able to use this

mode. Please refer to the “channel frequency setting” section for detail.

[TX Characteristics]

Item

Condition

20mW(13dBm) mode

Min

9

Typ

13

Max

15

Unit

dBm

10mW(10dBm) mode

1mW(0dBm) mode

6

-4

10

0

12

4

dBm

kHz

TX power

Frequency deviation setting range

[Fdev] (*1)

0.025

−

400

Spurious emission level(10mW mode)

The sencod order harmonic

The third order harmonic

−

-35

-30

dBm

*1. Depending on the frequency, max.frequency may be changed.

[RX Characteristics]

Item

Minimum RX sensitity

BER<0.1%

Condition

Min

Typ

Max

Unit

32.768kbps mode

100kbps mode

BER<0.1%

−

-108

−

dBm

−

-106

-100

dBm

Maximum RX input level

0

−

Minimum energy detection level

(ED value)

-107

70

-100

−

dBm

dB

60

−

Energy detection range

Dynamic range

Local frequency

Energy detection accuracy

-6

−

+6

-57

-47

dB

-63

-57

dBm

Secondary emission level

Frequency over 1000MHz

−

14/230

FEDL7406-06

ML7406

●RC oscillation circuits characteristics

ML7406 has on-chip low speed RC clock generator. For details, please refer to “LSI state transition control/SLEEP setting”

section.

Item

Symbol

Condition

Min

Typ

Max

Unit

RCOSC oscillation frequency

FRCOSC

−

44

−

kHz

●SPI interface characteristics

Item

SCLK clock frequency

SCEN input setup time

SCEN input hold time

SCLK high pulse width

SCLK low pulse width

SDI input setup time

SDI input hold time

Symbol

FSCLK

Condition

Min

0.032

30

Typ

2

Max

16

−

Unit

MHz

ns

TSCENSU

TSCENH

TSCLKH

TSCLKL

TSDISU

TSDIH

−

30

−

ns

28

−

ns

Load

capacitance

CL=20pF

28

−

ns

5

−

ns

15

−

ns

SCEN negate period

SDO output delay time

TSCENNI

200

−

ns

TSDODLY

−

22

ns

(Note) All measurement condition for the timings are VDDIO * 20% level and VDDIO * 80% level.

SCEN

TSCENH

FSCLK

TSCENSU

TSCLKL

SCLK

TSCLKH

TSDISU

TSDIH

SDI

MSB IN

BITS6-1

LSB IN

TSDODLY

MSB OUT

LSB OUT

SDO

TSCENNI

SCEN

15/230

FEDL7406-06

ML7406

●DIO iInterface characteristics

Item

Symbol

TDISU

Condition

Min

1

Typ

Max

Unit

DIO input setup time

−

µsec

DIO input hold time

DIO output hold time

TDIH

0

−

ns

TDOH

20

-clock

frequency

deviation

+clock

frequency

deviation

DCLK frequency accuracy (*1)

(TX)

FDCLK_TX

−

kHz

Load capacitance

CL=20pF

DCLK frequency accuracy (*2)

(RX)

FDCLK_RX

DDCLK_TX

-30

45

−

+30

55

%

DCLK output duty ratio

(TX)

DCLKoutput duty ratio

(RX)

DDCLK_RX

30

−

70

%

*1 If there is no decimal point generated in the TX data rate setting caluclation, (see [TX_RATE_H: B1 0x02]), master

clock frequency deviation is max.and min.of TX DCLK frequency.

*2 Max.and min.of RX DCLK frequency indicates jitter of recovered clock from RX signal upon synchronization.

(Note)

All timing measurement conditions are VDDIO * 20% and VDDIO * 80%.

FDCLK_TX/ FDCLK_RX

DCLK

TDISU

TDIH

DIO(Input)

VALID

TDOH

DIO(Output)

VALID

16/230

FEDL7406-06

ML7406

●Power-on characteristics

Item

Symbol

TPWON

Condition

Power on state

Min

Typ

Max

5

Unit

ms

Power-ontime

−

(all power pins)

(Note)

All timing measurement conditions are VDDIO * 20% and VDDIO * 80%.

TPWON

VDD level

GND level

80%

20%

VDD

●Reset characteristics

Item

Symbol

TRDL1

Condition

Min

150

Typ

Max

Unit

ms

RESETN release delay time

(power on period)

All power pins

After Power On

−

RESETN pulse period

(start-up from VDDIO=0V)

TRPW1

TRPW2

TRDL2

200

150

1

−

ns

ms

µs

RESETN pulse period 2(*1)

(start-up from VDDIO≠0V)

After VDDIO>1.8V

RESETN input delay time

(Note)

All timing measurement conditions are VDDIO * 20% level and VDDIO * 80% level.

VDD level

GNDlevel

1.8V

VDDIO

Below 1.8V

TRDL2

TRPW1

TRPW2

TRDL1

RESETN

(*1) When starting from VDDIO≠0V, a pulse must be sent to VRESETN after DDIO exceeds 1.8V.

17/230

FEDL7406-06

ML7406

●Deep Sleep mode characteristics

Item

Symbol

TRPFD

Condition

VDDIO=”H”

Min

0

Typ

Max

Unit

µs

REGPDIN rising edge delay time

−

REGPDIN assert time

TRPPLS

TRPRD

VDDIO=”H”

1.2

1.5

−

ms

REGPDIN release delay time

(Note)

All timing measurement conditions are VDDIO * 20% and VDDIO * 80%.

VDD level

GND level

VDDIO

TRPFD

TRPRD

RESETN

TRPPLS

REGPDIN

●Clock output characteristics

ML7406 has clock output function. Clock output can be controlled by DMON_SET([MON_CTRL: B0 0x4D(3-0)]) and

[GPIOn_CTRL: B0 0x4E-0x51] registers (n=0 to 3). Upon reset, clock is output through GPIO1 pin.

Item

Symbol

Condition

Min

Typ

Max

26

Unit

Clock output frequency

FCLKOUT

0.0064

3.33

MHz

Load

capacitance

CL=20pF

8.66MHz

33

48

−

67

52

%

Clock output duty ratio (*1)

DCLKOUT

All conditions

except above

50

*1 Duty cycle is High:Low = 1:2 , only when 8.66MHz is used. Please refer to [CLK_OUT: B1 0x01] register.

(Note)

All timing measurement conditions are VDDIO * 20% and VDDIO * 80%.

FCLKOUT

GPIO*

18/230

FEDL7406-06

ML7406

■Functional Description

●Host Interface

○Serial Peripheral Interface (SPI)

ML7406 has a SPI, which supports slave mode. Host MCU can read/write to the ML7406 registers and on-chip FIFO using

MCU clock. Single access mode and burst access mode are also supported.

[Single access mode timing chart]

In write operation, data will be stored into internal register at rising edge of clock which is capturing D0 data. During write

operation, if setting SCEN line to “H”, the data will not be stored into register. For more details of SCEN invert perios, please

refer to the “SPI interface characteristics”. After the internal clock is stabilized, the data will be written into the register in

synchronization with the internal clcok.

[Write]

SCLK

SCEN

A

6

A

0

D

7

D

0

SDI

“1”

Write data field

Address field

W

(Register write timing)

Before clock stable

After clock stable

D7-0

Up to 0.45 µs

[Read]

SCLK

SCEN

A

6

A

0

SDI

“0”

Address field

R

D

0

D

7

SDO

Data read field

19/230

FEDL7406-06

ML7406

[Burst access mode timing chart]

By maintaining SCEN line as “L”, Burst access mode will be active. By setting SCEN line to “H”, exiting from the burst

access mode. During burst access mode, address will be automatically incremented.

When SCEN line becomes “H” before Clock for D0 is input, data transaction will be aborted.

(Note)

If destination is [WR_TX_FIFO: B0 0x7C] or [RD_FIFO: B0 0x7F] register, address will not be incremented. And

continuous FIFO access is possible.

[Write]

SCLK

SCEN

A

6

A

0

D

7

D

0

SDI

“1”

Write data field

Address field

W

(Register write timing)

Before clock stable

After clock stable

D7-0

Up to 0.45μs

[Read]

SCLK

SCEN

A

6

A

0

“0”

SDI

Address field

R

D

7

D

0

SDO

Read data field

20/230

FEDL7406-06

ML7406

●LSI state transition control

○LSI state transition instruction

State can be controlled from MCU by setting registers below.

State transition command

Instruction

TX_ON

RX_ON

TRX_OFF

Force_TRX_OFF

SLEEP

SET_TRX ([RF_STATUS: B0 0x0B(3-0)]) = 0b1001

SET_TRX ([RF_STATUS: B0 0x0B(3-0)]) = 0b0110

SET_TRX ([RF_STATUS: B0 0x0B(3-0)]) = 0b1000

SET_TRX ([RF_STATUS: B0 0x0B(3-0)]) = 0b0011

SLEEP_EN([SLEEP/WU_SET: B0 0x2D(0)]) = 0b1

VCO_CA_LSTART([VCO_CAL_START: B0 0x6F(0)])= 0b1

VCO_CAL

State can be changed without command from MCU. If one of the following condition is met, state is changed automatically

according to the following table. In order to enable these functions, the following registers must be programmed.

Function

Control bit name

Automatic TXON after FIFO write completion (AUTO_TX)

Automatic TXON during FIFO wrtie (FAST_TX)

RF state setting after packet transmission completion

RF state setting after packet reception completion

AUTO_TX_EN([RF_STATUS_CTRL: B0 0x0A(4)])

FAST_TX_EN([RF_STATUS_CTRL: B0 0x0A(5)])

TXDONE_MODE([RF_STATUS_CTRL: B0 0x0A(1-0)])

RXDONE_MODE([RF_STATUS_CTRL: B0 0x0A(3-2)])

WAKEUP_MODE([SLEEP/WU_SET:B0 0x2D(6)])

WAKEUP_EN([SLEEP/WU_SET:B0 0x2D(4)])

AUTO_VCOCAL_EN([VCO_CAL_START: B0 0x6F(4)])

WU_DURATION_EN([SLEEP/WU_SET: B0 0x2D(5)])

FAST_DET_MODE_EN([CCA_CTRL:B0 0x39(3)])

PLL_LD_EN([PLL_LOCK_DETECT: B1 0x0B(7)])

Automatic RX_ON/TX_ON by Wake-up time

Automatic VCO calibration after exit from SLEEP

Automatic SLEEP by Timer

Automatic SLEEP by high speed carrier checking mode

Force_TRX_OFF after PLL unlock detection during TX

21/230

FEDL7406-06

ML7406

○State Diagram

Each state transition control is decribed in the follwing state diagram.

TRX_OFF

Force_TRX_OFF

SLEEP

TRX_OFF

Force_TRX_OFF

SLEEP

RECEIVE

TRASMIT

Force_TRX_OFF

SLEEP

Force_TRX_OFF

SLEEP

RX completion

(TRX_OFF)

RX start

(SyncWord detection)

TX completion

(TRX_OFF)

TX start

TRX_OFF

Force_TRX_OFF

SLEEP

TX_ON

TRX_OFF

Force_TRX_OFF

SLEEP

TRX_OFF

Force_TRX_OFF

SLEEP

RX_ON

TX_ON

RX_ON

TX_ON

TRX_OFF

Force_TRX_OFF

SLEEP

RX_ON

TX_ON

RX_ON

TX_ON

RX_ON

PLLWAIT

TX_ON

RX_ON

VCO_CAL

SLEEP

Start VCO_CAL

VCO_CAL

completion

TRX_OFF

IDLE

Force_TRX_OFF

VCO_CAL completion

SLEEP

Start VCO_CAL

Exit from

DEEP SLEEP

VCOCAL

Exit from SLEEP

DEEP

SLEEP

DEEP

SLEEP

Exit from

SLEEP

Exit from

DEEP SLEEP

State transition instruction

Pins control

[STATE]

DEEP SLEEP

SLEEP

: DEEP SLEEP

: SLEEP

TRX_OFF/IDLE

PLL_WAIT

TX_ON

TRANSMIT

RX_ON

RECEIVE

VCO_CAL

: IDLE (TX-RX stand-by)

: PLL stand-by

: TX ready (TX data waiting)

: TX on-going

: RX stand-by (RX data waiting)

: RX on-going

: VCO calibration

Normal sequence

(state transition)

Command from

Higher layer state

ML7406 Self controlled state transition

LSI state diagram

(Note)

The following state transition is inhibited;

DEEP SLEEP → any state → SLEEP

22/230

FEDL7406-06

ML7406

○SLEEP setting

DEEP_Sleep mode: Powers for all blocks except IO pins are turned off.

Sleep mode: Main regulator and 26MHz oscillation circuits are tured off. But sub-regulator is turned-on.

The following registers can be programmed to control SLEEP state.

Function

Control bit name

PDN_EN([SLEEP/WU_SET: B0 0x2D(1)])

WAKEUP_EN([SLEEP/WU_SET: B0 0x2D(4)])

WUT_CLK_SOURCE([SLEEP/WU_SET: B0 0x2D(2)])

RC32K_EN ([CLK_SET2: B0 0x03(3)])

Power control

Wake-up setting

Wake-up timer clock source setting

Internal RC oscillator control

Setting method and internal state for DEEP_SLEEP and various SLEEP modes are as follows:

SLEEP mode

Setting method

RESETN pin=”L”

REGPDIN pin=”H”

not supported

DEEP_SLEEP

SLEEP1

OFF

-

OFF

-

OFF

-

OFF

-

OFF

-

OFF

-

[SLEEP/WU_SET: B0 0x2D(4-0)] =

0b0_1001 (*2)

[CLK_SET2: B0 0x03(3)] = 0b0

(default)

SLEEP2

OFF

ON

OFF

OFF(*1)

OFF

ON

[SLEEP/WU_SET: B0 0x2D(4-0)] =

0b1_1001 (*2)

[CLK_SET2: B0 0x03(3)] = 0b0

(default)

[SLEEP/WU_SET: B0 0x2D(4-0)] =

0b1_1101 (*2)

SLEEP3

SLEEP4

OFF

ON

OFF

ON

[CLK_SET2: B0 0x03(3)] = 0b1

(*1) Low speed clock is supplied from EXT_CLK pin.

(*2) Please set proper value to [SLEEP/WU_SET: B0 0x2D(3)].

(Note)

Contents of registers are not kept during DEEP_SLEEP. Contents of registers are kept during SLEEP2,SLEEP3,SLEEP4.

However, the SLEEP time should be less than the below time, to keep contents of registers normally.

Operation maximum

Temperature[˚C]

25

45

65

85

SLEEP period[msec]

1900

1100

600

300

When the SLEEP time is longer than the above time, register value can be held by canceling SLEEP in the following

procedure. However, the wakeup timer function can not be used.

[REGULATOR_CTRL: B1 0x07] = 0xF 9

i.

ii.

WAIT 500us

iii.

iv.

v.

[REGULATOR_CTRL: B1 0x07] = 0xFD

SLEEP_EN ([SLEEP/WU_SET: B0 0x2D(0)]) = 0b0

[REGULATOR_CTRL: B1 0x07] = 0xFE

23/230

FEDL7406-06

ML7406

○Notes to set RF state

ML7406 is able to change the internal RF state transition autonomously (without commands from MCU) as well as RF state

change commands from MCU. (please refer to ”LSI state transition instruction”). If both timing of operation (autonomous

state and state change from MCU command) overlapped, unintentional RF state may occur. Timing of autonomous state RF

change is described in the following table.

Care must be taken not to overlap the conditions.

RF state change

(before→after)

Function

RF state transition timing (not from Host MCU

command)

Recommended process

Automatic TX

TRX_OFF/RX_ON

After TX data transfer completion interrut occurs,

{ value [TX_RATE_H/L: B1 0x02/03)] * 2 / 26}[μs]

period.

→TX_ON

FAST_TX mode

When FIFO write access exceed trigger level +1,

{ value [RX_RATE1_H/L:B1 0x04/05] * 5 / 26}[μs]

period.

Write access to [RF_STATUS:B0

0x0B] is possible after RF state

transition completion interrupt

(INT[3] group1), or move to the

state defined by GET_TRX

([RF_STATUS:B0 0x0B(7-4)]).

RF state setting after TX

completion

TX_ON→TRX_OFF

After TX completion interrupt (INT[16] group3),

{ value [TX_RATE_H/L:B1 0x02/03] * 2 / 26} [μs]

period

TX_ON→RX_ON

TX_ON→SLEEP

RX_ON→TRX_OFF

RX_ON→TX_ON

RX_ON→SLEEP

RF state setting after RX

completion

After data RX completion interrupt (INT[8] group2,

{ value [RX_RATE1_H/L:B1 0x04/05] * 2 / 26}[μs]

period

Wake-up timer

After wake-up timer completion interrupt (INT[6]

group1), 1 clock cycle period defined by

WUT_CLK_SET[3:0] ([WUT_CLK_SET:B0 0x2E

(3-0)]).

SLEEP→TX_ON

SLEEP→RX_ON

After wake-up timer completion interrupt (INT[6]:

group1), before VCO calibration completion

interrupt (INT[1] group1).

Write access to [RF_STATUS:B0

0x0B] and BANK2 is possible

after VCO calibration completion

interrupt (INY[1] group1).

SLEEP→VCO_CAL

→TX_ON

SLEEP→VCO_CAL

→RX_ON

Continuous operation

timer

After continuous operation timer completion, 1

clock cycle period defined by WUT_CLK_SET[3:0] 0x0B] is possible after RF state

([WUT_CLK_SET:B0 0x2E (3-0)]).

Write access to [RF_STATUS:B0

TX_ON→SLEEP

RX_ON→SLEEP

transition completion interrupt

(INT[3] group1), or move to the

state defined by GET_TRX

([RF_STATUS:B0 0x0B(7-4)]).

Write access to [RF_STATUS:B0

0x0B] is possible 147μs after PLL

unlock interrupt (INT[2] group1)

detected.

High speed carrier

checking

After CCA completion interrupt, duration 6.3[μs].

RX_ON→SLEEP

PLL unlock detection

TX_ON→TRX_OFF

After PLL unlock detection interrupt (INT[2]

group1) occurs, duration 147[μs].

24/230

FEDL7406-06

ML7406

●Packet Handling Function

○Packet format

ML7406 supports Wireless M-BUS frame FormatA/B, and Format C which is non Wireless M-BUS universal format. The

following packet handling are supported in FIFO mode or DIO mode

1) Preamble and SyncWord automatic insertion (TX)

2) Preamble and SyncWord automatic detection (RX)

3) Preamble and SyncWord automatic deletion (RX)

4) CRC data insertion (TX)

--- DIO/FIFO mode

--- DIO/FIFOmode

--- DIO/FIFO mode

--- FIFO mode

5) CRC check and error notification (RX)

--- DIO/FIFO mode

The following table shows control bits relative with the Packet format function.

Function

Control bit name

Packet formatsetting

IEEE 802.15.4g setting

PKT_FORMAT[1:0] ([PKT_CTRL1: B0 0x04(1-0)])

IEEE802_15_4G_EN ([PKT_CTRL1: B0 0x04(2)])

RX_EXTPKT_OFF ([PKT_CTRL1: B0 0x04(3)])

DAT_LF_EN ([PKT_CTRL1: B0 0x04(4)])

LEN_LF_EN ([PKT_CTRL1: B0 0x04(5)])

EXT_PKT_MODE[1:0] ([PKT_CTRL1: B0 0x04(7-6)])

LENGTH_MODE ([PKT_CTRL2: B0 0x05(0)])

RX extended link layer mode disable

Data area bit order setting

Length area bit order setting

Extended link layer mode setting

Length field setting

(1) Format A (Wireless M-BUS)

By setting PKT_FORMAT[1:0] ([PKT_CTRL1: B0 0x04(1-0)])=0b00, Wireless M-BUS Format A is selected.

Format A consists of 1^stBlock, 2^ndBlock and Optional Block(s). Each block has 2 bytes of CRC. “L-field” (1^stbyte of 1^st

Block ) indicates packet length, which includes subsequenct user data bytes from “C-field”. However, CRC bytes and postamble

are excluded. Depending on “L-field” value, 2^ndBlock and Optional Block(s) are added.

The following [] indicates register address [bank #, address].

Manchester/3-out-of-6 applicable [B0 0x07(3-2,1-0)]

CRC applicable

2nd Block

CRC applicable

Optional Block

MSB

LSB

Length

1st Block

Sync

Word

Preamble

Postamble

L

C

M

A

CRC

field

CRC

field

CI

field

Data

field

Data

field

field field field field field

0/2-8

bits

1

byte

Max.15

bytes

2

Max.16

bytes

2

> n*2 (*1)

bits

10/18/

1

2

6

2

bytes

32bits byte byte bytes bytes bytes

[B0 0x07]

[B0 0x42]

[B0 0x43]

[B0 0x08]

[B1 0x25-2E]

(*2)

[B0 0x44]

(*3)

(*4)

[B0 0x05]

[B0 0x7A/7B, 7D/7E]

TX: automatic insertion

RX: automatic detection, deletion

*1: Each mode has different minimum value of n.

*2: Indicates TX FIFO data storage area size.

*3: Indicates RX FIFO data storage area size.

*4: When RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)])=0b10, indicates DCLK/DIO output area.

25/230

FEDL7406-06

ML7406

Extended Link Layer Format

If “CI-field” (1^stbyte of 2^ndBlock)=0x8C or 0x8D, Extended Link Layer is applied. The packet format is as follows:

(a) CI-field = 0x8C

For TX, if 2 bytes extention format is used, set EXT_PKT_MODE[1:0] ([PKT_CTRL1: B0 0x04(7-6)])=0b01.

For RX, if RX_EXTPKT_OFF([PKT_CTRL1: B0 0x04(3)])=0b0, ML7406 recognizes “CI-field” and RX operation is

processed.

Manchester/3-out-of-6 applicable [B0 0x07(3-2,1-0)]

CRC applicable

Optional Block

CRC applicable

MSB

LSB

1st Block

(*1)

Extended

Length

Block

2nd Block

Sync

Word

Preamble

Postamble

CI

field

L

CI

CC ACC

CRC

field

CRC

C-CRC

field

Data

field

Data

field

field field field

field

0/2-8

bits

2

> n*2

bits

11

bytes

1

byte

Max 12

bytes

Max 16

bytes

10/18/

32bits byte

1

bytes

byte byte byte

(*2)

[B0 0x08]

[B1 0x25-2E]

[B0 0x07]

[B0 0x42]

[B0 0x43]

[B0 0x44]

(*3)

(*4)

[B0 0x05]

[B0 0x7A/7B, 7D/7E]

TX: automatic insertion

RX: automatic detection, deletion

*1: 1st Block is identical to normal Format A..

*2: Indicates TX FIFO data storage area size.

*3: Indicates RX FIFO data storage area size.

*4: When RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)])=0b10, indicating DCLK/DIO output area.

26/230

FEDL7406-06

ML7406

(b) CI-field = 0x8D

For TX, if 8 bytes extention format is used, set EXT_PKT_MODE[1:0] ([PKT_CTRL1: B0 0x04(7-6)])=0b10.

For RX, if RX_EXTPKT_OFF([PKT_CTRL1: B0 0x04(3)])=0b0, ML7406 recognizes “CI-field” and RX operation is

processed.

Manchester/3-out-of-6 applicable [B0 0x07(3-2,1-0)]

CRC applicable

LSB

MSB

1st Block

(*1)

Extended Block

Length

2nd Block

Optional Block

Sync

Word

Preamble

Postamble

CRC

field

Data

CI

field

Data

field

L

C-CRC

field

ACC

field

CI

CC

SN CRC

field field

field

field field

> n*2

bits

10/18/

32bits

2

1

Max 15

2

Max 16

bytes

2

1

11

1

4

0/2-8

bits

bytes

byte bytes bytes

bytes

byte bytes byte byte byte bytes

(*2)

[B0 0x07]

[B0 0x42]

[B0 0x43]

[B0 0x08]

[B1 0x25-2E]

[B0 0x44]

(*3)

(*4)

[B0 0x05]

[B0 0x7A/7B, 7D/7E]

TX: automatic insertion

RX: automatic detection, deletion

*1: 1^stBlock is identical to normal Format A..

*2: Indicating TX FIFO data storage area size.

*3: Indicating RX FIFO data storage area size.

*4: When RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)])=0b10, indicating DCLK/DIO output area.

27/230

FEDL7406-06

ML7406

(2) Format B (Wireless M-BUS)

By setting PKT_FORMAT([PKT_CTRL1: B0 0x04(1-0)])=0b01, Wireless M-BUS Format B is selected.

Format B consists of 1st Block, 2nd Block or Optional Block. Each block after 2nd Block has 2 bytes of CRC.

“L-field“ indicates packet length, which includes subsequent user data bytes from “C-field”. However, unlike Format A, CRC

bytes are included (Pastamble are exclueded). Depending on “L-field” value, 2nd Block and Optional Block(s) are added.

The following [] indicates register address [bank #, address].

Manchester/3-out-of-6 applicable [B0 0x07(3-2,1-0)]

CRC applicable

MSB

LSB

Length

1st Block

2nd Block

Optional Block

Sync

Word

Preamble

Postamble

L

C

M

A

field

CRC

field

CRC

CI

field

Data

field

Data

field

field field field

field

6

1

byte

Max 115

bytes

Max 126

bytes

10/18/

32bits byte byte

1

0/2-8

bits

> n*2 (*1)

bits

2

bytes

[B0 0x08]

[B1 0x25-2E]

(*2)

[B0 0x44]

[B0 0x07]

[B0 0x42]

[B0 0x43]

(*3)

(*4)

TX: automatic insertion

RX: automatic detection, deletion

[B0 0x05]

[B0 0x7A/7B, 7D/7E]

*1: Each mode has different minimum value of n.

*2: Indicates TX FIFO data storage area size.

*3: Indicates RX FIFO data storage area size.

*4: When RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)])=0b10, indicating DCLK/DIO output area.

28/230

FEDL7406-06

ML7406

Extended Link Layer Format

If “CI-field” (1^stbyte of 2^ndBlock ) = 0x8C or 0x8D, Extended Link Layer is applied. The packet format is as follows:

(a) CI-field = 0x8C

For TX, if 2bytes extention format is used, set EXT_PKT_MODE[1:0] ([PKT_CTRL1: B0 0x04(7-6)])=0b01.

For RX, if RX_EXTPKT_OFF([PKT_CTRL1: B0 0x04(3)])=0b0, ML7406 recognizes “CI-field” and RX operation is

processed.

Manchester/3-out-of-6 applicable [B0 0x07(3-2,1-0)]

CRC applicable

Optional Block

CRC applicable

MSB

LSB

1st Block

(*1)

Extended

Length

2nd Block

Block

CC ACC

field field field

Sync

Word

Preamble

Postamble

C-A

field

L

field

CI

CRC

field

CRC

CI

field

Data

field

Data

field

2

2-8

bits

> n*2

bits

9

1

byte

Max 112

bytes

Max 126

bytes

10/18/

32bits byte

1

bytes

byte byte byte

(*2)

[B0 0x08]

[B1 0x25-2E]

[B0 0x07]

[B0 0x42]

[B0 0x43]

[B0 0x44]

(*3)

(*4)

[B0 0x05]

[B0 0x7A/7B, 7D/7E]

TX: automatic insertion

RX: automatic detection, deletion

*1: 1^stBlock is identical to normal Format B..

*2: Indicating TX FIFO data storage area size.

*3: Indicating RX FIFO data storage area size.

*4: When RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)])=0b10, indicating DCLK/DIO output area.

29/230

FEDL7406-06

ML7406

(b) CI-field = 0x8D

For TX, if 8 bytes extention format is used, set EXT_PKT_MODE[1:0]([PKT_CTRL1: B0 0x04(7-6)])=0b10.

For RX, if RX_EXTPKT_OFF([PKT_CTRL1: B0 0x04(3)])=0b0, ML7406 recognizes “CI-field” and RX operation is

processed.

Manchester/3-out-of-6 applicable [B0 0x07(3-2,1-0)]

CRC applicable

Optional Block

CRC applicable

MSB

LSB

1st Block

(*1)

Extended

Length

2nd Block

Block

Sync

Word

Preamble

Postamble

C-A

field

SN CRC CI

field field field

L

field

CI

CC ACC

CRC

field

CRC

field

Data

field

Data

field

field field field

2-8

bits

2

1

Max. 106

2

Max.126

bytes

2

> n*2

bits

9

4

10/18/

1

bytes byte bytes bytes

bytes

32bits byte bytes byte byte byte bytes

(*2)

[B0 0x44]

[B0 0x07]

[B0 0x42]

[B0 0x43]

[B0 0x08]

[B1 0x25-2E]

(*3)

(*4)

TX: automatic insertion

RX: automatic detection, deletion

[B0 0x05]

[B0 0x7A/7B, 7D/7E]

*1: 1^stBlock is identical to normal Format B..

*2: Indicating TX FIFO data storage area size.

*3: Indicating RX FIFO data storage area size.

*4: When RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)])=0b10, indicating DCLK/DIO output area.

30/230

FEDL7406-06

ML7406

(3) Format C (non Wireless M-BUS, general purpose format)

By setting PKT_FORMAT([PKT_CTRL1: B0 0x04(1-0)])=0b10, Format C, which is non Wireless M-BUS format, is selected.

Format C consists of 1^stBlock only, which has 2 bytes of CRC. “L-field” indicates packet length, which includes subsequent

user data bytes, including CRC bytes. The length of “L-field” is defined by LENGTH_MODE([PKT_CTRL2:B0 0x5(0]). Data

Whitening function is supported.

The following [] indicates register address [bank #, address].

Manchester/3-out-of-6 applicable [B0 0x07(3-2,1-0)]

Whitening applicable [B0 0x08(0)]

CRC applicable

MSB

LSB

Length

1st Block

Sync

Word

Preamble

Postamble

L

field

CRC

field

Data

field

0/2-8

bits

Max2047

bytes

0/1/2/4

bytes

> n*2 (*1)

bit

1/2

bytes

Max

32bits

(*2)

[B0 0x08]

[B1 0x25-2E]

[B0 0x07]

[B0 0x42]

[B0 0x43]

[B0 0x44]

[B0 0x05]

(*3)

(*4)

TX: automatic insertion

RX: automatic detection, deletion

[B0 0x05]

[B0 0x7A/7B, 7D/7E]

*1 Preamble length (n) is programmable by [TXPR_LEN_H/L: B0 0x42/43] registers.

*2 indicating TX FIFO data strorage area size.

*3 Indicating RX FIFO data storage area size.

*4 When RXDIO_CTRL ([DIO_SET: B0 0x0C(7-6)])=0b10, indicating DCLK/DIO output area.

31/230

FEDL7406-06

ML7406

○CRC function

ML7406 has CRC32,CRC16 and CRC8 function. CRC is calculated and appended to TX data. CRC is checked for RX data.

The following modes are used for automatic CRC function.

●FIFO mode:

●DIO mode:

RXDIO_CTRL ([DIO_SET: B0 0x0C(7-6)]) = 0b00

RXDIO_CTRL ([DIO_SET: B0 0x0C(7-6)]) = 0b11

Function

Control bit name / Register

TX_CRC_EN([PKT_CTRL2: B0 0x05(2)])

TX CRC setting

RX CRC setting

CRC length setting

CRC complement value OFF setting

CRC polynomial setting

CRC error status

RX_CRC_EN([PKT_CTRL2: B0 0x05(3)])

CRC_LEN([PKT_CTRL2: B0 0x05(5-4)])

CRC_COMP_OFF([PKT_CTRL2: B0 0x05(6)])

[CRC_POLY3/2/1/0: B1 0x16/17/18/19] registers

[CRC_ERR_H/M/L: B0 0x13/14/15] registers

Any CRC polynomials for CRC32/CRC16/CRC8 can be specified. Reset value is as follows:

CRC16 polynomial = x¹⁶+ x¹³+ x¹²+ x¹¹+ x¹⁰+ x⁸+ x⁶+ x⁵+ x²+ 1 (reset value)

(Note) CRC result data can be inverted by CRC complement value OFF setting,.

CRC data will be generated by the following circuits. By programming [CRC_POLY3/2/1/0] registers, any CRC polynomials

can be supported. Generated CRC will be transfer from the left most bit (S15). If data length is shorter than CRC length (3 bytes

of CRC32 only), data “0”s will be added for CRC calculation. CRC check result is stored in [CRC_ERR_H/M/L] registers.

Unlike Format C, Format A/B can include multiple CRC fields in one packet. For multiple CRCs check results, CRC value

closest to L-field will be stored in CRC_ERR[0] ([CRC_ERR_L:B0 0x15(0)]). Subsequent bit will be stored in CRC_ERR from

MSB order.

CRC_POLY

[14]

CRC_POLY

[2]

CRC_POLY

[0]

CRC_POLY

[1]

CRC_POLY

[13]

Input

Data

S15

S14

S3

S2

S1

S0

(Note)

:exclusive OR

CRC polynomial circuits

General CRC polynomial can be programmed by below [CRC_POLY3/2/1/0] register setting.

CRC length can be set by CRC_LEN.

[CRC_POLY3/2/1/0]

CRC polynomial

(B1 0x16)

0x00

(B1 0x17)

0x00

(B1 0x18)

0x00

(B1 0x19)

0x03

CRC8

x⁸+ x²+ x + 1

x¹⁶+ x¹²+ x⁵+ 1

0x00

0x08

0x10

CRC16

x¹⁶+ x¹⁵+ x²+ 1

0x00

0x40

0x02

x¹⁶+ x¹³+ x¹²+ x¹¹+ x¹⁰+ x⁸+ x⁶+ x⁵+ x²+ 1

x³²+ x²⁶+ x²³+ x²²+ x¹⁶+ x¹²+ x¹¹+ x¹⁰+ x⁸+ x⁷+ x⁵+ x⁴

+ x²+ x + 1

0x00

0x1E

0xB2

CRC32

0x02

0x60

0x8E

0xDB

32/230

FEDL7406-06

ML7406

○Data whitening function (non Wireless M-BUS standard)

ML7406 supports Data whitening function. In packet format A/B, subsequent data followed by C-field can be processed data

whitening. In packet format C, data Whitening is applied from data field. Data generated by the following 9 bit pseudo random

sequence (PN9) will be “XOR” with TX data (encoded data if Manchester or 3-out-of 6 coding is selected) before transmission.

Intialization value of the PN9 generation shift register can be defined by [WHT_INIT_H/L: B1 0x64/65] registers. PN9

polynomial can be programmed with [WHT_CFG: B1 0x66] register.

Function

Data Whiteing setting enable

Data Whiteing initiazation value

Whitening polynomia

Control bit name

WHT_SET ([DATA_SET2: B0 0x08(0)])

WHT_INIT[8:0] ([WHT_INIT_H/L: B1 0x64(0)/65(7-0)])

WHT_CFG[7:0] ([WHT_CFG: B1 0x66(7-0)])

In order to make feedback from S1 register, setting 0b1 to WHT_CFG0 ([WHT_CFG: B1 0x66(0)]). Similaly in order to make

feedback from S2 register, setting 0b1 to WHT_CFG1 ([WHT_CFG: B1 0x66(1)]). Other bits of [WHT_CFG: B1 0x66]

register has same function. Two or more bits can be also set to 0b1. Therefore any type of PN9 polinominal can be

programmed.

Whitening

data

S8

S7

S6

S5

S4

S3

S2

S1

S0

(Note)

:exclusive OR

Whitening data generation circuits

(generator polynomial: x⁹+ x⁵+ 1)

General PN9 polynomial can be defined by [WHT_CFG].

WHT_CFG[7:0]

[WHT_CFG: B1 0x66]

PN9 polynomial

x⁹+ x⁴+ 1

0x08

0x10

x⁹+ x⁵+ 1

33/230

FEDL7406-06

ML7406

○SyncWord detection function

ML7406 supports automatic SyncWord recognition function. By having two sets of SyncWord pattern storage area, it is

possible to detect two different packet format (Format A/B) which are defined by Wireless M-Bus. (For details, please refer to

Wireless M-BUS standard) Receiving packet format is indicated by SW_DET_RSLT([STM_STATE:B0 0x77(5)]). In Format C,

it is possible to search for two SyncWords but detected result is not indicated.

1) TX

SyncWord pattern defined by SYNCWORD_SEL ([DATA_SET2: B0 0x08(4)]) will be selected. SyncWord length for TX is

defined by SYNC_WORD_LEN[5:0] ([SYNC_WORD_LEN: B1 0x25(5-0)]). From high bit of each SyncWord pattern will be

transmitted.

SYNCWORD_SEL

0

TX SyncWord pattern

SYNC_WORD1[31:0]

([SYNCWORD1_SET3/2/1/0: B1 0x27/28/29/2A])

SYNC_WORD2[31:0]

1

([SYNCWORD2_SET3/2/1/0: B1 0x2B/2C/2D/2E])

Example) SyncWord patten and SyncWord length

If the follwing registers are programmed, from higher bit of SYNC_WORD1[17:0] will be transmitted sequencially.

[SYNC_WORD_LEN: B1 0x25]=0x12

SYNCWORD_SEL ([DATA_SET2: B0 0x08(4)]) = 0b0

If the following registers are programmed, from higher bit of SYNC_WORD2[23:0] will be transmitted sequencially.

[SYNC_WORD_LEN: B1 0x25]=0x18

SYNCWORD_SEL ([DATA_SET2: B0 0x08(4)]) = 0b1

2) RX

By setting SYNCWORD_SEL and 2SW_DET_EN ([DATA_SET2: B0 0x08(4,3)]), one SyncWord pattern waiting or two

SyncWord patterns waiting can be selected as follows: Packet format automatic detection is valid if 2SW_DET_EN=0b1 and

Format A or Fromat B is selected by PKT_FORMAT[1:0] ([PKT_CTRL1:B0 0x04(1-0)]).

Automatic

SyncWord

2SW_DET_ SYNCWORD_

SyncWord pattern

During Sync Detection

packet

format

Detection

operation

Data process after SyncWord

EN

SEL

detection

Waiting for

1 pattern

Waiting for

1 pattern

Process according to each Format

setting

Process according to each Format

setting

0

1

SYNC_WORD1[31:0]

SYNC_WORD2[31:0]

no

[Format A or Format B setting]

If matched with SYNC_WORD1, then

process as Format A. If matched with

SYNC_WORD2, then process as

Format B.

SYNC_WORD1[31:0]

SYNC_WORD2[31:0]

Waiting for

2 patterns

1

−

yes

[Format C setting]

Process as Format C

34/230

FEDL7406-06

ML7406

Length of SyncWord pattern can be defined by SYNC_WORD_LEN[5:0] ([SYNC_WORD_LEN: B1 0x25(5-0)]). In this case,

SyncWord pattern defined by the length from low bit of SYNC_WORD1[31:0] or SYNC_WORD2[31:0] will be the pattern for

checking.

Example) SyncWord length

If the following registers are set, 18 bit of SYNC_WORD1[17:0] or SYNC_WORD2[17:0] will be reference pattern

for the SyncWord detection. Higher bits (bit31-18) are not checked.

[SYNC_WORD_LEN: B1 0x25]=0x12

[SYNC_WORD_EN: B1 0x26]=0x0F

32bit SyncWord pattern can be controlled by enabling/disabling by each 8bit, when receiving SyncWord. The following table

describes enable/disable control and SyncWord pattern.

SYNC_WORD*

[SYNC_WORD_EN]

(B1 0x26)

SyncWord detection operation

No SyncWord detection

[31:24]

[23:16]

[15:8]

[7:0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Only [7:0] are valid.

Upon [7:0] detection, SyncWord detection.

Only [15:8] are valid.

Upon [7:0] detection, SyncWord detection.

[15:0] are valid.

Upon [7:0] detection, SyncWord detection.

Only [23:16] are valid.

Upon [7:0] detection, SyncWord detection.

[23:16] and [7:0] are valid.

Upon [7:0] detection, SyncWord detection.

[23:8] are valid.

Upon [7:0] detection, SyncWord detection.

[23:0] are valid.

Upon [7:0] detection, SyncWord detection.

Only [31:24] are valid.

Upon [7:0] detection, SyncWord detection.

[31:24] and [7:0] are valid.

Upon [7:0] detection, SyncWord detection.

[31:24] and [15:8] are valid.

Upon [7:0] detection, SyncWord detection.

[31:24] and [15:0] are valid.

D.C.(*1)

ON

D.C.

ON

D.C.

ON

D.C.

ON

D.C.

ON

D.C.

ON

D.C.

ON

D.C.

ON

D.C.

ON

D.C.

ON

Upon [7:0] detection, SyncWord detection.

[31:16] are valid.

Upon [7:0] detection, SyncWord detection.

[31:16] and [7:0] are valid.

Upon [7:0] detection, SyncWord detection.

[31:8] are valid.

Upon [7:0] detection, SyncWord detection.

Whole [31:0] are valid.

ON

D.C.

ON

D.C.

ON

D.C.

ON

Upon [7:0] detection, SyncWord detection.

*1 D.C. stands for Don’t Care.

*2 Preamble pattern can be added to the SyncWord detection conditions by RXPR_LEN[5:0]([SYNC_CONDITION1: B0

0x45(5-0)]).

35/230

FEDL7406-06

ML7406

○Field check function

ML7406 has the function of comparing the 9 bytes following L-field (Format A/B: start from C-field, Format C: start from

Data-field) in a receiving packet. Based on comparison with the expected data, possible to generate interrupts (Field check

function). Field check can be possible with the following register setting. When using this function, RXDIO_CTRL[1:0]

([DIO_SET:B0 0x0C(7-6)] ) =0b00 (FIFO mode) or 0b11 (data output mode 2) setting is required.

Function

RX data process setting when Field check unmatched

Field check interrupt setting

C-field detection enable setting

M-field detection enable setting

A-field detection enable setting

C-field code setting

Register

[C_CHECK_CTRL: B0 0x1B(7)]

[C_CHECK_CTRL: B0 0x1B(6)]

[C_CHECK_CTRL: B0 0x1B(4-0)]

[M_CHECK_CTRL: B0 0x1C(3-0)]

[A_CHECK_CTRL: B0 0x1D(5-0)]

[C_FIELD_CODE1: B0 0x1E]

[C_FIELD_CODE2: B0 0x1F]

[C_FIELD_CODE3: B0 0x20]

[C_FIELD_CODE4: B0 0x21]

[C_FIELD_CODE5: B0 0x22]

[M_FIELD_CODE1: B0 0x23]

[M_FIELD_CODE2: B0 0x24]

[M_FIELD_CODE3: B0 0x25]

[M_FIELD_CODE4: B0 0x26]

[A_FIELD_CODE1: B0 0x27]

[A_FIELD_CODE2: B0 0x28]

[A_FIELD_CODE3: B0 0x29]

[A_FIELD_CODE4: B0 0x2A]

[A_FIELD_CODE5: B0 0x2B]

[A_FIELD_CODE6: B0 0x2C]

M-field code setting

A-field code setting

The following describes the relation between each comparison code and incoming RX data.

[Format A/B(Wireless M-Bus)]

Field check can be controlled by setting disabled/enabled for each comparison code (1 byte). If all specified Field data

(C-field/M-field/A-field) are matched, Field checking matching will be notified. However, if C-field data and

C_FIELD_CODE5 are matched, even if other Field data (M-field/A-field) are not matched, Field check result will be notified

as ”match”.

LSB

MSB

1st Block

Sync

Word

Preamble

L

C

M

A

CRC

field field

field

0/2

2

6

10/18/

1

Over n*2

bit

bytes

32bits byte byte

A1

A2

A3

A4

A5

A6

C1 M1

C2 M2

C3

M3

M4

C1: [C_FIELD_CODE1: B0 0x1E]

C2: [C_FIELD_CODE2: B0 0x1F]

C3: [C_FIELD_CODE3: B0 0x20]

C4: [C_FIELD_CODE4: B0 0x21]

C5: [C_FIELD_CODE5: B0 0x22]

A1. [A_FIELD_CODE1: B0 0x27]

A2. [A_FIELD_CODE2: B0 0x28]

A3. [A_FIELD_CODE3: B0 0x29]

A4. [A_FIELD_CODE4: B0 0x2A]

A5. [A_FIELD_CODE5: B0 0x2B]

A6. [A_FIELD_CODE6: B0 0x2C]

C4

C5

M1. [M_FIELD_CODE1: B0 0x23]

M2. [M_FIELD_CODE2: B0 0x24]

M3. [M_FIELD_CODE3: B0 0x25]

M4. [M_FIELD_CODE4: B0 0x26]

36/230

FEDL7406-06

ML7406

Check Field

C-field

Comaprison Code

C_FIELD_CODE1 or C_FIELD_CODE2 or

C_FIELD_CODE3 or C_FIELD_CODE4 or

C_FIELD_CODE5

M_FIELD_CODE1 or

M_FIELD_CODE2

M_FIELD_CODE3 or

M_FIELD_CODE4

A_FIELD_CODE1/2/3/4/5/6

Conditions for match

If one of the 5 comparison code is matched

M-field 1^stbyte

M-field 2^ndbyte

A-field

If one of the 2 comparison code is matched.

If comparison codes are matched.

[Format C]

Field check can be controlled by setting disabled/enabled for each comarison code (1 byte). If all specified Field data

(specified table below) are matched, Field checking matching will be notified. However, if 1^stbyte of Data field and

C_FIELD_CODE5 are matched, even if other Field data(from 2^ndbyte of Data field to 9^thbyte of Data field) are not matched,

Field check result will be notified as ”match”.

LSB

MSB

1st Block

Sync

Word

Preamble

L

field

Data

field

···

1

Over n*2

bit

10/18/

1-2

1

32bits byte byte byte byte byte byte byte byte byte byte

A1

A2

A3

A4

A5

A6

C1 M1

C2 M2

C3

M3

M4

A1. [A_FIELD_CODE1: B0 0x27]

A2. [A_FIELD_CODE2: B0 0x28]

A3. [A_FIELD_CODE3: B0 0x29]

A4. [A_FIELD_CODE4: B0 0x2A]

A5. [A_FIELD_CODE5: B0 0x2B]

A6. [A_FIELD_CODE6: B0 0x2C]

C1: [C_FIELD_CODE1: B0 0x1E]

C2: [C_FIELD_CODE2: B0 0x1F]

C3: [C_FIELD_CODE3: B0 0x20]

C4: [C_FIELD_CODE4: B0 0x21]

C5: [C_FIELD_CODE5: B0 0x22]

C4

C5

M1. [M_FIELD_CODE1: B0 0x23]

M2. [M_FIELD_CODE2: B0 0x24]

M3. [M_FIELD_CODE3: B0 0x25]

M4. [M_FIELD_CODE4: B0 0x26]

Check Field

Comparison Code

Conditions for match

If one of the 5 comparison code is matched

Data-field 1^stbyte

C_FIELD_CODE1 or C_FIELD_CODE2 or

C_FIELD_CODE3 or C_FIELD_CODE4 or

C_FIELD_CODE5

Data-field 2^ndbyte

Data-field 3^rdbyte

Data-field 4^thbyte

Data-field 5^thbyte

Data-field 6^thbyte

Data-field 7^thbyte

Data-field 8^thbyte

Data-field 9^thbyte

M_FIELD_CODE1 or M_FIELD_CODE2

M_FIELD_CODE3 or M_FIELD_CODE4

A_FIELD_CODE1

A_FIELD_CODE2

A_FIELD_CODE3

A_FIELD_CODE4

A_FIELD_CODE5

A_FIELD_CODE6

If one of the 2 comparison code is matched.

If comparison code is matched.

37/230

FEDL7406-06

ML7406

●Packet processing as a result of Field checking

By setting CA_RXD_CLR ([C_CHECK_CTRL: B0 0x1B(7)])=0b1, if the result of Field check is unmatch, data packet will

be aborted and wait for next packet data.

●Storing number of unmatched packets

Unmatched packets can be counted up to max. 2047 packets and result are stored in [ADDR_CHK_CTR_H: B1 0x62]

and[ADDR_CHK_CTR_L: B1 0x63]. This count value can be cleared by STATE_CLR4 ([STATE_CLR: B0 0x16(4)]).

38/230

FEDL7406-06

ML7406

○FIFO control function

ML7406 has on-chip TX_FIFO(64Byte) and RX_FIFO(64Byte). As TX/RX_FIFO do not support multiple packets, packet

should be processed one by one. If RX_FIFO keeps RX packet and next RX packet is received, RX_FIFO will be overwritten. It

applies to TX_FIFO as well. However TX FIFO access error interrupt (INT[20] group3) will be generated. When receiving, RX

data is stored in FIFO (byte by byte) and the host MCU will read RX data through SPI. When transmitting, host MCU write TX

data to TX_FIFO through SPI and transmitting through RF.

Writing or reading to FIFO is through SPI with burst access. TX data is written to [WR_TX_FIFO: B0 0x7C] register. RX

data is read from [RD_FIFO: B0 0x7F] register. Continuous access increments internal FIFO counter automatically. If FIFO

access is suspended during write or read operation, address will be kept until the packet will be process again. Therefore, when

resuming FIFO access, next data will be resumed from the suspended address.

FIFO control register are as follows:

Function

TX FIFO Full level setting

TX FIFO Empty level setting

RX FIFO Full level setting

RX FIFO Empty level setting

FIFO readout setting

Register

[TXFIFO_THRH: B0 0x17]

[TXFIFO_THRL: B0 0x18]

[RXFIFO_THRH: B0 0x19]

[RXFIFO_THRL: B0 0x1A]

[FIFO_SET: B0 0x78]

RX FIFO data usafe status indication

TX packet Length setting

RX packet Length setting

TX FIFO

[RX_FIFO_LAST: B0 0x79]

[TX_PKT_LEN_H/L: B0 0x7A/7B]

[RX_PKT_LEN_H/L: B0 0x7D/7E]

[WR_TX_FIFO: B0 0x7C]

FIFO read

[RD_FIFO: B0 0x7F]

TX – RX procedure using FIFO are as follows:

[TX]

i) TX data L-field value is set to [TX_PKT_LEN_H: B0 0x7A], [TX_PKT_LEN_L: B0 0x7B] register. If Length is 1

byte, [TX_PKT_LEN_L] register will be transmitted.

Length can be set to LENGTH_MODE([PKT_CTRL2: B0 0x05(0)]).

ii) TX data is written to [WR_TX_FIFO:B0 0x7C] register.

(Note)

1. If TX_FIFO write sequence is aborted during transmission, STATE_CLR0 [STATE_CLR:B0 0x16(0)] (TX FIFO

pointer clear) must be issued. Otherwise data pointer is kept in the LSI and the next packet is not processed properly.

For example, TX FIFO access error interrupt (INT[20] group3) is generated. This interrupt can be generated when the

next packet data is writren to the TX_FIFO before transmitting previous packet data or TX_FIFO overrun (FIFO is

written when no TX_FIFO space) or underrun (attempt to transmit when TX_FIFO is empty)

2. Depending on the packet format, TX data Length value is different.

Format A: Length includs data area excluding L-field and CRC data.

Format B: Length includes data area excluding L-field.

Format C: Length includes data area excluding L-field.

[RX]

i) L-field (Length) is read from [RX_PKT_LEN_H: B0 0x7D], [RX_PKT_LEN_L: B0 0x7E] registers.

ii) Reading RX data from RX_FIFO. When reading from RX_FIFO, set FIFO_R_SEL([FIFO_SET: B0 0x78(0)])= 0b0.

If FIFO_R_SEL=0b1 , TX_FIFO will be selected. Data usage value of RX_FIFO is indicated by [RX_FIFO_LAST: B0

0x79] register.

39/230

FEDL7406-06

ML7406

(Note)

1. If reading FIFO data is terminated before reading all data, STATE_CLR1 [STATE_CLR: B0 0x16(1)] (RX FIFO

pointer clear) must be issued. Otherwise If RX_FIFO is not cleared, the pointer controlling FIFO data keeps the same

status. Next RX data will not be processed in the FIFO properly.

For example, when RX_FIFO access error interrupt (INT[12] group2) is generated. This interrupt occurs when

RX_FIFO overrun (data received when no space in RX_FIFO) or underrun (reading empty RX_FIFO).

2. If 1 packet data is kept in the RX_FIFO, next RX data will be overwritten.

IF TX/RX pack is larger than FIFO size, FIFO access can be controlled by FIFO-Full trigger or FIFO-Empty trigger.

(1) TX FIFO usage notification function

This function is to notice TX_FIFO usage to the MCU using interrupt (SINTN). If TX_FIFO usage (un-transmitted data in

TX_FIFO) exceed the Full level threshold set by [TXFIFO_THRH: B0 0x17] register, interrupt will generate as FIFO-full

interrupt (INT[5] group1). If TX_FIFO usage is smaller than Empty level threshold set by [TXFIFO_THRL: B0 0x18] register,

FIFO-Empty interrupt will generate as FIFO-Empty interrout (INT[4] grou1). Interrupt signal (SINTN) can be output from

GPIO* or EXT_CLK pin.

For output setting, please refer to [GPIO0_CTRL: B0 0x4E], [GPIO1_CTRL: B0 0x4F], [GPIO2_CTRL: B0 0x50],

[GPIO3_CTRL: B0 0x51], [EXTCLK_CTRL: B0 0x52] registers for output setting.

[FIFO usage]

SINTN signal

0x3F

Clear interrupt

Generate interrupt

when written Data

exceed Full level

TX data amount

Full level

(Example 0x2E)

Generate interrupt

when TX data usage

is smaller than Empty

level

Full level

0x2E

0x0F

Empty level

(Example 0x0F)

Empty level

Time

TX start timing by

FAST_TX trigger

TX_FIFO usage transition

0x00

(Reference Sequence)

1.

Set Full level threshold and Empy level threshold..Each threshold should set as TXFIFO_THRH[5:0]

([TXFIFO_THRH:B0 0x17(5-0)]) > TXFIFO_THRL[5:0] ([TXFIFO_THRL:B0 0x18(5-0)]). And enabling Full level

threshold by TXFIFO_THRH_EN([TXFIFO_THRH:B0 0x17(7)=0b1.

2.

3.

4.

Enabling FAST_TX mode by FAST_TX_EN([RF_STATUS_CTRL:B0 0x0A(5)])=0b1 and start writing TX data to the

TX_FIFO[WR_TX_FIFO:B0 0x7C] until FIFO-Full interrupt (INT[5] group1) occurs.

After FIFO-Full interrupt is generated, Clear the interupt. Then disabling Full level threshold (TXFIFO_THRH_EN=

0b0) and enabling Empty level threshold (TXFIFO_THRL_EN([TXFIFO_THRL:B0 0x18(7)])=0b1).

After FIFO-Empty interrupt (INT[4] group1) is generated, Clear the interupt. Then disabling Empty level threshold

(TXFIFO_THRL_EN=0b0) and enabling Full level threshold (TXFIFO_THRH_ EN=0b1). Then resume writing TX

data to the TX_FIFO until next FIFO-Full interrupt occurs.

5.

Repeat 3.-4. until completion of TX.

40/230

FEDL7406-06

ML7406

(Note)

When skip disabling threshold level at sequece 3. or 4., depending on TX data read (PHY block) and TX_FIFO write timing

through SPI, in the middle of TX_FIFO writing, unwiilling FIFO-Full interrupt or FIFO-Empty interrupt may occurs.

(2) RX FIFO usage notification function

This function is to notify RX_FIFO usage amount by using interrupt (SINTN) to the MCU. If RX_FIFO usage (un-read data in

RX_FIFO) exceed Full level threshold defined by [RXFIFO_THRH: B0 0x19] register, interrupt will generate as FIFO-Full

interrupt (INT[5] group1). After MCU read RX data from RX_FIFO, un-read amount become smaller than Empty level

threshold defined by [RXFIFO_THRL: B0 0x1A] register, interrupt will generated as FIFO-Empty (INT[4] group1). Interrupt

signal (SINTN) can be output from GPIO* or EXT_CLK.

For output setting, please refer to [GPIO0_CTRL: B0 0x4E], [GPIO1_CTRL: B0 0x4F], [GPIO2_CTRL: B0 0x50],

[GPIO3_CTRL: B0 0x51], [EXTCLK_CTRL: B0 0x52] registers.

[FIFO usage]

SINTN signal

0x3F

Generate interrupt,

when RX data exceed

Full level,

Clear interrupt

RX data amount

FULL level

(Example 0x3E)

Generate interrupt,

when un-read data

amount is less than

Empty level after

read RX data from

RX_FIFO,

Full level

0x3E

0x0F

EMPTY level

(Example 0x0F)

Empty level

Time

RX_FIFO usage transition

0x00

(Reference Sequence)

1. Set Full level threshold and Empy level threshold..Each threshold should set as RXFIFO_THRH[5:0]

([RXFIFO_THRH:B0 0x19(5-0)]) > RXFIFO_THRL[5:0] ([RXFIFO_THRL:B0 0x1A(5-0)]). And enabling Full

level threshold by RXFIFO_THRH_EN([RXFIFO_THRH:B0 0x19(7)=0b1.

2. After issuing RX_ON, wait FIFO-Full interrupt (INT[5] group1) generation.

3. After FIFO-Full interrupt is generated, Clear the interupt. Then disabling Full level threshold (RXFIFO_THRH_EN=

0b0) and enabling Empty level threshold (RXFIFO_THRL_EN([RXFIFO_THRL:B0 0x1A(7)])=0b1). And start

reading RX data from RX_FIFO [RD_FIFO:B0 0x7F].

4. After FIFO-Empty interrupt (INT[4] group1) is generated, Clear the interupt. Then disabling Empty level threshold

(TXFIFO_THRL_EN=0b0) and enabling Full level threshold (TXFIFO_THRH_ EN=0b1). Then resume writing TX

data to the TX_FIFO until next FIFO-Full interrupt occurs.

5. Repeat 3.-4. until completion of RX data read out.

(Note)

1. When skip disabling threshold level at sequece 3. or 4., depending on RX data write (PHY block) and RX_FIFO read

timing through SPI, in the middle of RX_FIFO reading, unwiilling FIFO-Full interrupt or FIFO-Empty interrupt may

occurs.

2. This function is valid during data receiving. FIFO-Empty interrupt does not occur after RX completion.

41/230

FEDL7406-06

ML7406

○DIO function

Using GPIO0-3, EXT_CLK or SDI/SDO pins, TX/RX data can be input/output. Pins can be configured by [GPIO*_CTRL: B0

0x4E/0x4F/0x50/0x51], [EXTCLK_CTRL: B0 0x52] and [SPI/EXT_PA_CTRL: B0 0x53] registers.

Data format for TX/RX are as follows:

TX --- TX data (NRZ or Manchester/3-out-of-6coding) will be input.

RX --- pre-decoded RX data or decoded RX data will be output. (selectable by [DIO_SET: B0 0x0C] register)

DIO function registers are as follows:

Function

DIO RX data output start setting

DIO RX completion setting

TX DIO mode setting

Registers

[DIO_SET: B0 0x0C(0)]

[DIO_SET: B0 0x0C(2)]

[DIO_SET: B0 0x0C(5-4)]

[DIO_SET: B0 0x0C(7-6)]

RX DIO mode setting

(1) In case of using GPIO*, EXT_CLK pins

If GPIO0-3 or EXT_CLK pins are used as DCLK/DIO, DCLK/DIO should be controlled as follow. (below DIO/DCLK

vertical line part indicate output or input period)

[TX]

i) Continuous input mode (from host)

Set TXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(5-4)]) =0b01.

After TX_ON(SET_TRX[3:0]([RF_STATUS: B0 0x0B(3-0)])=0x9), DCLK is output continuously. At falling edge of

DCLK, TX data is input from DIO pin. TX data must be encoded data.

TX_ON

TX data

Preamble

SyncWord

Data-field

DIO(GPIO0-3,EXT_CLK)

DCLK(GPIO0-3,EXT_CLK)

TX_ON

command

TRX_OFF

command

(Note) For details of timing, please refer to the “TX” in the “Timing Chart”.

ii) Data input mode (from host)

Set TXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(5-4)]) =0b10.

After TX_ON, DCLK is output during data input period after SyncWord. TX data is input at falling edge of DCLK through

DIO input. Encoded TX data must be transferred from the host. Preamble and SyncWordis generated automatically

according to the registers setting.

TX_ON

TX data

Preamble

SyncWord

Data-field

DIO(GPIO0-3,EXT_CLK)

DCLK(GPIO0-3,EXT_CLK)

TX_ON

command

TRXOFF

command

42/230

FEDL7406-06

ML7406

Preamble can be set by PB_PAT([DATA_SET1: B0 0x07(7)] and TXPR_LEN[15:0] ([TXPR_LEN_H/L: B0 0x42/43]).

SyncWord can be set by SYNCWORD_SEL([DATA_SET2: B0 0x08(4)), SYNCWORD_LEN[5:0] ([SYNC_WORD_

LEN: 1 0x25(5-0)]), SYNC_WORD_EN* ([SYNC_WORD_EN: B1 0x26(3-0)]), SYNC_WORD1[31:0] ([SYNCWORD1_

SET3/2/1/0: B1 0x27/28/29/2A]), SYNC_WORD2[31:0] ([SYNCWORD2_SET3/2/1/0: B1 0x2B/2C/2D/2E]).

[RX]

i) Continuous output mode (to host)

Set RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)])=0b01.

After RX_ON(SET_TRX[3:0] ([RF_STATUS: B0 0x0B(3-0)])=0x6), DCLK is output continuously. RX data (demodulated

data) is output from DIO pin at falling edge of DCLK. RX data is not stored in RX_FIFO.

RX_ON

RX data

Preamble

SyncWord

Data-field

DIO(GPIO0-3,EXT_CLK)

DCLK(GPIO0-3,EXT_CLK)

RX_ON

command

TRX_OFF

command

(Note) For details of timing, please refer to the “RX” in the “Timing Chart”.

ii) Data output mode 1 (to host)

Set RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)]) =0b10.

After SyncWord detection, RX data is buffered in RX_FIFO. RX data buffering will continue until RX sync signal

(SYNC) becomes ”L”. By setting DIO_START ([DIO_SET: B0 0x0C(0)])=0b1, top data of buffered data will be output

through DIO interface (DIO/DCLK). (RX data is output at falling edge of DCLK). However, if DIO_START setting is

done after 64 byte timing, the top byte will be over written. If all buffered data is output until SYNC becomes ”L”, RX

completion interrupt (INT[8] group 2) will be generated. After RX completion, ready to receive next packet.

RX_ON

RX data

Preamble

SyncWord

Data-field

RX sync signal

Buffering to RX_FIFO

DIO(GPIO0-3,EXT_CLK)

DCLK(GPIO0-3,EXT_CLK)

RX_ON

command

DIO_START =0b1

TRX_OFF

command

(Note)

1.

RX data buffering in RX_FIFO is accessed byte by byte. DIO_START should be issued after 1 byte access time upon SyncWord

detection.

2.

This mode does not process L-field. Field checking function is not supported.

43/230

FEDL7406-06

ML7406

If DIO_START is issued before SyncWord detection, data is not buffered in RX_FIFO and RX data after SyncWord

detection will be output at falling edge of DCLK . In order to complete RX before SYNC becomes ”L”, DIO RX completion

setting (DIO_RX_COMPLETE([DIO_SET: B0 0x0C(2)]=0b1) is necessary. After DIO_RX_COMPLETE setting, ready to

receive the next packet.

RX_ON

RX data

Preamble

SyncWord

Data-field

RX sync signal

Buffering to RX_FIFO

DIO(GPIO0-3,EXT_CLK)

DCLK(GPIO0-3,EXT_CLK)

RX_ON

Command

DIO_RX_COMPLETE

=0b1

DIO_START=0b1

TRXOFF

command

iii) Data output mode 2 (to host)

Set RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)])=0b11.

Only Data-field of RX data is buffered in RX_FIFO. RX data indicated by L-field is stored in RX_FIFO. By

DIO_START([DIO_SET: B0 0x0C(0)])=0b1, top data of buffered data will be output through DIO interface

(DIO/DCLK). (RX data is output at falling edge of DCLK).

However, if DIO_START setting is done after 64 byte timing, the top byte will be overwritten. If all data indicated by

L-field is output, RX completion interrupt (INT[8] group2) will be generated. After RX completion, ready to receive next

packet. Length information is stored in [RX_PKT_LEN_H/L: B0 0x7D/7E] registers. This mode support fileld check

function.

RX_ON

RX data

Preamble

SyncWord

L-field

Data-field

DIO(GPIO0-3,EXT_CLK)

DCLK(GPIO0-3,EXT_CLK)

RX_ON

Command

DIO_START

issue

TRX_OFF

command

(Note)

RX data buffering in RX_FIFO is byte by byte access. DIO_START should be issued after elapsed time from SyncWord

detection to L-field length + over 1byte access time.

44/230

FEDL7406-06

ML7406

(2) In case of using SDI/SDO pin (sharing with SPI interface)

If SDI and SDO pins are used DCLK/DIO, DCLK/DIO is controlled as follow. (below DIO/DCLK vertical line part indicate

output or input.) Both SDO_CFG and SDI_CFG ([SPI/EXT_PA_CTRL:B0 0x53 (5,4)]) should be set 0b1.

[TX]

i) Continuous input mode (from host)

Set TXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(5-4)])=0b01

After TX_ON(SET_TRX[3:0] ([RF_STATUS: B0 0x0B(3-0)])=0x9), during SCEN pin is ”H”, DCLK is output from SDO pin.

TX data can be input from SDI pin at falling edge of DCLK. TX data must be encoded data. After TRX_OFF is issued

(SET_TRX[3:0] ([RF_STATUS: B0 0x0B(3-0)])=0x8), input data from DIO pin are not valid. During DCLK output, if SCEN

pin becomes “L”, DCLK output will stop. (SPI access has priority)

TX_ON

TX data

Preamble

SyncWord

Data-field

SCEN

DIO(SDI)

DCLK(SDO)

TX_ON

command

TRX_OFF

command

(Note)

Not to access SPI until TX completion. During packet transmission, if SPI access is attempted by the host, TX data error can

be expected.

ii) Data input mode (from host)

Set TXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(5-4)])=0b10.

After TX_ON, when SCEN is ”H”, DCLK is output from SDO pin during data input period after SyncWord. At falling edge of

DCLK, TX data should be input to SDI from the host. After TRX_OFF is issued (SET_TRX[3:0] ([RF_STATUS: B0

0x0B(3-0)])=0x8), TX data/clock input/output are invalid. During DCLK output period, if SCEN becomes “L”, DCLK output

will stop. (SPI access has a priority)

TX_ON

TX data

Preamble

SyncWord

Data-field

SCEN

DIO(SDI)

DCLK(SDO)

TX_ON

command

TRX_OFF

command

(Note)

Not to access SPI until TX completion. During packet transmission, if SPI access is attempted by the host, TX data error can be

expected.

45/230

FEDL7406-06

ML7406

[RX]

i) Continuous output mode (to host)

Set RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)])=0b01.

After RX_ON (SET_TRX[3:0]([RF_STATUS: B0 0x0B(3-0)])=0x6) issued, during SCEN is ”H” period, DCLK is output from

SDO pin, RX data is output from SDI pin at falling edge of DCLK. After TRX_OFF issuing(SET_TRX[3:0] ([RF_STATUS:

B0 0x0B(3-0)])=0x8), DCLK/DIO output will stop. Even if DCLK/DIO are output, when SCEN becomes “L”, DCLK/DIO

will stop. (SPI access has a higher priority)

RX_ON

RX data

Preamble

SyncWord

Data-field

SCEN

DIO(SDI)

DCLK(SDO)

RX_ON

command

TRX_OFF

command

(Note)

Not to access SPI until RX completion. During packet receiption, if SPI access is attemped by the host, RX data error can be

expected. It is recommended

ii) Data ouput mode 1 or data output mode 2 (to host)

Set RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)])=0b10/11

After RX_ON, RX data upon SyncWord (output mode 1) or RX data upon L-fileld (output mode 2) is buffered in RX_FIFO.

During SCEN is ”H”, by DIO_START([DIO_SET: B0 0x0C(0)])=0b1, top data of buffered data will be output through DIO

interface (DIO/DCLK). (RX data is output at falling edge of DCLK). Other output condition is same as the case of using

GPIO:/ECT_CLK pins. After TRX_OFF isuing, DCLK/DIO output will stop. Even during DCLK/DIO are output period, if

SCEN becomes “L”, DCLK/DIO output will stop. (SPI access has a priority)

(In case of data output mode1)

RX_ON

RX data

Preamble

SyncWord

Data-field

SCEN

DIO(SDI)

DCLK(SDO)

RX_ON

command

TRX_OFF

command

DIO_START

=0b1

DIO_RX_COMPLETE

=0b1

(Note)

Not to access SPI until RX completion. During packet receiption, if SPI access is attemped by the host, RX data error can be

expected.

46/230

FEDL7406-06

ML7406

(3) DCLK output method

In Data output mode 2, decoded data is output. Therefore, The DCLK output section in a output interval changes with the

coding method. DCLK output section is as follows.

In othe modes, undecoded data is input or output. DCLK is output continuously. Then, it is not depend on the coding method.

i) Data output mode 2

DCLK

Clock output (8 cycle)

1 cycle=1/data rate[bps]

Output interval

NRZ

Output interval

: 8 cycle

Manchester : 16 cycle

3 out of 6 : 12 cycle

ii) TX continuous input mode or RX continuous mode

DCLK

1 cycle=1/data rate[bps]

(*) The nuber of cycle per 1 byte

NRZ : 8 cycles

Manchester : 16 cycles

3 out of 6 : 12 cycles

iii) TX Data input mode / RX Data output mode1

DCLK

1 cycle=1/data rate[bps]

TX: The timing during transmitting

the last 2 bit SyncWord

RX: DIO_START issue

(*) The nuber of cycle per 1 byte

NRZ : 8 cycles

Manchester : 16 cycles

3 out of 6 : 12 cycles

47/230

FEDL7406-06

ML7406

●Timer Function

○Wake-up timer

ML7406 has automatic wake-up function using wake-up timer. The following operations are possible by using wake-up timer.

 Upon timer completion, automatically wake-up from SLEEP state. After wake-up operation can be selected as RX_ON

state or TX_ON state by WAKEUP_MODE ([SLEEP/WU_SET: B0 0x2D(6)]).

 By setting WUT_1SHOT_MODE ([SLEEP/WU_SET: B0 0x2D(7)]), continuous wake-up operation (interval operation)

or one shot operation can be selected

 In interval operation, if RX_ON /TX_ON state is caused by wake-up timer, continuous operation timer is in operation..

 After moving to RX_ON state by wake-up timer, when continuous operation timer completed, move to SLEEP state

automatically. However, if SyncWord is detected before timer completion, RX_ON state will be maintained. In this case,

ML7406 does not go back to SLEEP state automatically. SLEEPsetting (SLEEP_EN[SLEEP/WU_SET: B0

0x2D(0)])=0b1) is necessary to go back to SLEEP state. However if RXDONE_ MODE[1:0]([RF_STATUS_CTRL:B0

0x0A(3-2)]) =0b11, after RX completion, move to SLEEP state automatically.

 After moving to TX_ON state by wake-up timer, when continuous operation timer completed, go back to SLEEPstate

automatically.

 After wake-up by combining with high speed carrier checking mode, CCA is automatically performed, if IDLE is

detected, able to move to SLEEP state immediately. For details, please refer to the “(3) high speede carrier detection

mode”.

 By setting WU_CLK_SOURCE ([SLEEP/WU_SET:B0 0x2D(2)]), clock source for wake-up timer are selectable from

EXT_CLK pin or on-chip RC OSC.

Wake-up intervalm, wake-up timer interval and continuous operation timer can be calculated in the following formula.

Wake-up interval [s] = Wake-up timer interval [s] + Continuous operation timer [s]

Wake-uptimer interval [s] = Wake-up timer clock cycle *

Division setting ([WUT_CLK_SET: B0 0x2E(3-0)]) *

Wake-up timer interval setting ([WUT_INTERVAL_H/L: B0 0x2F/0x30])

Continuous operation timer [s] = Wake-up timer clock cycle *

Division setting([WUT_CLK_SET: B0 0x2E(7-4)]) *

Continuous operation timer setting ([WU_DURATION: B0 0x31] - 1)

(Note)

 In case of moving to TX_ON state after wake-up, move to SLEEP state when timer completed even in the middle of

transmission. Continuous oeration timer should be set in such manner that timer completing after TX completion.

 WUDT_CLK_SET[3:0] ([WUT_CLK_SET: B0 0x2E(7-4)]) and WUT_CLK_SET[3:0] ([WUT_CLK_SET: B0 0x2E

(3-0)]) can be set independently. In case of using continuous operation timer, please set the same value as

WUDT_CLK_SET as WUT_CLK_SET.

 Minimum value for wake-up timer interval setting ([WUT_INTERVAL_H/L: B0 0x2F/0x30]) is 0x02. And minimum value

for continuous operation timer setting ([WU_DURATION: B0 0x31]) is 0x01.

 Be noted that the SyncWord detection is not issued when in DIO mode with RXDIO_CTRL([DIO_SET: B0

0x0C(7-6)])=0b01. Therefore, when continuous operation timer completed, forcibly move to SLEEP state.

 When the SLEEP time is long, the wake-up timer function can not be used. For details, refer to "SLEEP setting".

48/230

FEDL7406-06

ML7406

(1) Interval operation

[RX]

After wake-up, RX_ON state. If continuous operation timer completed before SyncWord detection, automatically return to

SLEEP state. If SyncWord detected, continue RX_ON. After RX completion, continue operation defined by RXDONE_

MODE[1:0] ([RF_STATUS_ CTRL: B0 0x0A(3-2)]) .

[SLEEP/WU_SET: B0 0x2D(6-4)]=0b011

Continuous operation timer range

[WU_DURATION: B0 0x31]

Wake-up timer operation range

[WUT_INTERVAL_H/L: B0 0x2F/0x30]

Wake-up timer

Continuous

operation timer

RXON

TXON

SLEEP

*1

LSI state

RXON

SLEEP

RXON

SLEEP

Wake-up timer

enable setting

After Wake-up timer

completion , move to

RX_ON state.

Before Continuous

operation timer

completion,

After RX completion, move to SLEEP

state by SLEEP command.

*1 If not issuing SLEEP command,

continue operation defined by

RXDONE_MODE[1:0]

SyncWord detected.

Continuous operation

timer completion

move to SLEEP

state.

[TX]

After wake-up, TX_ON state. After TX completion, continue operation defined by TXDONE_MODE[1:0] ([RF_STATUS_

CTRL: B0 0x0A(1-0)]) .

If continuous operation timer completed, automatically return to SLEEP state. So continuous operation timer has to be set so

that timer completion occur after TX completion.

[SLEEP/WU_SET: B0 0x2D(6-4)]=0b111

Continuous operation timer range

[WU_DURATION: B0 0x28]

Wake-up timer operation period

[WUT_INTERVAL_H/L: B0 0x2F/0x30]

Wake-up timer

Continuous

operation timer

RXON

TXON

SLEEP

TXON

IDLE

SLEEP

LSI state

TX data write

to TX_FIFO

Wake-up operation

enables setting

Continuous operation

timer completion, move

to SLEEP state.

TX completion and move to

IDLE state.

In case of

TXDONE_MODE[1:0]=0b00

49/230

FEDL7406-06

ML7406

(2) 1 shot operation

[RX]

After wake-up timer completion, move to RX_ON state. And continue RX_ON state. Move to SLEEP state by SLEEP

command. If wake-up timer interval ([WUT_INTERVAL_H/L: B0 0x2F/0x30]) is maintained, after re-issuing SLEEP

command, 1 shot operation will be activated again. If RX completed during RX_ON, continue operation defined by

RXDONE_ MODE[1:0] ([RF_STATUS_ CTRL: B0 0x0A(3-2)]) . Same manner in TX_ON state.

[SLEEP/WU_SET: B0 0x2D(7-4)]=0b1011

Wake-up timer operation range

[WUT_INTERVAL_H/L: B0 0x2F/0x30]

Wake-up timer

Continuous

operation timer

RXON

TXON

RXON

SLEEP

RXON

SLEEP

LSI state

After SLEEP command,

move to SLEEP state.

Wake-up operation

enable setting

Wake-up timer completion

and move to RXON state

RX_ON is maintained if

SLEEP command is not

issued.

(3) Combination with high speed carrier detection

[Interval operation]

After wake-up timer completion, move to RX_ON state. Then perform CCA. If no carrier detected, automatically move to

SLEEP state. If carrier detected, maintaining RX_ON state and perform SuncWord detection. If continuous operation timer

completed before SyncWord detection, automatically move to SLEEP state. And If SyncWord detected, continue RX_ON

state state.

[SLEEP/WU_SET: B0 0x2D(7-4)]=0b0011

FAST_DET_MODE_EN([CCA_CTRL: B0 0x39(3)])=0b1

Wake-up timer operation range

[WUT_INTERVAL_H/L: B0 0x2F/0x30]

Continuous operation timer range

[WU_DURATION: B0 0x28]

Wake-up timer

Continuous operation timer

RXON

TXON

SLEEP

RXON

SLEEP

RXON

SLEEP

SLEEP RXON

RXON

LSI state

After RX completion,

move to SLEEP state

by command.

Wake up operation

enable setting

Continuous operation

timer completion. and

move to SLEEP state.

No carrier detection,

and move to SLEEP

state.

SyncWord detection before

continuous operation timer

completion

Carrier detected and

continue RXON.

50/230

FEDL7406-06

ML7406

[1 shot operation]

After wake-up timer completion, move to RX_ON state. And perform CCA to check carrier. If no carrier detected, go back to

SLEEP state automatically. After wake-up timer completion, wake-up to check the carrier again. If carrier is detected, continue

RX state. Able to go back to SLEEP by setting SLEEP parameters.

[SLEEP/WU_SET: B0 0x2D(7-4)]=0b1011

FAST_DET_MODE_EN([CCA_CTRL: B0 0x39(3)])=0b1

Wake-up timer operation range

[WUT_INTERVAL_H/L: B0 0x2F/0x30]

Wake-up timer

Continuous operation timer

RXON

TXON

RXON

SLEEP

RXON

SLEEP

RXON

SLEEP

LSI state

Wake-up operation

enable setting

By SLEEP

command go to

SLEEP state.

Carrier detected,

continue RXON

No carrier detected.

go to SLEEP state

○General purpose timer

ML7406 has general purpose timer. 2 channel of timer are able to function independently. Clock sources, timer setting can be

programmed independently. When timer is completed, General purpose timer 1 interrupt (INT[22] group3) or General purpose

timer 2 interrupt (INT[23] group3) will be generated.

General timer interval can be programmed as the following formula.

General purpose timer interval[s] = general purpose timer clock cycle *

Division setting ([GT_CLK_SET: B0 0x33]) *

General purpose timer interval setting ([GT1_TIMER: B0 0x34] or [GT2_TIMER: B0

0x35])

By setting GT2/1_CLK_SOURCE ([GT_SET: B0 0x32(5,1)]), clock sources for general purpose timer can be selectable from

wake-up timer clock or 2MHz.

51/230

FEDL7406-06

ML7406

●Frequency Setting Function

○Channel frequency setting

Maximum 256 channels can be selected (CH#0 to CH#255) by the following registers.

Frequency

CH#0 frequency

Register

[TXFREQ_I: B1 0x1B], [TXFREQ_FH: B1 0x1C], [TXFREQ_FM: B1 0x1D] and [TXFREQ_FL:

TX

RX

B1 0x1E]

[RXFREQ_I: B1 0x1F], [RXFREQ_FH: B1 0x20], [RXFREQ_FM: B1 0x21] and [RXFREQ_FL:

B1 0x22]

Channel space

Channel setting

-

[CH_SPACE_H: B1 0x23] and [CH_SPACE_L: B1 0x24]

[CH_SET: B0 0x09]

(1) Channel frequency setting overview

[Channel frequency setting]

Using above registers, channel frequency is defined as following formula.

Channel frequency = i) CH#0 frequency + ii) channel space * iii) channel setting

[Channel frequency allocation image]

iii) channel setting

(setting Nth channel)

ii) channel space setting

Channel No. 

0

1

2

3

···

n

··· 255

Frequency

i) CH#0 frequency setting

(Note)

The channel frequency to be selected must meet the following conditions. If the following conditions cannot be met,

please change channel #0 frequency or use other channels. If this formula cannot be met, expected frequency is not

functional or PLL may not be locked.

TX: (F_MCK1*n + 500kHz ) ≤ channel frequency ≤ (F_MCK1*(n+1) – 500kHz )

RX: (F_MCK1*n +2.2MHz ) ≤ channel frequency ≤ (F_MCK1*(n+1) )

F_MCK1: Master clock frequency

n = integer

Unusable Frequency

Usable Frequency

A

Frequency

(F_MCK1*n )

(F_MCK1*(n+1))

52/230

FEDL7406-06

ML7406

[Calculation example of above “A” range]

Condition: Master clock 26MHz, n=33

TX:(26*33+0.5)MHz ≤ channel frequency to be used ≤ (26*(33+1)-0.5)

→

858.5MHz ≤ channel frequency to be used ≤883.5MHz

RX:(26*33+2.2)MHz ≤ channel frequency to be used ≤ (26*(33+1)-2.2)

860.2MHz ≤ channel frequency to be used ≤881.8MHz

→

(Note)

“CH#0 frequency (Hz)” and “channle space (Hz)” may have error (Hz). Then the “channel frequency error (Hz)” is

defined as following formula.

Channel frequency error (Hz) = CH#0 frequency error (Hz) + channel space error (Hz)* channel setting

When changing “channel frequency” by setting “channel setting” without “CH#0 frequency” change, the “channel

frequency error” will become larger than by setting both “CH#0 frequency” and “channel setting”. If the “channle

frequency error” is larger than expection, please consider to change “CH#0 frequency”.

53/230

FEDL7406-06

ML7406

(2) Channel #0 frequency setting

TX frequency can be set by [TXFREQ_I: B1 0x1B], [TXFREQ_FH: B1 0x1C], [TXFREQ_FM: B1 0x1D] and

[TXFREQ_FL: B1 0x1E]. RX frequency can be set by [RXFREQ_I: B1 0x1F], [RXFREQ_FH: B1 0x20], [RXFREQ_FM:

B1 0x21] and [RXFREQ_FL: B1 0x22].

Channel #0 frequency setting value can be caluculated using the following formula.

f_rf

I 

(Integer part)

f_ref













f

rf

 I  2²⁰

(Integer part)

F 





f

ref

Here

f_rf

:channel #0 frequency

f_ref

:PLL reference frequency (=master clock frequency: F_MCK1)

I

F

:Integer part of frequency setting

:Fractional part of frequency setting

I

F

(Hex) is set to [TXFREQ_I: B1 0x1B], [RXFREQ_I: B1 0x1F] registers.

(Hex.) is set to the following registers.

For TX, from MSB, set in order of [TXFREQ_FH: B1 0x1C], [TXFREQ_FM: B1 0x1D], [TXFREQ_FL: B1 0x1E]

registers.

For RX, from MSB, set in order of [RXFREQ_FH: B1 0x20], [RXFREQ_FM: B1 0x21], [RXFREQ_FL: B1 0x22]

registers.

Frequency error ( f_err) is calculated as follows :

F

2²⁰











f_err I 

 f  f_rf



ref

[Example]

When set TX channel #0 frequency to 868MHz (master clock 26MHz), the calculations are as follows.

868MHz

I 

(Integer part) =33(0x21)

26MHz

868MHz

26MHz











 I 2²⁰

(Integer part)=403298(0x062762)

F 



[TXFREQ_I: B1 0x1B] = 0x21

[TXFREQ _FH: B1 0x1C] = 0x06

[TXFREQ _FM: B1 0x1D] = 0x27

[TXFREQ _FL: B1 0x1E] = 0x62

Frequency error f_erris as follows:

403298

2²⁰











f_err 33 

26MHz 868MHz  11.45Hz



(3) Channel space setting

Channel space can be set by [CH_SPACE_H: B1 0x23], [CH_SPACE_L: B1 0x24] registers. Hexadecimal values

calculated in the following formula should be set to [CH_SPACE_H: B1 0x23], [CH_SPACE_L: B1 0x24] registers.

(MSB->LSB order)

54/230

FEDL7406-06

ML7406

Channel space is from the center frequency of given channel to adjacent channel center frequency.

Channel space setting value can be calculated using the following formula:













f

sp

 2²⁰

(Integer part)

CH _ SPACE 





f

ref

Here

Channel space setting

CH _ SPACE :

f_sp: Channel space [Hz]

PLL reference frequency (=master clock frequency : F_MCK1)

f_ref

:

[Example]

When set channle space to 60kHz (master clock 26MHz), the calculation is as follows.

0.06MHz

26MHz













2²⁰

(Integer part) = 2419 (0x0973)

CH _ SPACE 

[CH_SPACE_H: B1 0x23] = 0x09

[CH_SPACE_L: B1 0x24] = 0x73

55/230

FEDL7406-06

ML7406

○IF frequency setting

In order to support various data rate , RX filters have to be optimised. The RX filter can be selected according to the IF

frequency. IF frequency can be set by using [IF_FREQ_H: B0 0x54] and [IF_FREQ_L: B0 0x55] registers. IF frequency

corresponds to each data rate must be selected as below.

Data rate

4.8kbps

500kHz

32.768kbps

500kHz

50kbps

500kHz

100kbps

720kHz

IF frequency

For other data rate, please refer to “Initialization table”.

If CCA is used to detect channel carrier power, required RX filter bandwidth may be different. [IF_FREQ_CCA_H: B1 0x56]

and [IF_FREQ_CCA_L: B1 0x57] registers must be used for CCA purpose. IF frequency must be set according to the IF

frequency.

IF frequency setting value can be calculated using the following formula:









( f / 2)

2²⁰

IF

(Integer part)

IF _ FREQ 





f_ref







Here

: IF frequency setting

IF _ FREQ

f_IF:IF frequency [Hz]

PLL reference frequency (=master clock frequency: F_MCK1)

f_ref

:

[Example]

When set IF frequency to 720kHz (master ckock 26MHz), the calculation is as follows.

IF_FREQ= {(0.72MHz / 2) / 26MHz} * 2²⁰(Integer part) = 14518 (0x38B6)

[IF_FREQ_H: B0 0x54] = 0x38

[IF_FREQ_L: B0 0x55] = 0xB6

○BPF frequency band setting

For normal operation (including AFC) and CCA operation, optimized BPF setting to [BPF_CO: B0 0x5C] and

[BPF_CO_CCA: B0 0x5D] registers are necessary. As indicated below table, proper value correspond to each data rate, must

be programmed.

Normal case

[BPF_CO: B0 0x5C]

CCA

Data rate

[kbps]

[BPF_CO_CCA: B0 0x5D]

[DRATE_SET: B0 0x06]

coefficient

1.44

Setting value

0xB8

coefficient

1.44

Setting value

0xB8

4.8

32.768

50

0b0010

0b1000

0b1010

0b1011

1.44

1

0xB8

0x80

1.44

1

0xB8

0x80

100

56/230

FEDL7406-06

ML7406

○Modulation setting

ML7406 supports GFSK modulation and FSK modulation.

(1) GFSK modulation setting

By setting GFSK_EN([DATA_SET1: B0 0x07(4)])=0b1, GFSK mode can be selected. In GFSK modulation, frequency

deviation can be set by [GFSK_DEV_H: B1 0x30] and [GFSK_DEV_L: B1 0x31] registers and Gasusiaan filter can be set

by [FSK_DEV0_H/GFIL0: B1 0x32] - [FSK_DEV3_H/GFIL6: B1 0x38] registers.

i) GFSK frequency deviation setting

F_DEV value can be calculated as the following formula:









f

_dev

2²⁰

(Integer part)

F _ DEV 







ref



Here

: Frequency deviation setting

F _ DEV

f_dev

f_ref

:

Frequency deviation [Hz]

PLL reference frequency (= master clock frequency: F_MCK1

)

[Example]

When set frequency deviation to 50kH (master clock 26MHz), the calculation is as follows.

F_DEV = {0.05MHz ÷ 26MHz} ×2²⁰(Integer value) = 2016 (0x07E0)

[GFSK_DEV_H: B1 0x30] = 0x07

[GFSK_DEV_L: B1 0x31] = 0xE0

ii) Gaussian filter setting

BT value of Gaussian filter and setting value to related registers are shown in the below table.

BT value

Register

0.5

1.0

[FSK_DEV0_H/GFIL0: B1 0x32]

[FSK_DEV0_L/GFIL1: B1 0x33]

[FSK_DEV1_H/GFIL2: B1 0x34]

[FSK_DEV1_L/GFIL3: B1 0x35]

[FSK_DEV2_H/GFIL4: B1 0x36]

[FSK_DEV2_L/GFIL5: B1 0x37]

[FSK_DEV3_H/GFIL6: B1 0x38]

0x49

0xA7

0x0F

0x14

0x19

0x1D

0x1E

0x00

0x10

0x04

0x0D

0x1E

0x32

0x3C

(Note)

GFSK filter coefficient setting register and FSK frequency deviation setting register are common. In GFSK mode, filter

coefficient applies to this register. In FSK mode, frequency deviation applies to this register.

57/230

FEDL7406-06

ML7406

(2) FSK modulation setting

By setting GFSK_EN([DATA_SET1: B0 0x07(4)])=0b0, FSK mode can be selected. Fine frequency deviation can be set

by [FSK_DEV0_H/GFIL0: B1 0x32] to [FSK_DEV4_L: B1 0x3B] registers. By adjusting [FSK_TIM_ADJ4-0: B1

0x3C-40] registers, FSK timing can be fine tuned.

V

IV

III

iv

i

i ii

iii

ii

iii iv

II

I

v

iv

i

iii ii

i ii

iv

iii

v

III

IV

V

1 output

0 output

TX_FSK_POL ([DATA_SET1:B0 0x07(6)]) = 0b0 setting

Frequency deviation setting

Timing setting

address

symbol

Register name

address

function

symbol

Register name

function

FSK_FDEV0_H/GFIL0

FSK_FDEV0_L/GFIL1

FSK_FDEV1_H/GFIL2

FSK_FDEV1_L/GFIL3

FSK_FDEV2_H/GFIL4

FSK_FDEV2_L/GFIL5

FSK_FDEV3_H/GFIL6

FSK_FDEV3_L

I

B1 0x32/33

i

FSK_TIM_ADJ4

FSK_TIM_ADJ3

FSK_TIM_ADJ2

FSK_TIM_ADJ1

FSK_TIM_ADJ0

B1 0x3C

B1 0x3D

B1 0x3E

B1 0x3F

B1 0x40

Modulation

timing

II

III

IV

V

B1 0x34/35

B1 0x36/37

B1 0x38/39

B1 0x3A/3B

ii

iii

iv

v

Frequency

deviation

4.3MHz/13MHz

counter value

(*1)

Resolution:

Approx.25Hz

FSK_FDEV4_H

FSK_FDEV4_L

(*1) Modulation timing resolution can be changed by FSK_CLK_SET ([FSK_CTRL: B1 0x2F(0)]).

(Note)

GFSK filter coefficient setting register and FSK frequency deviation setting register are common. In GFSK mode, filter

coefficient applies to this register. In FSK mode, frequency deviation applies to this register.

58/230

FEDL7406-06

ML7406

●RX related function

○AFC function

ML7406 supports AFC function. Frequency deviation (max±85ppm) between remote device and local device can be

compensated by this function. Using this function, stable RX sensitivity and interference blocking performance can be

achieved. This function can be enabled by setting AFC_EN([AFC/GC_CTRL: B1 0x15(7)])=0b1.

○Energy detection value (ED value) acquisition function

ML7406 supports calculating Energy detection value (ED value) based on Received signal strength indicator (RSSI).

ED value acquisition can be enabled by setting ED_CALC_EN ([ED_CTRL: B0 0x41(7)])=0b1 and as soon as trnasition to

RX_ON state, automatically start acquiring ED value. During RX_ON state, ED value constantly updated.

ED value is not RSSI value at given timing, but average values. Number of average times can be specified by ED_AVG[2:0]

([ED_CTRL: B0 0x41(2-0)]). During diversity operation, DIV_ED_AVG[2:0] ([2DIV_MODE: B1 0x48(2-0)]) is used for

setting. After acquiring specified average ED value, ED_DONE([ED_CTRL: B0 0x41(4)]) becomes ”0b1” and

ED_VALUE[7:0] ([ED_RSLT: B0 0x3A]) is updated.

ED_DONE bit will be cleared if one of the following conditions are met.

1. Gain is switched.

2. Once stopping ED value acquisition and then resume it.

3. Antenna is switched. (when diversity is enabled)

Timing from ED value starting point to ED value acquisition is calculated as below formula.

ED value average time = AD conversion time (16μs/17.8μs) * Number of average times.

(Note) AD conversion time can be set by ADC_CLK_SET([ADC_CLK_SET: B1 0x08(4)]). Reset value is 2MHz and AD

conversion time is 16μs.

The timing example is as follows:

[condition]

Set ADC_CLK_SEL([ADC_CLK_SEL: B1 0x08(4)])=0b1 (2MHz)

Set ED_AVG[2:0] ([ED_CTRL: B0 0x41(2-0)])=0b011 (8 times averaging)

ED value calculation

execution flag

(internal signal)

AD conversion (16μs/18.5μs)

RSSI value

(internal signal)

RSSI

10

RSSI RSSI

RSSI

6

RSSI

7

RSSI RSSI

RSSI

2

RSSI

3

RSSI

1

8

9

4

5

Compensation

and averaging

ED

1-8

ED

2-9

ED

3-10

ED_VALUE

[ED_RSLT: B0 0x3A]

INVALID

ED value averaging period (16μs*8=128μs)

Constantly update by

moving average

ED_DONE

([ED_CTRL:B0 0x41(4)])

59/230

FEDL7406-06

ML7406

○Diversity function

ML7406 supports two antenna diversity function.

While setting 2DIV_EN([2DIV_CTRL: B0 0x48(0)])=0b1, as soon as RX_ON is set, diversity mode will start. When

diversity mode is started, and upon RX data detection, each ED value will be acquired by switching two antennas. And then

antenna with higher ED value will be selected automatically. As diversity uses preamble data for ED value acquisition, longer

preamble length is desirable. If preamble is too short, accurate ED values may not be obtained.

The timing example is as below.

Sync

Word

RX packet

RX_ON

Preamble

Length

Data

INT[10] (Diversity search completion)

[INT_SOURCE_GRP2: B0 0x0E]

ANT_SW

ANT2: ED

value search

ANT1: ED

value search

Update ANT RSLT and ED values

[2DIV_RSLT: B0 0x49(1-0)])

[ANT1_ED:B0 0x4A]

Antenna

selection

ANT1/ANT2 search

is repeated

SEARCH_TIME1

([2DIV_SEARCH1:

B1 0x49(6-0)])

[ANT2_ED:B0 0x4B]

SEARCH_TIME2

([2DIV_SEARCH2:

B1 0x4A(6-0)])

ED values acquired by the diversity operation are stored in [ANT1_ED: B0 0x4A] and [ANT2_ED: B0 0x4B] registers and

antenna diversity result is indicated at 2DIV_RSLT[1:0] ([2DIV_RSLT: B0 0x49(1-0)]) when SyncWord is detected.

In diversity operation, the number of ED average times is specified by 2DIV_ED_AVG[2:0]([2DIV_MODE: B1 0x48(2:0)]).

Search time for each antenna is defined by [2DIV_SEARCH1:B1 0x49] and [2DIV_SEARCH2:B1 0x4A] registers. And its

time resolution is 16μs.

If diversity search completion interrupt (INT[10] group2) is cleared, ED values and antenna diversity result are cleared.

(Note)

When an incorrect diversity completion caused by errornous detection due to thermal noize, ML7406 resume antenna

diversity automatically. But when receiving a desired signal during the process of errounous detection, ED value obtained by

[ANT1_ED:B0 0x4A] or [ANT2_ED:B0 0x4B] may indicate a low value different from the actual input level.

If this event occures, the actual ED value of desired signal can be achibed by reading [ED_RSLT:B0 0x3A] registers after

SyncWord detection interrupt (INT[13] group2) generation.

60/230

FEDL7406-06

ML7406

(1) Antenna switching function

By using [2DIV_CTRL: B0 0x48], [ANT_CTRL: B0 0x4C], [SPI/EXT_PA_CTRL: B0 0x53] registers, TX-RX signal

selection (TRX_SW), antenna switching signal (ANT_SW), external PA control signal(DCNT) can be controlled.

ML7406 can support both SPDT and DPDT antena swith control. ANT_SW signal and TRX_SW signal output considion

for each antenna switch are explained below.

DPDT switch

Set 2PORT_SW([2DIV_CTRL: B0 0x48(1)])=0b1, ANT_CTRL1([2DIV_CTRL: B0 0x48(5)])=0b0. ANT_SW, TRX_SW

output condition of each Idle, TX, RX state are as follow. (default setting) If INV_TRX_SW([2DIV_CTRL: B0

0x48(2)])=0b1, polarity of ANT_SW and TRX_SW are reversed.

INV_TRX_SW=0b0

(default setting)

INV_TRX_SW=0b1

(reversed polarity)

TX/RX

state

Description

ANT_SW

TRX_SW

ANT_SW

TRX_SW

Idle

TX

H

L

H

L

H

L

Idle state

TX state

When Diversity disable or initial condition

when diversity enable is set ([2DIV_CTRL:

B0 0x48(0)]=0b1).

H

L

H

If diversity enable is set, during searching,

(ANT_SW=H, TRX_SW=L) and

(ANT_SW=L, TRX_SW=H) are switched

alternatively. After diversity completion, fix

to one of the condition.

RX

L/H

H/L

L/H

SPDT switch

Set 2PORT_SW([2DIV_CTRL: B0 0x48(1)])=0b0, ANT_CTRL1([2DIV_CTRL: B0 0x48(5)])=0b0. ANT_SW, TRX_SW

output condition of each Idle, TX, RX state are as follow. (default setting) If INV_TRX_SW([2DIV_CTRL: B0 0x48(2)])=0b1,

polarity of TRX_SW is reversed.

INV_TRX_SW=0b0

(default setting)

INV_TRX_SW=0b1

(polarity reverse)

TX/RX

condition

Description

ANT_SW

TRX_SW

ANT_SW

TRX_SW

Idle

TX

L

H

L

H

L

Idel state

TX state

When diversity disable or initial condition

when diversity enable is set ([2DIV_CTRL:

B0 0x48(0)]=0b1).

L

H

RX

If diversity enable is set,during searching

(TRX_SW=H) and (TRX_SW=L) is switched

alternatively. After diversity completion , fix

to one of the condition.

H/L

L

H/L

H

61/230

FEDL7406-06

ML7406

In the above setting, If INV_ANT_SW([2DIV_CTRL: B0 0x48(3)])=0b1, ANT_CTRL1([2DIV_CTRL: B0 0x48(5)])=0b1

are set, polarity of ANT_SW pin is reversed.

INV_ANT_SW=0b0

INV_ANT_SW=0b1

ANT_CTRL1=any

ANT_CTRL1=0b1

TX/RX state

Description

(default setting)

ANT_SW

TRX_SW

ANT_SW

TRX_SW

Idle

TX

RX

L

H

L

H

Idle state

TX state

When diversity disable or intial codition when

diversity enable is set ([2DIV_CTRL: B0

0x48(0)]=0b1).

If diversity enable is set, during searching

(ANT_SW=H) and (ANT_SW=L) is switched

alternatively. After diversity completion, fix

to one of the condition.

L

H

L

H/L

L/H

L

(2) Antenna switch forced setting

By [ANT_CTRL: B0 0x4C] register, ANT_SW pin output conditions can be set to fix.

TX: By TX_ANT_EN([ANT_CTRL: B0 0x4C(0)])=0b1, TX_ANT([ANT_CTRL: B0 0x4C(1)]) condition will be output.

RX: By RX_ANT_EN([ANT_CTRL: B0 0x4C(4)])=0b1, RX_ANT([ANT_CTRL: B0 0x4C(5)]) condition will be output.

However, output is defined by [GPIIO*_CTRL: B0 0x4E - 0x51] register , [GPIIO*_CTRL:B0 0x4E - 0x51] registers

setting has higer priority.

62/230

FEDL7406-06

ML7406

Antenna switching control signals can be also used as below.

Example 1) using one DPDT switch

Please set 2PORT_SW([2DIV_CTRL: B0 0x48(1)])=0b1.

LSI

DPDT#1

LNA_P pin

PA_OUT pin

TRX_SW output pin(GPIOx)

ANT_SW output pin (GPIOx)

(Note) altenate external PA control signal exists (GOIPn or EXT_CLK pin).

(Note) external circuits around LNA_P pin, PA_OUT pin and antenna switch (DPDT#1) are omitted in this example.

Example 2) using 2 SPDT switches

Please set 2PORT_SW([2DIV_CTRL: B0 0x48(1)])=0b0.

LSI

SPDT#1

SPDT#2

LNA_P pin

PA_OUT pin

TRX_SW output pin (GPIOx)

ANT_SW output pin (GPIOx)

(Note) altenate external PA control signal exsits. (GPIOx or EXT_CLK pin)

(Note) external circuits around LNA_P pin, PA_OUTpin and antenna switch(SPDT#2) are omitted in this example.

63/230

FEDL7406-06

ML7406

○CCA (Clear Channel Assessment) function

ML7406 supports CCA function. CCA function is to make a judment wheher the specified frequency channel is in-use or

available. Normal mode, continuous mode and IDLE detection mode are supported as following table.

[CCA mode setting]

[CCA_CTRL: B0 0x39]

Bit4 (CCA_EN)

Bit5 (CCA_CPU_EN)

Bit6 (CCA_IDLE_EN)

Normal mode

Continuous mode

IDLE detection mode

0b1

0b0

0b1

0b0

0b1

(1) Normal mode

Normal mode determines IDLE or BUSY. CCA (Normal mode) will be executed when RX_ON is issued while

CCA_EN(CCA_CTRL: B0 0x39(4)])=0b1, CCA_CPU_EN(CCA_CTRL: B0 0x39(5)])=0b0 and CCA_IDLE_EN

(CCA_CTRL: B0 0x39(6)])=0b0 are set.

Judgement of CCA is determined by average ED value in [ED_RSLT: B0 0x3A] register and CCA threshold value defined

by [CCA_LVL: B0 0x37] register. IF average ED value exceeds the CCA threshold value, it is considered as “BUSY”. And

CCA_RSLT[1:0]([CCA_CTRL: B0 0x39(1-0)]) =0b01 is set

If average ED value is smaller than CCA threshold value and maintains IDLE detection period which is defined by

IDLE_WAIT[9:0] of the [IDLE_WAIT_L: B0 0x3B], [IDLE_WAIT_H: B0 0x3C] registers. it is considered as “IDLE”.

And CCA_RSLT[1:0] =0b00 is set. For details operation of CCA_IDLE_WAIT[9:0], please refer to ”IDLE detection for

long time period”

If “BUSY” or “IDLE” state is detected, CCA completion interrupt (INT[18] group3) is generated, CCA_EN bit is cleared

to 0b0 automatically.

Upon clearing CCA completion interrupt, CCA_RSLT[1:0] are reset to 0b00. Therefore CCA_RSLT[1:0] should be read

before clearing CCA completion interrupt.

If an ED value exceeds the value defined by [CCA_IGNORE_LVL: B0 0x36] register, and as long as a given ED value is

included in the averaging target of ED value calculation, IDLE judgement is not performed. In this case if average ED value

exceeds CCA threshold value, it is considered as “BUSY” and CCA operation is terminated.

If average ED value is smaller than CCA threshold value, IDLE judgement is not determined. And CCA_RSLT[1:0]

indicates 0b11. CCA operation continues until “BUSY” is determined or the gievn ED value is out of averaging target and

“IDLE” is determined. For details operation of ED value execeeding [CCA_IGNORE_LVL: B0 0x36] register, please refer

to ”IDLE determination exclusion under strong signal input”.

Time from CCA command issue to CCA completion is in the formula below.

[IDLE detection]

CCA execution time = (ED value average times + IDLE_WAIT setting) * AD conversion time

[BUSY detection]

CCA execution time = ED value average times * AD conversion time

(Note)

1. Above formula does not consider IDLE judgement exclusion based on [CCA_IGNORE_LVL: B0 0x36] register.

For details, please refer to ”IDLE detection exclusion under strong signal input”.

2. AD conversion time can be slected by ADC_CLK_SEL([ADC_CLK_SET: B1 0x08(4)]).

ADC_CLK_SEL=0b0:17.7μs , 0b1:16μs(default)

64/230

FEDL7406-06

ML7406

The following is timing chart for normal mode.

[Condition]

ADC_CK_SEL([ADC_CLK_SET: B1 0x08(4)])=0b1 (2MHz)

ED_AVG[2:0] ([ED_CTRL: B0 0x41(2-0)])=0b011 (ED value 8 times average)

IDLE_WAIT[9:0] ([IDLE_WAIT_L/H: B0 0x3C/3B(1-0)])=0b00_0000_0000 (IDLE detection 0μs)

[IDLE detection case]

CCA_EN

[CCA_CTRL: B0 0x39(4)]

AD conversion(16μs)

*1

ED value average period (16μs*8=128μs)

ED value

(internal signal)

ED1

ED2

ED3

ED5

ED0

ED4

ED6

ED7

averaging

ED_VALUE[7:0]

[ED_RSLT: B0 0x3A]

ED

(0-7)

< CCA_LVL

B0 0x37

CCA_RSLT[1:0]

[CCA_CTRL: B0 0x39(1-0)]

0b00 (IDLE)

0b10 (CCA on-going)

INT[18] (CCA completion)

[INT_SOURCE_GRP3: B0 0x0F(2)]

IDLE_WAIT[9:0]

should be set, for

IDLE detection for

longer period.

CCA execution period(Min.128μs)

[BUSY result case]

CCA_EN

[CCA_CTRL: B0 0x39(4)]

AD conversion

(16μs)

*1

ED value average period (16μs*8=128μs)

ED1 ED2 ED3 ED5

ED4

ED value

(Internal signal)

ED0

ED6

ED7

averaging

ED_VALUE[7:0]

[ED_RSLT: B0 0x3A]

ED

(0-7)

> CCA_LVL

B0 0x37

CCA_RSLT[1:0]

[CCA_CTRL: B0 0x39(1-0)]

0b10 (CCA on-going)

0b01 (BUSY)

INT[18] (CCA completion)

[INT_SOURCE_GRP3: B0 0x0F(2)]

IDLE_WAIT[9:0]

should be set, for

IDLE detection for

longer period.

CCA execution period (Min.128μs)

(Note)

65/230

FEDL7406-06

ML7406

*1 During CCA operation, if set bandwidth to be extended (default is not extended), enabling filter stabilization time by

setting CCA_MASK_EN([CCA_MASK_SET: B2 0x7E(4)]) = 0b1. Stabilization time should be 1 ADC conversion time.

If this register is enabled, input operation is suspended until filter become stable.

(2) Continuous mode

Continuous mode continues CCA untill terminated by the host MCU. CCA continuous mode will be executed when

RX_ON is issued while CCA_EN(CCA_CTRL: B0 0x39(4)])=0b1, CCA_CPU_EN(CCA_CTRL: B0 0x39(5)])=0b1 and

CCA_IDLE_EN(CCA_CTRL: B0 0x39(6)])=0b0 are set.

Like normal mode, CCA judgement is determined by average ED value in [ED_RSLT: B0 0x3A] register and CCA

threshold defined by [CCA_LVL: B0 0x37] register. IF average ED value exceeds the CCA threshold value, it is considered

as “BUSY”. And CCA_RSLT[1:0]([CCA_CTRL: B0 0x39(1-0)]) = 0b01 is set.

If average ED value is smaller than CCA threshold value and maintains IDLE detection period which is defined by

IDLE_WAIT[9:0] of the [IDLE_WAIT_L: B0 0x3B], [IDLE_WAIT_H: B0 0x3C] registers, it is considered as “IDLE”.

And CCA_RSLT[1:0] =0b00 is set. For details operation of CCA_IDLE_WAIT[9:0], please refer to ”IDLE detection for

long time period”.

If an ED value exceeds the value defined by [CCA_IGNORE_LVL: B0 0x36] register, as long as a given ED value is

included in the averaging target of ED value calculation, IDLE judgement is not performed. In this case if average ED value

exceed CCA threshold level, it is considered as “BUSY” and CCA_RSLT[1:0] indicates 0b01. If average ED value is

smaller than CCA threshold level, IDLE judgement is not determined. And CCA_RSLT[1:0] indicates 0b11. For details

operation of ED value execeeding [CCA_IGNORE_LVL: B0 0x36] register, please refer to ”IDLE determination exclusion

under strong signal input”.

Continuous mode does not stop when “BUSY” or “IDLE” is detected. CCA operation continues until 0b1 is set to

CCA_STOP([CCA_CTRL: B0 0x39(7)]). Result is updated every time ED value is acquired. CCA completion interrup

(INT[18] group3) will not be generated.

66/230

FEDL7406-06

ML7406

The follwing is timing chart for continuous mode.

[Condition]

ADC_CK_SEL([ADC_CLK_SET: B1 0x08(4)])=0b1 (2MHz)

ED_AVG[2:0] ([ED_CTRL: B0 0x41(2-0)])=0b011 (ED value 8 times average)

IDLE_WAIT[9:0] ([IDLE_WAIT_L/H: B0 0x3C/3B(1-0)])=0b00_0000_0000 (IDLE detection period 0μs)

[BUSY to IDLE transition, terminated with CCA_STOP]

After CCA_STOP is issued,

CCA_CPU_EN, CCA_EN and

CCA_STOP are automatically

cleared.

CCA_CPU_EN/CCA_EN

[CCA_CTRL: B0 0x39(5-4)]

CCA_STOP

[CCA_CTRL]B0 0x39

AD conversion

(16μs)

ED value average period (128μs)

*1

ED value

(Internal signal)

●●●

ED0

ED7

ED8

ED28

ED50

averaging

ED

(1-8)

ED

(21-28)

ED

(43-50)

ED

(0-7)

●●●

ED_VALUE[7:0]

[ED_RSLT: B0 0x3A]

INVALID

> CCA_LVL

B0 0x37

<CCA_LVL

B0 0x37

CCA_RSLT[1:0]

[CCA_CTRL: B0 0x39(1-0)]

0b00 (IDLE)

0b10 (CCA on-going)

0b01 (BUSY)

IDLE_WAIT[9:0]

should be set, for

IDLE detection for

longer period.

INT[18] (CCA Completion)

[INT_SOURCE_GRP3: B0 0x0F(2)]

Interrupt not generated

ED_DONE

[ED_CTRL: B0 0x41(4)]

When 8 times ED value acquisition,

ED_DONE=0b1 (8 time averaging setting)

(Note)

*1 During CCA operation, if set bandwidth to be extended (default is not extended), enabling filter stabilization time by

setting CCA_MASK_EN([CCA_MASK_SET: B2 0x7E(4)]) = 0b1. Stabilization time should be 1 ADC conversion time.

If this register is enabled, input operation is suspended until filter become stable.

67/230

FEDL7406-06

ML7406

(3) IDLE detection mode

IDLE detection mode continues CCA until IDLE detection. IDLE detection CCA will be executed when RX_ON is issued

while CCA_EN(CCA_CTRL: B0 0x39(4)])=0b1, CCA_CPU_EN(CCA_CTRL: B0 0x39(5)])=0b0 and CCA_IDLE_EN

(CCA_CTRL: B0 0x39(6)])=0b1 are set.

Like normal mode, CCA judgement is determined by average ED value in [ED_RSLT: B0 0x3A] register and CCA

threshold defined by [CCA_LVL: B0 0x37] register. IF average ED value exceeds the CCA threshold value, it is considered

as “BUSY”. And CCA_RSLT[1:0]([CCA_CTRL: B0 0x39(1-0)]) =0b01 is set.

If average ED value is smaller than CCA threshold value and maintains IDLE detection period which is defined by

IDLE_WAIT[9:0] of the [IDLE_WAIT_L: B0 0x3B], [IDLE_WAIT_H: B0 0x3C] registers. it is considered as “IDLE”.

And CCA_RSLT[1:0] =0b00 is set. For details operation of CCA_IDLE_WAIT[9:0], please refer to ”IDLE detection for

longer period”.

In IDLE detection mode, only when IDLE is detected, CCA completion interrupt (INT[18] group3) is generated. After

IDLE detection, CCA_EN and CCA_IDLE_EN are reset to 0b0.

Upon clearing CCA completion interrupt, CCA_RSLT[1:0] are reset to 0b00. CCA_RSLT[1:0] should be read before

clearing CCA completion interrupt.

If an ED value exceeds the value defined by [CCA_IGNORE_LVL: B0 0x36] register, as long as a given ED value is

included in the averaging target of ED value calculation, IDLE judgement is not performed. In this case, if average ED

value is smaller than CCA threshold level, IDLE determination is not performed and CCA_RSLT[1:0] indicates 0b11. CCA

operation continues until given ED value is out of averaging target and “IDLE” is determined. For details of ED value

exceeding [CCA_IGNORE_LVL: B0 0x36] register, please refer to ”IDLE determination exclusion under strong signal

input”.

68/230

FEDL7406-06

ML7406

The follwing is timing chart for IDLE detection.

[Upon BUSY detection, continue CCA and IDLE detection case]

[Condition]

ADC_CK_SEL([ADC_CLK_SET: B1 0x08(4)])=0b1 (2MHz)

ED_AVG[2:0]([ED_CTRL: B0 0x41(2-0)])=0b011 (ED value 8 times average)

IDLE_WAIT[9:0] ([IDLE_WAIT_L/H: B0 0x3C/3B(1-0)])=0b00_0000_0000 (IDLE detection period 0μs)

After IDLE detection, CCA will be completed,

then CCA_EN, CCA_IDLE_EN are reset to

0b0 automatically..

CCA_IDLE_EN/CCA_EN

[CCA_CTRL: B0 0x39(6/4)]

AD conversion

(16μs)

ED value average period

*1

IDLE detection period

ED value

(internal signal)

●●●

ED0

ED7

ED8

ED28

ED27

ED29

averaging

ED

(20-27)

ED_VALUE[7:0]

[ED_RSLT: B0 0x3A]

ED

(22-29)

ED

(21-28)

ED

(0-7)

ED

(1-8)

●●●

INVALID

> CCA_LVL

B0 0x37

<CCA_LVL

B0 0x37

CCA_RSLT[1:0]

[CCA_CTRL: B0 0x39(1-0)]

0b00(IDLE)

0b10(CCA on-going)

0b01(BUSY)

BUSY INT. not generated

INT[18] (CCA completion)

[INT_SOURCE_GRP3: B0 0x0F(2)]

IDLE_WAIT[9:0]

should be set, for

IDLE detection for

longer period.

CCA execution period(Min.128μs+IDLE detection period)

(Note)

*1 During CCA operation, if set bandwidth to be extended (default is not extended), enabling filter stabilization time by

setting CCA_MASK_EN([CCA_MASK_SET: B2 0x7E(4)]) = 0b1. Stabilization time should be 1 ADC conversion time.

If this register is enabled, input operation is suspended until filter become stable.

69/230

FEDL7406-06

ML7406

(4) IDLE determination exclusion under strong signal input

If acquired ED value exceeds [CCA_IGNORE_LVL: B0 0x36] register, IDLE dertermination is not performed as lon as a

given ED value is included in the averaging target range. If average ED value including this strong ED value indicated in

[ED_RSLT: B0 0x39] register exceeds the CCA threshold value defined by [CCA_LVL: B0 0x37] register, it is considered

as ”BUSY”. And CCA_RSLT[1:0]([CCA_CTRL: B0 0x39(1-0)])=0b01 is set.

If average ED value is smaller than CCA threshold value, IDLE determination is not performed and CCA_RSLT[1:0]

indicates 0b11 ”CCA evaluation on-going (ED value excluding CCA judgement acquisition)”. CCA will continue until

“IDLE” or “BUSY” determination (in case of IDLE detection mode, IDLE is determined. In case of continuous mode,

CCA_STOP([CCA_CTRL: B0 0x39(7)]) is issued.)

(Note)

CCA completion interrupt (INT[18] group3) is generated only when “IDLE” or “BUSY” is determined. Therefore, if data

whose ED value exceeds CCA_IGNORE_LVL are input intermittently, neither “IDLE” or “BUSY” can be determined and

CCA may continues.

[ED value acquisition under extrem strong signal]

ED value >CCA_IGNORE_LVL

[CCA_IGNORE_LVL: B0 0x36]

ED value

(analog)

ED value

Averaging target includes ED

value exceeding

CCA_IGNORE_LVL. In this case

“IDLE” is not determined.

[Time 1]

[Time2]

[Time 3]

Shift register

(ED value 8 times

average)

However, if averaging value

exceeds CCA threshold, “BUSY”

is determined.

●

[Time 8]

[Time 9]

ED value, which includes CCA_IGNORE_LVL,

is out of averaging target. In this case, “IDLE”

can be determined.

70/230

FEDL7406-06

ML7406

The follwing is timing chart for CCA determination exclusion under strong signal.

[During IDLE_WAIT counting, detected extremly strong signal. After the given signal is out of averaging target, IDLE

detection case]

[Condition]

CCA normal mode

ADC_CK_SEL([ADC_CLK_SET: B1 0x08(4)])=0b1 (2MHz)

ED_AVG[2:0]([ED_CTRL: B0 0x41(2-0)])=0b011 (ED value 8 times average)

IDLE_WAIT[9:0]([IDLE_WAIT_L/H: B0 0x3C/3B(1-0)])=0b00_0000_0111(IDLE detection period 112μs)

ED VALUE>CCA_IGNORE_LVL

ED value <CCA_IGNORE_LVL

ED value<CCA_IGNORE_LVL

ED value

(internal signal)

●●●

ED13 ED14 ED15

●●●

ED7

ED8

ED21 ED22

ED29

Average ED value <CCA_LEVEL

(If average ED value >CCA_LVL, then BUSY detection.)

ED

(0-7)

ED

(1-8)

ED

(8-15)

ED

(22-29)

ED_VALUE[7:0]

[ED_RSLT: B0 0x3A]

●●●

INVALID

●●●

(6-13) (7-14)

(14-21) (15-22)

Resume counting due to the extreme

strong signal is out of averaging target.

ED value>CCA_IGNORE_LVL

detection and reset

CCA_PROG[9:0]

[CCA_PROG_L/H:B0 0x3E/3D]

●●●

0x007

0x006

0x000

0x001

CCA _RSLT maintains until

IDLE/BUSY detected.

Due to extreme strong signal detection,

CCA_RSLT is not indicating IDLE.

CCA_RSLT[1:0]

[CCA_CTRL: B0 0x39(1-0)]

0b10(on-going)

0b11(on-going)

0b00(IDLE)

INT[18] (CCA completion)

[INT_SOURCE_GRP3: B0 0x0F(2)]

CCA_RSLT[1:0]=0b11 do not generate interrupt

71/230

FEDL7406-06

ML7406

(5) IDLE detection for longer time period

When CCA IDLE detection is performed for longer time period, IDLE_WAIT[9:0]([IDLE_WAIT_L/H:B0 0x3C/3B(1-0)]

can be used. By setting IDLE_WAIT [9:0], averaging period longer than the period (for example, AD conversion16μs, 8

times average setting 128μs) can be possible.

This function can be used for IDLE determination – by counting times when average ED value becomes smaller than CCA

threshold defined by [CCA_LVL: B0 0x37] register. When counting exceed IDLE_WAIT [9:0], IDLE is determined. If

average ED value exceeds CCA threshold level, imemediately “Busy” is determined without wait for IDLE_WAIT [9:0]

period.

The following timing chart is IDLE detection setting IDLE_WAIT[9:0].

[ED value 8 timesv average IDLE detection case]

[Condition]

CCA normal mode

ADC_CK_SEL([ADC_CLK_SET: B0 0x08(4)])=0b1 (2MHz)

ED_AVG[2:0]([ED_CTRL: B0 0x41(2-0)])=0b011 (ED value 8 times average)

IDLE_WAIT[9:0]([IDLE_WAIT_L/H: B0 0x3C/3B(1-0)])=0b00_0000_0011 (IDLE detection period 48μs)

CCA_EN

[CCA_CTRL: B0 0x39(4)]

AD conversion

ED value averaging period

IDLE detection period

(16μs)

*1

(128μs)

(48μs)

ED value

(Internal signal)

●●●

ED0

ED1

ED2

ED7

ED8

ED9

ED10 ED11

averaging

ED

(0-7)

ED

(1-8)

ED

(2-9)

ED_VALUE[7:0]

[ED_RSLT: B0 0x3A]

ED

(3-10)

INVALID

< CCA_LVL

B0 0x37

IDLE_WAIT[9:0]

[IDLE_WAIT_L/H:B0 0x3C/3B]

0x000

0x001 0x002 0x003

CCA_RSLT[1:0]

[CCA_CTRL: B0 0x39(1-0)]

0b00(IDLE)

0b10 (detection on-going)

IDLE_WAIT start

INT[18] (CCA completion)

[INT_SOURCE_GRP3: B0 0x0F(2)]

CCA execution period(Min.128μs+48μs=176μs)

(average ED value < CCA_LVL)

continue for AD conversion period

3 times (48μs), then IDLE is

determined.

(Note)

*1 During CCA operation, if set bandwidth to be extended (default is not extended), enabling filter stabilization time by

setting CCA_MASK_EN([CCA_MASK_SET: B2 0x7E(4)]) = 0b1. Stabilization time should be 1 ADC conversion time.

If this register is enabled, input operation is suspended until filter become stable.

72/230

FEDL7406-06

ML7406

[ED value 1time IDLE detection case]

[Condition]

CCA normal mode

ADC_CK_SEL([ADC_CLK_SET: B1 0x08(4)])=0b1 (2MHz)

ED_AVG[2:0]([ED_CTRL: B0 0x41(2-0)])=0b000 (ED value 1 time average)

IDLE_WAIT[9:0]([IDLE_WAIT_L/H: B0 0x3C/3B(1-0)])=0b00_0000_1110 (IDLE detection period 224μs)

CCA_EN

[CCA_CTRL: B0 0x39(4)]

ED value average period (16μs)

AD conversion (16μs)

*1

IDLE detection period (224μs)

ED value

(Internal signal)

ED0

●●●

ED14

ED1

ED2

ED3

ED13

Do not average

ED_VALUE[7:0]

[ED_RSLT: B0 0x3A]

ED

(0)

ED

(1)

ED

(2)

ED

(12)

ED

(13)

ED

(14)

●●●

INVALID

If IDLE_WAIT=0x000,

IDLE detection here.

< CCA_TH

IDLE_WAIT[9:0]

[IDLE_WAIT_L/H;B0 0x3C/3B]

●●●

0x000

0x001 0x002

0x00E

0x00C 0x00D

CCA_RSLT[1:0]

[CCA_CTRL: B0 0x39(1-0)]

0b00(IDLE)

0b10(on-going)

INT[18] (CCA completion)

[INT_SOURCE_GRP3: B0 0x0F(2)]

CCA execution period(Min.16μs+224μs=240μs)

(average ED value < CCA_LVL)

continue for AD conversion

period 14 times (224μs) , then

IDLE is determined.

(Note)

*1 During CCA operation, if set bandwidth to be extended (default is not extended), enabling filter stabilization time by

setting CCA_MASK_EN([CCA_MASK_SET: B2 0x7E(4)]) = 0b1. Stabilization time should be 1 ADC conversion time.

If this register is enabled, input operation is suspended until filter become stable.

73/230

FEDL7406-06

ML7406

(6) CCA operation during diversity

CCA operation during diversity search

During diversity search, if CCA command is issued, diversity terminated and CCA starts.

Upon CCA starting, antenna is fixed to reset value(*1), maintaining until next diversity search. However, if

RX_ANT_EN([ANT_CTRL:B0 0x4C(4)])=0b1 is set, antenna is specified by RX_ANT([ANT_CTRL: B0 0x4C(5)]). After

CCA completion, diversity will be executed agaim.

*1 Please refer to the “Antenna switching function”. According to the default setting, ANT_SW and TRX_SW signals are

set.

If RX_ANT_EN=0b1, switch to the

antenna specified by RX_ANT.

If RX_ANT_EN=0b0. ANT1 is default

antenna.

After CCA completion, resume

diversity search.

ANT_SW

CCA_EN

[CCA_CTRL: B0 0x39(4)]

INT[18] (CCA completion)

[INT_SOURCE_GRP3: B0 0x0F(2)]

Searching diversity

Searching Diversity

CCA

(Note)

During CCA operation, RX operation is performed at the same time, even if CCA completion interrupt (INT[18] group3) is

not generated, SyncWord detection interrupt (INT[13] group2), RX FIFO access error interrupt (INT[12] group2), RX

length error interrupt (INT[11] group2), CRC error interrupt (INT[9] group2), RX completion interrupt (INT[8] group2) or

FIFO-Full interrupt (INT[5] group1) can be generated.

For details diversity function, please refer to the ”diversity function”.

74/230

FEDL7406-06

ML7406

During diversity , before RX_ON state, CCA is performed.

If diversity ON setting and CCA operation setting are enabled before RX_ON state, after RX_ON state transition, diversity

will not perform, but CCA will start. After CCA completion, diversity will be performed.

If RX_ANT_EN=0b1, switch to the

antenna specified by RX_ANT.

After CCA completion, perform

If RX_ANT_EN=0b0. ANT1 is default

diversity.

antenna.

RX_ON

ANT_SW

2DIV_DONE

[2DIV_RSLT: B0 0x49(7)]

CCA_EN

[CCA_CTRL: B0 0x39(4)]

INT[18] (CCA completion)

[INT_SOURCE_GRP3: B0 0x0F(2)]

Diversity search

CCA

75/230

FEDL7406-06

ML7406

(7) CCA threshold setting

CCA threshold value defined by [CCA_LVL: B0 0x37] register, should be considered desired input leve (ED value),

components variation, temperature fluctuation, and loss at antenna matching circuits. Input level and ED value are described

in the following formula.

ED value = 255 / 70 * (107 + input level[dBm])

However, if BPF setting modified and CCA is executed, ED value become bigger than normal case. CCA threshold can be

set as below , taking this compensation and variations into account.

CCA threshold = 255 / 70 * (107 + input level[dBm] - variations – other losses) + CCA compensation

Item

Variation (individual, temp.)

Other loss

Value

6dB

Antenna, matchich circuits loss

CCA compensation

12@100kbps, 15@200kbps, 0@other rate

Example) When input level threshold is set to -75dBm

conditions:other losses 1dB, 100kbps

CCA threshold = 255 / 70 * (107 - 75 - 6 - 1) + 12

≈ 103

= 0x67

In order to validate whether CCA threshold is optimised or not, CCA should be executed and confirmimg level changing

from IDLE to BUSY, every time input level is changed,

76/230

FEDL7406-06

ML7406

●Other Functions

○Data rate setting function

(1) Data rate change setting

ML7406 supports various TX/RX data rate setting defined by the following registers.

TX: [TX_RATE_H: B1 0x02] and [TX_RATE_L: B1 0x03] registers

RX: [RX_RATE1_H: B1 0x04], [RX_RATE1_L: B1 0x05] and [RX_RATE2: B1 0x06] registers

TX/RX data rate can be defined in the following formula.

[TX]

TX data rate [bps] = round (26MHz / 13/ TX_RATE[11:0])

Recommended values for each data rate are in the table below. Registers value below are automatically set to

[TX_RATE_H],[ TX_RATE_L] registers by setting TX_DRATE[3:0] ([DRATE_SET: B0 0x06(3-0)]).

[TX_RATE_H][ TX_RATE_L]

Data rate deviation

TX data rate [kbps]

register setting value

[%] *1

-0.02

0.04

-0.08

0.16

0.06

0.00

3.17

0.00

1.2

2.4

4.8

9.6

32.768

50

100

200

300

400

500

1667d

833d

417d

208d

61d

40d

20d

10d

7d

5d

4d

*1 Data rate deviation is assumption that frequency deviation of master clock(26MHz crystal oscillator or TCXO) is 0ppm.

[RX]

RX data rate [bps] = round (26MHz / {RX_RATE1[11:0] ×[RX_RATE2[6:0]})

Recommended values for each data rate are in the table below. Registers value below are automatically set to

[RX_RATE1_H][ RX_RATE1_L] [RX_RATE2] registers by setting RX_DRATE[3:0]( [DRATE_SET:B0 0x06(7-4)] ).

[RX_RATE1_H][RX_RATE1_L]

[RX_RATE2]

register setting

RX dta rate [kbps]

register setting value

1.2

2.4

4.8

9.6

32.768

50

100

200

300

400

500

169d

85d

42d

21d

11d

8d

4d

5d

3d

2d

0d

72d

65d

26d

29d

32d

26d

2d

(Note)

When LOW_RATE_EN([CLK_SET2:B0 0x03(0)])=0b1, [RX_RATE1_H/L] and [RX_RATE2] registers are not set

automatically by setting RX_DRATE[3:0]. Please calcurate appropriate values by replacing the 8.66MHz to 26MHz in the

above formula and set them to each register.

77/230

FEDL7406-06

ML7406

(2) Other register setting associate with data rate change

Data rate can be cahnged by RX_DRATE[3:0] ([DRATE_SET(7-4)]) and TX_DRATE[3:0] ([DRATE_SET(3-0)]), below

registers may have to be changed.

(Note)

1. Depending on data rate, the following chage may not be necessary. For details, please refer to each register description.

2. Please change data rate setting in TRX_OFF state.

3. After change of data rate setting, please execute RST1 [RST_SET: B0 0x01(1)] (MODEM Reset).

Registers

Parameters

Name

Address

B0 0x06

B1 0x23

B1 0x24

B1 0x30

B1 0x31

B1 0x32

B1 0x33

B1 0x34

B1 0x35

B1 0x36

B1 0x37

B1 0x38

B1 0x39

B1 0x3A

B1 0x3B

B1 0x3C

B1 0x3D

B1 0x3E

B1 0x3F

B1 0x40

B0 0x54

B0 0x55

B0 0x56

B0 0x57

B0 0x5C

B0 0x5D

B0 0x5E

B0 0x5F

B0 0x60

B0 0x61

B1 0x57

B1 0x58

B1 0x59

B1 0x5A

B1 0x5B

B1 0x5C

B1 0x5D

B1 0x5E

B1 0x5F

Data rate

DRATE_SET

CH_SPACE_H

CH_SPACE_L

GFSK_DEV_H

GFSK_DEV_L

FSK_DEV0_H/GFIL0

FSK_DEV0_L/GFIL1

FSK_DEV1_H/GFIL2

FSK_DEV1_L/GFIL3

FSK_DEV2_H/GFIL4

FSK_DEV2_L/GFIL5

FSK_DEV3_H/GFIL6

FSK_DEV3_L

Channel space

Frequency deviation(GFSK)

Frequencydeviation (FSK)

FSK_DEV4_H

FSK_DEV4_L

FSK_TIM_ADJ4

FSK_TIM_ADJ3

FSK_TIM_ADJ2

FSK_TIM_ADJ1

FSK_TIM_ADJ0

IF_FREQ_H

Frequency deviation time(FSK)

IF frequency

IF_FREQ_L

IF_FREQ_CCA_H

IF_FREQ_CCA_L

BPF_CO

BPF_CO_CCA

IFF_ADJ_H

If frequency during CCA

BPF coefficient

BPF coefficient during CCA

Demodulator DC level adjustment

IFF_ADJ_L

IFF_ADJ_CCA_H

IFF_ADJ_CCA_L

DEMOD_SET1

DEMOD_SET2

DEMOD_SET3

DEMOD_SET4

DEMOD_SET5

DEMOD_SET6

DEMOD_SET7

DEMOD_SET8

DEMOD_SET9

Demodulator DC level adjustment

during CCA

Demodulator adjustment1

Demodulator adjustment2

Demodulator adjustment3

Demodulator adjustment4

Demodulator adjustment5

Demodulator adjustment6

Demodulator adjustment7

Demodulator adjustment8

Demodulator adjustment9

78/230

FEDL7406-06

ML7406

○Interrupt generation function

ML7406 support interrupt generation function. When interrupt occurs, interrupt notification signal (SINTN) become “L” to

notify interrupt to the host MCU. Interrupt elements are divided into the 3 groups, [INT_SOURCE_GRP1: B0 0x0D],

[INT_SOURCE_GRP2: B0 0x0E] and [INT_SOURCE_GRP3: B0 0x0F]. Each interrupt element can be maskalable using

[INT_EN_GRP1: B0 0x10]. [INT_EN_GRP2: B0 0x11] and [INT_EN_GRP3: B0 0x12] registers. Interrupt notification signal

(SINTN) can be output from GPIO* or EXT_CLK. For output setting, please refer to [GPIO1_CTRL: B0 0x4E],

[GPIO1_CTRL: B0 0x4F], [GPIO2_CTRL: B0 0x50], [GPIO3_CTRL: B0 0x51] and [EXTCLK_CTRL: B0 0x52] registers.

(Note)

If one of the unmask interrupt event occurs, SINTN maintains Low.

(1) Interrupt events table

Each interrupt event is described below table.

Register

Interrupt name

INT[0]

Description

Clock stabilizaion completion interrupt

VCO calibration completion interrupt/

FUSE access completion interrupt

PLL unlock interrupt

INT[1]

INT[2]

INT[3]

INT[4]

RF state transition completion interrupt

FIFO-Empty interrupt

INT_SOURCE_GRP1

INT[5]

FIFO-Full interrupt

INT[6]

INT[7]

INT[8]

Wake-up timer completion interrupt

Clock calibration completion interrupt

RX completion interrupt

INT[9]

CRC error interrupt

INT[10]

INT[11]

INT[12]

INT[13]

INT[14]

INT[15]

INT[16]

INT[17]

INT[18]

INT[19]

INT[20]

INT[21]

INT[22]

INT[23]

Diversity search completion interrupt

RX Length error interrupt

RX FIFO access error interrupt

SyncWord detection interrupt

Field checking interrupt

Sync error interrupt

TX completion interrupt

TX Data request accept completion interrupt

CCA completion interrupt

TX Length error interrupt

TX FIFO access error interrupt

Reserved

General purpose timer 1 interrupt

General purpose timer 2 interrupt

INT_SOURCE_GRP2

INT_SOURCE_GRP3

79/230

FEDL7406-06

ML7406

(2) Interrupt generation timing

In each interrupt generation, timing from reference point to interrupt generation (notification) are described in the following

table. Timeout procedure for interrupt notification waiting are also described below.

(Note)

(1)The values are described in units of “bit cycle” in the below table is the value at 100kbps. If using other data rate, please

esitimate with appropriate “bit cycle”.

(2)Below table uses the following format for TX/RX data.

10 byte

Preamble

2 byte

SyncWord

1 byte

Length

24 byte

User data

2byte

CRC

(3)Even if each interrupt notification is masked, in case of interrupt occurence, interrupt elements are stored internally.

Therefore, as soon as interrupt notification is unmasked, interrupt will generate.

Timing from reference point to interrupt generation

Interrupt notice

Reference point

or interrupt generation timing

INT[0]

INT[1]

CLK stabilization

completion

RESETN release

(upon power-up)

SLEEP release

(recovered from

SLEEP)

50μs

VCO calibration

completion

VCO calibration start

0.6ms to 3.9ms

FUSE access completion RESETN release

48μs

INT[2]

INT[3]

PLL unlock detection

-

(TX) during TX after PA enable.

(RX) during RX after RX enable.

(IDLE) 210μs

(RX) 192μs

(IDLE) 119μs

RF state transition

completion

TX_ON command

RX_ON command

(TX) 244μs

TRX_OFF

command

Force_TRX_OFF

command

(TX)

TX_ON command

(*1)

(RX) -

(TX) -

(RX)

SyncWord detection

SLEEP setting

(TX) 147μs

(RX) 4μs

(TX) 147μs

(RX) 4μs

INT[4]

INT[5]

FIFO-Empty detection

FIFO-Full detection

NRZ coding, Empty trigger level is set to 0x02.

RFwake-up(210μs)+35byte(preamble to 22^ndData byte) * 8bit

* 10(bit cycle) =3010μs

By FIFO read, remaining FIFO data is under trigger level

By FIFO write, FIFO usage exceed trigger level

NRZ coding, Full trigger level is set to 0x05.

6byte (Length to 5^thData byte) * 8bit *10μs(bit cycle) = 480μs

Wake-up timer is completed.

For details, please refer to “wake-up timer”

Calibration timer is completed.

For details, please refer to “low speed clock shift detection

function”.

INT[6]

INT[7]

Wake-up timer

completion

Clock calibration

completion

Calibration start

INT[8]

INT[9]

RX completion

SyncWord detection NRZ coding

27byte (Length to CRC) * 8bite *10(bit cycle)=2160μs

SyncWord detection (Format A/B) each RX CRC block calculation completion

(Format C) RX completion

CRC error detection

INT[10]

INT[11]

INT[12]

Diversity search

completion

RX Length error

detection

RX FIFO access error

detection

-

SyncWord detection during diversity enable setting

SyncWord detection 80μs (L-field 1byte)

160μs (L-field 2byte)

-

(1)overflow occurs because FIFO read is too slow.

(2)underflow occurs because too many FIFO data is read

INT[13]

INT[14]

SyncWord detection

Field check completion

-

SyncWord detection

Match or mismatch detected in Field check

(*1) Before issuing TX_ON, writing full-length TX data to the TX_FIFO.

80/230

FEDL7406-06

ML7406

Timing From reference point to interrupt generation

Interrupt notice

Reference point

or interrupt generation timing

During RX after SyncWord detection, out-of-sync detected.

(When RXDIO_CTRL[1:0] ([DIO_SET: B0 0x0C(7-6)]) =0b00 or

0b11.)

INT[15]

Sync error detection

-

INT[16]

INT[17]

INT[18]

TX completion

TX_ON command

(*1)

RF wake-up+[TX data+3](bit)

=210μs+(39byte * 8 +3) bit * 10μs (bit cycle)=3360μs after

TX Data request accept

completion

CCA completion

-

After full length data are written to the TX_FIFO.

CCA execution start (1)Normal mode

(ED value calculation averaging times +IDLE_WAIT setting

[IDLE_WAIT_H/L:B0 0x3B,3C]) * AD conversion time

(2) IDLE detection mode

○IDLE judgment case

(ED value calculation averaging times +IDLE_WAIT setting

[IDLE_WAIT_H/L:B0 0x3B,3C]) * AD conversion time

○BUSY judgment case

(ED value calculation averaging times) *AD conversion time

AD conversion time period can be changed by AD clock

frequency ([ADC_CLK_SEL:B1 0x08]) . AD clock frequency =

1.88MHz: 17.7μs, 2.0MHz: 16μs. For details, please refer to the

“CCA (Clear Channel Assessment) function”.

After set length value to [TX_PKT_LEN_H/L: B0 0x7A/7B]

registers

INT[19]

INT[20]

TX Length error

detection

TX FIFO access error

detection

-

(1) When the next packet data is writren to the TX_FIFO before

transmitting previous packet data.

(2) FIFO overflow when writing

(3) FIFO underflow (no data) when transmitting

-

INT[21]

INT[22]

Reserved

General purpose timer 1

completion

-

General purpose timer 1 completion

Timer start

General purpose timer clock cycle * Division setting

[GT_CLK_SET: B0 0x33] * general purpose timer interval

setting [GT1_TIMER:B0 0x34]

For details, please refer to the “General purpose timer”.

General purpose timer 2 completion

INT[23]

General purpose timer 2

completion

Timer start

General purpose timer clock cycle * Division setting

[GT_CLK_SET: B0 0x33] * general purpose timer interval

setting [GT2_TIMER:B0 0x35]

For details, please refer to the “General purpose timer”.

(*1) Before issuing TX_ON, writing full-length TX data to the TX_FIFO.

81/230

FEDL7406-06

ML7406

(3) Clearing interrupt conditions

The following table shows the condition of clearing each intereupt. As a procedure to clear the interrup, it is recommended

that the interrupt to be cleared after masking the interrupt.

Interrupt notification

CLK stabilization completion

VCO calibration completion

/FUSE access completion

PLL unlock

Conditions for clearing interrupts

After interrupt generated

INT[0]

INT[1]

INT[2]

INT[3]

INT[4]

After interrupt generated

RF state transition completion

FIFO-Empty

(must clear before next FIFO-Empty trigger timing)

INT[5]

FIFO-Full

After interrupt generated

(must clear before next FIFO-Full trigger timing)

After interrupt generated

INT[6]

INT[7]

INT[8]

INT[9]

Wake-up timer completion

Clock calibration completion

RX completion

CRC error

INT[10] Diversity search completion

After RX completion interrupt (INT[8]), must clear

together with RX completion interrupt.

(Note) During data reception, clearing is prohibited.

After interrupt generated

INT[11] RX Length error

INT[12] RX FIFO access error

INT[13] SyncWord detection

INT[14] Field checking

INT[15] Sync error

After interrupt generated

INT[16/] TX completion

After interrupt generated

INT[17] TX Data request accept completion After interrupt generated

INT[18] CCA completion

After interrupt generated

(Note) clearing interrupt erase CCA result as well.

INT[19] TX Length error

After interrupt generated

INT[20] TX FIFO access error

INT[21] Reserved

After interrupt generated

INT[22] General purpose timer 1

INT[23] General purpose timer 2

After interrupt generated

82/230

FEDL7406-06

ML7406

○Temperature measurement function

ML7406 has temperature measurement function. This temperature information can be from A_MON pin (pin#23) as analog

output or digital information using [TEMP: B1 0x09] register. Analog or digital can be switched by [MON_CTRL: B0 0x4D]

register.

(Note)

 Please do not set TEMP_OUT([MON_CTRL: B0 0x4D(4)]) and TEMP_ADC_OUT([MON_CTRL: B0 0x4D(5)]) at the

same time. Correct value reading may not be guaranteed.

 If TEMP_ADC_OUT=0b1, ML7406 can not normally receive a received signal. When receiving, please set

TEMP_ADC_OUT to 0b0.

[Analog output]

ML7406 has current source circuits and its current flow through 75kΩ connected to A_MONpin (pin#23). From voltage

information, temperature information can be obtained.

Current from current source circuits are 10μA at 25˚C. The following formula can be used to calculate temperature from the

current.

Itemp = (273+ Temp) / (273+25) * 10 (μA)

Therefore, if 75kΩ resister is connected, temperature can be calculated using the following formula.

Vamon = (273+ Temp) / (275+25) * 10E-6 * 75000

If temperature is -40˚C to 85˚C, Vamon will be 0.59V to 0.9V.

The following formula can be used to calculate temperature from voltage .

Temp = Vamon * 397.3 - 273

[Digital output]

Digital temperature information is using 6bits ADC to convert from the above analog information. Internally, 4samples

information are added and indicates as 8bits information in [TEMP: B1 0x09] register. Ignoring low 2 bits, upper 6 bits are

used for average temperature information.

Temperature information is updated every 16μs. (If 1.73MHz is selected in [ADC_CLK_SET: B1 0x08] register., it is

updated every 18.5μs.

83/230

FEDL7406-06

ML7406

○Low speed clock shift detection function

ML7406 has low speed shift detection function to compensate inaccurate clock generated by RC oscillator (external clock or

internal RC oscillation circuits). By detecting frequency shift of the wake up timer, host can set wake-up timer parameters

which taking frequency shift into consideration. More accurate timer operation is possible by adjusting wake-up timer interval

setting ([WUT_INTERVAL_H/L: B0 0x2F/0x30]) or continuous operation timer interval ([WU_DURATION: B0 0x31]).

Setting

Register

Frequency shift detection clock frequency setting

Clock calibration time

[CLK_CAL_SET: B0 0x70]

[CLK_CAL_TIME: B0 0x71]

Clock calibration result value

[CLK_CAL_H: B0 0x72], [CLK_CAL_L: B0 0x73]

This function is to measure low speed wake-up timer cycle by using accurate high speed internal clock and count result will

be stored in [CLK_CAL_H/L: B0 0x72/0x73] registers. Above setting and count numbers are as follows:

High speed clock counter = {Wakeup timer clock cycle[SLEEP/WU_SET:B0 0x2D(2)] *

Clcok calibration time setting ([CLK_CAL_TIME:B0 0x71(5-0)]) /

{master clock cycle (26MHz) / clock division setting value ([CLK_CAL_SET: B0

0x70(7-4)])}

Clock calibration time is as follows:

Clock calibration time[s] = Wakeup timer clock cycle * Clock calibration time setting

[Example]

Assuming no division in the internal high speed clock, calibration time is set as 10 cycle. Set 1,000 to Wake-up interval

timer:

condition: wake-up timer clock frequency = 32.768kHz

detection clock division setting CLK_CAL_DIV[3:0][CLK_CAL_SET: B0 0x70(7-4)] = 0b0000

clock calibration time setting [CLK_CAL_TIME] = 0x0A

wake-up timer interval [WUT_INTERVAL_H/L:B0 0x2F,30] = 0x03E8

Theorical high speed clock count = (1/32.768kHz) * 10 / (1/26MHz)

= 7934(0x1EFE)

If getting [CLK_CAL_H/L:B0 0x72,73] = 0x1E17 (7703)

Counter difference = 7703 - 7934 = -231

Frequency shift = 1/[{1/32.768kHz + (-231) / 10 * 1/26MHz } - 1/32.768kHz] = 0.983 kHz

Then finding wake-up timer clock frequency accuracy is +3% higher. And the compensation vale (C) is calcurared as

below:

C= Wake-up timer interval([WUT_INTERVAL_H/L:B0 0x2F,30]) * frequecy shift / 32.768

= 1000 * 0.983kHz / 32.768kHz

=30

Therefore, setting [WUT_INTERVAL_H/L:B0 0x2F,30] = 1000 +30 = 1030 = 0x0406 to achive more accurate inteval

timinig.

(Note)

If calibration time is too short or if high speed counter is divided into low speed clock, calibration may not be accurate.

84/230

FEDL7406-06

ML7406

■LSI adjustment items and adjustment method

●PA adjustment

ML7406 has output circuits for 1mW and 20mW (10mW as well).

Output circuits can be selected by PA_MODE[1:0] ([PA_MODE: B0 0x67(5-4)]).

PA_MODE[1:0]

0b00

Output circuit

1mW

0b01

10mW

0b10

20mW

0b11

Not allowed

Output power can be adjusted by the following 3 registers.

Coarse adjustment 1

Coarse adjustment 2

Fine adjustment

PA_REG[3:0] ([PA_MODE: B0 0x67(3-0)]) 16 resolutions

PA_ADJ[3:0] ([PA_ADJ: B0 0x69(3-0)]) 16 resolutions

PA_REG_FINE_ADJ[4:0] ([PA_REG_FINE_ADJ: B0 0x68(4-0)]) 32 resolutions

Coarse adjustment 1: PA regulator voltage adjustment

Setting regulator voltage according to the desired output level.

However, please set PA regulator voltage to less than [VDD_PA(pin#22) – 0.3V].

PA_REG[3:0]

[PA_MODE:B0 0x67]

0b0000

PA regulator

voltage[V]

1.20

1.32

1.44

1.56

1.68

1.80

1.92

2.04

2.16

2.28

2.40

2.52

2.64

2.76

2.88

3.00

0b0001

0b0010

0b0011

0b0100

0b0101

0b0110

0b0111

0b1000

0b1001

0b1010

0b1011

0b1100

0b1101

0b1110

0b1111

Coarse adjustment 2: PA output gain adjustment

Controlling output power by adjusting PA gain. Adjustment steps are 0.4dB to 1.5dB.

[PA_ADJ: B0 0x69]=0x0F: output PA gain maximum.

[PA_ADJ: B0 0x69]=0x00: output gain minimum.

Fine adjustment: PA regulator voltage fine adjustment

Fine tuning output power by adjusting PA regulator voltage. Adjustment step is less than 0.2dB.

[PA_REG_FINE_ADJ B0 0x68]=0x1F: maximum

[PA_REG_FINE_ADJ B0 0x68]=0x00: minimum

(Note)

In order to achieve the most optimized result, Matching circuits may vary depending on the output mode.

85/230

FEDL7406-06

ML7406

○PA output adjustment flow

START

Coarse adjustment 1: PA_MODE setting and PA

regulator adjustment [PA_MODE: B0 0x67]

Coarse adjustment 2: PA output gain adjustment

PA output gain adjustment [PA_ADJ: B0 0x69]

Fine adjustment: PA regulator fine adjustment

[PA_REG_FINE_ADJ: B0 0x68]

END

86/230

FEDL7406-06

ML7406

●I/Q adjustment

Image rejection ratio can be adjusted by tuning IQ signal balance. The adjustment procedure is as follows:

1. From SG, image frequency signal is input to ANT pin (#24).

Input signal:

Input frequency: channel frequency - (2 * IF frequency)

In case of 100kbps, IF frequency = 720kHz: please refer to the “IF frequency setting”.

-70dBm

no modulation.wave

Input level:

2. Issuing RX_ON by [RF_STATUS:B0 0x7B] register, by adjusting [IQ_MAG_ADJ: B0 0x6C] and

[IQ_PHASE_ADJ: B0 0x6D] registers, Finding setting value so that ED value [ED_RSLT: B0 0x3A] is minimum.

○I/Q adjustment flow

START

Power on

1

Initialize setting

* please refer to “Initialization table”

Amplitude setting

[IQ_MAG_ADJ: B0 0x6C]

Init. value 0x08 setting

SG output setting

modulation: no modulation

level : -70dBm

frequency: CH frequency- 2* IF frequency

Phase adjustment by

[IQ_PHASE_ADJ: B0 0x6D]

so that ED value is minimum.

Phase value setting

[IQ_PHASE_ADJ: B0 0x6D]

RX_ON issue

[RF_STATUS: B0 0x0B]

Amplitude adjustment by

[IQ_MAG_ADJ: B0 0x6C]

so that ED value is minimum.

1

Amplitude setting

[IQ_MAG_ADJ: B0 0x6C]

Amplitude/phase re-adjustment

by changing range.

[IQ_MAG_ADJ] ±3LSB

[IQ_PHASE_ADJ] ±6LSB

so that ED value is minimum.

Amplitude, phase

confirm

END

87/230

FEDL7406-06

ML7406

●VCO adjustment

In order to compensate VCO operation margin, optimized capacitance compensation value should be set in each TX/RX

operation and frequency. This capacitance compensation value can be acquired by VCO calibration.

By performing VCO calibration when power-up or reset, acquired capacitance compensation values for upper limit and

lower limit of operation frequency range (for both TX/RX), based on this value optimised capacitance value is applied

during TX/RX operation.

○VCO adjustment flow

The following flow is the procedure for acquiring capacitance compensation value when power-up or reset.

START

Setting low limit frequency

[VCO_CAL_MIN_I: B1 0x4D]

Initialize

[VCO_CAL_MIN_FH: B1 0x4E]

setting

[VCO_CAL_MIN_FM: B1 0x4F]

[VCO_CAL_MIN_FL: B1 0x50]

Setting operation frequency range

[VCO_CAL_MAX_N: B1 0x51]

VCO calibration completion INT. clear

INT[1] ([INT_SOURCE_GRP1: B0 0x0D])

Set VCO_CAL_START = 0b1

Start

[VCO_CAL_START: B0 0x6F(0)]

calibration

No

Calibration operation

Completion wait

VCO calibration completion INT?

INT[1] [INT_SOURCE_GRP1: B0 0x0D]

Yes

END

(Note)

VCO calibration should be performed only during IDLE state .

88/230

FEDL7406-06

ML7406

VCO calibration is necessary every 0.6ms to 3.9ms.

After completion, capacitance compensation values are stored in the following registers.

Capacitance compensation value at low limit frequency: [VCAL_MIN: B1 0x52]

Capacitance compensation value at upper limit frequency: [VCAL_MAX: B1 0x53]

In actual operation, based on the 2 compensation values, the most optimized capacitance value for the frequency is

calculated and applied. The calculated value is stored in [VCO_CAL: B0 0x6E] register.

By evaluation stage, if below values are stored in the MCU memory and uses these values upon reset or power-up,

calibration operation can be omitted.

Registers to be saved in the MCU memory.

[VCO_CAL_MIN_I: B1 0x4D]

[VCO_CAL_MIN_FH: B1 0x4E]

[VCO_CAL_MIN_FM: B1 0x4F]

[VCO_CAL_MIN_FL: B1 0x50]

[VCO_CAL_MAX_N: B1 0x51]

[VCAL_MIN: B1 0x52]

[VCAL_MAX: B1 0x53]

(Note)

1. For low limit frequency, please use frequency at least 2.2MHz lower than operation frequency.

2. Upper limit frequency should be selected so that operation frequency is in the frequency range.

3. In case of like a channel change, if the setting frequency is outside of calibration frequency range, calibration has to be

performed again with proper frequency.

4. If PLL unlock occures, PLL unlock interrupt (INT[02] group1) will geneate. The following shows the ML7406

opereation related with LSI state and PLL_LD_EN([PLL_LOCK_DETECT:B1 0x0B(7)]) setting, after interrupt

generation.

PLL lock detection control setting and ML7406 operation after interrupt generation

LSI

state

check timig of

PLL unlock detection

PLL_LD_EN=0b1

PLL_LD_EN=0b0

[PLL_LOCK_DETECT:B1 0x0B(7)]

TX

RX

PA_ON =”H”

RX enable =”H”

interrupt occurs and TX stops forcibly

interrupt occurs and RX is continued

interrupt occurs and TX is continued

interrupt occurs and RX is continued

○VCO low limit frequency setting

VCO low limit frequency can be set as described in the “channel frequency setting”.

0x4D] register, is set to [VCO_CAL_MIN_FH:B1 0x4E], [VCO_CAL_MIN_FM:B1 0x4F], [VCO_CAL_MIN_FL:B1

0x50] registers in MSB – LSB order.

I

is set to [VCO_CAL_MIN_I:B1

F

example) If operation low limit frequency is 870MHz, setting value should be lower than 2.2MHz, Then in following

example, low limit frequency is set to 866MHz, master clock frequency is 26MHz.

I

F

= 866MHz/26MHz (Integer part) = 33(0x21)

=(866MHz/26MHz-33) * 2²⁰(Integer part) = 12905550 (0xC4EC4E)

Setting values for each register is as follows:

[VCO_CAL_MIN_I] = 0x21

[VCO_CAL_MIN_FH] = 0xC4

[VCO_CAL_MIN_FM] = 0xEC

[VCO_CAL_MIN_FL] = 0x4E

89/230

FEDL7406-06

ML7406

○VCO upper limit frequency setting

VCO upper limit frequency is calculated as following formula, based on low limit frequency value and

VCO_CAL_MAX_N[3:0] ([VCO_CAL_MAX_N: B1 0x51(3-0)]).

VCO calibration upper limit frequency = VCO calibration low limit frequency (B1 0x4D-0x50) + ΔF(B1 0x51)

ΔF is defined in the table below.

VCO_CAL_MAX_N[3:0]

0b0000

ΔF[MHz]

0

0b0001

0b0010

0b0011

0b0100

0.8125

1.625

3.25

6.5

0b0101

13

0b0110

26

0b0111

52

Other than above

prohibited

90/230

FEDL7406-06

ML7406

●Energy detection value (ED value) adjustment

[ED value adjustment]

ED value is calculated by RSSI signal (analog signal) from RF part,. By performing the following adjustment, it is possible

to correct the variation in LSIs.

The gain adjustment and related registers are described below.

In order to cover wider input range, gain should be changed at given point. Threshold for gain change points are set by

[GAIN_MTOL: B1 0x0C] to [GAIN_MTOH: B1 0x0F]. [RSSI_ADJ_M: B1 0x10] and [RSSI_ADJ_L: B1 0x11] registers

are used to addition values to maintain linearity when changing gain. RSSI slope can be set to [RSSI_MAG_ADJ: B1 0x13]

register so that ED value can be between 0x00(min) and 0xFF(max). Please set to these registers based on the “Initialization

table”, do not change the setting for these registers for tuning.

Adjusting the input level variation for the same input level can be set to [RSSI_ADJ: B0 0x66] register. It must compensate

the slope before compensation defined by [RSSI_MAG_ADJ:B0 0x13] register. However, if positive value is set , ED value

cannot be decreased down to 0x00 at low input signal level. If negative value is set, ED value cannot be increased up to 0xFF.

ED value

RSSI_MAG_ADJ

RSSI_ADJ_L

GAIN_HTOM

(B1 0x0E)

(B1 0x13)

(B1 0x11)

RSSI value (ADC output)

RSSI_ADJ_M

(B1 0x10)

GAIN_MTOH

(B1 0x0F)

RSSI_ADJ

(B0 0x66)

GAIN_MTOL

(B1 0x0C)

GAIN_LTOM

(B1 0x0D)

High gain

Operation range

Middle gain

Operation range

Low gain

Operation range

low

high

RF input level

Operation in the High gain range:

Operation in the Middle gain range:

RSSI value>GAIN_HtoM, and move to Middle gain.

RSSI value>GAIN_MtoL, and move to Low gain.

GAIN_MtoHRSSI value, and move to High gain.

GAIN_LtoMRSSIvalue, and move to Middle gain.

Operation in the Low gain range:

91/230

FEDL7406-06

ML7406

●Oscillation circuit adjustment

In case of using a crystal oscillator (ML7406C), crystal oscillator frequency deviation can be tuned by adjusting load

capacitance of XIN pin (pin#5) and XOUT pin (pin #6). Load capacitance can be adjusted by [OSC_ADJ1: B0 0x62] and

[OSC_ADJ2: B0 0x63].

Adjustable capacitance is as follows:

[OSC_ADJ1] Coarse adjustment of load capacitance: 0.7pF/step (setting range: 0x00 to 0x0F)

[OSC_ADJ2] Fine adjustment of load capacitance: 0.02pF/step (setteing range: 0x00 to 0x77)

OSC_ADJ

92/230

FEDL7406-06

ML7406

■Register setting

●Wireless M-Bus mode setting

The following parameter tables are example for programing each Wireless M-Bus mode (S/T/R/C).

○Mode S

Register

Comms direction

TX/RX parameter

TX frequency

name

TXFREQ_I

address

B1 0x1B

B1 0x1C

B1 0x1D

B1 0x1E

B1 0x1F

B1 0x20

B1 0x21

B1 0x22

B0 0x06

MeterToOther

0x21

OtherToMeter

←

TXFREQ_FH

TXFREQ_FM

TXFREQ_FL

RXFREQ_I

RXFREQ_FH

RXFREQ_FM

RXFREQ_FL

DRATE_SET

0x06

0x56

0xA5

0x21

0x06

0x56

0xA5

0x88

RX frequency

Data rate

Preamble pattern/

Modulation scheme/coding scheme

DATA_SET1

B0 0x07

0x00

←

-

DATA_SET2

GFSK_DEV_H

GFSK_DEV_L

B0 0x08

B1 0x30

B1 0x31

B1 0x32

B1 0x33

B1 0x34

B1 0x35

B1 0x36

B1 0x37

B1 0x38

B1 0x39

B1 0x3A

B1 0x3B

B1 0x3C

B1 0x3D

B1 0x3E

B1 0x3F

B1 0x40

B0 0x42

B0 0x43

B1 0x25

B1 0x27

B1 0x28

B1 0x29

B1 0x2A

B1 0x2B

B1 0x2C

B1 0x2D

B1 0x2E

B0 0x44

B0 0x54

B0 0x55

B0 0x56

B0 0x57

B0 0x5C

B0 0x5D

B0 0x60

B0 0x61

0x00

-

Searching two SyncWords

Frequency deviation (GFSK)

Frequency deviation (FSK)

FSK_DEV0_H/GFIL0

FSK_DEV0_L/GFIL1

FSK_DEV1_H/GFIL2

FSK_DEV1_L/GFIL3

FSK_DEV2_H/GFIL4

FSK_DEV2_L/GFIL5

FSK_DEV3_H/GFIL6

FSK_DEV3_L

FSK_DEV4_H

FSK_DEV4_L

FSK_TIM_ADJ4

FSK_TIM_ADJ3

0x07

0xE0

0x07

0xE0

0x07

0xE0

0x07

0xE0

0x07

0xE0

0x04

0x00

0x0F

0x12

0x00

0x76

0x96

-

←

FSK_TIM_ADJ2

FSK_TIM_ADJ1

FSK_TIM_ADJ0

TXPR_LEN_H

Frequency deviation time (FSK)

Preamble length

SyncWord length

TXPR_LEN_L

SYNC_WORD_LEN

SYNC_WORD1_SET0

SYNC_WORD1_SET1

SYNC_WORD1_SET2

SYNC_WORD1_SET3

SYNC_WORD2_SET0

SYNC_WORD2_SET1

SYNC_WORD2_SET2

SYNC_WORD2_SET3

POSTAMBLE_SET

IF_FREQ_H

←

-

←

SyncWord pattern1

SyncWord pattern2

-

0x11

0x27

0x62

0x27

0x62

0xB8

0x3A

0x20

Postamble setting

IF frequency setting

IF_FREQ_L

IF_FREQ_CCA_H

IF_FREQ_CCA_L

BPF_CO

BPF_CO_CCA

IFF_ADJ_CCA_H

IFF_ADJ_CCA_L

IF frequency during CCA

BPF coefficient

BPF coefficient during CCA.

Demodulator DC level adjustment

during CCA.

←

DEMOD_SET1

DEMOD_SET2

DEMOD_SET3

DEMOD_SET4

DEMOD_SET5

DEMOD_SET6

DEMOD_SET7

DEMOD_SET8

DEMOD_SET9

B1 0x57

B1 0x58

B1 0x59

B1 0x5A

B1 0x5B

B1 0x5C

B1 0x5D

B1 0x5E

B1 0x5F

←

0x15

0x3A

0x20

0x2A

0x6A

0x25

0x2C

0x02

0x89

Demodulator adjustment 1

Demodulator adjustment 2

Demodulator adjustment 3

Demodulator adjustment 4

Demodulator adjustment 5

Demodulator adjustment 6

Demodulator adjustment 7

Demodulator adjustment 8

Demodulator adjustment 9

93/230

FEDL7406-06

ML7406

○Mode T

Register

Comms. direction

TX/RX parameter

TX frequency

name

TXFREQ_I

address

B1 0x1B

B1 0x1C

B1 0x1D

B1 0x1E

B1 0x1F

B1 0x20

B1 0x21

B1 0x22

B0 0x06

MeterToOther

0x21

OtherToMeter

←

TXFREQ_FH

TXFREQ_FM

TXFREQ_FL

RXFREQ_I

RXFREQ_FH

RXFREQ_FM

RXFREQ_FL

DRATE_SET

0x06

0xBD

0x0B

0x21

0x56

0xA5

←

0x06

←

RX frequency

0x56

0xA5

0x8B

0xBD

0x0B

0xB8

Data rate

Preamble pattern/

Modulation scheme/coding scheme

DATA_SET1

DATA_SET2

B0 0x07

B0 0x08

0x02

0x08

Select SyncWord pattern/

Searching two SyncWords

TX: 0x00

RX: 0x10

-

←

GFSK_DEV_H

GFSK_DEV_L

B1 0x30

B1 0x31

B1 0x32

B1 0x33

B1 0x34

B1 0x35

B1 0x36

B1 0x37

B1 0x38

B1 0x39

B1 0x3A

B1 0x3B

B1 0x3C

B1 0x3D

B1 0x3E

B1 0x3F

B1 0x40

B0 0x42

B0 0x43

-

←

Frequency deviation (GFSK)

Frequency deviation (FSK)

-

FSK_DEV0_H/GFIL0

FSK_DEV0_L/GFIL1

FSK_DEV1_H/GFIL2

FSK_DEV1_L/GFIL3

FSK_DEV2_H/GFIL4

FSK_DEV2_L/GFIL5

FSK_DEV3_H/GFIL6

FSK_DEV3_L

0x07

0xE0

0x07

0xE0

0x07

0xE0

0x07

0xE0

0x07

0xE0

0x04

0x00

0x13

TX: 0x0A

RX: 0x12

0x00

0x3D

0x00

0x76

0x96

0x15

0x27

0x62

0x27

0x62

0xB8

0x3A

0x20

0x15

0x3A

0x20

0x2A

0x6A

0x25

0x2C

0x02

0x89

FSK_DEV4_H

FSK_DEV4_L

FSK_TIM_ADJ4

FSK_TIM_ADJ3

FSK_TIM_ADJ2

FSK_TIM_ADJ1

FSK_TIM_ADJ0

TXPR_LEN_H

Frequency deviation time (FSK)

←

Preamble length

SyncWord length

TXPR_LEN_L

0x0F

TX: 0x12

RX: 0x08

←

SYNC_WORD_LEN

B1 0x25

SYNC_WORD1_SET0

SYNC_WORD1_SET1

SYNC_WORD1_SET2

SYNC_WORD1_SET3

SYNC_WORD2_SET0

SYNC_WORD2_SET1

SYNC_WORD2_SET2

SYNC_WORD2_SET3

POSTAMBLE_SET

IF_FREQ_H

B1 0x27

B1 0x28

B1 0x29

B1 0x2A

B1 0x2B

B1 0x2C

B1 0x2D

B1 0x2E

B0 0x44

B0 0x54

B0 0x55

B0 0x56

B0 0x57

B0 0x5C

B0 0x5D

B0 0x60

B0 0x61

B1 0x57

B1 0x58

B1 0x59

B1 0x5A

B1 0x5B

B1 0x5C

B1 0x5D

B1 0x5E

B1 0x5F

←

SyncWord pattern 1(*1)

SyncWord pattern 2(*1)

0x76

0x96

←

0x00

0x3D

←

Postamble setting

0x38

0xB6

0x38

0xB6

0x80

0x1B

0x01

0x14

0x1B

0x01

0x21

0xB2

0x26

0x37

0x03

0xDB

IF frequency setting

IF_FREQ_L

IF_FREQ_CCA_H

IF_FREQ_CCA_L

BPF_CO

IF frequency during CCA.

BPF coefficient

BPF coefficient during CCA.

Demodulator DC level adjustment

during CCA

BPF_CO_CCA

IFF_ADJ_CCA_H

IFF_ADJ_CCA_L

DEMOD_SET1

DEMOD_SET2

DEMOD_SET3

DEMOD_SET4

DEMOD_SET5

DEMOD_SET6

DEMOD_SET7

Demodulator adjustment 1

Demodulator adjustment 2

Demodulator adjustment 3

Demodulator adjustment 4

Demodulator adjustment 5

Demodulator adjustment 6

Demodulator adjustment 7

Demodulator adjustment 8

Demodulator adjustment 9

DEMOD_SET8

DEMOD_SET9

94/230

FEDL7406-06

ML7406

○Mode C

Register

Comms. direction

TX/RX parameter

TX frequency

Name

TXFREQ_I

Address

B1 0x1B

B1 0x1C

B1 0x1D

B1 0x1E

B1 0x1F

B1 0x20

B1 0x21

B1 0x22

B0 0x06

Meter To Other

0x21

Other To Meter

←

TXFREQ_FH

TXFREQ_FM

TXFREQ_FL

RXFREQ_I

RXFREQ_FH

RXFREQ_FM

RXFREQ_FL

DRATE_SET

0x06

0x07

0xBD

0x17

0x0B

0x21

0xA1

←

0x07

0x06

RX frequency

0x17

0xA1

0xAB

0xBD

0x0B

0xBA

Data rate

Preamble pattern/

Modulation scheme/coding scheme

DATA_SET1

B0 0x07

0x05

0x15

Searching two SyncWord

DATA_SET2

GFSK_DEV_H

GFSK_DEV_L

B0 0x08

B1 0x30

B1 0x31

B1 0x32

B1 0x33

B1 0x34

B1 0x35

B1 0x36

B1 0x37

B1 0x38

B1 0x39

B1 0x3A

B1 0x3B

B1 0x3C

B1 0x3D

B1 0x3E

B1 0x3F

B1 0x40

B0 0x42

B0 0x43

B1 0x25

B1 0x27

B1 0x28

B1 0x29

B1 0x2A

B1 0x2B

B1 0x2C

B1 0x2D

B1 0x2E

B0 0x44

B0 0x54

B0 0x55

B0 0x56

B0 0x57

B0 0x5C

B0 0x5D

B0 0x60

B0 0x61

B1 0x57

B1 0x58

B1 0x59

B1 0x5A

B1 0x5B

B1 0x5C

B1 0x5D

B1 0x5E

B1 0x5F

0x08

-

←

0x03

0xF0

0x49

0xA7

0x0F

0x14

0x19

0x1D

0x1E

-

←

Frequency deviation (GFSK)

Frequency deviation (FSK)

FSK_DEV0_H/GFIL0

FSK_DEV0_L/GFIL1

FSK_DEV1_H/GFIL2

FSK_DEV1_L/GFIL3

FSK_DEV2_H/GFIL4

FSK_DEV2_L/GFIL5

FSK_DEV3_H/GFIL6

FSK_DEV3_L

0x07

0x16

0x07

0x16

0x07

0x16

0x07

0x16

0x07

0x16

0x04

0x00

0x10

0x20

0x54

0x3D

0x54

0xCD

0x54

0x3D

0x54

0x3D

0x00

0x27

0x62

0x27

0x62

0xB8

0x1F

0x04

0x15

0x1F

0x04

0x13

0x7A

0x23

0x2A

0x03

0xAC

FSK_DEV4_H

FSK_DEV4_L

FSK_TIM_ADJ4

FSK_TIM_ADJ3

FSK_TIM_ADJ2

FSK_TIM_ADJ1

FSK_TIM_ADJ0

TXPR_LEN_H

Frequency deviation time (FSK)

Preamble length

SyncWord length

TXPR_LEN_L

SYNC_WORD_LEN

SYNC_WORD1_SET0

SYNC_WORD1_SET1

SYNC_WORD1_SET2

SYNC_WORD1_SET3

SYNC_WORD2_SET0

SYNC_WORD2_SET1

SYNC_WORD2_SET2

SYNC_WORD2_SET3

POSTAMBLE_SET

IF_FREQ_H

SyncWord pattern1

SyncWord pattern2

←

Postamble setting

0x38

0xB6

0x38

0xB6

0x80

0x1B

0x01

0x14

0x1B

0x01

0x21

0xB2

0x26

0x37

0x03

0xDB

IF frequency setting

IF_FREQ_L

IF_FREQ_CCA_H

IF_FREQ_CCA_L

BPF_CO

IF frequency during CCA

BPF coefficient

BPF coefficient during CCA

Demodulator DC level adjustment

during CCA

BPF_CO_CCA

IFF_ADJ_CCA_H

IFF_ADJ_CCA_L

DEMOD_SET1

DEMOD_SET2

DEMOD_SET3

DEMOD_SET4

DEMOD_SET5

DEMOD_SET6

DEMOD_SET7

Demodulator adjustment 1

Demodulator adjustment 2

Demodulator adjustment 3

Demodulator adjustment 4

Demodulator adjustment 5

Demodulator adjustment 6

Demodulator adjustment 7

Demodulator adjustment 8

Demodulator adjustment 9

DEMOD_SET8

DEMOD_SET9

95/230

FEDL7406-06

ML7406

●IEEE 802.15.4g setting

The following parameter tables are example for programing IEEE 802.15.4 format.

○Common setting

(1) Whitening setting

Register

Setting

Value

0x00

0xF0

0x10

Parameter

Name

Address

B1 0x64

B1 0x65

B1 0x66

Whitening initialized state (high 1 bit)

Whitening initialized state (low byte)

Whitening polynomial

WHT_INIT_H

WHT_INIT_L

WHT_CFG

○TX

(1) CRC 16, without Whitening

Register

Name

PKT_CTRL1

PKT_CTRL2

DATA_SET2

Setting

Value

0x16

0x5D

0x00

Parameter

Address

B0 0x04

B0 0x05

B0 0x08

B0 0x7A

Packet format

CRC Length

Whitening enable

Packet header (bit15-11)

TX_PKT_LEN_H(bit7-3)

0b0_0010

(2) CRC 16, with Whitening

Register

Name

PKT_CTRL1

PKT_CTRL2

DATA_SET2

Setting

Value

0x16

0x5D

0x01

Parameter

Address

B0 0x04

B0 0x05

B0 0x08

B0 0x7A

Packet format

CRC Length

Whitening enable

Packet header (bit15-11)

TX_PKT_LEN_H(bit7-3)

0b0_0011

(3) CRC 32, without Whitening

Register

Name

PKT_CTRL1

PKT_CTRL2

DATA_SET2

Setting

Value

0x16

0xAD

0x00

Parameter

Address

B0 0x04

B0 0x05

B0 0x08

B0 0x7A

Packet format

CRC Length

Whitening enable

Packet header (bit15-11)

TX_PKT_LEN_H(bit7-3)

0b0_0000

(4) CRC 32, with Whitening

Register

Name

PKT_CTRL1

PKT_CTRL2

DATA_SET2

Setting

Value

0x16

0x5D

0x01

Parameter

Address

B0 0x04

B0 0x05

B0 0x08

B0 0x7A

Packet format

CRC Length

Whitening enable

Packet header (bit15-11)

TX_PKT_LEN_H(bit7-3)

0b0_0001

○RX

By setting IEEE4G_EN([PKT_CTRL1:B0 0x04(2)])=0b1, ML7406 identifies the FCS and Whitening information from the

receiving packet header (PHR).

Register

Setting

Value

0x16

Parameter

Name

Address

B0 0x04

B0 0x05

B0 0x08

Packet format

CRC Length

Whitening enable

PKT_CTRL1

PKT_CTRL2

DATA_SET2

0x5D or 0xAD

0x01 or 0x00

96/230

FEDL7406-06

ML7406

●BER measurement setting

The following registers setting are necessary for RX side when BER measurement equipment is connected.

[DIO_SET: B0 0x0C] = 0x40

[MON_CTRL: B0 0x4D] = 0x80

[GPIO0_CTRL: B0 0x4F] to [GPIO3_CTRL: B0 0x52] for setting DCLK/DIO output pins.

[GAIN_HTOM: B1 0x0E(7)] = 0b0

When termiate BER measurement and reurn from RX state, Force TRX_OFF should be issued by SET_TRX[3:0]

([RF_STATUS:B0 0x0b(3-0]) =0b0011.

97/230

FEDL7406-06

ML7406

■Flowchart

Category

Turn on

sequence

Condition 1

Condition 2

Name of flow

(1) Initialization flow

-

TX/RX common

Sequence

TX Sequence

-

(1) RF state transition wait

DIO mode

TX (1) DIO mode

FIFO mode

Under 64 byte

65 byte or more (FAST_TX)

-

TX (2) FIFO mode

TX (3) FIFO mode

TX (4) automatic TX

RX (1) DIO mode

Automatic TX

DIO mode

RX Sequence

FIFO mode

Under 64 byte

65 byte or mode

-

RX (2) FIFO mode

RX (3) FIFO mode

RX (4) ACK transmission

RX (5) Field checking

RX (6) CCA normal mode

ACK transmission

Field check

CCA

Normal mode

Continuous execution mode

IDLE detection mode

-

RX (6) CCA continuous execution mode

RX (6) CCA IDLE detection mode

RX (7) high speed carrier checking

RX (8) ED-SCAN

High speed carrier checking

ED-SCAN

Antenna diversity

SLEEP

Wake-up timer

Sync error

TX FIFO access error

RX FIFO access error

PLL unlock

Execute diversity

RX (9) antenna diversity

(1) SLEEP

(2) Wake-up timer

SLEEP

Sequence

Error Process

-

(1) Sync error

(2) TX FIFO access error

(3) RX FIFO access error

(4) PLL unlock

Data Rate

Change

-

(1) Change Data Rate

Sequence

98/230

FEDL7406-06

ML7406

●Turn on Sequence

(1) Initializing flow

In initialization status, Interrupt process, registers setting, VCO calibration are necessary.

(1) Interrupt process

Upon reset, all interrupt notification settings ([INT_EN_GRP1-3: B0 0x10-0x12]) are disabled.

After hard reset is released, INT[0] (group1: clock stabilization completion interrupt) and INT[1] (group1: VCO

calibration completion / Fuse access completion interrupt) will be detected. INT[0] and INT[1] should be enabled by

[INT_EN_GRP1:B0 0x10] register.

In case of ML7406T, after hard reset is released, set 0b1 to INT_EN[0] [INT_EN0:B0 0x10(0)] and TCXO_EN

[CLK_SET2:B0 0x03(6)] at first.

(2) Registers setting

(ML7406C)

After hard reset is released, all registers in BANK0 and BANK1 except FIFO access registers ([WR_TX_FIFO: B0

0x7C] and [RD_FIFO: B0 0x7F]), are accessible before INT[0] notification.

(ML7406T)

After hard reset is released, all registers in BANK0 and BANK1 except FIFO access registers ([WR_TX_FIFO: B0

0x7C] and [RD_FIFO: B0 0x7F]), are prohibited until INT[0] occurrence from GPIO0 pin.

(3) VCO calibration

VCO calibration is executed after setting upper and low limit of the operation frequency.

For details, please refer to the “VCO adjustment”.

START

INT_EN setting

[INT_EN_GRP1-3: B0

0x10-0x12]

No

Clock stabilized completion int. ?

INT[0] [INT_SOURCE_GRP1: B0 0x0D]

(1)Interrupt process

Yes

INT[0] Clear

[INT_SOURCE_GRP1 B0 0x0D]

Register setting

(2)Register setting

(3)VCO calibration

*For details, please refer to the “VCO adjustment”

VCO calibration execution

END

99/230

FEDL7406-06

ML7406

100/230

FEDL7406-06

ML7406

●TX/RX Common Sequence

(1) RF state transition wait

If below setting for RF state change is selected, please confirm the completion of RF state transtion by INT[3] (group1: RF

state transtion completion interrupt).

○RF state transition by [RF_STATUS: B0 0x0B]

○RF state transition by [RF_STATUS_CTRL: B0 0x0A]

●FAST_TX mode setting

●automatic TX setting

●RF state setting after TX completion

●RF state setting after RX completion

○RF state modification by wake-up timer setting

i) TRX_OFF flow

RF state change by [RF_STATUS: B0 0x0B]

SET_TRX[3:0]=0b1000

START

TRX_OFF issue

[RF_STATUS: B0 0x0B]

RF state transition completion

Interrupt confirmation

INT[3]( [INT_SOURCE_GRP1: B0 0x0D]

END

RF state change by [RF_STATUS_CTRL: B0 0x0A]

TXDONE_MODE[1:0=0b00

RXDONE_MODE[1:0]=0b00

START

TX completion interrupt?

INT[16] [[INT_SOURCE_GRP3:

B0 0x0F])

RX completion interrupt?

No

INT[8] [[INT_SOURCE_GRP3:

B0 0x0F])

Yes

RF state transition completion

Interrupt confirmation

RF state transition completion

Interrupt confirmation

INT[3] ([INT_SOURCE_GRP1: B0 0x0D])

END

101/230

FEDL7406-06

ML7406

ii) TX_ON flow

RF state transition change by [RF_STATUS: B0 0x0B]

SET_TRX[3:0]=0b1001

START

TX_ON issue

[RF_STATUS: B0 0x0B]

RF state transition completion

Interrupt confirmation

INT[3] ([INT_SOURCE_GRP1: B0 0x0D])

END

RF state transition by [RF_STATUS_CTRL]register(B0 0x0A)

RXDONE_MODE[1:0]=0b10

FAST_TX_EN=0b1 and

AUTO_TX_EN=0b1

START

No

RX completion int.??

INT[8] ([INT_SOURCE_GRP2: B0

0x0E])

FIFO write

Yes

RF state transition completion

Interrupt confirmation

INT[3]( [INT_SOURCE_GRP1: B0 0x0D])

RF state transition completion

Interrupt confirmation

INT[3]( [INT_SOURCE_GRP1: B0 0x0D])

END

102/230

FEDL7406-06

ML7406

iii) RX_ON flow

RF state change by [RF_STATUS: B0 0x0B]

RF state change by [RF_STATUS_CTRL: B0 0x0A]

SET_TRX[3:0]=0b0110

TXDONE_MODE[1:0]=0b10

START

RX_ON issue

[RF_STATUS: B0x0B]

TX completion int. ?

INT[16] ([[INT_SOURCE_GRP2: B0

0x0F]]

No

Yes

RF state transition completion

Interrupt confirmation

INT[3]( [INT_SOURCE_GRP1: B0 0x0D])

RF state transition completion

Interrupt confirmation

INT[3]( [INT_SOURCE_GRP1: B0 0x0D])

END

iv) Wake-up flow

The following flow doses not apply to the case when waiting for INT[13] (group 2: SyncWord detection interrupt.) after

wake-up.

START

SLEEP setting

RF state transition completion

Interrupt confirmation

INT[3]( [INT_SOURCE_GRP1: B0 0x0D])

END

103/230

FEDL7406-06

ML7406

● TX Sequence

(1) DIO mode

DIO(TX) mode can be selected by setting TXDIO_CTRL[1:0]([DIO_SET: B0 0x0C(5-4)])=0b01 or 0b10. In DIO mode,

when issuing TX_ON by [RF_STATUS:B0 0x0B] register, data input on the pin related DIO will be transimitted to the air.

After TX completion, TRX_OFF should be issued by [RF_STATUS:B0 0x0B] register.

START

*1 DIO/DCLK pins are defined as follows:

[GPIO0_CTRL: B0 0x4E]

[GPIO1_CTRL: B0 0x4F]

[GPIO2_CTRL: B0 0x50]

[GPIO3_CTRL: B0 0x51]

[EXT_CLK_CTRL: B0 0x52]

[SPI/EXT_PA_CTRL: B0 0x53]

DIO pins setting*1

TXDIO_CTRL setting=0b10

[DIO_SET: B0 0x0C(5-4)]

*2 Preamble, SyncWord is transmitted based on the

following registers.

preamble/SyncWord

setting*2

Preamble

[DATA_SET1: B0 0x07]

[TXPR_LEN_H/L: B0 0x42-43]

SyncWord [SYNCWORD1_SET0-3: B1 0x27-2A]

[SYNCWORD2_SET0-3: B1 0x2B-2E]

[SYNC_WORD_LEN: B1 0x25]

[DATA_SET2: B0 0x08]

TX_ON issue

[RF_STATUS: B0 0x0B]

*3 Timing up to DCLK output varies depending on TX

preamble, SFC, data rate.

DCLK output wait

*3

*4 TX data must be input at falling edge of DCLK.

*5 Please refer to RF state transition wait flow.

TX data input *4

(DIO pins)

No

TX completed?*5

Yes

TRX_OFF issue

[RF_STATUS: B0 0x0B]

Yes

Next packet to be transmitted?

No

END

104/230

FEDL7406-06

ML7406

(2) FIFO mode (less than 64byte)

FIFO mode (packet mode) can be selected by setting TXDIO_CTRL[1:0]([DIO_SET: B0 0x0C(5-4)])=0b00. In FIFO

mode, data is written to the TX_FIFO by [WR_TX_FIFO:B0 0x7C] register. After writing full data of a packet, issuing

TX_ON by [RF_STATUS:B0 0x0B] register. Following preamble/SyncWord, TX_FIFO data is transmitted to the air. Upon

TX completion interrupt (INT[16] group 3 ) occurs, interrupt must be cleared. If the next TX packet is sent, the next TX

packet data is written to the TX_FIFO. If RX is expected after TX, RX_ON should be issued by [RF_STATUS: B0 0x0B]

register. TX can be terminated by issuing TRX_OFF by [RF_STATUS:B0 0x0B] register.

START

If the TX data length is shorter than the FAST_TX

TX FIFO trigger level setting

trigger level, TX will start by writing all data to FIFO.

[TXFIFO_THRH: B0 0x17]=0x00

[TXFIFO_THRL: B0 0x18]=0x00

Write TX data

[WR_TX_FIFO:B0 0x7C]

From CCA flowchart

TX data request accept

completion (INT[17])?

No

[INT_SOURCE_GRP3: B0 0x0F(1)]

No

Yes

CCA result=BUSY?

INT[17] clear

[INT_SOURCE_GRP3: B0 0x0F]

Yes

CCA continue?

Yes

No

To CCA flowchart

i) If random back-off period specified in the IEEE is

used, go to CCA normal mode.

ii) If IDLE is detected in minimum period, go to

CCA IDLE detection mode.

CCA execution ?

No

TX FIFO clear

[STATE_CLR: B0 0x16]

TX_ON issue

[RF_STATUS: B0 0x0B]

*please refer to RF state

transition wait flow.

TRX_OFF issue

[RF_STATUS: B0 0x0B]

No

TX completion (INT[16]) ?

([INT_SOURCE_GRP3: B0 0x0F(0)])

RF state transition wait flow

Yes

INT[16/17] clear

([INT_SOURCE_GRP3: B0 0x0F])

Write TX data

[WR_TX_FIFO:B0 0x7C]

Set RXON after TX completion?

[RF_STATUS_CTRL:B0 0x0A]

Yes

No

Set TRXOFF/SLEEP after TX?

[RF_STATUS_CTRL:B0 0x0A]

RF state transition wait flow

No

Yes

Next packet TX ?

No

RX_ON issue

[RF_STATUS: B0 0x0B]

Yes

RX?

No

TRX_OFF issue

[RF_STATUS: B0 0x0B]

To RF state transition wait flow

and RX flow

To RF state transition wait flow

105/230

FEDL7406-06

ML7406

(3) FIFO mode (65 byte or more)

The Host must write TX data to the TX_FIFO while checking INT[5] (group1: FIFO-Full interrupt) and INT[4] (group1:

FIFO-Empty interrupt) in order to avoid FIFO-Overrun or FIFO-Underrun. Other operations are identical to the FIFO mode

(less than 64byte). Enabling FAST_TX mode by FAST_TX_EN ([RF_STATUS_CTRL: B0 0x0A(5)] =0b1, TX will start

when data amount written to the FIFO exceeds the bytes+1 in the [TXFIFO_THRL: B0 0x18].

START

FAST_TX mode setting

TX FIFO-Full level setting

[RF_STATUS_CTRL: B0 0x0A]

[TXFIFO_THRH: B0 0x17]

TX FIFO-Empty level setting [TXFIFO_THRL: B0 0x18]

●If data written to FIFO exceed THFIFO_THRL[5:0]

[TXFIFO_THRL:B0 0x18(5-0)]+1, ()TX will start.

●Please refer to RF state transition wait flow.

Write TX data

[WR_TX_FIFO:B0 0x7C]

FIFO-Empty (INT[4])?

([INT_SOURCE_GRP1: B0 0x0D(4)])

Yes

INT[4] clear

([INT_SOURCE_GRP: B0 0x0D)

No

*Total data amount should be the size

subtracting CRC length from the

Length value.

If too much TX data written to a

FIFO, after TX completion interrupt,

issue TRX_OFF and TX FIFO must

be cleared.

TX FIFO-Empty level

Disable setting

[TX_FIFO_THRL: B0 0x18]

Write TX data

[WR_TX_FIFO:B0 0x7C]

TX FIFO-Empty level

Enable setting

[TX_FIFO_THRL: B0 0x18]

TX Data request accept

completion (INT[17])?

No

([INT_SOURCE_GRP3: B0 0x0F(1)])

Yes

TX completion (INT[16])?

([INT_SOURCE_GRP3: B0 0x0F(0)])

Yes

INT[16] and INT[17] clear

([INT_SOURCE_GRP3: B0 0x0F])

Yes

Write TX data

[WR_TX_FIFO:B0 0x7C]

Set RX_ON after TX completion?

[RF_STATUS_CTRL:B0 0x0A]

No

Set TRX_OFF/SLEEP after TX?

[RF_STATUS_CTRL:B0 0x0A]

No

Yes

RX_ON issue

[RF_STATUS: B0 0x0B]

RX?

No

Next packet TX?

No

Yes

Go to RF state transition wait

and RX flow

To RF state transition wait flow

106/230

FEDL7406-06

ML7406

(4) Automatic TX (less than 64byte)

If AUTO_TX_EN([RF_STATUS_CTRL: B0 0x0A(4)]=0b1, TX starts automatically when FIFO is filled with data

equivalent to the Langth. Afer TX completion, RFstate transition setting is by TXDONE_MODE ([RF_STATUS_CTRL: B0

0x0A(1-0)]).

START

Automatic TX setting

RF_STATUS_CTRL: B0 0x0A]

●When data equivalent to Length is written to FIFO, TX

starts automatically.

●Please refer to RF state transition wait flow.

Write TX data

[WR_TX_FIFO:B0 0x7C]

Data TX request accept

No

completion (INT[17])?

([INT_SOURCE_GRP3: B0 0x0F(1)])

Yes

No

TX completion (INT[16])?

([INT_SOURCE_GRP3: B0 0x0F(0)])

Yes

INT[16] and INT[17] clear

([INT_SOURCE_GRP3: B0 0x0F])

Set RX_ON after TX completion?

[RF_STATUS_CTRL:B0 0x0A]

Yes

Write TX data

[WR_TX_FIFO:B0 0x7C]

No

Set TRX_OFF/SLEEP after TX?

[RF_STATUS_CTRL:B0 0x0A]

No

RX_ON issue

[RF_STATUS: B0 0x0B]

Yes

RX?

Yes

Next packet TX ?

No

To r RF sate transition wait

and RX flow.

To RF state transition wait flow

107/230

FEDL7406-06

ML7406

●RX Sequence

(1) DIO mode

DIO mode can be selected by setting RXDIO_CTRL[1:0]([DIO_SET: B0 0x0C(7-6)])=0b10/0b11. Upon setting DIO mode

and issuing RX_ON by [RF_STATUS:B0 0x0B] register, SyncWord detection will be started.

○DIO outmupt mode 1 operation

While RXDIO_CTRL[1:0]=0b10, after SyncWord pattern detection, RX data will be strored into the RX_FIFO. RX data

stored in the RX_FIFO is output through DIO pins, if setting DIO_START ([DIO_SET: B0 0x0C(0)])=0b1. Upon RX

completion, if more data is to be received, by setting DIO_RX_COMPLETE([DIO_SET: B0 0x0C(2)])=0b1 (DIO RX

completion), the next packet will be ready to receive. In case of TRX_OFF, issuing TRX_OFF by [RF_STATUS:B0 0x0B]

register.

START

*1 DIO/DCLK function pins setting

[GPIO0_CTRL: B0 0x4E]

[GPIO1_CTRL: B0 0x4F]

DIO pins setting *1

[GPIO2_CTRL: B0 0x50]

[GPIO3_CTRL: B0 0x51]

[EXT_CLK_CTRL: B0 0x52]

RXDIO_CTRL setting =0b10

[SPI/EXT_PA_CTRL: B0 0x53]

[DIO_SET: B0 0x0C(7-6)]

*2 Preamble, SyncWord and Error tolerance are set by

Preamble/SyncWord/

following registers.

Error tolerance setting *2

Preamble

[DATA_SET1: B0 0x07]

[SYNC_CONDITION1-3: B0 0x45-47]

[SYNCWORD1_SET0-3: B1 0x27-2A]

[SYNCWORD2_SET0-3: B1 0x2B-2E]

[SYNC_WORD_LEN: B1 0x25]

[DATA_SET2: B0 0x08]

SyncWord

RX_ON issue*3

[RF_STATUS: B0 0x0B]

*3 Please refer to RF state transition wait flow.

No

SyncWord detection (INT[13])?

[INT_SOURCE_GRP2 B0 0x0E(5)]

Yes

*4 Wait time should be more than 1 byte data

receiving period.

Wait *4

DIO START =0b1

[DIO_SET: 0x0C(0)]

No

DCLK output?

(DCLK function pins)

Yes

Read RX data *5

(DIO function pins)

*5 RX data must be transferred to the Host at rising

edge of DCLK.

No

RX completion?

Yes

DIO_RX_COMPLETION=0b1

[DIO_SET: 0x0C(2)]

Yes

Next packet RX?

No

TRX_OFF issue

[RF_STATUS: B0 0x0B]

To RF state transition wait flow

108/230

FEDL7406-06

ML7406

○DIO outmupt mode 2 operation

While RXDIO_CTRL[1:0]=0b11, RX data (after L-field) will be stored into the RX_FIFO. RX data stored in the RX_FIFO

is output through DIO pins, if setting DIO_START ([DIO_SET: B0 0x0C(0)])=0b1. Upon outputting RX data defined by

L-field, RX is completed and generate RF completion interrupt (INT[8] group2). In case of TRX_OFF, issuing TRX_OFF

by [RF_STATUS:B0 0x0B] register.

START

*1 DIO/DCLK function pins setting

[GPIO0_CTRL: B0 0x4E]

[GPIO1_CTRL: B0 0x4F]

DIO pins setting *1

[GPIO2_CTRL: B0 0x50]

[GPIO3_CTRL: B0 0x51]

[EXT_CLK_CTRL: B0 0x52]

RXDIO_CTRL setting =0b11

[SPI/EXT_PA_CTRL: B0 0x53]

[DIO_SET: B0 0x0C(7-6)]

*2 Preamble, SyncWord and Error tolerance are set by

Preamble/SyncWord/

following registers.

Error tolerance setting *2

Preamble

[DATA_SET1: B0 0x07]

[SYNC_CONDITION1-3: B0 0x45-47]

[SYNCWORD1_SET0-3: B1 0x27-2A]

[SYNCWORD2_SET0-3: B1 0x2B-2E]

[SYNC_WORD_LEN: B1 0x25]

[DATA_SET2: B0 0x08]

SyncWord

RX_ON issue*3

[RF_STATUS: B0 0x0B]

*3 Please refer to RF state transition wait flow.

No

SyncWord detection (INT[13])?

[INT_SOURCE_GRP2 B0 0x0E(5)]

Yes

*4 Wait time should be more than Length field+ 1

byte data receiving period.

Wait *4

1 byte period is decoded 8 bit data. If using

Manchester code, 1 byte period becomes 160μs

(@ 100kbps).

DIO START =0b1

[DIO_SET: 0x0C(0)]

No

DCLK output?

(DCLK function pins)

Yes

Read RX data *5

(DIO function pins)

*5 RX data must be transferred to the Host at rising edge of

DCLK.

No

RX completion (INT[8])? *6

[INT_SOURCE_GRP2 B0 0x0E(0]

*6 Upon outputting whole RX data. INT[8] will generate.

Yes

Next packet RX?

No

TRX_OFF issue

[RF_STATUS: B0 0x0B]

To RF state transition wait flow

109/230

FEDL7406-06

ML7406

(2) FIFO mode (less than 64byte)

FIFO mode can be selected by RXDIO_CTRL[1:0]([DIO_SET: B0 0x0C(7-6)])=0b00. After SyncWord detection, RX data

will be stored into the RX_FIFO. Upon Data RX completion interrupt (INT[8] group2) occurs, the host will read RX data

from [RD_FIFO:B0 0x7F] registers. If CRC errors interrupt (INT[9] group2) is generated, the next packet can be ready to

receive without reading all current RX data by setting STATE_CLR1 [STATE_CLR: B0 0x16(1)](RX FIFO pointer clear).

If FIFO-Full trigger and FIFO-Empty trigger are not used, please set 0b0 to both RXFIFO_THRH_EN([RXFIFO_THRH:

B0 0x19(7)]) and RXFIFO_THRL_EN([RXFIFO_THRH: B0 0x1A(7)]) .

START

RX FIFO trigger level setting

[RXFIFO_THRH: B0 0x19]=0x00

[RXFIFO_THRL: B0 0x1A]=0x00

*1 At lease following 2 interrupts in the group 2

RX_ON issue *1

should be un-masked for data receiving.

[RF_STATUS: B0 0x0B]

INT[8]: RX completion interrupt

INT[15]: Sync error interrupt

No

RX completion (INT[8])?

[INT_SOURCE_GRP2] B0 0x0E(0)]

Yes

CRC error (INT(9))?

[INT_SOURCE_GRP2] B0 0x0E(1)]

RX FIFO pointer clear

[STATE_CLR: B0 0x16(1)]

No

Rear RX data

[RD_FIFO:B0 0x7F]

INT [9] clear

[INT_SOURCE_GRP2: B0 0x0E(1)]

INT[8] clear

[INT_SOURCE_GRP2: B0 0x0E(0)]

Set TX_ON after RX completion ?

[RF_STATUS_CTRL:B0 0x0A]

No

Yes

Set TRXOFF/SLEEP after RX completion?

[RF_STATUS_CTRL:B0 0x0A]

No

Yes

Next packet to be received?

No

Yes

TX_ON issue

TX?

No

[RF_STATUS:B0 0x0B]

TRX_OFF issue

[RF_STATUS: B0 0x0B]

To RF state transition wait flow,

and TX flow

To RF state transition wait flow

110/230

FEDL7406-06

ML7406

(3) FIFO mode (more than 65byte)

The Host must read RX data from the RX_FIFO while checking INT[5] (group1: FIFO-Full interrupt) and INT[4] (group1:

FIFO-Empty interrupt) in order to avoid FIFO-Overrun or FIFO-Underrun. Other operations are identical to the FIFO mode

(less than 64byte).

START

*1 At lease following 2 interrupts in the group 2

RX_ON issue *1

[RF_STATUS: B0 0x0B]

should be un-masked for data receiving.

INT[8]: RX completion interrupt

INT[15]: Sync error interrupt

Yes

FIFO-Full (INT[5])?

[INT_SOURCE_GRP1: B0 0x0D(5)]

FIFO-Full interrupt clear

INT[5] [INT_SOURCE_GRP1: B0 0x0D()]

No

RX FIFO-Full level

Disable setting

[RX_FIFO_THRH: B0 0x19]

Read RX data from FIFO

FIFO-Full level

Enable setting

[RX_FIFO_THRH: B0 0x19]

No

ACK TX?

Yes

No

RX completion (INT[8])?

Ack TX flowchart

[INT_SOURCE_GRP2: B0 0x0E(0)]

Yes

CRC error (INT[9])?

[INT_SOURCE_GRP2: B0 0x0E(1)]

No

RX FIFO pointer clear

[STATE_CLR: B0 0x16(1)]

Read Rx data

[RD_FIFO:B0 0x7F]

INT[9] clear

[INT_SOURCE_GRP2: B0 0x0E()]

INT[8] clear

[INT_SOURCE_GRP2: B0

0x0E()]

Yes

Set TX_ON after RX completion ?

[RF_STATUS_CTRL:B0 0x0A]

No

Yes

Set TRXOFF/SLEEP after RX completion?

[RF_STATUS_CTRL:B0 0x0A]

To RF state change wait flow

No

Next packet to be received ?

No

Yes

TX_ON issue

[RF_STATUS:B0 0x0B]

Yes

TX ?

No

TRX_OFF issue

[RF_STATUS: B0 0x0B]

To RF state transition wait flow,

and TX flow

To RF state transition wait flow

111/230

FEDL7406-06

ML7406

(4) ACK transmission

ACK TX flow is as follows. During RX, ACK frame can be set in the TX FIFO.

START

* In case of using interrupt,

FIFO-Full interrupt notification should be ON.

RX FIFO trigger setting *1

[RXFIFO_THRH: B0 0x19]

[RXFIFO_THRL: B0 0x1A]

*2 Please refer to RF state transition wait

flow.

RX_ON issue*2

[RF_STATUS: B0 0x0B]

From RX flow

Self

No

addressed??

No

FIFO-Full (INT[5]) ?

[INT_SOURCE_GRP1: B0 0x0D(5)]

Yes

TX FIFO write *4

[WR_TX_FIFO:B0 0x7C]

*4 ACK frame is set to TX FIFO.

Yes

Read RX data *3

[RD_FIFO:B0 0x7F]

No

*5 Please refer the following “NOTE”.

RX completion (INT[8])? *5

[INT_SOURCE_GRP2: B0 0x0E(0)]

*3 read address field to

check length and packet

destination.

Yes

CRC error (INT[9])?

[INT_SOURCE_GRP2] B0 0x0E(1)]

*6 Please refer to RF state

No

transition wait flow.

TX_ON issue *6

[RF_STATUS: B0 0x0B]

INT[8] and [9] clear

[INT_SOURCE_GRP2: B0 0x0E((1-0)]

No

TX completion (INT[16])?

[INT_SOURCE_GRP3: B0 0x0F(0)]

Clear TX FIFO pointer

[STATE_CLR: B0 0x16(0)]

Yes

TRX_OFF issue

[RF_STATUS: B0 0x0B]

Yes

RX data read?

No

Clear RX FIFO pointer

[STATE_CLR: B0 0x16(1)]

Read all RX data

[RD_FIFO: B0 0x7F]

END

112/230

FEDL7406-06

ML7406

(Note)

If setting “FAST_TX_EB=0b1” or “AUTO_TX_EN=0b1 or “RXDONE_MODE[1:0]=0b01 (move to TX state)” at the

[RF_STATUS:CTRL:B0 0x0A] register, moving to TX_ON state automatically after RX completion in above flowchart.

Even if CRC error occurs, moving to TX_ON state. Since CRC errors interrupt (INT[9] group2) and RX completion

interrupt (INT[8] group2) occur almost same timeing, Therefore in case of CRC error interrupt occurs, Force_TRX_OFF

should be issued by [RF_STATUS:B0 0x0B] register withing the transition time from RX state to TX state(1.188msec), and

clear TX FIFO pointer by [STATE_CLR:B0 0x16] register. When it is hard to issue Force_TRX_OFF during the trasition

time due to MCU performance, “FAST_TX”, “AUTO_TX” and “move to TX state after RX completion” should be disabled.

(In “FAST_TX”, trnasmitting conditoin depends on [TXFIFO_THRL:B0 0x18] register.)

(5) Field checking

After enabling Filedcheck functions, issuing RX_ON by [RF_STATU:B0 0x0B] register. According to the setting of

CA_INT_CTRL ([C_CHECK_CTRL:B0 0x1B(6)], filed checking result (match or no match) can be notified by the interrupt

INT[14](gropup2: Filed checking interrupt). Numbers of unmatched packets can be counted and stored into

[ADDR_CHK_CTR_H/L: B1 0x62/0x63]) registers. This counter can be cleared by STATE_CLR4[STATE_CLR: B0

0x16(4)](Address check counter clear).

START

*1 C-field/M-field/A-field check can be possible with the setting

below.

Field check setting *1

[C_CHECK_CTRL: B0 0x1B]

[M_CHECK_CTRL: B0 0x1C]

[A_CHECK_CTRL: B0 0x1D]

[C_FIELD_WORD1-5: B0 0x1E-0x22]

[M_FIELD_WORD1-4: B0 0x21-0x26]

[A_FIELD_WORD1-6: B0 0x27-0x2C]

RX_ON issue

[RF_STATUS] B0 0x0B]

No

Field checking complete (INT[14])?

[INT_SOURCE_GRP2: B0 0x0E(6)]

Yes

INT[14] clear

[INT_SOURCE_GRP2: B0 0x0E]

No

RX data read?

Yes

RX flow

No

RX completion (INT[8])?

[INT_SOURCE_GRP2] B0 0x0E(0)]

Yes

*2 Clear all remaining interrupt in the

group 2

INT GRP2 clear *1

[INT_SOURCE_GRP2: B0 0x0E]

113/230

FEDL7406-06

ML7406

(6) CCA

○Normal mode

After setting CCA_EN([CCA_CTRL: B0 0x39(4)])=0b1, issuing RX_ON by [RF_STATU:B0 0x0B] register. Comparing

aquired ED average value with CCA threshold value in [CCA_LVL: B0 0x37] register and noitce the result. After CCA

execulation,CCA_EN is turned disable and RF maintaind RX_ON.

Even if set CCA_EN=0b1 in the RX_ON state, CCA execulation is possible. CCA execulation is also possible during

diversity. In this case, after CCA completion, diversity will be resumed automatically.

START

CCA_EN setting

[CCA_CTRL: B0 0x39(4)]

RX_ON issue *1

[RF_STATUS: B0 0x0B]

*1 CCA start

No

CCA completion (INT[18]) ?

[INT_SOURCE_GRP3: B0 0x0F(2)]

Yes

Read CCA result

CCA_EN setting

[CCA_CTRL: B0 0x39(1-0)]

[CCA_CTRL: B0 0x39]

INT[18] clear

[INT_SOURCE_GRP3: B0 0x0F(2)]

No

Discontinue CCA ?

Yes

TRX_OFF issue

[RF_STATUS: B0 0x0B]

END

114/230

FEDL7406-06

ML7406

○Continuous mode

Continuous CCA mode is executed by issuing RX_ON by [RF_STATU:B0 0x0B] register after setting

CCA_EN([CCA_CTRL: B0 0x39(4)])=0b1 and CCA_CPU_EN([CCA_CTRL: B0 0x39(5)])=0b1. In this mode, CCA

continues until CCA_STOP([CCA_CTRL: B0 0x39(7)])=0b1 is set. CCA completion interupt (INT[18]: group3) is not

generated. During CCA execution,CCA_RSLT([CCA_CTRL: B0 0x39(1-0)]), [CCA_PROG_L: B0 0x3E],

[CCA_PROG_H: B0 0x3D] are constantly updated. The value will be kept by setting CCA_STOP([CCA_CTRL: B0

0x39(7)])=0b1.

START

*1 CCA_IDLE_EN should be 0b0

CCA_CPU_EN setting *1

CCA_EN setting

[CCA_CTRL: B0 0x39(6-4)]

RX_ON issue *2

[RF_STATUS: B0 0x0B]

*2 CCA start

No

*3 RF state transition (RX_ON) completion

can be confirmed by [RF_STATU:B0

0x0B] = 0x66

RX_ON completion (INT[3]) ? *3

[INT_SOURCE_GRP1: B0 0x0D(3)]

Yes

*4 ()CCA result before RX_ON are invalid.

Please read the value after RX_ON and ED

value calculation flag is valid.

ED_DONE=0b1 ? *4

[ED_CTRL: B0 0x41(4)]

Yes

Read CCA result *5

CCA_RSLT[1:0] [CCA_CTRL: B0 0x39(1-0)]

CCA_PROG[9:0]

*5 CCA result can be read after

CCA_STOP execution.

[CCA_PROG_H/L: B0 0x3D,3E]

No

Stop CCA ?

Yes

CCA_STOP setting *6

*6 CCA stop

[CCA_CTRL: B0 0x39(7)]

TRX_OFF issue

[RF_STATUS: B0 0x0B]

END

115/230

FEDL7406-06

ML7406

○IDLE detection mode

CCA is continuously executed untill IDLE is detected. CCA (IDLE detection mode) will be executing by issuing RX_ON

by [RF_STATU:B0 0x0B] register after setting CCA_EN([CCA_CTRL: B0 0x39(4)])=0b1, CCA_IDLE_EN

([CCA_CTRL: B0 0x39(6)])=0b1.

START

*1 CCA_CPU_EN should be 0b0

CCA_IDLE_EN setting *1

CCA_EN setting

[CCA_CTRL: B0 0x39(6-4)]

RX_ON issue

[RF_STATUS: B0 0x0B]

No

CCA completion (INT[18])?

[INT_SOURCE_GRP3: B0 0x0F(2)]

Yes: IDLE detection

Yes

INT[18] clear

[INT_SOURCE_GRP3: B0 0x0F(2)]

END

116/230

FEDL7406-06

ML7406

(7) High speed carrier checking mode

This mode is used for deciding whether continuing RX state or stoping RX state during RX state, based on RSSI level and

SyncWord detection time. The value set in the [CCA_LVL:B0 0x37] register is used for RSSI level decision, continuous

operation timer is used for SyncWord detection time decision. After decision, operation will automaticall switch to – either

SLEEP state or RX state.

START

CCA threshold setting

[CCA_LVL:B0 0x37]

Continuous operation timer setting

[WUT_CLK_SET:B0 0x2E]

[WUT_DURATION:B0 0x31]

FAST_DET_MODE_EN setting

CCA_EN setting

[CCA_CTRL:B0 0x39(4-3)]

*1 CCA start

RX_ON issue *1

[RF_STATUS: B0 0x0B]

No: detection

Carrier detected?

(Automatic)

Yes: BUSY detection

Keep RX state

No *2

*2: Expiring the continuous

operation timer

SyncWord detection?

Yes

SLEEP command

(Automatic)

SLEEP state

Receive RX data

END

117/230

FEDL7406-06

ML7406

(8) ED-SCAN

ED value will be automatically acquired by issuing RX_ON by [RF_STATU:B0 0x0B] register after setting

ED_CALC_EN ([ED_CTRL: B0 0x41(7)])=0b1. . ED value is constantly updated when ED_RSLT_SET([ED_CTRL:B0

0x41(3)] )=0b0.

START

ED calculations enable setting

ED values will be acquired by enabling

ED calculation after RX_ON issue,

ED value constantly updated setting

[ED_CTRL: B0 0x41(7,3)]

RX_ON issue

[RF_STATUS:B0 0x0B]

ED value calculation

completion ?

No

[ED_CTRL:B0 0x41(4)]

Yes

ED values will be constantly updated.

Read ED value

[ED_RSLT:B0 0x3A]

Yes

Channel change ?

No

RF channel change

[CH_SET:B0 0x09]

TRX_OFF issue

[RF_STATUS:B0 0x0B]

General purpose timer start

[GT_SET:B0 0x32]

To RF state transition wait flow

No

General Timer INT ?

[INT_SOURCE_GRP3:B0 0x0F]

INT[22]/INT[23]

Yes

General timer INT clear

[INT_SOURCE_GRP3:B0 0x0F]

INT[22]/INT[23]

These processes are not necessary if 250μs

wait is added after RF channel change setting.

(*1)

(*1) general purpose timer setting example

If 250μs wait is programmed using general purpose timer 1,

The following registers can be used.

[GT_CLK_SET:B0 0x33] =0x01(128 division)

[GT_INTERVAL1:B0 0x34] =0x04(timer setting)

[GT_SET:B0 0x32] =0x03(2MHz clock, timer start)

118/230

FEDL7406-06

ML7406

(9) Antenna diversity

After setting 2DIV_EN([2DIV_CTRL:B0 0x48(0)])=0b1,issuing RX_ON by [RF_STATU:B0 0x0B] register. Antennas are

switched to acquire each ED value, the antenna with higher ED value will be automatically selected.

ED values ([ANT1_ED: B0 0x4A/ANT2_ED: B0 0x4B]) from diversity antennas and 2DIV_RSLT ([2DIV_RSLT: B0

0x49(1-0)]) will be updated, upon SyncWord detection. If Diversity detection completion interrupt

-

INT[10]( [INT_SOURCE_GRP2: B0x0E(2)]) is cleared, ED values - ([ANT1_ED: B0 0x4A/ANT2_ED: B0 0x4B]) by

diversity and diversity antenna result -2DIV_RSLT([2DIV_RSLT: B0 0x49(1-0)]) will be cleared.

START

2 diversity setting

[2DIV_CTRL: B0x48(0)]

RX_ON issue

[RF_STATUS: B0x0B]

No

RX completion (INT[8])?

[INT_SOURCE_GRP2: B0x0E(0)]

Yes

Each antenna ED value acquisition

[ANT1_ED: B0 0x4A/

ANT2_ED: B0 0x4B]

Diversity result acquisition

[2DIV_RSLT: B0 0x49(1-0)

INT[8] and INT[10] clear

[INT_SOURCE_GRP2: B0x0E(2,0)]

()

Yes

Next packet received?

No

TRX_OFF issue

[RF_STATUS: B0 0x0B]

END

119/230

FEDL7406-06

ML7406

●SLEEP Sequence

(1) SLEEP

SLEEP can be executed by setting SLEEP_EN([SLEEP/WU_SET:B0 0x2D(0)])=0b1. SLEEP can be released by setting

SLEEP_EN=0b0. If VCO calibration automatic execution setting AUTO_VCOCAL_EN([VCO_CAL_START:B0 0x6F

(4)])=0b1, VCO calibration is performed after clock stabilization completion interrupt (INT[0] group1) from SLEEP release.

START

SLEEP state

[SLEEP/WU_SET:B0 0x2D]

No

SLEEP released?

Yes

SLEEP released

[SLEEP/WU_SET: B0 0x2D]

No

Clock stabilization completion INT?

[INT_SOURCE_GRP1:B0 0x0D]

INT[0]

Yes

Automatic VCO calibration?

[VCO_CAL_START:B0 0x6F(4)]

No

Yes

VCO calibration

Completion INT[1]?

[INT_SOURCE_GRP1:B0 0x0D]

INT[1]

No

Yes

END

120/230

FEDL7406-06

ML7406

(2) Wake-up timer

By setting the following registers, after SLEEP, automatically wake-up to RX_ON state.

If SyncWord is detected before continuous operation timer-up, RX_ON will be continued to receive a packet. After

receiving RX completion interrupt(INT[8]: group2), by reading INT group2, MCU can determine read RX data or not. In

order to re-enter SLEEP state, executing SLEEP command after clearing all interrupts in INT group2. If generating Sync

error interrupt(INT[15]: group2), executing SLEEP command after clearing RX_FIFO and INT group2.

If SyncWord cannot be detected, automatically go back to SLEEP state after continuous operation timer-up.

Wake-up timer setting

WAKEUP_EN([SLEEP_SET:B0 0x2D(4)]) =0b1

RX_DURATION_EN([SLEEP_SET:B0 0x2D(5)])=0b1

WAKEUP_MODE([SLEEP_SET:B0 0x2D(6)])=0b0

[WUT_CLK_SET:B0 0x2E]

[WUT_INTERVAL_H:B0 0x2F]

[WUT_INTERVAL_L:B0 0x30]

[RX_DURATION:B0 0x31]

Field check function setting

*1 At lease following 2 interrupts in the group 2

[C_CHECK_CTR:B0 0x1B]

START *1

should be un-masked for data receiving.

INT[8]: RX completion interrupt

INT[15]: Sync error interrupt

[M_CHECK_CTRL:B0 0x1C]

[A_CHECK_CTRL:B0 0x1D]

[C_FIELD_WORD1:B0 0x1E] to

[C_FIELD_WORD5:B0 0x22]

[M_FIELD_WORD1:B0 0x23] to

[M_FIELD_WORD4:B0 0x26]

[A_FIELD_WORD1:B0 0x27] to

[A_FIELD_WORD6:B0 0x2C]

SLEEP execution

[SLEEP/WU_SET:B0 0x2D(0)]

Sync error (INT[15])?

No

RX completion (INT[8])?

[INT_SOURCE_GRP2:B0 0x0E(0)]

No

[INT_SOURCE_GRP2:B0 0x0E(7)]

Yes

Read

INT_SOURCE_GRP2

Field checking (INT[14])?

[INT_SOURCE_GRP2:B0 0x0E(6)]

No

Yes

RX FIFO clear

[STATE_CLR:B0 0x16(1)]

Read all RX data from RX FIFO

[]RD_FIFO:B0 0x7F

Clear INT GRP2

[INT_SOURCE_GRP2:B0 0x0E]

SLEEP execution

[SLEEP/WU_SET:B0 0x2D(0)]

No

Wake-up timer OFF?

Yes

Wake-up timer OFF

[SLEEP_SET:B0 0x2D(4)]

END

121/230

FEDL7406-06

ML7406

●Error Process

(1) Sync error

When out-of-sync is detected during data reception after SyncWord detection, Sync error interrupt (INT[15] group2) will be

generated, RX completion interrupt (INT[8]: group2) will not be generated. If Sync error interrupt occurs, issuing

STATE_CLR1 [STATE_CLR: B0 0x16(1)](RX FIFO pointer clear) without read RX_FIFO data and clear Sync error interrupt.

”data reception” indicates receiving data (L-field, data, CRC). after SyncWord detection.

START

*1 At lease following 2 interrupts in the group 2

should be un-masked for data receiving.

RX_ON issue *1

[RF_STATUS:B0 0x0B]

INT[8]: RX completion interrupt

INT[15]: Sync error interrupt

Out-of-Sync detection

No

Sync Word error (INT[15])?

[INT_SOURCE_GRP2:B0

0x0D(7)] )

Yes

Normal reception

(To RX flow)

Clear RX FIFO

[STATE_CLR:B0 0x16(1)]

INT[15] clear

[INT_SOURCE_GRP2:B0 0x0E]

Yes

Next packet to be received?

No

TRX_OFF issue

[RF_STATUS:B0 0x0B]

RF state transition wait flow

122/230

FEDL7406-06

ML7406

(Note)

When Sync error is detected in FIFO mode, the packet is decided as invalid, and ML7406 stops to write received data to FIFO

and clears reception FIFO control information (the number of the received data, the number of FIFO read). If FIFO is read in

this state, it shows invalid FIFO consumption and reception FIFO access error because FIFO is read in case of no received data.

In order to receicve the next packet normally, it is needed to execute Receiption FIFO Clear ([STATE_CLR:B0 0x16]) and reset

Reception FIFO access error interrupt (INT[12]) before starting the reception.

In case of Sync error, the state of RF continues RXON and becomes the SyncWord detection wait state for the next packet

reception from the notice of Sync error. In addition, it is needed to execute Reception FIFO Clear ([STATE_CLR:B0 0x16]) and

Reception-related interrupt Clear ([INT_SOURCE_GRP2:B0 0x0E]) .

An internal state by the FIFO control at the time of the Sync error and the necessary processing for the next packet reception are

as follows.

Processing FIFO after

SyncWord detection

until Sync error

FIFO processing after

the Sync error

Processing for the next packet

reception

Internal state

No need to read FIFO

No need to read FIFO If no data is read before Sync error It can read the next packet without

is detected, the FIFO read pointer

keeps the initial state.

the Reception FIFO Clear normally.

In orer to enable an interrupt

notification for reception, please

execute the Rception-related

interrupt Clear

([INT_SOURCE_GRP2:B0 0x0E]).

Need to read FIFO

The FIFO read pointer, which is

Because it is necessary to initialize

read until Sync error is detected, is FIFO read pointer to read next

not initialized.

packet data normally, please

execute the Reception FIFO clear

([STATE_CLR:B0 0x16]). And

please execute the

Reception-related intrrupt Clear

([INT_SOURCE_GRP2:B0 0x0E])

to enable interrupt notices for the

reception.

Need to read FIFO

No need to read FIFO It shows invalid information of the

number of data and access error of

FIFO because FIFO is read in case

of no received data.

The FIFO read pointer is not

initialized.

Need to read FIFO

123/230

FEDL7406-06

ML7406

(2) TX FIFO access error

If one of the following conditions is met, TX FIFO access error interrupt (INT[20]: group3) will be generated.

●After TX Data request accept completion interrupt (INT[17]: group3] was generated, next packet is written to the

TX_FIFO without transmiting the current TX data.

●Data write overflow occurs to the TX_FIFO.

●No TX data in the TX_FIFO during TX data transimission.

When TX FIFO acccess error interrupt occurs, issuing TRX_OFF after TX completion interrupt(INT[16]: group3) is

recognized, or issueing Force_TRX_OFF by [RF_STATUS:B0 0x0B] register without waiting for TX completion interrupt.

After that, issuing TX FIFO pointer clear by [STATE_CLR:B0 0x16] register and clear remaining interrupts relative with TX

in the [INT_SOURCE_GRP3:B0 0x0F] register.

If TX FIFO access error occurs, subquent TX data will be inverted. CRC error should be detected at rexeiver side even if

TRX_OFF is issued when TX completion interrupt detected.

START

FAST_TX setting

[RF_STATUS_CTRL:B0 0x0A]

[TXFIFO_THRH/L:B0 0x17/18]

*1 If data written to FIFO exceed THFIFO_THRL[5:0]

Write TX data *1

[TXFIFO_THRL:B0 0x18(5-0)]+1, ()TX will start.

(Length is included in the data length written to

FIFO)

[WR_TX_FIFO:B0 0x7C]

No

TX FIFO access error (INT[20])?

[NT_SOURCE_GRP3:B0 0x0F(4)]

Yes

Normal TX

(To TX flowchart)

Yes

Forced to stop TX ?

No

TX completion (INT[16]) ?

[INT_SOURCE_GRP3:B0 0x0F(0)]

Force_TRX_OFF issue

[RF_STATUS:B0 0x0B]

Yes

TRX_OFF issue

[RF_STATUS:B0 0x0B]

TX FIFO pointer clear

[STATE_CLR:B0 0x16(0)]

Clear INT GRP3

INT[16]-[20]

[INT_SOURCE_GRP3:B0 0x0F]

Yes

Next packet TX ?

No

RF state transition wait flow

124/230

FEDL7406-06

ML7406

(3) RX FIFO access error

If one of the following conditions is met, RX FIFO access error interrupt (INT[12]: group2) will be generated.

●RX data overflow occurs to RX_FIFO

●Read RX_FIFO during no data in the RX_FIFO

When RX FIFO acccess error interrupt occurs, issuing TRX_OFF after RX completion interrupt (INT[8]: group2) is

recognized, or issueing Force_TRX_OFF by [RF_STATUS:B0 0x0B] register without waiting for RX completion interrupt.

After that, issuing RX FIFO pointer clear by [STATE_CLR:B0 0x16] register and clear remaining interrupts in the

[INT_SOURCE_GRP2:B0 0x0E] register.

START

RX_ON issue

[RF_STATUS: B0 0x0B]

No

RX FIFO access error (INT[12])?

[NT_SOURCE_GRP2:B0 0x0E(4)]

Yes

Normal RX

(To RX flowchart)

Yes

Forced to stop RX ?

No

TX completion (INT[8]) ?

[INT_SOURCE_GRP2:B0 0x0E(0)]

Force_TRX_OFF issue

[RF_STATUS:B0 0x0B]

Yes

TRX_OFF issue

[RF_STATUS:B0 0x0B]

RX FIFO pointer clear

[STATE_CLR:B0 0x16(1)]

Clear INT GRP2

[INT_SOURCE_GRP2:B0 0x0E]

Yes

Next packet to be received?

No

RF state transition wait flow

125/230

FEDL7406-06

ML7406

(4) PLL unlock detection

○ TX

During TX, if PLL unlock is detected, PLL unlock interrupt (INT[2] group1) will be generated. When PLL unlock

interrupt occurs, Force_TRX_OFF is automaticcally issued and move to IDLE state. SET_TRX[3:0] ([RF_STATUS: B0

0x0B(3-0)]) will be written to 0b0011(Force_TRX_OFF). PLL unlock might be occurred when VCO calibration value is

not correct. Please confirm VCO calibration or perform VCOcalibration again.

After PLL unlock interrupt occurs, max. 147 μs is necessary to move to IDLE state. Please wait for at least 147μs before

next TX, RX or VCO calibration is performed.

START

Write TX data

[WR_TX_FIFO:B0 0x7C]

TX_ON issue

[RF_STATUS:B0 0x0B]

No

PLL unlock (INT[12])?

[INT_SOURCE_GRP1:B0 0x0D(2)]

Normal TX

(To TX flowchart)

Yes

*

Force_TRX_OFF is

issued automatically.

INT[12] clear

[INT_SOURCE_GRP1:B0 0x0D(2)]

Wait TRX_OFF(IDLE)

(147μsec)

Yes

Next packet TX?

No

END

126/230

FEDL7406-06

ML7406

○ RX

During RX, if PLL unlock is detected, PLL unlock interrupt (INT[2] group1) will be generated. During RX, even if PLL

unlock is detected, RX state is maintained (do not move to IDLE state). Please receive next packet after clearing PLL

unlock interrupt.

When PLL unlock interrupt occurs frequently, PLL unlock cause mitgh be due to the mismatch of the VCO circuit and

using frequency band. Please use after removing the cause by circuit verification.

START

RX_ON issue

[RF_STATUS:B0 0x0B]

No

PLL unlock (INT[2])?

[INT_SOURCE_GRP1:B0 0x0D(2)]

Normal RX

(To RX flowchart)

Yes

INT[2] clear

[INT_SOURCE_GRP1:B0 0x0D(2)]

Yes

Next packet to be received?

No

Force_TRX_OFF issue

[RF_STATUS:B0 0x0B]

END

127/230

FEDL7406-06

ML7406

●Data Rate Change Sequence

When changing data rate during operation, data rate should be set in TRX_OFF state. RST1([RST_SET: B0

0x01(1)])(MODEM reset) is required after change. If not issuing RST1, ML7406 can not transmit or receive correctlly.

START

*1

*1 TX_ON or RX_ON state

TRX_OFF issue

[RF_STATUS:B0 0x0B]

*2 Relating registers

Change Data Rate

*2

refer to “Data rate setting function”

RST1

[RST_SET:B0 0x01(1)]

END

128/230

FEDL7406-06

ML7406

■Timing Chart

The following are operation timing for major functions.

(Note)

Bold characters indicate pins related signals. Non bold characters indicate internal signals.

●Start-up

[ML7406C]

Regulator voltage wake up time

VDD

150ms *1

RESETN

OSC/Reg enable

Clock stabilization time

INT[0](CLK stabilized)

[INT_SOURCE_GRP1: B0 0x0D]

300 to 500μs *2

625μs *3

RF operation wait

completion

All BANK& FIFO

Access possible

SPI access

prohibited (*4)

RF operation

possible

[ML7406T]

Regulator voltage wake up time

VDD

150ms *1

RESETN

INT_EN[0]([INT_EN0: B0 0x10(0)])=0b1

TCXO_EN([CLK_SET2: B0 0x03(6)])=0b1

SCEN

Clock stabilization time

5.5μs *2

INT[0]

(CLK stabilized completion)

[INT_SOURCE_GRP1: B0 0x0D]

625μs *3

RF operation wait

completion

GPIO0

(Reset State:

interrupt indication)

SPI acces

prohibited (*5)

All BANK&FIFO

Access possible

SPI access

prohibited

RF operation

possible

SPI Access

possible

*1 : For wake-up timing of VDD and RESETN, please refer to the “Reset characteristics”.

*2 : When setting XTAL_EN([CLK_SET2: B0 0x03(4)])=0b1, it is possible to adjust to 10/50/250/500μs, by setting

OSC_W_SEL[1:0]( [ADC_CLK_SET: B1 0x08(6-5)]). When setting TCXO_EN([CLK_SET2: B0 0x03(6)])=0b1, clock

stabilization is 5.5us. In use of crystal oscillator circuit, clock stabilization time is about 300 to 500μs. This time changes by

the matching condition(component values, etc) for crystal oscillator circuit.

129/230

FEDL7406-06

ML7406

*3 : [VCO_CAL_START:B0 0x6F] and [RF_STATUS:B0 0x0B] resister access is possible, but process is pending until RF

operation wait completion signal is asserted.

*4 : In case of ML7406C, after hardware reset is released, all register access and FIFO access (**) is prohibited until INT[0]

occurrence.

(**) FIFO access: Accessing [WR_TX_FIFO: B0 0x7C] and [RD_FIFO: B0 0x7F] registers.

*5 : In case of ML7406T, after hard reset is released, set 0b1 to TCXO_EN [CLK_SET2:B0 0x03(6)] at first. All register

access and FIFO access (**) is prohibited until INT[0] occurrence.

(**) FIFO access: Accessing [WR_TX_FIFO: B0 0x7C] and [RD_FIFO: B0 0x7F] registers.

130/230

FEDL7406-06

ML7406

●TX

TX_ON

command

INT[3]

command

clear

FIFO write

SCEN

TX completion interrupt *1

SET_TRX[3:0]

[RF_STATUS: B0 0x0B]

0x8(TRX_OFF)

0x9(TX_ON)

210μs

147μs

GET_TRX[3:0]

[RF_STATUS: B0 0x0B]

0x8(TRX_OFF)

0x9(TX_ON)

0x8(TRX_OFF)

75μs

144μs

TX_ON

PA_ON

75μs

143μs

Data TX time *2

Air

INT[17]

(TX Data request accept completion)

[INT_SOURCE_GRP3: B0 0x0F]

INT[3]

(RF state transition completion)

[INT_SOURCE_GRP1: B0 0x0D]

INT[16]

(TX completion)

[INT_SOURCE_GRP3: B0 0x0F]

DCLK output (*3)

0.4 bit time

(at 100kbps, 4μs)

*1 : When TXDONE_MODE[1:0]([RF_STATUS_CTRL: B0 0x0A(1-0)]) = 0b00(default), SET_TRX[3:0]([RF_STATUS:

B0 0x0B(3-0)]) will be set to 0x8(TRX_OFF) automatically, upon detection of TX completion.

*2 : Data TX time calculation is as follows:

Data TX time [sec] = (number of TX bits+3)×1bit TX duration time[sec]

1bit TX duration time [sec] = 1/data rate [bps]

*3 : When setting TXDIO_CTRL[1:0]([DIO_SET: B0 0x0C(5-4)])=0b01.

131/230

FEDL7406-06

ML7406

●RX

DIO data output command

(When DIO function is used)

INT[3]clear

command

RX_ON

TRX_OFF

command

SCEN

SET_TRX[3:0]

0x6(RX_ON)

0x8(TRX_OFF)

[RF_STATUS: B0 0x0B]

4μs

119μs

GET_TRX[3:0]

[RF_STATUS: B0 0x0B]

0x8(TRX_OFF)

0x6(RX_ON)

RX enable

Sync

Word

PB

Length

Data CRC

Demod data

INT[3](RF state transition completion )

[INT_SOURCE_GRP1: B0 0x0D]

INT[13] (SyncWord detection)

[INT_SOURCE_GRP2: B0 0x0E]

INT[8] (RX completion)

[INT_SOURCE_GRP2: B0 0x0E]

DCLK output (*1)

1 to 2 bit time

(at 100kbps , 10 to 20µs)

*1 : When setting RXDIO_CTRL[1:0]([DIO_SET: B0 0x0C(7-6)])=0b10 or 0b11.

132/230

FEDL7406-06

ML7406

●Transtion from TX to RX

SET_TRX[3:0]

0x6(RX_ON)

0x9(TX_ON)

[RF_STATU: B0 0x0B]

244μs

GET_TRX[3:0]

[RF_STATUS: B0 0x0B]

0x9(TX_ON)

INT[3] (RF state transition completion)

[INT_SOURCE_GRP1: B0 0x0D]

PA_ON

143μs

●Transtion from RX to TX

SET_TRX[3:0]

0x9(TX_ON)

0x6(RX_ON)

[RF_STATUS: B0 0x0B]

192μs

GET_TRX[3:0]

[RF_STATUS: B0 0x0B]

0x6(RX_ON)

INT[3] (RF state transition completion)

[INT_SOURCE_GRP1: B0 0x0D]

57μs

PA_ON

133/230

FEDL7406-06

ML7406

●Transtion from IDLE to SLEEP

SLEEP

command

SLEEP_EN

[SLEEPWU_SET: B0 0x2D]

By SLEEP_EN=0b1,

automatic switching

SET_TRX[3:0]

[RF_STATUS: B0 0x0B]

0x3(Force_TRX_OFF)

0x8(TRX_OFF)

GET_TRX[3:0]

[RF_STATUS: B0 0x0B]

0x8(TRX_OFF)

SLEEP transition time *1

OSC/Reg enable

0.3μs

CLK_INIT_DONE

[CLK_SET: B0 0x02]

*1 : Clock input should be required for SLEEP transition. If TCXO is stopped during SLEEP state, please wait 0.3μs after

SLEEP command issued (SLEEP_EN([SLEEP/WU_SET: B0 0x2D(0)])=0b1) and then stop TCXO.

●Transtion from TX/RX state to SLEEP

SLEEP

command

SLEEP_EN

[SLEEPWU_SET: B0 0x2D]

By SLEEP_EN=0b1,

automatic switching

SET_TRX[3:0]

[RF_STATUS: B0 0x0B]

0x6(RX_ON)

0x9(TX_ON)

0x3(Force_TRX_OFF)

From RX_ON:4μs

From TX_ON:147μs

0x6(RX_ON)

0x9(TX_ON)

GET_TRX[3:0]

[RF_STATUS: B0 0x0B]

0x8(TRX_OFF)

1μs

INT[3] (RF state transition completion)

[INT_SOURCE_GRP1: B0 0x0D]

Time required from INT[3] to SLEEP *1

OSC/Reg enable

1.3μs

CLK_INIT_DONE

[CLK_SET: B0 0x02]

*1 : If TCXO is used, , please stop TCXO(clock) input after1.3μs from INT[3] notification by setting SLEEP command

(SLEEP_EN([SLEEP/WU_SET: B0 0x2D(0)])=0b1) .

134/230

FEDL7406-06

ML7406

●Transition from SLEEP to IDLE

SLEEP_EN=0b0

setting

SLEEP_EN

[SLEEPWU_SET: B0 0x2D]

OSC/Reg enable

Clock stabilization time

INT[0] (CLK stabilized complete)

[INT_SOURCE_GRP1: B0 0x0D]

50μs +α *1

Regulator stabilization time

1125μs *2

RF operation wait

completion

Sleep mode1: Register access possible

Sleep mode2: Register & FIFO access possible

Registers and FIFOs

access possible

RFoperation

possible

*1: When setting XTAL_EN([CLK_SET2: B0 0x03(4)])=0b1, it is possible to adjust to 10/50/250/500μs , by setting

[ADC_CLK_SET: B1 0x08(6-5)]. α is oscillation cuircuits start-up time, and max. is 500μs.

When using TCXO (TCXO_EN([CLK_SET2:B0 0x03(6)])=0b1), clock stabilization time is 5μs.

*2: [VCO_CAL_START:B0 0x6F] and [SET_TRX:B0 0x0B] registers access is possible, but process is pending until RF

operation wait completion is asserted.

135/230

FEDL7406-06

ML7406

●High speed carrier checking mode

RX_ON

command

INT[3] clear

command

SCEN

SET_TRX[3:0]

0x6(RX_ON)

0x8(TRX_OFF)

[RF_STATUS: B0 0x0B]

4μs

119μs

GET_TRX[3:0]

[RF_STATUS: B0 0x0B]

0x8(TRX_OFF)

0x6(RX_ON)

128μs

CCA on-going flag

1μs

INT[3] (RF state transition completion)

[INT_SOURCE_GRP1: B0 0x0D]

1.3μs (*1)

SLEEP flag

*1: Clock input should be required for SLEEP transition. If TCXO is stopped during SLEEP state, please wait 1.3μs from

INT[3] and then stop TCXO.

136/230

FEDL7406-06

ML7406

■Registers

●Registers map

Addressing range for each register BANK are 0x00-0x7F(128 bytes). Grey colours in the table are unused bits or reserved

bits . Please use the initial setting value, as reserved bits may be used for functions not open to the customers. It may cause

unexpected operation.

Each BANK can be selected by [BANK_SEL] register (B0 0x00, B1 0x00, B2 0x00, B3 0x00), enabling each bank in bit7-4

(B*_ACEN) and specified BANK number to bit3-0.

If registers value is specified in the description, do not change.

137/230

FEDL7406-06

ML7406

BANK0

bit

address

[HEX]

Register name

BANK_SEL

description

Register access bank selection

7

6

5

4

3

2

1

0

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

RST_SET

Software reset setting

CLK_SET1

Clock cofiguration 1

CLK_SET2

Clock configuration 2

PKT_CTRL1

Packet configuration 1

PKT_CTRL2

Packet configuration 2

DRATE_SET

Data rate setting

DATA_SET1

TX/RX data configulation 1

DATA_SET2

TX/RX data configulation 2

CH_SET

RF channel setting

RF_STATUS_CTRL

RF_STATUS

RFauto status transition control

RFstate setting and status indication

DIO mode configuration

DIO_SET

INT_SOURCE_GRP1

INT_SOURCE_GRP2

INT_SOURCE_GRP3

INT_EN_GRP1

INT_EN_GRP2

INT_EN_GRP3

CRC_ERR_H

Interrupt status for INT0 to INT7

Interrupt status for INT8 to INT15 (RX)

Interrupt statsu for INT16 to INT23 (TX)

Interrupt mask for INT0 to INT7

Interrupt mask for INT8 to INT15

Interrupt mask for INT16 to INT23

CRC error status (high byte)

CRC error status (middle byte)

CRC error status (low byte)

State clear control

CRC_ERR_M

CRC_ERR_L

STATE_CLR

TXFIFO_THRH

TXFIFO_THRL

RXFIFO_THRH

RXFIFO_THRL

C__CHECK_CTRL

M__CHECK_CTRL

A__CHECK_CTRL

C_FIELD_CODE1

C_FIELD_CODE2

C_FIELD_CODE3

C_FIELD_CODE4

C_FIELD_CODE5

M_FIELD_CODE1

M_FIELD_CODE2

M_FIELD_CODE3

M_FIELD_CODE4

A_FIELD_CODE1

A_FIELD_CODE2

A_FIELD_CODE3

A_FIELD_CODE4

A_FIELD_CODE5

A_FIELD_CODE6

SLEEP/WU_SET

WUT_CLK_SET

WUT_INTERVAL_H

WUT_INTERVAL_L

RX_DURATION

GT_SET

TX FIFO-Full level setting

TX FIFO-Emptythreshold, FAST_TXenable thresold

RX FIFO-Full thresold

RX FIFO-Empty threshold

Control field (C-field) detection setting

Manufactute ID field (M-field) detection setting

Address field (A-field) detection setting

C-field setting code #1

C-field setting code #2

C-field setting code #3

C-field setting code #4

C-field setting code #5

M-field 1^stbyte setting code #1

M-field 1^stbyte setting code #2

M-field 2^ndbyte setting code #1

M-field 2^ndbyte setting code #2

A-field 1^stbyte setting

A-field 2^ndbyte setting

A-field 3^rdbyte setting

A-field 4^thbyte setting

A-field 5^thbyte setting

A-field 6^thbyte setting

SLEEP execution and Wake-up operation setting

Wake-up timer clock division setting

Wake-up timer interval setting (high byte)

Wake-up timer interval setting (low byte)

Continue operation timer (after Wake-up) setting

General purpose timer configuration

General purposetimer clock division setting

General purpose timer #1 setting

General purpose timer #2 setting

GT_CLK_SET

GT1_TIMER

GT2_TIMER

138/230

FEDL7406-06

ML7406

bit

address

[HEX]

Register name

description

7

6

5

4

3

2

1

0

36

37

CCA_IGNORE_LVL

CCA_LVL

ED threshold level setting for excluding CCA judgement

CCA threshold level setting

38

CCA_ABORT

CCA_CTRL

Timing setting for forced termination of CCA operation

CCA control setting and result indication

39

3A

3B

3C

3D

3E

3F-40

41

ED_RSLT

ED value indication

IDLE_WAIT_H

IDLE_WAIT_L

CCA_PROG_H

CCA_PROG_L

Reserved

IDLE detection period setting during CCA (high 2 bits)

IDLE detection period setting during CCA (low byte)

IDLE detection elapsed time display (during CCA high byte)

IDLE detection elapsed time display during CCA(low byte)

I

ED_CTRL

ED detection control setting

42

TXPR_LEN_H

TXPR_LEN_L

POSTAMBLE_SET

SYNC_CONDITION1

SYNC_CONDITION2

TX preamble length setting (high byte)

TX preamblelength setting (low byte)

Postamble length and pattern setting

RX preamble setting and ED control setting

ED threshold setting during synchronization

43

44

45

46

Tolerance of bit error setting in RX preamble and SyncWord

detection

47

SYNC_CONDITION3

48

49

2DIV_CTRL

2DIV_RSLT

ANT1_ED

Antenna diversity setting

Antenna diversity result indication

4A

4B

4C

4D

4E

4F

50

ANT1 ED value during antenna diversity

ANT2 ED value during antenna diversity

Antenna control setting for TX, CCA or RX

Monitor function setting

ANT2_ED

ANT_CTRL

MON_CTRL

GPIO0_CTRL

GPIO1_CTRL

GPIO2_CTRL

GPIO3_CTRL

EXTCLK_CTRL

SPI/EXT_PA_CTRL

IF_FREQ_H

IF_FREQ_L

IF_FREQ_CCA_H

IF_FREQ_CCA_L

BPF_ADJ_H

BPF_ADJ_L

Reserved

GPIO0 pin (pin#16) configuration setting

GPIO1 pin (pin#17) configuration setting

GPIO2 pin (pin#18) configuration setting

GPIO3 pin (pin#19) configuration setting

EXT_CLK pin (pin #10) control setting

SPI interface IO configurattion /external PA control setting

IF frequency setting (high byte)

51

52

53

54

55

IF frequency setting (low byte)

56

IF frequency setting during CCA operation (high byte)

IF frequency setting during CCA operation (low byte)

Bandpass filter capacitance adjustment (high 2 bits)

Bandpass filter capacitance adjustment (low byte)

57

58

59

5A-5B

5C

5D

5E

5F

60

BPF_CO

BPF coefficient

BPF_CO_CCA

IFF_ADJ_H

BPFcoefficient (CCA)

Demodulator DC level adjustment (high 2 bits)

Demodulator DC level adjustment (low byte)

Demodulator DC level adjustment during CCA (high 7 bits)

Demodulator DC level adjustment during CCA (low byte)

Coarse adjustment of load capacito for oscillation circuits

Fine adjustment of load capaciatnce for oscillation circuits

Oscillation circuits bias adjustment

IFF_ADJ_L

IFF_ADJ_CCA_H

IFF_ADJ_CCA_L

OSC_ADJ1

61

62

63

OSC_ADJ2

64

OSC_ADJ3

65

OSC_ADJ4

Oscillation circuits bias adjustment (high speed start-up)

RSSI value adjustment

66

RSSI_ADJ

67

PA_MODE

PA mode setting/PA regulator coarse adjustment

PA regulator fine adjustment

68

PA_REG_FINE_ADJ

PA_ADJ

69

PA gain adjustment

6A

6B

6C

6D

Reserved

IQ_MAG_ADJ

IQ_PHASE_ADJ

IF I/Q amplitude balance adjustment

IF I/Q phase balance adjustment

139/230

FEDL7406-06

ML7406

bit

address

[HEX]

Register name

VCO_CAL

description

7

6

5

4

3

2

1

0

6E

6F

70

71

72

73

74

75

76

77

78

79

7A

7B

7C

7D

7E

7F

VCO calibration setting or status indicarion

VCO calibration execution

VCO_CAL_START

CLK_CAL_SET

CLK_CAL_TIME

CLK_CAL_H

Clock calibration setting

Clock calibration time setting

Clock calibration value readout (high byte)

Clock calibration value readout (low byte)

CLK_CAL_L

Reserved

SLEEP_INT_CLR

RF_TEST_MODE

STM_STATE

Interrupt clear setting during SLEEP state

TX test pattern setting

Sate machine status and synchronization status indication

FIFO readout setting

FIFO_SET

RD_FIFO_LAST

TX_PKT_LEN_H

TX_PKT_LEN_L

WR_TX_FIFO

RX_PKT_LEN_H

RX_PKT_LEN_L

RD_FIFO

RX FIFO data usage status indication

TX packet length setting (high byte)

TX packet length setting (low byte)

TX FIFO

RX packet length indication (high byte)

RX packet length indication (low byte)

FIFO read

140/230

FEDL7406-06

ML7406

BANK1

bit

address

[HEX]

Register name

BANK_SEL

description

7

6

5

4

3

2

1

0

00

01

02

03

04

05

06

07

08

09

0A

0B

BANK selection

CLK_OUT

CLK_OUT (GPIOn) output frequency setting

TX data rate conversion setting (high 4 bits)

TX data rate conversion setting (low byte)

RX data rate conversion setting1 (high 4 bits)

RX data rate conversion setting1 (low byte)

RX data rate conversion setting2

TX_RATE_H

TX_RATE_L

RX_RATE1_H

RX_RATE1_L

RX_RATE2

REGULATOR_CTRL

ADC_CLK_SET

TEMP

Regulator control setting

RSSI ADC clock frequency setting

Temperature digital value indication

Reserved

PLL_LOCK_DETECT

PLL lock detection setting

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

GAIN_MTOL

Threshold level setting for switching middle gain to low gain

Threshold level setting for switching low gain to middle gain

Threshold level setting for switching high gain to middle gain

Threshold level setting for switching middle gain to high gain

RSSI offset value setting during middle gain opoeration

RSSI offset value setting during low gain operation

RSSI stabilization wait time setting

GAIN_LTOM

GAIN_HTOM

GAIN_MTOH

RSSI_ADJ_M

RSSI_ADJ_L

RSSI_STABLE_TIME

RSSI_MAG_ADJ

RSSI_VAL

Scale factor setting for ED value conversion

RSSI value indication

AFC/GC_CTRL

CRC_POLY3

AFCcontrol/gain controlmode setting

CRC polynomial setting 3

CRC_POLY2

CRC polynomial setting 2

CRC_POLY1

CRC polynomial setting 1

CRC_POLY0

CRC polynomial setting 0

Reserved

TXFREQ_I

TX frequency setting (I counter)

TXFREQ_FH

TX frequency setting (F counter high 4bit)

TX frequency setting (F counter middle byte)

TX frequency setting (F counter low byte)

RX frequency setting (I counter)

TXFREQ_FM

TXFREQ_FL

RXFREQ_I

RXFREQ_FH

RX frequency setting (F counter high 4bit)

RX frequency setting (F counter middle byte)

RX frequency setting (F counter low byte)

Channel space setting (high byte)

Channel space setting (low byte)

SyncWord lenght setting

RXFREQ_FM

RXFREQ_FL

CH_SPACE_H

CH_SPACE_L

SYNC_WORD_LEN

SYNC_WORD_EN

SYNCWORD1_SET0

SYNCWORD1_SET1

SYNCWORD1_SET2

SYNCWORD1_SET3

SYNCWORD2_SET0

SYNCWORD2_SET1

SYNCWORD2_SET2

SYNCWORD2_SET3

FSK_CTRL

SyncWord enable setting

SyncWord #1 setting (bit24-31)

SyncWord #1 setting (bit16-23)

SyncWord #1 setting (bit8-15)

SyncWord #1 setting (bit0-7)

SyncWord #2 setting (bit24-31)

SyncWord #2 setting (bit16-23)

SyncWord #2 setting (bit8-15)

SyncWord #2 setting (bit0-7)

GFSK/FSK mudulation timing resolution setting

GFSK frequency deviation setting (high 6 bits)

GFSK frequency deviation setting (low byte)

GFSK_DEV_H

GFSK_DEV_L

FSK 1^stfrequency deviation setting (high 6 bits) /

Gaussian filter coefficient setting 0

32

33

34

FSK_DEV0_H/GFIL0

FSK_DEV0_L/GFIL1

FSK_DEV1_H/GFIL2

FSK 1^stfrequency deviation setting (low byte) /

Gaussian filter coefficient setting 1

FSK 2^ndfrequency deviation setting (high 6 bits) /

Gaussian filter coefficient setting 2

141/230

FEDL7406-06

ML7406

BANK1(continue)

bit

address

[HEX]

Register name

description

7

6

5

4

3

2

1

0

FSK 2^ndfrequency deviation setting (low byte) /

Gaussian filter coefficient setting 3

35

36

37

38

FSK_DEV1_L/GFIL3

FSK_DEV2_H/GFIL4

FSK_DEV2_L/GFIL5

FSK_DEV3_H/GFIL6

FSK 3^rdfrequency deviation setting (high 6 bits) /

Gaussian filter coefficient setting 4

FSK 3^rdfrequency deviation setting (low byte) /

Gaussian filter coefficient setting 5

FSK 4^thfrequency deviation setting (high 6 bits) /

Gaussian filter coefficient setting 6

39

3A

3B

3C

3D

3E

3F

FSK_DEV3_L

FSK_DEV4_H

FSK_DEV4_L

FSK_TIM_ADJ4

FSK_TIM_ADJ3

FSK_TIM_ADJ2

FSK_TIM_ADJ1

FSK_TIM_ADJ0

Reserved

FSK 4^thfrequency deviation setting (low byte)

FSK 5^thfrequency deviation setting (high 6 bits)

FSK 5^thfrequency deviation setting (low byte)

FSK 4^thfrequency deviation hold timing seting

FSK 3^rdfrequency deviation hold timing seting

FSK 2^ndfrequency deviation hold timing seting

FSK 1^stfrequency deviation hold timing seting

FSK no-deviation frequency (carrier frequency) hold timing seting

40

41-47

48

2DIV_MODE

Antenna diversity mode setting

49

2DIV_SEARCH1

2DIV_SEARCH2

2DIV_FAST_LVL

Reserved

Antenna diversity search time setting 1

4A

4B

4C

4D

4E

Antenna diversity search time setting 2

ED threshold level setting during Antenna diversity FAST mode

VCO_CAL_MIN_I

VCO_CAL_MIN_FH

VCO Calibration low limit frequency setting (I counter)

VCO Calibration low limit frequency setting (F counter high 4 bits)

VCO Calibration low limit frequency setting (F counter middle

byte)

4F

VCO_CAL_MIN_FM

VCO Calibration low limit frequency setting (F counter low byte)

50

51

VCO_CAL_MIN_FL

VCO_CAL_MAX_N

VCAL_MIN

VCO_CAL Max frequency setting

52

VCO calibration low limit value indication and setting

VCO calibration upper limit value indication and setting

53

VCAL_MAX

Reserved

54-55

56

DEMOD_SET0

DEMOD_SET1

DEMOD_SET2

DEMOD_SET3

DEMOD_SET4

DEMOD_SET5

DEMOD_SET6

DEMOD_SET7

DEMOD_SET8

DEMOD_SET9

DEMOD_SET10

DEMOD_SET11

ADDR_CHK_CTR_H

ADDR_CHK_CTR_L

WHT_INIT_H

Demodulator configulation 0

57

Demodulator configulation 1

58

Demodulator configulation 2

59

Demodulator configulation 3

5A

5B

5C

5D

5E

5F

Demodulator configulation 4

Demodulator configulation 5

Demodulator configulation 6

Demodulator configulation 7

Demodulator configulation 8

Demodulator configulation 9

60

Demodulator configulation 10

61

Demodulator configulation 11

62

Address check counter indication (high 3 bit)

Address check counter indication (low byte)

Whitening initializing state setting (high 1bit)

Whiteningi initializing state setting (low 8bit)

Whitening polynomial generation setting

63

64

65

WHT_INIT_L

66

WHT_CFG

Reserved

67-7E

7F

ID_CODE

ID code indication

142/230

FEDL7406-06

ML7406

BANK2

bit

address

[HEX]

Register name

BANK_SEL

description

7

6

5

4

3

2

1

0

00

7E

BANK selection

Filter stabilization setting during CCA

CCA_MASK_SET

BANK3

bit

address

[HEX]

Register name

description

7

6

5

4

3

2

1

0

00

23

BANK_SEL

BANK selection

2MODE_DET

2 modes detection setting (MODE-T and MODE-C)

(Note)

1. Other registers are closed register and access is limited. Accessible registers are written in the “initialization

table”.calibration operation, do not access BANK1 registers.

143/230

FEDL7406-06

ML7406

●Register Bank0

0x00[BANK_SEL]

Function: Register access bank selection

Address:0x00 (BANK0)

Reset value:0x11

Bit

7

Bit name

B3_ACEN

Reset value

0

R/W

description

BANK3 register access enable

0: access disable

1: access enable

BANK2 register access enable

0: access disable

1: access enable

BANK1 register access enable

0: access disable

1: access enable

6

5

4

B2_ACEN

B1_ACEN

B0_ACEN

0

1

R/W

BANK0 register access enable

0: access disable

1: access enable

BANK selection

0b0001: BANK0 access

0b0010: BANK1 access

0b0100: BANK2 access

0b1000: BANK3 access

Other setting: prohibit

3-0 BANK[3:0]

0001

R/W

(Note)

1. During VCOcalibration operation, do not access BANK1 registers.

2. Register acess can be done by CLK_INIT_DONE([CLK_SET1: B0 0x02(7)])=0b0.

But the registers related to RF status has to be accessed after CLK_INIT_DONE=0b1.

144/230

FEDL7406-06

ML7406

0x01[RST_SET]

Function: Software reset setting

Address:0x01 (BANK0)

Reset value:0x00

Bit

7

Bit name

RST3_EN

Reset value

0

R/W

description

Reset3 enable setting

0: reset disable

1: reset enable (after reset, automatically written to 0b0)

Reset2 enable setting

6

5

4

RST2_EN

RST1_EN

RST0_EN

0

R/W

0: reset disable

1: reset enable (after reset, automatically written to 0b0)

Reset1 enable setting

0: reset disable

1: reset enable (after reset, automatically written to 0b0)

Reset 0 enable setting

0: reset disable

1: reset enable (after reset, automatically written to 0b0)

PHY function reset

bit7(RST3_EN)=0b1, reset can be executed.

0: no reset

1: reset execution (after reset, automatically written to 0b0)

RF control function reset

bit6(RST2_EN)=0b1, reset can be executed.

0: no reset

1: reset execution (after reset, automatically written 0b0)

MODEM function reset

bit5(RST1_EN)=0b1, reset can be executed.

0: no reset

3

2

1

RST3

RST2

RST1

0

R/W

1: reset execution (after reset, automatically written to 0b0)

CFG (Configuration) function reset

bit4(RST0_EN)=0b1, reset can be executed.

0: no reset

1: reset execution (after reset, automatically written to 0b0)

0

RST0

0

R/W

(Note) all registers, except [CLK_SET2: B0 0x03] register bit6-3, are reset to

the initial value.

(Note) After reset, FIFO data are not guaranteed.

[Description]

1. Please set enable bit (bit7 to bit4) and execution bit (bit3 to bit0) at the same time. After reset, status are not retained

and automatically writen to 0b0.

2. 2μs after writing to the execution bit (bit3 to bit0), reset operation will complete. However, if executing reset in

SLEEP state (while SLEEP_EN ([SLEEP/WU_SET:B0 0x2D(0)]) =0b1), reset will be executed at Clock

stabilizzation completion interrupt (INT[0] group1) from SLEEP release and each bit turned to 0b0. If chnaging set

value before reset execution, last setting is valid.

145/230

FEDL7406-06

ML7406

0x02[CLK_SET1]

Function: Clock setting

Address:0x02 (BANK0)

Reset value:0x1F

Bit

7

Bit name

CLK_INIT_DONE

Reset value

R/W

R

description

Clock stabilization completion flag

0

6:5 Reserved

00

R/W

ADC clock control

0: clock stop

1: clock enable

RF function (RFstate control) clock control

0: clock stop

1: clock enable

TX function (MOD) clock control

0: clock stop

1: clock enable

RX function(DEMOD) clock control

0: clock stop

1: clock enable

4

3

2

1

0

CLK4_EN

CLK3_EN

CLK2_EN

CLK1_EN

CLK0_EN

1

R/W

PHY function clock control

0: clock stop

1: clock enable

0x03[CLK_SET2]

Function: Clock setting 2

Address:0x03 (BANK0)

Reset value:0x90

Bit

7

Bit name

Reset value

1

R/W

description

Logic block clock enable control

0: disable

MSTR_CLK_EN

1: enable

TCXO input control (1) (2) (3)

0: disable

1: enable

6

5

4

TCXO_EN

Reserved

XTAL_EN

0

1

R/W

Crystal oscillator circuits control (1) (2)

0: disable

1: enable

On-chip RC oscillator circuits control

3

RC32K_EN

0

R/W

0: disable

1: enable

2:0 Reserved

000

(Note)

1. In case of using TCXO, set 0b1 to either TCXO_EN. And one of TCXO_EN, XTAL _EN has to be 0b1.

2. RST0([RST_SET: B0 0x01(0)]) cannot clear these bits. In order to clear, hard reset (RESETN pin=”L”) or clear these

bits through SPI from Host MCU.

3. In case of using TCXO, this register must be programmed first. If other registers are set before programming this

register, values set to other registers are not valid.

4. In case of ML7406C, after hardware reset is released, all register access and FIFO access (**) is prohibited until

INT[0] occurrence.

(**) FIFO access: Accessing [WR_TX_FIFO: B0 0x7C] and [RD_FIFO: B0 0x7F] registers.

146/230

FEDL7406-06

ML7406

0x04[PKT_CTRL1]

Function: Packet configuration 1

Address:0x04 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

R/W

description

Extended Link Layer mode setting (Wireless M-Bus)

00: no Extended Link Layer

01: 2 byte extension (Extended Link Layer CI=0x8C)

10: 8 byte extension (Extended Link Layer CI=0x8D)

11: Reserved

Please refer to the “Packet Format”

(Note)

7:6 EXT_PKT_MODE[1:0]

00

When packet format setting is Format A and packet expansion mode is set

by 0b10, it cannot transmit and receive data properly with the Length

value meeting the following condition.

So please use the Length value where the following condition is not met.

(condition) a surplus of "(length -15)/16" becomes "0"

Length area bit order setting

5

4

3

LEN_LF_EN

0

R/W

0: MSB first

1: LSB first (1)

Data area bit order setting

0: MSB first

DAT_LF_EN

1: LSB first

RX Extended Link Layer mode setting (Wireless M-Bus)

0: Automatically detecting “Extended Link Layer”

1: HW does not check “Extended Link Layer” automatically

IEEE 802.15.4g packet enable setting

RX_EXTPKT_OFF

0: disabel

1: enable

(Note) While 0b1 is set, when in RX sate, bit 12 (CRC setting) and bit 11

(Whitening setting) in the L-field are identified and automatilly done proper

process. LENGTH_MODE([PKT_CTRL2:B0 0x05(0)])=0b1 (2byte mode)

setting shold be required .

(Note) When in TX state, packet format is not identified automatilcally.

WHT_SET([PKT_CTRL2:B0 0x08(2)] and CRC_LEN[1:0]([PKT_CTRL2:B0

0x05(5-4)] setting are required.

Please refer to the “IEEE802.15.4g setting”.

Packet format setting

00: Format A (Wireless M-Bus) (2)

01: Format B (Wireless M-Bus)

2

IEEE802_15_4G_EN

0

R/W

1:0 PKT_FORMAT[1:0]

00

10: Format C (non Wireless M-BUS, general purpose format)

11: Reserved

Please refer to the “Packet Format”

(Note)

1. If setting LSB first (LEN_LF_EN=0b1), the length value should be 63 bytes or less. If the length value is 64byte or

more, TX/RX operation is not possible.

2. If PKT_FORMAT=0b00, the length value should be 13 bytes or more. If the length value is 12 bytes or less, TX/RX

operation is not possible.

147/230

FEDL7406-06

ML7406

0x05[PKT_CTRL2]

Function: Packet configuration 2

Address:0x05 (BANK0)

Reset value:0x1C

Bit

7

Bit name

Reset value

0

R/W

description

CRC initialized state setting

0: all “0” setting

CRC_INIT_SEL

1: all “1” setting

CRC complement value OFF setting

0: complement value

1: no complement value

CRC length setting

00: CRC8

6

CRC_COMP_OFF

0

R/W

01: CRC16

10: CRC32

5:4 CRC_LEN[1:0]

01

11: Reserved

(Note) 0b00(CRC8) and 0b10(CRC32) are valid for Format C only

For details, please refer to ”CRC Function”.

RX CRC setting

0: disable

3

RX_CRC_EN

1

R/W

1: enable (CRC calculation)

(Note) If enable, CRC results are stored in [CRC_ERR_H/M/L: B0

0x13/14/15] registers.

TX CRC setting

0: disable

1: enable (CRC calculation)

(Note) If enable, CRC(s) are automatically appended to the TX data.

If meet the floowing conditons, TX FIFO access error interrupt is set. You

contorol size of last wirte data to TX FIFO to avoid this interrupt is set.

2

TX_CRC_EN

1

R/W

TX_CRC_EN = 0b0 and CRC_LEC = 0b00 and size of a last wirte data to

TX FIFO is 1byte

TX_CRC_EN = 0b0 and CRC_LEC = 0b01 and size of a last wirte data to

TX FIFO is equal to or less than 2bytes.

TX_CRC_EN = 0b0 and CRC_LEC = 0b10 and size of a last wirte data to

TX FIFO is equal to or less than 4bytes.

1

0

Reserved

0

R/W

Length field setting

0: 1 byte mode

1: 2 byte mode (Lengthis extended upper 3 bits)

Other setting prohibit

LENGTH_MODE

[Description]

1. In transmission (TX), based on the length from [TX_PKT_LEN_H/L:B0 0x7A/7B] registers, total data lenth will be

calculated. Upon transmitting all data, TX complete.

2. In receiving (RX), based on the the length from RX data, total data lenth will be calculated. Upon reception of all data,

RX complete.

3. For details. please refer to the “Packet Format”.

148/230

FEDL7406-06

ML7406

0x06[DRATE_SET]

Function: Data rate setting

Address:0x06 (BANK0)

Reset value:0xBB

Bit

Bit name

Reset value

R/W

description

RX data rate setting

(Note) By setting this register, optimal values automatically set to the

[RX_RATE1_H/L: B1 0x04/05] and [RX_RATE2: B1 0x06] registers

(Note) If RXDIO_CTRL[1:0]([DIO_SET:B0 0x0C(7-6)])=0b10 (enabling DIO

mode), less than or equal 9.6 kbps cannot be used by setting this register.

It is need to set specified values directly to the [RX_LATE1_H/L:B1

0x04/05] and [RX_LATE2:B1 0x06] registers according to the “Register

setting”.

Setting

0000

0001

0010

0011

0100

Data rate

1.2kbps

2.4kbps

4.8kbps

9.6kbps

10kbps

7:4 RX_DRATE [3:0]

1011

R/W

0101

0110

11.52kbps

15kbps

0111

20kbps

1000

1001

32.768kbps

40kbps

1010

50kbps

1011

1100

1101

1110

1111

100kbps

200kbps

300kbps

400kbps

500kbps

TX data rate setting

(Note) By setting this field, based on [TX_RATE_H/L: B1 0x02/03], optimal

value is selected.

Setting

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Data rate

1.2kbps

2.4kbps

4.8kbps

9.6kbps

10kbps

11.52kbps

15kbps

20kbps

32.768kbps

40kbps

50kbps

100kbps

200kbps

300kbps

400kbps

500kbps

3:0 TX_DRATE [3:0]

1011

R/W

[Description]

1. In order to change data rate, other registers must be programmed.

2. For details, please refer to “Data rate modification setting”.

149/230

FEDL7406-06

ML7406

0x07[DATA_SET1]

Function: TX/RX data configuration 1

Address:0x07 (BANK0)

Reset value:0x05

Bit

7

Bit name

Reset value

0

R/W

description

TX/RX preamble pattern setting

0: “01” pattern

PB_PAT

1: “10” pattern

TX data polarity setting

6

5

TX_FSK_POL

RX_FSK_POL

0

R/W

0: data“1”=deviated to high frequency, data“0”=low frequency

1: data“1”=deviated to low frequency, data“0”= high frequency

RX data polarity setting

0: data“1”=deviated to high frequency, data“0”=low frequency

1: data“1”=deviated to low frequency, data“0”= high frequency

GFSK mode setting

0: GFSK disable (FSK mode)

1: GFSK enable

For details, please refer to the “Modulation setting”

RX data coding mode setting

00: Manchester coding

01: NRZ coding

10: 3-out-of-6 coding

11: reserve

TX data coding mode setting

00: Manchester coding

4

GFSK_EN

0

R/W

3:2 RX_DEC_SCHEME [1:0]

1:0 TX_DEC_SCHEME [1:0]

01

R/W

01: NRZ coding

10: 3-out-of-6 coding

11: reserve

0x08[DATA_SET2]

Function: TX/RX data configuration 2

Address:0x08 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

R/W

description

7:5 Reserved

000

R/W

SyncWord pattern selection setting

0: sync word pattern 1

1: sync word pattern 2

For details, please refer to the “SyncWord detection function”.

Two SyncWords search setting

0: 2 Sync words searching disable

1: 2 Sync words searching enable

For details, please refer to “SyncWord detection function”.

Two RX preambles search setting

0: 2 preamble patterns search disable (distinguish between “01” pattern

and ”10” pattern)

4

3

SYNCWORD_SEL

0

R/W

2SW_DET_EN

2PB_DET_EN

2

0

R/W

1: 2preamble patterns search enable (do not distinguish between “01”

pattern and ”10” pattern)

Manchester polarity setting

0: do not inverse polarity

1: inverse polarity

Whitening setting

0: disable Whitening

1

0

MAN_POL

WHT_SET

0

R/W

1: enable Whitening

0x09[CH_SET]

Function: RF channel setting

Address:0x09 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

description

RF channel setting (setting range: 0 to 255)

For details, please refer to the “Channel frequency setting”.

7:0 RF_CH[7:0]

150/230

FEDL7406-06

ML7406

0x0A[RF_STATUS_CTRL]

Function: RF auto status transition control

Address:0x0A (BANK0)

Reset value:0x08

Bit

Bit name

Reset value

00

R/W

description

7:6 Reserved

FAST_TX mode setting

0: disabel FAST_TX mode

1: enable FAST_TXmode

(Note) If enable. move to the TX state after the data bytes writtrn into the TX

FIFO becomes grater than the value specified by TXFIFO_THRL[5:0]

([TXFIFO_THRL: B0 0x18(5-0)]).

Automatic TX mode setting

0: disable automatic TX mode

1: enable automatic TX mode

(Note) If enable, TX data specified by the Length are written to the TX FIFO,

move to the TX state.

RF state setting after packet reception completion.

00: move to IDLE state(TRX_OFF)

01: move to TX state

10: continue RX state

11: move to SLEEP state

RF state setting after packet transmission completion.

00: move to IDLE state(TRX_OFF)

01: continue TX state

5

4

FAST_TX_EN

0

R/W

AUTO_TX_EN

0

R/W

3:2 RXDONE_MODE[1:0]

1:0 TXDONE_MODE[1:0]

10

00

10: move to RX state

11: move to SLEEP state

(Note)

1. For details, please refer to the “LSI state transition control”.

0x0B[RF_STATUS]

Function: RF state setting and status indication

Address:0x0B (BANK0)

Reset value:0x88

Bit

bit

Reset value

1000

R/W

R

description

RF staus indication

0110: RX_ON (RX state)

1000: TRX_OFF (RF OFF state)

1001: TX_ON (TX state)

7:4 GET_TRX[3:0]

RF state setting

0011: Force_TRX_OFF (force RF OFFsetting)

0110: RX_ON (RX setting) (*1)

1000: TRX_OFF (RF OFFsetting) (*3)

1001: TX_ON (TX setting) (*2)

3:0 SET_TRX[3:0]

1000

R/W

*1 During TX operation, setting RX_ON is possible. In this case, after TX

completion, move to RX_ON state automatically.

*2 During RX operation, setting TX_ON is possible. In this case, after RX

completion, move to TX_ON state automatically.

*3 If TRX_OFF is selected during TX or RX operation, after TX or RX

operation completed, RF is turned off. If Force_TRX_OFF is selected

during TX or RX operation, RF is turned off immediately.

[Description]

1. For details, please refer to “LSI state control”

151/230

FEDL7406-06

ML7406

0x0C[DIO_SET]

Function: DIO mode configuration

Address:0x0C (BANK0)

Reset Value:0x00

Bit

Bit name

Reset value

R/W

description

RX DIO mode setting

00: disable DIO mode (FIFO mode)

01: continuous output mode

DIO (demodulated data) and DCLK are constantly output

10: data output mode 1

DIO (undecoded data) and DCLK is output after SyncWord detection.

11: data output mode 2

DIO (decoded data) and DCLK is output after L-field detection.

(Note) When measuring BER, set to 0b01.

7:6 RXDIO_CTRL[1:0]

00

(Note) If 0b10, as FIFO is used for storing undecoded RX data, FIFO cannot

be used. By setting bit0(DIO_START)=0b1, DIO and DCLK are output.

Data after SyncWord is stored into FIFO.

(Note) If 0b11, as FIFO is used for storing decoded RX data. By setting

bit0(DIO_START) =0b1, DIO and DCLK are output. Upon completion of

data (specified by the Length) transfering , DIO and DCLK output are stop.

Data after Length field is stored into FIFO.

TX DIO mode setting

00: disable DIO mode (FIFO mode)

01: DCLK is constantly output

10: DCLK is output after SyncWord.

5:4 TXDIO_CTRL[1:0]

00

R/W

(Note) When setting 0b01/10, FIFOcannot be used. Encoded data must be

sent to ML7406 at the falling edge of DCLK.

3

2

1

0

Reserved

0

R/W

DIO RX completion setting

0: RX not finished

1: RX completion

DIO_RX_COMPLETE

Reserved

(Note) after RX completion, reset to 0b0 automatically.

DIO RX data output start setting

0: no OUTPUT (NOT stop output)

1: start OUTPUT

DIO_START

(Note) Upon out of synchronization, reset to 0.

(Note)

1. For details, please refer to “DIO function”.

152/230

FEDL7406-06

ML7406

0x0D[INT_SOURCE_GRP1]

Function: Interrupt status for INT0 to INT7

Address:0x0D (BANK0)

Reser value:0x00

Bit

7

Bit name

Reset value

0

R/W

description

Clock calibration completion interrupt

0: no interrupt

1: interrupt

Wake-up timer completion interrupt

0: no interrupt

INT[7]

INT[6]

6

5

0

R/W

1: interrupt

(Note) Iif this interrupt is cleared during SLEEP state, interrupt by wake-up

timer completion will not generate.

FIFO-Full interrupt

0: no interrupt

1: interrupt

INT[5]

INT[4]

(Note) Interrupt will generate, if FIFO usage becomes the threshold defined

by TXFIFO_THRH[5:0]([TXFIFO_THRH: B0 0x17(5-0)]) in TX, or

RXFIFO_THRL[5:0] ([RXFIFO_THRH: B0 0x19(5-0)]) in RX.

FIFO-Empty interrupt

0: no interrupt

1: interrupt

4

0

R/W

(Note) Interrupt will generate, If FIFO usage is below threshold defined by

TXFIFO_THRL[5:0] ([TXFIFO_THRL: B0 0x18(5-0)]) in TX, or

RXFIFO_THRL[5:0] ([RXFIFO_THRL: B0 0x1A(5-0)] in RX,.

RF state transition completion interrupt

3

2

INT[3]

INT[2]

0

R/W

0: no interrupt

1: interrupt

PLL unlock interrupt

0: no interrupt

1: interrupt (unlock)

VCO calibration completion interrupt or Fuse access completion interrupt

0: no interrupt

1: interrupt

(Note) After RESETN release (RESETN=”H”), or by setting

1

INT[1]

INT[0]

0

R/W

PDN_EN([SLEEP/WU_SET: B0 0x2D(2)])=0b1, returned from SLEEP

state, Fise access interrupt completion occurs. VCO calibration should be

done, after clearing INT[1].

Clock stabilization completion interrupt

0: no interrupt

0

1: interrupt

(Note)

1. Regardless of [INT_EN_GRP1: B0 0x10] register setting, this register value reflect internal status. For writing, only

0b0 is valid, writing 0b1is ignored.

2. If one of unmasked interrupt event occur, interrupt pin keeps output “Low”.

3. During SLEEP state, interupts are not cleared immediately by this register. In this case, interrupts are cleared at the

clock stabilizzation completion timing after return from the SLEEP state.

If need to clear interrupts during SLEEP state, please use [SLEEP_INT_CLR:B0 0x75] register.

153/230

FEDL7406-06

ML7406

0x0E[INT_SOURCE_GRP2]

Function: Interrupt status for INT8 to INT15 (RX)

Address:0x0E (BANK0)

Reset value:0x00

Bit

7

Bit name

Reset value

0

R/W

Description

Sync error interrupt

0: no interrupt

1: interrupt

INT[15]

(Note) Upon SyncWord detection, while receiving packet (length specified by

L-filed), if RX out-of-sync detected, interrupt will generate.

Field checking interrupt

6

5

INT[14]

INT[13]

0

R/W

0: no interrupt

1: interrupt

SyncWord detection interrupt

0: no interrupt

1: interrupt

RX FIFO access error interrupt

0: no interrupt

4

3

2

INT[12]

INT[11]

INT[10]

0

R/W

1: interrupt

(Note) During RX using FIFO mode, if RX FIFO overrun or underrun detected,

interrupt will generate.

RX Length error interrupt

0: no interrupt

1: interrupt

Diversity search completion interrupt

0: no interrupt

1: interrupt

(Note) After diversity completion, interrupt will generate at SyncWord

detection timing.

CRC error interrupt

0: no interrupt

1: interrupt

(Note) Upon detection of CRC error, interrupt will generate. As Format A/B

have multiple CRC-fields, error CRC block is indicated by [CRC_ERR_H/M/L:

B0 0x13/14/15] registers. Format C has only one CRC field. Therefore MCU

can detect CRC error with this interruption,

1

0

INT[9]

INT[8]

0

R/W

RX completion interrupt

0: no interupt

1: interrupt

(Note) interrupt will generate, when RX data specified by the L-field, received.

[Description]

(1) If the following L-field data is received, RX Length error interruption will generate.

Packet format

Extension format

[PKT_CTRL1: B0 0x04]

No extension

Length Indicating RX Length error

[PKT_CTRL1:B0 0x04]

Under 8 byte

Under 12 byte

Fromat A

Fromat B

Fromat C

2 byte extension

8 byte extension

No extension

Under 16 byte

Under 1 0byte, 128 to 129 byte

2 byte extension

8 byte extension

Under 17byte, 19 to 20byte, 128 to 129 byte

0 byte(CRC8)

-

1 byte(CRC16)

2 byte(CRC32)

(Note)

1. Regardless of setting [INT_EN_GRP2: B0 0x11], this register value reflect internal status. For writing, only 0b0 is

valid, writing 0b1 is ignored.

2. If one of unmasked interrerupt event occurs, inturrupt pin keeps output “Low” .

3. During SLEEP state, interupts are not cleared immediately by this register. In this case, interrupts are cleared at the

clock stabilizzation completion timing after return from the SLEEP state.

If need to clear interrupts during SLEEP state, please use [SLEEP_INT_CLR:B0 0x75] register.

154/230

FEDL7406-06

ML7406

0x0F[INT_SOURCE_GRP3]

Function: Inrerrupt status for INT16 to INT23 (TX)

Address:0x0F (BANK0)

Reset value:0x00

Bit

7

Bit name

Reset value

0

R/W

description

General purpose timer 2 interrupt

0: no interrupt

INT[23]

1: interrupt

General purpose timer 1 interrupt

0: no interrupt

1: interrupt

6

5

INT[22]

INT[21]

0

R/W

Reserved

TX FIFO access error interrupt

0: no interrupt

1: interrupt

4

INT[20]

0

R/W

(Note) During TX using FIFO mode, if the FIFO overrun / underrun occur, or if

the next packet data is written to the FIFO before transmitting, interrupt will

generate.

TX lenghth error interrupt (1)

3

2

INT[19]

INT[18]

0

R/W

0: no interrupt

1: interrupt

CCA completion interrupt

0: no interrupt

1: interrupt

TX Data request accept completion interrupt

0: no interrupt

1

0

INT[17]

INT[16]

0

R/W

1: interrupt

(Note) Interrupt will generate. when TX data, whose lenghth specified by

[TX_PKT_LEN_H/L: B0 0x7A/7B] registers, written to the FIFO,

TX completion interrupt

0: no interrupt

1: interrupt

(Note) Interrupt will generate.when TX data, whose length specified by the

[TX_PKT_LEN_H/L: B0 0x7A/7B] registers, transmitted,

[Description]

1. If the following L-field data is written to the [TX_PKT_LEN_H/L: B0 0x7A/7B] registers, TX Length error interrupt

will generate.

Packet format

Extension format

[PKT_CTRL1: B0 0x04]

No extension

Length indicating TX Length error

[PKT_CTRL1: B0 0x04]

Under 8 byte

Under 12 byte

Under 16 byte

Fromat A

Fromat B

Fromat C

2 byte extension

8 byte extension

No extension

Under 10 byte, 128 to 129 byte

2 byte extension

8 byte extension

under 17 byte, 19 to 20 byte, 128 to 129 byte

0 byte (CRC8)

-

1 byte (CRC16)

2 byte (CRC32)

(Note)

1. Regardless of setting [INT_EN_GRP3: B0 0x12], this register value reflect internal status. For writing, only 0b0 is

valid, writing 0b1 is ignored.

2. If one of unmasked interrerupt event occurs, inturrupt pin keeps output “Low”.

3. During SLEEP state, interupts are not cleared immediately by this register. In this case, interrupts are cleared at the

clock stabilizzation completion timing after return from the SLEEP state.

If need to clear interrupts during SLEEP state, please use [SLEEP_INT_CLR:B0 0x75] register.

155/230

FEDL7406-06

ML7406

0x10[INT_EN_GRP1]

Function: Interupt mask for INT0 to INT7

Address:0x10 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0x00

R/W

description

Enabling from interrupt 0 event to interrupt 7 event.

0: masking interrupt

7:0 INT_EN[7:0]

1: generate interrupt

[Description]

1. Please refer to the “interrupt events tabe”

2. For event details, please refer to the [INT_SOURCE_GRP1: B0 0x0D] register.

0x11[INT_EN_GRP2]

Function: Interupt mask for INT8 to INT15

Address:0x11 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0x00

R/W

Description

Enabling from interrupt 8 event to interrupt 15 event.

0: masking interrupt

7:0 INT_EN[15:8]

1: generate interrupt

[Description]

1. Please refer to the “interrupt events tabe”

2. For event details, please refer to the [INT_SOURCE_GRP2: B0 0x0E] register.

0x12[INT_EN_GRP3]

Function: Interuptmask for INT16 to INT23

Address:0x12 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0x00

R/W

description

Enabling from interrupt 16 event to interrupt 23 event.

0: masking interrupt

7:0 INT_EN[23:16]

1: generate interrupt

[Description]

1. Please refer to the “interrupt events tabe”

2. For event details, please refer to the [INT_SOURCE_GRP3: B0 0x0F] register.

0x13[CRC_ERR_H]

Function: CRC error status (high byte)

Address:0x13 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

000_0000

R/W

description

7:1 Reserved

17th CRC error status

0: CRC OK or no CRC calculation

1: CRC error

0

CRC_ERR[16]

0

R

(Note) for Format A (Wireless M-Bus)

[Description]

1. For details, please refer to the “CRC function”.

156/230

FEDL7406-06

ML7406

0x14[CRC_ERR_M]

Function: CRC error status (middle byte)

Address:0x14 (BANK0)

Reset value:0x00

Bit

7

Bit name

CRC_ERR[15]

Reset value

0

R/W

R

Description

16th CRC error status

0: CRC OK or no CRC calculation

1: CRC error

(Note) For Format A (Wireless M-Bus)

15th CRC error status

0: CRC OK or no CRC calculation

1: CRC error

6

CRC_ERR[14]

0

R

(Note) For Format A (Wireless M-Bus)

14th CRC error status

0: CRC OK or no CRC calculation

1: CRC error

(Note) For Format A (Wireless M-Bus)

13th CRC error status

0: CRC OK or no CRC calculation

1: CRC error

(Note) For Format A (Wireless M-Bus)

12th CRC error status

0: CRC OK or no CRC calculation

1: CRC error

(Note) For Format A (Wireless M-Bus)

11th CRC error status

0: CRC OK or no CRC calculation

1: CRC error

(Note) For Format A (Wireless M-Bus)

10th CRC error status

0: CRC OK or no CRC calculation

1: CRC error

(Note) For Format A (Wireless M-Bus)

9th CRC error status

0: CRC OK or no CRC calculation

1: CRC error

5

4

3

2

1

0

CRC_ERR[13]

CRC_ERR[12]

CRC_ERR[11]

CRC_ERR[10]

CRC_ERR[9]

CRC_ERR[8]

0

R

(Note) For Format A (Wireless M-Bus)

[Description]

1. For details, please refer to the “CRC function”.

157/230

FEDL7406-06

ML7406

0x15[CRC_ERR_L]

function: CRC error status (low byte)

Address:0x15 (BANK0)

Reset value:0x00

Bit

7

Bit name

CRC_ERR[7]

Reset value

0

R/W

R

Description

8th CRC error status

0: CRC OK or no CRC calculation

1: CRC error

(Note) For Format A (Wireless M-Bus)

7th CRC error status

0: CRC OK or no CRC calculation

1: CRC error

(Note) For Format A (Wireless M-Bus)

6th CRC error status

0: CRC OK or no CRC calculation

1: CRC error

(Note) For Format A (Wireless M-Bus)

5th CRC error status

0: CRC OK or no CRC calculation

1: CRC error

(Note) For Format A (Wireless M-Bus)

4th CRC error status

0: CRC OK or no CRC calculation

1: CRC error

(Note) For Format A (Wireless M-Bus)

3rd CRC error status

0: CRC OK or no CRC calculation

1: CRC error

(Note) For Format A or B (Wireless M-Bus)

2nd CRC error status

0: CRC OK or no CRC calculation

1: CRC error

6

5

4

3

2

1

0

CRC_ERR[6]

CRC_ERR[5]

CRC_ERR[4]

CRC_ERR[3]

CRC_ERR[2]

CRC_ERR[1]

CRC_ERR[0]

0

R

(Note) For Format A or B (Wireless M-Bus)

1st CRCerror status

0: CRC OK or no CRCcalculation

1: CRC error

(Note) For Format A or B (Wireless M-Bus)

[Description]

1. For details, please refer to the “CRC function”.

158/230

FEDL7406-06

ML7406

0x16[STATE_CLR]

Function: State clear control

Address:0x16 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

R/W

Description

State clear enable

0: disabel State clear

1: enable State clear

7

STATE_CLR_EN

0

State clear to bit0 - 6 can be enabled depending on this bit.

6:5 Reseverd

00

Address check counter clear

1: Clear addres check counter.

4

STATE_CLR4

0

R/W

(Note) [ADDR_CHK_CTR_H/L:B1 0x62,63] registers wull be cleard

(Note) bit7(STATE_CLR_EN)=0b1 is required. After clear operation and then

automatically return to 0b0.

Diversity State clear

1: Clear diversity state.

(Note) bit7(STATE_CLR_EN)=0b1 is required. After clear operation and then

automatical return to 0b0.

PHY State clear

1: Clear PHY state.

(Note) bit7(STATE_CLR_EN)=0b1 is required. After clear operation and then

automatically return to 0b0.

RX FIFO pointer clear

1: Clear write pointer/read pointer of FIFO.

(Note) bit7(STATE_CLR_EN)=0b1 is required. After clear operation and then

automatically return to 0b0.

3

2

1

0

STATE_CLR3

STATE_CLR2

STATE_CLR1

STATE_CLR0

0

R/W

TX FIFO pointer clear

1: Clear write pointer/read pointer of FIFO.

(Note) bit7(STATE_CLR_EN)=0b1 is required. After clear operation and then

automatically return to 0b0.

[Description]

1. Please set enable bit (bit7) and execution bit (bit4 to bit0) at the same time. After completing a clearing operation,

automatically 0b0 will be written to each bit.

2. After writing to the execution bits, (bit3 to bit0), clearing will be completed within (master clock period ×

[RX_RATE_H/L: B1 0x04/05] × 2[sec]) μs.

0x17[TXFIFO_THRH]

Function: TX FIFO-Full level setting

Address:0x17 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

R/W

Description

TX FIFO Full level enable

0: disable

1: enable

7

6

TXFIFO_THRH_EN

Reserved

0

R/W

0

R/W

TX FIFO Full level setting

(Note) valid, if bit7(TXFIFO_THRH_EN)=0b1

5:0 TXFIFO_THRH[5:0]

00_0000

[Description]

1. For details, please refer to “TX FIFO usage notification function”

2. When TX FIFO data size exceeds the threshold , INT[5] (group 1) interrupt will generate.

159/230

FEDL7406-06

ML7406

0x18[TXFIFO_THRL]

Function: TX FIFO-Empty level setting and TX trigger level setting in FAST_TX mode

Address:0x18 (BANK0)

Reset value:0x00

Bit

7

bit name

TXFIFO_THRL_EN

Reserved

Reset value

R/W

Description

TX FIFO Empty level enable

0: disable

1: enable

0

6

TX FIFO Empty level setting and TX trigger level setting in FAST_TX mode

(Note) valid if bit7(TXFIFO_THRH_EN)=0b1.

(Note) TXFIFO_THRL[5:0] should be set larger than or equal 1.

(Note) If using FAST_TX mode, please set 0b1 to the FAST_TX_EN

([RF_STATUS_CTRL: B0 0x0A(5)]). Empty level should be set less than or

equal [FIFO write size(byte) – 3(byte)].

5:0 TXFIFO_THRL[5:0]

00_0000

R/W

[Description]

1. For details, please refer to “TX FIFO usage notification function”

2. When TX FIFO data size becomes below the threshold , INT[4] (gropu 1) interrupt will generate.

(Note)

1. The relation of TX FIFO writen data size and FAST_TX threshold should be relation of below table. It may be

transmitt without intending, if he relation are not kept.

FAST_TX threshold [byte]

TX_FIFO data size [byte]

1 – 2

3 – 6

7 – 14

15 - 30

31 – 62

63

1

1 – 3

1 – 7

1 – 15

1 – 31

1 – 63

160/230

FEDL7406-06

ML7406

0x19[RX FIFO_THRH]

Function: RX FIFO-Full level enable and level setting

Address:0x19 (BANK0)

Reset value:0x00

Bit

7

Bit name

RXFIFO_THRH_EN

Reserved

Reset value

0

R/W

Description

RX FIFO Full level enable

0: disable

1: enable

6

0

R/W

RX FIFO Full level settting

5:0 RXFIFO_THRH[5:0]

00_0000

(Note) valid if bit7(RXFIFO_THRH_EN)=0b1.

[Description]

1. For details, please refer to “RX FIFO usage notification function”

2. When RX FIFO data size excceds the threshold , INT[5] (group1) interrupt will generate.

0x1A[RX FIFO_THRL]

Function: RX FIFO-Empty level enable and level setting (high byte)

Address:0x1A (BANK0)

Reset value:0x00

Bit

7

Bit name

RXFIFO_THRL_EN

Reserved

Reset value

R/W

Description

RX FIFO Emptylevel enable

0: disable

1: enable

0

6

RX FIFO Emptylevel setting

5:0 RXFIFO_THRL[5:0]

00_0000

(Note) valid if bit7(RXFIFO_THRL_EN)=0b1.

(Note) Empty level should be set larger or equal 2.

[Description]

1. For details, please refer to “RX FIFO usage notification function”

2. When RX FIFO data size becomes below the threshold , INT[4] (group1) interrupt will generate.

161/230

FEDL7406-06

ML7406

0x1B[C_CHECK_CTRL]

Function: Control field detection setting

Address:0x1B (BANK0)

Reset value:0x00

Bit

7

Bit name

Reset value

0

R/W

Description

Data processing if Field mismatch.

0: RX data continue

1: RX data abort

CA_RXD_CLR

(Note) if 0b1 is set, immediately abort RX data and wait for the next RX

packet.

Field check interrupt setting

0: generate interrupt if Field match.

1: generate interrupt if Field mismatch.

(Note) selecte interupt will becomen INT[14] (group2).

6

5

CA_INT_CTRL

Reserved

0

R/W

Control field pattern 5 check enable

0: disable

1: enable

4

C_FIELD_CODE5_EN

0

R/W

(Note) The pattern 5 has specific function. If received Control field data

matches with the patterm 5, immediately generate interrupt and following

M-filed and A-field check do not proceed. Field mismach interrupt will not

generate.

Control field code #4 check enable

3

2

1

0

C_FIELD_CODE4_EN

C_FIELD_CODE3_EN

C_FIELD_CODE2_EN

C_FIELD_CODE1_EN

0

R/W

0: disable

1: enable

Control field code #3 check enable

0: disable

1: enable

Control field code #2 check enable

0: disable

1: enable

Control field code #1 check enable

0: disable

1: enable

[Description]

1. For details, please refer to the “Field check function”.

2. When using field check function, RXDIO_CTRL[1:0] ([DIO_SET:B0 0x0C(7-6)] ) =0b00 (FIFO mode) or 0b11 (data

output mode 2) setting is required.

0x1C[M_CHECK_CTRL]

Function: Manufacture ID field detection setting

Address:0x1C (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000

R/W

Description

7:4 Reserved

Manufacture ID field code #4 check enable

3

2

1

0

M_FIELD_CODE4_EN

0

R/W

0: disable

1: enable

Manufacture ID field code #3 check enable

0: disable

1: enable

Manufacture ID field code #2 check enable

0: disable

1: enable

Manufacture ID field code #1 check enable

0: disable

1: enable

M_FIELD_CODE3_EN

M_FIELD_CODE2_EN

M_FIELD_CODE1_EN

[Description]

1. For details, please refer to the “Field check function”.

2. When using field check function, RXDIO_CTRL[1:0] ([DIO_SET:B0 0x0C(7-6)] ) =0b00 (FIFO mode) or 0b11 (data

output mode 2) setting is required.

162/230

FEDL7406-06

ML7406

0x1D[A_CHECK_CTRL]

Function: Address field detection setting

Address:0x1D (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

00

R/W

Description

Address field code #6 check enable

7:6 Reserved

5

4

3

2

1

0

A_FIELD_CODE6_EN

0

R/W

0: disable

1: enable

Address field code #5 check enable

0: disable

1: enable

Address field code #4 check enable

0: disable

1: enable

Address field code #3 check enable

0: disable

1: enable

Address field code #2 check enable

0: disable

1: enable

Address field code #1 check enable

0: disable

1: enable

A_FIELD_CODE5_EN

A_FIELD_CODE4_EN

A_FIELD_CODE3_EN

A_FIELD_CODE2_EN

A_FIELD_CODE1_EN

[Description]

1. For details, please refer to the “Field check function”.

2. When using field check function, RXDIO_CTRL[1:0] ([DIO_SET:B0 0x0C(7-6)] ) =0b00 (FIFO mode) or 0b11 (data

output mode 2) setting is required.

0x1E[C_FIELD_CODE1]

Function: Control field setting (code #1)

Address:0x1E (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

Description

7:0 C_FIELD_CODE1[7:0]

C-field setting code #1

[Description]

1. For details, please refer to the “Field check function”.

0x1F[C_FIELD_CODE2]

Function: Control field setting (code #2)

Address:0x1F (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

Description

7:0 C_FIELD_CODE2[7:0]

C-field setting code #2

[Description]

1. For details, please refer to the “Field check function”.

163/230

FEDL7406-06

ML7406

0x20[C_FIELD_CODE3]

Function: Control field setting (code #3)

Address:0x20 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

Description

description

7:0 C_FIELD_CODE3[7:0]

C-field setting code #3

[Description]

1. For details, please refer to the “Field check function”.

0x21[C_FIELD_CODE4]

Function: Control field setting (code #4)

Address:0x21 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

7:0 C_FIELD_CODE4[7:0]

C-field setting code #4

[Description]

1. For details, please refer to the “Field check function”.

0x22[C_FIELD_CODE5]

Function: Control field setting (code #5)

Address:0x22 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

7:0 C_FIELD_CODE5[7:0]

C-field setting code #5

[Description]

1. For details, please refer to the “Field check function”.

0x23[M_FIELD_CODE1]

Function: Manufacture ID 1^stbyte setting (code#1)

Address:0x23 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

7:0 M_FIELD_CODE1[7:0]

M-field 1^stbyte setting code #1

[Description]

1. For details, please refer to the “Field check function”.

0x24[M_FIELD_CODE2]

Function: Manufacture ID 1^stbyte setting (code#2)

Address:0x24 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

7:0 M_FIELD_CODE2[7:0]

M-field 1^stbyte setting code #2

[Description]

1. For details, please refer to the “Field check function”.

164/230

FEDL7406-06

ML7406

0x25[M_FIELD_CODE3]

Function: Manufacture ID 2^ndbyte setting (code#1)

Address:0x25 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

description

7:0 M_FIELD_CODE3[7:0]

M-field 2^ndbyte setting code #1

[Description]

1. For details, please refer to the “Field check function”.

0x26[M_FIELD_CODE4]

Function: Manufacture ID 2^ndbyte setting (code#2)

Address:0x26 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

description

7:0 M_FIELD_CODE4[7:0]

M-field 2^ndbyte setting code #2

[Description]

1. For details, please refer to the “Field check function”.

0x27[A_FIELD_CODE1]

Function: Address field 1^stbyte setting

Adress:0x27 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

description

7:0 A_FIELD_CODE1[7:0]

A-field setting (1^stbyte)

[Description]

1. For details, please refer to the “Field check function”.

0x28[A_FIELD_CODE2]

Function: Address field 2^ndbyte setting

Adress:0x28 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

Description

7:0 A_FIELD_CODE2[7:0]

A-fieldsetting (2^ndbyte)

[Description]

1. For details, please refer to the “Field check function”.

0x29[A_FIELD_CODE3]

Function: Address field 3^rdbyte setting

Adress:0x29 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

Description

7:0 A_FIELD_CODE3[7:0]

A-field setting (3^rdbyte)

[Description]

1. For details, please refer to the “Field check function”.

165/230

FEDL7406-06

ML7406

0x2A[A_FIELD_CODE4]

Function: Address field 4^thbyte setting

Adress:0x2A (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

Description

7:0 A_FIELD_CODE4[7:0]

A-field setting (4^thbyte)

[Description]

1. For details, please refer to the “Field check function”.

0x2B[A_FIELD_CODE5]

Function: Address field 5^thbyte setting

Adress:0x2B (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

7:0 A_FIELD_CODE5[7:0]

A-field setting (5^thbyte)

[Description]

1. For details, please refer to the “Field check function”.

0x2C[A_FIELD_CODE6]

Function: Address field 6^thbyte setting

Adress:0x2C (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

7:0 A_FIELD_CODE6[7:0]

A-field setting (6^thbyte)

[Description]

1. For details, please refer to the “Field check function”.

166/230

FEDL7406-06

ML7406

0x2D[SLEEP/WU_SET]

Function: SLEEP exceution and Wake-up operation setting

Address:0x2D (BANK0)

Reset value:0x08

Bit

7

Bit name

Reset value

0

R/W

Description

Wake-up timer operation mode setting

0: continue interval operation

1: after 1-SHOT operation, stop Wake-up timer.

After Wake-up operation setting

0: move to RX_ON

WUT_1SHOT_MODE

1: move to TX_ON

(Note) When continue operation timer is time-out, move to the SLEEP state.

(Note) if TX FIFO is writen in the SLEEP state, TX Data request accept

completion interrupt (INT[17] group 3) will generate after return from the

SLEEP state.

6

WAKEUP_MODE

0

R/W

(Note) When 0b1 is set, TX Data should be transmitted before time out of

continue operation timer.

Continue operation timer enable setting after Wake-up.

0: After Wake-up, do not start continue operation timer

1: Afer Wake-up, start continue operation timer.

(Note) When 0b1is set, and WAKEUP_MODE=0b0, if SyncWord or specified

fields are not detected untill continue operation time-out, automatically

move to the SLEEP state.

Wake up enable setting

0: disable Wake- up

1: enable wake-up

(Note) When 0b1is set, after wake-up timer is time-out, automatically revover

from the SLEEP state. Move to the state specified by bit6

(WAKEUP_MODE).

RC oscillation circuits operation mode setting

0: continuous operation

5

4

3

WU_DURATION_EN

WAKEUP_EN

0

1

R/W

1: operation when in the SLEEP state.

(Note) Please refer to the “SLEEP setting”.

RCOSC_MODE

(Note) If 0b1 is set when continuous operation timer is used, continuous

operation timer doesn’t work. Please set 0b0.

Wake-up timer clock setting

0: external clock source (EXT_CLK Pin #10)

1: on-chip RC oscillation circuit

(Note) Please refer to the “SLEEP setting”.

2

1

0

WUT_CLK_SOURCE

Reserved

0

R/W

SLEEP mode control

0: recover from the SLEEPstate (normal operation)

1: move to the SLEEP state

SLEEP_EN

(Note) Please refer to the “SLEEP setting”.

[Description]

1. For details, please refer to the “Wake-up timer”

167/230

FEDL7406-06

ML7406

0x2E[WUT_CLK_SET]

Function: Wake-up timer clock division setting

Address:0x2E (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

R/W

description

Continuous operation timer clock setting

0000: no division (ML7406C prohibits this setting)

0001: divided by 128

0010: divided by 256

0011: divided by 512

0100: divided by 1024

0101: divided by 2048

0110: divided by 4096

7:4 WUDT_CLK_SET[3:0]

0000

0111: divided by 8192

Other setting: divided by 16384

(Note) the source clock is specified by WUT_CLK_SOURCE

([SLEEP/WU_SET: B0 0x2D(2)]).

(Note) In case of using continuous operation timer, please set the same

value as WUDT_CLK_SET as WUT_CLK_SET.

Wake-up timer clock setting

0000: no division

0001: divided by 128

0010: divided by 256

0011: divided by 512

0100: divided by 1024

0101: divided by 2048

3:0 WUT_CLK_SET[3:0]

0000

R/W

0110: divided by 4096

0111: divided by 8192

Other setting: divided by 16384

(Note) the source clock is specified by WUT_CLK_SOURCE

([SLEEP/WU_SET: B0 0x2D(2)]).

[Description]

1. For details, please refer to the “Wake-up timer”.

0x2F[WUT_INTERVAL_H]

Function: Wake-up timer interval setting (high byte)

Address:0x2F (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

Description

Wake-up timer interval setting (high byte)

(Note) combined toghether with [WUT_INTERVAL_H:B0 0x30] register.

Timer interval can be programmed as follows:

7:0 WUT_INTERVAL[15:8]

Wake-up timer interval =

Wake-up timer clock cycle ([SLEEP/WU_SET:B0 0x2D(2)])*

Division setting ([WUT_CLK_SET: B0 0x2E(3-0)]) *

(Wake-up timer interval setting [WUT_INTERVAL_H/L:B0 0x2F/30] + 1)

(Note) WUT_INTERVAL[15:0] should be set larger than or equal 2.

[Description]

1. For details, please refer to the “Wake-up timer”.

168/230

FEDL7406-06

ML7406

0x30[WUT_INTERVAL_L]

Function: Wake-up timer interval setting (low byte)

Address:0x30 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

Description

Wake-up timer interval setting (low byte)

7:0 WUT_INTERVAL[7:0]

For details, please refer to [TIMER_INTERVAL_H: B0 0x2F] register

[Description]

1. For details, please refer to the “Wake-up timer”.

0x31[WU_DURATION]

function: Continuous operation timer (after Wake-up) setting

Address:0x31 (BANK0)

Reset value:0x00

Bit

Bbit name

Reset value

0000_0000

R/W

Description

Continuousoperation timer (after wake-up) setting

Operation timer period

=

Wake-up timer clock cycle ([SLEEP/WU_SET:B0 0x2D(2)]) *

Division setting ([WUT_CLK_SET: B0 0x2E(7-4)]) *

7:0 WU_DURATION[7:0]

(Continuous operation timer setting (WU_DURATION[7:0]) + 1)

(Note) WU_DURATION[7:0] should be set larger than or equal 1.

[Description]

1. For details, please refer to the “Wake-up timer”.

0x32[GT_SET]

Function: General purpose timer configuration

Address:0x32 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

00

R/W

Description

7:6 Reserved

General purpose timer #2 clock sources setting

0: wake-up timer clock

1: 2MHz clock

General purpose timer #2 execution setting

0: pause timer counting

1: start or resume timer counting

(Note) After time-out, reset to 0b0 automatically.

5

4

GT2_CLK_SOURCE

0

R/W

GT2_START

0

R/W

3:2 Reserved

00

R/W

General purpose timer #1 clock sources setting

0: wake-up timer clock

1: 2MHz clock

1

GT1_CLK_SOURCE

General purpose timer #1 execution setting

0: pause timer counting

1: start or resume timer counting

(Note) After time-out, reset to 0b0 automatically.

0

GT1_START

0

R/W

[Description]

1. For details, please refer to the “General purpose timer”.

169/230

FEDL7406-06

ML7406

0x33[GT_CLK_SET]

Function: General purpose timer clock division setting

Address:0x33 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

R/W

description

General purpose timer clock #2 division setting

0000: no division

0001: divided by 128

0010: divided by 256

0011: divided by 512

0100: divided by 1024

0101: divided by 2048

0110: divided by 4096

7:4 GT2_CLK_SET[3:0]

0000

R/W

0111: divided by 8192

1000: divided by 16384

1001: divided by 32768

Other setting: divided by 65536

(Note): The source clock is specified by GT2_CLK_SOURCE ([GT_SET:B0

0x32(5).

General purpose timer clock #1 division setting

0000: no division

0001: divided by 128

0010: divided by 256

0011: divided by 512

0100: divided by 1024

0101: divided by 2048

0110: divided by 4096

3:0 GT1_CLK_SET[3:0]

0000

R/W

0111: divided by 8192

1000: divided by 16384

1001: divided by 32768

Other setting: divided by 65536

(Note): The source clock is specified by GT1_CLK_SOURCE ([GT_SET:B0

0x32(1).

[Description]

1. For details, please refer to the ”General purposetimer”.

0x34[GT1_TIMER]

Function: General purpose timer #1 setting

Address:0x34 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

description

General purpose timer #1 period setting

General purpose timer #1period

=

General purpose timer clock cycle ([GT_SET:B0 0x32(1)]) *

Division setting ([GT_CLK_SET:B0 0x33(3-0)]) *

7:0 GT1_TIMER[7:0]

General purpose timer 1 period setting (GT1_TIMER[7:0])

[Description]

1. For details, please refer to the “General purpose timer”

170/230

FEDL7406-06

ML7406

0x35[GT2_TIMER]

Function: General purpose timer #2 setting

Address:0x35 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

description

General purpose timer #2 period setting

General purpose timer #2 period

=

7:0 GT2_TIMER[7:0]

GT2 clock cycle ([GY_SET:B0 0x32(5)]) *

Division setting ([GT_CLK_SET:B0 0x33(7-4)]) *

GT2 timer period setting (GT2_TIMER[7:0])

[Description]

1. For details, please refer to the “General purpose timer”

0x36[CCA_IGNORE_LVL]

Function: ED threshold level setting for excluding CCA judgement

Address:0x36 (BANK0)

Reset value:0xFE

Bit

Bit name

Reset value

1111_1110

R/W

Description

ED threshold level setting for excluding CCA running average judgement

(Note) An ED value exceeding this threshold, is not used for averaging

defined by ED_AVG([ED_CTRL: B0 0x41(2-0)]). CCA result will not be

judged until acquiring ED values reached averaging number.

CCA_RSLT ([CCA_CTRL: B0 0x39(1-0)]) indicates 0b11 (evaluation

on-going).

7:0 CCA_IGNORE_LVL[7:0]

[Description]

1. For details operation of CCA, please refer to the “CCA(Clear Channel Asessment) function”.

0x37[CCA_LVL]

Function: CCA threshold setting

Address:0x37 (BANK0)

Reset value:0x18

Bit

Bit name

Reset value

0001_1000

R/W

Description

CCA thresold level setting (setting range:0 to 255)

(Note) If ED value exceed this threshold, CCA_RST ([CCA_CTRL: B0

0x39(1-0)]) indicates 0b01 (carrier detected)

7:0 CCA _LVL[7:0]

[Description]

1. For details operation of CCA, please refer to the “CCA(Clear Channel Asessment) function”.

171/230

FEDL7406-06

ML7406

0x38[CCA_ABORT]

Function: Timing setting for forced termination of CCA operation

Address:0x38 (BANK0)

Reset value:0xFF

Bit

Bit name

Reset value

1111_1111

R/W

Description

CCA forced termination timing setting (range:0 to 255)

(Note) If set 0b0000_0000, this function becomes invalid.

(Note) 1 bit resolution is 128 μs.

(Note) Time out function for avoiding incompletion of CCA operation by carrier

detection. If CCA operated period becomes the value defined by this

register value * RSSI ADC clock setting (default setting :16 μs) , IDLE

detection is terminated and packet is aborted, RF state become TRX_OFF.

(Note) 16 μs is in case of ADC clock = 2.0MHz. . If 1.73MHz is selected,

register value * 18.5 μs. Please refer [ADC_CLK_SET:B1 0x08]) register.

7:0 CCA _ABORT[7:0]

[Description]

1. For details operation of CCA, please refer to the “CCA(Clear Channel Asessment) function”.

0x39[CCA_CTRL]

Function: CCA control setting and result indication

Address:0x39 (BANK0)

Reset value:0x00

Bit

7

Bit name

CCA_STOP

Reset value

0

R/W

Description

CCA continuous mode termination setting (terminate by set 0b1)

(Note) If CCA_CPU_EN is executed, CCA will continuously perform until this

bit is set to 0b1.

CCA IDLE detection mode enable setting

0: disable

1: enable

CCA continuous mode enable setting

0: disable

1: enablee

6

5

CCA_IDLE_EN

CCA_CPU_EN

0

R/W

(Note) CCA will continue untill terminated by CCA_STOP bit.

CCA execution setting

0: not perform CCA

1: perform CCA

4

3

2

CCA_EN

0

R/W

(Note) After completion of CCA, reset to 0b0 automatically.

High speed carrier checking mode setting

0: during RXON, do not perform CCA.

1: during RXON, perform CCA.

(Note) As a result of CCA, if no carrier found, automatically move to SLEEP

state. Timer function can be combined together as well. For details, please

refer to the “Wake-up timer”.

CCA forced termination setting

0: do not terminate CCA

1: terminate CCA

FAST_DET_MODE_EN

CCA_ABORT_EN

(Note) valid if bit6(CCA_IDLE_EN)=0b1.

CCA result

00: no carrier

01: carrier detected

10: CCA evaluation on-going (evaluating IDLE)

11: CCA evaluation on-going (ED value excluding CCA judgement

acquisition.) Please refer [CCA_IGNORE_LVL:B0 0x36]) register.

(Note) These bits are not cleared automatically. Every time CCA detects

carrier, 0b00 should be set to clear these bits. Only 0b00 are valid.for

writing.

1:0 CCA_RSLT[1:0]

00

R/W

CCA completion is indicated by INT[18] (group 3).

[Description]

1. For details operation of CCA, please refer to the “CCA(Clear Channel Asessment) function”.

2. Please do not set 0b1 to both bit6(CCA_IDLE_EN) and bit5(CCA_CPU_EN) at the same time.

172/230

FEDL7406-06

ML7406

0x3A[ED_RSLT]

Function: ED value indication

Address:0x3A (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

R

Description

ED value indication

(Note) If ED_RSLT_SET([ED_CTRL: B0 0x41(3)])=0b0, ED value is updated

constantly during RX_ON. If ED_RSLT_SET=0b1, ED value is acquired at

SyncWord detection timing. The value is updated at reading RX_FIFO.

7:0 ED_VALUE[7:0]

[Description]

1. For details of ED value acquisition operation, please refer to “Energy detection value (ED value) acquisition function”

0x3B[IDLE_WAIT_H]

Function: IDLE detection period setting during CCA (high 2 bits)

Address:0x3B (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

00_0000

R/W

Description

7:2 Reserved

IDLE judgement max. wait time setting (high 2 bits)

(Note) In CCA IDLE judgement, it is used for detecting long IDLE (no carrier)

period.

(Note)Combined toghether with [IDLE_WAIT_L:B0 0x3C] register. IDLE

detection period is programmed as follows.

1:0 IDLE_WAIT[9:8]

00

R/W

IDLE detection period =

ED value averaging period (default 8 times =128μs) + (IDLE_WAIT[9:0] *

16 μs)

(Note: Above example is in case of ADC clock= 2MHz. If 1.73MHz is selected,

IDLE_WAIT[9:0] × 18.5 μs. Please refer [ADC_CLK_SET:B1 0x08])

register.

[Description]

1. For details operation of CCA, please refer to “CCA(Clear Channel Asessment) function”.

0x3C[IDLE_WAIT_L]

Function: IDLE detection period setting during CCA (low byte)

Address:0x3C (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

Description

IDLE judgement max. wait time setting (low byte)

7:0 IDLE_WAIT[7:0]

For details, please refer to [IDLE_WAIT_H:B0 0x3B] register

[Description]

1. For details operation of CCA, please refer to “CCA(Clear Channel Asessment) function”.

173/230

FEDL7406-06

ML7406

0x3D[CCA_PROG_H]

Function: IDLE judgement elapsed time indication during CCA (high 2 bits)

Address:0x3D (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

00_0000

R/W

Description

7:2 Reserved

IDLE judgement elapsed time indication during CCA (upper byte)

(Note) combined toghether with [CCA_PROG_L:B0 0x3E] register. IDLE

judgement elapsed time is calculated as follows.

IDLE judgement elapsed time =

1:0 CCA_PROG[9:8]

00

R

ED value averaging period (default 8 times =128μs) + (IDLE_WAIT[9:0] *

16 μs)

(Note: Above example is in case of ADC clock= 2MHz. If 1.73MHz is selected,

IDLE_WAIT[9:0] × 18.5 μs. Please refer [ADC_CLK_SET:B1 0x08])

register.

[Description]

1. For details operation of CCA, please refer to “CCA(Clear Channel Asessment) function”.

0x3E[CCA_PROG_L]

Function: IDLE judgement elapsed time indication during CCA (low byte)

Address:0x3E (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

R

Description

IDLE judgement elapsed time indication during CCA (low byte)

7:0 CCA_PROG[7:0]

For details, please refer to [CCA:PROG_H:B0 0x3D] register.

[Description]

1. For details operation of CCA, please refer to “CCA(Clear Channel Asessment) function”.

0x3F-0x40[Reserved]

Function:

Address:0x3F-0x40 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

Description

7:0 Reserved

174/230

FEDL7406-06

ML7406

0x41[ED_CTRL]

Function: ED detection control setting

Address:0x41 (BANK0)

Reset value:0x83

Bit

7

Bit name

ED_CALC_EN

Reset value

R/W

Description

ED value calculation enable setting

0: disable ED value calculation

1: enable ED value calculation

1

00

0

6:5 Reserved

ED value calculation completion flag

0: calculation on-going (not completed)

1: calculation completion

4

ED_DONE

ED indication setting in [ED_RSLT:B0 0x3A] register

0: ED value constantly updated

3

ED_RSLT_SET

0

R/W

1: ED value acquired at SyncWord detection timing

(Note) if 0b1 is set, the ED value is updated at reading RX_FIFO. Please read

[ED_RSLT:B0 0x3A] register after reasing RX_FIFO.

ED value calculation average times setting

000: 1 time

001: 2 times average

010: 4 times average

011: 8 times average

100: 1 6times average

2:0 ED_AVG[2:0]

011

R/W

101: 32 times average

Other thanabove: 16times average

(Note) ED_AVG[2:0] must be set when ED value calculation stop (TRX_OFF

state or TX_ON state or bit7(ED_CALC_EN)=0b0).

[Description]

1. For details of ED value acquisition operation, please refer to ”Energy detection value(ED value)acquisition function”

0x42[TXPR_LEN_H]

Function: TX preamble length setting (high byte)

Address:0x42 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

Description

TX preamble length setting (high byte)

TX preamble length = (specified value x2) bits

(Note) combined toghether with [TXPR_LEN_L: B0 0x43] register.

(Note) Do not set value less than 0x0010 to TXPR_LEN[15:0].ML7406

requires more than or equal 0x0010 preamble for synchronization.

(Note) If diversity is used, this parameter may have to change according to

the data rate. Please refer to the ”Register setting”

7:0 TXPR_LEN[15:8]

0x43[TXPR_LEN_L]

Function: TX preamble length setting (low byte)

Address:0x43 (BANK0)

Reset value:0x10

Bit

Bit name

Reset value

0001_0000

R/W

Description

TX preamble length setting (low byte)

7:0 TXPR_LEN[7:0]

For details, please refer to [TXPR_LEN_H:B0 0x42] register.

175/230

FEDL7406-06

ML7406

0x44[POSTAMBLE_SET]

Function: Postamble length and pattern setting

Address:0x44 (BANK0)

Reset value:0x10

Bit

7

Bit name

Reserved

Reset value

0

R/W

Description

Postamble length setting

Postamble length = (specified value × 2) bits.

6:4 POSTAMBLE_LEN[2:0]

Reserved

001

0

R/W

3

Postamble pattern setting

00: “01” pattern repetition

01: “10” pattern repetition

10: repetition of the last CRC pattern and its inversion

11: reserved

Postamble enable setting

0: no postamble addition

1: postamble addition

2:1 POSTAMBLE_PAT[1:0]

00

0

R/W

0

POSTAMBLE_EN

0x45[SYNC_CONDITION1]

Function: RX preamble setting and ED threshold check setting

Address:0x45 (BANK0)

Reset value:0x08

Bit

7

Bit name

Reset value

R/W

Description

ED threshold check enable setting during synchronization

0: disable ED threshold check during synchronization

1: enable ED threshold check during synchronization

(Note) ED threshold value is set to the [SYNC_CONDITION2: B0 0x46]

register.

SYNC_ED_EN

0

6

Reserved

RX preamble checking length setting (setting range: 0 to 32, unit: bit)

(Note) if lager than 0b10_0000, interpret as 0b10_0000.

(Note) when 1 or more value is set to this register, for syncword detection,

syncword detection is performed with the pattern added to syncword pattern

for the number of preambles set. If the false detection probability is high only

with the syncword length, this function can reduce the probability by adding a

5:0 RXPR_LEN[5:0]

00_1000

R/W

preamble.

(Note) ML7406 requires AFC convergence time(Max 24 bits). If the preamble

comparison length set in RXPR_LEN[5:0] overlaps the AFC convergence

time, syncword can not be detected. Therefore, please set this register to a

value equal to or less than the number of bytes obtained by subtracting the

AFC convergence time from the transmission preamble.

176/230

FEDL7406-06

ML7406

0x46[SYNC_CONDITION2]

Function: ED threshold setting during synchronization detection

Address:0x46 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

Description

ED thereshold value setting during synchronization

(Note) If SYNC_ED_EN ([SYNC_CONDITION1: B0 0x45(7)])=0b1, ED

thereshold value become valid.

7:0 SYNC_ED_TH[7:0]

(Note) If acquired ED value does not exceed this threshold, synchronization is

not detected.

0x47[SYNC_CONDITION3]

Function: Bit error tolerance setting in RX preamble and SyncWord detection.

Address:0x47 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000

R/W

Description

7:4 SW_RCV[3:0]

3:0 PB_RCV[3:0]

Error tolerance value (bits) in the SyncWord (setting range: 0 to 15)

Error tolerance value (bits) in the preamble (setting range: 0 to 15)

0000

177/230

FEDL7406-06

ML7406

0x48[2DIV_CTRL]

Function: Antenna diversity setting

Address:0x48 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

R/W

Description

7:6 Reserved

00

0

5

4

3

2

ANT_CTRL1

ANT control bit 1

ANT control bit 0

ANT_CTRL0

INV_ANT_SW

INV_TRX_SW

ANT_SW polarity setting

TRX_SW polarity setting

Antenna switch setting

0: SPDT switch is used

1: DPDT switch is used

Antenna diversity setting

0: no antenna diversity

1: antenna diversity

1

0

2PORT_SW

2DIV_EN

0

R/W

[Description]

1. For details, please refer to “diversity function”

0x49[2DIV_RSLT]

Function: Antenna diversity result indication

Address:0x49 (BANK0)

Reset value:0x00

Bit

7

Bit name

2DIV_DONE

Reset value

R/W

R

Description

Antenna diversity search completion status

0: diversity search on-going (not completed)

1: diversity search completion

0

0_0000

01

6:2 Reserved

R/W

R

Antenna diversity result

01: Antenna 1

1:0 2DIV_RSLT[1:0]

10: Antenna 2

[Description]

1. For details, please refer to “diversity function”

2. This register is updated at SyncWord detection timing in each packet.

0x4A[ANT1_ED]

Function: Acquired ED value by antenna 1

Address:0x4A (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

R

Description

Acquired ED value by antenna 1

(Note) Set 2DIV_EN([2DIV_CTRL: B0 0x48(0)])=0b1. This register is updated

at SyncWord detection timing in each packet. However, if diversity completion

interrupt- ([INT_SOURCE_GRP2: B0 0x0D(2)]) is cleared, this register will be

cleared.

7:0 ANT1_ED[7:0]

178/230

FEDL7406-06

ML7406

0x4B[ANT2_ED]

Function: Acquired ED value by antenna 2

Address:0x4B (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

R

Description

Acquired ED value by antenna 2

(Note) Set 2DIV_EN([2DIV_CTRL: B0 0x48(0)])=0b1. This register is updated

at SyncWord detection timing in each packet. However, if diversity

completion interrupt- ([INT_SOURCE_GRP2: B0 0x0D(2)]) is cleared, this

register will be cleared.

7:0 ANT2_ED[7:0]

0x4C[ANT_CTRL]

Function: TX/RX antenna control setting

Address:0x4C (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

00

R/W

Description

7:6 Reserved

Antenna setting for RX

0: antenna 1

5

4

RX_ANT

0

R/W

1: antenna 2

(Note) Valid if bit4(RX_ANT_EN)=0b01. This bit defines antenna during

RX_ON.

Antenna settinge enable for RX

0: disable

1: enable

RX_ANT_EN

0

R/W

3:2 Reserved

00

Antenna setting for TX

0: antenna 1

1

0

TX_ANT

0

R/W

1: antenna 2

(Note) Valid If bit0(TX_ANT_EN)=0b01. This bit defines antenna during

TX_ON.

Antenna settinge enable for TX

0: disable

TX_ANT_EN

1: enable

[Description]

1. For details, please refer to “diversity function”

179/230

FEDL7406-06

ML7406

0x4D[MON_CTRL]

Function: Monitor function setting

Address:0x4D (BANK0)

Reset value:0x01

Bit

Bit name

Reset value

0

R/W

Description

BER measurement mode setting

0: normal operation mode

1: BER measurement mode

7

BER_MODE

(Note) By setting BER measurement mode, demodulated data/clock are

output from DIO/DCLK. For details, please refer to the ”BER measurement

setting”

FIFO mode monitor setting

0: FIFO mode and DIO/DCLKare not output.

1: FIFOmode and DIO/DCLKare output.

(Note) Demodulated data/clock are output from DIO/DCLK.

Temperature information signal digital output setting

0: do not display temperature information (digital)

1: display temperature information (digital)

6

5

FIFOMODE_MON

TEMP_ADC_OUT

0

R/W

(Note) This value can be read from [TEMP: B1 0x09].

For details, please refer to “temperature display function”

TEMP value analog output setting

0: Temperature information (analog) will not be output from A_MON pin.

1: Temperature information (analog) will be output from A_MON pin.

4

TEMP_OUT

0

R/W

For details, please refer to “temperature display function”

Digital monitor output signal selection setting

0000: “L” output

0001: CLK_OUT output

0010: PLL lock detection signal output

if PLL is locked, digital monitor signal outputs “H”

0011: Synchronization detection signal output

if synchronization is completed, digital monitor signal outputs “H”

Other setting: reserved

3:0 DMON_SET

0001

(Note)

1. If TEMP_ADC_OUT=0b1, ML7406 can not normally receive a received signal. When receiving, please set

TEMP_ADC_OUT to 0b0.

0x4E[GPIO0_CTRL]

Function: GPIO0 pin (pin #16) cpnfiguration setting

Address:0x4E (BANK0)

Reset value:0x07

Bit

7

6

Bit name

GPIO0_INV

GPIO0_OD

Reset value

R/W

Description

0

GPIO0 output signal polarity setting

GPIO0 output OpenDrain setting

GPIO0 forced output value setting

0: “L” output

5

GPIO0_FORCEOUT

0

R/W

1: “H” output

(Note) the setting of bit7(GPIO0_INV) does not affect on this output value.

GPIO0 forced output enable setting

4

3

GPIO0_FORCEOUTEN

Reserved

0

R/W

0: disable

1: enable (output the value according to bit5(GPIO0_FORCEOUT) setting.)

GPIO0 input-output signal setting

000: [output] “L” level

001: [output] antenna switch control signal 1 (TX-RX switch signal: TRW_SW)

010: [output] antenna switch control signal 2 (antenna switch signal: ANT_SW)

011: [output] external PA control signal

2:0 GPIO0_IO_CFG[2:0]

111

R/W

100: [input/output] data (DIO)

101: [output] data clock (DCLK)

110: [output] digital monitor signal

please refer DEMON_SET[3:0] ([MON_CTRL:B0 0x4D(3-0)]).

111: [output] interrupt notification signal (SINTN)

180/230

FEDL7406-06

ML7406

0x4F[GPIO1_CTRL]

Function: GPIO1 pin (pin #17) configuration setting

Address:0x4F (BANK0)

Reset value:0x06

Bit

7

6

Bit name

GPIO1_INV

GPIO1_OD

Reset value

R/W

Description

0

GPIO1 output signal polarity setting

GPIO1 output OpenDrainsetting

GPIO1 output forced setting

0: “L” output

5

GPIO1_FORCEOUT

0

R/W

1: “H” output

(Note) the setting of bit7(GPIO1_INV) does not affect on this output value.

GPIO1 forced output enable setting

4

3

GPIO1_FORCEOUTEN

Reserved

0

R/W

0: disable

1: enable (output the value according to bit5(GPIO1_FORCEOUT) setting.)

GPIO1 input-output signal selection setting

000: [output] “L” level

001: [output] antenna switch control signal 1 (TX-RX switch signal: TRW_SW)

010: [output] antenna switch control signal 2 (antenna switch signal: ANT_SW)

011: [output] external PA control signal

2:0 GPIO1_IO_CFG [2:0]

110

R/W

100: [input/output] data (DIO)

101: [output] data clock (DCLK)

110: [output] digital monitor signal

please refer DEMON_SET[3:0] ([MON_CTRL:B0 0x4D(3-0)])

111: [output] Interrupt notification signal (SINTN)

0x50[GPIO2_CTRL]

Function: GPIO2 pin (pin #18) configuration setting

Address:0x50 (BANK0)

Reset value:0x02

Bit

7

6

Bit name

GPIO2_INV

GPIO2_OD

Reset value

R/W

Description

0

GPIO2 output signal polarity setting

GPIO2 output OpenDrain setting

GPIO2 forced output value setting

0: “L” output

5

GPIO2_FORCEOUT

0

R/W

1: “H” output

(Note) the setting of bit7(GPIO2_INV) does not affect on this output value.

GPIO2 forced output enable setting

0: disable

4

3

GPIO2_FORCEOUTEN

Reserved

0

R/W

1: enable (output the value according to bit5(GPIO2_FORCEOUT) setting.)

GPIO2 input-output signal selection setting

000: [output] “L” level

001: [output] antenna switch control signal 1 (TX-RX switch signal: TRW_SW)

010: [output] antenna switch control signal 2 (antenna switch signal: ANT_SW)

011: [output] external PA control signal

2:0 GPIO2_IO_CFG [2:0]

010

R/W

100: [input/output] data (DIO)

101: [output] data clock (DCLK)

110: [output] digital monitor signal

please refer DEMON_SET[3:0] ([MON_CTRL:B0 0x4D(3-0)])

111: [output] Interrupt notification signal (SINTN)

181/230

FEDL7406-06

ML7406

0x51[GPIO3_CTRL]

Function: GPIO3 pin (pin#19) configuration setting

Address:0x51 (BANK0)

Reset value:0x01

Bit

7

6

Bit name

GPIO3_INV

GPIO3_OD

Reset value

R/W

Description

0

GPIO3 output signal polarity setting

GPIO3 output OpenDrain setting

GPIO3 output forced setting

0: “L” output

5

GPIO3_FORCEOUT

0

R/W

1: “H” output

(Note) the setting of bit7(GPIO3_INV) does not affect on this output value.

GPIO3 forced output enable setting

4

3

GPIO3_FORCEOUTEN

Reserved

0

R/W

0: disable

1: enable (output the value accoding to bit5(GPIO3_FORCEOUT) setting.)

GPIO3 input-output signal selection setting

000: [output] “L” level

001: [output] antenna switch control signal 1 (TX-RX switch signal:TRW_SW)

010: [output] antenna switch control signal 2 (antenna switch signal:ANT_SW)

011: [output] external PA control signal

2:0 GPIO3_IO_CFG [2:0]

001

R/W

100: [input/output] data (DIO)

101: [output] data clock (DCLK)

110: [output] digital monitor signal

please refer DEMON_SET[3:0] ([MON_CTRL:B0 0x4D(3-0)])

111: [output] Interrupt notification signal (SINTN)

0x52[EXTCLK_CTRL]

Function: EXT_CLK pin (pin #10) control

Address:0x52 (BANK0)

Reset value:0x00

Bit

7

6

Bit name

EXTCLK_INV

EXTCLK _OD

Reset value

R/W

Description

0

EXT_CLK output signal polarity setting

EXT_CLK output OpenDrain setting

EXT_CLK output forced setting

0: “L” output

1: “H” output

5

EXTCLK _FORCEOUT

0

R/W

(Note) the setting of bit7(EXTCLK_INV) does not affect on this output value.

EXT_CLK forced output enable setting

0: disable

EXTCLK

_FORCEOUTEN

4

3

0

R/W

1: enable (output the value according to bit5(EXTCLK_FORCEOUT) setting.)

Reserved

EXT_CLK input/outputsignal selection setting

000: [input] external clock (32 kHz)

001: [output] antenna switch control signal 1 (TX/RXswitch signal: TRX_SW)

010: [output] antenna switch control signal 2 (antenna switch signal: ANT_SW)

011: [output] external PA control signal

2:0 EXTCLK _IO_CFG [2:0]

000

R/W

100: Reserved

101: [output] During RX: RX clock output

During TX: TX clock output

110: [output] Digital monitor signal

111: [output] interrupt notificationsignal (SINTN) output

182/230

FEDL7406-06

ML7406

0x53[SPI/EXT_PA_CTRL]

Function: SPI interface(SDI/SDO)pins/external PAcontrol

Address:0x53 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

00

R/W

Description

7:6 Reserved

SDO pin (pin #12) input/output signal setting

0: [output] SDO (SPI interface)

5

4

SDO_CFG

SDI_CFG

0

R/W

1: [output] SDO (when SCEN pin (pin #14) = ”L”)

SCEN pin =when ”H”, DCLK output

For details, please refer to the “DIO function”

SDI pin (pin #15) input/ouput signal setting

0: [input] SDI(SPI interface)

1: [input] SDI (when SCEN pin (pin #14)= “L”

[input/output] DIO (when SCEN pin = ”H”)

For details, please refer to the “DIO function”

0

00

0

R/W

3:2 Reserved

External PA control signal control timing setting

0: TX_ON signal output.

1: PA_ON signal output.

For details of each signal timing , please refer to ” TX” in “Timing Chart”

External PA control timing enable setting

0: disable (“L” output)

1

0

EXT_PA_CNT

EXT_PA_EN

0

R/W

1: enable (valid bit1(EXT_PA_CNT) setting)

0x54[IF_FREQ_H]

Function: IF frequency setting (high byte)

Address:0x54 (BANK0)

Reset value:0x38

Bit

Bit name

Reset value

0011_1000

R/W

Description

IF frequency setting (high byte)

(Note) combined together with [IF_FREQ_L:B0 0x55] register

(Note) Please set the value of 1/2 of the IF frequency value.

For details, please refer to the “IF frequency setting”.

7:0 IF_FREQ[15:8]

0x55[IF_FREQ_L]

Function: IFfrequency setting (low byte)

Address:0x55 (BANK0)

Reset value:0xB6

Bit

Bit name

Reset value

1011_0110

R/W

Description

IF frequency setting (low byte)

7:0 IF_FREQ[7:0]

For details, please refer to [IF_FREQ_H:B0 0x54] register

[Description]

1. For details, please refer to “IF frequency setting”

0x56[IF_FREQ_CCA_H]

Function: IF frequency setting during CCA operation (high byte)

Address:0x56 (BANK0)

Reset value:0x38

Bit

Bit name

Reset value

0011_1000

R/W

Description

IF frequency setting during CCA operation (high byte)

(Note) combined together with [IF_FREQ_CCA_L:B0 0x57] register.

(Note) Please set the value of 1/2 of the IF frequency value.

For details, please refer to the “IF frequency setting”.

7:0 IF_FREQ_CCA[15:8]

183/230

FEDL7406-06

ML7406

0x57[IF_FREQ_CCA_L]

Function: IF frequency setting during CCA operation (low byte)

Address:0x57

Reset value:0xB6

Bit

Bit name

Reset value

1011_0110

R/W

Description

IF frequency setting during CCA operation (low byte)

For details, please refer to [IF_FREQ_CCA_H:B0 0x56] register

7:0 IF_FREQ_CCA [7:0]

[Description]

1. For details, plese refer to “IF frequency setting”

0x58[BPF_ADJ_H]

Function: Bandpass filter capaciance adjustment (high 2 bits)

Address:0x58 (BANK0)

Reset value:0x02

Bit

Bit name

Reset value

00_0000

R/W

Description

7:2 Reserved

Bandpass filter capacitance adjustment (high 2 bits)

(Note) combined together with [BPF_ADJ_L:B0 0x59] register.

1:0 BPF_C[9:8]

10

R/W

0x59[BPF_ADJ_L]

Function: Bandpass filter capacitance adjustment (low byte)

Address:0x59 (BANK0)

Reset value:0x4A

Bit

Bit name

Reset value

0100_1010

R/W

Description

Bandpass filter capaciatnce adjustment (low byte)

For details, please refer to [BPF_ADJ_H:B0 0x58] register

7:0 BPF_C[7:0]

0x5A-0x5B[Reserved]

Function:

Address:0x5A-0x5B (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

Description

7:0 Reserved

184/230

FEDL7406-06

ML7406

0x5C[BPF_CO]

Function: Band pass filter frequency band adjustment coefficient

Address:0x5C (BANK0)

Reset value:0x80

Bit

Bit name

Reset value

1000_0000

R/W

Description

Band pass filter frequency band adjustment coefficient

bit7: × 1

bit6: × 1/2

bit5: × 1/4

bit4: × 1/8

bit3: × 1/16

bit2: × 1/32

bit1: × 1/64

bit0: × 1/128

7:0 BPF_CO[7:0]

[Description]

1. For details, please refer to “BPF frequency band setting”

0x5D[BPF_CO_CCA]

Function: Band pass filter frequency band adjustment coefficient during CCA.

Address:0x5D (BANK0)

Reset value:0x80

Bit

Bit name

Reset value

1000_0000

R/W

DEscription

Band pass filter frequency band adjustment coefficient during CCA.

bit7: × 1

bit6: × 1/2

bit5: × 1/4

bit4: × 1/8

bit3: × 1/16

bit2: × 1/32

bit1: × 1/64

bit0: × 1/128

7:0 BPF_CO_CCA[7:0]

[Description]

1. For details, please refer to “BPF frequency band setting”

0x5E[IFF_ADJ_H]

Function: Demodulator DC level adjustment (high 2 bit)

Address:0x5E (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

00_0000

00

R/W

Description

7:2 Reserved

1:0 FDET_ADJ[9:8]

Demodulator DC level adjustment (high 2 bits)

(Note)

1. Please use the value specified in the “Register setting”.

185/230

FEDL7406-06

ML7406

0x5F[IFF_ADJ_L]

Function: Demodulator DC level adjustment (low byte)

Address:0x5F (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

Description

Demodulator DC level adjustment (low byte)

7:0 FDET_ADJ[7:0]

(Note)

2. Please use the value specified in the “Register setting”.

0x60[IFF_ADJ_CCA_H]

Function: Demodulator DC level adjustment during CCA (high 7 bits)

Address:0x60 (BANK0)

Reset value:0x54

Bit

7

Bit name

Reserved

Reset value

0

101_0100

R/W

Description

6:0 FDET_ADJ_CCA1[6:0]

Demodulator DC level adjustment 1 during CCA

(Note)

1. Please use the value specified in the “Register setting”.

0x61[IFF_ADJ_CCA_L]

Function: Demodulator DC level adjustment during CCA (low byte)

Address:0x61 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

000

0_0000

R/W

Description

Demodulator DC level adjustment 3 during CCA

Demodulator DC level adjustment 2 during CCA

7:5 FDET_ADJ_CCA3[2:0]

4:0 FDET_ADJ_CCA2[4:0]

(Note)

1. Please use the value specified in the “Register setting”.

0x62[OSC_ADJ1]

Function: Coarse adjustment of load capacitance for oscillation circuits

Address:0x62 (BANK0)

Reset value:0x08

Bit

Bit name

Reset value

0000

R/W

Description

Load capacitance coarse adjustment - approximately 0.7pF/step

7:4 Reserved

3:0 OSC_ADJ_ROUGH[3:0]

1000

[Description]

1. For details, please refer to “oscillation circuits adjustment”

186/230

FEDL7406-06

ML7406

0x63[OSC_ADJ2]

Function: Fine adjustment of load capacitance for oscillation circuits

Address:0x63 (BANK0)

Reset value:0x40

Bit

7

Bit name

Reserved

Reset value

0

R/W

Description

Fine adjustment of load capacitance

approximately 0.02pF/step (adjustment range 0x00 to 0x77)

6:0 OSC_ADJ_FINE[6:0]

100_0000

R/W

-

[Description]

1. For details, please refer to “oscillation circuits adjustment”

0x64[Reserved]

Function:

Address:0x64 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

Description

7:0 Reserved

0x65[OSC_ADJ4]

Function: Oscillation circuits bais adjustment (high speed start-up)

Address:0x65 (BANK0)

Reset:0x1F

Bit

Bit name

Reset value

000

R/W

Description

7:5 Reserved

Oscillation circuits bais adjustment (high speed start-up)

00000: 0uA

to

4:0 OSC_BIAS2[4:0]

1_1111

R/W

11111: 720uA

0x66[RSSI_ADJ]

Function: RSSI value adjustment

Address:0x66 (BANK0)

Reset value:0x00

Bit

7

Bit name

RSSI_ADD

Reset value

0

R/W

Description

Adjustment direction setting

0: decrease (set -)

1: increase (set +)

6:5 Reserved

4:0 RSSI_ADJ[4:0]

00

0_0000

R/W

RSSI adjustment value setting

[Description]

1. For details, please refer to “Energy detection value (ED value) adjustment”

187/230

FEDL7406-06

ML7406

0x67[PA_MODE]

Function: PA mode setting/PA regulator coarse adjustment

Address:0x67 (BANK0)

Reset value:0x10

Bit

Bit name

Reset value

00

R/W

Description

7:6 Reserved

PA mode setting

00: 0dBm mode

01: 10dBm mode

10: 13dBm mode

11: (not allowed)

5:4 PA_MODE[1:0]

01

R/W

3:0 PA_REG[3:0]

[Description]

0000

PA regulator output voltage coarse adjustment setting

1. For details, please refer to the “PA adjustment”.

0x68[PA_REG_FINE_ADJ]

Function: PA regulator fine adjustment

Address:0x68 (BANK0)

Reset value:0x10

Bit

Bit name

Reset value

000

R/W

Description

7:5 Reserved

PA_REG_FINE_ADJ

[4:0]

PA regulator output voltage fine adjustment setting

(Note) PA output power can be adjusted in steps of less than 0.2dB.

4:0

1_0000

R/W

[Description]

1. For details, please refer to the “PA adjustment”.

0x69[PA_ADJ]

Function: PA gain adjustment

Address:0x69 (BANK0)

Reset value:0x07

Bit

Bit name

Reset value

0000

R/W

Description

7:4 Reserved

3:0 PA_ADJ[3:0]

0111

PA output gain adjustment setting

[Description]

1. For details, please refer to the “PA adjustment”.

0x6A[Reserved]

Function:

Address:0x6A (BANK0)

Reset value:0x2E

Bit

Bit name

Reset value

0010_1110

R/W

Description

7:0 Reserved]

188/230

FEDL7406-06

ML7406

0x6B[Reserved]

Function:

Address:0x6B (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

Description

7:0 Reserved

0x6C[IQ_MAG_ADJ]

Function: IF IQ amplitude balance adjustment

Address:0x6C (BANK0)

Reset value:0x08

Bit

Bit name

Reset value

00

R/W

Description

IQ signal amplitude balance adjustment

7:4 Reserved

3:0 MAG_ADJ[3:0]

1000

[Description]

1. Image rejection can be adjusted by MAG_ADJ[3:0]. For details, please refer to the “I/Q adjustment”.

0x6D[IQ_PHASE_ADJ]

Function: IF IQ phase balance adjustment

Address:0x6D (BANK0)

Reset value:0x20

Bit

Bit name

Reset value

00

10_0000

R/W

Description

IQ signal phase balance adjustment

7:6 Reserved

5:0 PHASE_ADJ[5:0]

[Description]

1. Image rejection can be adjusted by PHASE_ADJ [5:0]. For details, please refer to the “I/Q adjustment”.

0x6E[VCO_CAL]

Function: VCO calibration setting or status indication

Address:0x6E (BANK0)

Reset value:0x00

Bit

7

Bit name

CAL_WR_EN

Reset value

0

R/W

Description

VCO calibration mode setting

0: automatic setting mode

1: forced writing mode

Current VCO calibration value setting

(Note) In automatic setting mode, current calibration value is indicated.

(Note) In forced writing mode, the value set to VCO_CAL[6:0] will be applied

as the calibration value. (If CAL_WR_EN= 0b0, the set value is ignored.)

(Note) after completion of clock stabilization, the value will be 0b100_0000.

6:0 VCO_CAL[6:0]

000_0000

R/W

[Description]

1. For details, please refer to the “VCO adjustment”.

189/230

FEDL7406-06

ML7406

0x6F[VCO_CAL_START]

Function: VCO calibration execution

Address:0x6F (BANK0)

Reset value:0x00

Bit

Bit name

Reset valu

000

R/W

Description

7:5 Reserved

Automatic VCO calibration execution enable

0: disable automatic VCO calibration

1: execute automatic calibration when recovering from the SLEEP state.

4

AUTO_VCOCAL_EN

0

000

0

R/W

3:1 Reserved

Execute VCO calibration

0: execution completed

1: execution started

0

VCO_CAL_START

[Description]

1. For details, please refer to the “VCO adjustment”

0x70[CLK_CAL_SET]

Function: Low speed clock calibration control

Address:0x70 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000

R/W

Description

Clock division control for low speed clock calibration

0000: no division

7:4 CLK_CAL_DIV[3:0]

3:1 Reserved

0001: no division

Other setting: division setting

000

0

R/W

Execute low speed clock calibration

0: execution completion

1: execution start

0

CLK_CAL_START

[Description]

1. For details, please refer to the “Low speed clock shift detection function”

0x71[CLK_CAL_TIME]

Function: Low speed clock calibration time setting

Address:0x71 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

00

R/W

Description

Low speed Clock calibration time setting

7:6 Reserved

5:0 CLK_CAL_TIME [5:0]

00_0000

R/W

Calibration time =

Wake-up timer clock cycle ([SLEEP/WU_SET:B0 0x2D(2)]) * [set value]

[Description]

1. For details, please refer to the “Low speed clock shift detection function”

190/230

FEDL7406-06

ML7406

0x72[CLK_CAL_H]

Function: Low speed clock calibartion result indication (high byte)

Address:0x72 (BANK0)

Reset value:0xFF

Bit

Bit name

Reset value

1111_1111

R/W

R

Description

Low speed clock calibartion result (high byte)

7:0 CLK_CAL [15:8]

[Description]

1. For details, please refer to the “Low speed clock calibartion Auxiliary function”

0x73[CLK_CAL_L]

Function: Low speed clock calibartion result indication (low byte)

Address:0x73 (BANK0)

Reset value:0xFF

Bit

Bit name

Reset value

1111_1111

R/W

R

Description

Low speed clock calibartion result (low byte)

7:0 CLK_CAL [7:0]

[Description]

1. For details, please refer to the “Low speed clock calibartion Auxiliary function”

0x74[Reserevd]

Function:

Address:0x74 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

Description

7:0 Reserved

0x75[SLEEP_INT_CLR]

Function: Interrupt clear setting during SLEEP state

Address:0x75 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

000_0000

R/W

Description

Interrupt clear setting during SLEEP

7:1 Reserved

0: not clear interrupt

1: clear interrupt

(Note) During SLEEP state, interrupt cannot be cleared by

[INT_SOURCE_GRP*: B0 0x0D/0E/0F] registers. By setting this bit to 0b1,

interrupt can be cleared. This register can be written only during SLEEP

state. After return from SLEEP state, this bit becomes 0b0.

(Note) Clear is applicable to whole interrupts [INT_SOURCE_GRP*: B0

0x0D/0E/0F].

0

SLEEP_INT_CLR

0

R/W

191/230

FEDL7406-06

ML7406

0x76[RF_TEST_MODE]

Function: TX test pattern setting

Address:0x76 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

R/W

Description

7:6 Reserved

00

0

5

4

3

2

1

TEST5

TEST4

TEST3

TEST2

TEST1

CW output

“01” pattern output

All ”0” output

All ”1” output

PN9 output

0

Test mode enable

0: disable test mode

1: enable test mode

0

TEST_EN

0

R/W

[Description]

1. During normal operation, all bits have to be 0b0.

2. More than one bits are enabled at the same time, lowest bit is valid.

3. Data rate is value in the TX_DRATE[3:0] ([DRATA_SET: B0 0x06(3-0)]).

4. During PN9 output setting, any PN9 polynomial can be specified by [WHT_CFG: B1 0x66].

Most of the commercial Bit error metter use PN9’s polynomial as x⁹+x⁴+1, which is equivalent to [WHT_CFG: B1

0x66]=0x08.

0x77[STM_STATE]

Function: State machine status/synchronization status indication

Address:0x77 (BANK0)

Reset value:0x00

Bit

7

Bit name

Reset value

0

R/W

R

Description

Receiving mode indication

0: Receive mode T

1: Receive mode C

MODE_DET_RSLT

(Note) Indication is valid when 2MODE_DET_EN([2MODE_DET:B3 0x23(0)])

=0b1.

(Note) Updated at every SyncWord detection

RX synchronization detection status

0: not synchronized

1: synchronization detected

Receiving format indication

0: detect SyncWord #1 (Format A)

1: detect SyncWord #2 (Foomat B)

(Note) Indication is valid whne Packet format A or B is selected.

PKT_FORMAT[1:0] ([PKT_CTRL1: B0 0x04(1-0)])=0b00 or 0b01

(Note)Updated at every SyncWord detection timing.

State machine status

6

5

SYNC_STATE

0

R

SW_DET_RSLT

0_0000: IDLE state

0_0001: Preamble transmission state

0_0010: SyncWord transmission state

0_0011: L-field transmission state

0_0100: Data area TX state

4:0 PHY_STATE[4:0]

0_0000

R

0_0101: Postamble transmission state

0_0110: TX delay waiting state

0_0111: DIO TX state

1_0010: SyncWord detection state

1_0011: L-field receiving state

1_0100: Data area receiving state

1_0111: DIO RX state

192/230

FEDL7406-06

ML7406

0x78[FIFO_SET]

Function: FIFO readout setting

Address:0x78 (BANK0)

Reset value:0x00

Bit

Bbit name

Reset value

000_0000

R/W

Description

7:1 Reserved

FIFO readout setting

0: read RX FIFO

1: read TX FIFO

(Note) [RD_FIFO:B0 0x7F] register is used for reading both RX FIFO and TX

FIFO. If 0b1 is set in order to read TX FIFO, please readout data length

specified by [TX_PKT_LEN_H/L: B0 0x7A/7B] registers or set

STATE_CLR1 ([STATE_CLR:B0 0x16(1)]) = 0b1 (RX FIFO pointer clear).

If FIFO read is aborted without RX FIFO pointer clear and then change to

read RX FIFO, reading starts from the interrupting pointer. Therefore RX

FIFO could not be read correctly

0

FIFO_R_SEL

0

R/W

0x79[RX_FIFO_LAST]

Function: RX FIFO data usage status indication

Address:0x79 (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

00

R/W

Description

7:6 Reserved

RX FIFO data usage status (range: 0 to 63)

For details, please refer to the “FIFO control function”

5:0 RX_FIFO_LAST[5:0]

00_0000

R

0x7A[TX_PKT_LEN_H]

Function: TX packet length setting (high byte)

Address:0x7A (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

Description

TX packet length setting (high byte)

(Note) setting TX data Length.

FormatA: Length excluded L-field and CRC-field

FormatB/C: Length excluded L-field

(Note) combined toghether with [TX_PKT_LEN_L: B0 0x7B] register.

high byte value is valid when LENGTH_MODE([PKT_CTRL: B0 0x05

(0)])=0b1

7:0 TX_PKT_LEN[15:8]

For details, please refer to the “FIFO control function”

0x7B[TX_PKT_LEN_L]

Function: TX packet length setting (low byte)

Address:0x7B (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

Description

TX packet length setting (low byte)

For details, please refer to [PKT_LEN_H: B0 0x7A] register.

7:0 TX_PKT_LEN[7:0]

193/230

FEDL7406-06

ML7406

0x7C[WR_TX_FIFO]

Function: TX FIFO

Address:0x7C (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

W

Description

TX FIFO

(Note) TX data strored in the TX FIFO is one packet, regardless of packet

length. If one packet is stored - (after generation of TX data request

acceptance completion interrupt (INT[17] (group 3) and before generation

of TX completion interrupt, INT16 (group3) ) - and if the next writing access

is atempted, the TX FIFO will be over-wrtten. And TX FIFO access error

interrupt, INT[20] (group3) will be generated. In case of TX FIFO access

error occurs, set STATE_CLR0([STATE_CLR: B0 0x16(0)])=0b1. (TX FIFO

pointer clear)

7:0 TX_FIFO[7:0]

For details, plese refer to “FIFO control function”.

0x7D[RX_PKT_LEN_H]

Function: RX packet length indication (upper byte)

Address:0x7D (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000

R/W

R

Description

RX packet Length value (high byte)

(Note) combined toghether with [RX_PKT_LEN_L: B0 0x7E] register.

(Note) FormatA/B/C: indicating packet length excluding L-field.

7:0 RX_PKT_LEN[15:8]

0x7E[RX_PKT_LEN_L]

Function: RX packet length indication (low byte)

Address:0x7E (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

R

Description

RX packet Lengthvalue (low byte)

For details, please refer to [RX_PKT_LEN_H: B0 0x7D] register.

7:0 RX_PKT_LEN[7:0]

0x7F[RD_FIFO]

Function: FIFO read

Address:0x7F (BANK0)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

R

Description

FIFO read

(Note) read FIFO specified by FIFO_R_SEL([FIFO_SET: B0 0x78(0)]).

(Note) When RX operation, RX data can be stored up to one packet length,

regardless of packet length. If one packet data is stored and the next

packet is received, the FIFO will be over-written.

7:0 RD_FIFO[7:0]

(Note) if FIFO read is aborted, set STATE_CLR1 ([STATE_CLR:B0 0x16(1)])

= 0b1 (RX FIFO pointer clear).

For details, plese refer to the “FIFO control function”.

194/230

FEDL7406-06

ML7406

●Register Bank1

0x00[BANK_SEL]

Function: Register accesss selection

Address:0x00 (BANK1)

Reset value:0x11

Bit

7

Bit name

B3_ACEN

Reset value

0

R/W

DEscription

BANK3 register access enable

0: access disable

1: access enable

BANK2 register access enable

0: access disable

1: access enable BANK2

BANK1 register access enable

0: access disable

1: access enable BANK1

BANK0 register access enable

0: access disable

6

5

4

B2_ACEN

B1_ACEN

B0_ACEN

0

1

R/W

1: access enable BANK0

BANK switching

0b0001: BANK0 access

0b0010: BANK1 access

0b0100: BANK2 access

0b1000: BANK3 access

Others than above: not allowed

3-0 BANK[3:0]

0001

R/W

[Description]

1. Do not access BANK1 registers during VCO calibration.

2. Register acess can be done by CLK_INIT_DONE([CLK_SET1: B0 0x02(7)])=0b0.

But the register related to RF status has to be changed after CLK_INIT_DONE=0b1.

0x01[CLK_OUT]

Function: CLKOUT output frequency setting

Address:0x01 (BANK1)

Reset value:0x05

Bit

Bit name

Reset value

R/W

Description

Output clock frequency setting

The following formula is used.

0000_0000: 26MHz

0000_0001: 13MHz

0000_0010: 8.66MHz (Duty ratio ···High:Low=1:2)

0000_0011: 6.5MHz

0000_0100: 4.3MHz

0000_0101: 3.3MHz

7:0 CLK_DIV[7:0]

0000_0101

R/W

0000_0110: 2.6MHz

0000_0111: 0.86MHz

0000_1000: 0.43MHz

Other setting: The following formula is used to define output frequency.

Output frequency = 26 / (16 × [set value] + 2) [MHz]

For example, If value is 0x09,

Output frequency = 26 / (16 × 9 + 2) = 178kHz

NOTE:

Due to default value of [CLK_SET2: B0 0x03] register, For ML7406T, the CLK_OUT is not output after initiailzation.

When using CLK_OUT with above LSIs, proper clock source should be set at first, [CLK_SET2: B0 0x03] register.

195/230

FEDL7406-06

ML7406

0x02[TX_RATE_H]

Function: TX data rate conversion setting (high 4 bits)

Address:0x02 (BANK1)

Reset value:0x00

Bit

Bit name

Reset value

0000

R/W

Description

7:4 Reserved

TX data rate conversion setting (high 4 bits)

(Note) combined toghether with [TX_RATE_L: B1 0x03] register.

When a given data rate is set, the following formula is used.

3:0 TX_RATE[11:8]

0000

R/W

Setting value = round (26MHz / 13 / [a given data rate])

For details, please refer to the “Data rate setting function”

0x03[TX_RATE_L]

Function: TX data rate conversion setting (low rate)

Adress:0x03 (BANK1)

Reset value:0x14

Bit

Bit name

Reset value

0001_0100

R/W

Description

TX data rate conversion setting (low byte)

7:0 TX_RATE[7:0]

For details, please refer to [TX_RATE_H:B1 0x02] register .

0x04[RX_RATE1_H]

Function: RX data rate concversion setting 1 (high 4 bits)

Address:0x04 (BANK1)

Reset value:0x00

Bit

Bit name

Reset value

0000

R/W

Description

7:4 Reserved

RX data rate conversion setting (high 4 bits)

(Note) combined toghether with [RX_RATE1_L: B1 0x05] register.

When a given data rate is set, the following formula is used.

3:0 RX_RATE1[11:8]

0000

R/W

Setting value = round (26MHz / {[a given data rate] × [RX_RATE2]register)})

For details, please refer to the “Data rate setting function”

0x05[RX_RATE1_L]

Function: RX data rate cnvesrion setting 1 (low byte)

Address:0x05 (BANK1)

Reset value:0x04

Bit

Bit name

Reset value

0000_0100

R/W

Description

RX data rate conversion setting 1 (low byte)

7:0 RX_RATE1[7:0]

For details, please refer to ”[RX_RATE1_H:B1 0x04]” register.

196/230

FEDL7406-06

ML7406

0x06[RX_RATE2]

Function: Data rate conversion setting

Address:0x06 (BANK1)

Reset value:0x41

Bit

7

Bit name

Reserved

Reset value

0

R/W

Description

RX data rate conversion setting 2 (setting range: 30 to 127)

(Note) using together with RX_RATE1_H/L:B1 0x04/05] registers.

(Note) Do not set value below 0x1D to this register.

6:0 RX_RATE2[6:0]

0100_0001

R/W

For details, please refer to [RATE_SET1_H:B1 0x04] register.

0x07[REGULATOR_CTRL]

Function: Regulator control setting

Address:0x07(BANK1)

Reset value:0xFE

Bit

Bit name

Reset value

1111

R/W

Description

7:4 Reserved

Regulator supply control (RF circuit)

0: Stop

1: Supply

3

2

1

RFREG_EN

REG_EN

1

R/W

* Valid only when setting OVR_REG_CTRL = 0b1.

Regulator supply control

0: Stop

1: Supply

* Valid only when setting OVR_REG_CTRL = 0b1.

Regulator control

0: Main regulator

1: Sub regulator

REG_SEL

* Valid only when setting OVR_REG_CTRL = 0b1.

Regulator control selection setting

0: Automatic control

0

OVR_REG_CTRL

0

R/W

1: Register control

* When setting 0b1, the regulator control controls the regulator according to

the setting of REG_SEL, REG_EN, RFREG_EN.

0x08[ADC_CLK_SET]

Function: RSSI ADC clock frequency setting

Address:0x08 (BANK1)

Reset value:0x50

Bit

7

Bit name

Reserved

Reset value

0

R/W

Description

Clock stabilization waiting time setting

00: 500μs

01: 250μs

10: 50μs

11: 10μs

6:5 OSC_W_SEL[1:0]

10

R/W

(Note) When start-up or return from SLEEP state, the waiting time for clock

stabilization is set by this register.

For details, please refer to the “Start-up time” in the “Timing Chart”.

RSSI ADC clock setting

0: 1.73MHz

1: 2.0MHz

4

ADC_CLK_SEL

1

R/W

3:0 Reserved

0000

197/230

FEDL7406-06

ML7406

0x09[TEMP]

Function: Temperature digital value indication

Address:0x09(BANK1)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

Description

Temperature value

(Note) When using temperature measurement function, 75kΩ resistor must

be connected to A_MON pin and set 0b1 to TEMP_ADC_OUT

([MON_CTRL: B0 0x4D(5)]). Temperature information is available except

in the SLEEP state.

7:0 TEMP[7:0]

For details, please refer to “Temperature display function”.

198/230

FEDL7406-06

ML7406

0x0A[Reserved]

Function:

Address:0x0A(BANK1)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

Description

7:0 Reserved

0x0B[PLL_LOCK_DETECT]

Function: PLL lock detection setting

Address:0x0B (BANK1)

Reset value:0x81

Bit

Bit name

Reset value

R/W

Description

State control after PLL unlock detection when TX operation

0: Keep TX state

1: Stop TX state forcibly by Force_TRX_OFF

(Note) after PLL unlock detection, generates INT2 (group 1) and then move to

selected state.

7

PLL_LD_EN

1

(Note) during RX operation, after PLL unlock detection, generates INT2 and

keep RX state.

PLL lock detection time adjustment

Detection time = ([set value] * 8μs +1μs (default: 9 μs)

(Note) If PLL lock detection signal =”H” period excceds the detection time,

determined as PLL lock. If detecting PLL lock detection signal =”L”,

determined as PLL unlock immediately.

6:0 TIM_PLL_LD[6:0]

000_0001

R/W

(Note)

1. When move to IDLE state due to PLL unlock detection, please clear PLL unlock interrupt (INT[2] group1) before

transmitting or receive next data. And [RF_STATE:B0 0x0B] registers write access must be after 5 μs.

2. For details about PLL unlock detection condition and timing, please refer to the “VCO adjustment”.

0x0C[GAIN_MTOL]

Function: Threshold level setting for switching “middle gain” to “low gain”

Address:0x0C (BANK1)

Reset value:0x1E

Bit

Bit name

Reset value

00

01_1110

R/W

Description

7:6 Reserved

5:0 GC_TRIM_ML[5:0]

Gain switching threshold value (middle gain to low gain)

[Description]

1. For details operation of RSSI adjustment using this register, please refer to the ” Energy detection value(ED value)

adjustment”

(Note)

1. Please use the value specified in the “Register setting”.

2. This register value and [GAIN_LTOM] value have to be

GC_TRIM_ML > GC_TRIM_LM.

199/230

FEDL7406-06

ML7406

0x0D[GAIN_LTOM]

Function: Threshold level setting for switching “low gain” to “middle gain”

Address:0x0D (BANK1)

Reset value:0x02

Bit

Bit name

Reset value

00

00_0010

R/W

Drescription

7:6 Reserved

5:0 GC_TRIM_LM[5:0]

Gain switching threshold (low gain to middle gain)

[Description]

1. For details operation of RSSI adjustment using this register, please refer to the ” Energy detection value(ED value)

adjustment”

(Note)

1. Please use the value specified in the “Initialization table”.

2. This register value and [GAIN_MTOL] value have to be

GC_TRIM_ML > GC_TRIM_LM.

0x0E[GAIN_HTOM]

Function: Threshold level setting for switching “high gain” to “middle gain”

Address:0x0E (BANK1)

Reset value:0x9E

Bit

7

Bit name

GF_FIX_EN

Reserved

Reset value

1

R/W

Description

Gain switching setting

0: constantly updating

1: Upon synchronization established, gain will be fixed.

(Note) During BER measurement, set 0b0.

6

0

R/W

5:0 GC_TRIM_HM[5:0]

01_1110

Gain switching threshold value (high gain to middle gain)

[Description]

1. For details operation of RSSI adjustment using this register, please refer to the ” Energy detection value(ED value)

adjustment”

(Note)

1. Please use the value specified in the “Register setting”.

2. This register value and [GAIN_MTOH] value have to be

GC_TRIM_HM > GC_TRIM_MH.

0x0F[GAIN_MTOH]

Function: Threshold level setting for switching “middle gain” to “high gain”

Address:0x0F (BANK1)

Reset value:0x02

Bit

Bit name

Reset value

00

00_0010

R/W

Description

7:6 Reserved

5:0 GC_TRIM_MH[5:0]

Gain switching threshold value (middle gain to high gain)

[Description]

1. For details operation of RSSI adjustment using this register, please refer to the ” Energy detection value(ED value)

adjustment”

(Note)

1. Please use the value specified in the “Register setting”.

2. This register value and [GAIN_MTOM] value have to be

GC_TRIM_HM > GC_TRIM_MH.

200/230

FEDL7406-06

ML7406

0x10[RSSI_ADJ_M]

Function: RSSI offset value setting during middle gain operation

Address:0x10 (BANK1)

Reset value:0x15

Bit

Bit name

Reset value

00

01_0101

R/W

Description

7:6 Reserved

5:0 RSSI_GCADD [5:0]

RSSI offset value during middle gain operation

[Description]

1. For details operation of RSSI adjustment using this register, please refer to the ” Energy detection value(ED value)

adjustment”

(Note)

1. Please use the value specified in the “Register setting”.

0x11[RSSI_ADJ_L]

Function: RSSI offset value setting during low gain operation

Address:0x11 (BANK1)

Reset value:0x2B

Bit

Bit name

Reset value

00

10_1011

R/W

Description

7:6 Reserved

5:0 RSSI_GCADD2[5:0]

RSSI offset value during low gain operation

[Description]

1. For details operation of RSSI adjustment using this register, please refer to the ” Energy detection value(ED value)

adjustment”

(Note)

1. Please use the value specified in the “Register setting”.

0x12[RSSI_STABLE_TIME]

Function: RSSI stabilization wait time setting

Address:0x12 (BANK1)

Reset value:0x01

Bit

Bit name

Reset value

00

R/W

Description

7:6 Reserved

RSSI convergence wait time setting (setting range 0 to 3)

Wait time = ([set value] +2) * ADC clock setting (default:16 μs)

(Note) waiting time until RSSI value become stable. During this period, not

executing the next gain switching.

5:4 AD_MASK_SET[1:0]

00

R/W

(Note) 16 μs is in case of ADC clock = 2.0MHz. . If 1.73MHz is selected, RSSI

ADC clock = 18.5 μs. Please refer [ADC_CLK_SET:B1 0x08]) register.

After gain switching, RSSI stabilization wait time setting (setting range 1 to

15)

Wait time = ([set value]+1) * ADC clock setting (default :16 μs)

(Note)This period is RSSI stabilization time after gain switching. During this

period, RSSI value is not used for ED value calculation.

3:0 RSSI_STABLE[3:0]

0001

R/W

(Note) 16 μs is in case of ADC clock = 2.0MHz. . If 1.73MHz is selected, RSSI

ADC clock = 18.5 μs. Please refer [ADC_CLK_SET:B1 0x08]) register.

(Note)

1. Do not set 0x00 to this register.

201/230

FEDL7406-06

ML7406

0x13[RSSI_MAG_ADJ]

Function: Scale factor setting for ED value conversion

Address:0x13 (BANK1)

Reset value:0xD4

Bit

Bit name

Reset value

1101

R/W

Description

7:4 RSSI_MAG_M[3:0]

RSSI multiply value setting (setting range: 1 to 15)

RSSI division value 1/8 setting

0: do not apply

3

2

1

0

RSSI_MAG_D3

RSSI_MAG_D2

RSSI_MAG_D1

RSSI_MAG_D0

0

1

0

R/W

1: apply

RSSI division value 1/4 setting

0: do not apply

1: apply

RSSI division value 1/2 setting

0: do not apply

1: apply

RSSI division value 1/1 setting

0: do not apply

1: apply

(Note)

1. For details. Please refer to the “Energy detection value(ED value) adjustment”.

2. Division seeting can be selected one bit from bit3 to bit0. If more than one bits are set, only MSB is valid. (i.e. If both

bit3 and bit1 are set to 0b1, 1/8 setting is valid.)

3. If both multiplication and division are set, complex calculation is performed. However, if bit[3:0] = 0b0000, 1/1 will

be set. ( i.e. If bit[7:4] = 0b0100 (*4) and bit1=0b1 (1/2) are set, result will be x2)

4. If 0x00 is written to this register, *1 setting.

0x14[RSSI_VAL]

Function: RSSI value indication

Address:0x14 (BANK1)

Reset value:0x00

Bit

Bit name

Reset value

00

R/W

Description

7:6 Reserved

RSSI AD conversion value

(Note) Data update cycle is 16 μs.

5:0 RSSI [5:0]

00_0000

R

(Note) 16 μs is in case of ADC clock = 2.0MHz. . If 1.73MHz is selected,

update cycle will be 18.5 μs. Please refer [ADC_CLK_SET:B1 0x08])

register.

(Note)

1. As this ADC is shared with temperature measurement, during temperature measurement, this register value is

unchanged.

202/230

FEDL7406-06

ML7406

0x15[AFC/GC_CTRL]

Function: AFC /gain control setting

Address:0x15 (BANK1)

Reset value:0x82

Bit

7

Bit name

Reset value

1

R/W

Description

AFC enable setting

0: disable AFC

1: enable AFC

AFC_EN

6:2 Reserved

0_0000

Gain cpmtrol mode setting

00: high gain fix

1:0 GC_MODE [1:0]

10

R/W

01: high gain  middle gain transition enable

10: high gain  middle gain  low gain transition enable

11: Reserved

0x16[CRC_POLY3]

Function: CRC polynomial setting 3

Address:0x16 (BANK1)

Reset value:0x00

Bit

7

Bit name

Reserved

Reset value

0

000_0000

R/W

Description

6:0 CRC_POLY [30:24]

CRC polynomial setting 3

[Description]

1. For details, please refer to the “CRC function”.

0x17[CRC_POLY2]

Function: CRC polynomial setting 2

Address:0x17 (BANK1)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

Description

7:0 CRC_POLY [23:16]

CRC polynomial setting 2

[Description]

1. For details, please refer to the “CRC function”.

203/230

FEDL7406-06

ML7406

0x18[CRC_POLY1]

Function: CRC polynomial setting 1

Address:0x18 (BANK1)

Reset alue:0x1E

Bit

Bit name

Reset name

0001_1110

R/W

Description

7:0 CRC_POLY [15:8]

CRC polynomial setting 1

[Description]

1. For details, please refer to the “CRC function”.

0x19[CRC_POLY0]

Function: CRC polynomial setting 0

Address:0x19 (BANK1)

Reset value:0xB2

Bit

Bit name

Reset name

1011_0010

R/W

Description

7:0 CRC_POLY [7:0]

CRC polynomial setting 0

[Description]

1. For details, please refer to the “CRC function”.

0x1A[Reserved]

Function:

Address:0x1A (BANK1)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

Description

7:0 Reserved

0x1B[TXFREQ_I]

Function: TX frequency setting (I counter)

Address:0x1B (BANK1)

Reset value:0x21

Bit

Bit name

Reset value

00

R/W

Description

7:6 Reserved

TX frequency setting - I counter

(Note) Reset value is 868.950MHz.

5:0 TXFREQ_I [5:0]

10_0001

R/W

[Description]

1. For details, please refer to the “Channel #0 frequency setting”

0x1C[TXFREQ_FH]

Function: TX frequency setting (F counter high 4 bit)

Address:0x1C (BANK1)

Reset value:0x06

Bit

Bit name

Reset value

00

R/W

Description

7:4 Reserved

TX frequency setting (F counter high 4 bits)

(Note) Reset value is 868.950MHz.

3:0 TXFREQ_F[19:16]

0110

R/W

[Description]

For details, please refer to the “Channel #0 frequency setting”

204/230

FEDL7406-06

ML7406

0x1D[TXFREQ_FM]

Function: TX frequency setting (F counter middle byte)

Address:0x1D (BANK1)

Reset value:0xBD

Bit

Bit name

Reset value

1011_1101

R/W

Description

TX frequency setting (F counter middle byte)

(Note) Reset value is 868.950MHz.

7:0 TXFREQ_F[15:8]

[Description]

1. For details, please refer to the “Channel #0 frequency setting”

0x1E[TXFREQ_FL]

Function: TX frequency setting (F counter low byte)

Address:0x1E (BANK1)

Reset value:0x0B

Bit

Bit name

Reset value

0000_1011

R/W

Description

TX frequency setting (F counter low byte)

(Note) Reset value is 868.950MHz.

7:0 TXFREQ_F[7:0]

[Description]

1. For details, please refer to the “Channel #0 frequency setting”

0x1F[RXFREQ_I]

Function: RX frequency setting (I counter)

Address:0x1F (BANK1)

Reset value:0x21

Bit

Bit name

Reset value

00

R/W

Description

7:6 Reserved

RX frequency counter setting (I counter)

(Note) Reset value is 868.950MHz.

5:0 RXFREQ_I[5:0]

10_0001

R/W

[Description]

1. For details, please refer to the “Channel #0 frequency setting”

205/230

FEDL7406-06

ML7406

0x20[RXFREQ_FH]

Function: RX frequency setting (F counter high 4bit)

Address:0x20 (BANK1)

Reset value:0x06

Bit

Bit name

Reset value

0000

R/W

Description

7:4 Reserved

RX frequency setting F counter (high 4 bit)

(Note) Reset value is 868.950MHz.

3:0 RXFREQ_F[19:16]

0110

R/W

[Description]

1. For details, please refer to the “Channel #0 frequency setting”

0x21[RXFREQ_FM]

Function: RX frequency setting (F counter middle byte)

Address:0x21 (BANK1)

Reset value:0xBD

Bit

Bit name

Reset value

1011_1101

R/W

Description

RX frequency setting F counter (middle byte)

(Note) Reset value is 868.950MHz.

7:0 RXFREQ_F[15:8]

[Description]

1. For details, please refer to the “Channel #0 frequency setting”

0x22[RXFREQ_FL]

Function: RX frequency setting (F counter low byte)

Address:0x22 (BANK1)

Reset value:0x0B

Bit

Bit name

Reset value

0000_1011

R/W

Description

RX frequency setting F counter (low byte)

(Note) Reset value is 868.950MHz.

7:0 RXFREQ_F[7:0]

[Description]

1. For details, please refer to the “Channel #0 frequency setting”

0x23[CH_SPACE_H]

Function: Channel space setting (high byte)

Address:0x23 (BANK1)

Reset value:0x09

Bit

Bit name

Reset value

0000_1001

R/W

Description

Channel space setting (high byte)

(Note) Reset value is 60 kHz.

7:0 CH_SPACE[15:8]

[Description]

1. For details, please refer to the “Channel space setting”.

206/230

FEDL7406-06

ML7406

0x24[CH_SPACE_L]

Function: Channel space setting (low byte)

Address:0x24 (BANK1)

Reset value:0x73

Bit

Bit name

Reset value

0111_0011

R/W

Description

Channel space setting (low byte)

(Note) Reset value is 60 kHz.

7:0 CH_SPACE[7:0]

[Description]

1. For details, please refer to the “Channel space setting”.

0x25[SYNC_WORD_LEN]

Function: SyncWord length setting

Address:0x25 (BANK1)

Reset value:0x20

Bit

Bit name

Reset value

00

R/W

Description

7:6 Reserved

SyncWord length setting (setting range:8 to 32, unit:bit)

5:0 SYNC_WORD_LEN[5:0]

10_0000

R/W

(Note) If setting is smaller than 0b00_0111, operate as 0b00_1000.

(Note) If setting is larget than 0b10_0000, operate as 0b10_0000.

[Description]

1. For details, please refer to the “SyncWord detection function”

0x26[SYNC_WORD_EN]

Function: SyncWord enable setting

Address:0x26 (BANK1)

Reset value:0x0F

Bit

Bit name

Reset value

0000

R/W

Description

SYNC_WORD[31:24] checking enable

7:4 Reserved

3

2

1

0

SYNC_WORD_EN3

1

R/W

0: disable

1: enable

SYNC_WORD[23:16] checking enable

0: disable

SYNC_WORD_EN2

SYNC_WORD_EN1

SYNC_WORD_EN0

1: enable

SYNC_WORD[15:8] checking enable

0: disable

1: enable

SYNC_WORD[7:0] checking enable

0: disable

1: enable

[Description]

1. For details, please refer to the “SyncWord detection function”

0x27[SYNCWORD1_SET0]

Function: SyncWord #1 setting (bit24 to 31)

Address:0x27 (BANK1)

Reset value:0x54

Bit

Bit name

Reset value

0101_0100

R/W

Description

SyncWord pattern #1 setting (bit24 to 31)

7:0 SYNC_WORD1[31:24]

[Description]

1. For details, please refer to the “SyncWord detection function”

207/230

FEDL7406-06

ML7406

0x28[SYNCWORD1_SET1]

Function: SyncWord #1 setting (bit 16 to 23)

Address:0x28 (BANK1)

Reset value:0x3D

Bit

Bit name

Reset value

0011_1101

R/W

Description

SyncWord pattern #1 setting (bit 16 to 23)

7:0 SYNC_WORD1[23:16]

[Description]

1. For details, please refer to the “SyncWord detection function”

0x29[SYNCWORD1_SET2]

Function: SyncWord #1 setting (bit 8 to 15)

Address:0x29 (BANK1)

Reset value:0x54

Bit

Bit name

Reset value

0101_0100

R/W

Description

SyncWord pattern #1 setting (bit 8 to 15)

7:0 SYNC_WORD1[15:8]

[Description]

1. For details, please refer to the “SyncWord detection function”.

0x2A[SYNCWORD1_SET3]

Function: SyncWord #1 setting (bit 0 to 7)

Address:0x2A (BANK1)

Reset value:0xCD

Bit

Bit name

Reset value

1100_1101

R/W

Description

SyncWord pattern #1 setting (bit 0 to 7)

7:0 SYNC_WORD1[7:0]

[Description]

1. For details, please refer to the “SyncWord detection function”.

0x2B[SYNCWORD2_SET0]

Function: SyncWord #2 setting (bit 24 to 31)

Address:0x2B (BANK1)

Reset value:0x54

Bit

Bit name

Reset value

0101_0100

R/W

Description

SyncWord pattern #2 setting (bit 24 to 31)

7:0 SYNC_WORD2[31:24]

[Description]

1. For details, please refer to the “SyncWord detection function”.

0x2C[SYNCWORD2_SET1]

Function: SyncWord #2 setting (bit 16 to 23)

Address:0x2C (BANK1)

Reset value:0x3D

Bit

Bit name

Reset value

0011_1101

R/W

Description

SyncWord pattern #2 setting (bit 16 to 23)

7:0 SYNC_WORD2[23:16]

[Description]

1. For details, please refer to the “SyncWord detection function”.

208/230

FEDL7406-06

ML7406

0x2D[SYNCWORD2_SET2]

Function: SyncWord pattern setting 2 (bit 8 to 15)

Address:0x2D (BANK1)

Reset value:0x54

Bit

Bit name

Reset value

0101_0100

R/W

Description

7:0 SYNC_WORD2[15:8]

SyncWord pattern #2 setting (bit 8 to 15)

[Description]

1. For details, please refer to the “SyncWord detection function”.

0x2E[SYNCWORD2_SET3]

Function: SyncWord #2 setting (bit 0 to 7)

Address:0x2E (BANK1)

Reset value:0x3D

Bit

Bit name

Reset value

0011_1101

R/W

7:0 SYNC_WORD2[7:0]

SyncWord pattern #2 setting (bit 0 to 7)

[Description]

1. For details, please refer to the “SyncWord detection function”.

0x2F[FSK_CTRL]

Function: GFSK/FSK modulation timing resolution setting

Address:0x2F (BANK1)

Reset value:0x00

Bit

Bit name

Reset value

00_0000

R/W

7:1 Reserved

GFSK/FSK modulation timing resolution setting

0: 4.33MHz resolution

0

FSK_CLK_SET

0

R/W

1: 13MHz resolution

(Note) If bit rate is lower than 300kbps, please set 0b0.

If bit rate is higher than 300kbps,please set 0b1.

[Description]

1. For details, please refer to the “Modulation setting”.

0x30[GFSK_DEV_H]

Function: GFSK frequency deviation setting (high 6 bits)

Address:0x30 (BANK1)

Reset value:0x07

Bit

Bit name

Reset value

00

R/W

Description

7:6 Reserved

GFSK frequency deviation setting (high 6 bits)

(Note) combined toghether with [GFSK_DEV_L: B1 0x31] register.

(Note) Reset value is 45kHz.

5:0 GFSK_DEV[13:8]

00_0111

R/W

[Description]

1. For details, please refer to the “Modulation setting”.

209/230

FEDL7406-06

ML7406

0x31[GFSK_DEV_L]

Function: GFSK frequency deviation setting (low byte)

Address: 0x31 (BANK1)

Reset value:0x16

Bit

Bit name

Reset value

0001_0110

R/W

Description

GFSK frequency deviation setting (low byte)

(Note) combined toghether with [GFSK_DEV_H: B1 0x30] register.

(Note) Reset value is 45kHz.

7:0 GFSK_DEV[7:0]

[Description]

1. For details, please refer to “Modulation setting”.

0x32[FSK_DEV0_H/GFIL0]

Function: FSK 1^stfrequency deviation setting (high byte) / Gaussian filter coefficient setting 0

Address: 0x32 (BANK1)

Reset value:0x07

Bit

Bit name

Reset value

00

R/W

Description

Gaussian filter coefficient setting 0

7:6 GFIL0[7:6]

(Note) Gaussian filter coefficient bit range is bit7-0.

FSK 1^stfrequency deviation setting (high 6 bits)/

Gaussian filter coefficient setting 0

FSK_DEV0[13:8]/

GFIL0[5:0]

5:0

00_0111

R/W

(Note) FSK 1^stfrequency can be set comboned with [FSK_DEV0_L/GFIL1:

B1 0x33] register. Reset value is 45kHz.

[Description]

1. For details, please refer to the “Modulation setting”.

2. Gaussian filter coefficient and FSK frequency deviation setting functions are shared in this register.

0x33[FSK_DEV0_L/GFIL1]

Function: FSK 1^stfrequency deviation setting (low byte) / Gaussian filter coefficient setting 1

Address: 0x33 (BANK1)

Reset value:0x16

Bit

Bit name

Reset value

0001_0110

R/W

Description

FSK 1^stfrequency deviation setting (low byte)/

Gaussian filter coefficient setting 1

FSK_DEV0[7:0]/

GFIL1[7:0]

7:0

(Note) FSK 1^stfrequency can be set comboned with [FSK_DEV0_H/GFIL0:

B1 0x32] register. Reset value is 45kHz.

[Description]

1. For details, please refer to the “Modulation setting”.

2. Gaussian filter coefficient and FSK frequency deviation setting functions are shared in this register.

0x34[FSK_DEV1_H/GFIL2]

Function: FSK 2^ndfrequency deviation setting (high byte) / Gaussian filter coefficient setting 2

Address: 0x34 (BANK1)

Reset value:0x07

Bit

Bit name

Reset value

00

R/W

Description

7:6 Reserved

FSK 2^ndfrequency deviation setting (high byte)/

Gaussian filter coefficient setting 2

FSK_DEV1[13:8]/

GFIL2[4:0]

5:0

00_0111

R/W

(Note) FSK 2^ndfrequency can be set comboned with [FSK_DEV1_L/GFIL3:

B1 0x35] register. Reset value is 45kHz.

[Description]

1. For details, please refer to the “Modulation setting”.

2. Gaussian filter coefficient and FSK frequency deviation setting functions are shared in this register.

210/230

FEDL7406-06

ML7406

0x35[FSK_DEV1_L/GFIL3]

Function: FSK 2^ndfrequency deviation setting (low byte) / Gaussian filter coefficient setting 3

Address: 0x35 (BANK1)

Reset value:0x16

Bit

Bit name

Reset value

0001_0110

R/W

Description

FSK 2^ndfrequency deviation setting (low byte)/

Gaussian filter coefficient setting 3

FSK_DEV1[7:0]/

GFIL3[5:0]

7:0

(Note) FSK 2^ndfrequency can be set comboned with [FSK_DEV1_H/GFIL2:

B1 0x34] register. Reset value is 45kHz.

[Description]

1. For details, please refer to the “Modulation setting”.

2. Gaussian filter coefficient and FSK frequency deviation setting functions are shared in this register.

0x36[FSK_DEV2_H/GFIL4]

Function: FSK 3^rdfrequency deviation setting (high byte) / Gaussian filter coefficient setting 4

Address: 0x36 (BANK1)

Reset value:0x07

Bit

Bit name

Reset value

00

R/W

Description

7:6 Reserved

FSK 3^rdfrequency deviation setting (high byte)/

Gaussian filter coefficient setting 4

FSK_DEV2[13:8]/

GFIL4[5:0]

5:0

00_0111

R/W

(Note) FSK 3^rdfrequency can be set comboned with [FSK_DEV2_L/GFIL5:

B1 0x37] register.Reset value is 45kHz.

[Description]

1. For details, please refer to the “Modulation setting”.

2. Gaussian filter coefficient and FSK frequency deviation setting functions are shared in this register.

0x37[FSK_DEV2_L/GFIL5]

Function: FSK 3^rdfrequency deviation setting (low byte) / Gaussian filter coefficient setting 5

Address: 0x37 (BANK1)

Reset value:0x16

Bit

Bit name

Reset value

0001_0110

R/W

Description

FSK 3^rdfrequency deviation setting (low byte)/

Gaussian filter coefficient setting 5

FSK_DEV2[7:0]/

GFIL5[6:0]

7:0

(Note) FSK 3^rdfrequency can be set comboned with [FSK_DEV2_H/GFIL4:

B1 0x36] register. Reset value is 45kHz.

[Description]

1. For details, please refer to the “Modulation setting”.

2. Gaussian filter coefficient and FSK frequency deviation setting functions are shared in this register.

0x38[FSK_DEV3_H/GFIL6]

Function: FSK 4^thfrequency deviation setting (high byte) / Gaussian filter coefficient setting 6

Address: 0x38 (BANK1)

Reset value:0x07

Bit

7

Bit name

Reserved

Reset value

0

R/W

Description

Gaussian filter coefficient setting 6

6

GFIL6[6]

0

R/W

(Note) Gaussian filter coefficient bit range is bit6-0.

FSK 4^thfrequency deviation setting (high byte) /

Gaussian filter coefficient setting 6

FSK_DEV3[13:8]/

GFIL6[5:0]

5:0

00_0111

R/W

(Note) FSK 4^thfrequency can be set comboned with [FSK_DEV3_L: B1 0x39]

register.Reset value is 45kHz.

211/230

FEDL7406-06

ML7406

[Description]

1. For details, please refer to the “Modulation setting”.

2. Gaussian filter coefficient and FSK frequency deviation setting functions are shared in this register.

0x39[FSK_DEV3_L]

Function: FSK 4^thfrequency deviation setting (low byte)

Address: 0x39 (BANK1)

Reset value:0x16

Bit

Bit name

Reset value

0001_0110

R/W

Description

FSK 4^thfrequency deviation setting (low byte)

7:0 FSK_DEV3[7:0]

(Note) FSK 4^thfrequency can be set comboned with [FSK_DEV3_H/GFIL6: B1

0x36] register. Reset value is 45kHz.

[Description]

1. For details, please refer to “Modulation setting”.

0x3A[FSK_DEV4_H]

Function: FSK 5^thfrequency deviation setting (high byte)

Address: 0x3A (BANK1)

Reset value:0x07

Bit

Bit name

Reset value

00

R/W

Description

7:6 Reserved

FSK 5^thfrequency deviation setting (high byte)

5:0 FSK_DEV4[13:8]

00_0111

R/W

(Note) FSK 5^thfrequency can be set comboned with [FSK_DEV4_L: B1

0x3B] register.Reset value is 45kHz.

[Description]

1. For details, please refer to “Modulation setting”.

0x3B[FSK_DEV4_L]

Function: FSK 5^thfrequency deviation setting (low byte)

Address: 0x3B (BANK1)

Reset value:0x16

Bit

Bit name

Reset value

0001_0110

R/W

Description

FSK 5^thfrequency deviation setting (low byte)

7:0 FSK_DEV4[7:0]

(Note) FSK 5^thfrequency can be set comboned with [FSK_DEV4_H: B1

0x3A] register. Reset value is 45kHz.

[Description]

1. For details, please refer to “Modulation setting”.

0x3C[FSK_TIM_ ADJ4]

Function: FSK 4^thfrequency deviation hold time setting

Address: 0x3C (BANK1)

Reset value:0x04

Bit

7

Bit name

Reserved

Reset value

0

000_0100

R/W

Description

6:0 FSK_TIM_ADJ4 [6:0]

FSK 4^thfrequency deviation hold time

[Description]

1. For details, please refer to the “Modulation setting”.

212/230

FEDL7406-06

ML7406

0x3D[FSK_TIM_ ADJ3]

Function: FSK 3^rdfrequency deviation hold time setting

Address: 0x3D (BANK1)

Reset value:0x04

Bit

7

Bit name

Reserved

Reset value

0

000_0100

R/W

Description

FSK 3^rdfrequency deviation hold time

6:0 FSK_TIM_ADJ3[6:0]

[Description]

1. For details, please refer to the “Modulation setting”.

0x3E[FSK_TIM_ ADJ2]

Function: FSK 2^ndfrequency deviation hold time setting

Address: 0x3E (BANK1)

Reset value:0x04

Bit

7

Bit name

Reserved

Reset value

0

000_0100

R/W

Description

FSK 2^ndfrequency deviation hold time

6:0 FSK_TIM_ADJ2[6:0]

[Description]

1. For details, please refer to the “Modulation setting”.

0x3F[FSK_TIM_ ADJ1]

Function: FSK 1^stfrequency deviation hold time setting

Address: 0x3F (BANK1)

Reset value:0x04

Bit

7

Bit name

Reserved

Reset value

0

000_0100

R/W

Description

FSK 1^stfrequency deviation hold time

6:0 FSK_TIM_ADJ[6:0]

[Description]

1. For details, please refer to the “Modulation setting”.

0x40[FSK_TIM_ ADJ0]

Function: FSK no-deviation frequency (carrier frequency) hold time setting

Address: 0x40 (BANK1)

Reset value:0x04

Bit

7

Bit name

Reserved

Reset value

0

000_0100

R/W

Description

FSK no-diviation frequency hold time

6:0 FSK_TIM_ADJ[6:0]

[Description]

1. For details, please refer to the “Modulation setting”.

0x41-0x47[Reserved]

Function:

Address: 0x41-0x47 (BANK1)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

Description

7:0 Reserved

213/230

FEDL7406-06

ML7406

0x48[2DIV_MODE]

Function: Average diversity mode setting

Address: 0x48 (BANK1)

Reset value:0x01

Bit

Bit name

Reset value

000

R/W

Description

7:5 Reserved

Antenna diversity mode setting

4

3

SEARCH_MODE

Reserved

0

R/W

0: disable Antenna diversity FAST mode

1: enable Antenna diversity FAST mode

Average number of ED calculation during Antenna diversity

000: average 1 time

001: average 2 times

010: average 4 times

011: average 8 times

2:0 2DIV_ED_AVG [2:0]

001

R/W

100: average 16 times

101: average 32 times

Other than above: 16 times

[Description]

1. For details, please refer to the “diversity function”.

0x49[2DIV_SEARCH1]

Function: Antenna diversity search time setting

Address: 0x49 (BANK1)

Reset value:0x0E

Bit

7

Bit name

Reserved

Reset value

0

R/W

Description

Antenna diversity search time setting 1

(Note) Search time resolution is 16μs.

6:0 SEARCH_TIME1[6:0]

000_1110

R/W

[Description]

1. For details, please refer to the “diversity function”.

0x4A[2DIV_SEARCH2]

Function: Antenna diversity search time setting

Address: 0x4A (BANK1)

Reset value:0x0E

Bit

7

Bit name

Reserved

Reset value

0

R/W

Description

Antenna diversity search time setting 2

(Note) Search time resolution is 16μs.

6:0 SEARCH_TIME2[6:0]

000_1110

R/W

[Description]

1. For details, please refer to the “diversity function”.

214/230

FEDL7406-06

ML7406

0x4B[2DIV_FAST_LVL]

Function: ED threshold level setting during Antenna diversity FAST mode

Address: 0x4B (BANK1)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

Description

7:0 2DIV_FAST_LVL[7:0]

Antenna diversity FAST mode ED threshold level

0x4C[Reserved]

Function:

Address: 0x4C (BANK1)

Reset value:0x06

Bit

Bit name

Reset value

0000_0110

R/W

Description

7:0 Reserved

0x4D[VCO_CAL_MIN_I]

Function: VCO calibration low limit frequency setting (I counter)

Address: 0x4D (BANK1)

Reset value:0x21

Bit

Bit name

Reset value

00

10_0001

R/W

Description

7:6 Reserved

5:0 VCO_CAL_MIN_I[5:0]

VCO calibration low limit frequency setting - I counter

[Description]

1. For details information of VCO calibration usage, please refer to the “VCO adjustment”

2. For frequency setting method, please refer to the “VCO low limit frequency setting”

(Note)

1. For low limit frequency, please set the frequency 2.2MHz lower than frequency used.

0x4E[VCO_CAL_MIN_FH]

Function: VCO calibration low limit frequency setting (F counter high 4 bits)

Address: 0x4E (BANK1)

Reset value:0x04

Bit

Bit name

Reset value

0000

R/W

Description

VCO calibration low limit frequency setting - F counter high 4 bit

7:4 Reserved

3:0 VCO_CAL_MIN_F[19:16]

0100

[Description]

1. For details information of VCO calibration usage, please refer to the “VCO adjustment”

2. For frequency setting method, please refer to the “VCO low limit frequency setting”

(Note)

1. For low limit frequency, please set the frequency 2.2MHz lower than frequency used.

215/230

FEDL7406-06

ML7406

0x4F[VCO_CAL_MIN_FM]

Function: VCO calibration low limit frequency setting (F counter middle byte)

Address: 0x4F (BANK1)

Reset value:0xEC

Bit

Bit name

Reset value

1110_1100

R/W

Description

VCO calibration low limit frequency setting - F counter middle byte

7:0 VCO_CAL_MIN_F[15:8]

[Description]

1. For details information of VCO calibration usage, please refer to the “VCO adjustment”

2. For frequency setting method, please refer to the “VCO low limit frequency setting”

(Note)

1. For low limit frequency, please set the frequency 2.2MHz lower than frequency used.

0x50[VCO_CAL_MIN_FL]

Function: VCO calibration low limit frequency setting (F counter low byte)

Address: 0x50 (BANK1)

Reset value:0x4E

Bit

Bit name

Reset value

0100_1110

R/W

Description

7:0 VCO_CAL_MIN_F[7:0]

VCO calibration low limit frequency setting - F counter low byte)

[Description]

1. For details information of VCO calibration usage, please refer to the “VCO adjustment”

2. For frequency setting method, please refer to the “VCO low limit frequency setting”

(Note)

1. For low limit frequency, please set the frequency 2.2MHz lower than frequency used.

0x51[VCO_CAL_MAX_N]

Function: VCO calibration upper limit frequency setting

Address: 0x51 (BANK1)

Reset value:0x04

Bit

Bit name

Reset value

0000

R/W

Description

7:4 Reserved

VCO calibration upper frequency limit range setting

(ΔF from low limit frequency)

0000: 0MHz

0001: 0.8125MHz

0010: 1.625MHz

0011: 3.25MHz

3:0 VCO_CAL_MAX_N[3:0]

0100

R/W

0100: 6.5 MHz

0101: 13 MHz

0110: 26 MHz

0111: 52MHz

1000: 82.875MHz

1001: 104MHz

Other setting: prohibit

[Description]

1. For details information of VCO calibration usage, please refer to the “VCO adjustment”

2. For frequency setting method, please refer to the “VCO upper limit frequency setting”

(Note)

1. For upper limit frequency, please set the frequency range that includes the frequency used.

216/230

FEDL7406-06

ML7406

0x52[VCAL_MIN]

Function: VCO calibration low limit value indication and setting

Address: 0x52 (BANK1)

Reset value:0x40

Bit

7

Bit name

Reserved

Reset value

0

R/W

Description

VCO calibration low limit value

6:0 VCAL_MIN[6:0]

100_0000

R/W

(Note) after calibration by [VCO_CAL_START: B0 0x6F], value will be saved

automatically.

[Description]

1. For details usage of VCO calibration, please refer to the “VCO adjustment”

0x53[VCAL_MAX]

Function: VCO calibration upper limit value indication and setting

Address: 0x53 (BANK1)

Reset value:0x40

Bit

7

Bit name

Reserved

Reset value

0

R/W

Description

VCO calibration upper limit value

6:0 VCAL_MAX[6:0]

100_0000

R/W

(Note) after calibration by [VCO_CAL_START: B0 0x6F], value will be saved

automatically.

[Description]

1. For details usage of VCO calibration, please refer to the “VCO adjustment”

0x54-0x55[Reserved]

Function:

Address: 0x54-0x55 (BANK1)

Reset value:0x06

Bit

Bit name

Reset value

0000_0000

R/W

Description

7:0 Reserved

0x56[DEMOD_SET0]

Function: Demodulator configulation 0

Address: 0x56 (BANK1)

Reset value:0x00

Bit

Bit name

Reset value

000

R/W

Description

7:5 Reserved

Symbol timing recovery limiter setting

4

3

2

1

0

STR_LIM_ON

0

R/W

0: turn off limiter

1: turn on limiter

Symbol timing recovery setting

0: constantly tacking symbol timing

1: after SyncWord detection, keeping symbol timing

AFC limiter setting

0: turn on AFC limiter

1: turn off AFC limiter

AFC mode setting

0: constantly performing AFC

1: After SyncWord detection, keeping AFC.

AFC OFF enable setting

0: disable (performing AFC)

1: enable (not performinf AFC)

STR_HOLD_ON

AFC_LIM_OFF

AFC_HOLD_ON

AFC_OFF_EN

217/230

FEDL7406-06

ML7406

(Note)

1. Please use the value specified in the “Register setting”.

0x57[DEMOD_SET1]

Function: Demodulator configulation 1

Address: 0x57 (BANK1)

Reset value:0x14

Bit

Bit name

Reset value

00

R/W

Description

7:6 Reserved

IF edge width setting

00: 1 cycle width

5:4 IFEDGE_SEL[1:0]

01

R/W

01: 2 cycle width

10: 3 cycle width

11: 4 cycle width

Modulation divisor setting

0000: no division

0001: no division

3:0 DEMOD_DIV[3:0]

0100

Other setting : divisor value setting (default 1/4)

(Note)

1. Please use the value specified in the “Register setting”.

0x58[DEMOD_SET2]

Function: Demodulator configulation 2

Address: 0x58 (BANK1)

Reset value:0x28

Bit

7

Bit name

Reserved

Reset value

0

010_1000

R/W

Description

Demodulator LPF1 zero adjustment

6:0 FDET_LPF1_SUB[6:0]

(Note)

1. Please use the value specified in the “Register setting”.

0x59[DEMOD_SET3]

Function: Demodulator configulation 3

Address: 0x59 (BANK1)

Reset value:0x0C

Bit

Bit name

Reset value

000

0_1100

R/W

Description

Demodulator LPF3 zero adjustment

Demodulator LPF2 zero adjustment

7:5 FDET_LPF3_SUB[2:0]

4:0 FDET_LPF2_SUB[4:0]

(Note)

1. Please use the value specified in the “Register setting”.

0x5A[DEMOD_SET4]

Function: Demodulator configulation 4

Address: 0x5A (BANK1)

Reset value:0x24

Bit

Bit name

Reset value

0010

R/W

Description

Demodulator LPF2 cut-off frequency setting

Demodulator LPF1 cut-off frequency setting

7:4 LPF2_SEL[3:0]

3:0 LPF1_SEL[3:0]

0100

(Note)

1. Please use the value specified in the “Register setting”.

218/230

FEDL7406-06

ML7406

0x5B[DEMOD_SET5]

Function: Demodulator configulation 5

Address: 0x5B (BANK1)

Reset value:0x7A

Bit

Bit name

Reset value

R/W

Description

7:6 LPF3_GAIN[1:0]

5:3 LPF2_GAIN[2:0]

2:0 LPF3_SEL[2:0]

01

111

010

Demodulator LPF3 gain setting

Demodulator LPF2 gain setting

Demodulator LPF3 cut-off frequency setting

(Note)

1. Please use the value specified in the “Register setting”.

0x5C[DEMOD_SET6]

Function: Demodulator configulation 6

Address: 0x5C (BANK1)

Reset value:0x27

Bit

Bit name

Reset value

0010_0111

R/W

Description

7:0 RXDEV_RANGE[7:0]

RX frequency deviation range setting

(Note)

1. Please use the value specified in the “Register setting”.

0x5D[DEMOD_SET7]

Function: Demodulator configulation 7

Address: 0x5D (BANK1)

Reset value:0x5F

Bit

Bit name

Reset value

0101_1111

R/W

7:0 AFC_LIM[7:0]

AFC tacking range setting

(Note)

1. Please use the value specified in the “Register setting”.

0x5E[DEMOD_SET8]

Function: Demodulator configulation 8

Address: 0x5E (BANK1)

Reset value:0x03

Bit

Bit name

Reset value

00

R/W

7:6 LPF1_ADJ[1:0]

Demodulator LPF1 adjustment

Demodulator LPF2 clock setting

0: using over 15 kbps

5

LPF2_CLK_SEL

0

R/W

1: using less than or equal 15 kbps

4:3 Reserved

2:0 PLL_AFC_SHIFT[2:0]

00

011

R/W

PLL-AFC magnification adjustment 1

(Note)

1. Please use the value specified in the “Register setting”.

219/230

FEDL7406-06

ML7406

0x5F[DEMOD_SET9]

Function: Demodulator configulation 9

Address: 0x5F (BANK1)

Reset value:0x90

Bit

Bit name

Reset value

1001_0000

R/W

Description

PLL-AFC magnification adjustment 2

7:0 PLL_AFC_CO[7:0]

(Note)

1. Please use the value specified in the “Register setting”.

0x60[DEMOD_SET10]

Function: Demodulator configulation 10

Address: 0x60 (BANK1)

Reset value:0x10

Bit

Bit name

Reset value

000

1_0000

R/W

Description

7:5 Reserved

4:0 STR_PB_LEN[4:0]

Demodulator preamble detection threshold value setting

(Note)

1. Please use the value specified in the “Register setting”.

0x61[DEMOD_SET11]

Function: Demodulator configulation 11

Address: 0x61 (BANK1)

Reset value:0x08

Bit

Bit name

Reset value

000

0_1000

R/W

Description

Demodulator preamble detection threshold value setting (during diversity)

7:5 Reserved

4:0 STR_PB_LEN_DIV[4:0]

(Note)

1. Please use the value specified in the “Register setting”.

0x62[ADDR_CHK_CTR_H]

Function: Address check counter indication (high 3 bit)

Address: 0x62 (BANK1)

Reset value:0x00

Bit

Bit name

Reset value

0000_0

R/W

Description

7:3 Reserved

Indicating the number of packets mismatch during Field checking (high 3 bits)

(Note) combined toghether with [TX_RATE_L: B1 0x63] register.

(Note) Max. count is 2047. Count value can be cleared by

STATE_CLR4([STATE_CLR: B0 0x16(4)]) .

2:0 ADDR_CHK_CTR[10:8]

000

R

[Description]

1. For details, please refer to “Field checking function”.

220/230

FEDL7406-06

ML7406

0x63[ADDR_CHK_CTR_L]

Function: Address check counter indication (low byte)

Address: 0x63 (BANK1)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

R

Description

Indicating the number of packets mismatch during Field checking (low byte)

7:0 ADDR_CHK_CTR[7:0]

For details, please refer to ”[ADDR_CHK_CTR_H:B1 0x62]” register.

[Description]

1. For details, please refer to the “Field checking function”.

0x64[WHT_INIT_H]

Function: Whiteing initialized state setting (high 1 bit)

Address: 0x64 (BANK1)

Reset value:0x01

Bit

Bit name

Reset value

000_0000

1

R/W

Description

7:1 Reserved

0

WHT_INIT[8]

Whiteing initialized state setting (high 1 bit)

[Description]

1. For details, please refer to the “DataWhitening function”.

0x65[WHT_INIT_L]

Function: Whiteing initialized state setting (low byte)

Address: 0x65 (BANK1)

Reset value:0xFF

Bit

Bit name

Reset value

1111_1111

R/W

Description

Whiteing initialized state setting (low byte)

7:0 WHT_INIT[7:0]

[Description]

1. For details, please refer to the “DataWhitening function”.

0x66[WHT_CFG]

Function: Whiteing polynomial setting

Address: 0x66 (BANK1)

Reset value:0x08

Bit

Bit name

Reset value

0000_1000

R/W

Description

7:0 WHT_CFG[7:0]

Whiteing polynomial setting

[Description]

1. For details, please refer to “DataWhitening function”.

0x67-0x7E[Reserved]

Function:

Address: 0x67-0x7E (BANK1)

Reset value:0x00

Bit

Bit name

Reset value

0000_0000

R/W

Description

7:0 Reserved

221/230

FEDL7406-06

ML7406

0x7F[ID_CODE]

Function: ID code indication

Address: 0x7F (BANK1)

Reset value:0x81

Bit

Bit name

Reset value

1000_0001

R/W

Description

7:0 ID[7:0]

ID code

222/230

FEDL7406-06

ML7406

●Register Bank2

0x00[BANK_SEL]

Function: Register access bank selection

Address:0x00 (BANK2)

Reset value:0x11

Bit

7

Bit name

B3_ACEN

Reset value

0

R/W

description

BANK3 register access enable

0: access disable

1: access enable

BANK2 register access enable

0: access disable

1: access enable

BANK1 register access enable

0: access disable

1: access enable

6

5

4

B2_ACEN

B1_ACEN

B0_ACEN

0

1

R/W

BANK0 register access enable

0: access disable

1: access enable

BANK selection

0b0001: BANK0 access

0b0010: BANK1 access

0b0100: BANK2 access

0b1000: BANK3 access

Other setting: prohibit

3-0 BANK[3:0]

0001

R/W

(Note)

1. During VCOcalibration operation, do not access BANK1 registers.

2. Register acess can be done by CLK_INIT_DONE([CLK_SET1: B0 0x02(7)])=0b0.

But the registers related to RF status has to be accessed after CLK_INIT_DONE=0b1.

0x7E[CCA_MASK_SET]

Function: Filter stabilization time setting during CCA

Address:0x7E (BANK2)

Reset value:0x02

Bit

Bit name

Reset value

000

R/W

description

7:5 Reserved

Filter stabilization time setting during CCA

0: disable stabilization time

1: enable stabilization time

4

CCA_MASK_EN

0

R/W

(Note) please refer to the “CCA function” for detail.

3:0 Reserved

0010

223/230

FEDL7406-06

ML7406

●Register Bank3

0x00[BANK_SEL]

Function: Register access bank selection

Address:0x00 (BANK3)

Reset value:0x11

Bit

7

Bit name

B3_ACEN

Reset value

0

R/W

description

BANK3 register access enable

0: access disable

1: access enable

BANK2 register access enable

0: access disable

1: access enable

BANK1 register access enable

0: access disable

1: access enable

6

5

4

B2_ACEN

B1_ACEN

B0_ACEN

0

1

R/W

BANK0 register access enable

0: access disable

1: access enable

BANK selection

0b0001: BANK0 access

0b0010: BANK1 access

0b0100: BANK2 access

0b1000: BANK3 access

Other setting: prohibit

3-0 BANK[3:0]

0001

R/W

(Note)

1. During VCOcalibration operation, do not access BANK1 registers.

2. Register acess can be done by CLK_INIT_DONE([CLK_SET1: B0 0x02(7)])=0b0.

But the registers related to RF status has to be accessed after CLK_INIT_DONE=0b1.

0x23[2MODE_DET]

Function: 2 modes detection setting (MODE-T and MODE-C)

Address:0x23 (BANK3)

Reset value:0x00

Bit

Bit name

Reset value

0000_000

R/W

description

7:1 Reserved

Receiving mode setting

0: receiving Mode-C only

0

2MODE_DET_EN

0

R/W

1: receiveing both Mode-T and Mode –C

(Note) mode chang is inhibited in the RX_ON state. Please change in the

TRX_OFF state.

224/230

FEDL7406-06

ML7406

■Application circuit

The below diagram does not show decoupling capacitors for LSI power pins.

10uF decoupling capacitor should be placed to common 3.3V power pins .

MURATA LQW15series inductors are recommended.

Figure.Direct-Tie exmaple

Figure. Diversity exmaple

225/230

FEDL7406-06

ML7406

■Package Dimensions

Remarks for surface mount type package

Surface mount type package is very sensitive affected by heating from reflow process, humidity during storaging Therefore, in

case of reflow mouting process, please contact sales representative about product name, package name, number of pin, package

code and required reflow process condition (reflow method, temperature, number of reflow process), storage condition.

226/230

FEDL7406-06

ML7406

■Footprint Pattern (Recommendation)

When laying out PC boards, it is important to design the foot pattern so as to give consideration to ease of mounting, bonding,

positioning of parts, reliability, wiring, and elimination of slder bridges.

The optimum design for the foot pattern varies with the materials of the substrate, the sort and thichness of used soldering

paste, and the way of soldering. Therefore when laying out the foot pattern on the PC boards, refer to this figure which mean the

mounting area that the package leads are allowable for soldering PC boards.

P-WQFN32-0505-0.50-A63

227/230

FEDL7406-06

ML7406

■Revision History

page

Before

Release

Document No.

date

Revision description

After

revision revision

Sep 14,

PEDL7406-01

2012

-

Preliminary version

Initial release

June 12,

FEDL7406-01

2013

-

FEDL7406-02

July 9,

2013

14

16

93

14

16

93

Correct 100kbps minimum RX sensitivity

Correct figure of DIO interface characteristics. Initial level of DCLK is modified

from L to H.

Add description for initialization table

157

163

164

157

163

164

Correct note in TXFIFO_THRL[5:0]([TXFIFO_THRL: B0 0x18(5-0)].

Correct note in WAKEUP_MODE([SLEEP/WU_SET: B0 0x2D(6)].

Add note in WUDT_CLK_SET[3:0]([WUT_CLK_SET: B0 0x2E(7-4)].

219

Add RF switch unused example in application circuits example

FEDL7406-03

Jan. 24,

2017

-

Removed SPXO support

48

Add note for Wake-up timer interval and continuous operation timer.

60

Correct description of Antenna diversity search time resolution.

80

83

80

Correct interrupt generation timing of VCO calibration.

Add note in “Temperature masurement function”

Add note in Sync error detected

83

-

122

129

158

165

128

157

163

Add TX_ON signal in “TX Timing-chart”

Add note of [TXFIFO_THRL: B0 0x18]

Add note of RCOSC_MODE[SLEEP/WU_SET: B0 0x2D(3)]

164

175

177

166

177

179

Add note of WUDT_CLK_SET[WUT_CLK_SET: B0 0x2E(7-4)]

Add note of TEMP_ADC_OUT[MON_CTRL: B0 0x4D(5)].

Correct function description of EXT_CLK pin configuration

setting(EXTCLK_IO_CFG[EXTCLK_CTRL: B0 0x52(2-0)])

Correct function description of external setting

EXT_PA_CNT[SPI/EXT_PA_CTRL: B0 0x53(1)] and

EXT_PA_EN[SPI/EXT_PA_CTRL: B0 0x53(0)]

178

180

182

190

184

192

Removed registers B0 0x64-0x65

Add note of [CLK_OUT: B1 0x01]

197

200

Removed registers bit6-4 of [AFC_CTRL: B1 0x15]

Remove a register SEARCH_TIME_SET([2DIV_SEARCH1: B1 0x49(7)]).

Antenna diversity search time resolution is 16μs.

208

211

FEDL7406-04

Feb. 23,

2017

48

Correct fomula of continuous operation timer in Wake-up timer.

164

166

Correct fomula of Wake-up timer in [WUT_INTERVAL_H: B0 0x2F] register

Correct fomula of continuous operation timer in [WU_DURATION: B0 0x31]

register

165

23

167

23

FEDL7406-05

FEDL7406-06

July 20,

2018

Add note of SLEEP setting

48

192

7-8

8

48

194

7-8

8

Add note of Wake-up Timer

Add register [REGULATOR_CTRL: B1 0x07]

[Pin-definition] correct definition in reset state of pins

[Pin-definition]-[Regulator Pins] delete detail (*1)

Apr 12,

2019

228/230

FEDL7406-06

ML7406

page

Before

Release

date

Document No.

Revision description

After

revision revision

17

[Electrical Characteristics]-[Reset Characteristics] delete RESETN rising time.

[Function Description]-[Packet Handling Function]-[FIFO control function] add

note(2)

41

[LSI Adjustment items and Adjustment Method]-[VCO adjustment]

Correct VCO calibration range setting(delete 82.875, 104MHz)

[Flowchart]-[Turn On Sequence] Correct SPI access prohibited section

90

99

90

99

129-13 [Time Chart]-[Start-up] Correct SPI access prohibited

128

144

145

0

section(ML7406C/ML7406T)

146

[CLK_SET2: B0 0x03] add note 4

[PKT_CTRL1: B0 0x04] add note of Extended Link Layer mode setting

(Wireless M-Bus)

147

146

174

148

176

[PKT_CTRL2: B0 0x05] add note for CRC disabling setting

[SYNC_CONDITION1: B0 0x45] add register description

(Note) Corrections in spelling , improvements in the description are not included in the Revision history.

229/230

FEDL7406-06

ML7406

NOTES

1) The information contained herein is subject to change without notice.

2) Although LAPIS Semiconductor is continuously working to improve product reliability and quality, semiconductors can

break down and malfunction due to various factors. Therefore, in order to prevent personal injury or fire arising from failure,

please take safety measures such as complying with the derating characteristics, implementing redundant and fire

prevention designs, and utilizing backups and fail-safe procedures. LAPIS Semiconductor shall have no responsibility for

any damages arising out of the use of our Products beyond the rating specified by LAPIS Semiconductor.

3) Examples of application circuits, circuit constants and any other information contained herein are provided only to illustrate

the standard usage and operations of the Products.The peripheral conditions must be taken into account when designing

circuits for mass production.

4) The technical information specified herein is intended only to show the typical functions of the Products and examples of

application circuits for the Products. No license, expressly or implied, is granted hereby under any intellectual property

rights or other rights of LAPIS Semiconductor or any third party with respect to the information contained in this

document; therefore LAPIS Semiconductor shall have no responsibility whatsoever for any dispute, concerning such rights

owned by third parties, arising out of the use of such technical information.

5) The Products are intended for use in general electronic equipment (i.e. AV/OA devices, communication, consumer systems,

gaming/entertainment sets) as well as the applications indicated in this document.

6) The Products specified in this document are not designed to be radiation tolerant.

7) For use of our Products in applications requiring a high degree of reliability (as exemplified below), please contact and

consult with a LAPIS Semiconductor representative: transportation equipment (i.e. cars, ships, trains), primary

communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and

power transmission systems.

8) Do not use our Products in applications requiring extremely high reliability, such as aerospace equipment, nuclear power

control systems, and submarine repeaters.

9) LAPIS Semiconductor shall have no responsibility for any damages or injury arising from non-compliance with the

recommended usage conditions and specifications contained herein.

10) LAPIS Semiconductor has used reasonable care to ensure the accuracy of the information contained in this document.

However, LAPIS Semiconductor does not warrant that such information is error-free and LAPIS Semiconductor shall have

no responsibility for any damages arising from any inaccuracy or misprint of such information.

11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive.

For more details, including RoHS compatibility, please contact a ROHM sales office. LAPIS Semiconductor shall have no

responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations.

12) When providing our Products and technologies contained in this document to other countries, you must abide by the

procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US

Export Administration Regulations and the Foreign Exchange and Foreign Trade Act.

13) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Semiconductor.

2-4-8 Shinyokohama, Kouhoku-ku,

Yokohama 222-8575, Japan

http://www.lapis-semi.com/en/

230/230


型号：	ML7406
厂家：	ROHM
描述：	ML7406是支持750MHz～960MHz频段的低功耗Sub-GHz宽频无线LSI。ML7406主要用于ISM（Industrial, Scientific and Medical）频段和SRD（Short Range Device）用频段的无线基站。其中还特别内置了欧洲智能仪表通信标准（EN13757-4:2011：Wireless M-BUS）数据包格式的收发功能。通信无线仪表 ISM频段
文件：	总231页 (文件大小：2865K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ML7406 [ROHM]

相关型号：

ML7416N

ML7436N

ML7456N (新产品)

ML74UL00

ML74UL02

ML74UL04

ML74UL08

ML74UL32

ML74UL34

ML74UL4066

ML74WL00

ML74WL02