M12S128324A-6TG [ESMT]
1M x 32 Bit x 4 Banks Synchronous DRAM; 1M ×32位×4银行同步DRAM
| 型号： | M12S128324A-6TG |
| 厂家： | 
ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. |
| 描述： | 1M x 32 Bit x 4 Banks Synchronous DRAM |
| 文件： | 总46页 (文件大小：742K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESMT
SDRAM
M12S128324A
1M x 32 Bit x 4 Banks
Synchronous DRAM
FEATURES
y
y
y
y
JEDEC standard 2.5V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
- CAS Latency (1, 2 & 3 )
- Burst Length ( 1, 2, 4, 8 & full page )
- Burst Type ( Sequential & Interleave )
All inputs are sampled at the positive going edge of the
system clock
y
y
y
y
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
ORDERING INFORMATION
MAX
Product No.
PACKAGE COMMENTS
FREQ.
M12S128324A-6TG 166MHz 86 TSOPII
M12S128324A-6BG 166MHz 90 FBGA
M12S128324A-7TG 143MHz 86 TSOPII
Pb-free
Pb-free
Pb-free
Pb-free
M12S128324A-7BG 143MHz
90 FBGA
GENERAL DESCRIPTION
The M12S128324A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system applications.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4 1/46
ESMT
M12S128324A
PIN ARRANGEMENT
Top View
V
DD
1
V S S
8 6
8 5
8 4
8 3
8 2
8 1
8 0
7 9
7 8
7 7
7 6
7 5
7 4
7 3
7 2
7 1
7 0
6 9
6 8
6 7
D Q 0
V D DQ
D Q 1
D Q 2
V S S Q
D Q 3
D Q 4
V D DQ
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
D Q 15
V S SQ
D Q 14
D Q 13
V D D Q
D Q 12
D Q 11
V S SQ
D Q 10
D Q 9
D Q 5
D Q 6
V S S Q
D Q 7
N C
V D D Q
D Q 8
N C
V
DD
V S S
D Q M0
W E
D Q M 1
N C
C A S
R A S
C S
N C
C LK
C K E
A 9
A 11
21
22
23
24
25
26
27
28
29
3 0
3 1
3 2
3 3
3 4
3 5
3 6
3 7
3 8
3 9
6 6
6 5
6 4
6 3
6 2
6 1
6 0
5 9
5 8
5 7
5 6
5 5
5 4
5 3
5 2
5 1
5 0
4 9
4 8
4 7
4 6
4 5
4 4
A 8
B A 0
B A 1
A 1 0/A P
A 0
A 7
A 6
A 5
A 4
A 1
A 3
A 2
D Q M 3
D Q M2
V S
S
V D
D
N C
D Q 16
V S SQ
N C
D Q 3 1
V D D Q
D Q 3 0
D Q 2 9
V S SQ
D Q 2 8
D Q 2 7
V D D Q
D Q 2 6
D Q 2 5
V S SQ
D Q 2 4
D Q 17
D Q 18
V D D Q
D Q 19
D Q 20
V S SQ
D Q 21
D Q 22
V D D Q
4 0
4 1
D Q 23 4 2
86 P i n T S O P ( II)
( 400 m il 8 75m i l)
( 0.5 mm P in pi tc h)
4 3
V
D D
V S
S
x
90 Ball FBGA
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
DQ26 DQ24 VSS
DQ28 VDDQ VSSQ
VSSQ DQ27 DQ25
VSSQ DQ29 DQ30
VDDQ DQ31 NC
VSS DQM3 A3
VDD DQ23 DQ21
VDDQ VSSQ DQ19
DQ22 DQ20 VDDQ
DQ17 DQ18 VDDQ
NC DQ16 VSSQ
A2 DQM2 VDD
G
H
J
A4
A7
A5
A8
A6
NC
A9
A10
NC
A0
BA1
CS
A1
A11
CLK CKE
DQM1 NC
BA0
CAS
RAS
DQM0
K
L
NC
WE
VDDQ DQ8 VSS
VSSQ DQ10 DQ9
VSSQ DQ12 DQ14
DQ11 VDDQ VSSQ
DQ13 DQ15 VSS
VDD DQ7 VSSQ
DQ6 DQ5 VDDQ
DQ1 DQ3 VDDQ
VDDQ VSSQ DQ4
VDD DQ0 DQ2
M
N
P
R
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4
2/46
ESMT
M12S128324A
BLOCK DIAGRAM
CLK
Clock
Generator
Bank D
Bank C
Bank B
CKE
Row
Address
Buffer
&
Refresh
Counter
Address
Bank A
Mode
Register
Sense Amplifier
Column Decoder
DQM0~3
Column
Address
Buffer
&
Refresh
Counter
CS
RAS
CAS
WE
Data Control Circuit
DQ
PIN DESCRIPTION
PIN
NAME
INPUT FUNCTION
CLK
CS
System Clock
Active on the positive going edge to sample all inputs
Disables or enables device operation by masking or enabling all
inputs except CLK , CKE and DQM0-3.
Chip Select
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior new command.
Disable input buffers for power down in standby.
CKE
Clock Enable
Address
Row / column address are multiplexed on the same pins.
Row address : RA0~RA11, column address : CA0~CA7
A0 ~ A11
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
BA0 , BA1
Bank Select Address
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with
RAS low.
RAS
Enables row access & precharge.
Latches column address on the positive going edge of the CLK with
Column Address Strobe
Write Enable
CAS
WE
CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS , WE active.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4
3/46
ESMT
M12S128324A
PIN
NAME
INPUT FUNCTION
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
DQM0~3
Data Input / Output Mask
DQ0 ~ DQ31
Data Input / Output
Data inputs / outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
VDD / VSS
Power Supply / Ground
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
VDDQ / VSSQ
Data Output Power / Ground
No Connection
N.C
This pin is recommended to be left No Connection on the device.
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
Value
Unit
V
Voltage on any pin relative to VSS
Voltage on VDD supply relative to VSS
Storage temperature
-1.0 ~ 3.6
-1.0 ~ 3.6
-55 ~ +150
V
°C
W
Power dissipation
PD
IOS
1
Short circuit current
50
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITION
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C )
Parameter
Supply voltage
Symbol
Min
Typ
Max
Unit
Note
VDD, VDDQ
2.375
2.5
2.625
V
1
(for -6)
V
DD, VDDQ
2.3
0.8xVDDQ
-0.3
2.5
2.5
0
2.7
V
V
1
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
VIH
VDDQ+0.3
2
VIL
0.3
-
V
3
VOH
VDDQ -0.2
-
-
V
IOH = -0.1mA
IOL = 0.1mA
4
VOL
-
0.2
V
μ A
Input leakage current
ILI
-2
-
2
Note:
1. Under all conditions, VDDQ must be less than or equal to VDD
.
2. VIH(max) = 3.0V AC. The overshoot voltage duration is ≤ 3ns.
3. VIL(min) = -1.0V AC. The undershoot voltage duration is ≤ 3ns.
4. Any input 0V ≤ VIN ≤ VDDQ
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
5. Dout is disabled , 0V ≤ VOUT ≤ VDDQ.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4 4/46
ESMT
M12S128324A
CAPACITANCE (VDD = 2.5V, TA = 25°C, f = 1MHZ)
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0 ~ A11, BA0 ~ BA1)
CIN1
2
4
4
5
pF
Input capacitance
CIN2
2
2
pF
pF
(CLK, CKE, CS , RAS , CAS , WE & DQM)
Data input/output capacitance (DQ0 ~ DQ31)
COUT
DC CHARACTERISTICS
Recommended operating condition unless otherwise noted，TA = 0 to 70°C
Version
Test Condition
Parameter
Symbol
Unit Note
-6
-7
Burst Length = 1
tRC ≥ tRC(min)
Operating Current
(One Bank Active)
ICC1
mA
mA
1,2
110
90
IOL = 0 mA
ICC2P
0.8
0.6
CKE ≤ VIL(max), tcc = 10ns
Precharge Standby Current
in power-down mode
ICC2PS
CKE & CLK ≤ VIL(max), tcc = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tcc = 10ns
ICC2N
25
7
Input signals are changed one time during 20ns
Precharge Standby Current
in non power-down mode
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tcc = ∞
input signals are stable
ICC2NS
ICC3P
3
3
CKE ≤ VIL(max), tcc = 10ns
Active Standby Current
in power-down mode
mA
mA
ICC3PS
CKE & CLK ≤ VIL(max), tcc = ∞
ICC3N
CKE ≥ VIH(min), CS ≥ VIH(min), tcc = 15ns
Input signals are changed one time during 2clks
Active Standby Current
in non power-down mode
(One Bank Active)
30
All other pins ≥ VDD-0.2V or ≤ 0.2V
CKE ≥ VIH(min), CLK ≤ VIL(max), tcc = ∞
ICC3NS
10
mA
mA
input signals are stable
I
OL = 0 mA
Operating Current
(Burst Mode)
Page Burst
2 Banks activated
tCK = tCK(min)
ICC4
180
180
160
160
1,2
Refresh Current
ICC5
ICC6
mA
mA
tRC ≥ tRC(min)
Self Refresh Current
2
CKE ≤ 0.2V
Note : 1. Measured with outputs open. Addresses are changed only one time during tCC(min)
.
2. Refresh period is 64ms. A maximum of eight consecutive AUTO REFRESH commands (with tRFCmin) can be posed to
any given SDRAM, and the maximum absolute internal between any AUTO REFRSH command and the next AUTO
REFRESH command is 8x15.6μm. Addresses are changed only one time during tCC(min)
.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4 5/46
ESMT
M12S128324A
AC OPERATING TEST CONDITIONS [VDD = 2.5V± 0.2V, VDD = 2.375V~2.625V (for -6), TA = 0 to 70°C]
Parameter
Input levels (Vih/Vil)
Value
0.9XVDDQ / 0.2
0.5xVDDQ
Unit
V
Input timing measurement reference level
Input rise and fall-time
V
tr/tf = 1/1
ns
V
Output timing measurement reference level
Output load condition
0.5xVDDQ
See Fig. 2
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
Unit
Note
-6
-7
Row active to row active delay
RAS to CAS delay
tRRD(min)
12
14
ns
ns
1
1
tRCD(min)
18
18
42
18
20
42
Row precharge time
tRP(min)
ns
ns
us
ns
1
1
tRAS(min)
Row active time
tRAS
100
(max)
Row cycle time
@ Operating
tRC(min)
60
75
70
84
1
@ Auto Refresh
tRFC(min)
tCDL(min)
tRDL(min)
tBDL(min)
Last data in to col. address delay
Last data in to row precharge
Last data in to burst stop
1
2
1
CLK
CLK
CLK
2
2
2
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4 6/46
ESMT
M12S128324A
Version
Parameter
Symbol
Unit
Note
-6
-7
Col. address to col. address delay
tCCD(min)
1
2
CLK
ea
3
4
CAS latency = 3
Number of valid
Output data
CAS latency = 2
CAS latency = 1
1
0
Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
AC CHARACTERISTICS (AC operating condition unless otherwise noted)
-6
-7
Parameter
Symbol
Unit
Note
Min
6
Max
Min
7
Max
CAS latency = 3
CLK cycle time
tCC
1000
1000
ns
1
CAS latency = 2
CAS latency = 1
CAS latency = 3
CAS latency = 2
CAS latency = 1
CAS latency = 3
CAS latency = 2
CAS latency = 1
8
8.6
20
20
5.8
7
6
7
CLK to valid
output delay
tSAC
ns
ns
1,2
2
17
18
2
2
2
2
2
2
1
1
2
2
Output data
hold time
tOH
2
CLK high pulsh width
CLK low pulsh width
Input setup time
tCH
tCL
2.5
2.5
2
ns
ns
ns
ns
ns
3
3
3
3
2
tSS
tSH
tSLZ
Input hold time
1
CLK to output in Low-Z
1
CAS latency = 3
CAS latency = 2
CAS latency = 1
5.8
7
6
7
CLK to output
in Hi-Z
tSHZ
ns
-
17
18
Note : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns. (tr/2 - 0.5) ns should be considered.
3. Assumed input rise and fall time (tr & tf) =1ns.
If tr & tf is longer than 1ns. transient time compensation should be considered.
i.e., [(tr + tf)/2 – 1] ns should be added to the parameter.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4 7/46
ESMT
M12S128324A
SIMPLIFIED TRUTH TABLE
A11,A9~A0
COMMAND
CKEn-1 CKEn
DQM BA0,1 A10/AP
Note
1,2
3
CS RAS CAS WE
Register
Refresh
Mode Register set
Auto Refresh
H
X
H
L
L
L
L
L
X
OP CODE
H
L
L
L
H
X
X
3
Entry
Self
3
Refresh
L
H
L
H
X
L
H
X
H
H
X
H
X
X
X
Exit
L
H
H
H
X
X
X
3
Bank Active & Row Addr.
V
V
Row Address
Auto Precharge Disable
L
Column
Address
(A0~A7)
4
Read &
L
H
L
H
X
Column Address
Auto Precharge Enable
Auto Precharge Disable
H
L
4,5
4
Column
Address
(A0~A7)
Write &
H
H
H
X
X
X
L
L
L
H
H
L
L
H
H
L
L
L
X
X
X
V
Column Address
Auto Precharge Enable
H
4,5
6
Burst Stop
X
Bank Selection
All Banks
V
X
L
Precharge
X
H
H
L
X
V
X
X
V
X
X
V
X
Clock Suspend or
Active Power Down
Entry
Exit
H
L
L
H
L
X
X
X
X
X
H
L
X
H
X
V
X
H
X
V
X
H
X
V
Entry
H
X
Precharge Power Down Mode
H
L
Exit
L
H
X
X
DQM
H
H
X
X
V
X
X
X
7
H
L
X
H
X
H
No Operating Command
H
(V = Valid , X = Don’t Care. H = Logic High , L = Logic Low )
Note : 1.OP Code : Operating Code
A0~A11 & BA0~BA1 : Program keys. (@ MRS)
2.MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3.Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge of command is meant by “Auto”.
Auto/self refresh can be issued only at all banks idle state.
4.BA0~BA1 : Bank select addresses.
If both BA1 and BA0 are “Low” at read ,write , row active and precharge ,bank A is selected.
If both BA1 is “Low” and BA0 is “High” at read ,write , row active and precharge ,bank B is selected.
If both BA1 is “High” and BA0 is “Low” at read ,write , row active and precharge ,bank C is selected.
If both BA1 and BA0 are “High” at read ,write , row active and precharge ,bank D is selected
If A10/AP is “High” at row precharge , BA1 and BA0 is ignored and all banks are selected.
5.During burst read or write with auto precharge. new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6.Burst stop command is valid at every burst length.
7.DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (write DQM latency is 0), but
makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4 8/46
ESMT
M12S128324A
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address
Function
BA0~BA1
RFU
A11
A10/AP
RFU
A9
A8
A7
A6
A5
A4
A3
BT
A2
A1
A0
RFU
W.B.L
TM
CAS Latency
Burst Length
Test Mode
CAS Latency
Burst Type
Burst Length
A8
0
A7
Type
A6
0
A5
0
A4
0
Latency
A3
Type
A2
0
A1
0
A0
0
BT = 0
BT = 1
0
1
0
1
Mode Register Set
Reserved
Reserved
1
0
1
Sequential
Interleave
1
2
4
8
1
2
4
8
0
0
0
1
0
0
1
1
Reserved
0
1
0
2
0
1
0
1
Reserved
0
1
1
3
0
1
1
Write Burst Length
Length
1
0
0
Reserved
Reserved
Reserved
Reserved
1
0
0
Reserved Reserved
Reserved Reserved
Reserved Reserved
Full Page Reserved
A9
0
1
0
1
1
0
1
Burst
1
1
0
1
1
0
1
Single Bit
1
1
1
1
1
1
Full Page Length : 256
Note : 1. RFU(Reserved for future use) should stay “0” during MRS cycle.
2. If A9 is high during MRS cycle, “ Burst Read single Bit Write” function will be enabled.
3. The full column burst (256 bit) is available only at sequential mode of burst type.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4 9/46
ESMT
M12S128324A
BURST SEQUENCE (BURST LENGTH = 4)
Initial Address
Sequential
Interleave
A1
0
A0
0
0
1
2
3
1
2
3
0
2
3
0
1
3
0
1
2
0
1
2
3
1
0
3
2
2
3
0
1
3
2
1
0
0
1
1
0
1
1
BURST SEQUENCE (BURST LENGTH = 8)
Initial
Sequential
Interleave
A2
A1
A0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
0
2
3
4
5
6
7
0
1
3
4
5
6
7
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
6
0
1
0
3
2
5
4
7
6
2
3
2
1
0
7
6
5
4
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
6
5
4
3
2
1
0
7
0
1
2
3
4
5
1
2
3
4
5
6
7
3
0
1
6
7
4
5
7
4
5
2
3
0
1
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4 10/46
ESMT
M12S128324A
DEVICE OPERATIONS
CLOCK (CLK)
POWER-UP
The clock input is used as the reference for all SDRAM
operations.All operations are synchronized to the positive
going edge of the clock. The clock transitions must be
monotonic between VIL and VIH. During operation with CKE
high all inputs are assumed to be in valid state (low or high) for
the duration of setup and hold time around positive edge of the
clock for proper functionality and Icc specifications.
1.Apply power and start clock, Attempt to maintain CKE =
“H”, DQM = “H” and the other pins are NOP condition at
the inputs.
2.Maintain stable power, stable clock and NOP input
condition for minimum of 200us.
3.Issue precharge commands for all banks of the devices.
4.Issue 2 or more auto-refresh commands.
5.Issue a mode register set command to initialize the
mode register.
CLOCK ENABLE(CKE)
cf.) Sequence of 4 & 5 is regardless of the order.
The clock enable (CKE) gates the clock onto SDRAM. If CKE
goes low synchronously with clock (set-up and hold time same
as other inputs), the internal clock suspended from the next
clock cycle and the state of output and burst address is frozen
as long as the CKE remains low. All other inputs are ignored
from the next clock cycle after CKE goes low. When all banks
are in the idle state and CKE goes low synchronously with
clock, the SDRAM enters the power down mode from the next
clock cycle. The SDRAM remains in the power down mode
ignoring the other inputs as long as CKE remains low. The
power down exit is synchronous as the internal clock is
suspended. When CKE goes high at least “1CLK + tSS” before
the high going edge of the clock, then the SDRAM becomes
active from the same clock edge accepting all the input
commands.
The device is now ready for normal operation.
MODE REGISTER SET (MRS)
The mode register stores the data for controlling the
various operating modes of SDRAM. It programs the
CAS latency, burst type, burst length, test mode and
various vendor specific options to make SDRAM useful
for variety of different applications. The default value of
the mode register is not defined, therefore the mode
register must be written after power up to operate the
SDRAM. The mode register is written by asserting low
on CS , RAS , CAS and WE (The SDRAM should
be in active mode with CKE already high prior to writing
the mode register). The state of address pins A0~A11
and BA0~BA1 in the same cycle as CS , RAS , CAS
BANK ADDRESSES (BA0~BA1)
and WE going low is the data written in the mode
register. Two clock cycles is required to complete the
write in the mode register. The mode register contents
can be changed using the same command and clock
cycle requirements during operation as long as all
banks are in the idle state. The mode register is divided
into various fields into depending on functionality. The
burst length field uses A0~A2, burst type uses A3, CAS
latency (read latency from column address) use A4~A6,
vendor specific options or test mode use A7~A8,
A10/AP~A11 and BA0~BA1. The write burst length is
programmed using A9. A7~A9, A10/AP~A11 and
BA0~BA1 must be set to low for normal SDRAM
operation. Refer to the table for specific codes for
various burst length, burst type and CAS latencies.
This SDRAM is organized as four independent banks of
524,288 words x 32 bits memory arrays. The BA0~BA1 inputs
are latched at the time of assertion of RAS and CAS to
select the bank to be used for the operation. The banks
addressed BA0~BA1 are latched at bank active, read, write,
mode register set and precharge operations.
ADDRESS INPUTS (A0~A11)
The 20 address bits are required to decode the 524,288 word
locations are multiplexed into 12 address input pins (A0~A11).
The 12 row addresses are latched along with RAS and
BA0~BA1 during bank active command. The 8 bit column
addresses are latched along with CAS , WE and BA0~BA1
during read or with command.
BANK ACTIVATE
The bank activate command is used to select a random
row in an idle bank. By asserting low on RAS and
NOP and DEVICE DESELECT
When RAS
, CAS and WE are high , The SDRAM
CS with desired row and bank address, a row access
is initiated. The read or write operation can occur after a
time delay of tRCD (min) from the time of bank activation.
tRCD is the internal timing parameter of SDRAM,
therefore it is dependent on operating clock frequency.
The minimum number of clock cycles required between
bank activate and read or write command should be
calculated by dividing tRCD (min) with cycle time of the
clock and then rounding of the result to the next higher
integer.
performs no operation (NOP). NOP does not initiate any new
operation, but is needed to complete operations which require
more than single clock cycle like bank activate, burst read,
auto refresh, etc. The device deselect is also a NOP and is
entered by asserting CS high. CS high disables the
command decoder so that RAS , CAS , WE and all the
address inputs are ignored.
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M12S128324A
DEVICE OPERATIONS (Continued)
The SDRAM has four internal banks in the same chip and
shares part of the internal circuitry to reduce chip area,
therefore it restricts the activation of four banks
simultaneously. Also the noise generated during sensing of
each bank of SDRAM is high requiring some time for power
supplies to recover before another bank can be sensed
reliably. tRRD (min) specifies the minimum time required between
activating different bank. The number of clock cycles required
between different bank activation must be calculated similar to
tRCD (min) specification. The minimum time required for the bank
to be active to initiate sensing and restoring the complete row
of dynamic cells is determined by tRAS (min). Every SDRAM bank
activate command must satisfy tRAS (min) specification before a
precharge command to that active bank can be asserted. The
maximum time any bank can be in the active state is
determined by tRAS (max) and tRAS (max) can be calculated
similar to tRCD specification.
DQM OPERATION
The DQM is used mask input and output operations. It
works similar to OE during operation and inhibits writing
during write operation. The read latency is two cycles from
DQM and zero cycle for write, which means DQM masking
occurs two cycles later in read cycle and occurs in the
same cycle during write cycle. DQM operation is
synchronous with the clock. The DQM signal is important
during burst interrupts of write with read or precharge in
the SDRAM. Due to asynchronous nature of the internal
write, the DQM operation is critical to avoid unwanted or
incomplete writes when the complete burst write is
required. Please refer to DQM timing diagram also.
PRECHARGE
The precharge is performed on an active bank by
asserting low on clock cycles required between bank
activate and clock cycles required between bank activate
BURST READ
The burst read command is used to access burst of data on
consecutive clock cycles from an active row in an active bank.
and CS , RAS , WE and A10/AP with valid BA0~BA1
of the bank to be procharged. The precharge command
can be asserted anytime after tRAS (min) is satisfy from the
bank active command in the desired bank. tRP is defined
as the minimum number of clock cycles required to
complete row precharge is calculated by dividing tRP with
clock cycle time and rounding up to the next higher
integer. Care should be taken to make sure that burst
write is completed or DQM is used to inhibit writing before
precharge command is asserted. The maximum time any
bank can be active is specified by tRAS (max). Therefore,
each bank activate command. At the end of precharge,
the bank enters the idle state and is ready to be activated
again. Entry to power-down, Auto refresh, Self refresh and
Mode register set etc. is possible only when all banks are
in idle state.
The burst read command is issued by asserting low on CS
and RAS with WE being high on the positive edge of the
clock. The bank must be active for at least tRCD (min) before the
burst read command is issued. The first output appears in CAS
latency number of clock cycles after the issue of burst read
command. The burst length, burst sequence and latency from
the burst read command is determined by the mode register
which is already programmed. The burst read can be initiated
on any column address of the active row. The address wraps
around if the initial address does not start from a boundary
such that number of outputs from each I/O are equal to the
burst length programmed in the mode register. The output
goes into high-impedance at the end of burst, unless a new
burst read was initiated to keep the data output gapless. The
burst read can be terminated by issuing another burst read or
burst write in the same bank or the other active bank or a
precharge command to the same bank. The burst stop
command is valid at every page burst length.
AUTO PRECHARGE
The precharge operation can also be performed by using
auto precharge. The SDRAM internally generates the
timing to satisfy tRAS (min) and “tRP” for the programmed
burst length and CAS latency. The auto precharge
command is issued at the same time as burst write by
asserting high on A10/AP, the bank is precharge command
is asserted. Once auto precharge command is given, no
new commands are possible to that particular bank until
the bank achieves idle state.
BURST WRITE
The burst write command is similar to burst read command
and is used to write data into the SDRAM on consecutive clock
cycles in adjacent addresses depending on burst length and
burst sequence. By asserting low on CS , CAS and WE
with valid column address, a write burst is initiated. The data
inputs are provided for the initial address in the same clock
cycle as the burst write command. The input buffer is
deselected at the end of the burst length, even though the
internal writing can be completed yet. The writing can be
complete by issuing a burst read and DQM for blocking data
inputs or burst write in the same or another active bank. The
burst stop command is valid at every burst length. The write
burst can also be terminated by using DQM for blocking data
and procreating the bank tRDL after the last data input to be
written into the active row. See DQM OPERATION also.
ALL BANKS PRECHARGE
Four banks can be precharged at the same time by using
Precharge all command. Asserting low on CS , RAS ,
and WE with high on A10/AP after all banks have
satisfied tRAS (min) requirement, performs precharge on all
banks. At the end of tRP after performing precharge all, all
banks are in idle state.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4
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M12S128324A
DEVICE OPERATIONS (Continued)
AUTO REFRESH
SELF REFRESH
The storage cells of SDRAM need to be refreshed every 64ms
to maintain data. An auto refresh cycle accomplishes refresh of
a single row of storage cells. The internal counter increments
automatically on every auto refresh cycle to refresh all the
rows. An auto refresh command is issued by asserting low on
The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode for
data retention and low power operation of SDRAM. In self
refresh mode, the SDRAM disables the internal clock and
all the input buffers except CKE. The refresh addressing
and timing is internally generated to reduce power
consumption.
CS , RAS and CAS with high on CKE and WE . The auto
refresh command can only be asserted with all banks being in
idle state and the device is not in power down mode (CKE is
high in the previous cycle). The time required to complete the
auto refresh operation is specified by tRC (min). The minimum
number of clock cycles required can be calculated by driving
tRC with clock cycle time and them rounding up to the next
higher integer. The auto refresh command must be followed by
NOP’s until the auto refresh operation is completed. The auto
refresh is the preferred refresh mode when the SDRAM is
being used for normal data transactions. The auto refresh
cycle can be performed once in 15.6us or the burst of 4096
auto refresh cycles in 40ms.
The self refresh mode is entered from all banks idle state
by asserting low on CS , RAS , CAS and CKE with
high on WE . Once the self refresh mode is entered, only
CKE state being low matters, all the other inputs including
clock are ignored to remain in the refresh.
The self refresh is exited by restarting the external clock
and then asserting high on CKE. This must be followed by
NOP’s for a minimum time of tRC before the SDRAM
reaches idle state to begin normal operation. 4K cycles of
burst auto refresh is required immediately before self
refresh entry and immediately after self refresh exit.
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COMMANDS
CLK
Mode register set command
H
CKE
( CS ,RAS , CAS , WE = Low)
CS
RAS
CAS
The device has a mode register that defines how the device operates. In this
command, A0 through A11 and BA0~BA1 are the data input pins. After power on, the
mode register set command must be executed to initialize the device.
The mode register can be set only when all banks are in idle state.
During 2CLK following this command, the device cannot accept any other
commands.
WE
BA0, BA1
(Bank select)
A10
Add
Fig. 1 Mode register set
command
Activate command
CLK
( CS ,RAS = Low, CAS , WE = High)
H
CKE
The device has four banks, each with 2,048 rows.
This command activates the bank selected by BA1 and BA0 and a row address
selected by A0 through A11.
CS
RAS
CAS
This command corresponds to a conventional DRAM’s RAS falling.
WE
BA0, BA1
(Bank select)
Row
Row
A10
Add
Fig. 2 Row address stroble and
bank active command
CLK
Precharge command
H
CKE
( CS ,RAS , WE = Low, CAS = High )
CS
RAS
CAS
WE
This command begins precharge operation of the bank selected by BA1 and BA0.
When A10 is High, all banks are precharged, regardless of BA1 and BA0. When A10
is Low, only the bank selected by BA1 and BA0 is precharged.
After this command, the device can’t accept the activate command to the
precharging bank during tRP (precharge to activate command period).
This command corresponds to a conventional DRAM’s RAS rising.
BA0, BA1
(Bank select)
A10
(Precharge select)
Add
Fig. 3 Precharge command
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Write command
CLK
( CS , CAS , WE = Low, RAS = High)
H
CKE
CS
If the mode register is in the burst write mode, this command sets the burst start
address given by the column address to begin the burst write operation. The first
write data in burst can be input with this command with subsequent data on following
clocks.
RAS
CAS
WE
BA0, BA1
(Bank select)
A10
Add
Col.
Fig. 4 Column address and
write command
Read command
CLK
H
( CS , CAS = Low, RAS , WE = High)
CKE
CS
Read data is available after CAS latency requirements have been met.
This command sets the burst start address given by the column address.
RAS
CAS
WE
BA0, BA1
(Bank select)
A10
Add
Col.
Fig. 5 Column address and
read command
CLK
CBR (auto) refresh command
H
CKE
( CS , RAS , CAS = Low, WE , CKE = High)
CS
RAS
CAS
WE
This command is a request to begin the CBR refresh operation. The refresh
address is generated internally.
Before executing CBR refresh, all banks must be precharged.
After this cycle, all banks will be in the idle (precharged) state and ready for a
row activate command.
BA0, BA1
During tRC period (from refresh command to refresh or activate command), the
device cannot accept any other command.
(Bank select)
A10
Add
Fig. 6 Auto refresh command
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Self refresh entry command
CLK
CKE
( CS ,RAS , CAS , CKE = Low , WE = High)
CS
After the command execution, self refresh operation continues while CKE
remains low. When CKE goes to high, the device exits the self refresh mode.
During self refresh mode, refresh interval and refresh operation are performed
internally, so there is no need for external control.
RAS
CAS
Before executing self refresh, all banks must be precharged.
WE
BA0, BA1
(Bank select)
A10
Add
Fig. 7 Self refresh entry
command
Burst stop command
CLK
CKE
H
( CS , WE = Low, RAS , CAS = High)
CS
This command terminates the current burst operation.
Burst stop is valid at every burst length.
RAS
CAS
WE
BA0, BA1
(Bank select)
A10
Add
Fig. 8 Burst stop command
CLK
No operation
CKE
H
CS
RAS
CAS
WE
( CS = Low ,RAS , CAS , WE = High)
This command is not a execution command. No operations begin or terminate by
this command.
BA0, BA1
(Bank select)
A10
Add
Fig. 9 No operation
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BASIC FEATURE AND FUNCTION DESCRIPTIONS
1. CLOCK Suspend
1 ) C l o c k S u s p e n d e d D u r i n g W r i t e ( B L = 4 )
2 ) C l o c k S u s p e n d e d D u r i n g R e a d ( B L = 4 )
CLK
C M D
CK E
W R
R D
Mask ed by C K E
Inter nal
CLK
D3
D3
DQ ( C L 2 )
DQ ( C L 3 )
D2
D2
Q2
Q3
D0
D0
Q0
Q1
Q0
D1
D1
Q3
Q2
Q1
Not W r it ten
Suspended Dout
2. DQM Operation
2 ) R e a d M a s k ( B L = 4 )
1 ) W r i t e M a s k ( B L = 4 )
CLK
C M D
W R
R D
D Q M
DQ ( C L 2 )
DQ ( C L 3 )
M a s k e d b y D Q M
M a s k e d b y D Q M
H i - Z
D0
D1
Q3
Q0
D3
Q2
H i - Z
D3
D1
D0
Q1
Q3
Q2
DQ M t o D at a- i n M a sk = 0
DQ M to D at a- ou t Ma sk = 2
* N o t e 2
3 ) D Q M w i t h c l c o k s u s p e n d e d ( F u l l P a g e R e a d )
CLK
C M D
CK E
R D
Inter nal
CLK
D Q M
H i - Z
H i - Z
H i - Z
H i - Z
H i - Z
Q6
Q5
Q7
Q6
Q4
Q3
Q8
Q7
Q0
Q2
Q1
DQ ( C L 2 )
DQ ( C L 3 )
H i - Z
*Note : 1. CKE to CLK disable/enable = 1CLK.
2. DQM masks data out Hi-Z after 2CLKs which should masked by CKE ”L”.
3. DQM masks both data-in and data-out.
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3. CAS Interrupt (I)
* N o t e 1
1 ) R e a d i n t e r r u p t e d b y R e a d ( B L = 4 )
CL K
C M D
A D D
R D
B
R D
A
DQ ( C L 2 )
DQ ( C L 3 )
QB1 QB2 QB3
QB0 QB1 QB2
QB0
QA0
QA0
QB3
tC C D
* N o t e
2
2 ) W r i t e i n t e r r u p t e d b y W r i t e ( B L = 2 )
3 ) W r i t e i n t e r r u p t e d b y R e a d ( B L = 2 )
CLK
C M D
W R
R D
W R
W R
tC C D * N o t e
B
A
2
tC C D * N o t e
2
A D D
D Q
A
B
DQ ( C L 2 )
DQ ( C L 3 )
DB1
DA0 DB0
tC D L
DQ0
DA0
DA0
DQ1
DQ0
* N o t e
3
DQ1
tC D L
* N o t e
3
*Note : 1. By “interrupt” is meant to stop burst read/write by external before the end of burst.
By ” CAS interrupt ”, to stop burst read/write by CAS access ; read and write.
2. tCCD : CAS to CAS delay. (=1CLK)
3. tCDL : Last data in to new column address delay. (=1CLK)
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4. CAS Interrupt (II) : Read Interrupted by Write & DQM
( a) CL =2 , B L= 4
CLK
i ) C M D
R D
R D
R D
W R
D0
D Q M
D Q
D2
D1
D3
i i ) C M D
W R
D Q M
D Q
H i - Z
D2
D3
D2
D1
D0
D1
i i i ) C M D
W R
D Q M
D Q
H i - Z
D0
D3
D1
i v ) C M D
W R
R D
D Q M
D Q
H i - Z
D2
D3
Q0
D0
* N o t e 1
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(b) CL = 3 , B L= 4
CLK
R D
W R
D0
i ) C M D
D Q M
D Q
D2
D1
D3
W R
i i ) C M D
R D
D Q M
D Q
D2
D3
D0
D1
i i i ) C M D
W R
R D
D Q M
D Q
D2
D0
D1
D3
i v ) C M D
W R
R D
D Q M
D Q
H i - Z
D2
D3
D0
D1
v ) C M D
R D
W R
D Q M
D Q
H i - Z
Q0
D0
D1
D2
D3
* N o t e 1
*Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.
5. Write Interrupted by Precharge & DQM
1 ) N o r m a l W r i t e ( B L = 4 )
CLK
* N o t e 3
C M D
D Q M
D Q
W R
D0
PR E
* N o t e 2
D3
D1
D2
Ma s k e d b y D Q M
tRDL(min)
*Note : 1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
2. To inhibit invalid write, DQM should be issued.
3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt
but only another bank precharge of four banks operation.
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6. Precharge
2 ) N o r m a l R e a d ( B L = 4 )
1 ) N o r m a l W r i t e ( B L = 4 )
CLK
CLK
D Q
C M D
CL= 2
Q3
PR E
Q2
PR E
R D
W R
D0
1 * N o t e 2
DQ ( C L 2 )
D1
Q0
D2
D3
Q1
Q0
tR D L
C M D
PR E
CL= 3
Q2
* N o t e 1
2 * N o t e 2
DQ ( C L 3 )
Q3
Q1
.
7. Auto Precharge
1 ) N o r m a l W r i t e ( B L = 4 )
2 ) N o r m a l R e a d ( B L = 4 )
CLK
CLK
C M D
R D
C M D
D Q
W R
Q1
Q0
Q2
Q0
D0
Q3
Q2
D1
D2
D3
DQ ( C L 2 )
DQ ( C L 3 )
tR D L
Q1
Q3
* N o t e 3
Auto Pr ech ar ge st art s
* N o t e 3
Auto Pr ech arge st art s
*Note : 1. tRDL : Last data in to row precharge delay.
2. Number of valid output data after row precharge : 1,2 for CAS Latency = 2,3 respectively.
3. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
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8. Burst Stop & Interrupted by Precharge
1 ) W r i t e B u r s t S t o p ( B L = 8 )
1 ) W r i t e i n t e r r u p t e d b y p r e c h a r g e ( B L = 4 )
C L K
C L K
C M D
C M D
W R
P R E
W R
S T O P
t R D L
* N o t e 1
D Q M
D Q
D Q M
D Q
D 2
M a s k
D 3
D 0
D 0
D 1
D 4
D 5
D 1
D 2
* N o t e 2
t B D L
2 ) R e a d B u r s t S t o p ( B L = 4 )
2 ) R e a d i n t e r r u p t e d b y p r e c h a r g e ( B L = 4 )
C L K
C L K
* N o t e 3
C M D
C M D
S T O P
Q 0
R D
P R E
Q 0
R D
* N o t e 3
D Q ( C L 2 )
D Q ( C L 3 )
Q 1
Q 0
D Q ( C L 3 )
D Q ( C L 2 )
Q 1
Q 0
Q 1
Q 1
9. MRS
1 ) Mo d e R e g i s t e r S e t
CLK
* N o t e 4
C M D
A C T
PRE
M R S
tR P
2 C L K
*Note: 1. tRDL : 2 CLK; Last data in to Row Precharge.
2. tBDL : 1 CLK ; Last data in to burst stop delay.
3. Number of valid output data after burst stop : 1,2 for CAS latency = 2,3 respectiviely.
4. PRE : All banks precharge, if necessary.
MRS can be issued only at all banks precharge state.
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10. Clock Suspend Exit & Power Down Exit
1 ) C l o c k S u s p e n d ( = Ac t i v e P o w e r D o w n ) E x i t
2 ) P o w e r D o w n ( = P r e c h a r g e P o w e r D o w n )
CLK
CK E
CLK
CK E
tS S
tS S
Inter nal
Internal
CLK
* N o t e 1
* N o t e 2
CLK
C M D
R D
C M D
A C T
NO P
11. Auto Refresh & Self Refresh
* N o t e 3
1 ) A u t o R e f r e s h
&
S e l f R e f r e s h
C L K
* N o t e 4
* N o t e 5
C M D
C M D
P R E
A R
C K E
t R P
t R C
* N o t e 8
2 ) S e l f R e f r e s h
C L K
* N o t e 4
C M D
P R E
S R
C M D
C K E
t R P
t R C
*Note : 1. Active power down : one or more banks active state.
2. Precharge power down : all banks precharge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM.
No precharge commands are required after auto refresh command.
During tRC from auto refresh command, any other command can not be accepted.
4. Before executing auto/self refresh command, all banks must be idle state.
5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh entry, refresh interval and refresh operation are performed internally.
After self refresh entry, self refresh mode is kept while CKE is low.
During self refresh entry, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state.
For the time interval of tRC from self refresh exit command, any other command can not be accepted.
4K cycles of burst auto refresh is required immediately before self refresh entry and immediately after self refresh exit.
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12. About Burst Type Control
At MRS A3 = “0”. See the BURST SEQUENCE TABLE. (BL = 4,8)
BL = 1, 2, 4, 8 and full page.
Sequential Counting
Basic
MODE
At MRS A3 = “1”. See the BURST SEQUENCE TABLE. (BL = 4,8)
BL = 4, 8 At BL =1, 2 interleave Counting = Sequential Counting
Interleave Counting
Every cycle Read/Write Command with random column address can realize Random
Column Access.
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
Random Random Column Access
MODE tCCD = 1 CLK
13. About Burst Length Control
At MRS A210 = “000”
At auto precharge . tRAS should not be violated.
1
At MRS A210 = “001”
At auto precharge . tRAS should not be violated.
2
Basic
MODE
4
At MRS A210 = “010”
At MRS A210 = “011”
8
At MRS A210 = “111”
At the end of the burst length , burst is warp-around.
Full Page
tBDL = 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
Using burst stop command, any burst length control is possible.
Random
MODE
Burst Stop
Before the end of burst. Row precharge command of the same bank stops read /write burst
with auto precharge.
tRDL = 1 with DQM , Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
RAS Interrupt
(Interrupted by
Precharge)
During read/write burst with auto precharge, RAS interrupt can not be issued.
Interrupt
MODE
Before the end of burst, new read/write stops read/write burst and starts new read/write
burst.
CAS Interrupt
During read/write burst with auto precharge, CAS interrupt can not be issued.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4 24/46
ESMT
M12S128324A
FUNCTION TURTH TABLE (TABLE 1)
Current
State
CS RAS CAS WE
BA
ADDR
ACTION
Note
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
X
H
H
H
L
L
L
L
X
H
H
H
H
L
X
H
H
L
H
H
L
X
H
L
X
H
L
H
L
X
H
L
H
L
H
L
X
X
H
L
H
L
H
L
X
X
H
L
H
L
H
L
X
X
H
L
X
X
X
X
H
L
X
X
X
BA
BA
BA
X
X
X
X
NOP
NOP
ILLEGAL
2
2
IDLE
CA, A10/AP ILLEGAL
RA
A10/AP
Row (&Bank) Active ; Latch RA
NOP
Auto Refresh or Self Refresh
Mode Register Access
NOP
NOP
ILLEGAL
4
5
5
X
L
OP code
X
OP code
X
H
H
L
X
X
X
X
X
2
2
Row
Active
BA
BA
BA
BA
X
X
X
X
BA
BA
BA
BA
X
X
X
X
BA
BA
BA
BA
X
X
X
X
BA
BA
X
X
X
CA, A10/AP Begin Read ; latch CA ; determine AP
CA, A10/AP Begin Write ; latch CA ; determine AP
RA
A10/AP
L
H
H
L
X
H
H
L
ILLEGAL
Precharge
ILLEGAL
L
L
X
X
X
X
X
H
H
H
H
L
NOP (Continue Burst to End Æ Row Active)
NOP (Continue Burst to End Æ Row Active)
Term burst Æ Row active
Read
Write
CA, A10/AP Term burst, New Read, Determine AP
CA, A10/AP Term burst, New Write, Determine AP
RA
A10/AP
L
3
2
H
H
L
X
H
H
L
ILLEGAL
L
L
Term burst, Precharge timing for Reads
ILLEGAL
NOP (Continue Burst to End Æ Row Active)
NOP (Continue Burst to End Æ Row Active)
Term burst Æ Row active
X
X
X
X
X
H
H
H
H
L
CA, A10/AP Term burst, New Read, Determine AP
CA, A10/AP Term burst, New Write, Determine AP
RA
A10/AP
3
3
2
3
L
H
H
L
X
H
H
L
H
L
X
H
H
L
ILLEGAL
L
L
Term burst, Precharge timing for Writes
ILLEGAL
NOP (Continue Burst to End Æ Precharge)
NOP (Continue Burst to End Æ Precharge)
ILLEGAL
X
X
X
X
X
H
H
H
L
Read with
Auto
Precharge
CA, A10/AP ILLEGAL
RA, RA10
ILLEGAL
ILLEGAL
2
2
L
X
X
X
X
X
H
H
H
L
NOP (Continue Burst to End Æ Precharge)
NOP (Continue Burst to End Æ Precharge)
ILLEGAL
Write with
Auto
Precharge
X
X
X
X
BA
BA
X
CA, A10/AP ILLEGAL
RA, RA10
X
H
L
ILLEGAL
ILLEGAL
L
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4
25/46
ESMT
M12S128324A
Current
State
CS RAS CAS WE
BA
ADDR
ACTION
Note
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
X
H
H
H
L
X
H
H
L
H
H
L
X
H
H
L
H
H
L
X
H
L
H
L
X
H
H
L
X
H
L
X
H
L
X
X
H
L
X
H
L
X
X
X
X
X
X
X
H
L
X
X
X
BA
BA
BA
X
X
X
X
BA
BA
BA
X
X
X
X
X
X
X
X
X
X
CA
RA
A10/AP
NOP Æ Idle after tRP
NOP Æ Idle after tRP
ILLEGAL
ILLEGAL
ILLEGAL
NOP Æ Idle after tRDL
ILLEGAL
NOP Æ Row Active after tRCD
NOP Æ Row Active after tRCD
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP Æ Idle after tRC
NOP Æ Idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
Precharging
2
2
2
4
L
L
X
X
X
X
X
H
H
H
L
L
L
X
H
H
L
Row
Activating
2
2
2
2
CA
RA
A10/AP
X
X
X
X
X
X
X
X
X
X
X
Refreshing
L
X
H
H
H
L
NOP Æ Idle after 2clocks
NOP Æ Idle after 2clocks
ILLEGAL
ILLEGAL
ILLEGAL
Mode
Register
Accessing
X
X
X
X
X
X
X
Abbreviations :
RA = Row Address
NOP = No Operation Command
BA = Bank Address
CA = Column Address
AP = Auto Precharge
*Note : 1. All entries assume the CKE was active (High) during the precharge clock and the current clock cycle.
2. Illegal to bank in specified state ; Function may be legal in the bank indicated by BA, depending on the state of the
bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharge or in idle state. May precharge bank indicated by BA (and A10/AP).
5. Illegal if any bank is not idle.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4 26/46
ESMT
M12S128324A
FUNCTION TRUTH TABLE (TABLE2)
Current
State
CKE
CKE
n
CS RAS CAS WE
ADDR
ACTION
Note
( n-1 )
H
L
L
L
L
L
L
H
L
X
H
H
H
H
H
L
X
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
X
H
L
L
L
X
X
H
H
H
L
X
X
X
H
H
H
L
X
X
X
H
H
H
L
X
X
H
H
L
X
X
X
X
H
H
L
X
X
X
X
H
H
L
X
X
H
L
X
X
X
X
X
H
L
X
X
X
X
X
H
L
X
H
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID
Exit Self Refresh Æ Idle after tRC (ABI)
Exit Self Refresh Æ Idle after tRC (ABI)
ILLEGAL
6
6
Self
Refresh
ILLEGAL
ILLEGAL
L
X
X
H
L
L
L
NOP (Maintain Self Refresh)
INVALID
Exit Self Refresh Æ ABI
Exit Self Refresh Æ ABI
ILLEGAL
All
Banks
Precharge
Power
7
7
L
L
L
L
ILLEGAL
ILLEGAL
Down
L
L
X
X
H
L
L
L
L
L
L
NOP (Maintain Low Power Mode)
Refer to Table1
H
H
H
H
H
H
H
H
L
Enter Power Down
Enter Power Down
ILLEGAL
8
8
X
X
X
RA
All
Banks
Idle
ILLEGAL
H
L
L
Row (& Bank) Active
Enter Self Refresh
Mode Register Access
NOP
Refer to Operations in Table 1
Begin Clock Suspend next cycle
Exit Clock Suspend next cycle
Maintain Clock Suspend
L
L
X
8
OP Code
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Any State
other than
Listed
H
H
L
H
L
H
L
9
9
above
L
Abbreviations : ABI = All Banks Idle, RA = Row Address
*Note : 6.CKE low to high transition is asynchronous.
7.CKE low to high transition is asynchronous if restart internal clock.
A minimum setup time 1CLK + tSS must be satisfy before any command other than exit.
8.Power down and self refresh can be entered only from the all banks idle state.
9.Must be a legal command.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4 27/46
ESMT
M12S128324A
Single Bit Read-Write-Read Cycle(Same Page) @ CAS Latency = 3,Burst Length = 1
tC H
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
C K E
tC L
tC C
H I G H
tR A S
tR C
tS H
* N o t e 1
C S
tR C D
tR P
tS S
tS H
tS S
R A S
C A S
tC C D
tS H
tS S
tS H
A D D R
R b
C c
R a
C a
C b
tS S
* N o t e 2 , 3
* N o t e 4
* N o t e 2 , 3
* N o t e 2
* N o t e 2
* N o t e 2 , 3
B S
BS
BS
BS
BS
BA0, BA1
A10/AP
D Q
BS
* N o t e 3
* N o t e 3
* N o t e 4
* N o t e 3
R b
R a
tS H
tS A C
Qc
Qa
D b
tS L Z
tS S
tO H
tS H
W E
tS S
tS S
tS H
D Q M
Ro w A c t i ve
Rea d
Read
Row A c t i ve
W r i t e
Precha rge
: D o n ' t C a r e
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4 28/46
ESMT
M12S128324A
Note : 1. All input expect CKE & DQM can be don’t care when CS is high at the CLK high going edge.
2. Bank active @ read/write are controlled by BA0~BA1.
BA1
BA0
Active & Read/Write
Bank A
0
0
1
1
0
1
0
1
Bank B
Bank C
Bank D
3. Enable and disable auto precharge function are controlled by A10/AP in read/write command
A10/AP
BA1
0
BA0
0
Operating
Disable auto precharge, leave A bank active at end of burst.
Disable auto precharge, leave B bank active at end of burst.
Disable auto precharge, leave C bank active at end of burst.
Disable auto precharge, leave D bank active at end of burst.
Enable auto precharge , precharge bank A at end of burst.
Enable auto precharge , precharge bank B at end of burst.
Enable auto precharge , precharge bank C at end of burst.
Enable auto precharge , precharge bank D at end of burst.
0
1
0
1
0
1
1
0
0
0
1
1
1
0
1
1
4. A10/AP and BA0~BA1 control bank precharge when precharge is asserted.
A10/AP
BA1
0
BA0
0
Precharge
Bank A
0
0
0
0
1
0
1
Bank B
1
0
Bank C
1
1
Bank D
X
X
All Banks
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4 29/46
ESMT
M12S128324A
Power Up Sequence
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
C K E
H i g h l e v e l i s n e c e s s a r y
C S
t R C
t R C
t R P
R A S
C A S
A D D R
K e y
R A a
B A 1
B A 0
R A a
A10/AP
H i g h - Z
D Q
W E
D Q M
H i g h l e v e l i s n e c e s s a r y
M o d e R e g i s t e r S e t
A u t o R e f r e s h
A u t o R e f r e s h
P r e c h a r g e
( A l l B a n k s )
R o w A c t i v e
( A - B a n k )
:
D o n ' t c a r e
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4 30/46
ESMT
M12S128324A
Read & Write Cycle at Same Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
HIGH
CKE
CS
*Note1
tRC
tRCD
RAS
*Note2
CAS
ADDR
Rb
Cb
Ra
Ca
BA1
BA0
Rb
`
A10/AP
CL=2
Ra
tOH
Qa2
Qa3
Db2
Qa0
Db1
Db3
Qa1
Db0
Db0
tSAC
tSHZ
*Note3
tSHZ
tRDL
tRDL
DQ
tOH
CL=3
Qa1
Qa2
Db1
Qa0
Qa3
Db2
Db3
tSAC
*Note3
WE
DQM
Precharge
(A-Bank)
Row Active
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Read
Write
(A-Bank)
(A-Bank)
: Don't care
*Note :
1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row
precharge. Last valid output will be Hi-Z (tSHZ) after the clock.
3. Output will be Hi-Z after the end of burst. (1,2,4,8 & Full page bit burst)
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4 31/46
ESMT
M12S128324A
Page Read & Write Cycle at Same Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
H I G H
C K E
C S
tR C D
R A S
* N o t e 2
C A S
A D D R
R a
C a
C d
C b
C c
BA1
BA0
A10 /AP
R a
tR D L
Qa0
Qa1 Qb0
Dd0 Dd1
Qb2
Qb1
Dc 1
Qb1
CL = 2
Dc 0
Dc 0
D Q
CL = 3
Dc 1
Qa1
Qa0
Qb0
Dd0
Dd1
tC D L
W E
* N o t e 1
* N o t e 3
D Q M
Read
( A - Bank )
Read
( A - Bank )
Write
( A - Bank )
Write
( A - Bank )
Row Active
( A - Bank )
Prechar ge
(A - B an k )
: D o n ' t C a r e
Note : 1. To Write data before burst read ends. DQM should be asserted three cycle prior to write command to avoid bus
contention.
2. Row precharge will interrupt writing. Last data input , tRDL before row precharge , will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input
data after Row precharge cycle will be masked internally.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4 32/46
ESMT
M12S128324A
Page Read Cycle at Different Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
C K E
H I G H
* N o t e 1
C S
R A S
* N o t e 2
C A S
A D D R
BA1
R A a
R C c
R B b C A a
C B b
R D d C C c
C D d
BA0
A10/AP
CL= 2
R A a
R B b
R C c
R D d
QAa0
QDd0
QCc2
QCc1
QAa1
QAa0
QDd2
QDd1
QAa2
QBb1 QBb2
QBb0
QCc0
QBb2
D Q
CL= 3
QBb1
QDd1
QDd2
QAa1 QAa2 QBb0
QCc2 QDd0
QCc0 QCc1
W E
D Q M
P r e c h a r g e
( D - B a n k )
R e a d
( B - B a n k )
R e a d
( A - B a n k )
R e a d
( C - B a n k )
R e a d
( D - B a n k )
R o w A c t i v e
( A - B a n k )
R o w A c t i v e
( D - B a n k )
P r e c h a r g e
( C - B a n k )
R o w A c t i v e
( B - B a n k )
R o w A c t i v e
( C - B a n k )
P r e c h a r g e
( A - B a n k )
P r e c h a r g e
( B - B a n k )
: D o n ' t C a r e
Note: 1. CS can be don’t cared when RAS , CAS and WE are high at the clock high going edge.
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4 33/46
ESMT
M12S128324A
Page Write Cycle at Different Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
C K E
H I G H
C S
R A S
* N o t e 2
C A S
A D D R
R C c
CA a
R D d C C c
C D d
RA a
RB b
CB b
B A 1
B A 0
RB b
RA a
R D d
R C c
A10/AP
D Q
DBb3
D C c 0
DAa2
DAa0 DAa1
DBb2
CD d2
DAa3 DBb0 DBb1
tC D L
D C c 1 DD d0 DD d1
tR D L
W E
* N o t e 1
D Q M
W r i t e
( D - B a n k )
R o w A c t i v e
( D - B a n k )
W r i t e
( A - B a n k )
W r i t e
( B - B a n k )
R o w A c t i v e
( A - Bank )
P r e c h a r g e
( A l l B a n k s )
R o w A c t i v e
( B - B a n k )
W r i t e
( C - B a n k )
R o w A c t i v e
( C - B a n k )
:
D o n ' t c a r e
*Note : 1. To interrupt burst write by Row precharge , DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge , both the write and the precharge banks must be the same.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4 34/46
ESMT
M12S128324A
Read & Write Cycle at Different Bank @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
18
15
16
17
19
C L O C K
C K E
H I G H
C S
R A S
C A S
A D D R
RA a
C B c
C D b R B c
CA a
R D b
BA1
BA0
A10/AP
CL = 2
R A c
RA a
RB b
QAa1
QAa0
* N o t e 2
* N o t e 1
tC D L
DD d3
tR C D
DD b0
DD b2
QBc0
QBc2
QBc1
QAa3
Ddb1
QAa0
QAa2
D Q
CL = 3
QBc0 QBc1
QAa1 QAa2
QAa3
DD d3
DD b0 Ddb1 DD b2
W E
D Q M
Read
( B - Ban k )
W r i t e
( D - B an k )
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(D-Bank)
Row Active
(B-Bank)
: D o n ' t C a r e
*Note : 1. tCDL should be met to complete write.
2. tRCD should be met.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4 35/46
ESMT
M12S128324A
Read & Write cycle with Auto Precharge @ Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
C K E
H I G H
C S
R A S
C A S
A D D R
R b
C a
C b
R a
BA0
BA1
R a
R b
A10/AP
QAa2
CL = 2
D Q
QAa0 QAa1
QAa3
QAa2
DD d3
DD d3
DD b0 Ddb1
DD b2
DD b2
CL = 3
QAa0 QAa1
DD b0
QAa3
Ddb1
W E
D Q M
W r i t e wi t h
Auto Pr echar ge
( D- B an k )
Auto Pr echar ge
Star t Poin t
(D - Ban k )
Read with
Auto Precharge
( A - Bank )
Auto Pr echar ge
Star t Poin t
Row Active
( A - Bank )
Row Active
( D - Bank )
: D o n ' t C a r e
*Note : 1. tCDL should be controlled to meet minimum tRAS before internal precharge start.
(In the case of Burst Length = 1 & 2)
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4 36/46
ESMT
M12S128324A
Clock Suspension & DQM Operation Cycle @ CAS Letency = 2 , Burst Length = 4
16
17
18
0
1
2
5
9
10
11
12
13
14
15
19
3
4
6
7
8
C L O C K
C K E
C S
R A S
C A S
A D D R
R a
C a
C c
C b
BA1
BA0
R a
A10 /AP
* N o t e 2
tR C D
D Q
Qb0 Qb1
tS H Z
Qa0
Qa1
Qa3
tS H Z
Dc 2
Qa2
Dc 0
W E
* N o t e 1
D Q M
W r i t e
D Q M
Cl oc k
Su pen sion
Read
W r i t e
D Q M
Ro w A c t i ve
Read
Rea d D Q M
W r i t e
Cl oc k
Suspension
:D on ' t C ar e
*Note : 1. DQM is needed to prevent bus contention.
2. tRCD should be met.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4 37/46
ESMT
M12S128324A
Read interrupted by Precharge Command & Read Burst Stop Cycle @ Burst Length = Full page
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
H I G H
C K E
C S
R A S
C A S
A D D R
CA a
CA b
RA a
BA1
BA0
* N o t e 1
* N o t e 1
A10/AP
CL= 2
RA a
* N o t e 2
1
1
QAb3 QAb4
QAb1 QAb2
QAb5
QAa0
QAa2 QAa3 QAa4
QAb0
QAa1
QAa0
D Q
2
2
CL= 3
QAa2 QAa3 QAa4
QAa1
QAb0
QAb3 QAb4
QAb5
QAb1 QAb2
W E
D Q M
Read
(A - Ban k )
Burst Stop
Read
(A - Ban k )
Precharge
( A- B an k )
Row A c t i ve
( A- B an k )
:D on ' t C ar e
*Note : 1. About the valid DQs after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the lable 1,2 on them.
But at burst write, Burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of “Full page write burst stop cycles”.
2. Burst stop is valid at every burst length.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4 38/46
ESMT
M12S128324A
Write interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length = Full page
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
C K E
H I G H
C S
R A S
C A S
A D D R
CA b
CA a
RA a
BA1
BA0
RA a
A10/AP
tR D L
* N o t e 1
tB D L
DAa4
DAa2 DAa3
DAa0
DAa1
DAb3 DAb4 DAb5
DAb0 DAb1 DAb2
D Q
W E
D Q M
W ri t e
(A - Ban k )
Burst Stop
W r i t e
( A - Ban k )
Row A c t i ve
( A- B an k )
Precharge
( A- B an k )
:D on' t C ar e
*Note : 1. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by
AC parameter of tRDL.
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input
data after Row precharge cycle will be masked internally.
2. Burst stop is valid at every burst length.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4 39/46
ESMT
M12S128324A
Active/Precharge Power Down Mode @ CAS Latency = 2, Burst Length = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
* N o t e 2
tS S
tS S
tS S
* N o t e 1
C K E
* N o t e 3
C S
R A S
C A S
A D D R
R a
C a
B A 1
B A 0
A10/AP
R a
tS H Z
D Q
Qa1 Qa2
Qa0
W E
D Q M
Read
P r e c h a r g e
Pr ech ar ge
Row A c t i ve
Pow er - D ow n
E ntr y
Pr ech arge
Pow er - D ow n
Exi t
A c t i v e
P o w e r - d o w n
E x i t
A ct ive
Pow er - dow n
E ntr y
:
D o n ' t c a r e
*Note: 1. All banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least 1CLK + tSS prior to Row active command.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4 40/46
ESMT
M12S128324A
Self Refresh Entry & Exit Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1 9
C L O C K
C K E
* N o t e 4
* N o t e 2
t R C m i n
* N o t e 1
* N o t e 6
* N o t e 3
tS S
* N o t e 5
C S
R A S
* N o t e 7
C A S
A D D R
B A 0 , B A 1
A10/AP
D Q
H i - Z
H i - Z
W E
D Q M
S e l f R e f r e s h E xi t
S e l f R e f r e s h E n t r y
A u t o R e f r e s h
:
D o n ' t c a r e
*Note : TO ENTER SELF REFRESH MODE
1. CS , RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays “Low”.
cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum tRC is required after CKE going high to complete self refresh exit.
7. 4K cycles of burst auto refresh is required immediately before self refresh entry and immediately after self refresh exit.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4 41/46
ESMT
M12S128324A
Mode Register Set Cycle
Auto Refresh Cycle
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
8
9
10
C L O C K
C K E
H I G H
H I G H
C S
* N o t e 2
tR C
R A S
* N o t e 1
* N o t e 3
C A S
A D D R
R a
Key
H I - Z
H I - Z
D Q
W E
D Q M
New
Com man d
M R S
New C om m an d
:D on' t C ar e
Auto Ref res h
All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
*Note : 1. CS , RAS , CAS , & WE activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4 42/46
ESMT
M12S128324A
PACKING
86 - LEAD
DIMENSIONS
TSOP(II)
DRAM(400mil)
Symbol
Dimension in mm
Dimension in inch
Min
Norm
Max
1.20
0.15
1.05
0.27
0.23
0.21
0.16
Min
Norm
Max
A
A1
A2
b
0.047
0.006
0.011
0.018
0.009
0.008
0.006
0.05
0.95
0.17
0.17
0.12
0.10
0.10
1.00
0.002
0.037
0.007
0.007
0.005
0.004
0.004
0.039
b1
c
0.20
0.008
c1
D
0.127
0.005
22.22 BSC
0.61 REF
11.76 BSC
10.16 BSC
0.50
0.875 BSC
0.024 REF
0.463 BSC
0.400 BSC
0.020
ZD
E
E1
L
0.40
0.60
0.016
0.024
L1
e
0.80 REF
0.50 BSC
0.031 REF
0.020 BSC
R1
R2
θ
0.12
0.12
0°
0.005
0.005
0°
0.25
0.010
8°
8°
0°
0°
θ 1
θ 2
θ 3
10°
10°
15°
15°
20°
20°
10°
10°
15°
15°
20°
20°
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4 43/46
ESMT
M12S128324A
PACKING
DIMENSIONS
90-BALL
SDRAM ( 8x13 mm )
Symbol
Dimension in mm
Dimension in inch
Min
Norm
Max
Min
Norm
Max
0.055
A
A1
A2
øb
D
1.40
0.40
0.94
0.50
8.10
13.10
0.30
0.84
0.40
7.90
12.90
0.012
0.033
0.016
0.311
0.508
0.016
0.037
0.020
0.319
0.516
0.89
0.035
8.00
13.00
6.40
11.20
0.80
0.315
0.512
0.252
0.441
0.031
E
D1
E1
e
Controlling dimension : Millimeter.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4
44/46
ESMT
M12S128324A
Revision History
Revision
Date
Description
1.0
2008.07.07
Original
1. Modify ICC3N
1.1
2008.07.16
2. Modify the figure of DC output load circuit
Modify ICC4 and ICC5
1.2
1.3
2008.07.16
2008.08.07
Modify ICC4 and ICC5 for -7
1. Modify the description about self refresh operation
2. Correct type error
1.4
2009.03.27
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4 45/46
ESMT
M12S128324A
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or by any
means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at the time of
publication. ESMT assumes no responsibility for any error in this document, and
reserves the right to change the products or specification in this document without
notice.
The information contained herein is presented only as a guide or examples for the
application of our products. No responsibility is assumed by ESMT for any
infringement of patents, copyrights, or other intellectual property rights of third
parties which may result from its use. No license, either express , implied or
otherwise, is granted under any patents, copyrights or other intellectual property
rights of ESMT or others.
Any semiconductor devices may have inherently a certain rate of failure. To minimize
risks associated with customer's application, adequate design and operating
safeguards against injury, damage, or loss from such failure, should be provided by
the customer when making application designs.
ESMT's products are not authorized for use in critical applications such as, but not
limited to, life support devices or system, where failure or abnormal operation may
directly affect human lives or cause physical injury or property damage. If products
described here are to be used for such kinds of application, purchaser must do its
own quality assurance testing appropriate to such applications.
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.4 46/46
相关型号：
M12S16161A-5TG2Q
Synchronous DRAM, 1MX16, 4.5ns, CMOS, PDSO50, 0.400 X 0.825 INCH, 0.80 MM PITCH, LEAD FREE, TSOP2-50
ESMT
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