M12S16161A-10TG [ESMT]
512K x 16Bit x 2Banks Synchronous DRAM; 512K X 16位X 2Banks同步DRAM
| 型号： | M12S16161A-10TG |
| 厂家： | 
ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. |
| 描述： | 512K x 16Bit x 2Banks Synchronous DRAM |
| 文件： | 总28页 (文件大小：866K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESMT
M12S16161A
SDRAM
512K x 16Bit x 2Banks
Synchronous DRAM
FEATURES
GENERAL DESCRIPTION
The M12S16161A is 16,777,216 bits synchronous high
data rate Dynamic RAM organized as 2 x 524,288 words by
16 bits, fabricated with high performance CMOS technology.
Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
ꢀ
ꢀ
ꢀ
ꢀ
2.5V power supply
LVCMOS compatible with multiplexed address
Dual banks operation
MRS cycle with address key programs
-
-
-
CAS Latency (1, 2 & 3 )
Burst Length (1, 2, 4, 8 & full page)
Burst Type (Sequential & Interleave)
ꢀ
ꢀ
EMRS cycle with address key programs.
All inputs are sampled at the positive going edge of the
system clock
ꢀ
ꢀ
Burst Read Single-bit Write operation
Special Function Support.
ORDERING INFORMATION
-
-
-
PASR (Partial Array Self Refresh )
TCSR (Temperature compensated Self Refresh)
DS (Driver Strength)
MAX
Part NO.
Interface Package Comments
Freq.
Non-Pb-free
Non-Pb-free
Pb-free
Pb-free
M12S16161A-10T
M12S16161A-15T
100MHz
66MHz
ꢀ
ꢀ
ꢀ
DQM for masking
50
Auto & self refresh
LVCMOS
TSOP(II)
M12S16161A-10TG 100MHz
32ms refresh period (2K cycle)
M12S16161A-15TG
66MHz
PIN CONFIGURATION (TOP VIEW)
VDD
1
2
3
4
5
6
7
8
VSS
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
DQ0
DQ1
VSSQ
DQ2
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
LDQM
WE
CAS
RAS
CS
BA
A10/AP
A0
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
N.C/RFU
UDQM
CLK
CKE
N.C
A9
A8
A7
A6
A5
A4
VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
A1
A2
A3
VDD
50PIN TSOP(II)
(400mil x 825mil)
(0.8 mm PIN PITCH)
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2005
Revision : 1.0 1/28
ESMT
FUNCTIONAL BLOCK DIAGRAM
M12S16161A
LWE
Bank Select
Data Input Register
LDQM
512K x 16
512K x 16
DQi
CLK
ADD
Column Decoder
Latency & Burst Length
LCKE
Programming Register
LWCBR
LRAS LCBR
LWE
LDQM
LCAS
Timing Register
CKE
CLK
L(U)DQM
RAS
CAS
WE
CS
PIN FUNCTION DESCRIPTION
Pin
Name
System Clock
Input Function
CLK
CS
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM.
Chip Select
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
CKE
Clock Enable
A0 ~ A10/AP
BA
Address
Bank Select Address
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Row Address Strobe
Column Address Strobe
Write Enable
RAS
CAS
Latches column addresses on the positive going edge of the CLK with
CAS low.
Enables column access.
Enables write operation and row precharge.
WE
Latches data in starting from CAS , WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
L(U)DQM
Data Input / Output Mask
Blocks data input when L(U)DQM active.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2005
Revision : 1.0
2/28
ESMT
M12S16161A
DQ0 ~ 15
VDD/VSS
Data Input / Output
Data inputs/outputs are multiplexed on the same pins.
Power Supply/Ground
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved
noise immunity.
VDDQ/VSSQ Data Output Power/Ground
No Connection/
N.C/RFU
This pin is recommended to be left No Connection on the device.
Reserved for Future Use
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to VSS
Voltage on VDD supply relative to VSS
Storage temperature
Symbol
VIN,VOUT
VDD,VDDQ
TSTG
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ + 150
0.7
Unit
V
V
°C
Power dissipation
PD
W
Short circuit current
IOS
50
MA
Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
°C
°C
)
Recommended operating conditions (Voltage referenced to VSS = 0V, TA= 0
~ 70
Parameter
Symbol
VDD
Min
2.3
2.3
Typ
2.5
2.5
-
-
0
-
-
-
-
Max
2.7
2.7
2.7
Unit
V
V
V
V
V
V
V
uA
uA
Note
Supply voltage
VDDQ
1.65
1
1
2
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Output leakage current
VIH
VIL
VOH
VOL
IIL
0.8 x VDDQ
-0.3
VDDQ – 0.2
-
VDDQ+0.3
0.3
-
0.2
10
10
IOH =-0.1mA
IOL = 0.1mA
-10
-10
3
4
IOL
Note : 1. ESMT can support VDDQ 2.5V (in general case) and 1.8V (in specific case) for VDD 2.5V products. Please contact
to sales. Dept. when condisering the use fo VDDQ 1.8V (min 1.65V).
2.VIH (max) = 4.6V AC for pulse width ≤ 3ns acceptable.
3.VIL (min) = -1.0V AC for pulse width ≤ 3ns acceptable.
4.Any input 0V ≤ VIN ≤ VDDQ, all other pins are not under test = 0V.
5.Dout is disabled, 0V ≤ VOUT ≤ VDDQ.
°C
CAPACITANCE (VDD = 2.5V, TA = 25 , f = 1MHz)
Pin
Symbol
CCLK
Min
-
Max
4.0
Unit
pF
CLOCK
RAS , CAS , WE , CS , CKE, LDQM,
UDQM
CIN
-
4.0
pF
ADDRESS
DQ0 ~DQ15
CADD
COUT
-
-
4.0
6.0
pF
pF
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2005
Revision : 1.0 3/28
ESMT
M12S16161A
DC CHARACTERISTICS
°C
°C
)
(Recommended operating condition unless otherwise noted, TA = 0
~ 70
CAS
Latency
Version
Parameter
Symbol
Test Condition
Unit Note
-10
-15
Burst Length = 1
tRC ≥ tRC (min), tCC ≥ tCC (min), IOL= 0mA
Operating Current
(One Bank Active)
ICC1
35
25
mA
1
Precharge Standby
Current in power-down
mode
ICC2P
-
CKE ≤ VIL(max), tCC =15ns
mA
mA
ICC2PS
CKE ≤ VIL(max), CLK ≤ VIL(max), tCC = ∞
0.2
CKE ≥ VIH(min), CS ≥ VIH(min), tCC =15ns
Input signals are changed one time during 30ns
-
mA
ICC2N
Precharge Standby
Current in non
power-down mode
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
-
mA
mA
ICC2NS
ICC3P
Input signals are stable
-
-
CKE ≤ VIL(max), tCC =15ns
Active Standby Current
in power-down mode
ICC3PS
CKE ≤ VIL(max), CLK ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC=15ns
15
-
mA
ICC3N
Active Standby Current
in non power-down
mode
Input signals are changed one time during 30ns
CKE ≥ VIH (min), CLK ≤ VIL(max), tCC= ∞
mA
mA
ICC3NS
(One Bank Active)
Input signals are stable
IOL= 0Ma, Page Burst
1
2
Operating Current
(Burst Mode)
Refresh Current
35
35
25
25
ICC4
ICC5
All Band Activated, tCCD = tCCD (min)
tRC ≥ tRC(min)
TCSR range
2 Banks
mA
°C
45
100
95
70
120
110
100
90
ICC6
CKE ≤ 0.2V
uA
uA
1 Bank
Self Refresh Current
1/2 Bank
90
1/4 Bank
85
Deep Power Down
Current
ICC7
CKE ≤ 0.2V
10
Note: 1.Measured with outputs open. Addresses are changed only one time during tCC(min).
2.Refresh period is 32ms. Addresses are changed only one time during tCC(min).
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2005
Revision : 1.0 4/28
ESMT
M12S16161A
AC OPERATING TEST CONDITIONS (VDD=2.5V ± 0.2V,TA= 0°C ~ 70°C )
Parameter
Value
Unit
V
Input levels (Vih/Vil)
0.9 x VDDQ / 0.2
0.5 x VDDQ
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
V
tr / tf = 1 / 1
0.5 x VDDQ
See Fig.2
ns
V
VDDQ
500
Vtt =0.5x VDDQ
50
Output
VOH(DC) = VDDQ-0.2V, IOH = -0.1mA
VOL(DC) = 0.2V, IOL = 0.1mA
Output
Z0=50
500
20 pF
30 pF
(Fig.2) AC Output Load Circuit
(Fig.1) DC Output Load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
-15
Parameter
Symbol
Unit
Note
-10
Row active to row active delay
tRRD(min)
tRCD(min)
20
30
30
ns
ns
1
1
30
RAS to CAS delay
Row precharge time
tRP(min)
tRAS(min)
20
50
30
ns
ns
1
1
60
Row active time
tRAS(max)
100
90
1
us
Row cycle time
tRC(min)
70
ns
1
2
2
2
3
Last data in to new col. Address delay
Last data in to row precharge
Last data in to burst stop
tCDL(min)
CLK
CLK
CLK
CLK
tRDL(min)
2
tBDL(min)
1
Col. Address to col. Address delay
tCCD(min)
1
CAS latency=3
CAS latency=2
CAS latency=1
2
Number of valid output data
ea
4
1
0
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2.
Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2005
Revision : 1.0 5/28
ESMT
M12S16161A
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
-10
Max
-15
Parameter
Symbol
Unit Note
Min
10
15
-
Min
15
15
-
Max
CAS Latency =3
tCC
ns
ns
1
1
CLK cycle time
1000
1000
CAS Latency =2
CAS Latency =3
CAS Latency =2
9
12
12
12
CLK to valid
output delay
tSAC
-
-
Output data hold time
CLK high pulse width
CLK low pulse width
Input setup time
tOH
tCH
tCL
ns
ns
ns
ns
ns
ns
2
3
3
3
3
2
2.5
3
2.5
3
3
3
tSS
tSH
tSLZ
3
4
Input hold time
1
2
CLK to output in Low-Z
1
-
1
-
7
8
-
9
9
CAS Latency =3
CLK to output in
Hi-Z
tSHZ
-
-
-
-
ns
CAS Latency =2
CAS Latency =1
24
*All AC parameters are measured from half to half.
Note: 1.Parameters depend on programmed CAS latency.
2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.
3.Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the
parameter.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2005
Revision : 1.0 6/28
ESMT
Mode Register
M12S16161A
BA A10
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address bus
x
x
1
0
0
LTMODE
WT
BL
Burst Read and Single Write (for Write
Through Cache)
0
0
0
0
0
LTMODE
WT
BL
Mode Register Set
x =Don’t care
A2-A0
000
001
010
011
WT=0
WT=1
1
1
2
2
4
4
8
R
R
R
R
Burst length
8
100
101
110
R
R
R
111
Full page
0
1
Sequential
Interleave
Wrap type
A6-A4
CAS Latency
000
001
010
011
100
101
110
111
R
R
2
Latency mode
3
R
R
R
R
Mode Register Write Timing
Remark R : Reserved
CLOCK
CKE
CS
RAS
CAS
WE
A0-A11
Mode Register Write
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2005
Revision : 1.0 7/28
ESMT
Extended Mode Register
M12S16161A
BA
1
A10
0
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address bus
0
0
0
DS PASR
X
X
Extended Mode Register Set
x =Don’t care
WT=0
A2-A0
000
2 Banks
001
010
011
100
101
110
111
1 Bank (Bank 0, BA=0)
1/2 Bank (BA=A10=0)
PASR
R
R
1/4 Bank (BA=A10=A9=0)
R
R
A6-A5
00
Driver Strength
Full Strength
1/2 Strength
1/4 Strength
R
DS
01
10
11
Remark R : Reserved
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2005
Revision : 1.0
8/28
ESMT
M12S16161A
Burst Length and Sequence
(Burst of Two)
Starting Address
Sequential Addressing
Interleave Addressing
(column address A0 binary)
Sequence (decimal)
Sequence (decimal)
0
1
0,1
1,0
0,1
1,0
(Burst of Four)
Starting Address
Sequential Addressing
Sequence (decimal)
0,1,2,3
Interleave Addressing
Sequence (decimal)
0,1,2,3
(column address A1-A0, binary)
00
01
10
11
1,2,3,0
1,0,3,2
2,3,0,1
3,0,1,2
2,3,0,1
3,2,1,0
(Burst of Eight)
Starting Address
Sequential Addressing
Sequence (decimal)
0,1,2,3,4,5,6,7
1,2,3,4,5,6,7,0
2,3,4,5,6,7,0,1
3,4,5,6,7,0,1,2
4,5,6,7,0,1,2,3
5,6,7,0,1,2,3,4
6,7,0,1,2,3,4,5
7,0,1,2,3,4,5,6
Interleave Addressing
Sequence (decimal)
0,1,2,3,4,5,6,7
1,0,3,2,5,4,7,6
2,3,0,1,6,7,4,5
3,2,1,0,7,6,5,4
4,5,6,7,0,1,2,3
5,4,7,6,1,0,3,2
6,7,4,5,2,3,0,1
7,6,5,4,3,2,1,0
(column address A2-A0, binary)
000
001
010
011
100
101
110
111
Full page burst is an extension of the above tables of Sequential Addressing, with the length being 256 for 1Mx16 divice.
POWER UP SEQUENCE
1.Apply power and start clock, attempt to maintain CKE= “H”, L(U)DQM = “H” and the other pin are NOP condition at the inputs.
2.Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3.Issue precharge commands for all banks of the devices.
4.Issue 2 or more auto-refresh commands.
5.Issue mode register set command to initialize the mode register.
Cf.)Sequence of 4 & 5 is regardless of the order.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2005
Revision : 1.0 9/28
ESMT
SIMPLIFIED TRUTH TABLE
M12S16161A
COMMAND
CKEn-1 CKEn
DQM BA A10/AP A9~A0 Note
CS RAS CAS WE
Mode Register Set
H
H
X
X
L
L
L
L
L
L
L
L
X
X
OP CODE
OP CODE
1,2
1,2
Register
Refresh
Extended Mode Register
Set
Auto Refresh
H
L
3
3
H
L
L
L
H
X
X
Entry
Self Refresh
Exit
L
H
L
H
X
L
H
X
H
H
X
H
3
L
H
H
H
X
X
X
X
X
X
3
Bank Active & Row Addr.
V
V
Row Address
Column
L
4
Auto Precharge Disable
Read &
L
H
L
H
Address
Column Address
4,5
Auto Precharge Enable
Auto Precharge Disable
Auto Precharge Enable
H
L
H
(A0~A7)
Column
Address
(A0~A7)
4
4,5
6
4
4
Write & Column
Address
H
X
L
H
L
L
X
V
Burst Stop
H
H
X
X
L
L
H
L
H
H
L
L
X
X
X
Bank Selection
Both Banks
V
X
L
H
Precharge
X
H
L
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
V
X
X
H
X
V
Clock Suspend or
Active Power Down
Entry
Exit
H
L
L
H
L
X
X
X
X
X
X
H
L
Entry
H
Precharge Power Down Mode
H
L
Exit
L
H
X
V
X
DQM
H
H
H
H
L
X
X
X
X
7
H
L
X
H
H
X
X
H
H
X
X
H
L
No Operation Command
Deep Power Down Mode
X
Entry
Exit
L
L
X
X
H
X
X
(V= Valid, X= Don’t Care, H= Logic High , L = Logic Low)
Note:
1. OP Code: Operation Code
A0~ A10/AP, BA: Program keys.(@MRS). BA=0 for MRS and BA=1 for EMRS.
2. MRS/EMRS can be issued only at both banks precharge state.
A new command can be issued after 2 clock cycle of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by “Auto”.
Auto / self refresh can be issued only at both banks idle state.
4. BA: Bank select address.
If “Low”: at read, write, row active and precharge, bank A is selected.
If “High”: at read, write, row active and precharge, bank B is selected.
If A10/AP is “High” at row precharge, BA ignored and both banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read /write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but
makes
Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2005
Revision : 1.0 10/28
ESMT
M12S16161A
Single Bit Read-Write-Read Cycle (Same Page) @CAS Latency=3, Burst Length=1
tC H
4
0
1
2
3
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
tC L
tC C
H I G H
t S H
C K E
C S
tR A S
tR C
*Note1
tR P
tR C D
tS S
tS H
tS S
R A S
C A S
tC C D
tS H
tS S
tS S
tS H
A D D R
R a
R b
C a
C b
C c
tS H
tS S
*Note2
*Note2,3
*Note2,3
*Note2,3
*Note4
*Note2
BS
BA
BS
BS
BS
BS
BS
*Note 3
*Note 3
*Note 3
*Note4
R b
R a
A10/AP
D Q
tR A C
tS A C
tS H
Qc
D b
Qa
tS L Z
tS S
tO H
tS H
tS S
W E
tS S
tS H
D Q M
Row A c t i ve
Read
W r i t e
Row A c t i ve
Rea d
Pr echar ge
: D o n ' t C a r e
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2005
Revision : 1.0 11/28
ESMT
M12S16161A
*Note: 1. All inputs expect CKE & DQM can be don’t care when CS is high at the CLK high going edge.
2. Bank active & read/write are controlled by BA.
BA
0
Active & Read/Write
Bank A
1
Bank B
3.Enable and disable auto precharge function are controlled by A10/AP in read/write command.
A10/AP
0
BA
0
Operation
Disable auto precharge, leave bank A active at end of burst.
Disable auto precharge, leave bank B active at end of burst.
Enable auto precharge, precharge bank A at end of burst.
Enable auto precharge, precharge bank B at end of burst.
1
1
0
1
4.A10/AP and BA control bank precharge when precharge command is asserted.
A10/AP BA
precharge
Bank A
0
0
1
0
1
X
Bank B
Both Banks
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2005
Revision : 1.0 12/28
ESMT
Power Up Sequence
M12S16161A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
C K E
H i g h l e v e l i s n e c e s s a r y
CS
t R C
t R C
t R P
RAS
CAS
A D D R
R A a
K e y
BA
A10/AP
D Q
K e y
K e y
R A a
H i g h - Z
WE
D Q M
H i g h l e v e l i s n e c e s s a r y
M o d e R e g i s t e r S e t
P r e c h a r g e
A l l B a n k s
A u t o R e f r e s h
A u t o R e f r e s h
( A - B a n k )
R o w A c t i v e
:
D o n ' t c a r e
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2005
Revision : 1.0 13/28
ESMT
Read & Write Cycle at Same Bank @Burst Length = 4
M12S16161A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
HIGH
*Note1
tRC
CS
tRCD
RAS
CAS
*Note2
ADDR
Ra
Rb
Cb0
Ca0
BA
A10/AP
Ra
Rb
tOH
Qa1
CL=2
CL=3
Qa2
Qa3
Db2
Qa0
Db1
Db3
Db0
Db0
tRAC
*Note4
tSHZ
QC
tSHZ
Qa3
*Note3
tSAC
tRDL
tOH
Qa1
Qa0
Qa2
Db2
Db1
Db3
tRAC
*Note4
tSAC
*Note3
tRDL
WE
DQM
Precharge
(A-Bank)
Row Active
(A-Bank)
Row Active
(A-Bank)
Precharge
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
: Don't care
*Note: 1.Minimum row cycle times is required to complete internal DRAM operation.
2.Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row
precharge. Last valid output will be Hi-Z(tSHZ) after the clock.
3.Access time from Row active command. tcc*(tRCD +CAS latency-1)+tSAC
4.Ouput will be Hi-Z after the end of burst.(1,2,4,8 bit burst)
Burst can’t end in Full Page Mode.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2005
Revision : 1.0 14/28
ESMT
M12S16161A
Page Read & Write Cycle at Same Bank @ Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
HIGH
CS
tRCD
RAS
*Note2
CAS
ADDR
BA
Ra
Cb0
Ca0
Cc0
Cd0
A10/AP
Ra
tRDL
CL=2
Qa0
Qb0
Qb1
Qb0
Dc0
Dc0
Dc1
Dd1
Qb2
Qb1
Qa1
Qa0
Dd0
DQ
Qa1
Dc1 Dd0
Dd2
CL=3
tCDL
WE
*Note3
*Note1
DQM
Read
(A-Bank)
Write
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
: Don't care
*Note :1.To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus
contention.
2.Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3.DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2005
Revision : 1.0 15/28
ESMT
Page Read Cycle at Different Bank @ Burst Length=4
M12S16161A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
HIGH
*Note1
CS
RAS
CAS
ADDR
BA
*Note2
RAa
CAc
CAa
CBd
RBb
RBb
CBb
CAe
RAa
A10/AP
CL=2
QAa0 QAa1
QAa3
QAa2
QBb1
QBb0
QAa2
QBb0
QAa3
QBb2
QBb1
QBb3 QAc0
QBd1 QAe0
QAc1 QBd0
QAe1
DQ
CL=3
QAa0 QAa1
QBb2
QBb3 QAc0
QBd1 QAe0
QAc1 QBd0
QAe1
WE
DQM
Read
(B-Bank)
Read
(B-Bank)
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Row Active
(B-Bank)
: Don't care
*Note: 1. CS can be don’t cared when RAS , CAS and WE are high at the clock high going dege.
2.To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2005
Revision : 1.0 16/28
ESMT
Page Write Cycle at Different Bank @Burst Length = 4
M12S16161A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLOCK
CKE
HIGH
CS
RAS
CAS
*Note2
CAa
ADDR
BA
CBb
CAc
RBb
CBd
RAa
A10/AP
DQ
RAa
RBb
DBb3 DAc0 DAc1
DBb2
DAa1 DAa2
DBb0 DBb1
DBd0
DAa0
DAa3
DBd1
tCDL
tRDL
WE
*Note1
DQM
Precharge
(Both Banks)
Row Active
(A-Bank)
Write
(B-Bank)
Row Active
(B-Bank)
Write
(A-Bank)
Write
(A-Bank)
Write
(B-Bank)
: Don't care
*Note: 1.To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2.To interrupt burst write by row precharge, both the write and the precharge banks must be the same.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2005
Revision : 1.0 17/28
ESMT
Read & Write Cycle at Different Bank @ Burst Length = 4
M12S16161A
*Note: 1.tCDL should be met to complete write.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2005
Revision : 1.0
18/28
ESMT
M12S16161A
Read & Write Cycle with auto Precharge @ Burst Length =4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
C K E
H I G H
C S
RA S
C A S
A D D R
C b
R a
R b
C a
BA
A10/AP
R a
R b
CL= 2
D Q
Qa1 Qa2
Qa3
Qa2
Qa0
Db0
Db0
Db1
Db2
Db3
Db3
CL= 3
Qa1
Qa3
Qa0
Db1 Db2
W E
D Q M
Row Active
( A - Bank )
Read with
Auto Precharge
( A - Bank )
Auto Precharge
Start Point
( A - Bank)
W r i t e wi t h
Auto Pr echarge
( B- Bank )
Aut o Pr echarge
Star t Poin t
( B- Bank )
Row Active
( B - Bank )
: D o n ' t C a r e
*Note: 1.tCDL Should be controlled to meet minimum tRAS before internal precharge start
(In the case of Burst Length=1 & 2 and BRSW mode)
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2005
Revision : 1.0 19/28
ESMT
M12S16161A
Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
C K E
C S
RA S
CA S
A D D R
BA
R a
C a
C b
C c
R a
A10/AP
D Q
Qb0
Qa0
Qa1
Qa2
Qa3
Dc 2
Qb1
Dc 0
tS H Z
tS H Z
W E
* N o t e 1
D Q M
Cl oc k
Suspension
W r i t e
D Q M
Row A c t i ve
Read
Read
W r i t e
D Q M
Cl oc k
Suspension
Read D Q M
W r i t e
:D on' t C ar e
*Note:1.DQM is needed to prevent bus contention.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2005
Revision : 1.0 20/28
ESMT
M12S16161A
Read Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length =Full page
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
H I G H
C K E
CS
RAS
CAS
A D D R
BA
CA a
CA b
RA a
A10/AP
RA a
*Note2
QAa3 QAa4
1
1
QAa2
QAa1
QAb0
QAb1
QAb0
QAb5
QAb3 QAb4
QAa0
CL = 2
QAa1
QAa0
QAb2
D Q
2
2
QAa2 QAa3 QAa4
CL= 3
WE
QAb4
QAb3
QAb1 QAb2
QAb5
D Q M
Rea d
(A - Ban k )
Bur st Sto p
Prech arg e
( A- B an k )
Read
( A - Ban k )
Row A c t i ve
( A- B an k )
:D o n' t C a r e
*Note: 1.Burst can’t end in full page mode, so auto precharge can’t issue.
2.About the valid DQs after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the label 1,2 on them.
But at burst write, burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of “Full page write burst stop cycle”.
3.Burst stop is valid at every burst length.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2005
Revision : 1.0 21/28
ESMT
M12S16161A
Write Interrupted by Precharge Command & Write Burst stop Cycle @ Burst Length =Full page
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
C K E
H I G H
C S
RA S
CA S
RA a
CA a
A D D R
BA
CA b
A10 /AP
RA a
tB D L
tR D L
* N o t e 2
D Q
DAa0
DAb2 DAb3
DAb0 DAb1
DAb4
DAa1 DAa2 DAa3 DAa4
DAb5
W E
D Q M
W ri t e
(A - Ban k )
Ro w A c t i ve
( A- B an k )
Burst Stop
W r i t e
( A - Ba n k )
Pre ch ar g e
( A- B an k )
:D on ' t C ar e
*Note: 1. Burst can’t end in full page mode, so auto precharge can’t issue.
2.Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by
AC parameter of tRDL.
DQM at write interrupted by precharge command is needed to prevent invalid write.
Input data after Row precharge cycle will be masked internally.
3.Burst stop is valid at every burst length.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2005
Revision : 1.0 22/28
ESMT
Burst Read Single bit Write Cycle @Burst Length=2
M12S16161A
C L O C K
* N o t e 1
H I G H
C K E
C S
RA S
* N o t e 2
CA S
CA a RB b CA b
RA a
RA a
C B c
A D D R
BA
R A c
CA d
A10/AP
R A c
RB b
CL= 2
CL= 3
DAa0
QAb0 QAb1
QAd0 QAd1
QAd0 QAd1
DBc 0
DBc 0
D Q
QAb0 QAb1
DAa0
W E
D Q M
Ro w A c t i ve
( A- B an k )
Rea d
Row A c t i ve
( A- B an k )
Pr ech ar g e
Row Active
(B-Bank)
( A- B an k )
( A- B an k )
W r i t e wi t h
Auto Pr echar g e
( B- Ba nk )
Read with
Auto Precharge
(A-Bank)
W r i t e
( A - Ba n k )
:D on ' t C ar e
*Note:1.BRSW modes is enabled by setting A9 “High” at MRS(Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to “1” regardless of programmed burst length.
2.When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated.
Auto precharge is executed at the next cycle of burst-end, so in the case of BRSW write command, the precharge
command will be issued after two clock cycles.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2005
Revision : 1.0 23/28
ESMT
M12S16161A
Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
* N o t e 2
tSS
tS S
tSS
* N o t e 1
C K E
*Note3
C S
RA S
CA S
R a
C a
A D D R
B A
A10/AP
R a
tS H Z
Qa0
Qa2
Qa1
D Q
W E
D Q M
Pr ech ar ge
Pow er - D ow n
E ntr y
Row Active
Read
P r e c h a r g e
Precharge
Power-Down
Exit
Active
Active
Power-down
Entry
Power-down
Exit
:
D o n ' t c a r e
*Note :1.Both banks should be in idle state prior to entering precharge power down mode.
2.CKE should be set high at least 1CLK+tss prior to Row active command.
3.Can not violate minimum refresh specification. (32ms)
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2005
Revision : 1.0 24/28
ESMT
Self Refresh Entry & Exit Cycle
M12S16161A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
C L O C K
C K E
* N o t e 2
* N o t e 4
tR C m i n
* N o t e 6
* N o t e 1
tS S
*Note3
* N o t e 5
C S
RA S
CA S
* N o t e 7
A D D R
BA
A10 /AP
H i - Z
H i - Z
D Q
W E
D Q M
S e l f R e f r e s h E xi t
S e l f R e f r e s h E n t r y
A u t o R e f r e s h
:
D o n ' t c a r e
*Note: TO ENTER SELF REFRESH MODE
1. CS ,RAS & CAS with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.
3. The device remains in self refresh mode as long as CKE stays “Low”.
cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System clock restart and be stable before returning CKE high.
5. CS Starts from high.
6. Minimum tRC is required after CKE going high to complete self refresh exit.
7. 2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst
refresh.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2005
Revision : 1.0 25/28
ESMT
M12S16161A
Mode Register Set Cycle
Auto Refresh Cycle
1
2
3
4
5
6
0
1
2
3
4
5
6
7
8
9
10
0
C L O C K
H I G H
H I G H
C K E
C S
*Note2
tR C
RA S
*Note 1
*Note3
CA S
Key
A D D R
R a
D Q
W E
H i - Z
H i - Z
D Q M
M R S
New C om m an d
Au to Ref res h
Ne w C om m a n d
:D on ' t C ar e
*Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
*Note: 1. CS ,RAS , CAS & WE activation at the same clock cycle with address key will set internal mode register.
2.Minimum 2 clock cycles should be met before new RAS activation.
3.Please refer to Mode Register Set table.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2005
Revision : 1.0 26/28
ESMT
PACKAGE DIMENSIONS
M12S16161A
50-LEAD TSOP(II) SDRAM(400mil)
Dimension in mm
Dimension in inch
Symbol
Min
-
Nom
-
Max
1.20
Min
-
Nom
Max
A
A1
A2
B
-
0.005
0.039
-
0.014
-
0.047
0.008
0.041
0.018
0.016
0.008
0.006
0.830
0.471
0.405
0.024
0.051
0.95
0.30
0.30
0.12
0.10
20.82
11.56
10.03
0.40
0.127
1.00
-
0.35
-
0.203
1.05
0.002
0.037
0.012
0.012
0.005
0.004
0.820
0.455
0.394
0.016
0.45
B1
C
0.40
0.21
C1
D
0.127
20.95
11.76
10.16
0.50
0.80 REF
0.80 BSC
-
0.16
0.005
0.825
0.463
0.400
0.020
0.031 REF
0.031 BSC
-
21.08
11.96
10.29
0.60
E
E1
L
L1
e
θ
0
8
0
8
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2005
Revision : 1.0 27/28
ESMT
M12S16161A
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or by
any means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at the
time of publication. ESMT assumes no responsibility for any error in this
document, and reserves the right to change the products or specification in
this document without notice.
The information contained herein is presented only as a guide or examples
for the application of our products. No responsibility is assumed by ESMT for
any infringement of patents, copyrights, or other intellectual property rights of
third parties which may result from its use. No license, either express ,
implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of ESMT or others.
Any semiconductor devices may have inherently a certain rate of failure. To
minimize risks associated with customer's application, adequate design and
operating safeguards against injury, damage, or loss from such failure,
should be provided by the customer when making application designs.
ESMT's products are not authorized for use in critical applications such as,
but not limited to, life support devices or system, where failure or abnormal
operation may directly affect human lives or cause physical injury or property
damage. If products described here are to be used for such kinds of
application, purchaser must do its own quality assurance testing appropriate
to such applications.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2005
Revision : 1.0 28/28
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