F59D2G81LA-45TG [ESMT]
2 Gbit (256M x 8 / 128M x 16) 1.8V NAND Flash Memory;
| 型号： | F59D2G81LA-45TG |
| 厂家： | 
ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. |
| 描述： | 2 Gbit (256M x 8 / 128M x 16) 1.8V NAND Flash Memory |
| 文件： | 总56页 (文件大小：2100K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESMT
F59D2G81LA / F59D2G161LA
Flash
2 Gbit (256M x 8 / 128M x 16)
1.8V NAND Flash Memory
FEATURES
Voltage Supply: 1.8V (1.7V ~ 1.95V)
Organization
Command/Address/Data Multiplexed I/O Port
Hardware Data Protection
x8:
- Program/Erase Lockout During Power Transitions
- Memory Cell Array: (256M + 8M) x 8bit
- Data Register: (2K + 64) x 8bit
x16:
Reliable CMOS Floating Gate Technology
- ECC Requirement: x8 – 1bit/512Byte
x16 - 1bit/256 Word
- Memory Cell Array: (128M + 4M) x 16bit
- Data Register: (1K + 32) x 16bit
- Endurance: 100K Program/Erase cycles
- Data Retention: 10 years
Automatic Program and Erase
x8:
- Page Program: (2K + 64) byte
- Block Erase: (128K + 4K) byte
Command Register Operation
Automatic Page 0 Read at Power-Up Option
- Boot from NAND support
- Automatic Memory Download
x16:
NOP: 4 cycles
- Page Program: (1K + 32) word
- Block Erase: (64K + 2K) word
Page Read Operation
- Page Size: (2K + 64) Byte (x8)
Page Size: (1K + 32) Word (x16)
- Random Read: 25us (Max.)
- Serial Access: 45ns (Min.)
Cache Program/Read Operation
Copy-Back Operation
Two-Plane Operation
EDO mode
Bad-Block-Protect
Memory Cell: 1bit/Memory Cell
Fast Write Cycle Time
- Program time: 450us (Typ.)
- Block Erase time: 3.5ms (Typ.)
ORDERING INFORMATION
Product ID
Speed
Package
Comments
x8:
F59D2G81LA -45TG
F59D2G81LA -45BG
x16:
45 ns
45 ns
48 pin TSOPI
63 ball BGA
Pb-free
Pb-free
F59D2G161LA -45BG 45 ns
63 ball BGA
Pb-free
GENERAL DESCRIPTION
The device is a 256Mx8bit with spare 8Mx8bit capacity (or
128Mx16bit with spare 4Mx16bit capacity). The device is offered
in 1.8V VCC Power Supply. Its NAND cell provides the most
cost-effective solution for the solid state mass storage market.
The memory is divided into blocks that can be erased
independently so it is possible to preserve valid data while old
data is erased.
Word. The I/O pins serve as the ports for address and command
inputs as well as data input/output. The copy back function
allows the optimization of defective blocks management: when a
page program operation fails the data can be directly
programmed in another page inside the same array section
without the time consuming serial data insertion phase. The
cache program feature allows the data insertion in the cache
register while the data register is copied into the Flash array.
This pipelined program operation improves the program
throughput when long files are written inside the memory. A
cache read feature is also implemented. This feature allows to
dramatically improving the read throughput when consecutive
pages have to be streamed out. This device includes extra
feature: Automatic Read at Power Up.
The device contains 2048 blocks, composed by 64 pages
consisting in two NAND structures of 32 series connected Flash
cells. A program operation allows to write the 1056-Word page in
typical 350us and an erase operation can be performed in typical
3.5ms on a 128K-Byte for X8 device block (or 64K-Word for X16
device block).
Data in the page mode can be read out at 45ns cycle time per
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0
1/56
ESMT
F59D2G81LA / F59D2G161LA
PIN CONFIGURATION (x8) (TOP VIEW)
(TSOPI 48L, 12mm X 20mm Body, 0.5mm Pin Pitch)
NC
NC
NC
NC
NC
NC
R/B
RE
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
NC
NC
VCC
VSS
NC
CE
9
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
NC
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
NC
BALL CONFIGURATION (x8) (TOP VIEW)
(BGA 63 BALL, 9mm X 11mm Body, 0.8 Ball Pitch)
1
2
3
4
5
6
7
8
9
10
NC
NC
A
B
C
D
E
F
NC
NC
NC
NC
NC
WP
NC
ALE
VSS
CLE
CE
NC
NC
WE
NC
NC
R / B
NC
RE
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
G
H
J
NC
NC
NC
I/O0
VCC
NC
NC
NC
NC
I/O5
I/O7
VSS
I/O1
I/O2
VCC
NC
I/O6
VSS
I/O3
I/O4
K
L
NC
NC
NC
NC
NC
NC
NC
NC
M
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 2/56
ESMT
F59D2G81LA / F59D2G161LA
BALL CONFIGURATION (x16) (TOP VIEW)
(BGA 63 BALL, 9mm X 11mm Body, 0.8 Ball Pitch)
1
2
3
4
5
6
7
8
9
10
NC
NC
A
B
C
D
E
F
NC
NC
NC
NC
NC
WP
NC
ALE
VSS
CLE
CE
NC
NC
NC
WE
NC
NC
R / B
NC
RE
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
I/O13 I/O15
G
H
J
NC
NC
I/O8
I/O0
VCC
I/O10 I/O12 I/O14
I/O5
I/O6
I/O7
VSS
I/O9
VSS
I/O1 I/O11
VCC
I/O4
I/O2
I/O3
K
L
NC
NC
NC
NC
NC
NC
NC
NC
M
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 3/56
ESMT
F59D2G81LA / F59D2G161LA
Pin Description
Symbol
Pin Name
Functions
The I/O pins are used to input command, address and data, and to output data
during read operations. The I/O pins float to Hi-Z when the chip is deselected
or when the outputs are disabled.
I/O0~I/O7 (x8)
Data Inputs / Outputs
I/O0~I/O15 (x16)
The CLE input controls the activating path for commands sent to the internal
command register. Commands are latched into the command register through
Command Latch
Enable
CLE
the I/O ports on the rising edge of the WE signal with CLE high.
The ALE input controls the activating path for addresses sent to the internal
address registers. Addresses are latched into the address register through the
ALE
CE
Address Latch Enable
Chip Enable
I/O ports on the rising edge of WE with ALE high.
The CE input is the device selection control. When the device is in the Busy
state, CE high is ignored, and the device does not return to standby mode in
program or erase operation. Regarding CE control during read operation,
refer to ’Page read’ section of Device operation.
The RE input is the serial data-out control, and when it is active low, it drives
Read Enable
Write Enable
Write Protect
RE
WE
WP
the data onto the I/O bus. Data is valid tREA after the falling edge of RE which
also increments the internal column address counter by one.
The WE input controls writes to the I/O port. Commands, address and data
are latched on the rising edge of the WE pulse.
The WP pin provides inadvertent program/erase protection during power
transitions. The internal high voltage generator is reset when the WP pin is
active low.
The R/
B
output indicates the status of the device operation. When low, it
indicates that a program, erase or random read operation is in process and
returns to high state upon completion. It is an open drain output and does not
float to Hi-Z condition when the chip is deselected or when outputs are
disabled.
Ready / Busy Output
R /
B
VCC
VSS
NC
Power
VCC is the power supply for device.
Ground
No Connection
Lead is not internally connected.
Note: Connect all VCC and VSS pins of each device to common power supply outputs. Do not leave VCC or VSS disconnected.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 4/56
ESMT
F59D2G81LA / F59D2G161LA
BLOCK DIAGRAM (x8)
ARRAY ORGANIZATION (x8)
Array Address (x8)
I/O0
A0
I/O1
A1
I/O2
A2
I/O3
A3
I/O4
A4
I/O5
A5
I/O6
A6
I/O7
A7
Address
1st cycle
2nd cycle
3rd cycle
4th cycle
5th cycle
NOTE:
Column Address
Column Address
Row Address
Row Address
Row Address
A8
A9
A10
A14
A22
L*
A11
A15
A23
L*
L*
L*
L*
L*
A12
A20
A28
A13
A21
L*
A16
A24
L*
A17
A25
L*
A18
A26
L*
A19
A27
L*
Column Address: Starting Address of the Register.
*L must be set to “Low”.
* The device ignores any additional input of address cycles than required.
A18 is for Plane Address setting.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0
5/56
ESMT
F59D2G81LA / F59D2G161LA
BLOCK DIAGRAM (x16)
ARRAY ORGANIZATION (x16)
Array Address (x16)
I/O0
A0
I/O1
A1
I/O2
A2
I/O3
A3
I/O4
A4
I/O5
A5
I/O6
A6
I/O7
A7
I/O8~I/O15
Address
1st cycle
2nd cycle
3rd cycle
4th cycle
5th cycle
NOTE:
Column Address
Column Address
Row Address
Row Address
Row Address
L*
L*
L*
L*
L*
A8
A9
A10
A13
A21
L*
L*
L*
L*
L*
L*
A11
A19
A27
A12
A20
L*
A14
A22
L*
A15
A23
L*
A16
A24
L*
A17
A25
L*
A18
A26
L*
Column Address: Starting Address of the Register.
*L must be set to “Low”.
* The device ignores any additional input of address cycles than required.
A17 is for Plane Address setting.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 6/56
ESMT
F59D2G81LA / F59D2G161LA
Product Introduction
The device is a 2,112Mbit memory organized as 64K rows (pages) by 2,112x8 columns. Spare 64x8 columns are located from column
address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommodating data transfer between the I/O
buffers and memory during page read and page program operations. The program and read operations are executed on a page basis,
while the erase operation is executed on a block basis. The memory array consists of 2048 separately erasable 128K-byte blocks. It
indicates that the bit-by-bit erase operation is prohibited on the device.
The device has addresses multiplexed into 8 or 16 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to
future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by
bringing WE to low while CE is low. Those are latched on the rising edge of WE . Command Latch Enable (CLE) and Address
Latch Enable (ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle.
For example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and
block erase and page program, require two cycles: one cycle for setup and the other cycle for execution.
In addition to the enhanced architecture and interface, the device incorporates copy-back program feature from one page to another
page without need for transporting the data to and from the external buffer memory.
Command Set
Acceptable Command
Function
1st Cycle
00h
2nd Cycle
30h
during Busy
Read
Read for Copy Back
Read ID
00h
35h
90h
-
O
Reset
FFh
-
Page Program
80h
10h
10h
D0h
-
Copy-Back Program
85h
Block Erase
60h
Random Data Input(1)
Random Data Output(1)
Read Status
85h
05h
E0h
-
O
O
70h
Read Status 2
F1h
-
Two-Plane Read(3)
60h-60h
60h-60h
00h-05h
80h-11h
85h-11h
60h-60h
80h
30h
35h
E0h
81h-10h
81h-10h
D0h
15h
-
Two-Plane Read for Copy-Back
Two-Plane Random Data Output (1)(3)
Two-Plane Page Program(2)
Two-Plane Copy-Back Program(2)
Two-Plane Block Erase
Cache Program
Cache Read
31h
Read Start For Last Page Cache Read
Two-Plane Cache Read(3)
Two-Plane Cache Program(2)
3Fh
-
60h-60h
80h-11h
33h
81h-15h
NOTE:
1. Random Data Input/Output can be executed in a page.
2. Any command between 11h and 80h/81h/85h is prohibited except 70h/F1h and FFh.
3. Two-Plane Random Data Output must be used after Two-Plane Read operation or Two-Plane Cache Read operation.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 7/56
ESMT
F59D2G81LA / F59D2G161LA
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
VCC
VIN
-0.6 to +2.54
Voltage on any pin relative to VSS
-0.6 to +2.54
V
VI/O
-0.6 to VCC + 0.3 (< 2.54V)
-40 to +125
Temperature Under Bias
Storage Temperature
Short Circuit Current
NOTE:
TBIAS
TSTG
℃
℃
-65 to +150
IOS
5
mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, TA = 0 to 70℃)
Parameter
Supply Voltage
Supply Voltage
Symbol
VCC
Min.
1.7
0
Typ.
1.8
0
Max.
1.95
0
Unit
V
VSS
V
DC AND OPERATION CHARACTERISTICS
(Recommended operating conditions otherwise noted)
Parameter
Page Read with
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
ICC1
-
15
20
tRC=45ns, CE=VIL, IOUT=0mA
Serial Access
Program
Erase
Operating
Current
mA
ICC2
ICC3
ISB1
-
-
-
-
-
15
15
-
20
20
1
Stand-by Current (TTL)
Stand-by Current (CMOS)
Input Leakage Current
mA
uA
CE=VIH, WP =0V/VCC
ISB2
ILI
-
10
50
CE= VCC -0.2, WP =0V/ VCC
VIN=0 to VCC (max)
±10
-
-
-
-
-
-
-
uA
uA
V
±10
VCC + 0.3
0.2 x VCC
-
Output Leakage Current
Input High Voltage
ILO
VOUT=0 to VCC (max)
-
(1)
VIH
-
0.8 x VCC
-0.3
(1)
Input Low Voltage, All inputs
Output High Voltage Level
Output Low Voltage Level
VIL
-
V
VOH
VOL
IOH=-100uA
IOL=+100uA
VCC - 0.1
-
V
0.1
V
VOL=0.2V
3
4
-
mA
Output Low Current (R/
B
)
B
IOL (R / )
NOTE:
1. VIL can undershoot to -0.4V and VIH can overshoot to VCC + 0.4V for durations of 20 ns or less.
2. Typical value are measured at VCC=1.8V, TA=25℃. Not 100% tested.
VALID BLOCK
Symbol
Min.
Typ.
Max.
Unit
NVB
2,008
-
2,048
Block
NOTE:
1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The
number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain
one or more bad bits which cause status failure during program and erase operation. Do not erase or program factory-marked bad
blocks. Refer to the attached technical notes for appropriate management of initial invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment.
3. The number of valid block is on the basis of single plane operations, and this may be decreased with two plane operations.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 8/56
ESMT
F59D2G81LA / F59D2G161LA
AC TEST CONDITION
(TA= 0 to 70℃, VCC=1.8V~1.95V, unless otherwise noted)
Parameter
Input Pulse Levels
Condition
0V to VCC
5 ns
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
VCC /2
1 TTL Gate and CL=30pF
CAPACITANCE
(TA=25℃, VCC=1.8V, f=1.0MHz)
Item
Symbol
Test Condition
VIL = 0V
Min.
Max.
10
Unit
pF
Input / Output Capacitance
Input Capacitance
CI/O
CIN
-
-
VIN = 0V
10
pF
NOTE: Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
H
ALE
L
Mode
Command Input
CE
L
WE
RE
H
WP
X
Read Mode
L
H
L
H
X
Address Input (5 clock)
Command Input
H
L
L
L
L
H
H
H
H
H
H
Write Mode
L
H
Address Input (5 clock)
L
L
Data Input
L
X
X
X
X
X
L
X
L
X
X
X
X
H
H
X
X
X
X
X
X
Data Output
H
X
X
X
X
X
During Read (Busy)
During Program (Busy)
During Erase (Busy)
Write Protect
X
H
H
X
X(1)
L
(2)
X
0V/VCC
Stand-by
NOTE:
1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 9/56
ESMT
F59D2G81LA / F59D2G161LA
Program / Erase Characteristics
Parameter
Symbol
tPROG
Min.
Typ.
450
-
Max.
950
Unit
us
Average Program Time
-
-
Dummy Busy Time for Cache Operation
tCBSY
950
us
Number of Partial Program Cycles in the
Same Page
NOP
tBERS
tDBSY
-
-
-
4
10
1
Cycle
ms
Block Erase Time
3.5
0.5
Dummy Busy Time for Two-Plane Page
Program
us
NOTE:
1. Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 1.8V VCC and 25℃
temperature.
2. tPROG is the average program time of all pages. Users should be noted that the program time variation from page to page is
possible.
3. tCBSY max. time depends on timing between internal program completion and data-in.
AC Timing Characteristics for Command / Address / Data Input
Parameter
CLE Setup Time
Symbol
Min.
25
Max.
Unit
ns
(1)
tCLS
-
-
CLE Hold Time
CE Setup Time
CE Hold Time
tCLH
10
ns
(1)
tCS
35
10
25
-
-
-
ns
ns
ns
tCH
tWP
WE Pulse Width
ALE Setup Time
ALE Hold Time
Data Setup Time
Data Hold Time
Write Cycle Time
(1)
tALS
25
10
20
10
45
-
-
-
-
-
ns
ns
ns
ns
ns
tALH
(1)
tDS
tDH
tWC
tWH
15
100(2)
-
-
ns
ns
WE High Hold Time
(2)
Address to Data Loading Time
tADL
NOTE:
1. The transition of the corresponding control pins must occur only once while WE is held low.
2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 10/56
ESMT
F59D2G81LA / F59D2G161LA
AC Characteristics for Operation
Parameter
Symbol
Min.
-
Max.
25
Unit
us
Data Transfer from Cell to Register
tR
tAR
10
-
ns
ALE to RE Delay
tCLR
tRR
tRP
10
20
25
-
-
ns
ns
ns
ns
CLE to RE Delay
-
-
Ready to RE Low
RE Pulse Width
tWB
100
WE High to Busy
WP Low to WE Low (disable mode)
tWW
100
-
ns
WP High to WE Low (enable mode)
Read Cycle Time
tRC
45
-
-
ns
ns
tREA
30
RE Access Time
tCEA
tRHZ
tCHZ
tCSD
tRHOH
tRLOH
tCOH
tREH
tIR
-
-
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE Access Time
100
RE High to Output Hi-Z
CE High to Output Hi-Z
CE High to ALE or CLE Don’t Care
RE High to Output Hold
RE Low to Output Hold
CE High to Output Hold
RE High Hold Time
-
30
-
0
15
5
-
-
15
15
0
-
-
-
Output Hi-Z to RE Low
RE High to WE Low
tRHW
tWHR
100
60
-
-
WE High to RE Low
Read
-
-
-
-
5
us
us
us
us
Program
Erase
10
Device Resetting
Time during ...
tRST
500
5(1)
Ready
Cache Busy in Read Cache (following
31h and 3Fh)
tDCBSYR
-
30
us
NOTE: 1. If reset command (FFh) is written at Ready state, the device goes into Busy for maximum 5us.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 11/56
ESMT
F59D2G81LA / F59D2G161LA
NAND Flash Technical Notes
Mask Out Initial Invalid Block(s)
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by ESMT. The
information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s) have the
same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not
affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The
system design must be able to mask out the initial invalid block(s) via address mapping.
The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte
(1bit/256Word) ECC.
Identifying Initial Invalid Block(s) and Block Replacement Management
All device locations are erased (FFh) except locations where the initial invalid block(s) information is written prior to shipping. The initial
invalid block(s) status is defined by the 1st byte in the spare area. ESMT makes sure that either the 1st or 2nd page of every initial
invalid block has non-FFh data at the 1st byte column address in the spare area.
Do not erase or program factory-marked bad blocks. The host controller must be able to recognize the initial invalid block information
and to create a corresponding table to manage block replacement upon erase or program error when additional invalid blocks develop
with Flash memory usage.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 12/56
ESMT
F59D2G81LA / F59D2G161LA
Check “FFh” at the 1st Byte column address in
the spare area of the 1st or 2nd page in the
block.
For (i=0; i<Num_of_LUs; i++)
{
For (j=0; j<Blocks_Per_LU; j++)
{
Defect_Block_Found=False;
Read_Page(lu=i, block=j, page=0);
If (Data[coloumn=First_Byte_of_Spare_Area]!=FFh) Defect_Block_Found=True;
Read_Page(lu=i, block=j, page=1);
If (Data[coloumn=First_Byte_of_Spare_Area]!=FFh) Defect_Block_Found=True;
If (Defect_Block_Found)
Mark_Block_as_Defective(lu=i, block=j);
}
}
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 13/56
ESMT
F59D2G81LA / F59D2G161LA
Error in Write or Read Operation
Within its lifetime, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.
The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after
erase or program, block replacement should be done. Because program status fail during a page program does not affect the data of
the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and
reprogramming the current target data and copying the rest of the replaced block. In case of Read, ECC must be employed. To
improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by
ECC without any block replacement. The additional block failure rate does not include those reclaimed blocks.
Failure Mode
Erase failure
Detection and Countermeasure sequence
Read Status after Erase → Block Replacement
Read Status after Program → Block Replacement
Verify ECC → ECC Correction
Write
Read
Program failure
Up to 1 bits failure
NOTE: Error Correcting Code →RS Code or BCH Code etc.
Example: 1bit / 512 Byte
Program Flow Chart
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 14/56
ESMT
F59D2G81LA / F59D2G161LA
Erase Flow Chart
Read Flow Chart
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0
15/56
ESMT
F59D2G81LA / F59D2G161LA
Block Replacement
Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB (Least Significant Bit) page of the block to MSB (Most
Significant Bit) pages of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB
among the pages to be programmed. Therefore, LSB page doesn’t need to be page 0.
(64)
Page 63
(64)
Page 63
:
(32)
:
:
(1)
:
Page 31
Page 31
Page 2
Page 1
Page 0
Page 2
Page 1
Page 0
(3)
(2)
(1)
(3)
(32)
(2)
Data register
Data register
From the LSB page to MSB page
Ex.) Random page program (Prohibition)
DATA IN: Data (1)
Data (64)
DATA IN: Data (1)
Data (64)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 16/56
ESMT
F59D2G81LA / F59D2G161LA
System Interface Using CE Don’t Care
For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2,112byte
(1,056word) data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications that use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and serial
access would provide significant savings in power consumption.
Program/Read Operation with ”CE not-care”
Address Information
I/O
DATA
ADDRESS
Row Add1
Device
I/Ox
Data In / Out
Col. Add1
Col. Add2
Row Add2
Row Add3
F59D2G81LA
(x8)
I/O0~7
2,112 Byte
1,056 Byte
A0 ~ A7
A8 ~ A11
A12 ~ A19
A11 ~ A18
A20 ~ A27
A28
F59D2G161LA
(x16)
I/O0~15
A0 ~ A7
A8 ~ A10
A19 ~ A26
A27
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 17/56
ESMT
F59D2G81LA / F59D2G161LA
Timing Diagrams
Command Latch Cycle
Address Latch Cycle
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0
18/56
ESMT
F59D2G81LA / F59D2G161LA
Input Data Latch Cycle
Serial Access Cycle after Read (CLE = L, ALE = L, WE = H)
NOTE:
1. Dout transition is measured at ±200mV from steady state voltage at I/O with load.
2. tRHOH starts to be valid when frequency is lower than 20MHz.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 19/56
ESMT
F59D2G81LA / F59D2G161LA
Serial Access Cycle after Read (EDO Type CLE = L, ALE = L, WE = H)
NOTE:
1. Transition is measured at ±200mV from steady state voltage with load.
This parameter is sample and not 100% tested. (tCHZ, tRHZ
2. tRLOH is valid when frequency is higher than 20MHZ.
)
tRHOH starts to be valid when frequency is lower than 20MHZ.
Status Read Cycle
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 20/56
ESMT
F59D2G81LA / F59D2G161LA
Read Operation (Read One Page)
Read Operation (Intercepted byCE
)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0
21/56
ESMT
F59D2G81LA / F59D2G161LA
Random Data Output In a Page
Page Program Operation
NOTE: tADL is the time from the WE rising edge of final address cycle to the WE rising edge of the first data cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 22/56
ESMT
F59D2G81LA / F59D2G161LA
Page Program Operation with Random Data Input
NOTE: tADL is the time from the WE rising edge of final address cycle to the WE rising edge of the first data cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 23/56
ESMT
F59D2G81LA / F59D2G161LA
Copy-Back Operation with Random Data Input
Cache Program Operation
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0
24/56
ESMT
F59D2G81LA / F59D2G161LA
Cache Read Operation
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0
25/56
ESMT
F59D2G81LA / F59D2G161LA
Block Erase Operation
Read ID Operation
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0
26/56
ESMT
F59D2G81LA / F59D2G161LA
Two-plane Page Read Operation with Two-plane Random Data Out
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 27/56
ESMT
F59D2G81LA / F59D2G161LA
Two-plane Cache Read Operation
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0
28/56
ESMT
F59D2G81LA / F59D2G161LA
Two-plane Page Program Operation
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0
29/56
ESMT
F59D2G81LA / F59D2G161LA
Two-plane Cache Program Operation
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0
30/56
ESMT
F59D2G81LA / F59D2G161LA
Two-plane Block Erase Operation
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0
31/56
ESMT
F59D2G81LA / F59D2G161LA
ID Definition Table
ID Access command = 90H
1st Cycle
(Maker Code) (Device Code)
2nd Cycle
Product ID
3rd Cycle
4th Cycle
5th Cycle
F59D2G81LA (x8)
C8h
C8h
AAh
BAh
90h
90h
15h
55h
46h
46h
F59D2G161LA(x16)
Description
1st Byte
2nd Byte
3rd Byte
4th Byte
5th Byte
Maker Code
Device Code
Internal Chip Number, Cell Type, etc
Page Size, Block Size, etc
Plane Number, Plane Size, ECC Level
3rd ID Data
Description
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1
2
4
8
0
0
1
1
0
1
0
1
Internal Chip Number
Cell Type
2 Level Cell
4 Level Cell
8 Level Cell
16 Level Cell
1
2
4
8
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
Number of
Simultaneously
Programmed Page
Not Support
Support
Not Support
Support
0
1
Interleave Program
Between multiple chips
0
1
Cache Program
4th ID Data
Description
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1KB
2KB
4KB
8KB
0
0
1
1
0
1
0
1
Page Size
(w/o redundant area)
8
16
0
1
Redundant Area Size
(byte/512byte)
64KB
128KB
256KB
512KB
x8
0
0
1
1
0
1
0
1
Block Size
(w/o redundant area)
0
1
Organization
x16
45ns
0
0
1
1
0
1
0
1
Reserved
Reserved
Reserved
Serial Access Time
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 32/56
ESMT
F59D2G81LA / F59D2G161LA
5th ID Data
Description
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1
2
4
8
0
0
1
1
0
1
0
1
Plane Number
64Mb
128Mb
256Mb
512Mb
1Gb
2Gb
4Gb
8Gb
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Plane Size
(w/o redundant area)
Reserved
Reserved
0
0
0
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 33/56
ESMT
F59D2G81LA / F59D2G161LA
DEVICE OPERATION
Page Read
Upon initial device power up, the device defaults to Read mode. This operation is also initiated by writing 00h command, five-cycle
address, and 30h command. After initial power up, the 00h command can be skipped because it has been latched in the command
register. The 2,112Byte (1,056Word) of data on a page are transferred to cache registers via data registers within 25us (tR). Host
controller can detect the completion of this data transfer by checking the R/
B
output. Once data in the selected page have been
loaded into cache registers, each Byte can be read out in 45ns cycle time by continuously pulsing RE . The repetitive high-to-low
transitions of RE clock signal make the device output data starting from the designated column address to the last column address.
The device can output data at a random column address instead of sequential column address by using the Random Data Output
command. Random Data Output command can be executed multiple times in a page.
After power up, device is in read mode so 00h command cycle is not necessary to start a read operation.
A page read sequence is illustrated in the following figure, where column address, page address are placed in between commands 00h
and 30h. After tR read time, the R/
B
de-asserts to ready state. Read Status command (70h) can be issued right after 30h. Host
controller can toggle RE to access data starting with the designated column address and their successive bytes.
Read Operation
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 34/56
ESMT
F59D2G81LA / F59D2G161LA
Random Data Output In a Page
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0
35/56
ESMT
F59D2G81LA / F59D2G161LA
Page Program
The device is programmed based on the unit of a page, and consecutive partial page programming on one page without intervening
erase operation is strictly prohibited. Addressing of page program operations within a block should be in sequential order. A complete
page program cycle consists of a serial data input cycle in which up to 2,112byte (1,056word) of data can be loaded into data register
via cache register, followed by a programming period during which the loaded data are programmed into the designated memory cells.
The serial data input cycle begins with the Serial Data Input command (80h), followed by a five-cycle address input and then serial data
loading. The bytes not to be programmed on the page do not need to be loaded. The column address for the next data can be changed
to the address follows Random Data Input command (85h). Random Data Input command may be repeated multiple times in a page.
The Page Program Confirm command (10h) starts the programming process. Writing 10h alone without entering data will not initiate
the programming process. The internal write engine automatically executes the corresponding algorithm and controls timing for
programming and verification, thereby freeing the host controller for other tasks. Once the program process starts, the host controller
can detect the completion of a program cycle by monitoring the R/
B
output or reading the Status bit (I/O6) using the Read Status
command. Only Read Status and Reset commands are valid during programming. When the Page Program operation is completed,
the host controller can check the Status bit (I/O0) to see if the Page Program operation is successfully done. The command register
remains the Read Status mode unless another valid command is written to it.
A page program sequence is illustrated in following figure, where column address, page address, and data input are placed in between
80h and 10h. After tPROG program time, the R/
B
de-asserts to ready state. Read Status command (70h) can be issued right after 10h.
Program & Read Status Operation
Random Data Input In a page
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0
36/56
ESMT
F59D2G81LA / F59D2G161LA
Cache Program
Cache Program is an extension of Page Program, which is executed with 2,112 byte (x8) or 1,056 word (x16) data registers, and is
available only within a block. Since the device has 1 page of cache memory, serial data input may be executed while data stored in
data register are programmed into memory cell.
After writing the first set of data up to 2,112 bytes (x8) or 1,056 word (x16) into the selected cache registers, Cache Program command
(15h) instead of actual Page Program (10h) is inputted to make cache registers free and to start internal program operation. To transfer
data from cache registers to data registers, the device remains in Busy state for a short period of time (tCBSY) and has its cache
registers ready for the next data-input while the internal programming gets started with the data loaded into data registers. Read Status
command (70h) may be issued to find out when cache registers become ready by polling the Cache-Busy status bit (I/O6). Pass/fail
status of only the previous page is available upon the return to Ready state. When the next set of data is inputted with the Cache
Program command, tCBSY is affected by the progress of pending internal programming. The programming of the cache registers is
initiated only when the pending program cycle is finished and the data registers are available for the transfer of data from cache
registers. The status bit (I/O5) for internal Ready/Busy may be polled to identity the completion of internal programming. If the system
monitors the progress of programming only with R/
actual Page Program command (10h).
B
, the last page of the target programming sequence must be programmed with
Cache Program (available only within a block)
NOTE:
1. Since programming the last page does not employ caching, the program time has to be that of Page Program. However, if the
previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after
completion of the previous cycle, which can be expressed as the following formula.
2. tPROG = Program time for the last page + Program time for the (last-1)th page – (Program command cycle time + Last page data
loading time)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 37/56
ESMT
F59D2G81LA / F59D2G161LA
Copy-Back Program
Copy-Back Program is designed to efficiently copy data stored in memory cells without time-consuming data reloading when there is
no bit error detected in the stored data. The benefit is particularly obvious when a portion of a block is updated and the rest of the block
needs to be copied to a newly assigned empty block. Copy-Back operation is a sequential execution of Read for Copy-Back and of
Copy-Back Program with Destination address. A Read for Copy-Back operation with “35h” command and the Source address moves
the whole 2,112 byte (1,056 word) data into the internal buffer. The host controller can detect bit errors by sequentially reading the data
output. Copy-Back Program is initiated by issuing Page-Copy Data-Input command (85h) with Destination address. If data modification
is necessary to correct bit errors and to avoid error propagation, data can be reloaded after the Destination address. Data modification
can be repeated multiple times as shown in the following figure. Actual programming operation begins when Program Confirm
command (10h) is issued. Once the program process starts, the Read Status command (70h) may be entered to read the status
register. The host controller can detect the completion of a program cycle by monitoring the R/
B
output, or the Status bit (I/O6) of the
Status Register. When the Copy-Back Program is complete, the Status Bit (I/O0) may be checked. The command register remains
Read Status mode until another valid command is written to it.
Page Copy-Back Program Operation
Page Copy-Back Program Operation with Random Data Input
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 38/56
ESMT
F59D2G81LA / F59D2G161LA
Block Erase
The block-based Erase operation is initiated by an Erase Setup command (60h), followed by a three-cycle row address, in which only
Plane address and Block address are valid while Page address is ignored. The Erase Confirm command (D0h) following the row
address starts the internal erasing process. The two-step command sequence is designed to prevent memory content from being
inadvertently changed by external noise.
At the rising edge of WE after the Erase Confirm command input, the internal control logic handles erase and erase-verify. When the
erase operation is completed, the host controller can check Status bit (I/O0) to see if the erase operation is successfully done. The
following figure illustrates a block erase sequence, and the address input (the first page address of the selected block) is placed in
between commands 60h and D0h. After tBERS erase time, the R/
B
de-asserts to ready state. Read Status command (70h) can be
issued right after D0h to check the execution status of erase operation.
Block Erase Operation
Read Status
A status register on the device is used to check whether program or erase operation is completed and whether the operation is
completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the status register to
I/O pins on the falling edge of CE or RE , whichever occurs last. These two commands allow the system to poll the progress of each
device in multiple memory connections even when R/
change.
B pins are common-wired. RE or CE does not need to toggle for status
Read Status command 70h is used to retrieve operating status of commands like page read, page program and block erase. Similarly,
Read Status Two-plane Command F1h is used to retrieve operating status of two-plane commands.
The command register remains in Read Status mode unless other commands are issued to it. Therefore, if the status register is read
during a random read cycle, a read command (00h) is needed to start read cycles.
Status Register Definition for 70h Command
I/O
Page Program
Block Erase Cache Program
Read
Cache Read
Definition
Pass: ”0”
Fail: ”1”
I/O0
Pass / Fail
Pass / Fail
NA
Pass / Fail (N)
NA
NA
Pass: ”0”
Fail: ”1”
I/O1
NA
Pass / Fail (N-1)
NA
NA
I/O2
I/O3
I/O4
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Don’t cared
Don’t cared
Don’t cared
Busy: ”0”
Ready: ”1”
True Ready /
Busy
True Ready /
Busy
I/O5
I/O6
I/O7
NA
NA
NA
Busy: ”0”
Ready: ”1”
Ready /
Busy
Ready /
Busy
Ready / Busy
Write Protect
Ready / Busy
Write Protect
Ready / Busy
Write Protect
Protected: ”0”
Not Protected: ”1”
Write Protect
Write Protect
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 39/56
ESMT
F59D2G81LA / F59D2G161LA
Status Register Definition for F1h Command
Cache
Program
I/O
Page Program
Block Erase
Read
NA
Cache Read
Definition
Pass: ”0”
Chip Pass /
Fail (N)
Chip Pass /
Fail
Chip Pass /
Fail
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
NA
NA
NA
NA
NA
Fail: ”1”
Pass: ”0”
Fail: ”1”
Plane0 Pass /
Fail
Plane0 Pass /
Fail
Plane0 Pass /
Fail (N)
NA
Pass: ”0”
Fail: ”1”
Plane1 Pass /
Fail
Plane1 Pass /
Fail
Plane1 Pass /
Fail (N)
NA
Pass: ”0”
Fail: ”1”
Plane0 Pass /
Fail (N-1)
NA
NA
NA
NA
NA
Pass: ”0”
Fail: ”1”
Plane1 Pass /
Fail (N-1)
NA
True Ready /
Busy
Busy: ”0”
Ready: ”1”
True Ready /
Busy
NA
NA
NA
Busy: ”0”
Ready: ”1”
Ready /
Busy
Ready / Busy
Write Protect
Ready / Busy
Write Protect
Ready / Busy
Write Protect
Ready / Busy
Write Protect
Protected: ”0”
Not Protected: ”1”
Write Protect
NOTE:
1. I/Os defined NA are recommended to be masked out when Read Status is being executed.
2. n : current page, n-1 : previous page.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 40/56
ESMT
F59D2G81LA / F59D2G161LA
Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h.
Four read cycles sequentially output the manufacturer code (C8h), and the device code and 3rd, 4th, 5th cycle ID respectively. The
command register remains in Read ID mode until further commands are issued to it.
Read ID Operation
ID Definition Table
1st Cycle
(Maker Code) (Device Code)
2nd Cycle
Product ID
3rd Cycle
4th Cycle
5th Cycle
F59D2G81LA (x8)
C8h
C8h
AAh
BAh
90h
90h
15h
55h
46h
46h
F59D2G161LA (x16)
Reset
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer
valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the
Status Register is cleared to value C0h when WP is high. If the device is already in reset state a new reset command will be
accepted by the command register. The R/
figure.
B pin changes to low for tRST after the Reset command is written. Refer to the following
Device Status
After Power-up
After Reset
Operation mode
00h Command is latched
Waiting for next command
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 41/56
ESMT
F59D2G81LA / F59D2G161LA
Cache Read
Cache Read is an extension of Page Read, and is available only within a block. The normal Page Read command (00h-30h) is always
issued before invoking Cache Read. After issuing the Cache Read command (31h), read data of the designated page (page N) are
transferred from data registers to cache registers in a short time period of tDCBSYR, and then data of the next page (page N+1) is
transferred to data registers while the data in the cache registers are being read out. Host controller can retrieve continuous data and
achieve fast read performance by iterating Cache Read operation. The Read Start for Last Page Cache Read command (3Fh) is used
to complete data transfer from memory cells to data registers.
Read Operation with Cache Read
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 42/56
ESMT
F59D2G81LA / F59D2G161LA
Two-Plane Page Program
Two-plane Page Program is an extension of Page Program, and which utilizes the two sets of 2,112-byte data registers to enable
simultaneous programming of same page of same block from each plane.
After writing the first set of data (up to 2,112 bytes) into the selected data registers, Dummy Page Program command (11h) instead of
Page Program command (10h) is input to finish data loading for the first memory plane. R/B# remains in Busy state for a short period of
time (tDBSY). Read Status (70h) may be issued to find out when the device returns to Ready state by polling the Status bit I/O6. The
second set of data for the other memory plane is loaded after the 81h command and address sequence. After that, the Page Program
command (10h) must be issued to start the programming process. Refer to Page Program command for the operation of R/
B
and
Read Status. The Status bit I/O0 is set to “1” when either page fails. The following figure shows the restriction in addressing with
Two-plane Page Program.
Read Command Sequence of Two-plane Page Program
NOTE: Any command between 11h and 81h is prohibited except 70h/F1h and FFh.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 43/56
ESMT
F59D2G81LA / F59D2G161LA
Two-Plane Page Read
The Two-plane Page Read sequence and its restrictions are shown in the following figure. Two-plane Page Read is initiated by
repeating command 60h followed the three address cycles twice, and only same page of same block can be selected from each plane.
Once the data is loaded into the cache registers, the data output of the first plane can be read out by issuing command 00h with five
address cycles, command 05h with two-cycle column address and finally E0h. The data output of the second plane can be read out
using the identical command sequence. Two-plane Read command can only must be used in a block which has been
programmed with Two-plane Page Program operation.
Two-Plane Block Erase
Similar to Two-plane Page Program, two symmetric blocks from each plane can be simultaneously erased by using Two-plane Block
Erase command. Following figure illustrates the Two-plane Block Erase sequence.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 44/56
ESMT
F59D2G81LA / F59D2G161LA
Two-Plane Cache Read
The Two-plane Cache Read sequence is shown in below, only same page of same block can be selected from each plane. After Read
Confirm command (33h), the data are transferred to data registers within tR. After issuing Cache Read command (31h), read data in the
data registers are transferred to cache registers within a short period of time (tDCBSYR). Once the data are loaded into the cache
registers, the data of both planes can be read out in the same way as the Two-Plane Page Read operation. The host controller shall
use 3Fh instead of 31h to indicate the Two-plane Cache Read operation for the last target pages.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 45/56
ESMT
F59D2G81LA / F59D2G161LA
Two-Plane Copy-Back Program
NOTE:
1. Copy Back Program operation is allowed only within the same memory plane.
2. Any command between 11h and 81h is prohibited except 70h/F1h and FFh.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 46/56
ESMT
F59D2G81LA / F59D2G161LA
Two-Plane Copy-Back Program with Random Data Input
NOTE:
1. Copy Back Program operation is allowed only within the same memory plane.
2. Any command between 11h and 81h is prohibited except 70h/F1h and FFh.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 47/56
ESMT
F59D2G81LA / F59D2G161LA
Two-Plane Cache Program Operation
NOTE: Any command between 11h and 81h is prohibited except 70h/F1h and FFh.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0
48/56
ESMT
F59D2G81LA / F59D2G161LA
Ready / Busy
The device has a R/
B
output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/
B
pin is normally high but transition to low after program or erase command is written to the command
register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The
B
B
pin is an open-drain driver thereby allowing two or more R/ outputs to be Or-tied. Because pull-up resistor value is related to tr (R/ )
and current drain during busy (ibusy), an appropriate value can be obtained with the following reference chart (the following figure). Its
value can be determined by the following guidance.
Read / Busy Pin Electrical Specifications
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 49/56
ESMT
F59D2G81LA / F59D2G161LA
Data Protection & Power Up Sequence
The timing sequence shown in the following figure is necessary for the power-on/off sequence.
The device internal initialization starts after the power supply reaches an appropriate level in the power on sequence. During the
initialization the device R/
commands are 70h.
B
signal indicates the Busy state as shown in the following figure. In this time period, the acceptable
The WP signal is useful for protecting against data corruption at power on/off.
AC Waveforms for Power Transition
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 50/56
ESMT
F59D2G81LA / F59D2G161LA
Write Protect Operation
Enabling WP during erase and program busy is prohibited. The erase and program operations are enabled and disabled as follows:
Enable Programming
Disable Programming
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 51/56
ESMT
F59D2G81LA / F59D2G161LA
Enable Erasing
Disable Erasing
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0
52/56
ESMT
F59D2G81LA / F59D2G161LA
PACKING DIMENSION
48-LEAD TSOP(I) ( 12x20 mm )
Dimension in mm
Min Norm Max
------- ------- 1.20 ------- ------- 0.047
0.05 ------- 0.15 0.006 ------- 0.002
Dimension in inch
Min Norm Max
Dimension in mm
Min Norm Max
20.00 BSC
Dimension in inch
Min Norm Max
0.787 BSC
Symbol
Symbol
A
A 1
A 2
b
b1
c
D
D 1
E
e
L
18.40 BSC
12.00 BSC
0.50 BSC
0.724 BSC
0.472 BSC
0.020 BSC
0.95 1.00
0.17 0.22
0.17 0.20
1.05 0.037 0.039 0.041
0.27 0.007 0.009 0.011
0.23 0.007 0.008 0.009
0.50 0.60
0O
-------
0.70 0.020 0.024 0.028
8O 0O 8O
-------
0.10 ------- 0.21 0.004 ------- 0.008
0.10 ------- 0.16 0.004 ------- 0.006
θ
c1
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 53/56
ESMT
F59D2G81LA / F59D2G161LA
PACKING DIMENSIONS
63-BALL
NAND Flash ( 9x11 mm )
E
Pin #1
D
A2
A
A1
Seating plane
C
ccc C
Detail A
Detail A
e
e
Solder ball
e
e
b
D1
Detail B
Pin #1
Index
E1
Detail B
Dimension in mm
Norm
Dimension in inch
Norm
Symbol
Min
Max
1.00
0.35
Min
Max
0.039
0.014
A
A1
A2
Φb
D
0.25
0.010
0.60 BSC
0.024 BSC
0.40
10.90
8.90
0.50
11.10
9.10
0.016
0.429
0.350
0.020
0.437
0.358
11.00
9.00
0.433
0.354
E
D1
E1
e
8.80 BSC
7.20 BSC
0.8 BSC
0.346 BSC
0.283 BSC
0.031 BSC
ccc
0.10
0.004
Controlling dimension : Millimeter.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 54/56
ESMT
F59D2G81LA / F59D2G161LA
Revision History
Revision
Date
Description
1.0
2018.06.08
Original
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0
55/56
ESMT
F59D2G81LA / F59D2G161LA
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or
by any means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at
the time of publication. ESMT assumes no responsibility for any error in
this document, and reserves the right to change the products or
specification in this document without notice.
The information contained herein is presented only as a guide or
examples for the application of our products. No responsibility is
assumed by ESMT for any infringement of patents, copyrights, or other
intellectual property rights of third parties which may result from its use.
No license, either express , implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of ESMT or
others.
Any semiconductor devices may have inherently a certain rate of failure.
To minimize risks associated with customer's application, adequate
design and operating safeguards against injury, damage, or loss from
such failure, should be provided by the customer when making
application designs.
ESMT's products are not authorized for use in critical applications such
as, but not limited to, life support devices or system, where failure or
abnormal operation may directly affect human lives or cause physical
injury or property damage. If products described here are to be used for
such kinds of application, purchaser must do its own quality assurance
testing appropriate to such applications.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jun. 2018
Revision: 1.0 56/56
相关型号：
©2020 ICPDF网 联系我们和版权申明