F25L08PA-50PIG [ESMT]
3V Only 8 Mbit Serial Flash Memory with Dual; 3V只有8兆位串行闪存，配有双
| 型号： | F25L08PA-50PIG |
| 厂家： | 
ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. |
| 描述： | 3V Only 8 Mbit Serial Flash Memory with Dual |
| 文件： | 总32页 (文件大小：490K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESMT
Flash
F25L08PA
Operation Temperature Condition -40°C~85°C
3V Only 8 Mbit Serial Flash Memory with Dual
FEATURES
y
y
Single supply voltage 2.7~3.6V
Standard, Dual SPI
y
y
Page Programming
- 256 byte per programmable page
y
Speed
Auto Address Increment (AAI) WORD Programming
- Decrease total chip programming time over
Byte Program operations
- Read max frequency: 33MHz
- Fast Read max frequency: 50MHz; 100MHz
- Fast Read Dual max frequency: 50MHz / 100MHz
(100MHz / 200MHz equivalent Dual SPI)
y
y
Lockable 4K bytes OTP security sector
y
Low power consumption
- Active current: 35 mA
- Standby current: 30μ A
SPI Serial Interface
- SPI Compatible: Mode 0 and Mode 3
y
y
End of program or erase detection
Write Protect ( WP )
y
y
Reliability
- 100,000 typical program/erase cycles
- 20 years Data Retention
y
y
Hold Pin (HOLD )
Program
All Pb-free products are RoHS-Compliant
- Byte programming time: 7μ s (typical)
- Page programming time: 1.5 ms (typical)
y
Erase
- Chip erase time 10 sec (typical)
- Block erase time 1 sec (typical)
- Sector erase time 90 ms (typical)
ORDERING INFORMATION
Product ID
Speed
Package
COMMENTS
Pb-free
F25L08PA –50PIG
F25L08PA –100PIG
F25L08PA –50PAIG
50MHz 8 lead SOIC
100MHz 8 lead SOIC
50MHz 8 lead SOIC
150mil
150mil
200mil
200mil
300mil
300mil
Pb-free
Pb-free
F25L08PA –100PAIG 100MHz 8 lead SOIC
Pb-free
F25L08PA –50DIG
F25L08PA –100DIG
50MHz 8 lead PDIP
100MHz 8 lead PDIP
Pb-free
Pb-free
GENERAL DESCRIPTION
The F25L08PA is a 8Megabit, 3V only CMOS Serial Flash
memory device. The device supports the standard Serial
Peripheral Interface (SPI), and a Dual SPI. ESMT’s memory
devices reliably store memory data even after 100,000
programming and erase cycles.
The device features sector erase architecture. The memory array
is divided into 256 uniform sectors with 4K byte each; 16 uniform
blocks with 64K byte each. Sectors can be erased individually
without affecting the data in other sectors. Blocks can be erased
individually without affecting the data in other blocks. Whole chip
erase capabilities provide the flexibility to revise the data in the
device. The device has Sector, Block or Chip Erase but no page
erase.
The memory array can be organized into 4,096 programmable
pages of 256 byte each. 1 to 256 byte can be programmed at a
time with the Page Program instruction. The device also can be
programmed to decrease total chip programming time with Auto
Address Increment (AAI) programming.
The sector protect/unprotect feature disables both program and
erase operations in any combination of the sectors of the
memory.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2009
Revision: 1.3
1/32
ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
PIN CONFIGURATIONS
8-PIN SOIC
1
8
VDD
CE
HOLD
SCK
SO
2
3
7
6
WP
SI
VSS
4
5
8-PIN PDIP
1
8
VDD
CE
HOLD
SCK
SO
2
3
7
6
WP
SI
VSS
4
5
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2009
Revision: 1.3 2/32
ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
PIN DESCRIPTION
Symbol
Pin Name
Functions
To provide the timing for serial input and
output operations
SCK
Serial Clock
To transfer commands, addresses or data
serially into the device.
SI
Serial Data Input
Data is latched on the rising edge of SCK.
To transfer data serially out of the device.
SO
CE
WP
Serial Data Output
Chip Enable
Data is shifted out on the falling edge of
SCK.
To activate the device when CE is low.
The Write Protect ( WP ) pin is used to
enable/disable BPL bit in the status
register.
Write Protect
To temporality stop serial communication
with SPI flash memory without resetting
the device.
Hold
HOLD
VDD
VSS
Power Supply
Ground
To provide power.
FUNCTIONAL BLOCK DIAGRAM
Flash
Address
Buffers
and
X-Decoder
Latches
Y-Decoder
I/O Butters
Control Logic
and
Data Latches
Serial Interface
CE
SCK
SO
WP
HOLD
SI
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2009
Revision: 1.3 3/32
ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
SECTOR STRUCTURE
Table 1: F25L08PA Sector Address Table
Block Address
Sector Size
(Kbytes)
Block
15
Sector
Address range
A19 A18 A17 A16
255
:
4KB
:
0FF000H – 0FFFFFH
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
:
240
239
:
4KB
4KB
:
0F0000H – 0F0FFFH
0EF000H – 0EFFFFH
14
13
12
11
10
9
:
224
223
:
4KB
4KB
:
0E0000H – 0E0FFFH
0DF000H – 0DFFFFH
:
208
207
:
4KB
4KB
:
0D0000H – 0D0FFFH
0CF000H – 0CFFFFH
:
192
191
:
4KB
4KB
:
0C0000H – 0C0FFFH
0BF000H – 0BFFFFH
:
176
175
:
4KB
4KB
:
0B0000H – 0B0FFFH
0AF000H – 0AFFFFH
:
160
159
:
4KB
4KB
:
0A0000H – 0A0FFFH
09F000H – 09FFFFH
:
144
143
:
4KB
4KB
:
090000H – 090FFFH
08F000H – 08FFFFH
:
8
128
127
:
4KB
4KB
:
080000H – 080FFFH
07F000H – 07FFFFH
:
7
112
111
:
4KB
4KB
:
070000H – 070FFFH
06F000H – 06FFFFH
:
6
96
95
:
4KB
4KB
:
060000H – 060FFFH
05F000H – 05FFFFH
:
5
80
79
:
4KB
4KB
:
050000H – 050FFFH
04F000H – 04FFFFH
:
4
64
63
:
4KB
4KB
:
040000H – 040FFFH
03F000H – 03FFFFH
:
3
48
4KB
030000H – 030FFFH
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2009
Revision: 1.3
4/32
ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
Table 1: F25L08PA Sector Address Table - Continued
Block Address
Sector Size
(Kbytes)
Block
2
Sector
Address range
A19 A18 A17 A16
47
:
4KB
:
02F000H – 02FFFFH
0
0
0
0
0
0
1
0
0
0
1
0
:
32
31
:
4KB
4KB
:
020000H – 020FFFH
01F000H – 01FFFFH
:
1
0
16
15
:
4KB
4KB
:
010000H – 010FFFH
00F000H – 00FFFFH
:
0
4KB
000000H – 000FFFH
STATUS REGISTER
The software status register provides status on whether the flash
memory array is available for any Read or Write operation,
whether the device is Write enabled, and the state of the memory
Write protection. During an internal Erase or Program operation,
the status register may be read only to determine the completion
of an operation in progress. Table 2 describes the function of
each bit in the software status register.
Table 2: Software Status Register
Default at
Power-up
Bit
0
Name
BUSY
WEL
Function
Read/Write
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
1 = Device is memory Write enabled
0 = Device is not memory Write enabled
0
0
R
R
1
2
3
4
5
BP0
BP1
BP2
Indicate current level of block write protection (See Table 3)
Indicate current level of block write protection (See Table 3)
Indicate current level of block write protection (See Table 3)
1
1
1
0
R/W
R/W
R/W
N/A
RESERVED Reserved for future use
Auto Address Increment Programming status
1 = AAI programming mode
6
AAI
0
0
R
0 = Page Program mode
1 = BP2,BP1,BP0 are read-only bits
0 = BP2,BP1,BP0 are read/writable
7
BPL
R/W
Note:
1. Only BP0, BP1, BP2 and BPL are writable.
2. All register bits are volatility
3. All area are protected at power-on (BP2=BP1=BP0=1)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2009
Revision: 1.3 5/32
ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
WRITE ENABLE LATCH (WEL)
BUSY
The Write-Enable-Latch bit indicates the status of the internal
memory Write Enable Latch. If this bit is set to “1”, it indicates the
device is Write enabled. If the bit is set to “0” (reset), it indicates
the device is not Write enabled and does not accept any memory
Write (Program/ Erase) commands. This bit is automatically reset
under the following conditions:
The Busy bit determines whether there is an internal Erase or
Program operation in progress. A “1” for the Busy bit indicates
the device is busy with an operation in progress. A “0” indicates
the device is ready for the next valid operation.
• Power-up
• Write Disable (WRDI) instruction completion
• Page Program instruction completion
• Auto Address Increment (AAI) Programming is completed and
reached its highest unprotected memory address
• Sector Erase instruction completion
• Block Erase instruction completion
• Chip Erase instruction completion
Auto Address Increment (AAI)
The Auto-Address-Increment-Programming-Status bit provides
status on whether the device is in AAI Programming mode or
Page Program mode. The default at power up is Page Program
mode.
• Write Status Register instructions
Table 3: F25L08PA Block Protection Table
Protection Level
Status Register Bit
Protected Memory Area
BP2
BP1
0
BP0
Block Range
Address Range
None
0
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
None
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
All Blocks
All Blocks
All Blocks
0
Block 15
F0000H – FFFFFH
E0000H – FFFFFH
C0000H – FFFFFH
80000H – FFFFFH
00000H – FFFFFH
00000H – FFFFFH
00000H – FFFFFH
1
Block 14~15
Block 12~15
Block 8~15
Block 0~15
Block 0~15
Block 0~15
1
0
0
1
1
Block Protection (BP2, BP1, BP0)
Block Protection Lock-Down (BPL)
The Block-Protection (BP2, BP1, BP0) bits define the size of the
memory area, as defined in Table 3, to be software protected
against any memory Write (Program or Erase) operations. The
Write Status Register (WRSR) instruction is used to program the
WP pin driven low (VIL), enables the Block-Protection-
Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP2, BP1, and BP0 bits. When the
WP pin is driven high (VIH), the BPL bit has no effect and its
value is “Don’t Care”. After power-up, the BPL bit is reset to 0.
BP2, BP1, BP0 bits as long as WP is high or the Block-
Protection-Look (BPL) bit is 0. Chip Erase can only be executed if
Block-Protection bits are all 0. After power-up, BP2, BP1 and BP0
are set to1.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2009
Revision: 1.3
6/32
ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
HOLD OPERATION
Hold mode when the SCK next reaches the active low state. See
Figure 1 for Hold Condition waveform.
HOLD pin is used to pause a serial sequence underway with the
SPI flash memory without resetting the clocking sequence. To
activate the HOLD mode, CE must be in active low state. The
HOLD mode begins when the SCK active low state coincides
with the falling edge of the HOLD signal. The HOLD mode ends
Once the device enters Hold mode, SO will be in high impedance
state while SI and SCK can be VIL or VIH.
If CE is driven active high during a Hold condition, it resets the
when the HOLD signal’s rising edge coincides with the SCK
active low state.
internal logic of the device. As long as HOLD signal is low, the
memory remains in the Hold condition. To resume
communication with the device, HOLD must be driven active
If the falling edge of the HOLD signal does not coincide with the
SCK active low state, then the device enters Hold mode when the
SCK next reaches the active low state.
high, and CE must be driven active low. See Figure 26 for Hold
timing.
Similarly, if the rising edge of the HOLD signal does not
coincide with the SCK active low state, then the device exits in
SCK
HOLD
Hold
Active
Active
Active
Hold
Figure 1: HOLD Condition Waveform
WRITE PROTECTION
Table 4: Conditions to Execute Write-Status-Register
(WRSR) Instruction
F25L08PA provides software Write Protection.
The Write-Protect pin ( WP ) enables or disables the lock-down
function of the status register. The Block-Protection bits (BP2,
BP1, BP0, and BPL) in the status register provide Write
protection to the memory array and the status register. See Table
3 for Block-Protection description.
BPL
1
Execute WRSR Instruction
Not Allowed
WP
L
L
0
Allowed
H
X
Allowed
Write Protect Pin ( WP )
The Write-Protect ( WP ) pin enables the lock-down function of
the BPL bit (bit 7) in the status register. When WP is driven low,
the execution of the Write Status Register (WRSR) instruction is
determined by the value of the BPL bit (see Table 4). When WP
is high, the lock-down function of the BPL bit is disabled.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2009
Revision: 1.3 7/32
ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
INSTRUCTIONS
Instructions are used to Read, Write (Erase and Program), and
configure the F25L08PA. The instruction bus cycles are 8 bits
each for commands (Op Code), data, and addresses. Prior to
executing any Page Program, Auto Address Increment (AAI)
Programming, Write Status Register, Sector Erase, Block Erase,
or Chip Erase instructions, the Write Enable (WREN) instruction
must be executed first. The complete list of the instructions is
provided in Table 5. All instructions are synchronized off a high to
low before an instruction is entered and must be driven high after
the last bit of the instruction has been shifted in (except for Read,
Read ID, Read Status Register, Read Electronic Signature
instructions). Any low to high transition on CE , before receiving
the last bit of an instruction bus cycle, will terminate the
instruction in progress and return the device to the standby
mode.
low transition of CE . Inputs will be accepted on the rising edge
of SCK starting with the most significant bit. CE must be driven
Instruction commands (Op Code), addresses, and data are all
input from the most significant bit (MSB) first.
Table 5: Device Operation Instructions
Bus Cycle 1~3
4
SOUT SIN SOUT SIN SOUT SIN
Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z
Max.
Freq
Operation
1
2
3
5
6
N
SIN
SOUT
SIN
SOUT
SIN
X
X
SOUT
SIN SOUT
Read
33 MHz 03H
X
X
DOUT0
X
DOUT1
DOUT0
X
X
cont.
cont.
Fast Read
0BH Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z
3BH A23-A16 A15-A8 A7-A0
Fast Read Dual
X
DOUT0~1
cont.
Output12,13
Sector Erase4 (4K Byte)
Block Erase4, (64K Byte)
20H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z
D8H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z
60H /
-
-
-
-
-
-
-
-
-
-
-
-
Chip Erase
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
C7H
Up to
Page Program (PP)
02H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z DIN0
ADH Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z DIN0
Hi-Z
DIN1
Hi-Z
256 Hi-Z
bytes
Auto Address Increment
word programming5 (AAI)
Read Status Register
(RDSR) 6
Hi-Z
DIN1
Hi-Z
-
-
-
-
-
-
05H Hi-Z
50H Hi-Z
X
-
DOUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Enable Write Status
Register (EWSR) 7
Write Status Register
(WRSR) 7
50MHz
01H Hi-Z
06H Hi-Z
04H Hi-Z
DIN
Hi-Z
-
-
-
-
-
-
-.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Write Enable (WREN) 10
Write Disable (WRDI)/
Exit secured OTP mode
Enter secured OTP mode
(ENSO)
-
-
-
-
-
B1H Hi-Z
ABH Hi-Z
ABH Hi-Z
ABH Hi-Z
9FH Hi-Z
90H Hi-Z
-
X
-
-
-
-
-.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
100MHz
Read Electronic
13H
33H
73H
8CH
-
-
Signature (RES) 8
RES in secured OTP
mode & not lock down
RES in secured OTP
mode & lock down
Jedec Read ID
X
-
-
-
-.
-.
X
-
-
X
-
X
X
20H
14H
(JEDEC-ID) 9
00H Hi-Z
01H Hi-Z
X
X
8CH
13H
X
X
13H
8CH
-
-
-
-
Read ID (RDID) 11
00H
Hi-Z 00H Hi-Z
Enable SO to output
70H Hi-Z
80H Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
RY/
(EBSY)
Disable SO to output
Status during AAI
RY/
Status during AAI
(DBSY)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2009
Revision: 1.3 8/32
ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
Note:
1. Operation: SIN = Serial In, SOUT = Serial Out, Bus Cycle 1 = Op Code
2. X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary); cont. = continuous
3. One bus cycle is eight clock periods.
4. Sector Earse addresses: use AMS -A12, remaining addresses can be VIL or VIH
Block Earse addresses: use AMS -A16, remaining addresses can be VIL or VIH
5. To continue programming to the next sequential address location, enter the 8-bit command, followed by the data to be
programmed.
6. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE .
7. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in
conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR
instruction to make both instructions effective.
8. The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE .
9. The Jedec-Read-ID is output first byte 8CH as manufacture ID; second byte 20H as top memory type; third byte 14H as
memory capacity.
10. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each
other. The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both
instructions effective. Both EWSR and WREN can enable WRSR, user just need to execute one of it. A successful WRSR
can reset WREN.
11. The Manufacture ID and Device ID output will repeat continuously until CE terminates the instruction.
12. Dual commands use bidirectional IO pins. DOUT and cont. are serial data out; others are serial data in.
13. Dual output data:
IO
IO
0
= (D
6
, D
4
, D
2
, D
0
), (D
6
, D
4
, D
2
, D
0
)
)
1
= (D
7
, D5
, D3
, D1
), (D
7
, D5
, D3
, D1
DOUT0
DOUT1
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2009
Revision: 1.3 9/32
ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
Read (33MHz)
The Read instruction supports up to 33 MHz, it outputs the data
starting from the specified address location. The data output
stream is continuous through all addresses until terminated by a
the data from address location FFFFFH had been read, the next
output will be from address location 000000H.
The Read instruction is initiated by executing an 8-bit command,
low to high transition on CE . The internal address pointer will
automatically increment until the highest memory address is
reached. Once the highest memory address is reached, the
address pointer will automatically increment to the beginning
(wrap-around) of the address space, i.e. for 8Mbit density, once
03H, followed by address bits [A23 -A0]. CE must remain active
low for the duration of the Read cycle. See Figure 2 for the Read
sequence.
Figure 2: Read Sequence
Fast Read (50 MHz; 100 MHz)
The Fast Read instruction supporting up to 100 MHz is initiated
by executing an 8-bit command, 0BH, followed by address bits
all addresses until terminated by a low to high transition on CE .
The internal address pointer will automatically increment until the
highest memory address is reached. Once the highest memory
address is reached, the address pointer will automatically
increment to the beginning (wrap-around) of the address space,
i.e. for 8Mbit density, once the data from address location
FFFFFH has been read, the next output will be from address
location 000000H.
[A23 -A0] and a dummy byte. CE must remain active low for the
duration of the Fast Read cycle. See Figure 3 for the Fast Read
sequence.
Following a dummy byte (8 clocks input dummy cycle), the Fast
Read instruction outputs the data starting from the specified
address location. The data output stream is continuous through
CE
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47 48
MODE3
MODE0
55 56
63 64
71 72
80
SCK
SI
0B
ADD.
MSB
ADD.
ADD.
X
MSB
N
N+1
DOUT
N+2
DOUT
N+3
DOU T
N+4
DOU T
HIGH IMPENANCE
SO
DOU T
MSB
Note : X = Dummy Byte : 8 Clocks Input Dummy (VIL or VIH)
Figure 3: Fast Read Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2009
Revision: 1.3 10/32
ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
Fast Read Dual Output (50 MHz; 100 MHz)
The Fast Read Dual Output (3BH) instruction is similar to the
standard Fast Read (0BH) instruction except the data is output
on SI and SO pins. This allows data to be transferred from the
device at twice the rate of standard SPI devices. This instruction
is for quickly downloading code from Flash to RAM upon
power-up or for applications that cache code- segments to RAM
for execution.
The Fast Read Dual Output instruction is initiated by executing
an 8-bit command, 3BH, followed by address bits [A23 -A0] and a
dummy byte. CE must remain active low for the duration of the
Fast Read Dual Output cycle. See Figure 4 for the Fast Read
Dual Output sequence.
Figure 4: Fast Read Dual Output Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2009
Revision: 1.3
11/32
ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
Page Program (PP)
The Page Program instruction allows many bytes to be
programmed in the memory. The bytes must be in the erased
state (FFH) when initiating a Program operation. A Page
Program instruction applied to a protected memory area will be
ignored.
latched data are discarded and the last 256 bytes Data are
guaranteed to be programmed correctly within the same page. If
less than 256 bytes Data are sent to device, they are correctly
programmed at the requested addresses without having any
effects on the other bytes of the same page.
Prior to any Write operation, the Write Enable (WREN) instruction
CE must be driven high before the instruction is executed. The
user may poll the Busy bit in the software status register or wait
TPP for the completion of the internal self-timed Page Program
operation. While the Page Program cycle is in progress, the Read
Status Register instruction may still be accessed for checking the
status of the Busy bit. It is recommended to wait for a duration of
TBP before reading the status register to check the BUSY bit. The
BUSY bit is a 1 during the Page Program cycle and becomes a 0
when the cycle is finished and the device is ready to accept other
instructions again. After the Page Program cycle has finished, the
Write-Enable-Latch (WEL) bit in the Status Register is cleared to
0. See Figure 7 for the Page Program sequence.
must be executed. CE must remain active low for the duration
of the Page Program instruction. The Page Program instruction is
initiated by executing an 8-bit command, 02H, followed by
address bits [A23-A0]. Following the address, at least one byte
Data is input (the maximum of input data can be up to 256 bytes).
If the 8 least significant address bits [A7-A0] are not all zero, all
transmitted data that goes beyond the end of the current page
are programmed from the start address of the same page (from
the address whose 8 least significant bits [A7-A0] are all zero).
If more than 256 bytes Data are sent to the device, previously
Figure 7: Page Program Sequence
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Revision: 1.3
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ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
Auto Address Increment (AAI) WORD Program
The AAI program instruction allows multiple bytes of data to be
programmed without re-issuing the next sequential address
location. This feature decreases total programming time when
the multiple bytes or entire memory array is to be programmed.
An AAI program instruction pointing to a protected memory area
will be ignored. The selected address range must be in the
erased state (FFH) when initiating an AAI program instruction.
While within AAI WORD programming sequence, the only valid
instructions are AAI WORD program operation, RDSR, WRDI.
Users have three options to determine the completion of each
AAI WORD program cycle: hardware detection by reading the
SO; software detection by polling the BUSY in the software status
register or wait TBP. Refer to End of Write Detection section for
details.
7) to LSB (bit 0). The first byte of data (D0) will be programmed
into the initial address [A23 -A1] with A0 =0; the second byte of
data (D1) will be programmed into the initial address [A23 -A1] with
A0 =1. CE must be driven high before the AAI WORD program
instruction is executed. The user must check the BUSY status
before entering the next valid command. Once the device
indicates it is no longer busy, data for next two sequential
addresses may be programmed and so on. When the last desired
byte had been entered, check the busy status using the hardware
method or the RDSR instruction and execute the WRDI
instruction, to terminate AAI. User must check BUSY status after
WRDI to determine if the device is ready for any command.
Please refer to Figure 10 and Figure 11.
There is no wrap mode during AAI programming; once the
highest unprotected memory address is reached, the device will
exit AAI operation and reset the Write-Enable-Latch bit (WEL = 0)
and the AAI bit (AAI=0).
Prior to any write operation, the Write Enable (WREN) instruction
must be executed. The AAI WORD program instruction is
initiated by executing an 8-bit command, ADH, followed by
address bits [A23 -A0]. Following the addresses, two bytes of data
is input sequentially. The data is input sequentially from MSB (bit
End of Write Detection
There are three methods to determine completion of a program
cycle during AAI WORD programming: hardware detection by
reading the SO, software detection by polling the BUSY bit in the
Software Status Register or wait TBP. The Hardware End of Write
Detection method is described in the section below.
Hardware End of Write Detection
The Hardware End of Write Detection method eliminates the
overhead of polling the BUSY bit in the Software Status Register
during an AAI Word program operation. The 8-bit command, 70H,
configures the SO pin to indicate Flash Busy status during AAI
WORD programming (refer to Figure 8). The 8-bit command, 70H,
must be executed prior to executing an AAI WORD program
instruction. Once an internal programming operation begins,
status on the SO pin. A “0”
Indicates the device is busy; a “1” Indicates the device is ready
for the next instruction. De-asserting CE will return the SO pin
to tri-state. The 8-bit command, 80H,disables the SO pin to
output busy status during AAI WORD program operation and
return SO pin to output Software Status Register data during AAI
WORD programming (refer to Figure 9).
asserting CE will immediately drive the status of the internal flash
Figure 8: Enable SO as Hardware RY/BY
during AAI Programming
Figure 9: Disable SO as Hardware RY/BY
during AAI Programming
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ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
Figure 10: AAI Word Program Sequence with Hardware End of Write Detection
Figure 11: AAI Word Program Sequence with Software End of Write Detection
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ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
64K Byte Block Erase
The 64K-byte Block Erase instruction clears all bits in the
selected block to FFH. A Block Erase instruction applied to a
protected memory area will be ignored. Prior to any Write
operation, the Write Enable (WREN) instruction must be
-A0]. Address bits [AMS -A16] (AMS = Most Significant address) are
used to determine the block address (BAX), remaining address
bits can be VIL or VIH. CE must be driven high before the
instruction is executed. The user may poll the Busy bit in the
Software Status Register or wait TBE for the completion of the
internal self-timed Block Erase cycle. See Figure 13 for the Block
Erase sequence.
executed. CE must remain active low for the duration of the any
command sequence. The Block Erase instruction is initiated by
executing an 8-bit command, D8H, followed by address bits [A23
Figure 13: 64K-byte Block Erase Sequence
4K Byte Sector Erase
The Sector Erase instruction clears all bits in the selected sector
to FFH. A Sector Erase instruction applied to a protected memory
area will be ignored. Prior to any Write operation, the Write
[AMS -A12] (AMS = Most Significant address) are used to determine
the sector address (SAX), remaining address bits can be VIL or
VIH. CE must be driven high before the instruction is executed.
The user may poll the Busy bit in the Software Status Register or
wait TSE for the completion of the internal self-timed Sector Erase
cycle. See Figure 14 for the Sector Erase sequence.
Enable (WREN) instruction must be executed. CE must remain
active low for the duration of the any command sequence. The
Sector Erase instruction is initiated by executing an 8-bit
command, 20H, followed by address bits [A23 -A0]. Address bits
CE
15 16
31
23 24
0 1 2 3 4 5 6 7 8
MODE3
MODE0
SCK
SI
20
ADD.
MSB
ADD.
ADD.
MSB
HIGH IMPENANCE
SO
Figure 14: 32K-byte Sector Erase Sequence
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ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
Chip Erase
The Chip Erase instruction clears all bits in the device to FFH. A
Chip Erase instruction will be ignored if any of the memory area is
protected. Prior to any Write operation, the Write Enable (WREN)
Erase instruction is initiated by executing an 8-bit command, 60H
or C7H. CE must be driven high before the instruction is
executed. The user may poll the Busy bit in the Software Status
Register or wait TCE for the completion of the internal self-timed
Chip Erase cycle. See Figure 15 for the Chip Erase sequence.
instruction must be executed. CE must remain active low for
the duration of the Chip-Erase instruction sequence. The Chip
CE
0 1 2 3 4 5 6 7
MODE3
SCK
SI
MODE0
60 or C7
MSB
HIGH IMPENANCE
SO
Figure 15: Chip Erase Sequence
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows reading of
the status register. The status register may be read at any time
even during a Write (Program/Erase) operation.
When a Write operation is in progress, the Busy bit may be
checked before sending any new commands to assure that the
new commands are properly received by the device.
CE must be driven low before the RDSR instruction is entered
and remain low until the status data is read. Read Status
Register is continuous with ongoing clock cycles until it is
terminated by a low to high transition of the CE . See Figure 16
for the RDSR instruction sequence.
Figure 16: Read-Status-Register (RDSR) Sequence
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ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
Write Enable (WREN)
The Write Enable (WREN) instruction sets the Write-Enable-
Latch bit in the Software Status Register to 1 allowing Write
operations to occur.
(Program/Erase) operation. CE must be driven high before the
WREN instruction is executed.
The WREN instruction must be executed prior to any Write
CE
0 1 2 3 4 5 6 7
MODE3
MODE0
SCK
SI
06
MSB
HIGH IMPENANCE
SO
Figure 17: Write Enable (WREN) Sequence
Write Disable (WRDI)
The Write Disable (WRDI) instruction resets the Write-Enable-
Latch bit to 0 disabling any new Write operations from occurring
or exits from OTP mode to normal mode.
CE must be driven high before the WRDI instruction is
executed.
CE
0 1 2 3 4 5 6 7
MODE3
SCK
SI
MODE0
04
MSB
HIGH IMPENANCE
SO
Figure 18: Write Disable (WRDI) Sequence
Enable Write Status Register (EWSR)
The Enable Write Status Register (EWSR) instruction arms the
Write Status Register (WRSR) instruction and opens the status
register for alteration. The Enable Write Status Register
instruction does not have any effect and will be wasted, if it is not
followed immediately by the Write Status Register (WRSR)
instruction. CE must be driven low before the EWSR instruction
is entered and must be driven high before the EWSR instruction
is executed.
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ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
Write Status Register (WRSR)
The Write Status Register instruction writes new values to the
When WP is high, the lock-down function of the BPL bit is
disabled and the BPL, BP0, BP1,and BP2 bits in the status
BP2, BP1, BP0, and BPL bits of the status register. CE must be
driven low before the command sequence of the WRSR
instruction is entered and driven high before the WRSR
instruction is executed. See Figure 19 for EWSR or WREN and
WRSR instruction sequences.
register can all be changed. As long as BPL bit is set to 0 or WP
pin is driven high (VIH) prior to the low-to-high transition of the
CE pin at the end of the WRSR instruction, the bits in the status
register can all be altered by the WRSR instruction. In this case,
a single WRSR instruction can set the BPL bit to “1” to lock down
the status register as well as altering the BP0; BP1 and BP2 bits
Executing the Write Status Register instruction will be ignored
when WP is low and BPL bit is set to “1”. When the WP is
low, the BPL bit can only be set from “0” to “1” to lock down the
status register, but cannot be reset from “1” to “0”.
at the same time. See Table 4 for a summary description of WP
and BPL functions.
CE
0 1 2 3 4 5 6 7 8 9 1011 12 13 1415
MODE3
0 1 2 3 4 5 6 7
SCK MODE0
STATUS
REGISTER IN
50 or 06
7 6 5 4 3 2 1
0
SI
01
MSB
MSB
HIGH IMPENANCE
SO
Figure 19: Enable Write Status Register (EWSR) or Write Enable (WREN) and Write Status Register (WRSR)
Enter Secured OTP Mode (ENSO)
The ENSO (B1H) instruction is for entering the additional 4K
bytes secured OTP mode. The additional 4K bytes secured OTP
sector is independent from main array, which may use to store
unique serial number for system identifier. User must unprotect
whole array (BP0=BP1=BP2=0), prior to any Program operation
in OTP sector. After entering the secured OTP mode, only the
secured OTP sector can be accessed and user can only follow
the Read or Program procedure with OTP address range
(address bits [A23 –A12] must be “0”). The secured OTP data
cannot be updated again once it is lock down or has been
programmed. In secured OTP mode, WRSR command will
ignore the input data and lock down the secured OTP sector
(OTP_lock bit =1). To exit secured OTP mode, user must
execute WRDI command. RES can be used to verify the secured
OTP status as shown in Table 6.
Figure 20: Enter OTP Mode (ENSO) Sequence
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ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
OTP Sector Address
Size
Address Range
4K bytes
000000H ~ 000FFFH
Note: The OTP sector is an independent Sector.
Read-Electronic-Signature (RES)
The RES instruction can be used to read the 8-bit Electronic
Signature of the device on the SO pin. The RES instruction can
provide access to the Electronic Signature of the device (except
while an Erase, Program or WRSR cycle is in progress), Any
RES instruction executed while an Erase, Program or WRSR
cycle is in progress is no decoded, and has no effect on the cycle
in progress. In OTP mode, user also can execute RES to confirm
the status.
Figure 21: Read-Electronic-Signature (RES) Instruction
Table 6: Electronic Signature Data
Command
Mode
Electronic Signature Data
Normal
13H
In secured OTP mode &
33H
73H
RES
non lock down (OTP_lock =0)
In secured OTP mode &
lock down (OTP_lock =1)
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ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
JEDEC Read-ID
The JEDEC Read-ID instruction identifies the device as
F25L08PA and the manufacturer as ESMT. The device
information can be read from executing the 8-bit command, 9FH.
Following the JEDEC Read-ID instruction, the 8-bit
manufacturer’s ID, 8CH, is output from the device. After that, a
16-bit device ID is shifted out on the SO pin. Byte1, 8CH,
identifies the manufacturer as ESMT. Byte2, 20H, identifies the
memory type as SPI Flash. Byte3, 14H, identifies the device as
F25L08PA. The instruction sequence is shown in Figure 22.
The JEDEC Read ID instruction is terminated by a low to high
transition on CE at any time during data output. If no other
command is issued after executing the JEDEC Read-ID
instruction, issue a 00H (NOP) command before going into
Standby Mode ( CE =VIH).
Figure 22: JEDEC Read-ID Sequence
Table 7: JEDEC Read-ID Data
Device ID
Memory Capacity
Manufacturer’s ID
Memory Type
(Byte 1)
(Byte 2)
(Byte 3)
8CH
20H
14H
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ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
Read-ID (RDID)
The Read-ID instruction (RDID) identifies the devices as
F25L08PA and manufacturer as ESMT. This command is
backward compatible to all ESMT SPI devices and should be
used as default device identification when multiple versions of
ESMT SPI devices are used in one design. The device
information can be read from executing an 8-bit command, 90H,
followed by address bits [A23 -A0]. Following the Read-ID
instruction, the manufacturer’s ID is located in address 00000H
and the device ID is located in address 00001H.
Once the device is in Read-ID mode, the manufacturer’s and
device ID output data toggles between address 00000H and
00001H until terminated by a low to high transition on CE .
Figure 23: Read-ID Sequence
Table 8: Product ID Data
Address
Byte1
Byte2
8CH
13H
00000H
Device ID
Manufacturer’s ID
ESMT F25L08PA
13H
8CH
00001H
Device ID
Manufacturer’s ID
ESMT F25L08PA
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ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
ELECTRICAL SPECIFICATIONS
Absolute Maximum Stress Ratings
(Applied conditions are greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the
operational sections of this datasheet is not implied. Exposure to absolute maximum stress rating conditions may affect device
reliability.)
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
( Note 1: Output shorted for no more than one second. No more than one output shorted at a time. )
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . . . . . CL = 15 pF for ≧75MHz
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .CL = 30 pF for ≦50MHz
See Figures 28 and 29
OPERATING RANGE
Parameter
Symbol
VDD (for FCLK <= 50MHz)
VDD (for FCLK = 100MHz)
TA
Value
Unit
V
2.7 ~ 3.6
3.0 ~3.6
-40 ~ 85
Operating Supply Voltage
Ambient Operating Temperature
℃
Table 9: DC OPERATING CHARACTERISTICS
Limits
Max
15
Symbol
IDDR1
Parameter
Test Condition
Min
Unit
Read Current
Standard
Dual
mA
CE =0.1 VDD/0.9 VDD, SO=open
CE =0.1 VDD/0.9 VDD, SO=open
@33 MHz
18
20
23
Read Current
@ 50MHz
Standard
Dual
IDDR2
mA
Read Current
@ 100MHz
Program and Erase Current
Standard
Dual
25
28
IDDR3
IDDW
mA
mA
CE =0.1 VDD/0.9 VDD, SO=open
CE =VDD
35
ISB
ILI
ILO
VIL
VIH
VOL
VOH
Standby Current
30
1
1
µA
µA
µA
V
V
V
CE =VDD, VIN =VDD or VSS
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
VDD=VDD Max
IOL=100 µA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
0.8
0.7 x VDD
VDD-0.2
0.2
V
Table 10: LATCH UP CHARACTERISTIC
Symbol
Parameter
Minimum
Unit
Test Method
1
ILTH
Latch Up
100 + IDD
mA
JEDEC Standard 78
Note 1: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
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ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
Table 11: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
Unit
µs
1
TPU-READ
VDD Min to Read Operation
VDD Min to Write Operation
10
10
1
TPU-WRITE
µs
Table 12: CAPACITANCE (TA = 25°C, f=1 MHz, other pins open)
Parameter
Description
Test Condition
VOUT = 0V
Maximum
12 pF
1
COUT
Output Pin Capacitance
Input Capacitance
1
CIN
VIN = 0V
6 pF
Note 1: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Table 13: AC OPERATING CHARACTERISTICS
Normal 33MHz Fast 50 MHz Fast 100 MHz
Symbol
Parameter
Unit
Min
Max
Min
Max Min
Max
FCLK
TSCKH
TSCKL
Serial Clock Frequency
Serial Clock High Time
Serial Clock Low Time
33
50
100
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13
13
5
9
9
5
5
1
TCES
5
5
CE Active Setup Time
CE Active Hold Time
CE Not Active Setup Time
CE Not Active Hold Time
CE High Time
1
TCEH
5
5
5
1
TCHS
5
5
5
1
TCHH
5
5
5
TCPH
TCHZ
TCLZ
TDS
100
100
100
9
9
9
CE High to High-Z Output
SCK Low to Low-Z Output
Data In Setup Time
0
3
3
5
5
5
5
0
3
3
5
5
5
5
0
3
TDH
THLS
THHS
THLH
THHH
THZ
Data In Hold Time
3
5
HOLD Low Setup Time
HOLD High Setup Time
HOLD Low Hold Time
5
5
5
HOLD High Hold Time
9
9
9
9
9
HOLD Low to High-Z Output
HOLD High to Low-Z Output
Output Hold from SCK Change
Output Valid from SCK
TLZ
9
TOH
TV
0
0
0
12
8
7
Note 1: Relative to SCK.
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ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
ERASE AND PROGRAMMING PERFORMANCE
Limit
Unit
Parameter
Symbol
Typ2
Max3
Sector Erase Time
TSE
TBE
TCE
TBP
TPP
90
200
2
ms
s
Block Erase Time
1
10
Chip Erase Time
30
30
5
s
Byte Programming Time
Page Programming Time
Chip Programming Time
Erase/Program Cycles1
Data Retention
7
us
1.5
ms
s
25
100
-
100,000
20
Cycles
Years
-
Notes:
1. Not 100% Tested, Excludes external system level over head.
2. Typical values measured at 25°C, 3V.
3. Maximum values measured at 85°C, VDD(min).
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ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
Figure 24: Serial Input Timing Diagram
Figure 25: Serial Output Timing Diagram
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ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
Figure 26: HOLD Timing Diagram
VCC
VCC (max)
Program, Erase and Write command is ignored
CE must track VCC
VCC (min)
Read command
is allowed
T
VSL
Device is fully
accessible
Reset
State
VWI
T
PUW
Time
Figure 27: Power-Up Timing Diagram
Table 14: Power-Up Timing and VWI Threshold
Unit
Parameter
Symbol
Min.
Max.
TVSL
TPUW
VWI
200
us
ms
V
VCC(min) to CE low
Time Delay before Write instruction
10
2
Write Inhibit Threshold Voltage
1
Note: These parameters are characterized only.
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ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
Input timing reference level
Output timing reference level
0.8VCC
0.2VCC
0.7VCC
0.3VCC
AC
Measurement
Level
0.5VCC
Note : Input pulse rise and fall time are <5ns
Figure 28: AC Input/Output Reference Waveforms
Figure 29: A Teat Load Example
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ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
PACKAGING DIMENSIONS
8-LEAD
SOIC ( 150 mil )
8
5
GAUGE PLANE
L
DETAIL "X"
1
4
e
b
D
L1
"X"
SEATING PLANE
Dimension in mm
Dimension in inch
Dimension in mm
Dimension in inch
Symbol
Symbol
Min
1.35
0.10
1.25
0.33
0.19
5.80
Norm
1.60
Max
1.75
0.25
1.55
0.51
0.25
6.20
Min
Norm
0.063
0.006
0.057
0.016
Max
Min
Norm
4.90
Max
Min
Norm
0.193
Max
A
A1
A2
b
0.053
0.004
0.049
0.013
0.069
0.010
0.061
0.020
0.010
0.244
D
E
L
4.80
3.80
0.40
5.00
4.00
0.86
0.189
0.150
0.016
0.197
0.157
0.034
0.15
3.90
0.154
1.45
0.66
0.026
0.406
0.203
6.00
e
1.27 BSC
1.05
0.050 BSC
0.041
c
0.0075 0.008
0.228 0.236
1.00
1.10
0.039
0.043
L1
θ
0°
8°
0°
8°
H
---
---
Controlling dimension : millimenter
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2009
Revision: 1.3 28/32
ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
PACKING DIMENSIONS
8-LEAD SOIC 200 mil ( official name – 209 mil )
θ
5
8
4
1
b
e
D
L
L1
SEATING PLANE
DETAIL "X"
Dimension in mm
Dimension in inch
Dimension in mm
Dimension in inch
Symbol
Symbol
Min
---
Norm
---
Max
2.16
0.25
1.91
0.51
0.25
5.33
Min
Norm
---
Max
Min
Norm
7.90
Max
Min
Norm
0.311
Max
A
A1
A2
b
---
0.085
0.010
0.075
0.020
0.010
0.210
E
E1
L
7.70
5.18
0.50
8.10
5.38
0.80
0.303
0.204
0.020
0.319
0.212
0.032
0.05
1.70
0.36
0.19
5.13
0.15
1.80
0.41
0.20
5.23
0.002
0.067
0.014
0.007
0.202
0.006
0.071
0.016
0.008
0.206
5.28
0.208
0.65
0.026
e
1.27 BSC
1.37
0.050 BSC
0.054
c
1.27
1.47
0.050
0.058
L1
θ
0°
8°
0°
8°
D
---
---
Controlling dimension : millimenter
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2009
Revision: 1.3 29/32
ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
PACKING
DIMENSIONS
8-LEAD P-DIP ( 300 mil )
D
8
5
0
1
4
S e a tin g P la n e
1
b
b
e
Dimension in mm
Dimension in inch
Symbol
Min
Norm
Max
Min
Norm
Max
A
A1
A2
D
5.00
0.21
0.38
3.18
9.02
0.015
0.125
0.355
3.30
9.27
3.43
0.130
0.365
0.135
0.400
10.16
E
7.62 BSC.
6.35
0.300 BSC.
0.250
E1
L
6.22
9.02
6.48
0.245
0.115
0.255
0.150
9.27
10.16
0.130
e
2.54 TYP.
9.02
0.100 TYP.
0.355
eB
b
8.51
9.53
15O
0.335
0O
0.375
15O
0.46 TYP.
1.52 TYP.
7O
0.018 TYP.
0.060 TYP.
7O
b1
θO
0O
Controlling dimension : Inch.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2009
Revision: 1.3
30/32
ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
Revision History
Revision
Date
Description
1.0
2008.11.19
Original
1.Modify headline
2.Delete the rating of Temperature Under Bias
1.1
2009.05.11
1.2
1.3
2009.06.04
2009.07.20
Add 8 lead SOIC (150mil) package
Modify the description of OTP mode
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2009
Revision: 1.3 31/32
ESMT
F25L08PA
Operation Temperature Condition -40°C~85°C
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or
by any means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at
the time of publication. ESMT assumes no responsibility for any error in
this document, and reserves the right to change the products or
specification in this document without notice.
The information contained herein is presented only as a guide or
examples for the application of our products. No responsibility is
assumed by ESMT for any infringement of patents, copyrights, or other
intellectual property rights of third parties which may result from its use.
No license, either express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of ESMT or
others.
Any semiconductor devices may have inherently a certain rate of failure.
To minimize risks associated with customer's application, adequate
design and operating safeguards against injury, damage, or loss from
such failure, should be provided by the customer when making
application designs.
ESMT's products are not authorized for use in critical applications such
as, but not limited to, life support devices or system, where failure or
abnormal operation may directly affect human lives or cause physical
injury or property damage. If products described here are to be used for
such kinds of application, purchaser must do its own quality assurance
testing appropriate to such applications.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jul. 2009
Revision: 1.3 32/32
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