F25L08QA-100HG2S [ESMT]
Flash, 8MX1, PDSO8, 6 X 5 MM, 1.27 MM PITCH, ROHS COMPLIANT, WSON-8;
| 型号： | F25L08QA-100HG2S |
| 厂家： | 
ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. |
| 描述： | Flash, 8MX1, PDSO8, 6 X 5 MM, 1.27 MM PITCH, ROHS COMPLIANT, WSON-8 时钟 光电二极管 内存集成电路 |
| 文件： | 总43页 (文件大小：355K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ESMT
F25L08QA (2S)
Flash
8 Mbit Serial Flash Memory
with Dual and Quad
FEATURES
Single supply voltage 2.7~3.6V
Standard, Dual and Quad SPI
Erase
- Chip Erase time 7 sec (typical)
Speed
- 64K bytes Block Erase time 0.75 sec (typical)
- 32K bytes Block Erase time 500 ms (typical)
- 4K bytes Sector Erase time 90 ms (typical)
- Read max frequency: 33MHz
- Fast Read max frequency: 50MHz / 86MHz / 100MHz
- Fast Read Dual/Quad max frequency: 50MHz / 86MHz /
100MHz
(100MHz / 172MHz / 200MHz equivalent Dual SPI;
200MHz / 344MHz / 400MHz equivalent Quad SPI)
Page Programming
- 256 byte per programmable page
Lockable 512 bytes OTP security sector
SPI Serial Interface
Low power consumption
- SPI Compatible: Mode 0 and Mode 3
- Active current: 25 mA (max.)
- Standby current: 25μ A (max.)
End of program or erase detection
Write Protect ( WP )
- Deep Power Down current: 10μ A (max.)
Reliability
Hold Pin (HOLD )
- 100,000 typical program/erase cycles
- 20 years Data Retention
All Pb-free products are RoHS-Compliant
Program
- Page programming time: 1.5 ms (typical)
ORDERING INFORMATION
Product ID
Speed
Package
Comments
F25L08QA –50PG2S
F25L08QA –86PG2S
F25L08QA –100PG2S
F25L08QA –50PAG2S
F25L08QA –86PAG2S
F25L08QA –100PAG2S
F25L08QA –50HG2S
F25L08QA –86HG2S
F25L08QA –100HG2S
50MHz
86MHz
100MHz
50MHz
86MHz
100MHz
50MHz
86MHz
100MHz
8-lead
SOIC
150 mil
200 mil
Pb-free
8-lead
SOIC
Pb-free
Pb-free
8-contact
WSON
6x5 mm
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2 1/43
ESMT
F25L08QA (2S)
GENERAL DESCRIPTION
The F25L08QA is a 8Megabit, 3V only CMOS Serial Flash
memory device. The device supports the standard Serial
Peripheral Interface (SPI), and a Dual/Quad SPI. ESMT’s
memory devices reliably store memory data even after 100,000
programming and erase cycles.
is divided into 256 uniform sectors with 4K byte each; 32 uniform
blocks with 32K byte each; 16 uniform blocks with 64K byte each.
Sectors can be erased individually without affecting the data in
other sectors. Blocks can be erased individually without affecting
the data in other blocks. Whole chip erase capabilities provide
the flexibility to revise the data in the device. The device has
Sector, Block or Chip Erase but no page erase.
The memory array can be organized into 4,096 programmable
pages of 256 byte each. 1 to 256 byte can be programmed at a
time with the Page Program instruction.
The sector protect/unprotect feature disables both program and
erase operations in any combination of the sectors of the
memory.
The device features sector erase architecture. The memory array
FUNCTIONAL BLOCK DIAGRAM
Page Address
Latch / Counter
Memory
Array
High Voltage
Generator
Page Buffer
Status
Register
Y-Decoder
Byte Address
Latch / Counter
Command and Conrol Logic
Serial Interface
CE
SCK
SO
(SIO
WP
(SIO
HOLD
(SIO3)
SI
(SIO0)
1
)
2
)
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2 2/43
ESMT
F25L08QA (2S)
PIN CONFIGURATIONS
8-Lead SOIC
(SOIC 8L, 150mil Body, 1.27mm Pin Pitch)
(SOIC 8L, 208mil Body, 1.27mm Pin Pitch)
CE
V
DD
8
7
1
SO / SIO
1
HOLD / SIO
SCK
3
2
6
5
3
4
WP / SIO
2
VSS
SI / SIO0
8- Contact WSON
(WSON 8C, 6mmX5mm Body, 1.27mm Contact Pitch)
1
VDD
CE
8
HOLD
2
7
SO
3
6
SCK
SI
WP
4
VSS
5
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2 3/43
ESMT
F25L08QA (2S)
PIN DESCRIPTION
Symbol
Pin Name
Functions
SCK
Serial Clock
To provide the timing for serial input and output operations
To transfer commands, addresses or data serially into the device. Data is
latched on the rising edge of SCK (for Standard read mode). / Bidirectional IO
pin to transfer commands, addresses or data serially into the device on the
rising edge of SCK and read data or status from the device on the falling edge
of SCK(for Dual/Quad mode).
Serial Data Input /
Serial Data Input Output 0
SI / SIO0
To transfer data serially out of the device. Data is shifted out on the falling edge
of SCK (for Standard read mode). / Bidirectional IO pin to transfer commands,
addresses or data serially into the device on the rising edge of SCK and read
data or status from the device on the falling edge of SCK (for Dual/Quad
mode).
Serial Data Output /
Serial Data Input Output 1
SO / SIO1
Chip Enable
CE
To activate the device when CE is low.
The Write Protect ( WP ) pin is used to enable/disable BPL bit in the status
register. / Bidirectional IO pin to transfer commands, addresses or data serially
into the device on the rising edge of SCK and read data or status from the
device on the falling edge of SCK (for Quad mode).
Write Protect /
Serial Data Input Output 2
WP / SIO2
To temporality stop serial communication with SPI flash memory without
resetting the device. / Bidirectional IO pin to transfer commands, addresses or
data serially into the device on the rising edge of SCK and read data or status
from the device on the falling edge of SCK (for Quad mode).
Hold /
HOLD / SIO3
Serial Data Input Output 3
VDD
VSS
Power Supply
Ground
To provide power.
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2
4/43
ESMT
F25L08QA (2S)
SECTOR STRUCTURE
Table 1: Sector Address Table
Block Address
64KB
Block
32KB
Block
Sector Size
(Kbytes)
Sector
Address range
A19
1
A18
A17
A16
1
255
:
4KB
:
0FF000H – 0FFFFFH
31
30
29
28
27
26
25
24
23
22
21
20
:
248
247
:
4KB
4KB
:
0F8000H – 0F8FFFH
15
14
13
12
11
10
1
1
0F7000H – 0F7FFFH
:
240
239
:
4KB
4KB
:
0F0000H – 0F0FFFH
0EF000H – 0EFFFFH
:
232
231
:
4KB
4KB
:
0E8000H – 0E8FFFH
0E7000H – 0E7FFFH
:
1
1
1
1
1
1
1
1
0
0
1
0
0
1
1
0
1
0
1
0
224
223
:
4KB
4KB
:
0E0000H – 0E0FFFH
0DF000H – 0DFFFFH
:
216
215
:
4KB
4KB
:
0D8000H – 0D8FFFH
0D7000H – 0D7FFFH
:
208
207
:
4KB
4KB
:
0D0000H – 0D0FFFH
0CF000H – 0CFFFFH
:
200
199
:
4KB
4KB
:
0C8000H – 0C8FFFH
0C7000H – 0C7FFFH
:
192
191
:
4KB
4KB
:
0C0000H – 0C0FFFH
0BF000H – 0BFFFFH
:
184
183
:
4KB
4KB
:
0B8000H – 0B8FFFH
0B7000H – 0B7FFFH
:
176
175
:
4KB
4KB
:
0B0000H – 0B0FFFH
0AF000H – 0AFFFFH
:
168
167
:
4KB
4KB
:
0A8000H – 0A8FFFH
0A7000H – 0A7FFFH
:
160
4KB
0A0000H – 0A0FFFH
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2 5/43
ESMT
F25L08QA (2S)
Table 1: Sector Address Table – Continued I
Sector Size
Block Address
64KB
Block
32KB
Block
Sector
Address range
(Kbytes)
A19
1
A18
A17
A16
1
159
:
4KB
:
09F000H – 09FFFFH
19
18
17
16
15
14
13
12
11
10
9
:
152
151
:
4KB
4KB
:
098000H – 098FFFH
9
8
7
6
5
4
0
0
097000H – 097FFFH
:
144
143
:
4KB
4KB
:
090000H – 090FFFH
08F000H – 08FFFFH
:
136
135
:
4KB
4KB
:
088000H – 088FFFH
087000H – 087FFFH
:
1
0
0
0
0
0
1
1
1
1
0
1
1
0
0
0
1
0
1
0
128
127
:
4KB
4KB
:
080000H – 080FFFH
07F000H – 07FFFFH
:
120
119
:
4KB
4KB
:
078000H – 078FFFH
077000H – 077FFFH
:
112
111
:
4KB
4KB
:
070000H – 070FFFH
06F000H – 06FFFFH
:
104
103
:
4KB
4KB
:
068000H – 068FFFH
067000H – 067FFFH
:
96
95
:
4KB
4KB
:
060000H – 060FFFH
05F000H – 05FFFFH
:
88
87
:
4KB
4KB
:
058000H – 058FFFH
057000H – 057FFFH
:
80
79
:
4KB
4KB
:
050000H – 050FFFH
04F000H – 04FFFFH
:
72
71
:
4KB
4KB
:
048000H – 048FFFH
047000H – 047FFFH
:
8
64
4KB
040000H – 040FFFH
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2 6/43
ESMT
F25L08QA (2S)
Table 1: Sector Address Table – Continued II
Sector Size
Block Address
64KB
Block
32KB
Block
Sector
Address range
(Kbytes)
A19
A18
A17
A16
63
:
4KB
:
03F000H – 03FFFFH
7
6
5
4
3
2
1
0
:
56
55
:
4KB
4KB
:
038000H – 038FFFH
037000H – 037FFFH
:
3
2
1
0
0
0
1
1
48
47
:
4KB
4KB
:
030000H – 030FFFH
02F000H – 02FFFFH
:
40
39
:
4KB
4KB
:
028000H – 028FFFH
027000H – 027FFFH
:
0
0
0
0
0
0
1
0
0
0
1
0
32
31
:
4KB
4KB
:
020000H – 020FFFH
01F000H – 01FFFFH
:
24
23
:
4KB
4KB
:
018000H – 018FFFH
017000H – 017FFFH
:
16
15
:
4KB
4KB
:
010000H – 010FFFH
00F000H – 00FFFFH
:
8
4KB
4KB
:
008000H – 008FFFH
007000H – 007FFFH
:
7
:
0
4KB
000000H – 000FFFH
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2 7/43
ESMT
F25L08QA (2S)
STATUS REGISTER
The software status register provides status on whether the flash
memory array is available for any Read or Write operation,
whether the device is Write enabled, and the state of the memory
Write protection. During an internal Erase or Program operation,
the status register may be read only to determine the completion
of an operation in progress. Table 2 describes the function of
each bit in the software status register.
Table 2: Software Status Register
Default at
Power-up
Bit
Name
Function
Read/Write
Status Register -1
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
0
1
BUSY
WEL
0
0
R
R
1 = Device is memory Write enabled
0 = Device is not memory Write enabled
2
3
4
5
BP0
BP1
BP2
BP3
Indicate current level of block write protection (See Table 3)
Indicate current level of block write protection (See Table 3)
Indicate current level of block write protection (See Table 3)
Indicate current level of block write protection (See Table 3)
0
0
0
0
R/W
R/W
R/W
R/W
1 = Quad enabled
0 = Quad disabled
6
7
QE
0
0
R/W
R/W
1 = BP3, BP2,BP1,BP0 are read-only bits
0 = BP3, BP2,BP1,BP0 are read/writable
BPL
Default at
Power-up
Bit
Name
Function
Read/Write
Status Register -2
8
SUS
Suspend Status
0
0
R
9~15
Reserved
Reserved for future use
N/A
Note:
1. BUSY and WEL are read only.
2. BP0~3, QE and BPL bits are non-volatile.
Write Enable Latch (WEL)
BUSY
The Write-Enable-Latch bit indicates the status of the internal
memory Write Enable Latch. If this bit is set to “1”, it indicates the
device is Write enabled. If the bit is set to “0” (reset), it indicates
the device is not Write enabled and does not accept any memory
Write (Program/ Erase) commands. This bit is automatically reset
under the following conditions:
The BUSY bit determines whether there is an internal Erase or
Program operation in progress. A “1” for the BUSY bit indicates
the device is busy with an operation in progress. A “0” indicates
the device is ready for the next valid operation.
• Power-up
• Write Disable (WRDI) instruction completion
• Page Program instruction completion
• Sector Erase instruction completion
• Block Erase instruction completion
• Chip Erase instruction completion
• Write Status Register instructions
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2
8/43
ESMT
F25L08QA (2S)
Table 3: Block Protection Table
Status Register Bit
Protected Memory Area
Protection Level
BP3
X
0
BP2
0
BP1
0
BP0
0
64KB Block Range
None
Address Range
None
0
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
Upper 7/8
Upper 15/16
Bottom 1/16
Bottom 1/8
Bottom 1/4
Bottom 1/2
Bottom 7/8
Bottom 15/16
All Blocks
0
0
1
Block 15
0F0000H – 0FFFFFH
0E0000H – 0FFFFFH
0C0000H – 0FFFFFH
080000H – 0FFFFFH
020000H – 0FFFFFH
010000H – 0FFFFFH
000000H – 00FFFFH
000000H – 01FFFFH
000000H – 03FFFFH
000000H – 07FFFFH
000000H – 0DFFFFH
000000H – 0EFFFFH
000000H – 0FFFFFH
0
0
1
0
Block 14~15
Block 12~15
Block 8~15
Block 2~15
Block 1~15
Block 0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
1
0
0
1
1
0
1
0
Block 0~1
Block 0~3
Block 0~7
Block 0~13
Block 0~14
Block 0~15
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
X
1
1
1
Block Protection (BP3, BP2, BP1, BP0)
Block Protection Lock-Down (BPL)
The Block-Protection (BP3, BP2, BP1, BP0) bits define the
memory area, as defined in Table 3, to be software protected
against any memory Write (Program or Erase) operations. The
Write Status Register (WRSR) instruction is used to program the
WP pin driven low (VIL), enables the Block-Protection-
Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP3, BP2, BP1 and BP0 bits. When
the WP pin is driven high (VIH), the BPL bit has no effect and its
value is “Don’t Care”.
BP3, BP2, BP1 and BP0 bits as long as WP is high or the
Block- Protection-Look (BPL) bit is 0. Chip Erase can only be
executed if BP3, BP2, BP1 and BP0 bits are all 0. The factory
default setting for Block Protection Bit (BP3 ~ BP0) is 0.
Quad Enable (QE)
When the Quad Enable bit is reset to “0” (factory default), WP
and HOLD pins are enabled. When QE pin is set to “1”, Quad
SIO2 and SIO3 are enabled. (The QE should never be set to “1”
during standard and Dual SPI operation if the WP and HOLD
pins are tied directly to the VDD or VSS.)
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2
9/43
ESMT
F25L08QA (2S)
HOLD OPERATION
HOLD pin is used to pause a serial sequence underway with the
SPI flash memory without resetting the clocking sequence. To
Once the device enters Hold mode, SO will be in high impedance
state while SI and SCK can be VIL or VIH.
activate the HOLD mode, CE must be in active low state. The
HOLD mode begins when the SCK active low state coincides
with the falling edge of the HOLD signal. The HOLD mode ends
If CE is driven active high during a Hold condition, it resets the
internal logic of the device. As long as HOLD signal is low, the
memory remains in the Hold condition. To resume
when the HOLD signal’s rising edge coincides with the SCK
active low state.
communication with the device, HOLD must be driven active
high, and CE must be driven active low. See Figure 31 for Hold
timing.
If the falling edge of the HOLD signal does not coincide with the
SCK active low state, then the device enters Hold mode when the
SCK next reaches the active low state.
The HOLD function is only available for Standard SPI and Dual
SPI operation, not during Quad SPI because this pin is used for
SIO3 when the QE bit of Status Register-1 is set for Quad I/O.
Similarly, if the rising edge of the HOLD signal does not
coincide with the SCK active low state, then the device exits in
Hold mode when the SCK next reaches the active low state. See
Figure 1 for Hold Condition waveform.
SCK
HOLD
Hold
Active
Active
Active
Hold
Figure 1: HOLD Condition Waveform
WRITE PROTECTION
The device provides software Write Protection.
Table 4: Conditions to Execute Write-Status- Register
(WRSR) Instruction
The Write-Protect pin ( WP ) enables or disables the lock-down
function of the status register. The Block-Protection bits (BP3,
BP2, BP1, BP0 and BPL) in the status register provide Write
protection to the memory array and the status register. When the
BPL
1
Execute WRSR Instruction
Not Allowed
WP
L
QE bit of Status Register-1 is set for Quad I/O, the WP pin
function is not available since this pin is used for SIO2.
L
0
Allowed
H
X
Allowed
Write Protect Pin ( WP )
The Write-Protect ( WP ) pin enables the lock-down function of
the BPL bit (bit 7) in the status register. When WP is driven low,
the execution of the Write Status Register (WRSR) instruction is
determined by the value of the BPL bit (see Table 4). When WP
is high, the lock-down function of the BPL bit is disabled.
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2 10/43
ESMT
F25L08QA (2S)
INSTRUCTIONS
Instructions are used to Read, Write (Erase and Program), and
configure the F25L08QA. The instruction bus cycles are 8 bits
each for commands (Op Code), data, and addresses. Prior to
executing any Page Program, Write Status Register, Sector
Erase, Block Erase, or Chip Erase instructions, the Write Enable
(WREN) instruction must be executed first. The complete list of
the instructions is provided in Table 5. All instructions are
entered and must be driven high after the last bit of the instruction
has been shifted in (except for Read, Read ID, Read Status
Register, Read Electronic Signature instructions). Any low to high
transition on CE , before receiving the last bit of an instruction
bus cycle, will terminate the instruction in progress and return the
device to the standby mode.
synchronized off a high to low transition of CE . Inputs will be
accepted on the rising edge of SCK starting with the most
Instruction commands (Op Code), addresses, and data are all
input from the most significant bit (MSB) first.
significant bit. CE must be driven low before an instruction is
Table 5: Device Operation Instruction
Bus Cycle 1~3
4
Max.
Freq
Operation
1
2
3
5
6
N
SIN SOUT
SIN
SOUT
SIN
SOUT SIN SOUT SIN SOUT SIN SOUT SIN SOUT
Read
Fast Read
33 MHz 03H Hi-Z A23-A16 Hi-Z
0BH Hi-Z A23-A16 Hi-Z
A15-A8 Hi-Z A7-A0 Hi-Z
A15-A8 Hi-Z A7-A0 Hi-Z
X
X
DOUT0
X
X
X
X
DOUT1
DOUT0
X
X
cont.
cont.
cont.
-
cont.
-
Fast Read Dual Output12,13
Fast Read Dual I/O12, 14
Fast Read Quad
3BH
BBH
A23-A16
A23-A8
A15-A8
A7-A0
DOUT0~1
A7-A0, M7-M0
DOUT0~1
cont.
-
6BH
EBH
A23-A16
A15-A8
A7-A0
X
DOUT0~3
-
-
-
-
Output12, 15
Fast Read Quad I/O12, 16
Sector Erase4 (4K Byte)
Block Erase5 (32K Byte)
Block Erase5 (64K Byte)
A23-A0, M7-M0
X, DOUT0~1
DOUT2~6
cont.
20H Hi-Z A23-A16 Hi-Z
52H Hi-Z A23-A16 Hi-Z
D8H Hi-Z A23-A16 Hi-Z
60H /
A15-A8 Hi-Z A7-A0 Hi-Z
A15-A8 Hi-Z A7-A0 Hi-Z
A15-A8 Hi-Z A7-A0 Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Chip Erase
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
C7H
Erase Suspend
Erase Resume
75H
7AH Hi-Z
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Up to
Page Program (PP)
02H Hi-Z A23-A16 Hi-Z
A15-A8 Hi-Z A7-A0 Hi-Z DIN0 Hi-Z DIN1 Hi-Z 256 Hi-Z
50MHz
~
bytes
Up to 256
Quad Page Program17
Mode Bit Reset 6
Deep Power Down (DP)
Read Status Register-1
(RDSR-1) 7
32H
A23-A16
A15-A8
A7-A0
DIN0~3
DIN4~7
byte
FFH Hi-Z
B9h Hi-Z
FFH
-
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DOUT
(S7-S0)
DOUT
(S15-S8)
05H Hi-Z
35H Hi-Z
X
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Read Status Register-2
100MHz
X
-
(RDSR-2) 7
Write Status Register
(WRSR) 10
DIN
(S7-S0)
-
01H Hi-Z
06H Hi-Z
04H Hi-Z
Hi-Z
-
-
-
-
-
-
-.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Write Enable (WREN) 10
Write Disable (WRDI)/ Exit
secured OTP mode
Enter secured OTP mode
(ENSO)
-
-
-
-
-
B1H Hi-Z
ABH Hi-Z
ABH Hi-Z
ABH Hi-Z
ABH Hi-Z
-
-
-
-.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Release from Deep Power
Down (RDP)
-
-
-
-
-
-
Read Electronic Signature
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
13H
33H
73H
(RES) 8
RES in secured OTP mode
& not lock down
RES in secured OTP mode
& lock down
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2 11/43
ESMT
F25L08QA (2S)
Table 5: Device Operation Instruction - Continued
Bus Cycle 1~3
Max.
Freq
Operation
1
2
3
4
5
6
N
SIN SOUT
SIN
SOUT
SIN
SOUT SIN SOUT SIN SOUT SIN SOUT SIN SOUT
Jedec Read ID
50MHz 9FH Hi-Z
~
X
8CH
X
40H
Hi-Z
X
14H
-
-
-
-
-
-
(JEDEC-ID) 9
00H Hi-Z
01H Hi-Z
X
X
8CH
13H
X
X
13H
8CH
-
-
-
-
Read ID (RDID) 11
90H Hi-Z
00H
Hi-Z
00H
100MHz
Notes:
1. Operation: SIN = Serial In, SOUT = Serial Out, Bus Cycle 1 = Op Code
2. X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary); cont. = continuous
3. One bus cycle is eight clock periods.
4. 4K byte Sector Earse addresses: use AMS -A12, remaining addresses can be VIL or VIH.
5. 32K byte Block Earse addresses: use AMS -A15, remaining addresses can be VIL or VIH
64K byte Block Earse addresses: use AMS -A16, remaining addresses can be VIL or VIH
6. This instruction is recommended when using the Dual or Quad Mode bit feature.
7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE .
8. The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE .
9. The JEDEC-Read-ID is output first byte 8CH as manufacture ID; second byte 40H as memory type; third byte 14H as
memory capacity.
10. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each
other. The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both
instructions effective. A successful WRSR can reset WREN.
11. The Manufacture ID and Device ID output will repeat continuously until CE terminates the instruction.
12. Dual and Quad commands use bidirectional IO pins. DOUT and cont. are serial data out; others are serial data in.
13. Dual output data:
IO
IO
0
= (D
6
, D
4
, D
2
, D
0
), (D
6
, D
4
, D
2
, D
0
)
)
1
= (D
7
, D5
, D3
, D1
), (D
7
, D5
, D3
, D1
DOUT0
DOUT1
14. M7-M0: Mode bits. Dual input address:
IO
IO
0
= (A22, A20, A18, A16, A14, A12, A10, A
8
)
(A
6
, A
4
, A
2
, A
0
, M
6
, M
4
, M
2
, M
0
)
1
= (A23, A21, A19, A17, A15, A13, A11, A
9
)
(A7
, A
5
, A
3
, A
1
, M
7
, M
5
, M
3
, M
1
)
Bus Cycle-2
Bus Cycle-3
15. Quad output data:
IO
IO
IO
IO
0
1
2
3
= (D
= (D
= (D
= (D
4
5
6
7
, D
, D
, D
, D
0
1
2
3
), (D
), (D
), (D
), (D
4
5
6
7
, D
, D
, D
, D
0
1
2
3
), (D
), (D
), (D
), (D
4
5
6
7
, D
, D
, D
, D
0
1
2
3
), (D
), (D
), (D
), (D
4
5
6
7
, D
, D
, D
, D
0
1
2
3
)
)
)
)
DOUT0
DOUT1
DOUT2
DOUT3
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2 12/43
ESMT
F25L08QA (2S)
16. M7-M0: Mode bits. Quad input address:
IO
IO
IO
IO
0
1
2
3
= (A20, A16, A12, A
= (A21, A17, A13, A
= (A22, A18, A14, A10, A
8
, A
4
, A
, A
0
, M
4
, M
, M
0
)
)
2
9
, A5
1
, M5
1
6
, A
2
, M
6
, M
)
)
= (A23, A19, A15, A11, A
7
, A
3
, M
7
, M
3
Bus Cycle-2
Fast Read Quad I/O data:
IO
IO
IO
IO
0
1
2
3
= (X, X), (X, X), (D
= (X, X), (X, X), (D
= (X, X), (X, X), (D
= (X, X), (X, X), (D
4
5
6
7
, D
, D
, D
, D
0
1
2
3
), (D
4
5
6
7
, D
, D
, D
, D
0
1
2
3
) (D
) (D
) (D
) (D
4
5
6
7
, D
, D
, D
, D
0
1
2
3
), (D
), (D
), (D
), (D
4
5
6
7
, D
, D
, D
, D
0
1
2
3
), (D
), (D
), (D
), (D
4
5
6
7
, D
, D
, D
, D
0
1
2
3
), (D
), (D
), (D
), (D
4
5
6
7
, D
, D
, D
, D
0
1
2
3
)
)
)
)
), (D
), (D
), (D
DOUT0
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
Bus Cycle-3
Bus Cycle-4
17. The instruction is initiated by executing command code, followed by address bits into SI (SIO0) before DIN, and then input
data to bidirectional IO pins (SIO0 ~ SIO3).
Quad input data:
IO
IO
IO
IO
0
1
2
3
= (D
= (D
= (D
= (D
4
5
6
7
, D
, D
, D
, D
0
1
2
3
), (D
), (D
), (D
), (D
4
5
6
7
, D
, D
, D
, D
0
1
2
3
), (D
), (D
), (D
), (D
4
5
6
7
, D
, D
, D
, D
0
1
2
3
), (D
), (D
), (D
), (D
4
5
6
7
, D
, D
, D
, D
0
1
2
3
)
)
)
)
DIN0
DIN1
DIN2
DIN3
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2 13/43
ESMT
F25L08QA (2S)
Read (33MHz)
The Read instruction supports up to 33 MHz, it outputs the data
starting from the specified address location. The data output
stream is continuous through all addresses until terminated by a
the data from address location 0FFFFFH had been read, the
next output will be from address location 000000H.
The Read instruction is initiated by executing an 8-bit command,
low to high transition on CE . The internal address pointer will
automatically increment until the highest memory address is
reached. Once the highest memory address is reached, the
address pointer will automatically increment to the beginning
(wrap-around) of the address space, i.e. for 8Mbit density, once
03H, followed by address bits [A23 -A0]. CE must remain active
low for the duration of the Read cycle. See Figure 2 for the Read
sequence.
CE
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47 48
MODE3
MODE0
55 56
63 64
70
SCK
SI
03
ADD.
MSB
ADD.
A DD.
MSB
N
N+1
DOUT
N+2
DOUT
N+3
DOU T
N+4
DOU T
HIGH IMPENDANCE
SO
DOU T
MSB
Figure 2: Read Sequence
Fast Read (50 MHz ~ 100 MHz)
The Fast Read instruction supporting up to 100 MHz is initiated
by executing an 8-bit command, 0BH, followed by address bits
all addresses until terminated by a low to high transition on CE .
The internal address pointer will automatically increment until the
highest memory address is reached. Once the highest memory
address is reached, the address pointer will automatically
increment to the beginning (wrap-around) of the address space,
i.e. for 8Mbit density, once the data from address location
0FFFFFH has been read, the next output will be from address
location 000000H.
[A23 -A0] and a dummy byte. CE must remain active low for the
duration of the Fast Read cycle. See Figure 3 for the Fast Read
sequence.
Following a dummy byte (8 clocks input dummy cycle), the Fast
Read instruction outputs the data starting from the specified
address location. The data output stream is continuous through
CE
0
1 2
3
4 5 6 7
8
15 16
23 24
31 32
39 40
47 48
MODE3
MODE0
55 56
63 64
71 72
80
SCK
SI
0B
ADD.
MSB
ADD.
ADD.
X
MSB
N
N+1
DOUT
N+2
DOUT
N+3
DOU T
N+4
DOU T
HIGH IMPENANCE
SO
DOU T
MSB
Note : X = Dummy Byte : 8 Clocks Input Dummy (VIL or VIH)
Figure 3: Fast Read Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2 14/43
ESMT
F25L08QA (2S)
Fast Read Dual Output (50 MHz ~ 100 MHz)
The Fast Read Dual Output (3BH) instruction is similar to the
standard Fast Read (0BH) instruction except the data is output
on bidirectional I/O pins (SIO0 and SIO1). This allows data to be
transferred from the device at twice the rate of standard SPI
devices. This instruction is for quickly downloading code from
Flash to RAM upon power-up or for applications that cache code-
segments to RAM for execution.
The Fast Read Dual Output instruction is initiated by executing
an 8-bit command, 3BH, followed by address bits [A23 -A0] and a
dummy byte. CE must remain active low for the duration of the
Fast Read Dual Output cycle. See Figure 4 for the Fast Read
Dual Output sequence.
CE
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32
39 40
43 44
MODE3
MODE0
47 48
51 52
55 56
SCK
SIO0
IO0 switches from Input to Ouput
Dummy
3B
ADD.
MSB
ADD.
ADD.
6
7
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
1
6
7
4
MSB
DOUT
N
DOUT
N+1
DOU T
N+2
DOU T
N+3
DOUT
N+4
5
HIGH IMPENANCE
SIO1
5
1
7
5
1
7
5
1
7
5
3
3
3
3
Note: The input data during the dummy clocks is “don’t care”.
However , the IO0 pin should be high-impefance piror to the falling edge of the first data clock.
Figure 4: Fast Read Dual Output Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2 15/43
ESMT
F25L08QA (2S)
Fast Read Dual I/O (50 MHz ~ 100 MHz)
The Fast Read Dual I/O (BBH) instruction is similar to the Fast
Read Dual Output (3BH) instruction, but with the capability to
input address bits [A23 -A0] two bits per clock.
If [M7 –M0] = “AxH”, the next Fast Read Dual I/O instruction (after
CE is raised and the lowered) doesn’t need the command code
(See Figure 6). This way let the instruction sequence reduce 8
clocks and allows to enter address immediately after CE is
asserted low. If [M7 –M0] are the value other than “AxH”, the next
instruction need the first byte command code, thus returning to
normal operation. A Mode Bit Reset (FFH) also can be used to
reset mode bits [M7 –M0] before issuing normal instructions.
To set mode bits [M7 -M0] after the address bits [A23 -A0] can
further reduce instruction overhead (See Figure 5). The upper
mode bits [M7 –M4] controls the length of next Fast Read Dual I/O
instruction with/without the first byte command code (BBH). The
lower mode bits [M3 –M0] are “don’t care”.
CE
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
27 28
31 32
35 36
39 40
MODE3
MODE0
SCK
SIO0
IO0 switches from Input to Ouput
22
2
20 18 16 14 12 10
6
4
5
0
1
6
4
BB
8
9
6
7
4
2
0
6
4
2
0
6
4
2
0
6
4
2 0
6
7
4
MSB
DOUT
N
DOU T
N+1
DOUT
N+2
DOUT
N+3
DOUT
N+4
5
HIGH IMPENANCE
SIO1
23 21 19
11
7
3
7
5
M7-0
17 15 13
5
1
7
5
1
7
5
1
7
5
1
3
3
3
3
A23-16 A15-8
A7- 0
Note: The mode bits [M3 -M0] are “don’t care”.
However , the IO pins should be high-impefance piror to the falling edge of the first data clock.
Figure 5: Fast Read Dual I/O Sequence ([M7 -M0] = 0xH or NOT AxH)
CE
SCK
SIO0
MODE3
MODE0
0 1 2 3 4 5 6 7 8 9 10 11 121314 15 16
1920
2324
2728
3132
IO0 switches from Input to Ouput
22
2
20 18 16 14 12 10
6
4
0
1
6
4
8
6
7
4
2
0
1
6
7
4
2
0
1
6
7
4
2
0
1
6
7
4
2
0
1
6
7
4
DOUT
N
DOUT
N+1
DOU T
N+2
DOUT
N+3
DOUT
N+4
5
SIO1
23 21 19
11
9
7
5
3
7
5
17 15 13
5
5
5
5
3
3
3
3
A23-16 A15- 8
A7-0
M7-0
Note: The mode bits [M3 -M0] are “don’t care”.
However , the IO pins should be high-impefance piror to the falling edge of the first data clock.
Figure 6: Fast Read Dual I/O Sequence ([M7 -M0] = AxH)
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2 16/43
ESMT
F25L08QA (2S)
Fast Read Quad Output (50 MHz ~ 100 MHz)
The Fast Read Quad Output (6B) instruction is similar to the Fast
Read Dual Output (3BH) instruction except the data is output on
bidirectional I/O pins (SIO0, SIO1, SIO2 and SIO3). A Quad
Enable (QE) bit of Status Register-1 must be set “1” to enable
Quad function. This allows data to be transferred from the device
at four times the rate of standard SPI devices.
The Fast Read Quad Output instruction is initiated by executing
an 8-bit command, 6BH, followed by address bits [A23 -A0] and a
dummy byte. CE must remain active low for the duration of the
Fast Read Dual Output cycle. See Figure 7 for the Fast Read
Quad Output sequence.
CE
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32
39 40 4142 43 44 45 46
4748
MODE3
MODE0
SCK
IO0 switches from Input to Ouput
Dummy
6B
ADD.
MSB
ADD.
ADD.
4
5
0
1
0
4
0
0
4
0
SIO0
SIO1
SIO2
SIO3
4
5
4
MSB
HIGH IMPENANCE
HIGH IMPENANCE
HIGH IMPENANCE
1
5
1
1
5
6
7
1
2
3
5
N
N+1 N+2 N+3 N+4
DOU T DOUT DOUT DOU T DOUT
Note: The input data during the dummy clocks is “don’t care”.
However , the IO pins should be high-impefance piror to the falling edge of the first data clock.
Figure 7: Fast Read Quad Output Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2 17/43
ESMT
F25L08QA (2S)
Fast Read Quad I/O (50 MHz ~ 100 MHz)
The Fast Read Quad I/O (EBH) instruction is similar to the Fast
Read Quad Output (6BH) instruction, but with the capability to
input address bits [A23 -A0] four bits per clock. A Quad Enable
(QE) bit of Status Register-1 must be set “1” to enable Quad
function.
If [M7 –M0] = “AxH”, the next Fast Read Quad I/O instruction (after
CE is raised and the lowered) doesn’t need the command code
(See Figure 9). This way let the instruction sequence reduce 8
clocks and allows to enter address immediately after CE is
asserted low. If [M7 –M0] are the value other than “AxH”, the next
instruction need the first byte command code, thus returning to
normal operation. A Mode Bit Reset (FFH) also can be used to
reset mode bits [M7 –M0] before issuing normal instructions.
To set mode bits [M7 -M0] after the address bits [A23 -A0] can
further reduce instruction overhead (See Figure 8). The upper
mode bits [M7 –M4] controls the length of next Fast Read Quad
I/O instruction with/without the first byte command code (EBH).
The lower mode bits [M3 –M0] are “don’t care”.
CE
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
MODE3
MODE0
SCK
IO0 switches from Input to Ouput
Dummy
20
16 12
8
4
5
0
1
4
EB
0
1
4
0
0
4
0
SIO0
SIO1
4
MSB
HIGH IMPENANCE
HIGH IMP ENANCE
HIGH IMP ENANCE
21 17 13
22 18 14
5
9
5
1
5
1
5
1
SIO2
6
7
2
3
10
6
7
2
3
6
7
2
3
6
7
2
3
6
7
2
3
SIO3
23 19 15 11
A23- 0
M7-0
N
N+1 N+2
DOUT DOUT DOUT
Note: The mode bits [M3 -M0] are “don’t care”.
However , the IO pins should be high-impefance piror to the falling edge of the first data clock.
Figure 8: Fast Read Quad I/O Sequence ([M7 -M0] = 0xH or NOT AxH)
CE
0
1
2
3
8
4
5
6
7
8
9 10 11 12 13 14 15 16
MODE3
MODE0
SCK
IO0 switches from Input to Ouput
Dummy
20
16 12
4
5
0
1
4
5
0
1
4
5
0
1
0
4
5
0
1
4
5
SIO0
SIO1
21 1 7 13
22 18 14
9
1
6
7
2
3
10
6
7
2
3
6
7
2
3
6
7
2
3
SIO
2
6
7
2
3
23 19 15 11
SIO
3
A23-0
M7-0
N
N+1 N+2
DOUT DOUT DOU T
Note: The mode bits [M3 -M0] are “don’t care”.
However , the IO pins should be high-impefance piror to the falling edge of the first data clock.
Figure 9: Fast Read Quad I/O Sequence ([M7 -M0] = AxH)
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2 18/43
ESMT
F25L08QA (2S)
Page Program (PP)
The Page Program instruction allows many bytes to be
programmed in the memory. The bytes must be in the erased
state (FFH) when initiating a Program operation. A Page
Program instruction applied to a protected memory area will be
ignored.
latched data are discarded and the last 256 bytes Data are
guaranteed to be programmed correctly within the same page. If
less than 256 bytes Data are sent to device, they are correctly
programmed at the requested addresses without having any
effects on the other bytes of the same page.
Prior to any Write operation, the Write Enable (WREN) instruction
CE must be driven high before the instruction is executed. The
user may poll the BUSY bit in the software status register or wait
TPP for the completion of the internal self-timed Page Program
operation. While the Page Program cycle is in progress, the Read
Status Register instruction may still be accessed for checking the
status of the BUSY bit. The BUSY bit is a 1 during the Page
Program cycle and becomes a 0 when the cycle is finished and
the device is ready to accept other instructions again. After the
Page Program cycle has finished, the Write-Enable-Latch (WEL)
bit in the Status Register-1 is cleared to 0. See Figure 10 for the
Page Program sequence.
must be executed. CE must remain active low for the duration
of the Page Program instruction. The Page Program instruction is
initiated by executing an 8-bit command, 02H, followed by
address bits [A23-A0]. Following the address, at least one byte
Data is input (the maximum of input data can be up to 256 bytes).
If the 8 least significant address bits [A7-A0] are not all zero, all
transmitted data that goes beyond the end of the current page
are programmed from the start address of the same page (from
the address whose 8 least significant bits [A7-A0] are all zero).
If more than 256 bytes Data are sent to the device, previously
Figure 10: Page Program Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2
19/43
ESMT
F25L08QA (2S)
Quad Page Program
The Quad Page Program instruction allows many bytes to be
programmed in the memory by using four I/O pins (SIO0, SIO1,
SIO2 and SIO3). The instruction can improve programmer
performance and the effectiveness of application that have slow
clock speed <20MHz. For system with faster clock, this
instruction can’t provide more actual favors, because the required
internal page program time is far more than the time data flows in.
Therefore, we suggest that user can execute this command while
the clock speed <20MHz.
Prior to Quad Page Program operation, the Write Enable (WREN)
instruction must be executed and Quad Enable (QE) bit of Status
Register must be set “1”. The other function descriptions are as
same as standard Page Program. See Figure 11 for the Quad
Page Program sequence.
CE
0
1
2
3
4
5
6
7
8
15 16
23 24
31 32 3334 35 36 37 3839
MODE3
MODE0
SCK
SS
32
ADD.
MSB
ADD.
ADD.
4
5
0
1
0
1
4
5
0
1
0
1
4
0
SIO0
SIO1
SIO2
SIO3
4
5
4
5
SS
MSB
SS
SS
SS
5
6
7
1
2
3
DIN 0 DIN 1 DIN2 DIN3
DIN255
Figure 11: Quad Page Program Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Nov. 2013
Revision: 1.2 20/43
ESMT
F25L08QA (2S)
Mode Bit Reset
Mode bits [M7 –M0] are issued to further reduce instruction
overhead for Fast Read Dual/Quad I/O operation. If [M7 –M0] =
“AxH”, the next Fast Read Dual/Quad I/O instruction doesn’t
need the command code.
However, the device doesn’t have a hardware reset pin, so if
[M7 –M0] = “AxH”, the device will not recognize any standard SPI
instruction. After a system reset, it is recommended to issue a
Mode Bit Reset instruction first to release the status of [M7 –M0] =
“AxH” and allow the device to recognize standard SPI instruction.
See Figure 12 for the Mode Bit Reset instruction.
If the system controller is reset during operation, it will send a
standard instruction (such as Read ID) to the Flash memory.
Mode bit Reset for Dual I/O
Mode bit Reset for Quad I/O
CE
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
MODE3
SCK MODE0
SIO0
SIO1
FF
FF
SIO2
SIO3
Note: To reset mode bits during Quad I/O operation, only eight clocks are needed. The command code is “FFH”.
To reset mode bits during Dual I/O operation, sixteen clocks are needed to shift in command code “FFFFH”.
Figure 12: Mode Bit Reset Instruction
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ESMT
F25L08QA (2S)
64K Byte Block Erase
The 64K-byte Block Erase instruction clears all bits in the
selected block to FFH. A Block Erase instruction applied to a
protected memory area will be ignored. Prior to any Write
operation, the Write Enable (WREN) instruction must be
-A0]. Address bits [AMS -A16] (AMS = Most Significant address) are
used to determine the block address (BAX), remaining address
bits can be VIL or VIH. CE must be driven high before the
instruction is executed. The user may poll the BUSY bit in the
Software Status Register or wait TBE for the completion of the
internal self-timed Block Erase cycle. See Figure 13 for 64K Byte
Block Erase sequence.
executed. CE must remain active low for the duration of the any
command sequence. The Block Erase instruction is initiated by
executing an 8-bit command, D8H, followed by address bits [A23
CE
0 1 2 3 4 5 6 7 8
15 16
23 24
31
MODE3
MODE0
SCK
ADD.
ADD.
ADD.
D8
SI
MSB
MSB
HIGH IMPENANCE
SO
Figure 13: 64K-byte Block Erase Sequence
32K Byte Block Erase
The 32K-byte Block Erase instruction clears all bits in the
selected block to FFH. A Block Erase instruction applied to a
protected memory area will be ignored. Prior to any Write
operation, the Write Enable (WREN) instruction must be
-A0]. Address bits [AMS -A15] (AMS = Most Significant address) are
used to determine the block address (BAX), remaining address
bits can be VIL or VIH. CE must be driven high before the
instruction is executed. The user may poll the BUSY bit in the
Software Status Register or wait TBE for the completion of the
internal self-timed Block Erase cycle. See Figure 14 for 32K Byte
Block Erase sequence.
executed. CE must remain active low for the duration of the any
command sequence. The Block Erase instruction is initiated by
executing an 8-bit command, 52H, followed by address bits [A23
CE
0 1 2 3 4 5 6 7 8
15 16
23 24
31
MODE3
MODE0
SCK
ADD.
ADD.
ADD.
52
SI
MSB
MSB
HIGH IMPENANCE
SO
Figure 14: 32K-byte Block Erase Sequence
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ESMT
F25L08QA (2S)
4K Byte Sector Erase
The Sector Erase instruction clears all bits in the selected sector
to FFH. A Sector Erase instruction applied to a protected memory
area will be ignored. Prior to any Write operation, the Write
[AMS -A12] (AMS = Most Significant address) are used to determine
the sector address (SAX), remaining address bits can be VIL or
VIH. CE must be driven high before the instruction is executed.
The user may poll the BUSY bit in the Software Status Register
or wait TSE for the completion of the internal self-timed Sector
Erase cycle. See Figure 15 for the Sector Erase sequence.
Enable (WREN) instruction must be executed. CE must remain
active low for the duration of the any command sequence. The
Sector Erase instruction is initiated by executing an 8-bit
command, 20H, followed by address bits [A23 -A0]. Address bits
CE
0 1 2 3 4 5 6 7 8
15 16
23 24
31
MODE3
MODE0
SCK
ADD.
ADD.
ADD.
20
SI
MSB
MSB
HIGH IMPENANCE
SO
Figure 15: 4K-byte Sector Erase Sequence
Chip Erase
The Chip Erase instruction clears all bits in the device to FFH. A
Chip Erase instruction will be ignored if any of the memory area is
protected. Prior to any Write operation, the Write Enable (WREN)
Erase instruction is initiated by executing an 8-bit command, 60H
or C7H. CE must be driven high before the instruction is
executed. The user may poll the BUSY bit in the Software Status
Register or wait TCE for the completion of the internal self-timed
Chip Erase cycle. See Figure 16 for the Chip Erase sequence.
instruction must be executed. CE must remain active low for
the duration of the Chip Erase instruction sequence. The Chip
CE
0 1 2 3 4 5 6 7
MODE3
SCK
SI
MODE0
60 or C7
MSB
HIGH IMPENANCE
SO
Figure 16: Chip Erase Sequence
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F25L08QA (2S)
Erase Suspend
The Erase Suspend instruction allows the system to interrupt a
Sector or Block Erase operation and then read from any other
sector or block. The Write Status Register instruction and Sector /
Block Erase instructions are not allowed during suspend. Erase
Suspend is valid only during the Sector or Block Erase operation.
If written during the Chip Erase or Program operation, the Erase
Suspend instruction is ignored. A maximum of TSUS is required to
suspend the erase operation. The BUSY bit in the Software
Status Register will clear to “0” after Erase Suspend. A power-off
during the suspend period will reset the device and release the
suspend status.
CE
0
1
2
3
4
5
6
7
MODE3
TSUS
SCK MODE0
SI
75
MSB
HIGH IMPEDANCE
SO
Accept Read or Program Instruction
Figure 17: Erase Suspend Instruction
Erase Resume
The Erase Resume instruction must be written to resume the
Sector or Block Erase operation after Erase Suspend. After
issued the BUSY bit in the Software Status Register will be set to
“1” and the sector or block will complete the erase operation.
Erase Resume instruction will be ignored unless an Erase
Suspend operation is active.
CE
0
1
2
3
4
5
6
7
MODE3
SCK MODE0
SI
7A
MSB
Resume Sector or Block Erase
Figure 18: Erase Resume Instruction
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ESMT
F25L08QA (2S)
Write Enable (WREN)
The Write Enable (WREN) instruction sets the Write-Enable-
Latch bit in the Software Status Register to 1 allowing Write
operations to occur.
(Program/Erase) operation. CE must be driven high before the
WREN instruction is executed.
The WREN instruction must be executed prior to any Write
CE
0 1 2 3 4 5 6 7
MODE3
MODE0
SCK
SI
06
MSB
HIGH IMPENANCE
SO
Figure 19: Write Enable (WREN) Sequence
Write Disable (WRDI)
The Write Disable (WRDI) instruction resets the Write-Enable-
Latch bit to 0 disabling any new Write operations from occurring
or exits from OTP mode to normal mode.
CE must be driven high before the WRDI instruction is
executed.
CE
0 1 2 3 4 5 6 7
MODE3
SCK
SI
MODE0
04
MSB
HIGH IMPENANCE
SO
Figure 20: Write Disable (WRDI) Sequence
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F25L08QA (2S)
Write Status Register (WRSR)
The Write Status Register instruction writes new values to the
BP3, BP2, BP1, BP0, QE and BPL (Status Register-1) bits of the
When WP is high, the lock-down function of the BPL bit is
disabled and the BPL, BP0, BP1, BP2 and BP3 bits in the status
status register. CE must be driven low before the command
sequence of the WRSR instruction is entered and driven high
register can all be changed. As long as BPL bit is set to 0 or WP
pin is driven high (VIH) prior to the low-to-high transition of the
before the WRSR instruction is executed. CE must be driven
high after the eighth bit of data that is clocked in. If it is not done,
the WRSR instruction will not be issued. See Figure 21 for
WREN and WRSR instruction sequences.
CE pin at the end of the WRSR instruction, the bits in the status
register can all be altered by the WRSR instruction. In this case,
a single WRSR instruction can set the BPL bit to “1” to lock down
the status register as well as altering the BP0; BP1, BP2 and BP3
bits at the same time. See Table 4 for a summary description of
Executing the Write Status Register instruction will be ignored
when WP is low and BPL bit is set to “1”. When the WP is
low, the BPL bit can only be set from “0” to “1” to lock down the
status register, but cannot be reset from “1” to “0”.
WP and BPL functions.
CE
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
MODE3
MODE0
SCK
Stauts Register-1
Data In
06
01
7
6
4
3
2
0
1
SI
5
MSB
MSB
HIGH IMPENANCE
SO
Figure 21: Write Enable (WREN) and Write Status Register (WRSR)
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows reading of
the status register. The status register may be read at any time
even during a Write (Program/Erase) operation. When a Write
operation is in progress, the BUSY bit may be checked before
sending any new commands to assure that the new commands
are properly received by the device.
and remain low until the status data is read. The RDSR-1
instruction code is “05H” for Status Register-1. The RDSR-2
instruction code is “35H” for Status Register-2. Read Status
Register is continuous with ongoing clock cycles until it is
terminated by a low to high transition of the CE . See Figure 22
for the RDSR instruction sequence.
CE must be driven low before the RDSR instruction is entered
CE
MODE3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK MODE0
05 or 35
SI
MSB
HIGH IMPEDANCE
SO
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MSB
Status Register -1 or -2 Data Out
Figure 22: Read Status Register (RDSR-1 or RDSR-2) Sequence
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ESMT
F25L08QA (2S)
Enter OTP Mode (ENSO)
The ENSO (B1H) instruction is for entering the additional 512
bytes secured OTP mode. The additional 512 bytes secured OTP
sector is independent from main array, which may use to store
unique serial number for system identifier. User must unprotect
whole array (BP0=BP1=BP2=BP3=0), prior to any Program
operation in OTP sector. After entering the secured OTP mode,
only the secured OTP sector can be accessed and user can only
follow the Read or Program procedure with OTP address range
(address bits [A23 –A9] must be “0”). The secured OTP data
cannot be updated again once it is lock down or has been
programmed. In secured OTP mode, WRSR command will
ignore the input data and lock down the secured OTP sector
(OTP_lock bit =1). To exit secured OTP mode, user must
execute WRDI command. RES can be used to verify the secured
OTP status as shown in Table 6.
Figure 23: Enter OTP Mode (ENSO) Sequence
OTP Sector Address
Size
Address Range
512 bytes
000000H ~ 0001FFH
Note: The OTP sector is an independent Sector.
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ESMT
F25L08QA (2S)
Deep Power Down (DP)
The Deep Power Down instruction is for minimizing power
consumption (the standby current is reduced from ISB1 to ISB2.).
Once the device is in deep power down status, all instructions will
be ignored except the Release from Deep Power Down
instruction (RDP) and Read Electronic Signature instruction
(RES). The device always power-up in the normal operation with
the standby current (ISB1). See Figure 24 for the Deep Power
Down instruction.
This instruction is initiated by executing an 8-bit command, B9H,
and then CE must be driven high. After CE is driven high, the
device will enter to deep power down within the duration of TDP
.
CE
MODE3
0
1
2
3
4
5
6
7
TDP
SCK MODE0
B9
SI
MSB
Standard Current
Deep Power Down Current
(ISB2)
Figure 24: Deep Power Down Instruction
Release from Deep Power Down (RDP) and Read Electronic-Signature (RES)
The Release form Deep Power Down and Read
Electronic-Signature instruction is a multi-purpose instruction.
CE low and executing an 8-bit command, ABH, followed by 3
dummy bytes. The Electronic-Signature byte is then output from
the device. The Electronic-Signature can be read continuously
The instruction can be used to release the device from the deep
power down status. This instruction is initiated by driving CE
until CE go high. See Figure 26 for RES sequence. After
driving CE high, it must remain high during for the duration of
TRES2, and then the device will resume normal operation and
other instructions are accepted.
low and executing an 8-bit command, ABH, and then drive CE
high. See Figure 25 for RDP instruction. Release from the deep
power down will take the duration of TRES1 before the device will
resume normal operation and other instructions are accepted.
The instruction is executed while an Erase, Program or WRSR
cycle is in progress is ignored and has no effect on the cycle in
progress. In OTP mode, user also can execute RES to confirm
the status of OTP.
CE must remain high during TRES1
.
The instruction also can be used to read the 8-bit Electronic-
Signature of the device on the SO pin. It is initiated by driving
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ESMT
F25L08QA (2S)
CE
MODE3
0
1
2
3
4
5
6
7
TRES1
SCK MODE0
AB
SI
MSB
HIGH IMPEDANCE
SO
Standby Current
Deep Power Down Current
(ISB2)
Figure 25: Release from Deep Power Down (RDP) Instruction
CE
30 31 32 33 34 35 36 37 38
0
1
2
3
4
5
6
7
8
9
MODE3
TRES2
SCK MODE0
SS
3 Dummy Bytes
SS
AB
SI
MSB
HIGH IMPEDANCE
SS
Electronic-Signature Data Out
SO
MSB
Standby
Current
Deep Power Down Current
(ISB2)
Figure 26: Read Electronic -Signature (RES) Sequence
Table 6: Electronic Signature Data
Command
Mode
Electronic Signature Data
Normal
13H
In secured OTP mode &
33H
73H
RES
non lock down (OTP_lock =0)
In secured OTP mode &
lock down (OTP_lock =1)
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ESMT
F25L08QA (2S)
JEDEC Read-ID
The JEDEC Read-ID instruction identifies the device as
F25L08QA and the manufacturer as ESMT. The device
information can be read from executing the 8-bit command, 9FH.
Following the JEDEC Read-ID instruction, the 8-bit
manufacturer’s ID, 8CH, is output from the device. After that, a
16-bit device ID is shifted out on the SO pin. Byte1, 8CH,
identifies the manufacturer as ESMT. Byte2, 40H, identifies the
memory type as SPI Flash. Byte3, 14H, identifies the device as
F25L08QA. The instruction sequence is shown in Figure 27.
The JEDEC Read ID instruction is terminated by a low to high
transition on CE at any time during data output. If no other
command is issued after executing the JEDEC Read-ID
instruction, issue a 00H (NOP) command before going into
Standby Mode ( CE =VIH).
CE
0
1
2
3
4 5 6 7 8 9 10 11 12 13 1415 1617 1819 2021 22 23 24 25 2627 2829 3031
MODE3
MODE0
SCK
9F
SI
MSB
HIGH IMPENANCE
SO
8C
40
14
MSB
MSB
MSB
Figure 27: JEDEC Read-ID Sequence
Table 7: JEDEC Read-ID Data
Device ID
Manufacturer’s ID
(Byte 1)
Memory Type
(Byte 2)
Memory Capacity
(Byte 3)
8CH
40H
14H
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F25L08QA (2S)
Read-ID (RDID)
The Read-ID instruction (RDID) identifies the devices as
F25L08QA and manufacturer as ESMT. This command is
backward compatible to all ESMT SPI devices and should be
used as default device identification when multiple versions of
ESMT SPI devices are used in one design. The device
information can be read from executing an 8-bit command, 90H,
followed by address bits [A23 -A0]. Following the Read-ID
instruction, the manufacturer’s ID is located in address 000000H
and the device ID is located in address 000001H.
Once the device is in Read-ID mode, the manufacturer’s and
device ID output data toggles between address 000000H and
000001H until terminated by a low to high transition on CE .
CE
15 16
31 32
0
1
2
3
4
5
6
7
8
23 24
MSB
39 40
47 48
55 56
63
MODE3
SCK MODE0
SI
90
00
00
ADD1
MSB
HIGH
IMPENANCE
HIGH IMPENANCE
SO
8C
13
8C
13
MSB
Note: The Manufacture’s and Device IDoutput stream iscontinuous until terminated by a low to high transition on CE.
1. 00H will output the Manufacture’s ID first and 01H will output Device ID first before toggling between the two. .
Figure 28: Read ID Sequence
Table 8: Product ID Data
Address
Byte1
Byte2
8CH
13H
000000H
Device ID
Manufacturer’s ID
ESMT F25L08QA
13H
8CH
000001H
Device ID
Manufacturer’s ID
ESMT F25L08QA
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ESMT
F25L08QA (2S)
ELECTRICAL SPECIFICATIONS
Absolute Maximum Stress Ratings
(Applied conditions are greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the
operational sections of this datasheet is not implied. Exposure to absolute maximum stress rating conditions may affect device
reliability.)
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Output Short Circuit Current (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
( Note 1: Output shorted for no more than one second. No more than one output shorted at a time. )
TABLE 9: AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . . . . . CL = 15 pF for ≧75MHz
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .CL = 30 pF for ≦50MHz
See Figures 34 and 35
TABLE 10: OPERATING RANGE
Parameter
Symbol
VDD
Value
Unit
2.7 ~ 3.6
-40 ~ +85
Operating Supply Voltage
Ambient Operating Temperature
V
℃
TA
TABLE 11: DC OPERATING CHARACTERISTICS
Limits
Max
Symbol
Parameter
Test Condition
Min
Unit
Standard
Dual
Quad
Standard
Dual
Quad
Standard
Dual
Quad
9
10.5
12
10
12
13.5
15
16.5
18
Read Current
@ 33MHz
IDDR1
mA
mA
mA
CE =0.1 VDD/0.9 VDD, SO=open
Read Current
@ 50MHz
IDDR2
CE =0.1 VDD/0.9 VDD, SO=open
CE =0.1 VDD/0.9 VDD, SO=open
Read Current
@ 86MHz
IDDR3
Standard
Dual
Quad
22
23.5
25
Read Current
@ 100MHz
IDDR4
IDDW
IDDE
mA
mA
CE =0.1 VDD/0.9 VDD, SO=open
CE =VDD
Program and Write Status
Register Current
20
Sector and Block Erase Current
Chip Erase Current
20
20
25
10
mA
mA
µA
CE =VDD
CE =VDD
ISB1
ISB2
Standby Current
CE =VDD, VIN =VDD or VSS
CE =VDD, VIN =VDD or VSS
Deep Power Down Current
µA
ILI
ILO
VIL
VIH
VOL
VOH
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
1
1
µA VIN=GND to VDD, VDD=VDD Max
µA VOUT=GND to VDD, VDD=VDD Max
V
V
-0.5
0.7 x VDD
0.3 x VDD
VDD +0.4
0.4
V
V
IOL=1.6 mA
IOH=-100 µA
VDD-0.2
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ESMT
F25L08QA (2S)
TABLE 12: LATCH UP CHARACTERISTIC
Symbol
Parameter
Latch Up
Minimum
Unit
Test Method
JEDEC Standard 78
1
ILTH
100 + IDD
mA
Note 1: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 13: CAPACITANCE (TA = 25°C, f=1 MHz, other pins open)
Parameter
Description
Test Condition
VOUT = 0V
Maximum
8 pF
1
COUT
Output Pin Capacitance
Input Capacitance
1
CIN
VIN = 0V
6 pF
Note 1: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 14: AC OPERATING CHARACTERISTICS
Normal 33MHz Fast 50 MHz
Fast 86 MHz
Fast 100 MHz
Symbol
Parameter
Unit
Min
Max
Min
Max
Min
Max
Min
Max
FCLK
Serial Clock Frequency
33
50
86
100
MHz
ns
TSCKH
TSCKL
Serial Clock High Time
13
13
0.1
0.1
5
9
9
6
6
4
4
Serial Clock Low Time
ns
2
TCLCH
Clock Rise Time (Slew Rate)
Clock Fall Time (Slew Rate)
0.1
0.1
5
0.1
0.1
5
0.1
0.1
5
V/ns
V/ns
ns
2
TCHCL
1
TCES
CE Active Setup Time
CE Active Hold Time
CE Not Active Setup Time
CE Not Active Hold Time
CE Deselect Time
1
TCEH
5
5
5
5
ns
1
TCHS
5
5
5
5
ns
1
TCHH
5
5
5
5
ns
TCPH
TCHZ
TCLZ
TDS
10
10
10
10
ns
7
7
7
7
ns
CE High to High-Z Output
SCK Low to Low-Z Output
Data In Setup Time
0
2
1
5
5
5
5
0
2
1
5
5
5
5
0
2
1
5
5
5
5
0
2
1
5
5
5
5
ns
ns
TDH
Data In Hold Time
ns
THLS
THHS
THLH
THHH
ns
HOLD Low Setup Time
HOLD High Setup Time
HOLD Low Hold Time
ns
ns
ns
HOLD High Hold Time
HOLD Low to High-Z Output
HOLD High to Low-Z Output
3
THZ
8
8
8
8
8
8
8
8
ns
3
TLZ
ns
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F25L08QA (2S)
TABLE 14: AC OPERATING CHARACTERISTICS - Continued
Normal 33MHz Fast 50 MHz
Fast 86 MHz
Fast 100 MHz
Symbol
Parameter
Unit
Min
Max
Min
Max
Min
Max
Min
Max
TOH
TV
Output Hold from SCK Change
0
0
0
0
ns
ns
ns
ns
us
us
us
us
Output Valid from SCK
12
8
8
8
4
TWHSL
20
20
20
20
Write Protect Setup Time before CE Low
Write Protect Hold Time after CE High
CE High to Deep Power Down Mode
CE High to Standby Mode ( for DP)
CE High to Standby Mode (for RES)
CE High to next Instruction after Suspend
4
TSHWL
100
100
100
100
3
TDP
3
3
3
3
3
3
3
3
3
TRES1
3
TRES2
1.8
20
1.8
20
1.8
20
1.8
20
3
TSUS
Note:
1. Relative to SCK.
2. TSCKH + TSCKL must be less than or equal to 1/ FCLK
.
3. Value guaranteed by characterization, not 100% tested in production.
4. Only applicable as a constraint for a Write status Register instruction when Block- Protection-Look (BPL) bit is set at 1.
TABLE 15: ERASE AND PROGRAMMING PERFORMANCE
Limit
Unit
Parameter
Symbol
Typ2
Max3
250
1000
1.5
15
Sector Erase Time (4KB)
TSE
TBE1
TBE2
TCE
TW
90
ms
ms
Block Erase Time (32KB)
Block Erase Time (64KB)
Chip Erase Time
500
0.75
7
s
s
Write Status Register Time
Page Programming Time
Erase/Program Cycles1
Data Retention
10
15
ms
TPP
1.5
5
ms
100,000
20
-
Cycles
Years
-
Notes:
1. Not 100% Tested, Excludes external system level over head.
2. Typical values measured at 25°C, 3V.
3. Maximum values measured at 85°C, 2.7V.
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F25L08QA (2S)
Figure 29: Serial Input Timing Diagram
Figure 30: Serial Output Timing Diagram
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F25L08QA (2S)
CE
SCK
SO
SI
HOLD
Figure 31: HOLD Timing Diagram
WP
CE
TSHWL
TWHSL
SCK
SI
HIGH IMPENANCE
SO
Figure 32: Write Protect setup and hold timing during WRSR when BPL = 1
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F25L08QA (2S)
VDD
VDD (max)
Program, Erase and Write command is ignored
CE must track VDD
VDD (min)
Read command
is allowed
T
VSL
Device is fully
accessible
Reset
State
VWI
T
PUW
Time
Figure 33: Power-Up Timing Diagram
Table 16: Power-Up Timing and VWI Threshold
Unit
Parameter
Symbol
Min.
10
1
Max.
TVSL
TPUW
VWI
us
ms
V
VDD(min) to CE low
Time Delay before Write instruction
10
Write Inhibit Threshold Voltage
1
2.5
Note: These parameters are characterized only.
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F25L08QA (2S)
Input timing reference level
Output timing reference level
0.8VDD
0.2VDD
0.7VDD
0.3VDD
AC
Measurement
Level
0.5VDD
Note : Input pulse rise and fall time are <5ns
Figure 34: AC Input/Output Reference Waveforms
Figure 35: A Test Load Example
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F25L08QA (2S)
PACKAGING DIMENSIONS
8-LEAD
SOIC ( 150 mil )
8
5
GAUGE PLANE
L
DETAIL "X"
1
4
e
b
D
L1
"X"
SEATING PLANE
Dimension in mm
Dimension in inch
Dimension in mm
Dimension in inch
Symbol
Symbol
Min
1.35
0.10
1.25
0.33
0.19
5.80
Norm
1.60
Max
1.75
0.25
1.55
0.51
Min
Norm
0.063
0.006
0.057
0.016
Max
Min
Norm
4.90
Max
Min
Norm
0.193
Max
0.197
0.157
0.034
A
A1
A2
b
0.053
0.004
0.049
0.013
0.069
0.010
0.061
0.020
0.010
0.244
D
E
L
4.80
3.80
0.40
5.00
4.00
0.86
0.189
0.150
0.016
0.15
3.90
0.154
1.45
0.66
0.026
0.406
0.203
6.00
e
1.27 BSC
1.05
0.050 BSC
0.041
c
0.25 0.0075 0.008
6.20 0.228 0.236
1.00
1.10
0.039
0.043
L1
0
8
0
8
H
---
---
Controlling dimension : millimenter
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F25L08QA (2S)
PACKING DIMENSIONS
8-LEAD SOIC 200 mil ( official name – 208 mil )
θ
5
8
4
1
b
e
D
L
L1
SEATING PLANE
DETAIL "X"
Dimension in mm
Dimension in inch
Dimension in mm
Dimension in inch
Symbol
Symbol
Min
---
Norm
---
Max
2.16
0.25
1.91
0.51
0.25
5.33
Min
Norm
---
Max
Min
Norm
7.90
Max
Min
Norm
0.311
Max
0.319
0.212
0.032
A
A1
A2
b
---
0.085
0.010
0.075
0.020
0.010
0.210
E
E1
L
7.70
5.18
0.50
8.10
5.38
0.80
0.303
0.204
0.020
0.05
1.70
0.36
0.19
5.13
0.15
1.80
0.41
0.20
5.23
0.002
0.067
0.014
0.007
0.202
0.006
0.071
0.016
0.008
0.206
5.28
0.208
0.65
0.026
e
1.27 BSC
1.37
0.050 BSC
0.054
c
1.27
1.47
0.050
0.058
L1
0
8
0
8
D
---
---
Controlling dimension : millimenter
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F25L08QA (2S)
PACKING DIMENSIONS
8-CONTACT
WSON ( 6x5 mm )
D
PIN# 1
L
DETAIL : "B"
"A"
D2
DETAIL : "A"
"B"
PIN# 1
Symbol
Dimension in mm
Dimension in inch
Min
0.70
0.00
0.35
5.90
2.50
4.90
2.10
Norm
0.75
0.02
0.40
6.00
2.60
5.00
2.20
Max
0.80
0.05
0.45
6.10
2.70
5.10
2.30
Min
Norm
0.030
0.001
0.016
0.236
0.102
0.197
0.087
Max
A
A1
b
D
D2
E
E2
e
L
0.028
0.000
0.014
0.232
0.098
0.193
0.083
0.031
0.002
0.018
0.240
0.106
0.201
0.091
1.27 BSC
0.60
0.050 BSC
0.024
0.55
0.65
0.022
0.026
Controlling dimension : millimeter
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F25L08QA (2S)
Revision History
Revision
Date
Description
0.1
2011.09.30
Original
1.Add WSON package
0.2
2012.02.13
2.Modify the specification of TSE, TBE1, TBE2,TCE and TPP
1. Delete "Preliminary"
2. Modify Ambient Operating Temperature
1.0
2012.09.24
3. Correct the description of Block Protection and Block
Protection Lock-Down
1.1
1.2
Correct the description of Erase Suspend
2012.10.11
2013.11.29
1. Modify the figures of Read Sequence and Fast Read
Dual I/O Sequence ([M7 -M0] = AxH)
2. Correct max. value of TWHSL and TSHWL to min. value
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F25L08QA (2S)
Important Notice
All rights reserved.
No part of this document may be reproduced or duplicated in any form or
by any means without the prior permission of ESMT.
The contents contained in this document are believed to be accurate at
the time of publication. ESMT assumes no responsibility for any error in
this document, and reserves the right to change the products or
specification in this document without notice.
The information contained herein is presented only as a guide or
examples for the application of our products. No responsibility is
assumed by ESMT for any infringement of patents, copyrights, or other
intellectual property rights of third parties which may result from its use.
No license, either express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of ESMT or
others.
Any semiconductor devices may have inherently a certain rate of failure.
To minimize risks associated with customer's application, adequate
design and operating safeguards against injury, damage, or loss from
such failure, should be provided by the customer when making
application designs.
ESMT's products are not authorized for use in critical applications such
as, but not limited to, life support devices or system, where failure or
abnormal operation may directly affect human lives or cause physical
injury or property damage. If products described here are to be used for
such kinds of application, purchaser must do its own quality assurance
testing appropriate to such applications.
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