S1D13705F00A [EPSON]
LCD Controller ICs; LCD控制器IC
| 型号： | S1D13705F00A |
| 厂家： | 
EPSON COMPANY |
| 描述： | LCD Controller ICs |
| 文件： | 总94页 (文件大小：534K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MF1167-02
LCD Controller ICs
S1D13305 Series
Technical Manual
No part of this material may be reproduced or duplicated in any form or by any means without the written
permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.
Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this
material or due to its application or use in any product or circuit and, further, there is no representation that
this material is applicable to products requiring high level reliability, such as, medical products. Moreover,
no license to any intellectual property rights is granted by implication or otherwise, and there is no represen-
tation or warranty that anything made in accordance with this material will be free from any patent or
copyright infringement of a third party. This material or portions thereof may contain technology or the
subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of
Japan and may require an export license from the Ministry of International Trade and Industry or other
approval from another government agency.
✽ In this manual, Zilog's Z80-CPU or its equivalent shall be called Z80, Intel's 8085A or its equivalent shall
be called 8085 and Motorola's MC6809 and MC6802 or their equivalents shall be called 6809 and 6802,
respectively.
® stands for registered trade mark.
All other product names mentioned herein are trademarks and/or registered trademarks of their respec-
tive owners.
© Seiko Epson Corporation 2001 All rights reserved.
The information of the product number change
Starting April 1, 2001, the product number will be changed as listed below. To order from April 1,
2001 please use the new product number. For further information, please contact Epson sales
representative.
Configuration of product number
Devices
S1
D
13706
F
00A0
00
Packing specification
Specification
Package (B: CSP, F: QFP)
Corresponding model number
Model name (D: driver, digital products)
Product classification (S1: semiconductor)
Evaluation Board
S5U 13705 P00C
Specification
Corresponding model number (13705: for S1D13705)
Product classification (S5U: development tool for semiconductor)
Comparison table between new and previous number
• S1D13305 Series
• S1D1370x Series
• S1D1380x Series
Previous No.
New No.
Previous No.
New No.
Previous No.
New No.
SED1335 Series
SED1335D0A
SED1335F0A
SED1335F0B
S1D13305 Series
S1D13305D00A
S1D13305F00A
S1D13305F00B
SED137x Series
SED1374F0A
S1D1370x Series
S1D13704F00A
SED138x Series
SED1386F0A
S1D1380x Series
S1D13806F00A
SED1375F0A
S1D13705F00A
SED1376B0A
SED1376F0A
S1D13706B00A
S1D13706F00A
• S1D1350x Series
Previous No.
New No.
SED1378 Series
S1D13708 Series
SED135x Series
SED1353D0A
SED1353F0A
SED1353F1A
S1D1350x Series
S1D13503D00A
S1D13503F00A
S1D13503F01A
• S1D13A0x Series
Previous No.
New No.
SED13Ax Series
SED13A3F0A
SED13A3B0B
S1D13A0x Series
S1D13A03F00A
S1D13A03B00B
SED1354F0A
SED1354F1A
SED1354F2A
S1D13504F00A
S1D13504F01A
S1D13504F02A
SED13A4B0B
S1D13A04B00B
SED1355F0A
SED1356F0A
S1D13505F00A
S1D13506F00A
Comparison table between new and previous number of Evaluation Boards
• S1D1350x Series
• S1D1370x Series
• S1D1380x Series
Previous No.
SDU1353#0C
New No.
Previous No.
SDU1374#0C
New No.
Previous No.
SDU1386#0C
New No.
S5U13503P00C
S5U13704P00C
S5U13806P00C
SDU1354#0C
SDU1355#0C
SDU1356#0C
S5U13504P00C
S5U13505P00C
S5U13506P00C
SDU1375#0C
S5U13705P00C
SDU1376#0C
SDU1376BVR
S5U13706P00C
S5U13706B32R
SDU1378#0C
S5U13708P00C
• S1D13A0x Series
Previous No.
New No.
SDU13A3#0C
SDU13A4#0C
S5U13A03P00C
S5U13A04P00C
CONTENTS
CONTENTS
1. OVERVIEW ................................................................................................................................................................. 1
2. FEATURES ................................................................................................................................................................. 1
3. BLOCK DIAGRAM ....................................................................................................................................................... 2
4. PINOUTS ..................................................................................................................................................................... 3
5. PIN DESCRIPTION ..................................................................................................................................................... 4
5.1. S1D13305F00A/00B Pin Summary ................................................................................................................... 4
5.2. Pin Functions ..................................................................................................................................................... 5
5.2.1. Power supply ......................................................................................................................................... 5
5.2.2. Oscillator ................................................................................................................................................ 5
5.2.3. Microprocessor interface........................................................................................................................ 5
5.2.4. Display memory control ......................................................................................................................... 6
5.2.5. LCD drive signals ................................................................................................................................... 7
6. SPECIFICATIONS ....................................................................................................................................................... 7
6.1. Absolute Maximum Ratings ............................................................................................................................... 7
6.2. S1D13305 .......................................................................................................................................................... 8
6.3. S1D13305F Timing Diagrams .......................................................................................................................... 10
6.3.1. 8080 family interface timing ................................................................................................................. 10
6.3.2. 6800 family interface timing ................................................................................................................. 11
6.3.3. Display memory read timing ................................................................................................................ 12
6.3.4. Display memory write timing ................................................................................................................ 13
6.3.5. SLEEP IN command timing ................................................................................................................. 15
6.3.6. External oscillator signal timing............................................................................................................ 16
6.3.7. LCD output timing ................................................................................................................................ 17
7. PACKAGE DIMENSIONS ......................................................................................................................................... 19
7.1. S1D13305F00A ............................................................................................................................................... 19
7.2. S1D13305F00B ............................................................................................................................................... 19
8. INSTRUCTION SET .................................................................................................................................................. 20
8.1. The Command Set ........................................................................................................................................... 20
8.2. System Control Commands ............................................................................................................................. 21
8.2.1. SYSTEM SET ...................................................................................................................................... 21
8.2.1.1. C ........................................................................................................................................... 21
8.2.1.2. M0 ......................................................................................................................................... 21
8.2.1.3. M1 ......................................................................................................................................... 21
8.2.1.4. M2 ......................................................................................................................................... 22
8.2.1.5. W/S ....................................................................................................................................... 22
8.2.1.6. IV .......................................................................................................................................... 23
8.2.1.7. FX ......................................................................................................................................... 24
8.2.1.8. WF ........................................................................................................................................ 25
8.2.1.9. FY ......................................................................................................................................... 25
8.2.1.10. C/R ....................................................................................................................................... 25
8.2.1.11. TC/R ..................................................................................................................................... 26
8.2.1.12. L/F ........................................................................................................................................ 26
8.2.1.13. AP ......................................................................................................................................... 27
8.2.2. SLEEP IN ............................................................................................................................................. 27
8.3. Display Control Commands ............................................................................................................................. 28
8.3.1. DISP ON/OFF ...................................................................................................................................... 28
8.3.1.1. D ........................................................................................................................................... 28
8.3.1.2. FC ......................................................................................................................................... 28
8.3.1.3. FP ......................................................................................................................................... 28
8.3.2. SCROLL............................................................................................................................................... 29
8.3.2.1. C ........................................................................................................................................... 29
8.3.2.2. SL1, SL2 ............................................................................................................................... 30
S1D13305 Series
Technical Manual
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CONTENTS
8.3.3. CSRFORM ........................................................................................................................................... 34
8.3.3.1. CRX ...................................................................................................................................... 34
8.3.3.2. CRY ...................................................................................................................................... 34
8.3.3.3. CM ........................................................................................................................................ 34
8.3.4. CSRDIR ............................................................................................................................................... 34
8.3.5. OVLAY ................................................................................................................................................. 35
8.3.5.1. MX0, MX1 ............................................................................................................................. 35
8.3.5.2. DM1, DM2 ............................................................................................................................ 36
8.3.5.3. OV ........................................................................................................................................ 36
8.3.6. CGRAM ADR ....................................................................................................................................... 36
8.3.7. HDOT SCR .......................................................................................................................................... 37
8.3.7.1. D0 to D2 ............................................................................................................................... 37
8.4. Drawing Control Commands ............................................................................................................................ 37
8.4.1. CSRW .................................................................................................................................................. 37
8.4.2. CSRR ................................................................................................................................................... 38
8.5. Memory Control Commands ............................................................................................................................ 38
8.5.1. MWRITE .............................................................................................................................................. 38
8.5.2 MREAD ................................................................................................................................................ 39
9. DISPLAY CONTROL FUNCTIONS ........................................................................................................................... 40
9.1. Character Configuration ................................................................................................................................... 40
9.2. Screen Configuration ....................................................................................................................................... 42
9.2.1. Screen configuration ............................................................................................................................ 42
9.2.2. Display address scanning .................................................................................................................... 42
9.2.3. Display scan timing .............................................................................................................................. 45
9.3. Cursor Control .................................................................................................................................................. 46
9.3.1. Cursor register function........................................................................................................................ 46
9.3.2. Cursor movement ................................................................................................................................ 46
9.3.3. Cursor display layers ........................................................................................................................... 46
9.4. Memory to Display Relationship ...................................................................................................................... 48
9.5. Scrolling ........................................................................................................................................................... 51
9.5.1. On-page scrolling ................................................................................................................................. 51
9.5.2. Inter-page scrolling .............................................................................................................................. 51
9.5.3. Horizontal scrolling............................................................................................................................... 52
9.5.4. Bidirectional scrolling ........................................................................................................................... 53
9.5.5. Scroll units ........................................................................................................................................... 53
10. CHARACTER GENERATOR .................................................................................................................................... 54
10.1. CG Characteristics ........................................................................................................................................... 54
10.1.1. Internal character generator................................................................................................................. 54
10.1.2. External character generator ROM ...................................................................................................... 54
10.1.3. Character generator RAM .................................................................................................................... 54
10.2. CG Memory Allocation ..................................................................................................................................... 55
10.3. Setting the Character Generator Address ........................................................................................................ 56
10.3.1. M1 = 1 .................................................................................................................................................. 56
10.3.2. CG RAM addressing example ............................................................................................................. 57
10.4. Character Codes .............................................................................................................................................. 58
11. MICROPROCESSOR INTERFACE .......................................................................................................................... 59
11.1. System Bus Interface ....................................................................................................................................... 59
11.1.1. 8080 series .......................................................................................................................................... 59
11.1.2. 6800 series .......................................................................................................................................... 59
11.2. Microprocessor Synchronization ...................................................................................................................... 59
11.2.1. Display status indication output ........................................................................................................... 59
11.2.2. Internal register access ........................................................................................................................ 59
11.2.3. Display memory access ....................................................................................................................... 59
11.3. Interface Examples .......................................................................................................................................... 61
11.3.1. Z80 to S1D13305 series interface ....................................................................................................... 61
11.3.2. 6802 to S1D13305 series interface...................................................................................................... 61
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S1D13305 Series
Technical Manual
CONTENTS
12. DISPLAY MEMORY INTERFACE ............................................................................................................................. 62
12.1. Static RAM ....................................................................................................................................................... 62
12.2. Supply Current during Display Memory Access ............................................................................................... 63
13. OSCILLATOR CIRCUIT ............................................................................................................................................ 63
14. STATUS FLAG .......................................................................................................................................................... 63
15. RESET ....................................................................................................................................................................... 65
16. APPLICATION NOTES ............................................................................................................................................. 65
16.1. Initialization Parameters ................................................................................................................................... 65
16.1.1. SYSTEM SET instruction and parameters........................................................................................... 65
16.1.2. Initialization example............................................................................................................................ 66
16.1.3. Display mode setting example 1: combining text and graphics .......................................................... 72
16.1.4. Display mode setting example 2: combining graphics and graphics .................................................. 73
16.1.5. Display mode setting example 3: combining three graphics layers .................................................... 75
16.2. System Overview ............................................................................................................................................. 76
16.3 System Interconnection ................................................................................................................................... 77
16.3.1. S1D13305F .......................................................................................................................................... 77
16.4. Smooth Horizontal Scrolling ............................................................................................................................. 79
16.5. Layered Display Attributes ............................................................................................................................... 80
16.5.1. Inverse display ..................................................................................................................................... 80
16.5.2. Half-tone display .................................................................................................................................. 80
16.5.2.1. Menu pad display ................................................................................................................. 80
16.5.2.2. Graph display ....................................................................................................................... 81
16.5.3. Flashing areas ..................................................................................................................................... 81
16.5.3.1. Small area ............................................................................................................................ 81
16.5.3.2. Large area ............................................................................................................................ 81
16.6. 16 × 16-dot Graphic Display............................................................................................................................. 81
16.6.1. Command usage.................................................................................................................................. 81
16.6.2. Kanji character display ......................................................................................................................... 81
17. INTERNAL CHARACTER GENERATOR FONT ....................................................................................................... 84
18. GLOSSARY OF TERMS ........................................................................................................................................... 85
Request for Information on S1D13305 Series ................................................................................................................. 86
S1D13305 Series
Technical Manual
EPSON
iii
OVERVIEW/FEATURES
1. OVERVIEW
2. FEATURES
The S1D13305 series is a controller IC that can display
•
Text, graphics and combined text/graphics display
text and graphics on LCD panel.
modes
The S1D13305 series can display layered text and graph-
ics, scroll the display in any direction and partition the
display into multiple screens.
The S1D13305 series stores text, character codes and bit-
mapped graphics data in external frame buffer memory.
Display controller functions include transferring data
from the controlling microprocessor to the buffer memory,
reading memory data, converting data to display pixels
and generating timing signals for the buffer memory,
LCD panel.
The S1D13305 series has an internal character generator
with 160, 5 × 7 pixel characters in internal mask ROM.
The character generators support up to 64, 8 × 16 pixel
characters in external character generator RAM and up to
256, 8 × 16 pixel characters in external character genera-
tor ROM.
•
•
•
•
Three overlapping screens in graphics mode
Up to 640 × 256 pixel LCD panel display resolution
Programmable cursor control
Smooth horizontal and vertical scrolling of all or part
of the display
1/2-duty to 1/256-duty LCD drive
Up to 640 × 256 pixel LCD panel display resolution
memory
160, 5 × 7 pixel characters in internal mask-program-
med character generator ROM
•
•
•
•
•
Up to 64, 8 × 16 pixel characters in external character
generator RAM
Up to 256, 8 × 16 pixel characters in external character
generator ROM
6800 and 8080 family microprocessor interfaces
Low power consumption—3.5 mA operating current
(VDD = 3.5V), 0.05 µA standby current
Package
•
•
•
•
line-up
Package
QFP5-60 pin
QFP6-60 pin
S1D13305F00A
S1D13305F00B
2.7 to 5.5 V (S1D13305F)
S1D13305 Series
Technical Manual
EPSON
1
BLOCK DIAGRAM
3. BLOCK DIAGRAM
Video RAM
Character
LCD
Character
Generator RAM
Generator ROM
VRD, VWR (S1D13305F)
Input/Output
Register
Video RAM Interface
LCD Controller
Cursor
Address
Controller
Display
Address
Controller
Character
Generator
ROM
Refresh
Counter
Layered
Controller
Dot Counter
Microprocessor Interface
Oscillator
XG
XD
2
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S1D13305 Series
Technical Manual
PINOUTS
4. PINOUTS
◊
S1D13305F00A
◊
S1D13305F00B
45
46
31
VD3
VD2
VD1
VD0
VA15
VA14
VA13
VA12
VA11
VA10
VA9
XD3
30
D7
D6
D5
D4
D3
D2
D1
D0
XD
CS
A0
DD
D0
D1
VA8
50
45
40
VA9
VA10
VA11
VA12
VA13
V
S1D13305F00A
60
1
30
29
S1D13305F00B
Index
D2
D3
D4
D5
D6
NC
Index
V
DD
VA14
VA15
VD0
VD1
VD2
A0
VA8
CS
XD
5
VA7
6
10
15
20
VA6
XG
SEL1
60
1
16
15
NC
S1D13305 Series
Technical Manual
EPSON
3
PIN DESCRIPTION
5. PIN DESCRIPTION
5.1. S1D13305F00A/00B Pin Summary
Number
Name
Type
Description
S1D13305F00A S1D13305F00B
27 to 28
30 to 43
1 to 6
50 to 59
VA0 to VA15
Output
VRAM address bus
VWR
VCE
VRD
RES
NC
44
45
7
Output
Output
Output
Input
—
VRAM write signal
Memory control signal
VRAM read signal
Reset
8
46
9
10
47
28, 48, 49
11, 12, 60
No connection
8080 family: Read signal
6800 family: Enable clock (E)
RD
50
51
52
53
13
14
15
16
Input
Input
Input
Input
8080 family: Write signal
6800 family: R/W signal
WR
8080 or 6800 family interface
select
SEL2
SEL1
8080 or 6800 family interface
select
XG
XD
CS
A0
54
55
56
57
58
17
18
19
20
21
Input
Output
Input
Oscillator connection
Oscillator connection
Chip select
Input
Data type select
2.7 to 5.5V supply
VDD
Supply
59 to 60
1 to 6
D0 to D7
22 to 29
Input/output Data bus
XD0 to XD3
XECL
XSCL
VSS
7 to 10
11
30 to 33
34
Output
Output
Output
Supply
Output
Output
X-driver data
X-driver enable chain clock
X-driver data shift clock
Ground
12
35
13
36
LP
14
37
Latch pulse
WF
15
38
Frame signal
Power-down signal when display is
blanked
YDIS
16
39
Output
YD
17
18
40
41
Output
Output
Scan start pulse
YSCL
Y-driver shift clock
VD0 to VD7
19 to 26
42 to 49
Input/output VRAM data bus
4
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S1D13305 Series
Technical Manual
PIN DESCRIPTION
5.2. Pin Functions
5.2.1. Power supply
Pin Name
Function
2.7 to 5.5V supply.
This may be the same supply as the controlling microprocessor.
VDD
VSS
Ground
Note: The peak supply current drawn by the S1D13305 series may be up to ten times the average supply current. The power
supply impedance must be kept as low as possible by ensuring that supply lines are sufficiently wide and by placing 0.47 µF
decoupling capacitors that have good high-frequency response near the device’s supply pins.
5.2.2. Oscillator
Pin Name
Function
Crystalconnectionforinternaloscillator(Seesection13). Thispincanbedrivenbyanexternal
clock source that satisfies the timing specifications of the EXT φ0 signal (See section 6.3.6).
XG
Crystal connection for internal oscillator. Leave this pin open when using an external clock
source.
XD
5.2.3. Microprocessor interface
Pin Name
Function
D0 to D7
Tristate input/output pins. Connect these pins to an 8- or 16-bit microprocessor bus.
Microprocessor interface select pin. The S1D13305 series supports both 8080 family
processors (such as the 8085 and Z80®) and 6800 family processors (such as the 6802
and 6809).
SEL1, SEL2
SEL1
SEL2*
Interface
8080 family
6800 family
A0
A0
A0
RD
RD
E
WR
WR
R/W
CS
CS
CS
0
1
0
0
Note: SEL1 should be tied directly to VDD or VSS to prevent noise. If noise does appear on SEL1, decouple it to ground using a
capacitor placed as close to the pin as possible.
S1D13305 Series
Technical Manual
EPSON
5
PIN DESCRIPTION
Pin Name
Function
8080 family interface
A0
0
RD
0
WR
1
Function
Status flag read
1
0
1
Display data and cursor address read
Display data and parameter write
Command write
0
1
0
1
1
0
A0
6800 family interface
A0
0
R/W
E
1
1
1
1
Function
Status flag read
1
1
0
0
1
Display data and cursor address read
Display data and parameter write
Command write
0
1
When the 8080 family interface is selected, this signal acts as the active-LOW read strobe. The
S1D13305 series output buffers are enabled when this signal is active.
RD or E
When the 6800 family interface is selected, this signal acts as the active-HIGH enable clock.
Data is read from or written to the S1D13305 series when this clock goes HIGH.
Whenthe8080familyinterfaceisselected, thissignalactsastheactive-LOWwritestrobe. The
bus data is latched on the rising edge of this signal.
WR or R/W
Whenthe6800familyinterfaceisselected,thissignalactsastheread/writecontrolsignal.Data
is read from the S1D13305 series if this signal is HIGH, and written to the S1D13305 series if
it is LOW.
Chip select. This active-LOW input enables the S1D13305 series. It is usually connected
to the output of an address decoder device that maps the S1D13305 series into the memory
space of the controlling microprocessor.
CS
This active-LOW input performs a hardware reset on the S1D13305 series. It is a
Schmitt-trigger input for enhanced noise immunity; however, care should be taken to ensure
that it is not triggered if the supply voltage is lowered.
RES
5.2.4. Display memory control
The S1D13305 series can directly access static RAM and
PROM. The designer may use a mixture of these two
types of memory to achieve an optimum trade-off be-
tween low cost and low power consumption.
Pin Name
Function
16-bit display memory address. When accessing character generator RAM or ROM, VA0 to
VA3, reflect the lower 4 bits of the S1D13305 series’s row counter.
VA0 to VA15
VD0 to VD7 8-bit tristate display memory data bus. These pins are enabled when VR/W is LOW.
VWR
VRD
VCE
Active-LOW display memory write control output.
Active-LOW display memory read control output.
Active-LOW static memory standby control signal. VCE can be used with CS.
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S1D13305 Series
Technical Manual
PIN DESCRIPTION/SPECIFICATIONS
5.2.5. LCD drive signals
In order to provide effective low-power drive for LCD
matrixes, the S1D13305 series can directly control both
the X- and Y-drivers using an enable chain.
Pin Name
Function
4-bit X-driver (column drive) data outputs. Connect these outputs to the inputs of the X-driver
chips.
XD0 to XD3
The falling edge of XSCL latches the data on XD0 to XD3 into the input shift registers of the
X-drivers. To conserve power, this clock halts between LP and the start of the following display
line (See section 6.3.7).
XSCL
The falling edge of XECL triggers the enable chain cascade for the X-drivers.
Every 16th clock pulse is output to the next X-driver.
XECL
LP latches the signal in the X-driver shift registers into the output data latches. LP is a falling-
edge triggered signal, and pulses once every display line.
LP
Connect LP to the Y-driver shift clock on modules.
LCD panel AC drive output. The WF period is selected to be one of two values with SYSTEM
SET command.
WF
The falling edge of YSCL latches the data on YD into the input shift registers of the
Y-drivers. YSCL is not used with driver ICs which use LP as the Y-driver shift clock.
YSCL
YD is the data pulse output for the Y drivers. It is active during the last line of each frame, and
is shifted through the Y drivers one by one (by YSCL), to scan the display’s common
connections.
YD
Power-down output signal. YDIS is HIGH while the display drive outputs are active.
YDIS goes LOW one or two frames after the sleep command is written to the S1D13305
series. All Y-driver outputs are forced to an intermediate level (de-selecting the display
segments) to blank the display. In order to implement power-down operation in the LCD unit,
the LCD power drive supplies must also be disabled when the display is disabled by YDIS.
YDIS
6. SPECIFICATIONS
6.1. Absolute Maximum Ratings
Parameter
Supply voltage range
Symbol
Rating
–0.3 to 7.0
–0.3 to VDD + 0.3
300
Unit
V
VDD
Input voltage range
VIN
V
Power dissipation
PD
mW
°C
°C
°C
Operating temperature range
Storage temperature range
Soldering temperature (10 seconds). See note 1.
T
opg
stg
solder
–20 to 75
–65 to 150
260
T
T
Notes:
1. The humidity resistance of the flat package may be reduced if the package is immersed in solder. Use a soldering technique
that does not heatstress the package.
2. If the power supply has a high impedance, a large voltage differential can occur between the input and supply voltages. Take
appropriate care with the power supply and the layout of the supply lines. (See section 6.2.)
3. All supply voltages are referenced to VSS = 0V.
S1D13305 Series
Technical Manual
EPSON
7
SPECIFICATIONS
6.2. S1D13305
V
DD = 4.5 to 5.5V, VSS = 0V, T
a
= –20 to 75°C
Rating
Typ.
5.0
Parameter
Symbol
Condition
Unit
Min.
4.5
2.0
—
Max.
5.5
6.0
2.0
5.0
15
Supply voltage
V
DD
OH
V
V
Register data retention voltage
Input leakage current
V
—
I
LI
LO
opr
V
V
I
I
= VDD. See note 5.
= VSS. See note 5.
0.05
0.10
11
µA
µA
mA
Output leakage current
Operating supply current
I
—
I
See note 4.
—
Sleep mode,
VOSC1 = VCS = VRD = VDD
Quiescent supply current
IQ
—
0.05
20.0
µA
Oscillator frequency
External clock frequency
Oscillator feedback resistance
TTL
f
OSC
CL
1.0
1.0
0.5
—
—
10.0
10.0
3.0
MHz
MHz
MΩ
Measured at crystal,
47.5% duty cycle.
See note 6.
f
Rf
1.0
HIGH-level input voltage
LOW-level input voltage
V
IHT
See note 1.
See note 1.
0.5VDD
—
—
V
DD
V
V
V
ILT
VSS
0.2VDD
I
OH = –5.0 mA.
See note 1.
OL = 5.0 mA. See note 1.
HIGH-level output voltage
V
OHT
2.4
—
—
—
—
V
V
LOW-level output voltage
CMOS
V
OLT
I
VSS + 0.4
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
Open-drain
V
IHC
ILC
OHC
See note 2.
See note 2.
0.8VDD
—
—
—
—
V
DD
V
V
V
V
V
VSS
0.2VDD
—
V
I
I
OH = –2.0 mA. See note 2.
OH = 1.6 mA. See note 2.
VDD – 0.4
V
V
OLC
OLN
—
V
SS + 0.4
LOW-level output voltage
Schmitt-trigger
IOL = 6.0 mA.
—
—
V
SS + 0.4
V
Rising-edge threshold voltage
Falling-edge threshold voltage
Notes:
V
T+
T–
See note 3.
See note 3.
0.5VDD 0.7VDD 0.8VDD
0.2VDD 0.3VDD 0.5VDD
V
V
V
1. D0 to D7, A0, CS, RD, WR, VD0 to VD7, VA0 to VA15, VRD, VWR and VCE are TTL-level inputs.
2. SEL1 is CMOS-level inputs. YD, XD0 to XD3, XSCL, LP, WF, YDIS are CMOS-level outputs.
3. RES is a Schmitt-trigger input. The pulsewidth on RES must be at least 200 µs. Note that pulses of more than a few seconds
will cause DC voltages to be applied to the LCD panel.
4.
fOSC = 10 MHz, no load (no display memory), internal character generator, 256 × 200 pixel display. The operating
supply current can be reduced by approximately 1 mA by setting both CLO and the display OFF.
5. VD0 to VD7 and D0 to D7 have internal feedback circuits so that if the inputs become high-impedance, the input
state immediately prior to that is held. Because of the feedback circuit, input current flow occurs when the
inputs are in an intermediate state.
6. Because the oscillator circuit input bias current is in the order of µA, design the printed circuit board so as to
reduce leakage currents.
8
EPSON
S1D13305 Series
Technical Manual
SPECIFICATIONS
VDD = 2.7 to 4.5 V, VSS = 0 V, Ta = –20 to 75˚C unless otherwise noted
Rating
Typ.
3.5
Parameter
Supply voltage
Symbol
Condition
Unit
Min.
2.7
2.0
—
Max.
VDD
VOH
ILI
4.5
6.0
2.0
5.0
—
V
V
Register data retention voltage
Input leakage current
—
VI = VDD. See note 5.
VI = VSS. See note 5.
VDD = 3.5 V. See note 4.
See note 4.
0.05
0.10
3.5
µA
µA
Output leakage current
ILO
—
—
Operating supply current
Quiescent supply current
Iopr
IQ
mA
—
—
7.0
Sleep mode,
VOSC1 = VCS = VRD = VDD
—
0.05
20.0
µA
Oscillator frequency
fOSC
fCL
1.0
1.0
0.7
—
—
—
8.0
8.0
3.0
MHz
MHz
MΩ
Measured at crystal,
47.5% duty cycle.
See note 6.
External clock frequency
Oscillator feedback resistance
TTL
Rf
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
CMOS
VIHT
VILT
See note 1.
0.5 VDD
VSS
—
—
—
—
VDD
0.2 VDD
—
V
V
V
V
See note 1.
VOHT
VOLT
IOH = –3.0 mA. See note 1.
IOL = 3.0 mA. See note 1.
2.4
—
VSS + 0.4
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
Open-drain
VIHC
VILC
See note 2.
See note 2.
0.8 VDD
VSS
—
—
—
—
VDD
0.2 VDD
—
V
V
V
V
VOHC
VOLC
IOH = –2.0 mA. See note 2. VDD – 0.4
IOH = 1.6 mA. See note 2.
IOL = 6.0 mA.
—
VSS + 0.4
LOW-level output voltage
Schmitt-trigger
VOLN
—
—
VSS + 0.4
V
Rising-edge threshold voltage
Falling-edge threshold voltage
VT+
VT–
See note 3.
See note 3.
0.5 VDD
0.2 VDD
0.7 VDD
0.3 VDD
0.8 VDD
0.5 VDD
V
V
Notes
1. D0 to D7, A0, CS, RD, WR, VD0 to VD7, VA0 to VA15, VRD, VWR and VCE are TTL-level inputs.
2. SEL1 is CMOS-level inputs. YD, XD0 to XD3, XSCL, LP, WF, YDIS are CMOS-level outputs.
3. RES is a Schmitt-trigger input. The pulsewidth on RES must be at least 200 µs. Note that pulses of more than a few seconds will
cause DC voltages to be applied to the LCD panel.
4. fOSC = 10 MHz, no load (no display memory), internal character generator, 256 × 200 pixel display. The operating supply current can
be reduced by approximately 1 mA by setting both CLO and the display OFF.
5. VD0 to VD7 and D0 to D7 have internal feedback circuits so that if the inputs become high-impedance, the input state immediately
prior to that is held. Because of the feedback circuit, input current flow occurs when the inputs are in an intermediate state.
6. Because the oscillator circuit input bias current is in the order of µA, design the printed circuit board so as to reduce leakage currents.
S1D13305 Series
Technical Manual
EPSON
9
SPECIFICATIONS
6.3. S1D13305F Timing Diagrams
6.3.1. 8080 family interface timing
AO, CS
tAW8
tAH8
tCYC8
WR, RD
tCC
tDH8
tDS8
D0 to D7
(Write)
tACC8
tOH8
D0 to D7
(Read)
Ta
= –20 to 75°C
V
DD = 4.5 to 5.5V VDD = 2.7 to 4.5V
Signal Symbol
Parameter
Unit
Condition
Min.
10
0
Max.
—
Min.
10
Max.
—
t
AH8
AW8
CYC8
CC
Address hold time
Address setup time
System cycle time
Strobe pulsewidth
Data setup time
ns
ns
ns
ns
ns
ns
ns
ns
A0, CS
t
—
0
—
See note.
120
120
5
See note.
t
—
—
WR, RD
t
—
150
120
5
—
CL = 100pF
tDS8
—
—
t
DH8
Data hold time
—
—
D0 to D7
tACC8
RD access time
—
50
50
—
80
55
tOH8
Output disable time
10
10
Note: For memory control and system control commands:
= 2t + t + t + 75 > t + 245
t
CYC8
C
CC
CEA
ACV
For all other commands:
= 4t + t + 30
t
CYC8
C
CC
10
EPSON
S1D13305 Series
Technical Manual
SPECIFICATIONS
6.3.2. 6800 family interface timing
E
tCYC6
tAW6
tEW
R/W
tAH6
A0, CS
tDH6
tDS6
D0 to D7
(Write)
tACC6
tOH6
D0 to D7
(Read)
Note: tCYC6 indicates the interval during which CS is LOW and E is HIGH.
T
a
= –20 to 75°C
V
DD = 4.5 to 5.5V VDD = 2.7 to 4.5V
Signal Symbol
Parameter
Unit
Condition
Min.
Max.
—
Min.
See note.
10
Max.
—
t
CYC6
System cycle time
Address setup time
Address hold time
Data setup time
Data hold time
See note.
ns
ns
ns
ns
ns
ns
ns
ns
A0,
CS,
R/W
t
AW6
0
0
—
—
t
AH6
DS6
DH6
OH6
—
0
—
t
t
100
0
—
120
0
—
CL =
100 pF
—
—
D0 to D7
E
t
Output disable time
Access time
10
—
120
50
85
—
10
75
130
—
tACC6
—
t
EW
Enable pulsewidth
150
Note: For memory control and system control commands:
= 2t + t + t + 75 > t + 245
t
CYC6
C
EW
CEA
ACV
For all other commands:
= 4t + t + 30
t
CYC6
C
EW
S1D13305 Series
Technical Manual
EPSON
11
SPECIFICATIONS
6.3.3. Display memory read timing
EXTΦ0
tC
tW
tCE
tW
VCE
tCYR
VA0 to VA15
tASC
tAHC
tRCH
VR/W
tRCS
tCEA
tCE3
tOH2
tACV
VD0 to VD7
Ta
= –20 to 75°C
V
DD = 4.5 to 5.5V VDD = 2.7 to 4.5V
Signal Symbol
Parameter
Clock period
Unit
Condition
Min.
Max.
Min.
Max.
EXT φ0
tC
100
—
125
—
ns
ns
VCE HIGH-level
pulsewidth
tW
tC
– 50
—
tC
– 50
—
VCE
VCE LOW-level
pulsewidth
t
2t – 30
—
—
—
2t – 30
—
—
—
ns
ns
ns
CE
C
C
t
CYR
ASC
Read cycle time
3t
C
3t
C
Address setup time to
falling edge of VCE
VA0 to
VA15
t
tC
– 70
tC
– 100
CL = 100
pF
Address hold time from
falling edge of VCE
t
AHC
RCS
2t – 30
—
—
—
2t – 40
—
—
—
ns
ns
ns
C
C
Read cycle setup time to
falling edge of VCE
t
tC
– 45
tC – 60
VRD
Read cycle hold time
from rising edge of VCE
tRCH
0.5t
C
0.5tC
t
t
t
ACV
CEA
OH2
Address access time
VCE access time
—
—
0
3t
C
– 100
– 80
—
—
0
3t
C
– 115
ns
ns
ns
ns
2t
C
2t
C – 90
VD0 to
VD7
Output data hold time
VCE to data off time
—
—
t
CE3
0
—
0
—
12
EPSON
S1D13305 Series
Technical Manual
SPECIFICATIONS
6.3.4. Display memory write timing
tC
EXT φ O
tW
tCE
VCE
tASC
tCA
tAHC
VA0 to VA15
tAS tWSC
tWHC
tAH2
VR/W
tDH2
tDSC
tDHC
VD0 to VD7
S1D13305 Series
Technical Manual
EPSON
13
SPECIFICATIONS
T
a
= –20 to 75°C
V
DD = 4.5 to 5.5V VDD = 2.7 to 4.5V
Signal Symbol
Parameter
Clock period
Unit
Condition
Min.
Max.
Min.
Max.
EXT φ0
t
C
100
—
125
—
ns
ns
VCE HIGH-level
pulsewidth
t
W
tC
– 50
—
t
C
– 50
– 30
—
VCE
VCE LOW-level
pulsewidth
t
CE
2t
C
– 30
—
—
—
2t
C
—
—
—
ns
ns
ns
tCYW
Write cycle time
3t
C
3t
C
Address hold time from
falling edge of VCE
tAHC
2t
C
– 30
2t
C
– 40
Address setup time to
falling edge of VCE
t
ASC
t
– 70
0
—
—
—
—
—
—
—
—
50
t
– 110
0
—
—
—
—
—
—
—
—
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
C
VA0 to
VA15
Address hold time from
rising edge of VCE
t
CA
AS
CL = 100
pF
Address setup time to
falling edge of VWR
t
0
0
Address hold time from
rising edge of VWR
t
AH2
10
10
Write setup time to
falling edge of VCE
t
WSC
WHC
tC
– 80
tC
– 115
VWR
Write hold time from
falling edge of VCE
t
2t – 20
2t – 20
C
C
Data input setup time to
falling edge of VCE
tDSC
tC
– 85
tC – 125
VD0 to
VD7
Data input hold time
from falling edge of VCE
t
DHC
2t – 30
2t – 30
C
C
Data hold time from
rising edge of VWR
t
DH2
5
5
Note: VD0 to VD7 are latching input/outputs. While the bus is high impedance, VD0 to VD7 retain the write data until the data read
from the memory is placed on the bus.
14
EPSON
S1D13305 Series
Technical Manual
SPECIFICATIONS
6.3.5. SLEEP IN command timing
VCE
SLEEP IN write
SYSTEM SET write
tWRL
tWRD
WR
(Command input)
YDIS
T
a
= –20 to 75°C
V
DD = 4.5 to 5.5V VDD = 2.7 to 4.5V
Signal Symbol
Parameter
Unit
ns
Condition
Min.
Max.
Min.
Max.
VCE falling-edge delay
time
See note 1.
See note 1.
t
WRD
—
—
CL = 100
pF
WR
YDIS falling-edge delay
time
See note 2.
See note 2.
tWRL
—
—
ns
Notes:
1. t
2. t
= 18t + t
+ 40 (t is the time delay from the sleep state until stable operation)
OSS
WRD
WRL
C
OSS
= 36t × [TC/R] × [L/F] + 70
C
S1D13305 Series
Technical Manual
EPSON
15
SPECIFICATIONS
6.3.6. External oscillator signal timing
tRCL
tFCL
EXTφ0
tWL
tWH
tC
Ta
= –20 to 75°C
V
DD = 4.5 to 5.5V VDD = 2.7 to 4.5V
Signal Symbol
Parameter
Unit
Condition
Min.
—
Max.
15
Min.
—
Max
15
tRCL
External clock rise time
External clock fall time
ns
ns
tFCL
—
15
—
15
External clock
HIGH-level pulsewidth
See note 1. See note 2. See note 1. See note 2.
tWH
ns
EXT φ0
External clock
LOW-level pulsewidth
See note 1. See note 2. See note 1. See note 2.
t
WL
ns
ns
tC
External clock period
100
—
125
—
Notes:
1.
475
(t
(t
C
C
– tRCL – tFCL) ×
– tRCL – tFCL) ×
< tWH, tWL
1000
2.
525
> tWH, tWL
1000
16
EPSON
S1D13305 Series
Technical Manual
SPECIFICATIONS
6.3.7. LCD output timing
The following characteristics are for a 1/64 duty cycle.
Row
LP
62
63 64
1
2
3
4
60 61 62 63
64
1 frame time
YD
WF
WF
1 line time
Row 1
Row 64
Row 2
LP
XSCL
(14) (15) (16)
(1)
(15)(16)(1)(2)(3)
(15)(16)
(1)
XD0 to XD3
t
CX
t
r
t
WX
tf
XSCL
t
DS
tDH
t
LS
XD0 to XD3
LP
t
WL
t
LD
t
DHY
t
DF
WF(B)
YD
S1D13305 Series
Technical Manual
EPSON
17
SPECIFICATIONS
T
a
= –20 to 75°C
V
DD = 4.5 to 5.5V VDD = 2.7 to 4.5V
Signal Symbol
Parameter
Rise time
Unit
Condition
Min.
—
Max.
30
30
—
Min.
—
Max
40
40
—
t
r
f
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Fall time
—
—
t
CX
Shift clock cycle time
XSCL clock pulsewidth
X data hold time
4t
C
4tC
XSCL
t
WX
2t
C
C
– 60
– 50
– 100
– 50
– 80
0
—
2t
C
C
– 60
– 50
– 105
– 50
– 120
0
—
t
DH
2t
—
2t
—
XD0 to
XD3
CL =
100 pF
t
DS
X data setup time
Latch data setup time
LP pulsewidth
2t
C
—
2t
2t
4t
C
—
tLS
2t
C
C
—
C
—
LP
t
WL
4t
—
C
—
t
LD
LP delay time from XSCL
Permitted WF delay
Y data hold time
—
—
WF
YD
t
DF
—
50
—
—
50
—
t
DHY
2t
C
– 20
2tC – 20
18
EPSON
S1D13305 Series
Technical Manual
PACKAGE DIMENSIONS
7. PACKAGE DIMENSIONS
Unit: mm
7.1. S1D13305F00A
7.2. S1D13305F00B
◊
QFP5-60 pin
◊
QFP6-60 pin
0.4
0.1
0.4
0.2
25.6 ±
17.6 ±
14.0 ±
20.0 ±
54
36
45
31
46
30
55
35
60
1
30
29
Index
Index
5
24
16
60
1
15
6
23
0.1
0.1
0.35 ±
1.0 ±
0.15
0.15
0.8 ±
0.35 ±
0 to 12°
0 to 12°
2.8
1.8
S1D13305 Series
Technical Manual
EPSON
19
INSTRUCTION SET
8. INSTRUCTION SET
8.1. The Command Set
Table 1. Command set
Command
Read
Code
Parameters
Class
Command
Hex Command Description
No. of Sec-
Bytes tion
RD WR A0 D7 D6 D5 D4 D3 D2 D1 D0
Initialize device and
display
SYSTEM SET
SLEEP IN
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
1
40
8
0
1
8.2.1
8.2.2
8.3.1
System
control
53 Enter standby mode
58, Enable and disable dis-
59 play and display flashing
DISP ON/OFF
D
Set display start address
and display regions
SCROLL
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
1
1
0
1
1
1
1
1
0
0
0
0
1
0
44
10
2
8.3.2
8.3.3
8.3.6
CSRFORM
CGRAM ADR
5D Set cursor type
Set start address of char-
5C
2
Display
control
acter generator RAM
4C
to
4F
CD CD
Set direction of cursor
movement
CSRDIR
1
0
1
0
1
0
0
1
1
0
8.3.4
1
1
1
0
0
1
Set horizontal scroll
position
HDOT SCR
OVLAY
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
5A
1
1
8.3.7
8.3.5
Set display overlay
format
5B
CSRW
CSRR
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
0
1
0
46 Set cursor address
2
2
8.4.1
8.4.2
8.5.1
Drawing
control
47 Read cursor address
42 Write to display memory
MWRITE
—
Memory
control
Read from display
memory
MREAD
1
0
1
0
1
0
0
0
0
1
1
43
—
8.5.2
Notes:
1. In general, the internal registers of the S1D13305 series are modified as each command parameter is input. However,
the microprocessor does not have to set all the parameters of a command and may send a new command before all parameters
have been input. The internal registers for the parameters that have been input will have been changed but the remaining
parameter registers are unchanged.
2-byte parameters (where two bytes are treated as 1 data item) are handled as follows:
a. CSRW, CSRR: Each byte is processed individually. The microprocessor may read or write just the low byte of the cursor
address.
b. SYSTEM SET, SCROLL, CGRAM ADR: Both parameter bytes are processed together. If the command is changed after
half of the parameter has been input, the single byte is ignored.
2. APL and APH are 2-byte parameters, but are treated as two 1-byte parameters.
20
EPSON
S1D13305 Series
Technical Manual
INSTRUCTION SET
8.2. System Control Commands
8.2.1. SYSTEM SET
Initializes the device, sets the window sizes, and selects
the LCD interface format. Since this command sets the
basic operating parameters of the S1D13305 series, an
incorrect SYSTEM SET command may cause other
commands to operate incorrectly.
MSB
LSB
D7
0
D6
1
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
A0
1
WR
0
RD
1
C
P1
P2
P3
P4
P5
P6
P7
P8
0
WF
0
0
0
0
IV
0
1
0
W/S
0
M2
M1
M0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FX
0
0
FY
C/R
TC/R
L/F
APL
APH
Figure 1. SYSTEM SET instruction
8.2.1.1. C
Note that if the CG ROM address space overlaps the
display memory address space, that portion of the display
memory cannot be written to.
This control byte performs the following:
1. Resets the internal timing generator
2. Disables the display
3. Cancels sleep mode
Parameters following P1 are not needed if only can-
celing sleep mode.
8.2.1.3. M1
Selects the memory configuration for user-definable char-
acters. The CG RAM codes select one of the 64 codes
shown in figure 46.
8.2.1.2. M0
M1 = 0: No D6 correction.
Selects the internal or external character generator ROM.
The internal character generator ROM contains 160, 5 ×
7 pixel characters, as shown in figure 70. These charac-
ters are fixed at fabrication by the metallization mask.
The external character generator ROM, on the other
hand, can contain up to 256 user-defined characters.
M0 = 0: Internal CG ROM
The CG RAM1 and CG RAM2 address spaces are not
contiguous, the CG RAM1 address space is treated as
character generator RAM, and the CG RAM2 address
space is treated as character generator ROM.
M1 = 1: D6 correction.
The CG RAM1 and CG RAM2 address spaces are
contiguout and are both treated as character generator
RAM.
M0 = 1: External CG ROM
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Technical Manual
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INSTRUCTION SET
8.2.1.4. M2
8.2.1.5. W/S
Selects the height of the character bitmaps. Characters
more than 16 pixels high can be displayed by creating a
bitmap for each portion of each character and using the
S1D13305 series graphics mode to reposition them.
M2 = 0: 8-pixel character height (2716 or equivalent
ROM)
Selects the LCD drive method.
W/S = 0: Single-panel drive
W/S = 1: Dual-panel drive
M2 = 1: 16-pixel character height (2732 or equivalent
ROM)
EI
X driver
X driver
YD
Y driver
LCD
Figure 2. Single-panel display
X driver
X driver
EI
YD
Upper Panel
Lower Panel
Y driver
X driver
X driver
Figure 3. Above and below two-panel display
22
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S1D13305 Series
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INSTRUCTION SET
EI
X driver
X driver
X driver
X driver
YD
Y driver
Left Panel
Right Panel
Figure 4. Left-and-right two-panel display
Note
There are no Seiko Epson LCD units in the configuration shown in Figure 4.
Table 2. LCD parameters
W/S = 0
W/S = 1
Parameter
IV = 1
C/R
IV = 0
IV = 1
C/R
IV = 0
C/R
C/R
TC/R
L/F
C/R
TC/R (See note 1.)
L/F
TC/R
L/F
TC/R
L/F
TC/R
L/F
00H to L/F + 1
(See note 2.)
SL1
SL2
00H to L/F
(L/F) / 2
(L/F) / 2
00H to L/F + 1
(See note 2.)
00H to L/F
(L/F) / 2
(L/F) / 2
SAD1
SAD2
SAD3
SAD4
First screen block
First screen block
First screen block
First screen block
Second screen block Second screen block Second screen block Second screen block
Third screen block
Invalid
Third screen block
Invalid
Third screen block
Third screen block
Fourth screen block Fourth screen block
Cursor move-
ment range
Above-and-below configuration:
continuous movement over whole screen
Continuous movement over whole screen
Notes:
1. See table 26 for further details on setting the C/R and TC/R parameters when using the HDOT SCR command.
2. The value of SL when IV = 0 is equal to the value of SL when IV = 1, plus one.
8.2.1.6. IV
Screen origin compensation for inverse display. IV is
usually set to 1.
The best way of displaying inverted characters is to
Exclusive-OR the text layer with the graphics back-
ground layer. However, inverted characters at the top or
left of the screen are difficult to read as the character
origin is at the top-left of its bitmap and there are no
background pixels either above or to the left of these
characters.
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Technical Manual
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INSTRUCTION SET
The IV flag causes the S1D13305 series to offset the text
screen against the graphics back layer by one vertical
pixel. Use the horizontal pixel scroll function (HDOT
SCR) to shift the text screen 1 to 7 pixels to the right. All
characters will then have the necessary surrounding back-
ground pixels that ensure easy reading of the inverted
characters.
8.2.1.7. FX
Define the horizontal character size. The character width
in pixels is equal to FX + 1, where FX can range from 00
to 07H inclusive. If data bit 3 is set (FX is in the range 08
to 0FH) and an 8-pixel font is used, a space is inserted
between characters.
See Section 10.5 for information on scrolling.
IV = 0: Screen top-line correction
Table 3. Horizontal character size selection
IV = 1: No screen top-line correction
FX
[FX] character width
(pixels)
HEX D3 D2 D1 D0
Display start point
IV
Back layer
00
01
↓
0
0
↓
0
0
↓
0
0
↓
0
1
↓
1
2
↓
1 dot
HDOT SCR
Character
07
0
1
1
1
8
Since the S1D13305 series handles display data in 8-bit
units, characters larger than 8 pixels wide must be formed
from 8-pixel segments. As Figure 6 shows, the remainder
of the second eight bits are not displayed. This also
applies to the second screen layer.
Dots 1 to 7
In graphics mode, the normal character field is also eight
pixels. If a wider character field is used, any remainder in
the second eight bits is not displayed.
Figure 5. IV and HDOT SCR adjustment
FX
FX
FY
8 bits
8 bits
FY
8 bits
8 bits
Address A Address B
Non-display area
Figure 6. FX and FY display addresses
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S1D13305 Series
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INSTRUCTION SET
8.2.1.8. WF
8.2.1.10. C/R
Selects the AC frame drive waveform period. WF is
usually set to 1.
WF = 0: 16-line AC drive
Sets the address range covered by one display line, that is,
the number of characters less one, multiplied by the
number of horizontal bytes per character.
WF = 1: two-frame AC drive
C/R can range from 0 to 239.
In two-frame AC drive, the WF period is twice the frame
period.
In 16-line AC drive, WF inverts every 16 lines.
Although 16-line AC drive gives a more readable display,
horizontal lines may appear when using high LCD drive
voltages or at high viewing angles.
For example, if the character width is 10 pixels, then the
address range is equal to twice the number of characters,
less 2. See Section 16.1.1 for the calculation of C/R.
[C/R] cannot be set to a value greater than the address
range. It can, however, be set smaller than the address
range, in which case the excess display area is blank. The
number of excess pixels must not exceed 64.
8.2.1.9. FY
Sets the vertical character size. The height in pixels is
equal to FY + 1.
FY can range from 00 to 0FH inclusive.
Set FY to zero (vertical size equals one) when in graphics
mode.
Table 4. Vertical character size selection
FY
[FY] character
height (pixels)
HEX D3 D2 D1 D0
00
01
↓
0
0
↓
0
↓
1
1
0
0
↓
1
↓
1
1
0
0
↓
1
↓
1
1
0
1
↓
1
↓
0
1
1
2
↓
07
↓
8
↓
0E
0F
15
16
Table 5. Display line address range
C/R
[C/R] bytes per display line
HEX
00
01
↓
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
D0
0
0
0
↓
1
↓
1
1
1
2
0
0
0
0
0
0
1
↓
↓
↓
↓
↓
↓
↓
↓
4F
↓
0
1
0
0
1
1
1
80
↓
↓
↓
↓
↓
↓
↓
↓
EE
EF
1
1
1
0
1
1
0
239
240
1
1
1
0
1
1
1
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Technical Manual
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25
INSTRUCTION SET
8.2.1.11. TC/R
Sets the length, including horizontal blanking, of one
line. The line length is equal to TC/R + 1, where TC/ R can
range from 0 to 255.
the equation given in section 16.1.1 in order to hold the
frame period constant and minimize jitter for any given
main oscillator frequency, fOSC.
TC/R must be greater than or equal to C/R + 4. Provided
this condition is satisfied, [TC/R] can be set according to
Table 6. Line length selection
TC/R
[TC/R] line length (bytes)
HEX
00
01
↓
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
D0
0
0
0
↓
1
↓
1
1
1
2
0
0
0
0
0
0
1
↓
↓
↓
↓
↓
↓
↓
↓
52
↓
0
1
0
1
0
0
0
83
↓
↓
↓
↓
↓
↓
↓
↓
FE
FF
1
1
1
1
1
1
0
255
256
1
1
1
1
1
1
1
8.2.1.12. L/F
Sets the height, in lines, of a frame. The height in lines is
equal to L/F + 1, where L/F can range from 0 to 255.
Table 7. Frame height selection
L/F
[L/F] lines per frame
HEX
00
01
↓
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
1
2
0
0
0
0
0
0
0
1
↓
↓
↓
↓
↓
↓
↓
↓
↓
7F
↓
0
1
1
1
1
1
1
1
128
↓
↓
↓
↓
↓
↓
↓
↓
↓
FE
FF
1
1
1
1
1
1
1
0
255
256
1
1
1
1
1
1
1
1
If W/S is set to 1, selecting two-screen display, the
number of lines must be even and L/F must, therefore, be
an odd number.
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S1D13305 Series
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INSTRUCTION SET
8.2.1.13. AP
Defines the horizontal address range of the virtual screen.
APL is the least significant byte of the address.
APL
APH
AP7
AP6
AP5
AP4
AP3
AP2
AP1
AP9
AP0
AP8
AP15
AP14
AP13
AP12
AP11
AP10
Figure 7. AP parameters
Table 8. Horizontal address range
Blank data is sent to the X-drivers, and the Y-drivers have
their bias supplies turned off by the YDIS signal. Using
the YDIS signal to disable the Y-drivers guards against
any spurious displays.
Hex code
APH
[AP] addresses
per line
APL
The internal registers of the S1D13305 series maintain
their values during the sleep state. The display memory
control pins maintain their logic levels to ensure that the
display memory is not corrupted.
0
0
↓
0
0
↓
0
0
↓
0
1
↓
0
1
↓
The S1D13305 series can be removed from the sleep state
by sending the SYSTEM SET command with only the P1
parameter. The DISP ON command should be sent next
to enable the display.
0
↓
0
↓
5
↓
0
↓
80
↓
F
F
F
F
F
F
E
F
216 – 2
216 – 1
MSB
LSB
C
0
1
0
1
0
0
1
1
Figure 9. SLEEP IN instruction
Display area
1. The YDIS signal goes LOW between one and two
frames after the SLEEP IN command is received.
Since YDIS forces all display driver outputs to go to
the deselected output voltage, YDIS can be used as a
power-down signal for the LCD unit. This can be
done by having YDIS turn off the relatively high-
power LCD drive supplies at the same time as it
blanks the display.
C/R
Display memory limit
AP
2. Since all internal clocks in the S1D13305 series are
halted while in the sleep state, a DC voltage will be
applied to the LCD panel if the LCD drive supplies
remain on.
If reliability is a prime consideration, turn off the
LCD drive supplies before issuing the SLEEP IN
command.
Figure 8. AP and C/R relationship
8.2.2. SLEEP IN
3. Note that, although the bus lines become high imped-
ance in the sleep state, pull-up or pull-down resistors
on the bus will force these lines to a known state.
Places the system in standby mode. This command has no
parameter bytes. At least one blank frame after receiving
this command, the S1D13305F halts all internal opera-
tions, including the oscillator, and enters the sleep state.
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Technical Manual
EPSON
27
INSTRUCTION SET
8.3. Display Control Commands
8.3.1. DISP ON/OFF
8.3.1.3. FP
Turns the whole display on or off. The single-byte param-
eter enables and disables the cursor and layered screens,
and sets the cursor and screen flash rates. The cursor can
be set to flash over one character or over a whole line.
Each pair of bits in FP sets the attributes of one screen
block, as follows.
The display attributes are as follows:
Table 10. Screen block attribute selection
MSB
LSB
FP1
FP0
First screen block (SAD1)
C
0
1
0
1
1
0
0
D
Second screen block (SAD2,
SAD4). See note.
FP3
FP2
P1 FP5 FP4 FP3 FP2 FP1 FP0 FC1 FC0
FP5
0
FP4
0
Third screen block (SAD3)
OFF (blank)
Figure 10. DISP ON/OFF parameters
0
1
No flashing
Flash at fFR/32 Hz
(approx. 2 Hz)
8.3.1.1. D
1
1
0
1
ON
Turns the display ON or OFF. The D bit takes prece-
dence over the FP bits in the parameter.
D = 0: Display OFF
Flash at fFR/4 Hz
(approx. 16 Hz)
D = 1: Display ON
Note
If SAD4 is enabled by setting W/S to 1, FP3 and FP2
control both SAD2 and SAD4. The attributes of
SAD2 and SAD4 cannot be set independently.
8.3.1.2. FC
Enables/disables the cursor and sets the flash rate. The
cursor flashes with a 70% duty cycle (ON/OFF).
Table 9. Cursor flash rate selection
FC1
0
FC0
0
Cursor display
OFF (blank)
No flashing
0
1
Flash at fFR/32 Hz
(approx. 2 Hz)
1
1
0
1
ON
Flash at fFR/64 Hz
(approx. 1 Hz)
Note: As the MWRITE command always enables the cursor,
thecursorpositioncanbecheckedevenwhenperform-
ing consecutive writes to display memory while the
cursor is flashing.
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INSTRUCTION SET
8.3.2. SCROLL
8.3.2.1. C
Sets the scroll start address and the number of lines per
scroll block. Parameters P1 to P10 can be omitted if not
required. The parameters must be entered sequentially as
shown in Figure 11.
MSB
LSB
C
0
1
0
0
0
1
0
0
P1 A7 A6 A5 A4 A3 A2 A1 A0 (SAD 1L)
P2 A15 A14 A13 A12 A11 A10 A9 A8 (SAD 1H)
P3 L7 L6 L5 L4 L3 L2 L1 L0 (SL 1)
P4 A7 A6 A5 A4 A3 A2 A1 A0 (SAD 2 L)
P5 A15 A14 A13 A12 A11 A10 A9 A8 (SAD 2H)
P6 L7 L6 L5 L4 L3 L2 L1 L0 (SL 2)
P7 A7 A6 A5 A4 A3 A2 A1 A0 (SAD 3L)
P8 A15 A14 A13 A12 A11 A10 A9 A8 (SAD 3H)
P9 A7 A6 A5 A4 A3 A2 A1 A0 (SAD 4L)
P10 A15 A14 A13 A12 A11 A10 A9 A8 (SAD 4H)
Figure 11. SCROLL instruction parameters
Note: Set parameters P9 and P10 only if both two-screen
drive (W/S = 1) and two-layer configuration are se-
lected. SAD4 is the fourth screen block display start
address.
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Technical Manual
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29
INSTRUCTION SET
Table 11. Screen block start address selection
SL1, SL2
[SL] screen lines
HEX
00
01
↓
L7
0
L6
0
L5
0
L4
0
L3
0
L2
0
L1
0
L0
0
1
2
0
0
0
0
0
0
0
1
↓
↓
↓
↓
↓
↓
↓
↓
↓
7F
↓
0
1
1
1
1
1
1
1
128
↓
↓
↓
↓
↓
↓
↓
↓
↓
FE
FF
1
1
1
1
1
1
1
0
255
256
1
1
1
1
1
1
1
1
8.3.2.2. SL1, SL2
SL1 and SL2 set the number of lines per scrolling screen.
The number of lines is SL1 or SL2 plus one. The relation-
ship between SAD, SL and the display mode is described
below.
Table 12. Text display mode
W/S
Screen
First Layer
SAD1
Second Layer
SAD2
First screen block
Second screen block
SL1
SL2
SAD3 (see note 1)
Third screen block (partitioned screen)
Set both SL1 and SL2 to L/F + 1
if not using a partitioned screen.
Screen configuration example:
SAD2
SAD1
SL1
SL2
0
Graphics display page 2
Character display page 1
Character display page 3
SAD3
Layer 2
Layer 1
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S1D13305 Series
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INSTRUCTION SET
Table 12. Text display mode (continued)
W/S
Screen
First Layer
Second Layer
SAD1
SL1
SAD2
SL2
Upper screen
Lower screen
SAD3
(See note 2.)
SAD4
(See note 2.)
Set both SL1 and SL2 to ((L/F) / 2 + 1).
Screen configuration example:
SAD2
SAD1
SL1
1
Graphics display page 2
Character display page 1
SAD3
Graphics display page 4
(SAD4)
Character display page 3
Layer 1
Layer 2
Notes:
1. SAD3 has the same value as either SAD1 or SAD2, whichever has the least number of lines (set by SL1 and SL2).
2. Since the parameters corresponding to SL3 and SL4 are fixed by L/F, they do not have to be set in this mode.
S1D13305 Series
Technical Manual
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INSTRUCTION SET
Table 13. Graphics display mode
W/S
Screen
First Layer
Second Layer
Third Layer
SAD1
SL1
SAD2
SL2
—
Two-layer composition
SAD3 (see note 3.)
Set both SL1 and SL2 to
L/F + 1 if not using a
partitioned screen
—
Upper screen
Screen configuration example:
SAD2
SAD1
SL1
SL2
Graphics display page 2
0
Character display page 1
SAD3
Character display page 3
Layer 1
Layer 2
SAD1
SL1 = L/F + 1
Screen configuration example:
SAD2
SL2 = L/F + 1
SAD3
—
Three-layer configuration
SAD3
SAD2
SAD1
Graphics display page 3
SL2
SL1
Graphics display page 2
0
Graphics display page 1
Layer 3
Layer 2
Layer 1
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Table 13. Graphics display mode (continued)
W/S
Screen
First Layer
Second Layer
Third Layer
SAD1
SL1
SAD2
SL2
Upper screen
—
SAD3
(See note 2.)
SAD4
(See note 2.)
Lower screen
—
Set both SL1 and SL2 to ((L/F) / 2 + 1).
Screen configuration example (See note 3.):
SAD2
SAD1
1
Graphics display page 2
SL1
Graphics display page 1
SAD3
Graphics display page 4
Graphics display page 3
Layer 1
Layer 2
Notes:
1. SAD3 has the same value as either SAD1 or SAD2, whichever has the least number of lines (set by SL1 and SL2).
2. Since the parameters corresponding to SL3 and SL4 are fixed by L/F, they do not have to be set.
3. If, and only if, W/S = 1, the differences between SL1 and (L/F + 1) / 2, and between SL2 and (L/F + 1) / 2, are blanked.
Upper Panel
Lower Panel
SL1
L/2
L
Graphics
Figure 12. Two-panel display height
S1D13305 Series
Technical Manual
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INSTRUCTION SET
Character start point
8.3.3. CSRFORM
Sets the cursor size and shape. Although the cursor is
normally only used in text displays, it may also be used in
graphics displays when displaying special characters.
0
1
2
3
4
5
6
•
•
•
0
1
2
3
4
5
6
7
8
9
MSB
LSB
C
0
0
1
0
0
0
0
0
1
0
0
1
1
0
1
CRX
P1
X3
Y3
X2
Y2
X1 X0
Y1 Y0
CRY
P2 CM
Figure 13. CSRFORM parameter bytes
8.3.3.1. CRX
CRX = 5 dots
CRY = 9 dots
CM = 0
Sets the horizontal size of the cursor from the character
origin. CRX is equal to the cursor size less one. CRX must
be less than or equal to FX.
Figure 14. Cursor size and position
8.3.3.3. CM
Table 14. Horizontal cursor size selection
Sets the cursor shape. Always set CM to 1 when in
graphics mode.
CM = 0: Underscore cursor
CRX
[CRX] cursor width
(pixels)
HEX X3 X2 X1 X0
0
1
↓
0
0
↓
0
↓
1
1
0
0
↓
1
↓
1
1
0
0
↓
0
↓
1
1
0
1
↓
0
↓
0
1
1
2
CM = 1: Block cursor
8.3.4. CSRDIR
↓
Sets the direction of automatic cursor increment. The
cursor can move left or right one character, or up or down
by the number of bytes specified by the address pitch, AP.
When reading from and writing to display memory, this
automatic cursor increment controls the display memory
address increment on each read or write.
4
↓
9
↓
E
F
15
16
MSB
LSB
CD1 CD2
8.3.3.2. CRY
Sets the location of an underscored cursor in lines, from
the character origin. When using a block cursor, CRY sets
the vertical size of the cursor from the character origin.
CRY is equal to the number of lines less one.
C
0
1
0
0
1
1
Figure 15. CSRDIR parameters
Table 15. Cursor height selection
10
CRY
[CRY] cursor height
(lines)
–AP
HEX Y3 Y2 Y1 Y0
0
1
↓
0
0
↓
1
↓
1
1
0
0
↓
0
↓
1
1
0
0
↓
0
↓
1
1
0
1
↓
0
↓
0
1
Illegal
–1
+1
2
↓
01
00
8
↓
9
+AP
↓
E
F
15
16
11
Figure 16. Cursor direction
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INSTRUCTION SET
Table 16. Cursor shift direction
C
CD1
CD0
Shift direction
4CH
4DH
4EH
4FH
0
0
1
1
0
1
0
1
Right
Left
Up
Down
Note: Since the cursor moves in address units even if FX ≥ 9,
the cursor address increment must be preset for move-
ment in character units. See Section 9.3.
8.3.5. OVLAY
Selects layered screen composition and screen text/ graph-
ics mode.
MSB
LSB
C
0
0
1
0
0
0
1
1
0
1
1
P1
OV DM2 DM1 MX1 MX0
Figure 17. OVLAY parameters
8.3.5.1. MX0, MX1
MX0 and MX1 set the layered screen composition method,
which can be either OR, AND, Exclusive-OR or Priority-
OR. Since the screen composition is organized in layers
and not by screen blocks, when using a layer divided into
two screen blocks, different composition methods cannot
be specified for the individual screen blocks.
The Priority-OR mode is the same as the OR mode unless
flashing of individual screens is used.
Table 17. Composition method selection
MX1
MX0
Function
Composition Method
Applications
0
0
L1 L2 L3 OR
Underlining, rules, mixed text and graphics
Inverted characters, flashing regions,
underlining
0
1
(L1 L2) L3 Exclusive-OR
(L1 ∩ L2) L3 AND
1
1
0
1
Simple animation, three-dimensional
appearance
L1 > L2 > L3
Priority-OR
Notes:
L1: First layer (text or graphics). If text is selected, layer L3 cannot be used.
L2: Second layer (graphics only)
L3: Third layer (graphics only)
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INSTRUCTION SET
Layer 1
Layer 2
Layer 3
Visible display
1
2
3
4
OR
EPSON
EPSON
Exclusive OR
AND
EPSON
EPSON
EPSON
EPSON
SON
Prioritized OR
EPSON
Figure 18. Combined layer display
Notes:
L1: Not flashing
L2: Flashing at 1 Hz
L3: Flashing at 2 Hz
8.3.5.2. DM1, DM2
8.3.5.3. OV
DM1 and DM2 specify the display mode of screen blocks
1 and 3, respectively.
DM1/2 = 0: Text mode
Specifies two- or three-layer composition in graphics
mode.
OV = 0: Two-layer composition
OV = 1: Three-layer composition
Set OV to 0 for mixed text and graphics mode.
DM1/2 = 1: Graphics mode
Note 1: Screen blocks 2 and 4 can only display graphics.
Note 2: DM1 and DM2 must be the same, regardless of
the setting of W/S.
8.3.6. CGRAM ADR
Specifies the CG RAM start address.
MSB
LSB
C
0
1
0
1
1
1
0
0
P1 A7 A6 A5 A4 A3 A2 A1 A0 (SAGL)
P2 A15 A14 A13 A12 A11 A10 A9 A8 (SAGH)
Figure 19. CGRAM ADR parameters
Note
See section 10 for information on the SAG parameters.
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Table 18. Scroll step selection (continued)
8.3.7. HDOT SCR
While the SCROLL command only allows scrolling by
characters, HDOT SCR allows the screen to be scrolled
horizontally by pixels. HDOT SCR cannot be used on
individual layers.
P1
D2 D1 D0
Number of pixels
to scroll
HEX
00
01
02
↓
0
0
0
1
↓
0
1
0
↓
0
1
2
↓
0
0
↓
MSB
LSB
C
0
0
1
0
0
0
1
0
1
0
0
1
0
06
07
1
1
1
1
0
1
6
7
P1
D2 D1 D0
Figure 20. HDOT SCR parameters
M
8.3.7.1. D0 to D2
A
B
X
Y
Specifies the number of pixels to scroll. The C/R param-
eter has to be set to one more than the number of
horizontal characters before using HDOT SCR. Smooth
scrolling can be simulated if the controlling microproces-
sor repeatedly issues the HDOT SCR command to the
S1D13305 series. See Section 9.5 for more information
on scrolling the display.
M = 0
N = 0
Z
A
B
X
Y
Z
A
B
X
Y
Display width
N
M/N is the number of bits (dots) that parameter 1 (P1)
is incremented/decremented by.
Figure 21. Horizontal scrolling
8.4. Drawing Control Commands
8.4.1. CSRW
The 16-bit cursor address register contains the display
memory address of the data at the cursor position as
shown in Figure 22.
The MREAD and MWRITE commands use the address
in this register.
Note that the microprocessor cannot directly access the
display memory.
MSB
LSB
C
0
1
0
0
0
1
1
0
P1 A7 A6 A5 A4 A3 A2 A1 A0 (CSRL)
P2 A15 A14 A13 A12 A11 A10 A9 A8 (CSRH)
Figure 22. CSRW parameters
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INSTRUCTION SET
The cursor address register can only be modified by the
CSRW command, and by the automatic increment after
an MREAD or MWRITE command. It is not affected by
display scrolling.
If a new address is not set, display memory accesses will
be from the last set address or the address after previous
automatic increments.
8.4.2. CSRR
Reads from the cursor address register. After issuing the
command, the data read address is read twice, for the low
byte and then the high byte of the register.
MSB
LSB
C
0
1
0
0
0
1
1
1
P1 A7 A6 A5 A4 A3 A2 A1 A0 (CSRL)
P2 A15 A14 A13 A12 A11 A10 A9 A8 (CSRH)
Figure 23. CSRR parameters
8.5. Memory Control Commands
8.5.1. MWRITE
The microprocessor may write a sequence of data bytes
to display memory by issuing the MREAD command and
then writing the bytes to the S1D13305 series. There is no
need for further MWRITE commands or for the micro-
processor to update the cursor address register after each
byte as the cursor address is automatically incremented
by the amount set with CSRDIR, in preparation for the
next data write.
MSB
LSB
C
0
1
0
0
0
0
1
0
P1
P2
Pn
n ≥ 1
Figure 24. MWRITE parameters
Note:
P1, P2, ..., Pn: display data.
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8.5.2. MREAD
Puts the S1D13305 series into the data output state.
Each time the microprocessor reads the buffer, the cursor
address is incremented by the amount set by CSRDIR and
the next data byte fetched from memory, so a sequence of
data bytes may be read without further MREAD com-
mands or by updating the cursor address register.
If the cursor is displayed, the read data will be from two
positions ahead of the cursor.
MSB
LSB
C
0
1
0
0
0
0
1
1
P1
P2
Pn
n ≥ 1
Figure 25. MREAD parameters
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DISPLAY CONTROL FUNCTIONS
9. DISPLAY CONTROL FUNCTIONS
9.1. Character Configuration
The origin of each character bitmap is in the top left
corner as shown in Figure 29. Adjacent bits in each byte
are horizontally adjacent in the corresponding character
image.
Although the size of the bitmap is fixed by the character
generator, the actual displayed size of the character field
can be varied in both dimensions.
Character starting point
FX
D7
to
D0
R0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R1
R2
R3
Character
height
R4
R5
R6
R7
FY
R8
R9
R10
R11
R12
R13
R14
R15
Space
data
Space
Space
data
Character width
Space
Figure 26. Example of character display ([FX] ≤ 8) and generator bitmap
If the area outside the character bitmap contains only
zeros, the displayed character size can easily be increased
by increasing FX and FY, as the zeros ensure that the
extra space between displayed characters is blank.
The displayed character width can be set to any value up
to 16 even if each horizontal row of the bitmap is two
bytes wide.
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Horizontal
non-display
area
FX
Character
Height
FY
16 dots
Space
Vertical
non-display
area
8 dots
8 dots
Character width
Space
Figure 27. Character width greater than one byte wide ([FX] = 9)
Note: The S1D13305 series does not automatically insert spaces between characters. If the displayed character size is
8 pixels or less and the space between character origins is nine pixels or more, the bitmap must use two bytes per row,
even though the character image requires only one.
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DISPLAY CONTROL FUNCTIONS
9.2. Screen Configuration
9.2.1. Screen configuration
The basic screen configuration of the S1D13305 series is
as a single text screen or as overlapping text and graphics
screens. The graphics screen uses eight times as much
display memory as the text screen.
Figure 28 shows the relationship between the virtual
screens and the physical screen.
A/P
C/R
0000H
Character
memory area
0800H
07FFH
Graphics
memory area
Display
memory
window
47FFH
(0,YM)
(X,Y)
(XW,YM)
(XM,YM)
Y
(0,0)
X
(XM,0)
Figure 28. Virtual and physical screen relationship
9.2.2. Display address scanning
The S1D13305 series scans the display memory in the
same way as a raster scan CRT screen. Each row is
scanned from left to right until the address range equals
C/R. Rows are scanned from top to bottom.
In graphics mode, at the start of each line, the address
counter is set to the address at the start of the previous line
plus the address pitch, AP.
In text mode, the address counter is set to the same start
address, and the same character data is read, for each row
in the character bitmap. However, a new row of the
character generator output is used each time. Once all the
rows in the character bitmap have been displayed, the
address counter is set to the start address plus AP and the
next line of text is displayed.
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1
•
SAD
SAD + 1
SAD + 2
SAD + C/R
•
•
8
9
•
SAD + AP
SAD + AP
+ 1
SAD + AP
+ 2
SAD + AP
+ C/R
•
•
16
17
•
SAD + 2AP
•
•
24
•
•
•
•
C/R
W/S = 0, FX = 8, FY = 8
Figure 29. Character position parameters
Note: One byte of display memory corresponds to one character.
SAD
SAD +1
SAD + 2
SAD + C/R
1
2
3
SAD + AP
SAD + AP
+ 1
SAD + AP
+ 2
SAD + AP
+ C/R
SAD
SAD +1
SAD + 2
SAD + 2AP
Line 1
AP
AP
•
•
•
•
•
•
•
•
SAD + C/R
SAD + AP
SAD + AP + 1
Line 2
Line 3
SAD + AP + C/R
SAD + 2AP
C/R
W/S = 0, FX = 8
Figure 30. Character parameters vs. memory
Note: One bit of display memory corresponds to one pixel.
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DISPLAY CONTROL FUNCTIONS
1
SAD1
SAD1 + 1
SAD1 + 2
SAD1 + C/R
•
•
•
8
9
SAD1 + AP
SAD1 + AP
+ 1
SAD1 + AP
+ 2
SAD1 + AP
+ C/R
•
•
•
16
17
SAD1 + 2AP
•
•
•
24
25
•
•
•
(L/F)/2 = β
β + 1
SAD3 + 1
SAD3 + 2
SAD3 + C/R
•
•
•
β + 8
β + 9
SAD3 + AP
SAD3 + AP
+ 1
SAD3 + AP
+ 2
SAD3 + AP
+ C/R
•
•
•
β + 16
β + 17
SAD3 + 2AP
•
•
•
β + 24
β + 25
•
•
•
•
(L/F)
C/R
W/S = 1, FX = 8, FY = 8
Figure 31. Two-panel display address indexing
Note
In two-panel drive, the S1D13305 series reads line 1 and line β + 1 as one cycle. The upper and lower panels
are thus read alternately, one line at a time.
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9.2.3. Display scan timing
Figure 32 shows the basic timing of the S1D13305 series.
One display memory read cycle takes nine periods of the
system clock, φ0 (fOSC ). This cycle repeats (C/R + 1)
times per display line.
When reading, the display memory pauses at the end of
each line for (TC/R - C/R) display memory read cycles,
though the LCD drive signals are still generated. TC/R
may be set to any value within the constraints imposed by
C/R, fOSC , fFR , and the size of the LCD panel, and it may
be used to fine tune the frame frequency. The micropro-
cessor may also use this pause to access the display
memory data.
φ0
T0
T1
Display read cycle interval
T2
VCE
VA
Character generator
read interval
Character read interval
Graphics read interval
Figure 32. Display memory basic read cycle
Display period
TC/R
Divider frequency
period
C/R
Line 1
O
R
R
R
2
3
O
O
Frame
period
•
•
•
•
•
O
(L/F)
LP
R
Figure 33. Relationship between TC/R and C/R
Note: The divider adjustment interval (R) applies to both the upper and lower screens even if W/S = 1. In this case, LP is active
only at the end of the lower screen’s display interval.
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DISPLAY CONTROL FUNCTIONS
9.3. Cursor Control
9.3.1. Cursor register function
The S1D13305 series cursor address register functions as
both the displayed cursor position address register and
the display memory access address register. When ac-
cessing display memory outside the actual screen memory,
the address register must be saved before accessing the
memory and restored after memory access is complete.
Although the cursor is normally displayed for character
data, the S1D13305 series may also display a dummy
cursor for graphical characters. This is only possible if the
graphics screen is displayed, the text screen is turned off
and the microprocessor generates the cursor control ad-
dress.
D = 1
Cursor display
address register
FC1 = 0
Cursor ON
FC0 = 1
Cursor register
Address pointer
Figure 34. Cursor addressing
FP1 = 0
Block screen 1 (character
screen) OFF
Note that the cursor may disappear from the display if the
cursor address remains outside the displayed screen
memory for more than a few hundred milliseconds.
FP0 = 0
9.3.2. Cursor movement
FP3 = 0
Block screen 2 (graphics
screen) ON
On each memory access, the cursor address register
changes by the amount previously specified with CSRDIR,
automatically moving the cursor to the desired location.
FP2 = 1
Figure 35. Cursor display layers
9.3.3. Cursor display layers
Although the S1D13305 series can display up to three
layers, the cursor is displayed in only one of these layers:
Two-layer configuration: First layer (L1)
Consider the example of displaying Chinese characters
on a graphics screen. To write the display data, the cursor
address is set to the second screen block, but the cursor is
not displayed. To display the cursor, the cursor address is
set to an address within the blank text screen block.
Since the automatic cursor increment is in address units,
not character units, the controlling microprocessor must
set the cursor address register when moving the cursor
over the graphical characters.
Three-layer configuration: Third layer (L3)
The cursor will not be displayed if it is moved outside the
memory for its layer. Layers may be swapped or the
cursor layer moved within the display memory if it is
necessary to display the cursor on a layer other than the
present cursor layer.
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8 dots 8 dots
8 dots 8 dots
Block cursor
18 dots
Auto shift
Auto shift
Auto shift
Cursor address preset
Figure 36. Cursor movement
If no text screen is displayed, only a bar cursor can be
displayed at the cursor address.
If the first layer is a mixed text and graphics screen and the
cursor shape is set to a block cursor, the S1D13305 series
automatically decides which cursor shape to display. On
the text screen it displays a block cursor, and on the
graphics screen, a bar cursor.
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DISPLAY CONTROL FUNCTIONS
9.4. Memory to Display Relationship
The S1D13305 series supports virtual screens that are
larger than the physical size of the LCD panel address
range, C/R. A layer of the S1D13305 series can be
considered as a window in the larger virtual screen held
in display memory. This window can be divided into two
blocks, with each block able to display a different portion
of the virtual screen.
This enables, for example, one block to dynamically
scroll through a data area while the other acts as a status
message display area. See Figure 37 and 38.
AP
C/R
SAD1
W/S = 0
W/S = 1
Character page 1
Character page 3
SAD1
SAD3
SAD3
Display page 1
Display page 3
Display page 1
SAD2
Layer 1
SAD2
SAD4
Graphics page 2
Layer 1
SAD4
Graphics page 2
C/R
Display page 2
Display page 4
Display page 2
Layer 2
Layer 2
CG RAM
SAD1
C/R
Character page 1
SAD1
SAD3
Display page 1
Display page 3
C/R
SAD3
Character page 3
Layer 1
SAD2
C/R
SAD2
Display page 2
Graphics page 2
Layer 2
C/R
SAD3
Graphics page 3
C/R
Graphics page 2
SAD3
SAD2
SAD1
Display page 3
Display page 2
SAD2
Display page 1
C/R
SAD1
Graphics page 1
Layer 1
Layer 2
Layer 3
Figure 37. Display layers and memory
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AP
0000H
FX
SAD1
FY
CRY
CSRA
CRX
Display
window
L/F
Virtual display
memory limit
C/R
FX = Horizontal character field ≤ 16 dots
FY = Vertical character field ≤ 16 dots
CRX = Horizontal cursor size ≤ 16 dots
CRY = Vertical cursor size ≤ 16 dots
C/R = Characters per row ≤ 240 bytes
L/F = Lines per frame ≤ 256 bytes
AP = Address pitch ≤ 64 Kbytes
FFFFH
Figure 38. Display window and memory
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DISPLAY CONTROL FUNCTIONS
Figure 39. Memory map and magnified characters
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9.5. Scrolling
The controlling microprocessor can set the S1D13305
series scrolling modes by overwriting the scroll address
registers SAD1 to SAD4, and by directly setting the
scrolling mode and scrolling rate.
Since the S1D13305 series does not automatically erase
the bottom line, it must be erased with blanking data when
changing the scroll address register.
9.5.1. On-page scrolling
The normal method of scrolling within a page is to move
the whole display up one line and erase the bottom line.
Display memory
AP
C/R
ABC
ABC
SAD1
Before scrolling
WXYZ
789
WXYZ
789
SAD3
SAD1
Blank
WXYZ
789
After scrolling
WXYZ
789
Blank
Figure 40. On-page scrolling
9.5.2. Inter-page scrolling
Scrolling between pages and page switching can be
performed only if the display memory capacity is greater
than one screen.
Display memory
AP
C/R
ABC
ABC
SAD1
Before scrolling
WXYZ
789
WXYZ
789
ABC
WXYZ
789
After scrolling
SAD1
WXYZ
789
Figure 41. Inter-page scrolling
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DISPLAY CONTROL FUNCTIONS
9.5.3. Horizontal scrolling
The display can be scrolled horizontally in one-character
units, regardless of the display memory capacity.
Display memory
ABC XYZ
Display
ABC
123
XYZ
SAD1
Before scrolling
123
AP
C/R
BC
23
XYZ1
ABC
123
XYZ
After scrolling
SAD1
Figure 42. Horizontal wraparound scrolling
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9.5.4. Bidirectional scrolling
Bidirectional scrolling can be performed only if the
display memory is larger than the physical screen both
horizontally and vertically. Although scrolling is nor-
mally done in single-character units, the HDOT SCR
command can be used to scroll horizontally in pixel units.
Single-pixel scrolling both horizontally and vertically
can be performed by using the SCROLL and HDOT SCR
commands. See Section 16.4
Display memory
AP
BC
Before scrolling
EFG
TUV
A BC
EFG
TUV
12
12 34
567
C/R
89
ABC
E FG
TUV
FG
TUV
After scrolling
1234
56
1234
56 7
89
Figure 43. Bidirectional scrolling
9.5.5. Scroll units
Tale 19. Scroll units
Mode
Vertical
Horizontal
Pixels or
characters
Text
Characters
Graphics
Pixels
Pixels
Note that in a divided screen, each block cannot be indepen-
dently scrolled horizontally in pixel units.
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CHARACTER GENERATOR
10. CHARACTER GENERATOR
10.1. CG Characteristics
10.1.1. Internal character generator
10.1.3. Character generator RAM
The internal character generator is recommended for
minimum system configurations containing a S1D13305
series, display RAM, LCD panel, single-chip micropro-
cessor and power supply. Since the internal character
generator uses a CMOS mask ROM, it is also recom-
mended for low-power applications.
•
•
•
5 × 7-pixel font (See Section 17.)
160 JIS standard characters
Can be mixed with character generator RAM (maxi-
mum of 64 CG RAM characters)
•
Can be automatically spaced out up to 8 × 16 pixels
10.1.2. External character generator ROM
The external CG ROM can be used when fonts other than
those in the internal ROM are needed. Data is stored in the
external ROM in the same format used in the internal
ROM. (See Section 10.3.)
•
•
•
Up to 8 × 8-pixel characters (M2 = 0) or 8 × 16-pixel
characters (M2 = 1)
Up to 256 characters (192 if used together with the
internal ROM)
Mapped into the display memory address space at
F000H to F7FFH (M2 = 0) or F000H to FFFFH (M2
= 1)
•
Characters can be up to 8 × 16-pixels; however, excess
bits must be set to zero.
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10.2. CG Memory Allocation
Since the S1D13305 series uses 8-bit character codes, it
can handle no more than 256 characters at a time. How-
ever, if a wider range of characters is required, character
generator memory can be bank-switched using the
CGRAM ADR command.
Built–in CG ROM
(160 characters,
5 × 7 pixels max)
CG RAM n
CG RAM 2
CG RAM
SAG
CG RAM 1
M0 = 1
(64 characters max, 8 × 16 pixels max)
Basic CG space
(256 characters,
8 × 16 pixels max)
256 characters max
M1 = 0
CG RAM
CG ROM
M0 = 1
256 characters max
M1 = 0
Built-in CG ROM
(160 characters,
5 × 7 pixels max)
CG RAM n
CG RAM 2
CG RAM
ADR
CG RAM
CG RAM 1
(64 characters max, 8 × 16 pixels max)
Figure 44. Internal and external character mapping
Note that there can be no more than 64 characters per bank.
Table 20. Character mapping
Item
Internal/external character generator selection
1 to 8 pixels
Parameter
Remarks
M0
M2 = 0
M2 = 1
Character field height 9 to 16 pixels
Greater than 16 pixels
Graphics mode (8 bits × 1 line)
Internal CG ROM/RAM select
External CG ROM/RAM select
Determined by the
character code
Automatic
M1
CG RAM bit 6 correction
Specified with CG RAM ADR
command
Can be moved anywhere in the
display memory address space
CG RAM data storage address
192 characters or less
External CG ROM
Other than the area of Figure 49
Set SAG to F000H and overly
SAG and the CG ROM table
address
More than 192 characters
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CHARACTER GENERATOR
10.3. Setting the Character Generator Address
The CG RAM addresses in the VRAM address space are
not mapped directly from the address in the SAG register.
The data to be displayed is at a CG RAM address
calculated from SAG + character code + ROW select
address. This mapping is shown in Table 21 and 22.
Table 21. Character fonts, number of lines ≤ 8 (M2 = 0, M1 = 0)
SAG
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Character code
+ROW select address
CG RAM address
0
0
0
0
0
0
0
0
0
0
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
0
R2 R1 R0
VA15 VA14 VA13 VA12 VA11 VA10 VA9 VA8 VA7 VA6 VA5 VA4 VA3 VA2 VA1 VA0
Table 22. Character fonts, 9 ≤ number of lines ≤ 16 (M2 = 1, M1 = 0)
SAG
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Character code
+ROW select address
CG RAM address
0
0
0
0
0
0
0
0
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
0
0
R3 R2 R1 R0
VA15 VA14 VA13 VA12 VA11 VA10 VA9 VA8 VA7 VA6 VA5 VA4 VA3 VA2 VA1 VA0
Row
R3
0
R2
0
R1
0
R0
0
Row 0
Row 1
Row 2
0
0
0
1
0
0
1
0
Line 1
Line 2
1
Row 7
Row 8
0
1
1
0
1
0
0
Row 14
Row 15
1
1
1
1
1
1
0
1
Figure 45. Row select address
Note: Lines = 1: lines in the character bitmap ≤ 8
Lines = 2: lines in the character bitmap ≥ 9
10.3.1. M1 = 1
The S1D13305 series automatically converts all bits set
in bit 6 of character code for CG RAM 2 to zero. Because
of this, the CG RAM data areas become contiguous in
display memory.
When writing data to CG RAM:
•
Calculate the address as for M1 = 0.
•
Change bit 6 of the character code from “1” to “0”.
56
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S1D13305 Series
Technical Manual
CHARACTER GENERATOR
10.3.2. CG RAM addressing example
•
•
•
Define a pattern for the “A” in Figure 26.
The CG RAM table start address is 4800H.
The character code for the defined pattern is 80H (the
first character code in the CG RAM area).
and can be used as desired. 80H is thus the first code for
CG RAM. As characters cannot be used if only using
graphics mode, there is no need to set the CG RAM data.
As the character code table in Figure 46 shows, codes
80H to 9FH and E0H to FFH are allocated to the CG RAM
Table 23. Character data example
CGRAM AD 5CH
P1
P2
00H
40H
Reverse the CG RAM address calculation to calculate SAG
CSRDIR
CSRW
P1
4CH Set cursor shift direction to right
46H
00H
48H
42H
70H
88H
88H
88H
F8H
88H
88H
00H
00H
↓
CG RAM start address is 4800H
P2
MWRITE
P
Write ROW 0 data
Write ROW 1 data
Write ROW 2 data
Write ROW 3 data
Write ROW 4 data
Write ROW 5 data
Write ROW 6 data
Write ROW 7 data
Write ROW 8 data
↓
P2
P3
P4
P5
P6
P7
P8
P8
↓
P16
00H
Write ROW 15 data
S1D13305 Series
Technical Manual
EPSON
57
CHARACTER GENERATOR
10.4. Character Codes
The following figure shows the character codes and the
codes allocated to CG RAM. All codes can be used by the
CG RAM if not using the internal ROM.
Upper 4 bits
Lower 4 bits
0
1
2
3
0
1
2
3
4
5
6
7
8
9
:
4
@
A
B
C
D
E
F
5
P
Q
R
S
T
U
V
W
X
Y
Z
[
6
'
7
p
q
r
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
!
"
a
b
c
d
e
f
#
$
%
&
'
s
t
u
v
w
x
y
z
{
G
H
I
g
h
i
(
)
*
J
j
+
,
;
K
L
k
l
<
=
>
?
¥
|
.
M
N
O
]
m
n
o
}
-
^
→
←
/
_
CG RAM1
CG RAM2
M1 = 0
M1 = 1
Figure 46. On-chip character codes
58
EPSON
S1D13305 Series
Technical Manual
MICROPROCESSOR INTERFACE
11. MICROPROCESSORINTERFACE
11.1. System Bus Interface
SEL1, SEL2, A0, RD, WR and CS are used as control
signals for the microprocessor data bus. A0 is normally
connected to the lowest bit of the system address bus.
SEL1 and SEL2 change the operation of the RD and WR
pins to enable interfacing to either an 8080 or 6800 family
bus, and should have a pull-up or pull-down resistor.
With microprocessors using an 8080 family interface, the
S1D13305 series is normally mapped into the I/O address
space.
Display flicker may occur if there is more than one
consecutive access that cannot be ignored within a frame.
The microprocessor can minimize this either by perform-
ing these accesses intermittently, or by continuously
checking the status flag (D6) and waiting for it to become
HIGH.
11.2.1. Display status indication output
When CS, A0 and RD are LOW, D6 functions as the
display status indication output. It is HIGH during the
TV-mode vertical retrace period or the LCD-mode hori-
zontal retrace period, and LOW, during the period the
controller is writing to the display. By monitoring D6 and
writing to the data memory only during retrace periods,
the display can be updated without causing screen flicker.
11.1.1. 8080 series
Table 24. 8080 series interface signals
A0 RD WR
Function
Status flag read
0
0
1
Display data and cursor address
read
1
0
1
11.2.2. Internal register access
0
1
1
1
0
0
Display data and parameter write
Command write
The SYSTEM SET and SLEEP IN commands can be
used to perform input/output to the S1D13305 series
independently of the system clock frequency. These are
the only commands that can be used while the S1D13305
series is in sleep mode.
11.1.2. 6800 series
Table 25. 6800 series interface signals
11.2.3. Display memory access
A0 R/W
E
Function
Status flag read
The S1D13305 series supports a form of pipelined pro-
cessing, in which the microprocessor synchronizes its
processing to the S1D13305 series timing. When writing,
the microprocessor first issues the MWRITE command.
It then repeatedly writes display data to the S1D13305
series using the system bus timing. This ensures that the
microprocessor is not slowed down even if the display
memory access times are slower than the system bus
access times. See Figure 47.
0
1
1
Display data and cursor address
read
1
1
1
0
1
0
0
1
1
Display data and parameter write
Command write
11.2. Microprocessor Synchronization
The S1D13305 series interface operates at full bus speed,
completing the execution of each command within the
cycle time, tCYC . The controlling microprocessor’s per-
formance is thus not hampered by polling or handshaking
when accessing the S1D13305 series.
When reading, the microprocessor first issues the MREAD
command, which causes the S1D13305 series to load the
first read data into its output buffer. The microprocessor
then reads data from the S1D13305 series using the
system bus timing. With each read, the S1D13305 series
reads the next data item from the display memory ready
for the next read access. See Figure 48.
S1D13305 Series
Technical Manual
EPSON
59
MICROPROCESSOR INTERFACE
tCYC
WR
Microprocessor
Command write
Data write
Data write
D0 to D7
VR/W
VRW
Display memory
VD0 to VD7
Figure 47. Display memory write cycle
WR
RD
tCYC
Command write
Microprocessor
Data read
Data read
D0 to D7
VR/W
VRW
Display memory
VD0 to VD7
Figure 48. Display memory read cycle
Note
A possible problem with the display memory read cycle is that the system bus access time, tACC, does not
depend on the display memory access time, tACV. The microprocessor may only make repeated reads if the
read loop time exceeds the S1D13305 series cycle time, tCYC. If it does not, NOP instructions may be inserted
in the program loop. tACC, tACV and tCYC limits are given in section 6.2.
60
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S1D13305 Series
Technical Manual
MICROPROCESSOR INTERFACE
11.3. Interface Examples
11.3.1. Z80 to S1D13305 series interface
IORQ
A0
A0
A1
to
Decoder
CS
A15
S1D13305
series
Z80®
D0
to
D0
to
D7
D7
SEL 1
SEL 2
RD
WR
RD
WR
RES
RESET
RESET
Figure 49. Z80® to S1D13305 series interface
Note: Z80® is a registered trademark of Zilog Corporation.
11.3.2. 6802 to S1D13305 series interface
VMA
A0
A0
A1
to
Decoder
CS
A15
S1D13305
series
6802
D0
to
D0
to
VDD
D7
D7
SEL 1
SEL 2
E
R/W
RD
WR
RES
RESET
RESET
Figure 50. 6802 to S1D13305 series interface
S1D13305 Series
Technical Manual
EPSON
61
DISPLAY MEMORY INTERFACE
12. DISPLAY MEMORY INTERFACE
12.1. Static RAM
The figure below shows the interface between an 8K × 8
static RAM and the S1D13305 series. Note that bus
buffers are required if the bus is heavily loaded.
•
S1D13305F
Note
VA0 to VA12
VA13 to VA15
A0 to A12
HC138
A-C
Y
CE1
CE2
VDD
2764-pin
S1D13305
compatible
memory
WRD
OE
VWR
WE
VD0 to VD7
I/O1 to I/O8
Note
Figure 51. Static RAM interface
Note: If the bus load is too much, use a bus buffer.
62
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S1D13305 Series
Technical Manual
DISPLAY MEMORY INTERFACE/OSCILLATOR CIRCUIT/STATUS FLAG
12.2. Supply Current during Display Memory Access
The 24 address and data lines of the S1D13305 series
cycle at one-third of the oscillator frequency, fOSC. The
charge and discharge current on these pins, IVOP, is given
by the equation below. When IVOP exceeds IOPR, it can be
estimated by:
If VOPR = 5.0V, f = 1.0 MHz, and the display memory bus
capacitance is 1.0 pF per line:
IVOP ≤ 120 µA / MHz × pF
To reduce current flow during display memory accesses,
it is important to use low-power memory, and to mini-
mize both the number of devices and the parasitic capaci-
tance.
IVOP C V f
where C is the capacitance of the display memory bus, V
is the operating voltage, and f is the operating frequency.
13. OSCILLATOR CIRCUIT
The S1D13305 series incorporates an oscillator circuit. A
stable oscillator can be constructed simply by connecting
an AT-cut crystal and two capacitors to XG and XD, as
shown in the figure below. If the oscillator frequency is
increased, CD and CG should be decreased proportion-
ally.
S1D13305 series
XG
XD
Note that the circuit board lines to XG and XD must be as
short as possible to prevent wiring capacitance from
changing the oscillator frequency or increasing the power
consumption.
C
C
= 3 to 20 pF
= 2 to 18 pF
D
G
CG
CD
Load impedance = 700 Ω (max)
Figure 52. Crystal oscillator
14. STATUS FLAG
The S1D13305 series has a single bit status flag.
D6: X line standby
The D6 status flag is HIGH for the TC/R-C/R cycles at the
end of each line where the S1D13305 series is not reading
the display memory. The microprocessor may use this
period to update display memory without affecting the
display, however it is recommended that the display be
turned off when refreshing the whole display.
D7
D0
X
D6
X
X
X
X
X
X
X: Don’t care
Figure 53. Status flag
LP
tTC/R
tm
tC/R
XSCL
Figure 54. C/R to TC/R time difference
CS
0
A0
0
RD
0
D6 (flag)
0: Period of retrace lines
1: Period of display
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Technical Manual
EPSON
63
STATUS FLAG
Read Status Flag
D6 = 0?
No
Yes
Data Input
No
Data Input ?
Yes
Figure 55. Flowchart for busy flag checking
<Timing To Be Observed For Avoiding S1D 13305 Series Write Noise>
• Precaution on the write timing to VRAM
The allowable writing duration is since “5 × 9 × tOSC” has elapsed (tOSC = 1/fOSC: a cycle of the
oscillation frequency) from the positive going edge of LP up to {(TCR) – (C/R) – 7} × 9 × tOSC.
Currently employed D6 status flag reading method does
not identify the timing when the read D6 = Low took
place. Thus, negative going edge of LP should be used as
the interrupt signal when implementing the writing in
above timing.
If you try to access the display memory in other timing
than the above, flickering of the display screen will result.
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Technical Manual
RESET/APPLICATION NOTES
15. RESET
VDD
1ms reset pulse
RES
0.7 VDD
0.3 VDD
Figure 56. Reset timing
The S1D13305 series requires a reset pulse at least 1 ms
long after power-on in order to re-initialize its internal
state.
For maximum reliability, it is not recommended to apply
a DC voltage to the LCD panel while the S1D13305 series
is reset. Turn off the LCD power supplies for at least one
frame period after the start of the reset pulse.
The S1D13305 series cannot receive commands while it
is reset. Commands to initialize the internal registers
should be issued soon after a reset.
During reset, the LCD drive signals XD, LP and FR are
halted.
A delay of 3 ms (maximum) is required following the
rising edges of both RES and VDD to allow for system
stabilization.
16. APPLICATION NOTES
16.1. Initialization Parameters
The parameters for the initialization commands must be
determined first. Square brackets around a parameter
name indicate the number represented by the parameter,
rather than the value written to the parameter register. For
example, [FX] = FX + 1.
❒ TC/R
TC/R must satisfy the condition [TC/R] ≥ [C/R] + 4.
❒ fOSC and fFR
Once TC/R has been set, the frame frequency, fFR, and
lines per frame [L/F] will also have been set. The
lower limit on the oscillator frequency fOSC is given
by:
16.1.1. SYSTEM SET instruction and
parameters
❒ FX
fOSC ≥ ([TC/R] × 9 + 1) × [L/F] × fFR
❒ If no standard crystal close to the calculated value of
fOSC exists, a higher frequency crystal can be used and
the value of TC/R revised using the above equation.
❒ Symptoms of an incorrect TC/R setting are listed
below. If any of these appears, check the value of TC/
R and modify it if necessary.
The horizontal character field size is determined from
the horizontal display size in pixels [VD] and the
number of characters per line [VC].
[VD] / [VC] ≤ [FX]
❒ C/R
•
Vertical scanning halts and a high-contrast hori-
zontal line appears.
C/R can be determined from VC and FX.
[C/R] = RND ([FX] / 8) × [VC]
where RND(x) denotes × rounded up to the next
highest integer. [C/R] is the number of bytes per line,
not the number of characters.
•
•
•
All pixels are on or off.
The LP output signal is absent or corrupted.
The display is unstable.
S1D13305 Series
Technical Manual
EPSON
65
APPLICATION NOTES
Table 26. Epson LCD unit example parameters
Product name and
[FX]
f
OSC (MHz)
[FY]
[C/R]
TC/R
resolution (X × Y)
See Note 2.
[FX] = 6 pixels:
256 / 6 = 42 remainder 4
= 4 blank pixels
[C/R] = 42 = 2AH bytes:
C/R = 29H. When using HDOT
SCR, [C/R] = 43 bytes
8 or 16, depending
on the screen
2DH
1.85
256 × 64
512 × 64
256 × 128
512 × 128
[FX] = 6 pixels:
512 / 6 = 85 remainder 2
= 2 blank pixels
[C/R] = 85 = 55H bytes:
C/R = 54H. When using HDOT
SCR, [C/R] = 86 bytes
8 or 16, depending
on the screen
58H
22H
69H
3.59
2.90
8.55
[FX] = 8 pixels:
256 / 8 = 32 remainder 0
= no blank pixels
[C/R] = 32 = 20H bytes:
C/R = 19H. When using HDOT
SCR, [C/R] = 33 bytes
8 or 16, depending
on the screen
[FX] = 10 pixels:
512 / 10 = 51 remainder 2
= 2 blank pixels
[C/R] = 102 = 66H bytes:
C/R = 65H. When using HDOT
SCR, [C/R] = 103 bytes
8 or 16, depending
on the screen
Notes:
1. The remainder pixels on the right-hand side of the display are automatically blanked by the S1D13305F. There is no need to
zero the display memory corresponding to these pixels.
2. Assuming a frame frequency of 60 Hz.
16.1.2. Initialization example
The initialization example shown in Figure 57 is for a
S1D13305 series with an 8-bit microprocessor interface
bus and an Epson EG4810S-AR display unit (512 × 128
pixels).
Clear first
memory layer
Start
Clear second
memory layer
Supply on
SYSTEM SET
SCROLL
CSRW
CSR FORM
DISP ON
HDOT SCR
OVLAY
Output display
data
DISP OFF
Figure 57. Initialization procedure
Note: Set the cursor address to the start of each screen’s layer memory, and use MWRITE to fill the memory with space
characters,20H(textscreenonly)or00H(graphicsscreenonly).Determiningwhichmemorytoclearisexplainedinsection
16.1.3.
66
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S1D13305 Series
Technical Manual
APPLICATION NOTES
Table 27. Initialization procedure
No.
1
Command
Operation
Power-up
Supply
2
3
SYSTEM SET
C = 40H
P1 = 38H
M0: Internal CG ROM
M1: CG RAM is 32 characters maximum
M2: 8 lines per character
W/S: Two-panel drive
IV: No top-line compensation
P2 = 87H
FX: Horizontal character size = 8 pixels
WF: Two-frame AC drive
P3 = 07H
P4 = 3FH
P5 = 49H
FY: Vertical character size = 8 pixels
C/R: 64 display addresses per line
TC/R: Total address range per line = 90
fOSC = 6.0 MHz, fFR = 70 Hz
P6 = 7FH
L/F: 128 display lines
P7 = 80H
P8 = 00H
AP: Virtual screen horizontal size is 128 addresses
4
SCROLL
C = 44H
P1 = 00H
P2 = 00H
First screen block start address
Set to 0000H
P3 = 40H
Display lines in first screen block = 64
P4 = 00H
P5 = 10H
Second screen block start address
Set to 1000H
P6 = 40H
Display lines in second screen block = 64
P7 = 00H
P8 = 04H
Third screen block start address
Set to 0400H
(continued)
S1D13305 Series
Technical Manual
EPSON
67
APPLICATION NOTES
Table 27. Initialization procedure (continued)
No.
Command
P9 = 00H
P10 = 30H
Operation
Fourth screen block start address
Set to 3000H
Display memory
(SAD1) 0000H
(SAD3) 0400H
0800H
1st display memory page
2nd display memory page
(SAD2) 1000H
3rd display memory page
4th display memory page
(SAD4) 3000H
5000H
5
6
HDOT SCR
C = 5AH
P1 = 00H
OVLAY
Set horizontal pixel shift to zero
C = 5BH
P1 = 01H
MX 1, MX 0: Inverse video superposition
DM 1: First screen block is text mode
DM 2: Third screen block is text mode
7
DISP ON/OFF
C = 58H
D: Display OFF
P1 = 56H
FC1, FC0: Flash cursor at 2 Hz
FP1, FP0: First screen block ON
FP3, FP2: Second and fourth screen blocks ON
FP5, FP4: Third screen block ON
8
Clear data in first layer
Fill first screen layer memory with 20H (space character)
(continued)
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S1D13305 Series
Technical Manual
APPLICATION NOTES
Table 27. Initialization procedure (continued)
No.
Command
Operation
9
Clear data in second layer
Fill second screen layer memory with 00H (blank data)
Display
Character code in every position
1st layer
Blank code in every position
2nd layer
10
11
CSRW
C = 46H
P1 = 00H
P2 = 00H
Set cursor to start of first screen block
CRX: Horizontal cursor size = 5 pixels
CSR FORM
C = 5DH
P1 = 04H
P2 = 86H
CRY: Vertical cursor size = 7 pixels
CM: Block cursor
12
DISP ON/OFF
C = 59H
Display ON
Display
13
CSR DIR
C = 4CH
Set cursor shift direction to right
(continued)
S1D13305 Series
Technical Manual
EPSON
69
APPLICATION NOTES
Table 27. Initialization procedure (continued)
No.
Command
MWRITE
C = 42H
Operation
14
P1 = 20H
P2 = 45H
P3 = 50H
P4 = 53H
P5 = 4FH
P6 = 4EH
‘ ’
‘E’
‘P’
‘S’
‘O’
‘N’
EPSON
15
CSRW
C = 46H
P1 = 00H
P2 = 10H
Set cursor to start of second screen block
Set cursor shift direction to down
16
17
CSR DIR
C = 4FH
MWRITE
C = 42H
P1 = FFH
↓
Fill in a square to the left of the ‘E’
P9 = FFH
EPSON
18
CSRW
C = 46H
P1 = 01H
P2 = 10H
Set cursor address to 1001H
19
MWRITE
C = 42H
(continued)
70
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S1D13305 Series
Technical Manual
APPLICATION NOTES
Table 27. Initialization procedure (continued)
No.
Command
Operation
P1 = FFH
Fill in the second screen block in the second column of line 1
↓
P9 = FFH
CSRW
20
↓
Repeatoperations18and19tofillinthebackgroundunder
‘EPSON’
Inverse display
29
MWRITE
EPSON
30
CSRW
C = 46H
P1 = 00H
P2 = 01H
CSR DIR
C = 4CH
MWRITE
C = 42H
Set cursor to line three of the first screen block
Set cursor shift direction to right
31
32
P1 = 44H
P2 = 6FH
P3 = 74H
P4 = 20H
P5 = 4DH
P6 = 61H
P7 = 74H
P8 = 72H
P9 = 69H
P10 = 78H
P11 = 20H
P12 = 4CH
P13 = 43H
P14 = 44H
‘D’
‘o’
‘t’
‘ ’
‘M’
‘a’
‘t’
‘r’
‘i’
‘x’
‘ ’
Inverse display
EPSON
Dot matrix LCD
‘L’
‘C’
‘D’
S1D13305 Series
Technical Manual
EPSON
71
APPLICATION NOTES
16.1.3. Display mode setting example 1: combining text and graphics
❒ Conditions
❒ Display memory allocation
•
320 × 200 pixels, single-panel drive (1/200 duty
•
First layer (text): 320/8 = 40 characters per line,
200/8 = 25 lines. Required memory size = 40 × 25
= 1000 bytes.
cycle)
•
•
•
•
First layer: text display
Second layer: graphics display
8 × 8-pixel character font
CG RAM not required
•
Second layer (graphics): 320/8 = 40 characters per
line, 200/1 = 200 lines. Required memory size = 40
× 200 = 8000 bytes.
03E8H
2nd graphics layer
(8000 bytes)
0000H
1st character layer
(1000 bytes)
2327H
03E7H
Figure 58. Character over graphics layers
SCROLL
❒ Register setup procedure
SYSTEM SET TC/R calculation
C = 40H
C = 44H
P1 = 00H
P2 = 00H
P3 = C8H
P4 = E8H
P5 = 03H
P6 = C8H
P7 = XH
P8 = XH
P9 = XH
P10 = XH
P1 = 30H
P2 = 87H
P3 = 07H
P4 = 27H
P5 = 2FH
P6 = C7H
P7 = 28H
P8 = 00H
fOSC = 6 MHz
fFR = 70 Hz
(1/6) × 9 × [TC/R] × 200 = 1/70
[TC/R] = 48, so TC/R = 2FH
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EPSON
S1D13305 Series
Technical Manual
APPLICATION NOTES
CSR FORM
C = 5DH
P1 = 04H
P2 = 86H
OVLAY
C = 5BH
P1 = 00H
DISP ON/OFF
C = 59H
P1 = 16H
HDOT SCR
C = 5AH
P1 = 00H
X = Don’t care
16.1.4. Display mode setting example 2: combining graphics and graphics
❒ Conditions
❒ Display memory allocation
•
320 × 200 pixels, single-panel drive (1/ 200 duty
cycle)
•
First layer (graphics): 320/8 = 40 characters per
line, 200/1 = 200 lines. Required memory size = 40
× 200 = 8000 bytes.
•
•
First layer: graphics display
Second layer: graphics display
•
Second layer (graphics): 320/8 = 40 characters per
line, 200/1 = 200 lines. Required memory size =
8000 bytes.
1F40H
2nd graphics layer
(8000 bytes)
0000H
1st graphics layer
(8000 bytes)
3E7FH
1F3FH
Figure 59. Two-layer graphics
S1D13305 Series
Technical Manual
EPSON
73
APPLICATION NOTES
❒ Register setup procedure
CSR FORM
C = 5DH
P1 = 07H
P2 = 87H
SYSTEM SET TC/R calculation
C = 40H
P1 = 30H
P2 = 87H
P3 = 07H
P4 = 27H
P5 = 2FH
P6 = C7H
P7 = 28H
P8 = 00H
fOSC = 6 MHz
fFR = 70 Hz
HDOT SCR
C = 5AH
P1 = 00H
(1/6) × 9 × [TC/R] × 200 = 1/70
[TC/R] = 48, so TC/R = 2FH
OVLAY
C = 5BH
P1 = 0CH
SCROLL
C = 44H
P1 = 00H
P2 = 00H
P3 = C8H
P4 = 40H
P5 = 1FH
P6 = C8H
P7 = XH
P8 = XH
P9 = XH
P10 = XH
DISP ON/OFF
C = 59H
P1 = 16H
X = Don’t care
74
EPSON
S1D13305 Series
Technical Manual
APPLICATION NOTES
16.1.5. Display mode setting example 3: combining three graphics layers
❒ Conditions
❒ Display memory allocation
•
320 × 200 pixels, single-panel drive (1/200 duty
•
All layers (graphics): 320/8 = 40 characters per
line, 200/1 = 200 lines. Required memory size = 40
× 200 = 8000 bytes.
cycle)
•
•
•
First layer: graphics display
Second layer: graphics display
Third layer: graphics display
3E80H
3rd graphics layer
(8000 bytes)
1F40H
2nd graphics layer
(8000 bytes)
5DBFH
0000H
1st graphics layer
(8000 bytes)
3E7FH
1F3FH
Figure 60. Three-layer graphics
❒ Register setup procedure
SCROLL
SYSTEM SET TC/R calculation
C = 44H
P1 = 00H
P2 = 00H
P3 = C8H
P4 = 40H
P5 = 1FH
P6 = C8H
P7 = 80H
P8 = 3EH
P9 = XH
P10 = XH
C = 40H
P1 = 30H
P2 = 87H
P3 = 07H
P4 = 27H
P5 = 2FH
P6 = C7H
P7 = 28H
P8 = 00H
fOSC = 6 MHz
fFR = 70 Hz
(1/6) × 9 × [TC/R] × 200 = 1/70
[TC/R] = 48, so TC/R = 2FH
S1D13305 Series
Technical Manual
EPSON
75
APPLICATION NOTES
CSR FORM
C = 5DH
P1 = 07H
P2 = 87H
OVLAY
C = 5BH
P1 = 1CH
DISP ON/OFF
C = 59H
P1 = 16H
HDOT SCR
C = 5AH
P1 = 00H
X = Don’t care
16.2. System Overview
LCD control circuits are integrated onto the S1D13305
series, few external components are required to construct
a complete medium- resolution liquid crystal display.
Figure 61 shows the S1D13305 series in a typical system.
The microprocessor issues instructions to the S1D13305
series, and the S1D13305 series drives the LCD panel and
may have up to 64KB of display memory. Since all of the
S1D13305 series
External character
generator memory
Character
generator
Display memory
address bus
Micro-
processor
Display memory
Display
address
control
Display memory
data bus
LCD unit
Driver
control
Driver bus
Main
memory
X driver
X driver
X driver
Data bus
Address bus
Control bus
LCD panel
Y driver
Figure 61. System block diagram
76
EPSON
S1D13305 Series
Technical Manual
APPLICATION NOTES
16.3. System Interconnection
16.3.1. S1D13305F
10MHz crystal
HC138
Y7
CS7
CS6
to
XG
XD
A0
A0
VA13
to
VA15
VCE
VRD
VA0
to
A
B
C
Y6
to
Y0
CS0
A1
to
A7
CS
Decoder
VA12
IORQ
VA12
Micro-
processor
A0 to A12
(RAM1)
A0 to A12
(RAM2)
A0 to A11
WE
CS1
CS2
OE
WE
CS1
CS2
OE
OE
D0
to
D7
D0
to
D7
S1D13305F
(CGROM)
D0 to D7
D0 to D7
D0 to D7
CE
RD
RD
WR
RESET
WR
RES
VD0
to
VD7
XD0
to
XD3
RESET
LAT
DI
INH
FR
LCD
YSCL
POFF
V1
V2
V3
V4
V5
Power
supply
converter
FR
EI
FR
EI
FR
EI
E0
E0
VREG
LCD UNIT
Figure 62. System interconnection diagram
S1D13305 Series
Technical Manual
EPSON
77
APPLICATION NOTES
The S1D13305 series layered screens and flexible scroll-
ing facilities support a range of display functions and
reduces the load on the controlling microprocessor when
displaying underlining, inverse display, text overlaid on
graphics or simple animation.
These facilities are supported by the S1D13305 series
ability to divide display memory into up to four different
areas.
❒ CG RAM table
•
Character generator memory can be modified by
the external microprocessor
Character sizes up to 8 × 16-pixels (16 bytes per
character)
Maximum of 64 characters
Table mapping can be changed
•
•
•
❒ CG ROM table
❒ Character code table
•
•
Used when the internal character generator is not
adequate
Can be used in conjunction with the internal char-
acter generator and external character generator
RAM
•
•
•
Contains character codes for text display
Each character requires 8 bits
Table mapping can be changed by using the scroll
start function
❒ Graphics data table
•
Character sizes up to 8 × 16-pixels (16 bytes per
character)
Maximum of 256 characters
Fixed mapping at F000H to FFFFH
•
•
•
Contains graphics bitmaps
Word length is 8 bits
Table mapping can be changed
•
•
78
EPSON
S1D13305 Series
Technical Manual
APPLICATION NOTES
16.4. Smooth Horizontal Scrolling
Figure 63 illustrates smooth display scrolling to the left.
When scrolling left, the screen is effectively moving to
the right, over the larger virtual screen.
To scroll the display to the right, the reverse procedure is
followed.
When the edge of the virtual screen is reached, the
microprocessor must take appropriate steps so that the
display is not corrupted. The scroll must be stopped or the
display modified.
Instead of changing the display start address SAD and
shifting the display by eight pixels, smooth scrolling is
achieved by repeatedly changing the pixel-shift param-
eter of the HDOT SCR command. When the display has
been scrolled seven pixels, the HDOT SCR pixel-shift
parameter is reset to zero and SAD incremented by one.
Repeating this operation at a suitable rate gives the
appearance of smooth scrolling.
Note that the HDOT SCR command cannot be used to
scroll individual layers.
HDOT SCR
parameter
SAD
SAD + 1 SAD + 2
P1 = 00H
P1 = 01H
Magnified
AP
SAD = SAD
P1 = 02H
P1 = 03H
Display
C/R
Virtual screen
P1 = 07H
P1 = 00H
SAD = SAD + 1
Not visible
Visible
Figure 63. HDOT SCR example
Note: TheresponsetimeofLCDpanelschangesconsiderablyat lowtemperatures.Smoothscrollingundertheseconditionsmay
make the display difficult to read.
S1D13305 Series
Technical Manual
EPSON
79
APPLICATION NOTES
16.5. Layered Display Attributes
S1D13305 series incorporates a number of functions for
enhanced displays using monochrome LCD panels. It
allows the display of inverse characters, half-intensity
menu pads and flashing of selected screen areas. These
functions are controlled by the OVLAY and DISP ON/
OFF commands.
Attribute
Reverse
MX1
MX0
Combined layer display
1st layer display
2ndt layer display
0
1
0
1
0
0
1
1
0
1
0
1
EPSON
IV
EPSON
IV
Yes, No
ME
Yes, No
Half-tone
ME
BL
RL
Error
Error
Local flashing
Ruled line
BL
RL
0
0
1
0
1
1
LINE
LINE
LINE
LINE
Figure 64. Layer synthesis
A number of means can be used to achieve these effects,
depending on the display configuration. These are listed
below. Note, however, that not all of these can be used in
the one layer at the same time.
16.5.2. Half-tone display
The FP parameter can be used to generate half-intensity
display by flashing the display at 17 Hz. Note that this
mode of operation may cause flicker problems with
certain LCD panels.
16.5.1. Inverse display
The first layer is text, the second layer is graphics.
16.5.2.1. Menu pad display
Turn flashing off for the first layer, on at 17 Hz for the
second layer, and combine the screens using the OR
function.
1. CSRW, CSDIR, MWRITE
Write is into the graphics screen at the area to be
inverted.
1. OVLAY: P1 = 00H
2. DISP ON/OFF: P1 = 34H
2. OVLAY: MX0 = 1, MX1 = 0
Set the combination of the two layers to Exclusive-
OR.
3. DISP ON/OFF: FP0 = FP1 = 1, FP1 = FP3 = 0.
Turn on layers 1 and 2.
SAD1
SAD2
Half-tone
AB
AB
+
1st layer
2nd layer
Combined layer display
Figure 65. Half-tone character and graphics
80
EPSON
S1D13305 Series
Technical Manual
APPLICATION NOTES
16.5.2.2. Graph display
To present two overlaid graphs on the screen, configure
the display as for the menu bar display and put one graph
on each screen layer. The difference in contrast between
the half- and full-intensity displays will make it easy to
distinguish between the two graphs and help create an
attractive display.
1. OVLAY: P1 = 00H
2. DISP ON/OFF: P1 = 34H
16.5.3. Flashing areas
16.5.3.1 Small area
16.5.3.2. Large area
To flash selected characters, the MPU can alternately
write the characters as character codes and blank charac-
ters at intervals of 0.5 to 1.0 seconds.
Divide both layer 1 and layer 2 into two screen blocks
each, layer 2 being divided into the area to be flashed and
the remainder of the screen. Flash the layer 2 screen
block at 2 Hz for the area to be flashed and combine the
layers using the OR function.
ABC
ABC
XYZ
XYZ
Figure 66. Localized flashing
16.6. 16 × 16-dot Graphic Display
16.6.1. Command usage
16.6.2. Kanji character display
This example shows how to display 16 × 16-pixel
The program for writing large characters operates as
characters. The command sequence is as follows:
follows:
CSRW
Set the cursor address.
1. The microprocessor reads the character data from its
ROM.
CSRDIR Set the cursor auto-increment direction.
MWRITE Write to the display memory.
2. The microprocessor sets the display address and
writes to the VRAM. The flowchart is shown in
Figure 69.
S1D13305 Series
Technical Manual
EPSON
81
APPLICATION NOTES
A0 = 0
A0 = 1
O
8 O7 O6 O5 O4 O3 O2 O1
O8 O7 O6 O5 O4 O3 O2 O1
CG ROM output
0H
1H
2H
3H
4H
5H
6H
7H
8H
9H
AH
BH
CH
DH
EH
FH
(1)
(3)
(2)
(4)
(5)
(6)
(n) shows the CG ROM data
readout order
(7)
(8)
(9)
(10)
(12)
(14)
(16)
(18)
(20)
(22)
(24)
(26)
(28)
(30)
(32)
(11)
(13)
(15)
(17)
(19)
(21)
(23)
(25)
(27)
(29)
(31)
(Kanji ROM pattern)
1st column
2nd column
Scan address A1 to A4
(6)
(4)
(2)
2nd column
(4)
(2)
(19)
(17)
(15)
(13)
(11)
(9)
memory area
1st column
(3)
(1)
(7)
memory area
(5)
(3)
(1)
Data held in the microprocessor memory
Data written into the S1D13305 display memory
Figure 67. Graphics address indexing
82
EPSON
S1D13305 Series
Technical Manual
APPLICATION NOTES
320 dots
Direction of cursor movement
(1)
(3)
(2)
(4)
(5)
(6)
240 dots
(7)
(8)
(9)
(10)
(12)
(14)
(16)
(18)
(20)
(22)
(24)
(26)
(28)
(30)
(32)
(11)
(13)
(15)
(17)
(19)
(21)
(23)
(25)
(27)
(29)
(31)
Figure 68. Graphics bit map
Using an external character generator ROM, and 8 × 16-
pixel font can be used, allowing a 16 × 16-pixel character
to be displayed in two segments. The external CG ROM
EPROM data format is described in Section 9.1. This will
allow the display of up to 128, 16 × 16-pixel characters.
If CG RAM is also used, 96 fixed characters and 32 bank-
switchable characters can also be supported.
Start
Enable cursor downwards movement
Set column 1 cursor address
Write data
Set column 2 cursor address
Write data
End
Figure 69. 16 × 16-dot display flowchart
S1D13305 Series
Technical Manual
EPSON
83
INTERNAL CHARACTER GENERATOR FONT
17. INTERNAL CHARACTER GENERATOR FONT
Character code bits 0 to 3
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
2
3
4
5
6
7
A
B
C
D
1
Figure 70. On-chip character set
Note
The shaded positions indicate characters that have the whole 6 × 8 bitmap blackened.
84
EPSON
S1D13305 Series
Technical Manual
GLOSSARY OF TERMS
18. GLOSSARY OF TERMS
A
Address
AP
C
Address pitch parameter
Character display mode
CD
Cursor direction of movement parameter
CG
Character generator
CGRAM ADR
CM
C/R
CRX
CRY
CSR DIR
CSR FORM
CSRR
CSRW
DM
Character generator memory address
Cursor display shape parameter
Characters per row parameter
Horizontal cursor size parameter
Vertical cursor size parameter
Cursor direction of movement instruction
Cursor size, position and type instruction
Read cursor address register instruction
Write cursor address register instruction
Display mode parameter
FC
Flashing cursor parameter
fFR
fOSC
Frame frequency
Oscillator frequency
FP
Screen flashing parameter
FX
FY
G
Horizontal character size parameter
Vertical character size parameter
Graphics display mode
GLC
HDOT SCR
IV
Graphic line control unit
Horizontal scrolling by pixels instruction
Screen origin compensation for inverse display
Lines per frame instruction
Display memory read instruction
Display memory write instruction
Screen composition mode
L/F
MREAD
MWRITE
MX
OV
OVLAY
P
Graphics layer select parameter
Screen layer mode instruction
Parameter
R
Row
RAM
ROM
SAD
SL
TC/R
VRAM
WF
Random access memory
Read only memory
Display scrolling start address parameter
Display scrolling length parameter
Length, including horizontal blanking, of one screen line
Display memory
Display drive waveform parameter
W/S
Windows per screen parameter
S1D13305 Series
Technical Manual
EPSON
85
Request for Information on S1D13305 Series
Company:
Dated:__________, 19____
Name of the inquiring person:
The phenomenon occurred on:
Desired date of receiving the reply: ______________
Device name: S1D13305F00A/ S1D13305F00B
Number of units of the device causing the phenomenon: __units
(Scope of occurrence: ___ / ___)
(Lot No.
)
Applications:
Your address:
Documents in your current possession:
Your phone number:
-
-
FAX:
-
-
Image plane size: ____ dots × ____ dots (single-plane drive/2-plane drive)
Using LCD module (manufacturer):
Display mode (circle either one)
Frame frequency:
Hz.
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
(1) First layer: Characters Two-part plane, Second layer: Graphics Single plane
(2) First layer: Characters Single plane,
Second layer: Graphics Single plane
< (1)' >
(3) First layer: Characters Two-part plane, Second layer: Graphics Two-part plane
(4) First layer: Graphics Two-part plane, Second layer: Graphics Single plane
(5) First layer: Graphics Single plane,
(6) First layer: Graphics Single plane,
Second layer: Graphics Single plane
Second layer: Graphics Single plane,
< (4)' >
Third layer: Graphics Single plane
(7) First layer: Graphics Two-part plane, Second layer: Graphics Two-part plane
Initialization parameter: Give in decimals or duodecimals.
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
System setting
P1(IV, W/S, M2, M1, M0)
P2(W/F, FX)
P3(FY)
Scroll
HDOT SCR
P1
OVLAY
P1
DISP ON/OFF
CSRFORM
=
=
=
=
=
=
=
=
P1(SADIL)
P2(SADIH)
P3(SL1)
=
=
=
=
=
P1
P2
=
=
=
P4(C/R)
P4(SAD2L)
P5(TC/R)
P5(SAD2H) =
P1
=
P6(L/F)
P6(SL2)
=
=
CSRW
P1
P7(APL)
P7(SAD3L)
=
=
P8(APH)
P8(SAD3H) =
P9(SAD4L)
P2
=
CSR DIR
P10(SAD4H) =
C
=
Oscillation frequency:
CPU:
MHz. (internal/external)
CPU clock:
MHz.
Frame memory capacity:
Kb.
(using memory IC:
, access time:
nsec.)
Descriptions of your inquiry (Give details such as what type of display is being sought for and which phenomenon is occurring.)
Attached documents (circuit diagram, timing chart, program list, or others)
86
EPSON
S1D13305 Series
Technical Manual
S1D13305 Series
Technical Manual
ELECTRONIC DEVICES MARKETING DIVISION
EPSON Electronic Devices Website
http://www.epson.co.jp/device/
First issue April,1998 D
C
This manual was made with recycle papaer,
and printed using soy-based inks.
Printed March, 2001 in Japan
A
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800X480 PIXELS DOT MAT LCD DSPL CTLR, PQFP100, 14 X14 MM, 1.70 MM HEIGHT, QFP-100
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