UPD4564163G5 [ELPIDA]
64M-bit Synchronous DRAM 4-bank, LVTTL; 64M位同步DRAM 4银行， LVTTL
| 型号： | UPD4564163G5 |
| 厂家： | 
ELPIDA MEMORY |
| 描述： | 64M-bit Synchronous DRAM 4-bank, LVTTL |
| 文件： | 总85页 (文件大小：903K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD4564441, 4564841, 4564163
64M-bit Synchronous DRAM
4-bank, LVTTL
Description
The µPD4564441, 4564841, 4564163 are high-speed 67,108,864-bit synchronous dynamic random-access
memories, organized as 4,194,304 × 4 × 4, 2,097,152 × 8 × 4, 1,048,576 ×16 × 4 (word × bit × bank), respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
These products are packaged in 54-pin TSOP (II).
Features
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by A12 and A13 (Bank Select)
• Byte control (×16) by LDQM and UDQM
• Programmable Wrap sequence (Sequential / Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable /CAS latency (2 and 3)
• Automatic precharge and controlled precharge
• CBR (auto) refresh and self refresh
• ×4, ×8, ×16 organization
• Single 3.3 V ± 0.3 V power supply
• LVTTL compatible inputs and outputs
• 4,096 refresh cycles / 64 ms
• Burst termination by Burst stop command and Precharge command
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Document No. E0149N10 (Ver.1.0)
(Previous No. M12621EJCV0DS00)
Date Published August 2001 (K)
Printed in Japan
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
µPD4564441, 4564841, 4564163
Ordering Information
Organization
(word × bit × bank)
Clock frequency
Package
Part number
MHz (MAX.)
µPD4564441G5-A80-9JF
µPD4564441G5-A10-9JF
µPD4564441G5-A10B-9JF
µPD4564841G5-A80-9JF
µPD4564841G5-A10-9JF
µPD4564841G5-A10B-9JF
µPD4564163G5-A80-9JF
µPD4564163G5-A10-9JF
µPD4564163G5-A10B-9JF
4M × 4 × 4
2M × 8 × 4
1M × 16 × 4
125
100
100
125
100
100
125
100
100
54-pin Plastic TSOP (II)
(10.16mm (400))
2
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
Part Number
[ x4, x8 ]
µ
PD4564841G5 - A80
NEC Memory
Synchronous DRAM
Memory density
64 : 64M bits
Minimum cycle time
80 : 8 ns (125 MHz)
10 : 10 ns (100 MHz)
10B : 10 ns (100 MHz)
Organization
4 : x4
8 : x8
Number of banks
4 : 4 banks
Low voltage
Interface
1 : LVTTL
A : 3.3
± 0.3 V
Package
G5 : TSOP (II)
[ x16 ]
163
Organization
16 : x16
Number of banks
and Interface
3 : 4 banks, LVTTL
3
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
Pin Configurations
/xxx indicates active low signal.
[µPD4564441]
54-pin Plastic TSOP (II) (10.16mm (400))
4M words × 4 bits × 4 banks
V
NC
CC
1
2
3
4
5
6
7
8
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Vss
NC
VssQ
NC
DQ3
VccQ
NC
NC
VssQ
NC
DQ2
VccQ
NC
Vss
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
V
CC
Q
NC
DQ0
V
SS
Q
NC
NC
Q
V
CC
9
NC
DQ1
VSSQ
NC
V
NC
/WE
/CAS
/RAS
/CS
A13
A12
A10
A0
A1
A2
A3
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
CC
A4
Vss
CC
A0 to A13 Note : Address inputs
DQ0 to DQ3 : Data inputs / outputs
CLK
CKE
/CS
: Clock input
: Clock enable
: Chip select
/RAS
/CAS
/WE
DQM
VCC
: Row address strobe
: Column address strobe
: Write enable
: DQ mask enable
: Supply voltage
: Ground
VSS
Note A0 to A11 : Row address inputs
A0 to A9 : Column address inputs
A12, A13 : Bank select
VCCQ
VSSQ
NC
: Supply voltage for DQ
: Ground for DQ
: No connection
4
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
[µPD4564841]
54-pin Plastic TSOP (II) (10.16mm (400))
2M words × 8 bits × 4 banks
V
DQ0
CC
1
2
3
4
5
6
7
8
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Vss
DQ7
VssQ
NC
DQ6
VccQ
NC
DQ5
VssQ
NC
DQ4
VccQ
NC
Vss
NC
DQM
CLK
CKE
NC
A11
A9
A8
V
CC
Q
NC
DQ1
V
SS
Q
NC
DQ2
V
CC
Q
9
NC
DQ3
VSSQ
NC
V
NC
/WE
/CAS
/RAS
/CS
A13
A12
A10
A0
A1
A2
A3
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
CC
A7
A6
A5
A4
CC
Vss
A0 to A13 Note : Address inputs
DQ0 to DQ7 : Data inputs / outputs
CLK
CKE
/CS
: Clock input
: Clock enable
: Chip select
/RAS
/CAS
/WE
DQM
VCC
: Row address strobe
: Column address strobe
: Write enable
: DQ mask enable
: Supply voltage
: Ground
VSS
Note A0 to A11 : Row address inputs
A0 to A8 : Column address inputs
A12, A13 : Bank select
VCCQ
VSSQ
NC
: Supply voltage for DQ
: Ground for DQ
: No connection
5
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
[µPD4564163]
54-pin Plastic TSOP (II) (10.16mm (400))
1M words × 16 bits × 4 banks
V
DQ0
CC
1
2
3
4
5
6
7
8
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Vss
DQ15
VssQ
DQ14
DQ13
VccQ
DQ12
DQ11
VssQ
DQ10
DQ9
VccQ
DQ8
Vss
V
CC
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
CC
Q
9
DQ5
DQ6
VSSQ
DQ7
V
LDQM
/WE
/CAS
/RAS
/CS
A13
A12
A10
A0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
CC
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A1
A2
A3
V
A4
Vss
CC
A0 to A13 Note : Address inputs
DQ0 to DQ15 : Data inputs / outputs
CLK
CKE
/CS
: Clock input
: Clock enable
: Chip select
/RAS
/CAS
/WE
LDQM
UDQM
VCC
: Row address strobe
: Column address strobe
: Write enable
: Lower DQ mask enable
: Upper DQ mask enable
: Supply voltage
: Ground
VSS
Note A0 to A11 : Row address inputs
A0 to A7 : Column address inputs
A12, A13 : Bank select
VCCQ
VSSQ
NC
: Supply voltage for DQ
: Ground for DQ
: No connection
6
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
Block Diagram
CLK
Clock
Generator
CKE
Bank D
Bank C
Bank B
Row
Address
Address
Buffer
&
Refresh
Counter
Mode
Register
Bank A
Sense Amplifier
DQM
/CS
Column Decoder &
Latch Circuit
Column
Address
Buffer
&
Burst
Counter
/RAS
/CAS
/WE
Data Control Circuit
DQ
7
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
CONTENTS
1. Input / Output Pin Function ........................................................................................................... 10
2. Commands ...................................................................................................................................... 11
3. Simplified State Diagram ............................................................................................................... 14
4. Truth Table ...................................................................................................................................... 15
4.1 Command Truth Table............................................................................................................................ 15
4.2 DQM Truth Table ..................................................................................................................................... 15
4.3 CKE Truth Table...................................................................................................................................... 15
4.4 Operative Command Table .................................................................................................................... 16
4.5 Command Truth Table for CKE ............................................................................................................. 19
5. Initialization ..................................................................................................................................... 20
6. Programming the Mode Register .................................................................................................. 21
7. Mode Register ................................................................................................................................. 22
7.1 Burst Length and Sequence ................................................................................................................. 23
8. Address Bits of Bank-Select and Precharge ................................................................................ 24
9. Precharge ........................................................................................................................................ 25
10. Auto Precharge ............................................................................................................................... 26
10.1 Read with Auto Precharge .................................................................................................................. 26
10.2 Write with Auto Precharge ................................................................................................................. 27
11. Read / Write Command Interval .................................................................................................... 28
11.1 Read to Read Command Interval ....................................................................................................... 28
11.2 Write to Write Command Interval ....................................................................................................... 28
11.3 Write to Read Command Interval ....................................................................................................... 29
11.4 Read to Write Command Interval ....................................................................................................... 30
12. Burst Termination ........................................................................................................................... 31
12.1 Burst Stop Command ......................................................................................................................... 31
12.2 Precharge Termination ....................................................................................................................... 32
12.2.1 Precharge Termination in READ Cycle ................................................................................... 32
12.2.2 Precharge Termination in WRITE Cycle ................................................................................. 33
8
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
13. Electrical Specifications ................................................................................................................ 34
13.1 AC Parameters for Read Timing ........................................................................................................ 39
13.2 AC Parameters for Write Timing ........................................................................................................ 41
13.3 Relationship between Frequency and Latency ................................................................................. 42
13.4 Mode Register Set ............................................................................................................................... 43
13.5 Power on Sequence and CBR (auto) Refresh ................................................................................... 44
13.6 /CS Function ........................................................................................................................................ 45
13.7 Clock Suspension during Burst Read (using CKE Function) ......................................................... 46
13.8 Clock Suspension during Burst Write (using CKE Function) ......................................................... 48
13.9 Power Down Mode and Clock Mask .................................................................................................. 50
13.10 CBR (auto) Refresh ............................................................................................................................. 51
13.11 Self Refresh (Entry and Exit) .............................................................................................................. 52
13.12 Random Column Read (Page with Same Bank) ............................................................................... 53
13.13 Random Column Write (Page with Same Bank) ............................................................................... 55
13.14 Random Row Read (Ping-Pong Banks) ............................................................................................ 57
13.15 Random Row Write (Ping-Pong Banks) ............................................................................................ 59
13.16 Read and Write .................................................................................................................................... 61
13.17 Interleaved Column Read Cycle ......................................................................................................... 63
13.18 Interleaved Column Write Cycle ......................................................................................................... 65
13.19 Auto Precharge after Read Burst ....................................................................................................... 67
13.20 Auto Precharge after Write Burst ....................................................................................................... 69
13.21 Full Page Read Cycle .......................................................................................................................... 71
13.22 Full Page Write Cycle .......................................................................................................................... 73
13.23 Byte Write Operation ........................................................................................................................... 75
13.24 Burst Read and Single Write (Option) ............................................................................................... 76
13.25 Full Page Random Column Read ....................................................................................................... 77
13.26 Full Page Random Column Write ....................................................................................................... 78
13.27 PRE (Precharge) Termination of Burst .............................................................................................. 79
14. Package Drawing ............................................................................................................................ 81
15. Recommended Soldering Conditions .......................................................................................... 82
16. Revision History ............................................................................................................................. 83
9
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
1. Input / Output Pin Function
Pin name
Input / Output
Input
Function
CLK
CKE
CLK is the master clock input. Other inputs signals are referenced to the CLK rising
edge.
Input
CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising
edge is valid; otherwise it is invalid. If the CLK rising edge is invalid, the internal clock
is not issued and the µPD4564xxx suspends operation.
When the µPD4564xxx is not in burst mode and CKE is negated, the device enters
power down mode. During power down mode, CKE must remain low.
/CS
Input
Input
Input
/CS low starts the command input cycle. When /CS is high, commands are ignored
but operations continue.
/RAS, /CAS, /WE
A0 - A13
/RAS, /CAS and /WE have the same symbols on conventional DRAM but different
functions. For details, refer to the command table.
Row Address is determined by A0 - A13 at the CLK (clock) rising edge in the active
command cycle. It does not depend on the bit organization.
Column Address is determined by A0 - A9 at the CLK rising edge in the read or write
command cycle. It depends on the bit organization: A0 - A9 for ×4 device, A0 - A8 for
×8 device, A0 - A7 for ×16 device.
A12 and A13 are the bank select signal (BS). In command cycle, A12 and A13 low
select bank A, A12 low and A13 high select bank B, A12 high and A13 low select bank
C and then A12 and A13 high select bank D.
A10 defines the precharge mode. When A10 is high in the precharge command cycle,
all banks are precharged; when A10 is low, only the bank selected by A12 and A13 is
precharged.
When A10 is high in read or write command cycle, the precharge starts automatically
after the burst access.
DQM, UDQM,
LDQM
Input
DQM controls I/O buffers. In ×16 products, UDQM and LDQM control upper byte and
lower byte I/O buffers, respectively.
In read mode, DQM controls the output buffers like a conventional /OE pin.
DQM high and DQM low turn the output buffers off and on, respectively.
The DQM latency for the read is two clocks.
In write mode, DQM controls the word mask. Input data is written to the memory cell if
DQM is low but not if DQM is high.
The DQM latency for the write is zero.
DQ0 - DQ15
Input / Output
(Power supply)
DQ pins have the same function as I/O pins on a conventional DRAM.
VCC, VSS, VCCQ,
VSSQ
VCC and VSS are power supply pins for internal circuits. VCCQ and VSSQ are power
supply pins for the output buffers.
10
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
2. Commands
Fig.1 Mode register set command
Mode register set command
CLK
(/CS, /RAS, /CAS, /WE = Low)
CKE
/CS
H
The µPD4564xxx has a mode register that defines how the device
operates. In this command, A0 through A13 are the data input pins.
After power on, the mode register set command must be executed to
initialize the device.
/RAS
/CAS
/WE
The mode register can be set only when all banks are in idle state.
During 2 CLK (tRSC) following this command, the µPD4564xxx cannot
accept any other commands.
A12, A13
A10
Add
Fig.2 Row address strobe and
bank activate command
Activate command
(/CS, /RAS = Low, /CAS, /WE = High)
CLK
CKE
/CS
H
The µPD4564xxx has four banks, each with 4,096 rows.
This command activates the bank selected by A12 and A13 (BS) and a
row address selected by A0 through A11.
/RAS
/CAS
/WE
This command corresponds to a conventional DRAM’s /RAS falling.
A12, A13
(Bank select)
A10
Add
Row
Row
Precharge command
Fig.3 Precharge command
(/CS, /RAS, /WE = Low, /CAS = High)
CLK
CKE
/CS
H
This command begins precharge operation of the bank selected by
A12 and A13 (BS). When A10 is High, all banks are precharged,
regardless of A12 and A13. When A10 is Low, only the bank selected
by A12 and A13 is precharged.
/RAS
/CAS
/WE
After this command, the µPD4564xxx can’t accept the activate
command to the precharging bank during tRP (precharge to activate
command period).
A12, A13
(Bank select)
A10
This command corresponds to a conventional DRAM’s /RAS rising.
(Precharge select)
Add
11
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
Write command
Fig.4 Column address and write
command
(/CS, /CAS, /WE = Low, /RAS = High)
CLK
CKE
/CS
H
If the mode register is in the burst write mode, this command sets the
burst start address given by the column address to begin the burst write
operation. The first write data in burst mode can input with this
command with subsequent data on following clocks.
/RAS
/CAS
/WE
A12, A13
(Bank select)
A10
Add
Col.
Read command
Fig.5 Column address and read
command
(/CS, /CAS = Low, /RAS, /WE = High)
CLK
CKE
/CS
H
Read data is available after /CAS latency requirements have been met.
This command sets the burst start address given by the column
address.
/RAS
/CAS
/WE
A12, A13
(Bank select)
A10
Add
Col.
CBR (auto) refresh command
Fig.6 CBR (auto) refresh command
CLK
(/CS, /RAS, /CAS = Low, /WE, CKE = High)
CKE
/CS
H
This command is a request to begin the CBR (auto) refresh operation.
The refresh address is generated internally.
/RAS
/CAS
/WE
Before executing CBR (auto) refresh, all banks must be precharged.
After this cycle, all banks will be in the idle (precharged) state and
ready for a row activate command.
A12, A13
(Bank select)
During tRC period (from refresh command to refresh or activate
command), the µPD4564xxx cannot accept any other command.
A10
Add
12
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
Self refresh entry command
Fig.7 Self refresh entry command
CLK
CKE
/CS
(/CS, /RAS, /CAS, CKE = Low, /WE = High)
After the command execution, self refresh operation continues while
CKE remains low. When CKE goes high, the µPD4564xxx exits the self
refresh mode.
/RAS
/CAS
/WE
During self refresh mode, refresh interval and refresh operation are
performed internally, so there is no need for external control.
Before executing self refresh, all banks must be precharged.
A12, A13
(Bank select)
A10
Add
Burst stop command
Fig.8 Burst stop command in Full
Page Mode
(/CS, /WE = Low, /RAS, /CAS = High)
This command can stop the current burst operation.
CLK
CKE
H
/CS
/RAS
/CAS
/WE
A12, A13
(Bank select)
A10
Add
No operation
Fig.9 No operation
CLK
(/CS = Low, /RAS, /CAS, /WE = High)
CKE
/CS
H
This command is not an execution command. No operations begin or
terminate by this command.
/RAS
/CAS
/WE
A12, A13
(Bank select)
A10
Add
13
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
3. Simplified State Diagram
Self
Refresh
MRS
Mode
Register
Set
REF
CBR (auto)
Refresh
IDLE
Power
Down
CKE
CKE
Active
Power
Down
ROW
ACTIVE
Write
Read
CKE
Read
CKE
WRITE
WRITE
READ
SUSPEND
READ
SUSPEND
Write
CKE
CKE
CKE
CKE
CKE
READA
SUSPEND
WRITEA
WRITEA
READA
SUSPEND
CKE
Precharge
POWER
ON
Precharge
Automatic sequence
Manual input
14
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
4. Truth Table
4.1 Command Truth Table
Function
Symbol
CKE
/CS
/RAS
/CAS
/WE
A12,
A13
×
A10
A11,
n – 1
H
n
×
×
×
×
×
×
×
×
×
×
×
A9 - A0
Device deselect
No operation
DESL
NOP
H
L
L
L
L
L
L
L
L
L
L
×
H
H
H
H
H
H
L
×
H
H
L
×
H
L
×
×
×
×
H
×
Burst stop
BST
H
×
×
×
Read
READ
READA
WRIT
WRITA
ACT
H
H
H
L
V
L
V
V
V
V
V
×
Read with auto precharge
Write
H
L
V
H
L
H
L
V
Write with auto precharge
Bank activate
H
L
L
V
H
V
L
H
H
H
H
L
H
L
V
Precharge select bank
Precharge all banks
Mode register set
PRE
H
L
V
PALL
MRS
H
L
L
×
H
L
×
H
L
L
L
V
Remark H = High level, L = Low level, × = High or Low level (Don't care), V = Valid data input
4.2 DQM Truth Table
Function
Symbol
CKE
DQM
n – 1
H
n
×
×
×
×
×
×
U
L
Data write / output enable
ENB
L
Data mask / output disable
MASK
ENBU
ENBL
MASKU
MASKL
H
H
Upper byte write enable / output enable
Lower byte write enable / output enable
Upper byte write inhibit / output disable
Lower byte write inhibit / output disable
H
L
×
×
L
H
H
H
×
×
H
H
Remark H = High level, L = Low level, × = High or Low level (Don't care)
4.3 CKE Truth Table
Current state
Function
Symbol
CKE
/CS
/RAS
/CAS
/WE Address
n – 1
H
L
n
L
Activating
Any
Clock suspend mode entry
Clock suspend mode
Clock suspend mode exit
CBR (auto) refresh command
Self refresh entry
×
×
×
L
L
L
H
×
H
L
×
×
×
L
L
H
×
×
×
H
×
×
×
L
L
H
×
×
×
H
×
×
×
×
×
×
×
×
×
×
×
×
L
Clock suspend
Idle
L
H
H
L
×
REF
H
H
L
H
H
H
×
Idle
SELF
Self refresh
Self refresh exit
H
H
L
L
Idle
Power down entry
Power down exit
H
L
×
Power down
H
H
×
L
H
Remark H = High level, L = Low level, × = High or Low level (Don't care)
15
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
4.4 Operative Command Table Note1
(1/3)
Current state
Idle
/CS /RAS /CAS /WE
Address
Command
DESL
NOP or BST
Action
Nop or power down
Nop or power down
Notes
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
×
H
H
H
L
×
H
L
×
×
×
×
2
2
3
3
H
L
BA, CA, A10 READ/READA ILLEGAL
L
BA, CA, A10 WRIT/WRITA
ILLEGAL
H
H
L
H
L
BA, RA
ACT
Row activating
L
BA, A10
PRE/PALL
REF/SELF
MRS
Nop
L
H
L
×
CBR (auto) refresh or self refresh
4
L
L
Op-Code
Mode register accessing
Row active
×
×
×
×
×
DESL
Nop
Nop
H
H
H
L
H
L
×
NOP or BST
H
L
BA, CA, A10 READ/READA Begin read : Determine AP
5
5
3
6
L
BA, CA, A10 WRIT/WRITA
Begin write : Determine AP
ILLEGAL
H
H
L
H
L
BA, RA
ACT
L
BA, A10
PRE/PALL
REF/SELF
MRS
Precharge
L
H
L
×
ILLEGAL
L
L
Op-Code
ILLEGAL
Read
×
×
×
×
×
×
DESL
Continue burst to end → Row active
Continue burst to end → Row active
Burst stop → Row active
H
H
H
H
L
H
H
L
H
L
NOP
BST
H
L
BA, CA, A10 READ/READA Terminate burst, new read : Determine AP
7
7, 8
3
L
BA, CA, A10 WRIT/WRITA
Terminate burst, start write : Determine AP
ILLEGAL
H
H
L
H
L
BA, RA
ACT
L
BA, A10
PRE/PALL
REF/SELF
MRS
Terminate burst, precharging
ILLEGAL
L
H
L
×
L
L
Op-Code
ILLEGAL
Write
×
×
×
×
×
×
DESL
Continue burst to end → Write recovering
Continue burst to end → Write recovering
Burst stop → Row active
H
H
H
H
L
H
H
L
H
L
NOP
BST
H
L
BA, CA, A10 READ/READA Terminate burst, start read : Determine AP
7, 8
7
L
BA, CA, A10 WRIT/WRITA
Terminate burst, new write : Determine AP
H
H
L
H
L
BA, RA
BA, A10
×
ACT
ILLEGAL
3
L
PRE/PALL
REF/SELF
MRS
Terminate burst, precharging
ILLEGAL
9
L
H
L
L
L
Op-Code
ILLEGAL
16
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
(2/3)
Current state
Read with auto
precharge
/CS /RAS /CAS /WE
Address
Command
DESL
Action
Notes
H
L
L
L
L
L
L
L
L
×
H
H
H
H
L
×
H
H
L
×
H
L
×
×
×
Continue burst to end → Precharging
Continue burst to end → Precharging
ILLEGAL
NOP
BST
H
L
BA, CA, A10 READ/READA ILLEGAL
3
3
3
3
L
BA, CA, A10 WRIT/WRITA
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
H
H
L
H
L
BA, RA
BA, A10
×
ACT
L
PRE/PALL
REF/SELF
MRS
L
H
L
L
L
Op-Code
×
Write with auto
precharge
H
×
×
×
DESL
Continue burst to end → Write
recovering with auto precharge
L
H
H
H
×
×
NOP
BST
Continue burst to end → Write
recovering with auto precharge
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
H
H
L
H
L
L
H
L
ILLEGAL
BA, CA, A10 READ/READA ILLEGAL
3
3
3
3
L
BA, CA, A10 WRIT/WRITA
ILLEGAL
H
H
L
H
L
BA, RA
ACT
ILLEGAL
L
BA, A10
PRE/PALL
REF/SELF
MRS
ILLEGAL
L
H
L
×
ILLEGAL
L
L
Op-Code
ILLEGAL
Precharging
×
×
×
×
×
×
DESL
Nop → Enter idle after tRP
Nop → Enter idle after tRP
ILLEGAL
H
H
H
H
L
H
H
L
H
L
NOP
BST
H
L
BA, CA, A10 READ/READA ILLEGAL
3
3
3
L
BA, CA, A10 WRIT/WRITA
ILLEGAL
H
H
L
H
L
BA, RA
ACT
ILLEGAL
L
BA, A10
PRE/PALL
REF/SELF
MRS
Nop → Enter idle after tRP
ILLEGAL
L
H
L
×
L
L
Op-Code
ILLEGAL
Row activating
×
×
×
×
×
×
DESL
Nop → Enter bank active after tRCD
Nop → Enter bank active after tRCD
ILLEGAL
H
H
H
H
L
H
H
L
H
L
NOP
BST
H
L
BA, CA, A10 READ/READA ILLEGAL
3
3
L
BA, CA, A10 WRIT/WRITA
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
H
H
L
H
L
BA, RA
BA, A10
×
ACT
3, 10
3
L
PRE/PALL
REF/SELF
MRS
L
H
L
L
L
Op-Code
17
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
(3/3)
Current state
/CS /RAS /CAS /WE
Address
Command
DESL
Action
Notes
Write recovering
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
×
H
H
H
H
L
×
H
H
L
×
H
L
×
×
×
Nop → Enter row active after tDPL
Nop → Enter row active after tDPL
Nop → Enter row active after tDPL
NOP
BST
H
L
BA, CA, A10 READ/READA Start read, Determine AP
8
L
BA, CA, A10 WRIT/WRITA
New write, Determine AP
ILLEGAL
H
H
L
H
L
BA, RA
ACT
3
3
L
BA, A10
PRE/PALL
REF/SELF
MRS
ILLEGAL
L
H
L
×
ILLEGAL
L
L
Op-Code
ILLEGAL
Write recovering
×
×
×
H
L
×
×
×
DESL
Nop → Enter precharge after tDPL
Nop → Enter precharge after tDPL
Nop → Enter precharge after tDPL
with auto precharge
H
H
H
H
L
H
H
L
NOP
BST
H
L
BA, CA, A10 READ/READA ILLEGAL
3, 8
3
L
BA, CA, A10 WRIT/WRITA
ILLEGAL
H
H
L
H
L
BA, RA
ACT
ILLEGAL
3
L
BA, A10
PRE/PALL
REF/SELF
MRS
ILLEGAL
L
H
L
×
ILLEGAL
L
L
Op-Code
ILLEGAL
Refreshing
×
×
×
×
×
×
×
×
H
L
×
×
×
×
×
×
×
×
×
×
DESL
Nop → Enter idle after tRC
Nop → Enter idle after tRC
ILLEGAL
H
H
L
H
L
NOP/BST
READ/WRIT
ACT/PRE/PALL
REF/SELF/MRS
DESL
H
L
ILLEGAL
L
ILLEGAL
Mode register
accessing
×
×
Nop → Enter idle after tRSC
Nop → Enter idle after tRSC
ILLEGAL
H
H
H
H
H
L
NOP
BST
×
READ/WRIT
ILLEGAL
L
L
×
×
ACT/PRE/PALL/ ILLEGAL
REF/SELF/MRS
Notes 1.
2.
All entries assume that CKE was active (High level) during the preceding clock cycle.
If all banks are idle, and CKE is inactive (Low level), µPD4564xxx will enter Power down mode.
All input buffers except CKE will be disabled.
3.
4.
Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA),
depending on the state of that bank.
If all banks are idle, and CKE is inactive (Low level), µPD4564xxx will enter Self refresh mode. All input
buffers except CKE will be disabled.
5.
6.
7.
8.
9.
Illegal if tRCD is not satisfied.
Illegal if tRAS is not satisfied.
Must satisfy burst interrupt condition.
Must satisfy bus contention, bus turn around, and/or write recovery requirements.
Must mask preceding data which don't satisfy tDPL.
10. Illegal if tRRD is not satisfied.
Remark H = High level, L = Low level, × = High or Low level (Don’t care), V = Valid data
18
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
4.5 Command Truth Table for CKE
Current State
CKE
n – 1
/CS /RAS /CAS /WE Address
Action
Notes
n
×
Self refresh
H
L
×
H
L
L
L
×
H
L
L
L
H
L
L
L
×
H
L
×
H
L
L
L
L
H
L
L
L
L
×
×
×
×
×
×
×
×
×
H
H
L
×
×
H
H
L
×
H
H
L
×
×
H
×
×
H
L
L
L
×
H
L
L
L
×
×
×
×
×
×
×
×
×
H
L
×
×
×
H
L
×
×
H
L
×
×
×
H
×
×
×
H
L
L
×
×
H
L
L
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
H
×
×
×
×
H
L
×
×
×
H
L
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
INVALID, CLK (n-1) would exit self refresh
Self refresh recovery
Self refresh recovery
ILLEGAL
H
H
H
H
L
L
L
L
ILLEGAL
L
Maintain self refresh
Idle after tRC
Self refresh recovery
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
Idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
L
ILLEGAL
L
ILLEGAL
L
ILLEGAL
Power down
All banks idle
×
INVALID, CLK (n – 1) would exit power down
EXIT power down → Idle
EXIT power down → Idle
Maintain power down mode
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
CBR (auto) refresh
H
H
L
×
×
×
L
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
×
Op-Code Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
L
L
L
×
Self refresh
1
1
1
2
L
Op-Code Refer to operations in Operative Command Table
×
×
×
×
Power down
Row active
H
L
×
Refer to operations in Operative Command Table
Power down
×
Any state other than
listed above
H
H
L
H
L
Refer to operations in Operative Command Table
Begin clock suspend next cycle
Exit clock suspend next cycle
Maintain clock suspend
×
×
×
H
L
L
Notes 1. Self refresh can be entered only from the all banks idle state. Power down can be entered only from all
banks idle or row active state.
2. Must be legal command as defined in Operative Command Table.
Remark H = High level, L = Low level, × = High or Low level (Don't care)
19
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
5. Initialization
The synchronous DRAM is initialized in the power-on sequence according to the following.
(1) To stabilize internal circuits, when power is applied, a 100 µs or longer pause must precede any signal toggling.
(2) After the pause, all banks must be precharged using the Precharge command (The Precharge all banks
command is convenient).
(3) Once the precharge is completed and the minimum tRP is satisfied, the mode register can be programmed.
After the mode register set cycle, tRSC (2 CLK minimum) pause must be satisfied as well.
(4) Two or more CBR (auto) refresh must be performed.
Remarks 1. The sequence of Mode register programming and Refresh above may be transposed.
2. CKE and DQM must be held high until the Precharge command is issued to ensure data-bus Hi-Z.
20
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
6. Programming the Mode Register
The mode register is programmed by the Mode register set command using address bits A13 through A0 as data
inputs. The register retains data until it is reprogrammed or the device loses power.
The mode register has four fields;
Options
/CAS latency : A6 through A4
Wrap type : A3
: A13 through A7
Burst length : A2 through A0
Following mode register programming, no command can be issued before at least 2 CLK have elapsed.
/CAS Latency
/CAS latency is the most critical of the parameters being set. It tells the device how many clocks must elapse
before the data will be available.
The value is determined by the frequency of the clock and the speed grade of the device. 13.3 Relationship
between Frequency and Latency shows the relationship of /CAS latency to the clock period and the speed grade of
the device.
Burst Length
Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is
completed, the output bus will become Hi-Z.
The burst length is programmable as 1, 2, 4, 8 or full page.
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data will be addressed. This order is programmable as either
“Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system.
Some microprocessor cache systems are optimized for sequential addressing and others for interleaved
addressing. 7.1 Burst Length and Sequence shows the addressing sequence for each burst length using them.
Both sequences support bursts of 1, 2, 4 and 8. Additionally, sequence supports the full page length.
21
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
7. Mode Register
13
0
12
0
11
0
10
0
9
0
8
0
7
1
6
6
6
5
4
4
4
3
2
2
2
1
0
JEDEC Standard Test Set (refresh counter test)
13
x
12
x
11
x
10
x
9
1
8
0
7
0
5
3
1
0
0
LTMODE
WT
BL
Burst Read and Single Write
(for Write Through Cache)
13
12
11
10
9
8
1
7
0
5
3
1
Use in future
13
x
12
x
11
x
10
x
9
x
8
1
7
1
6
5
4
3
2
1
0
V
V
V
V
V
V
V
Vender Specific
V = Valid
x = Don’t care
13
0
12
0
11
0
10
0
9
0
8
0
7
0
6
5
4
3
2
1
0
LTMODE
WT
BL
Mode Register Set
Bits2-0
000
001
010
011
100
101
110
111
WT = 0
WT = 1
1
1
2
2
4
4
Burst length
8
8
R
R
R
R
R
R
R
Full page
0
1
Sequential
Interleave
Wrap type
Bits6-4
000
001
010
011
100
101
110
111
/CAS latency
R
R
2
3
Latency
mode
R
R
R
R
Remark R : Reserved
Mode Register Set Timing
CLK
CKE
/CS
/RAS
/CAS
/WE
A0 - A13
Mode Register Set
22
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
7.1 Burst Length and Sequence
[Burst of Two]
Starting address
(column address A0, binary)
Sequential addressing sequence
(decimal)
Interleave addressing sequence
(decimal)
0
1
0, 1
1, 0
0, 1
1, 0
[Burst of Four]
Starting address
(column address A1 - A0, binary)
Sequential addressing sequence
(decimal)
Interleave addressing sequence
(decimal)
00
01
10
11
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
[Burst of Eight]
Starting address
(column address A2 - A0, binary)
Sequential addressing sequence
(decimal)
Interleave addressing sequence
(decimal)
000
001
010
011
100
101
110
111
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
Full page burst is an extension of the above tables of sequential addressing, with the length being 1,024 (for 16M ×4
device), 512 (for 8M ×8 device), and 256 (for 4M ×16 device).
23
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
8. Address Bits of Bank-Select and Precharge
A12 A13
Result
Row
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9 A10 A11 A12 A13
Select Bank A
“Activate” command
0
0
1
1
0
1
0
1
(Activate command)
Select Bank B
“Activate” command
Select Bank C
“Activate” command
Select Bank D
“Activate” command
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9 A10 A11 A12 A13
A10 A12 A13 Result
(Precharge command)
0
0
0
0
1
0
0
1
1
x
0
1
0
1
x
Precharge Bank A
Precharge Bank B
Precharge Bank C
Precharge Bank D
Precharge All Banks
x : Don’t care
disables Auto-Precharge
(End of Burst)
0
1
enables Auto-Precharge
(End of Burst)
Col.
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9 A10
x
A12 A13
(/CAS strobes)
A12 A13
Result
enables Read/Write
commands for Bank A
0
0
1
1
0
1
0
1
enables Read/Write
commands for Bank B
enables Read/Write
commands for Bank C
enables Read/Write
commands for Bank D
24
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
9. Precharge
The precharge command can be issued anytime after tRAS (MIN.) is satisfied.
Soon after the precharge command is issued, precharge operation performed and the synchronous DRAM enters
the idle state after tRP is satisfied. The parameter tRP is the time required to perform the precharge.
The earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is
as follows.
It is depending on the /CAS latency and clock cycle time.
Burst length=4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
/CAS latency = 2
PRE
Q3
Read
Command
Hi-Z
DQ
Q1
Q2
Q4
Q3
/CAS latency = 3
Command
Read
PRE
Q2
Hi-Z
DQ
Q1
Q4
(tRAS must be satisfied)
In order to write all data to the memory cell correctly, the asynchronous parameter “tDPL” must be satisfied. The tDPL
(MIN.) specification defines the earliest time that a precharge command can be issued. Minimum number of clocks is
calculated by dividing tDPL (MIN.) with clock cycle time.
In summary, the precharge command can be issued relative to reference clock that indicates the last data word is
valid. In the following table, minus means clocks before the reference; plus means time after the reference.
/CAS latency
Read
–1
Write
2
3
+tDPL (MIN.)
+tDPL (MIN.)
–2
25
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
10. Auto Precharge
During a read or write command cycle, A10 controls whether auto precharge is selected. A10 high in the Read or
Write command (Read with Auto precharge command or Write with Auto precharge command), auto precharge is
selected and begins automatically.
The tRAS must be satisfied with a read with auto precharge or a write with auto precharge operation. In addition, the
next activate command to the bank being precharged cannot be executed until the precharge cycle ends.
In read cycle, once auto precharge has started, an activate command to the bank can be issued after tRP has been
satisfied.
In write cycle, the tDAL must be satisfied to issue the next activate command to the bank being precharged.
The timing that begins the auto precharge cycle depends on both the /CAS latency programmed into the mode
register and whether read or write cycle.
10.1 Read with Auto Precharge
During a read cycle, the auto precharge begins one clock earlier (/CAS latency of 2) or two clocks earlier (/CAS
latency of 3) the last data word output.
Burst length = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CLK
/CAS latency = 2
Auto precharge starts
Command
READA B
Hi-Z
DQ
QB1
QB2
QB3
QB4
/CAS latency = 3
Auto precharge starts
Command
READA B
Hi-Z
DQ
QB1
QB2
QB3
QB4
(tRAS must be satisfied)
Remark READA means Read with Auto precharge
26
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
10.2 Write with Auto Precharge
During a write cycle, the auto precharge starts at the timing that is equal to the value of the tDPL (MIN.) after the last
data word input to the device.
Burst length = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
/CAS latency = 2
Auto precharge starts
Command
WRITA B
DB1
Hi-Z
DQ
DB2
DB3
DB4
t
DPL(MIN.)
/CAS latency = 3
Auto precharge starts
Command
WRITA B
DB1
Hi-Z
DQ
DB2
DB3
DB4
t
DPL(MIN.)
(tRAS must be satisfied)
Remark WRITA means Write with Auto Precharge
In summary, the auto precharge begins relative to a reference clock that indicates the last data word is valid.
In the table below, minus means clocks before the reference; plus means after the reference.
/CAS latency
Read
–1
Write
2
3
+tDPL (MIN.)
+tDPL (MIN.)
–2
27
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
11. Read / Write Command Interval
11.1 Read to Read Command Interval
During a read cycle, when new Read command is issued, it will be effective after /CAS latency, even if the previous
read operation does not completed. READ will be interrupted by another READ.
The interval between the commands is 1 cycle minimum. Each Read command can be issued in every clock
without any restriction.
Burst length = 4, /CAS latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CLK
Command
Read A
Read B
Hi-Z
DQ
QA1
QB1
QB2
QB3
QB4
1cycle
11.2 Write to Write Command Interval
During a write cycle, when a new Write command is issued, the previous burst will terminate and the new burst will
begin with a new Write command. WRITE will be interrupted by another WRITE.
The interval between the commands is minimum 1 cycle. Each Write command can be issued in every clock
without any restriction.
Burst length = 4, /CAS latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command
DQ
Write A
DA1
Write B
DB1
Hi-Z
DB2
DB3
DB4
1cycle
28
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
11.3 Write to Read Command Interval
Write command and Read command interval is also 1 cycle.
Only the write data before Read command will be written.
The data bus must be Hi-Z at least one cycle prior to the first DOUT.
Burst length = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
/CAS latency = 2
Command
Write A
DA1
Read B
Hi-Z
DQ
QB1
QB2
QB3
QB4
/CAS latency = 3
Command
Write A
DA1
Read B
Hi-Z
DQ
QB1
QB2
QB3
QB4
29
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
11.4 Read to Write Command Interval
During a read cycle, READ can be interrupted by WRITE.
The Read and Write command interval is 1 cycle minimum. There is a restriction to avoid data conflict. The Data
bus must be Hi-Z using DQM before WRITE.
Burst length = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command
DQM
Read
Write
Hi-Z
DQ
D1
D2
D3
D4
1cycle
READ can be interrupted by WRITE. DQM must be High at least 3 clocks prior to the Write command.
Burst length = 8
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CLK
/CAS latency = 2
Command
Read
Write
DQM
DQ
Q1
Q2
Q3
D1
Write
D1
D2
D3
Hi-Z is
necessary
/CAS latency = 3
Command
Read
DQM
DQ
Q1
Q2
D2
D3
Hi-Z is
necessary
30
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
12. Burst Termination
There are two methods to terminate a burst operation other than using a Read or a Write command. One is the
burst stop command and the other is the precharge command.
12.1 Burst Stop Command
During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus
goes to Hi-Z after the /CAS latency from the burst stop command.
Burst length = X
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Command
Read
BST
/CAS latency = 2
Hi-Z
DQ
Q1
Q2
Q1
Q3
/CAS latency = 3
Hi-Z
DQ
Q2
Q3
Remark BST: Burst stop command
During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes
to Hi-Z at the same clock with the burst stop command.
Burst length = X
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Command
Write
BST
/CAS latency = 2, 3
Hi-Z
DQ
D1
D2
D3
D4
Remark BST: Burst stop command
31
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
12.2 Precharge Termination
12.2.1 Precharge Termination in READ Cycle
During a read cycle, the burst read operation is terminated by a precharge command.
When the precharge command is issued, the burst read operation is terminated and precharge starts.
The same bank can be activated again after tRP from the precharge command.
To issue a precharge command, tRAS must be satisfied.
When /CAS latency is 2, the read data will remain valid until one clock after the precharge command.
Burst length = X, /CAS latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Command
Read
PRE
ACT
Hi-Z
DQ
Q1
Q2
Q3
Q4
t
RP
(tRAS must be satisfied)
When /CAS latency is 3, the read data will remain valid until two clocks after the precharge command.
Burst length = X, /CAS latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command
Read
PRE
ACT
Hi-Z
DQ
Q1
Q2
Q3
Q4
t
RP
(tRAS must be satisfied)
32
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
12.2.2 Precharge Termination in WRITE Cycle
During a write cycle, the burst write operation is terminated by a precharge command.
When the precharge command is issued, the burst write operation is terminated and precharge starts.
The same bank can be activated again after tRP from the precharge command.
To issue a precharge command, tRAS must be satisfied.
When /CAS latency is 2, the write data written prior to the precharge command will be correctly stored. However,
invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM
must be high at the same clock as the precharge command. This will mask the invalid data.
Burst length = X, /CAS latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Command
Write
PRE
ACT
DQM
DQ
Hi-Z
D1
D2
D3
D4
D5
t
RP
(tRAS must be satisfied)
When /CAS latency is 3, the write data written prior to the precharge command will be correctly stored. However,
invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM
must be high at the same clock as the precharge command. This will mask the invalid data.
Burst length = X, /CAS latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command
Write
PRE
ACT
DQM
DQ
Hi-Z
D1
D2
D3
D4
D5
t
RP
(tRAS must be satisfied)
33
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
13. Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 100 µs and then, execute Power on sequence and CBR (auto) Refresh before
proper device operation is achieved.
Absolute Maximum Ratings
Parameter
Voltage on power supply pin relative to GND
Voltage on any pin relative to GND
Short circuit output current
Power dissipation
Symbol
Condition
Rating
−0.5 to +4.6
−0.5 to +4.6
50
Unit
V
VCC, VCCQ
VT
IO
V
mA
W
PD
TA
Tstg
1
Operating ambient temperature
Storage temperature
0 to 70
°C
°C
−55 to + 125
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
VCC, VCCQ
VIH
Condition
MIN.
3.0
TYP.
3.3
MAX.
3.6
Unit
V
Supply voltage
High level input voltage
2.0
VCC+0.3 Note1
V
Low level input voltage
VIL
−0.3 Note2
+0.8
V
Operating ambient temperature
TA
0
70
°C
Notes 1. VIH(MAX.) = VCC + 1.5 V (Pulse width ≤ 5 ns)
2. VIL(MIN.) = –1.5 V (Pulse width ≤ 5 ns)
Pin Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Input capacitance
Symbol
CI1
Condition
MIN.
TYP.
MAX.
Unit
pF
A0 - A13
2.5
2.5
4
4
CI2
CLK, CKE, /CS, /RAS, /CAS, /WE,
DQM, UDQM, LDQM
Data input / output capacitance
CI/O
DQ0 - DQ15
4
6.5
pF
34
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
C Characteristics 1 (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test condition
/CAS Grade
latency
Maximum
Unit Notes
×4
75
65
60
80
70
70
1
×8
80
70
65
85
75
75
1
×16
90
80
70
115
90
90
1
Operating current
ICC1
Burst length = 1,
CL = 2 -A80
-A10
mA
1
tRC ≥ tRC (MIN.), Io = 0 mA,
One bank active
-A10B
CL = 3 -A80
-A10
-A10B
Precharge standby current
in power down mode
ICC2P
CKE ≤ VIL (MAX.), tCK = 15 ns
mA
mA
ICC2PS CKE ≤ VIL (MAX.), tCK = ∞
ICC2N
1
1
1
Precharge standby current
in non power down mode
CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.),
Input signals are changed one time during 30 ns.
20
20
20
ICC2NS CKE ≥ VIH (MIN.), tCK = ∞,
6
6
6
Input signals are stable.
Active standby current
in power down mode
ICC3P
ICC3PS CKE ≤ VIL (MAX.), tCK = ∞
ICC3N
CKE ≤ VIL (MAX.), tCK = 15 ns
5
4
5
4
5
4
mA
mA
Active standby current
CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.),
25
25
25
in non power down mode
Input signals are changed one time during 30 ns.
ICC3NS CKE ≥ VIH (MIN.), tCK = ∞ ,
15
15
15
Input signals are stable.
Operating current
(Burst mode)
ICC4
ICC5
ICC6
tCK ≥ tCK (MIN.), Io = 0 mA,
CL = 2 -A80
-A10
90
70
105
80
165
130
110
195
165
165
130
130
105
135
135
115
1
mA
mA
mA
2
All banks active
-A10B
65
70
CL = 3 -A80
-A10
105
90
125
105
105
130
130
105
135
135
115
1
-A10B
90
CBR (auto) refresh current
tRC ≥ tRC (MIN.)
CL = 2 -A80
-A10
130
130
105
135
135
115
1
3
-A10B
CL = 3 -A80
-A10
-A10B
Self refresh current
CKE ≤ 0.2 V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC1 is measured condition that addresses are changed only one time during tCK (MIN.).
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC4 is measured condition that addresses are changed only one time during tCK (MIN.).
3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
35
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
II (L)
Test condition
MIN.
TYP.
MAX.
+1.0
Unit
Note
Input leakage current
0 ≤ VI ≤ VCCQ, VCCQ = VCC
−1.0
µA
All other pins not under test = 0 V
Output leakage current
High level output voltage
Low level output voltage
IO (L)
VOH
VOL
0 ≤ VO ≤ VCCQ, DOUT is disabled
IO = −4 mA
−1.5
+1.5
0.4
µA
V
2.4
IO = +4 mA
V
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
Test Conditions
Parameter
Value
2.4 / 0.4
1.4
Unit
AC high level input voltage / low level input voltage
Input timing measurement reference level
Transition time (Input rise and fall time)
Output timing measurement reference level
V
V
1
ns
V
1.4
t
CK
t
CH
t
CL
2.4 V
CLK
1.4 V
0.4 V
t
SETUP
t
HOLD
2.4 V
1.4 V
0.4 V
Input
t
AC
t
OH
Output
36
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
Synchronous Characteristics
Parameter
Symbol
-80
MAX.
-10
MAX.
-10B
MAX.
Unit Note
MIN.
8
MIN.
10
MIN.
10
Clock cycle time
/CAS latency = 3
/CAS latency = 2
/CAS latency = 3
/CAS latency = 2
tCK3
tCK2
tAC3
tAC2
tCH
(125 MHz)
(100 MHz)
(100 MHz) ns
10
(100 MHz)
13
(77 MHz)
15
(67 MHz)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Access time from CLK
6
6
6
7
7
8
1
1
CLK high level width
CLK low level width
Data-out hold time
3
3
3
3
0
3
3
2
1
2
1
2
1
2
2
3
3
3
3
0
3
3
2
1
2
1
2
1
2
2
3.5
3.5
3
tCL
/CAS latency = 3
/CAS latency = 2
tOH3
tOH2
tLZ
1
1
3
Data-out low-impedance time
Data-out high-impedance time
0
/CAS latency = 3
/CAS latency = 2
tHZ3
tHZ2
tDS
6
6
6
7
3
7
8
3
Data-in setup time
Data-in hold time
2.5
1
tDH
Address setup time
Address hold time
CKE setup time
tAS
2.5
1
tAH
tCKS
tCKH
tCKSP
tCMS
2.5
1
CKE hold time
CKE setup time (Power down exit)
2.5
2.5
Command (/CS, /RAS, /CAS, /WE, DQM)
setup time
Command (/CS, /RAS, /CAS, /WE, DQM)
hold time
tCMH
1
1
1
ns
Note 1. Output load
Z = 50Ω
Output
50 pF
37
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
Asynchronous Characteristics
Symbol
-80
MAX.
-10
MAX.
-10B
MAX.
Unit Note
Parameter
MIN.
70
70
48
20
20
16
8
MIN.
70
70
50
20
20
20
10
10
MIN.
90
90
60
30
30
20
10
10
ACT to REF/ACT command period (operation)
REF to REF/ACT command period (refresh)
ACT to PRE command period
tRC
tRC1
tRAS
tRP
ns
ns
ns
ns
ns
ns
ns
ns
ns
120,000
120,000
120,000
PRE to ACT command period
Delay time ACT to READ/WRITE command
ACT (one) to ACT (another) command period
Data-in to PRE command period /CAS latency = 3
/CAS latency = 2
tRCD
tRRD
tDPL3
tDPL2
tDAL3
8
Data-in to ACT (REF) command /CAS latency = 3
period (Auto precharge)
1CLK
+20
1CLK
+20
1CLK
+30
/CAS latency = 2
tDAL2
1CLK
+20
1CLK
+20
1CLK
+30
ns
Mode register set cycle time
Transition time
tRSC
tT
2
2
1
2
1
CLK
ns
0.5
30
64
30
64
30
64
Refresh time (4,096 refresh cycles)
tREF
ms
38
Data Sheet E0149N10
13.1 AC Parameters for Read Timing (Manual Precharge, Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
t
CK
CLK
t
CH
t
CL
CKE
/CS
t
CKH
t
CKS
t
CMS
t
CMH
/RAS
/CAS
/WE
A13
A12
µ
µ
A10
ADD
DQM
DQ
t
AS
t
AH
L
t
AC
t
AC
t
AC
t
AC
t
HZ
Hi-Z
t
LZ
t
OH
t
OH
t
OH
RP
t
OH
t
RCD
t
RAS
t
t
RC
Activate
Command
for Bank A
Read
Command
for Bank A
Precharge
Command
for Bank A
Activate
Command
for Bank A
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
t
CK
CLK
t
CH
t
CL
CKE
/CS
Auto Precharge
Start for Bank C
t
CKH
t
CKS
t
CMS
t
CMH
/RAS
/CAS
/WE
A13
A12
µ
µ
A10
ADD
DQM
DQ
t
AS
t
AH
L
t
AC
t
AC
t
AC
t
AC
t
HZ
Hi-Z
t
RCD
t
LZ
t
OH
t
OH
t
OH
t
OH
t
RAS
t
RRD
t
RC
Activate
Command
for Bank C
Read with
Auto Precharge
Command
Activate
Command
for Bank D
Activate
Command
for Bank C
for Bank C
13.2 AC Parameters for Write Timing (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
Auto Precharge
Start for Bank C
t
CKH
t
CKS
t
CMS
t
CMH
/RAS
/CAS
/WE
A13
A12
µ
µ
A10
ADD
DQM
DQ
t
AS
t
AH
L
t
DS
t
DH
Hi-Z
t
RCD
t
DAL
t
RC
t
RRD
t
RCD
t
DPL
t
RP
t
RAS
t
RC
Write with
Auto Precharge
Command
Activate
Command
for Bank C
Activate
Command
for Bank B
Write
Command
for Bank B
Activate Precharge
Command Command
for Bank C for Bank B
Activate
Command
for Bank B
for Bank C
µPD4564441, 4564841, 4564163
13.3 Relationship between Frequency and Latency
Speed version
-80
-10
-10B
Clock cycle time [ns]
8
125
3
10
100
2
10
100
3
13
77
2
10
100
3
15
67
2
Frequency [MHz]
/CAS latency
[tRCD]
3
2
2
2
3
2
/RAS latency (/CAS latency + [tRCD])
6
4
5
4
6
4
[tRC]
9
7
7
6
9
6
[tRC1]
[tRAS]
[tRRD]
[tRP]
9
7
7
6
9
6
6
5
5
4
6
4
2
2
2
2
2
2
3
2
2
2
3
2
[tDPL]
[tDAL]
[tRSC]
1
1
1
1
1
1
4
3
3
3
4
3
2
2
2
2
2
2
42
Data Sheet E0149N10
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
t
RSC
2 CLK (MIN.)
/RAS
/CAS
/WE
A13
A12
A10
µ
µ
ADDRESS KEY
ADD
DQM
DQ
Hi-Z
Precharge
All Banks
Command
Mode
Register Set
Command
Activate
Command
is valid
t
RP
CLK
CKE
Clock cycle is necessary
High level is necessary
t
RSC
2 refresh cycles are necessary
/CS
/RAS
/CAS
/WE
A13
A12
A10
ADD
DQM
DQ
ADDRESS KEY
µ
µ
High level is necessary
Hi-Z
Precharge
All Banks
Command
is necessary
Mode
Register Set
Command
CBR (Auto)
Refresh
Command
CBR (Auto)
Refresh
Command
is necessary
Activate
Command
is necessary is necessary
t
RP
t
RC1
t
RC1
Only /CS signal needs to be issued at minimum rate
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A13
L
L
A12
A10
ADD
DQM
DQ
µ
µ
RAa
RAa
CAa
CAb
L
Hi-Z
QAa1 QAa2 QAa3 QAa4
DAb1 DAb2 DAb3 DAb4
Activate
Command
for Bank A
Read
Command
for Bank A
Write
Command
for Bank A
Precharge
Command
for Bank A
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
A13
A12
A10
ADD
DQM
DQ
µ
µ
RAa
RAa
CAa
L
Hi-Z
QAa1 QAa2
QAa3
QAa4
Activate
Command
for Bank A
Read
Command
for Bank A
Hi-Z (turn off)
at the end of burst
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
A13
A12
µ
µ
A10
ADD
DQM
DQ
RAa
RAa
CAa
L
Hi-Z
QAa1 QAa2
QAa3
QAa4
Activate
Read
Hi-Z (turn off)
Command
for Bank A
Command
for Bank A
at the end of burst
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
A13
A12
µ
µ
A10
ADD
DQM
DQ
RAa
RAa
CAa
L
Hi-Z
DAa1
DAa2
DAa3
DAa4
Activate
Write
Command
for Bank A
Command
for Bank A
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
A13
A12
µ
µ
A10
ADD
DQM
DQ
RAa
RAa
CAa
L
Hi-Z
DAa1
DAa2
DAa3
DAa4
Activate
Write
Command
for Bank A
Command
for Bank A
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
t
CKSP
t
CKSP
CKE
/CS
VALID
/RAS
/CAS
/WE
A13
A12
µ
µ
A10
RAa
RAa
ADD
DQM
CAa
L
Hi-Z
QAa1 QAa2 QAa3
QAa4
DQ
Activate
Command
for Bank A
Read
Command
for Bank A
Precharge
Command
for Bank A
T0
H
T1
T2
T3
T4
T5
T6
Tn
Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6
Tm Tm + 1 Tm + 2 Tm + 3 Tm + 4 Tm + 5 Tm + 6 Tm + 7
CLK
CKE
/CS
/RAS
/CAS
/WE
A13
A12
µ
µ
A10
ADD
DQM
DQ
L
Hi-Z
Q1
Precharge
Command
Activate
Command
Read
Command
(if necessary)
t
RP
t
RC1
t
RC1
T0
T1
T2
T3
T4
Tn
Tn + 1 Tn + 2
Tm Tm + 1
Tk
Tk + 1 Tk + 2 Tk + 3 Tk + 4
CLK
CKE
/CS
/RAS
/CAS
/WE
A13
A12
A10
ADD
DQM
DQ
µ
µ
L
Hi-Z
Precharge
Command
Activate
Command
(if necessary)
(or Activate Command)
Next Clock
Enable
Next Clock
Enable
t
RP
t
RC1
t
RC1
T0
H
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
A13
A12
A10
ADD
DQM
DQ
µ
µ
RAd
RAa
RAa
CAa
CAb
CAc
RAd
CAd
L
Hi-Z
QAa1 QAa2 QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4
QAd1 QAd2 QAd3
Activate
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank A
Precharge
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
T0
H
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
A13
A12
A10
ADD
DQM
DQ
µ
µ
RAa
RAa
RAa
CAa
CAb
CAc
RAa
CAa
L
Hi-Z
QAa1 QAa2 QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4
Read
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank A
Precharge
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
T0
H
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
A13
A12
µ
µ
A10
ADD
DQM
DQ
RDd
RDa
RDa
CDa
CDb
CDc
RDd
CDd
L
Hi-Z
DDa1 DDa2 DDa3 DDa4 DDb1 DDb2 DDc1 DDc2 DDc3 DDc4
DDd1 DDd2 DDd3 DDd4
Activate
Command
for Bank D
Write
Command
for Bank D
Write
Command
for Bank D
Write
Command
for Bank D
Precharge
Command
for Bank D
Activate
Command
for Bank D
Write
Command
for Bank D
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A13
A12
A10
ADD
DQM
DQ
µ
µ
RDd
RDa
RDa
CDa
CDb
CDc
RDd
CDd
L
Hi-Z
DDa1 DDa2 DDa3 DDa4 DDb1 DDb2 DDc1 DDc2 DDc3 DDc4
DDd1 DDd2
Activate
Command
for Bank D
Write
Command
for Bank D
Write
Command
for Bank D
Write
Command
for Bank D
Precharge
Command
for Bank D
Activate
Command
for Bank D
Write
Command
for Bank D
T0
H
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
A13
A12
µ
µ
A10
ADD
DQM
DQ
RBa
RBa
RDb
RDa
RDa
CDa
CBa
RDb
CDb
L
Hi-Z
QDa1 QDa2 QDa3 QDa4 QDa5 QDa6 QDa7 QDa8 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QBa8
Activate
Command
for Bank D
Read
Command
for Bank D
Activate
Command
for Bank B
Read
Command
for Bank B
Activate
Command
for Bank D
Read
Command
for Bank D
Precharge
Command
for Bank D
T0
H
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
A13
A12
A10
ADD
DQM
DQ
RAa
RAa
RBb
RBa
RBa
µ
µ
CBa
CAa
RBb
CBb
L
Hi-Z
QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QBa8 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7
Activate
Command
for Bank B
Read
Command
for Bank B
Activate
Command
for Bank A
Read
Command
for Bank A
Precharge
Command
for Bank B
Activate
Command
for Bank B
Read
Command
for Bank B
Precharge
Command
for Bank A
T0
H
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
A13
A12
µ
µ
A10
ADD
DQM
DQ
RDa
RDa
RAb
RAb
RAa
RAa
CAa
CDa
CAb
L
Hi-Z
DAa1 DAa2 DAa3 DAa4 DAa5 DAa6 DAa7 DAa8 DDa1 DDa2 DDa3 DDa4 DDa5 DDa6 DDa7 DDa8 DAb1 DAb2 DAb3
Activate
Command
for Bank A
Write
Command
for Bank A
Activate
Command
for Bank D
Write
Command
for Bank D
Activate
Command
for Bank A
Write
Command
for Bank A
Precharge
Precharge
Command
for Bank A
Command
for Bank D
T0
H
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
A13
A12
A10
RDa
RDa
RAb
RAa
RAa
µ
µ
ADD
CAa
CDa
RAb
CAb
L
DQM
Hi-Z
DAa1 DAa2 DAa3 DAa4 DAa5 DAa6 DAa7 DAa8 DDa1 DDa2 DDa3 DDa4 DDa5 DDa6 DDa7 DDa8 DAb1 DAb2
DQ
Activate
Command
for Bank A
Write
Command
for Bank A
Activate
Command
for Bank D
Write
Command
for Bank D
Precharge
Command
for Bank A
Activate
Command
for Bank A
Write
Command
for Bank A
Precharge
Command
for Bank D
T0
H
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
A13
A12
µ
µ
A10
RAa
RAa
ADD
CAa
CAb
Write Latency = 0
CAc
DQM
DQ
L
Word Masking
Hi-Z
QAa1 QAa2 QAa3 QAa4
DAb1 DAb2
DAb4
QAc1 QAc2
QAc4
Activate
Command
for Bank A
Read
Command
for Bank A
Write
Command
for Bank A
Read
Command
for Bank A
Hi-Z at the end of wrap function
0-Clock Latency
2-Clock Latency
T0
H
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
A13
A12
µ
µ
A10
RAa
RAa
ADD
CAa
CAb
Write Latency = 0
CAc
DQM
DQ
L
Word Masking
Hi-Z
QAa1 QAa2 QAa3 QAa4
DAb1 DAb2
DAb4
QAc1 QAc2
Activate
Read
Write
Read
Command
for Bank A
Command
for Bank A
Command
for Bank A
Command
for Bank A
Hi-Z at the end of wrap function
0-Clock Latency
2-Clock Latency
T0
H
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
A13
A12
µ
µ
A10
RAa
RAa
RDa
RDa
ADD
CAa
CDa
CDb
CDc
CAb
CDd
DQM
DQ
L
Hi-Z
Aa1
Aa2
Aa3
Aa4
Da1
Da2
Db1
Db2
Dc1
Dc2
Ab1
Ab2
Dd1
Dd2
Dd3
Dd4
Activate
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank A
Read
Command
for Bank D
Activate
Command
for bank D
Precharge
Command
for Bank A
Precharge
Command
for Bank D
T0
H
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
A13
A12
µ
µ
A10
RAa
RAa
RDa
RDa
ADD
CAa
CDa
CDb
CAb
CDc
DQM
DQ
L
Hi-Z
Aa1
Aa2
Aa3
Aa4
Da1
Da2
Db1
Db2
Dc1
Dc2
Ab1
Ab2
Ab3
Ab4
Activate
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank A
Precharge
Command
for Bank D
Precharge
Command
for Bank A
Activate
Command
for Bank D
T0
H
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
A13
A12
A10
ADD
µ
µ
RAa
RAa
RBa
RBa
CAa
Aa1
CBa
Ba1
CBb
Bb1
CBc
Bc1
CAb
Ab1
CBd
DQM
DQ
L
Hi-Z
Aa2
Aa3
Aa4
Ba2
Bb2
Bc2
Ab2
Bd1
Bd2
Bd3
Bd4
Activate
Command
for Bank A
Write
Command
for Bank A
Activate
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank A for Bank B for Bank A
Write
Precharge
Command Command
Precharge
Command
for Bank B
Interleaved Column Write Cycle (2/2) (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A13
A12
A10
ADD
µ
µ
RAa
RAa
RBa
RBa
CAa
Aa1
CBa
Ba1
CBb
Bb1
CAb
CBd
CBc
DQM
DQ
L
Hi-Z
Aa2
Aa3
Aa4
Ba2
Bb2
Bc1
Bc2
Ab1
Ab2
Bd1
Bd2
Bd3
Bd4
Activate
Write
Write
Write
Write
Write
Write
Command
for Bank A
Command
for Bank A
Command
for Bank B
Command
for Bank B
Command
for Bank B
Command
for Bank A
Command
for Bank B
Activate
Command
for Bank B
Precharge
Command
for Bank A
Precharge
Command
for Bank B
13.19 Auto Precharge after Read Burst (1/2) (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A13
A12
µ
µ
A10
RAa
RAa
RDa
RDa
RDb
RAc
ADD
CAa
CDa
CAb
RDb
CDb
RAc
CAc
DQM
DQ
L
Hi-Z
Activate
Command
for Bank A
Activate
Command
for Bank A
Activate
Command
for Bank D
Activate
Command
for Bank D
Read
Command
for Bank A
Read with
Auto Precharge
Command
Read with
Auto Precharge
Command
Read with
Auto Precharge
Command
Read with
Auto Precharge
Command
for Bank D
for Bank A
for Bank D
for Bank A
Auto Precharge
Start for Bank A
Auto Precharge
Start for Bank D
Auto Precharge
Start for Bank D
Auto Precharge after Read Burst (2/2) (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A13
A12
µ
µ
A10
ADD
DQM
DQ
RAa
RAa
RDa
RDb
CAa RDa
CDa
CAb
RDb
CDb
L
Hi-Z
Activate
Command
for Bank A
Activate
Command
for Bank D
Read with
Auto Precharge
Command
Activate
Command
for Bank D
Read with
Auto Precharge
Command
Read
Command
for Bank A
Read with
Auto Precharge
Command
for Bank A
for Bank D
Auto Precharge
Start for Bank D
Auto Precharge
Start for Bank A
for Bank D
13.20 Auto Precharge after Write Burst (1/2) (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A13
A12
A10
RAa
RAa
RDa
RDa
RDb
RAc
µ
µ
ADD
CAa
CDa
CAb
RDb
CDb
RAc
CAc
DQM
DQ
L
Hi-Z
Activate
Command
for Bank A
Activate
Command
for Bank D
Activate
Command
for Bank D
Activate
Command
for Bank A
Write
Command
for Bank A
Write with
Auto Precharge
Command
Write with
Auto Precharge
Command
Write with
Auto Precharge
Command
Write with
Auto Precharge
Command
for Bank D
for Bank D
for Bank A
for Bank A
Auto Precharge
Start for Bank D
Auto Precharge
Start for Bank A
Auto Precharge
Start for Bank D
Auto Precharge after Write Burst (2/2) (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A13
A12
µ
µ
A10
ADD
DQM
DQ
RAa
RAa
RDa
RDb
CAa RDa
CDa
CAb
RDb
CDb
L
Hi-Z
Activate
Command
for Bank A
Activate
Command
for Bank D
Write with
Auto Precharge
Command
Activate
Command
for bank D
Write with
Auto Precharge
Command
for Bank A
Write
Command
for Bank A
Write with
Auto Precharge
Command
for Bank D
Auto Precharge
Start for Bank D
Auto Precharge
Start for Bank A
for Bank D
13.21 Full Page Read Cycle (1/2) (/CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
Tn
Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8 Tn + 9 Tn + 10 Tn + 11 Tn + 12 Tn + 13
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A13
A12
A10
ADD
µ
µ
RAa
RDa
RDa
RDb
RAa
CAa
CDa
RDb
DQM
DQ
L
Hi-Z
Aa
Aa+1 Aa+2 Aa-2 Aa-1
Aa
Aa+1
Da
Da+1 Da+2 Da+3 Da+4 Da+5 Da+6
Activate
Command
for Bank A
Read
Command
for Bank A
Activate
Command
for Bank D
Read
Command
for Bank D
Precharge
Command
for Bank D
Activate
Command
for Bank D
Burst Stop Command
Full Page Read Cycle (2/2) (/CAS latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
Tn
Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8 Tn + 9 Tn + 10 Tn + 11 Tn + 12
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A13
A12
A10
ADD
µ
µ
RAa
RAa
RDa
RDa
RDb
CAa
CDa
RDb
L
DQM
DQ
Hi-Z
Aa
Aa+1 Aa-3 Aa-2 Aa-1
Aa
Aa+1
Da
Da+1 Da+2 Da+3 Da+4 Da+5
Activate
Command
for Bank A
Read
Command
for Bank A
Activate
Command
for Bank D
Read
Command
for Bank D
Precharge
Command
for Bank D
Activate
Command
for Bank D
Burst Stop Command
13.22 Full Page Write Cycle (1/2) (/CAS latency = 2)
T0
T1
T2
T3
T4
T5
Tn
Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8 Tn + 9 Tn + 10 Tn + 11 Tn + 12 Tn + 13 Tn + 14 Tn + 15
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A13
A12
A10
ADD
µ
µ
RAa
RAa
RDa
RDa
RDb
CAa
Aa
CDa
Da
RDb
DQM
DQ
L
Hi-Z
Aa+1 Aa+2
Aa-2 Aa-1
Aa
Aa+1
Da+1 Da+2 Da+3 Da+4 Da+5
Precharge
Command
for Bank D
Write
Command
for Bank D
Activate
Command
for Bank A
Write
Command
for Bank A
Activate
Command
for Bank D
Activate
Command
for Bank D
Burst Stop Command
Full Page Write Cycle (2/2) (/CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
Tn
Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8 Tn + 9 Tn + 10 Tn + 11 Tn + 12 Tn + 13
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A13
A12
A10
ADD
µ
µ
RAa
RAa
RDa
RDa
RDb
CAa
Aa
CDa
Da
RDb
DQM
DQ
L
Hi-Z
Aa+1 Aa+2 Aa+3 Aa-1
Aa
Aa+1
Da+1 Da+2 Da+3 Da+4 Da+5
Write
Command
for Bank D
Precharge
Command
for Bank D
Activate
Command
for Bank A
Write
Command
for Bank A
Activate
Command
for Bank D
Activate
Command
for Bank D
Burst Stop Command
Burst is not completed
in the Full Page Mode
13.23 Byte Write Operation (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
A13
A12
A10
µ
µ
ADD
LDQM
UDQM
DQ
(lower)
DQ
(upper)
Activate
Command
for Bank D
Read
Command
for Bank D
Upper Byte
not Read
Lower Byte Upper Byte Lower Byte
not Write not Write not Write
13.24 Burst Read and Single Write (Option) (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A13
A12
A10
µ
µ
ADD
DQM
DQ
Hi-Z
Qa1
Qa2
Qa3
Qa4
D1
Qb1
Qb2
Qb4
D2
Activate
Command
for Bank D
Read
Command
for Bank D
Single Write
Command
for Bank D
Single Write
Command
for Bank D
Read
Command
for Bank D
Single Write
Command
for Bank D
13.25 Full Page Random Column Read (Burst Length = Full Page, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A13
A12
µ
µ
A10
ADD
DQM
DQ
RAa
RAa
RDa
RDa
CAa
CDa
CAb
CDb
CDc
CAc
L
Hi-Z
QAa1 QDa1 QAb1 QAb2 QDb1 QDb2 QAc1 QAc2 QAc3 QDc1 QDc2 QDc3
Activate
Command
for Bank D
Activate
Command
for Bank A
Precharge
Command
for Bank D
Read
Command
for Bank A
Read
Command
for Bank D
Read
Command
for Bank A
Read
Command
for Bank D
Read
Command
for Bank A
(PRE Termination of Burst)
Read
Command
for Bank D
T0
H
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
A13
A12
µ
µ
A10
ADD
DQM
DQ
RAa
RAa
RDa
RDa
CAa
CDa
CAb
CDb
CDc
CAc
L
Hi-Z
DAa1 DDa1 DAb1 DAb2 DDb1 DDb2 DAc1 DAc2 DAc3 DDc1 DDc2 DDc3 DDc4
Activate
Command
for Bank A
Activate
Command
for Bank D
Precharge
Command
for Bank D
(PRE Termination of Burst)
Write
Command
for Bank A
Write
Command
for Bank A
Write
Command
for Bank D
Write
Command
for Bank A
Write
Command
for Bank D
Write
Command
for Bank D
13.27 PRE (Precharge) Termination of Burst (1/2) (Burst Length = 8, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A13
A12
A10
ADD
DQM
DQ
RAa
RAa
RAb
RAb
RAc
RAc
µ
µ
CAa
CAb
Write
Masking
L
Hi-Z
Hi-Z
DAa1 DAa2 DAa3 DAa4 DAa5
QAb1 QAb2 QAb3 QAb4 QAb5
Activate
Write
Read
Activate
Command
for Bank A
Command
for Bank A
Command
for Bank A
Command
for Bank A
Precharge
Command
for Bank A
Activate
Command
for Bank A
Precharge
Command
for Bank A
PRE Termination
of Burst
PRE Termination
of Burst
t
RCD
t
DPL
t
RP
t
RAS
t
RAS
PRE (Precharge) Termination of Burst (2/2) (Burst Length = 8, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
A13
A12
A10
ADD
DQM
DQ
RAa
RAa
RAb
RAc
µ
µ
CAa
RAb
CAb
RAc
L
Write
Masking
Hi-Z
Hi-Z
DAa1 DAa2 DAa3 DAa4 DAa5
QAb1 QAb2 QAb3 QAb4
Write
Command
for Bank A
Read
Command
for Bank A
Activate
Command
for Bank A
Activate
Command
for Bank A
Precharge
Command
PRE Termination
for Bank A
Activate
Command
for Bank A
Precharge
Command
for Bank A
PRE Termination
of Burst
of Burst
t
RCD
t
DPL
t
RP
t
RAS
t
RAS
µPD4564441, 4564841, 4564163
14. Package Drawing
54-PIN PLASTIC TSOP (II) (10.16 mm (400))
54
28
detail of lead end
F
P
E
1
27
A
H
I
J
G
S
L
C
N
S
B
K
D
M
M
NOTES
ITEM MILLIMETERS
1. Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
A
B
C
22.22±0.05
0.91 MAX.
0.80 (T.P.)
2. Dimension "A" does not include mold fiash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15 mm per side.
+0.08
0.32
D
−0.07
E
F
G
H
I
0.10±0.05
1.1±0.1
1.00
11.76±0.20
10.16±0.10
0.80±0.20
J
+0.025
0.145
K
−0.015
L
M
N
0.50±0.10
0.13
0.10
+7°
3°
P
−3°
S54G5-80-9JF-2
81
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
15. Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the µPD4564×××.
Type of Surface Mount Device
µPD4564×××G5: 54-pin Plastic TSOP (II) (10.16mm (400))
82
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
16. Revision History
Edition /
Date
Page
Previous
Description
Location
Type of
revision
This edition
edition
NEC Corporation (M12621E)
11th edition /
April, 1999
p.15
p.15
Modification, CKE Truth Table - Power down
Addition
p.19
p.19
Modification, Command Truth Table for CKE - Power down
Addition
p.37
p.46
p.47
p.50
p.51
p.52
p.77
p.2, 3
p.35
p.37
p.46
p.47
p.50
p.51
p.52
p.77
p.2, 3
p.35
Modification
Modification
Modification
Modification
Modification
Modification
Modification
Deletion
Note 1. Output load
Symbol
Symbol
Timing Chart (Power Down Mode Exit) , Symbol
Symbol
Symbol
Timing Chart (Precharge Command for Bank D)
12th edition /
-AxxL
January, 2000
Modification
Deletion
ICC2PS
-AxxL
p.36
p.81
p.36
p.81
Modification
Modification
AC Characteristics Test Conditions
Package Drawing
Elpida Memory, Inc. (E0149N)
-
-
-
Republished by Elpida Memory, Inc.
Ver.1.0 /
August. 2001
83
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
NOTES FOR CMOS DEVICES
PRECAUTION AGAINST ESD FOR MOS DEVICES
1
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
84
Data Sheet E0149N10
µPD4564441, 4564841, 4564163
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
used in a non-condensing environment.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
M01E0107
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