UPD4564323G5-A10-9JH [NEC]
64M-bit Synchronous DRAM 4-bank, LVTTL; 64M位同步DRAM 4银行， LVTTL
| 型号： | UPD4564323G5-A10-9JH |
| 厂家： | 
NEC |
| 描述： | 64M-bit Synchronous DRAM 4-bank, LVTTL |
| 文件： | 总84页 (文件大小：1032K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD4564323 for Rev.E
64M-bit Synchronous DRAM
4-bank, LVTTL
Description
The µPD4564323 is a high-speed 67,108,864-bit synchronous dynamic random-access memory, organized as
524,288 words × 32 bits × 4 banks.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
These products are packaged in 86-pin TSOP (II).
Features
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0 and BA1 (Bank Select)
• ×32 organization
• Byte control by DQM0, DQM1, DQM2 and DQM3
• Programmable Wrap sequence (Sequential / Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable /CAS latency (2 and 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• Single 3.3 V ± 0.3 V power supply
• LVTTL compatible inputs and outputs
• 4,096 refresh cycles / 64 ms
• Burst termination by Burst stop command and Precharge command
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
M14376EJ2V0DS00 (2nd edition)
Date Published December 1999 NS CP (K)
Printed in Japan
The mark • shows major revised points.
1999
©
µ
PD4564323 for Rev. E
★
Ordering Information
Organization
Clock frequency
MHz (MAX.)
Part number
Package
(word × bit × bank)
µPD4564323G5-A60-9JH
µPD4564323G5-A70-9JH
µPD4564323G5-A80-9JH
µPD4564323G5-A10-9JH
µPD4564323G5-A10B-9JH
512K × 32 × 4
166
143
125
100
100
86-pin Plastic TSOP (II)
(10.16 mm (400))
2
Data Sheet M14376EJ2V0DS00
µ
PD4564323 for Rev. E
★
Part Number
µ
PD4564323G5 - A60
NEC Memory
Synchronous
DRAM
Memory Density
64 : 64M bits
Minimum Cycle Time
60 : 6 ns (166MHz)
70 : 7 ns (143MHz)
80 : 8 ns (125MHz)
10 : 10 ns (100MHz)
10B : 10 ns (100MHz)
Organization
32 : x32
Number of Banks
& Interface
3 : 4Bank, LVTTL
Low Voltage
A : 3.3
± 0.3 V
Package
G5 : TSOP(II)
3
Data Sheet M14376EJ2V0DS00
µ
PD4564323 for Rev. E
Pin Configuration
/xxx indicates active low signal.
[µPD4564323]
86-pin Plastic TSOP (II) (10.16 mm (400))
512K words × 32 bits × 4 banks
VCC
1
86
V
SS
DQ0
2
3
4
5
6
7
8
9
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
DQ15
VSSQ
DQ14
DQ13
VCCQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VCCQ
V
CCQ
DQ1
DQ2
V
SSQ
DQ3
DQ4
V
CCQ
DQ5
DQ6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
V
SSQ
DQ7
NC
DQ8
NC
V
CC
V
SS
DQM0
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10(AP)
A0
A1
A2
DQM2
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
VCC
V
SS
NC
DQ16
NC
DQ31
VCCQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VCCQ
DQ26
DQ25
VSSQ
VSSQ
DQ17
DQ18
V
CCQ
DQ19
DQ20
V
SSQ
DQ21
DQ22
V
CCQ
DQ23
DQ24
V
CC
V
SS
A0 to A10Note
BA0, BA1
: Address inputs
: Bank select
DQ0 to DQ31 : Data inputs / outputs
CLK
CKE
/CS
: Clock input
: Clock enable
: Chip select
/RAS
/CAS
/WE
: Row address strobe
: Column address strobe
: Write enable
DQM0 to DQM3: DQ mask enable
VCC
VSS
: Supply voltage
: Ground
VCCQ
VSSQ
NC
: Supply voltage for DQ
: Ground for DQ
: No connection
Note A0 to A10 : Row address inputs
A0 to A7 : Column address inputs
4
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
Block Diagram
CLK
Clock
Generator
CKE
Bank D
Bank C
Bank B
Row
Address
Address
Buffer
&
Refresh
Counter
Mode
Register
Bank A
Sense Amplifier
DQM
DQ
/CS
Column Decoder &
Latch Circuit
Column
Address
Buffer
&
Burst
Counter
/RAS
/CAS
/WE
Data Control Circuit
5
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
CONTENTS
1. Input / Output Pin Function .............................................................................................................. 8
2. Commands ......................................................................................................................................... 9
3. Simplified State Diagram ................................................................................................................ 12
4. Truth Table ....................................................................................................................................... 13
4.1 Command Truth Table............................................................................................................................. 13
4.2 DQM Truth Table...................................................................................................................................... 13
4.3 CKE Truth Table....................................................................................................................................... 13
4.4 Operative Command Table .................................................................................................................... 14
4.5 Command Truth Table for CKE ............................................................................................................. 17
5. Initialization ...................................................................................................................................... 18
6. Programming the Mode Register ................................................................................................... 19
7. Mode Register .................................................................................................................................. 20
7.1 Burst Length and Sequence .................................................................................................................. 21
8. Address Bits of Bank-Select and Precharge ................................................................................ 22
9. Precharge ......................................................................................................................................... 23
10. Auto Precharge ................................................................................................................................ 24
10.1 Read with Auto Precharge .................................................................................................................. 24
10.2 Write with Auto Precharge .................................................................................................................. 25
11. Read / Write Command Interval ..................................................................................................... 26
11.1 Read to Read Command Interval ........................................................................................................ 26
11.2 Write to Write Command Interval ....................................................................................................... 26
11.3 Write to Read Command Interval ........................................................................................................ 27
11.4 Read to Write Command Interval ........................................................................................................ 28
12. Burst Termination ........................................................................................................................... 29
12.1 Burst Stop Command .......................................................................................................................... 29
12.2 Precharge Termination ........................................................................................................................ 30
12.2.1 Precharge Termination in READ Cycle .................................................................................... 30
12.2.2 Precharge Termination in WRITE Cycle .................................................................................. 31
6
Data Sheet M14376EJ2V0DS00
µ
PD4564323 for Rev. E
13. Electrical Specifications ................................................................................................................. 32
13.1 AC Parameters for Read Timing ......................................................................................................... 37
13.2 AC Parameters for Write Timing ......................................................................................................... 39
13.3 Relationship between Frequency and Latency ................................................................................. 40
13.4 Mode Register Set ................................................................................................................................ 41
13.5 Power on Sequence and CBR (Auto) Refresh ................................................................................... 42
13.6 /CS Function ......................................................................................................................................... 43
13.7 Clock Suspension during Burst Read (using CKE Function) .......................................................... 44
13.8 Clock Suspension during Burst Write (using CKE Function) .......................................................... 46
13.9 Power Down Mode and Clock Mask ................................................................................................... 48
13.10 CBR (Auto) Refresh ............................................................................................................................. 49
13.11 Self Refresh (Entry and Exit) ............................................................................................................... 50
13.12 Random Column Read (Page with Same Bank) ................................................................................ 51
13.13 Random Column Write (Page with Same Bank) ................................................................................ 53
13.14 Random Row Read (Ping-Pong Banks) ............................................................................................. 55
13.15 Random Row Write (Ping-Pong Banks) ............................................................................................. 57
13.16 Read and Write ..................................................................................................................................... 59
13.17 Interleaved Column Read Cycle ......................................................................................................... 61
13.18 Interleaved Column Write Cycle ......................................................................................................... 63
13.19 Auto Precharge after Read Burst ....................................................................................................... 65
13.20 Auto Precharge after Write Burst ....................................................................................................... 67
13.21 Full Page Read Cycle ........................................................................................................................... 69
13.22 Full Page Write Cycle ........................................................................................................................... 71
13.23 Byte Write Operation ........................................................................................................................... 73
13.24 Burst Read and Single Write (Option) ................................................................................................ 74
13.25 Full Page Random Column Read ........................................................................................................ 75
13.26 Full Page Random Column Write ....................................................................................................... 76
13.27 PRE (Precharge) Termination of Burst ............................................................................................... 77
14. Package Drawing ............................................................................................................................. 79
15. Recommended Soldering Condition ............................................................................................. 80
16. Revision History .............................................................................................................................. 80
7
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
1. Input / Output Pin Function
Pin name
Input / Output
Input
Function
CLK
CKE
CLK is the master clock input. Other inputs signals are referenced to the CLK rising
edge.
Input
CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising
edge is valid; otherwise it is invalid. If the CLK rising edge is invalid, the internal clock
is not issued and the µPD4564323 suspends operation.
When the µPD4564323 is not in burst mode and CKE is negated, the device enters
power down mode. During power down mode, CKE must remain low.
/CS
Input
Input
Input
/CS low starts the command input cycle. When /CS is high, commands are ignored
but operations continue.
/RAS, /CAS, /WE
A0 - A10
/RAS, /CAS and /WE have the same symbols on conventional DRAM but different
functions. For details, refer to the command table.
Row Address is determined by A0 - A10 at the CLK (clock) rising edge in the active
command cycle.
Column Address is determined by A0 - A7 at the CLK rising edge in the read or write
command cycle.
A10 defines the precharge mode. When A10 is high in the precharge command cycle,
all banks are precharged; when A10 is low, only the bank selected by BA0 and BA1 is
precharged.
When A10 is high in read or write command cycle, the precharge starts automatically
after the burst access.
BA0, BA1
Input
Input
BA0 and BA1 are the bank select signal. In command cycle, BA0 and BA1 low select
bank A, BA0 low and BA1 high select bank C, BA0 high and BA1 low select bank B
and then BA0 and BA1 high select bank D.
DQM0 - DQM3
DQM controls I/O buffers. DQM0 controls DQ0 - DQ7, DQM1 controls DQ8 - DQ15,
DQM2 controls DQ16 - DQ23, DQM3 controls DQ24 - DQ31.
In read mode, DQM controls the output buffers like a conventional /OE pin.
DQM high and DQM low turn the output buffers off and on, respectively.
The DQM latency for the read is two clocks.
In write mode, DQM controls the word mask. Input data is written to the memory cell if
DQM is low but not if DQM is high.
The DQM latency for the write is zero.
DQ0 - DQ31
Input / Output
(Power supply)
DQ pins have the same function as I/O pins on a conventional DRAM.
VCC, VSS, VCCQ,
VSSQ
VCC and VSS are power supply pins for internal circuits. VCCQ and VSSQ are power
supply pins for the output buffers.
8
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
2. Commands
Mode register set command
Fig.1 Mode register set command
CLK
(/CS, /RAS, /CAS, /WE = Low)
CKE
/CS
H
The µPD4564323 has a mode register that defines how the device
operates. In this command, A0 through A10, BA0 and BA1 are the data input
pins. After power on, the mode register set command must be executed to
initialize the device.
/RAS
/CAS
/WE
The mode register can be set only when all banks are in idle state.
During 2 CLK (tRSC) following this command, the µPD4564323 cannot
accept any other commands.
BA0, BA1
(Bank select)
A10
Add
Activate command
Fig.2 Row address strobe and
bank activate command
(/CS, /RAS = Low, /CAS, /WE = High)
CLK
CKE
/CS
H
The µPD4564323 has four banks, each with 4,096 rows.
This command activates the bank selected by BA0 and BA1 and a row
address selected by A0 through A10.
/RAS
/CAS
/WE
This command corresponds to a conventional DRAM’s /RAS falling.
BA0, BA1
(Bank select)
A10
Add
Row
Row
Precharge command
Fig.3 Precharge command
CLK
(/CS, /RAS, /WE = Low, /CAS = High)
CKE
/CS
H
This command begins precharge operation of the bank selected by BA0 and
BA1. When A10 is High, all banks are precharged, regardless of BA0 and
BA1. When A10 is Low, only the bank selected by BA0 and BA1 is
precharged.
/RAS
/CAS
/WE
After this command, the µPD4564323 can’t accept the activate command to
the precharging bank during tRP (precharge to activate command period).
This command corresponds to a conventional DRAM’s /RAS rising.
BA0, BA1
(Bank select)
A10
(Precharge select)
Add
9
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
Write command
Fig.4 Column address and write
command
(/CS, /CAS, /WE = Low, /RAS = High)
CLK
CKE
/CS
H
If the mode register is in the burst write mode, this command sets the burst
start address given by the column address to begin the burst write operation.
The first write data in burst mode can input with this command with
subsequent data on following clocks.
/RAS
/CAS
/WE
BA0, BA1
(Bank select)
A10
Add
Col.
Read command
Fig.5 Column address and read
command
(/CS, /CAS = Low, /RAS, /WE = High)
CLK
CKE
/CS
H
Read data is available after /CAS latency requirements have been met.
This command sets the burst start address given by the column address.
/RAS
/CAS
/WE
BA0, BA1
(Bank select)
A10
Add
Col.
CBR (auto) refresh command
Fig.6 CBR (auto) refresh command
CLK
(/CS, /RAS, /CAS = Low, /WE, CKE = High)
CKE
/CS
H
This command is a request to begin the CBR (auto) refresh operation. The
refresh address is generated internally.
/RAS
/CAS
/WE
Before executing CBR (auto) refresh, all banks must be precharged.
After this cycle, all banks will be in the idle (precharged) state and ready for
a row activate command.
BA0, BA1
(Bank select)
During tRC period (from refresh command to refresh or activate command),
the µPD4564323 cannot accept any other command.
A10
Add
10
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
Self refresh entry command
Fig.7 Self refresh entry command
CLK
CKE
/CS
(/CS, /RAS, /CAS, CKE = Low, /WE = High)
After the command execution, self refresh operation continues while CKE
remains low. When CKE goes high, the µPD4564323 exits the self refresh
mode.
/RAS
/CAS
/WE
During self refresh mode, refresh interval and refresh operation are
performed internally, so there is no need for external control.
Before executing self refresh, all banks must be precharged.
BA0, BA1
(Bank select)
A10
Add
Burst stop command
Fig.8 Burst stop command in Full
Page Mode
(/CS, /WE = Low, /RAS, /CAS = High)
This command can stop the current burst operation.
CLK
CKE
H
/CS
/RAS
/CAS
/WE
BA0, BA1
(Bank select)
A10
Add
No operation
Fig.9 No operation
CLK
(/CS = Low, /RAS, /CAS, /WE = High)
CKE
/CS
H
This command is not an execution command. No operations begin or
terminate by this command.
/RAS
/CAS
/WE
BA0, BA1
(Bank select)
A10
Add
11
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
3. Simplified State Diagram
Self
Refresh
MRS
Mode
Register
Set
REF
CBR(auto)
Refresh
IDLE
Power
Down
CKE
CKE
Active
Power
Down
ROW
ACTIVE
Write
Read
CKE
Read
CKE
WRITE
WRITE
READ
SUSPEND
READ
SUSPEND
Write
CKE
CKE
CKE
CKE
CKE
READA
SUSPEND
WRITEA
WRITEA
READA
SUSPEND
CKE
Precharge
POWER
ON
Precharge
Automatic sequence
Manual input
12
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
4. Truth Table
4.1 Command Truth Table
Function
Symbol
CKE
/CS
/RAS
/CAS
/WE
BA0,
BA1
×
A10
A9 - A0
n – 1
H
n
×
×
×
×
×
×
×
×
×
×
×
Device deselect
No operation
DESL
NOP
H
L
L
L
L
L
L
L
L
L
L
×
H
H
H
H
H
H
L
×
H
H
L
×
H
L
×
×
×
×
H
×
Burst stop
BST
H
×
×
×
Read
READ
READA
WRIT
WRITA
ACT
H
H
H
L
V
L
V
V
V
V
V
×
Read with auto precharge
Write
H
L
V
H
L
H
L
V
Write with auto precharge
Bank activate
H
L
L
V
H
V
L
H
H
H
H
L
H
L
V
Precharge select bank
Precharge all banks
Mode register set
PRE
H
L
V
PALL
MRS
H
L
L
×
H
L
×
H
L
L
L
V
Remark
H = High level, L = Low level, × = High or Low level (Don't care), V = Valid data input
4.2 DQM Truth Table
Function
Symbol
CKE
DQM
n-1
H
H
H
H
H
H
H
H
H
H
n
×
×
×
×
×
×
×
×
×
×
0
1
2
3
Data write/output enable
ENB
L
Data mask/output disable
MASK
ENB0
H
DQ0 - DQ7 write enable/output enable
DQ8 - DQ15 write enable/output enable
DQ16 - DQ23 write enable/output enable
DQ24 - DQ31 write enable/output enable
DQ0 - DQ7 write inhibit/output disable
DQ8 - DQ15 write inhibit/output disable
DQ16 - DQ23 write inhibit/output disable
DQ24 - DQ31 write inhibit/output disable
L
×
×
×
H
×
×
×
×
L
×
×
×
H
×
×
×
×
L
×
×
×
H
×
×
×
×
L
×
×
×
H
ENB1
ENB2
ENB3
MASK0
MASK1
MASK2
MASK3
Remark
H = High level, L = Low level, × = High or Low level (Don't care)
4.3 CKE Truth Table
Current state
Function
Symbol
CKE
n – 1
/CS
/RAS
/CAS
/WE
Address
n
L
Activating
Any
Clock suspend mode entry
Clock suspend
H
L
×
×
×
L
L
L
H
×
H
L
×
×
×
L
L
H
×
×
×
H
×
×
×
L
L
H
×
×
×
H
×
×
×
×
×
×
×
×
×
×
×
×
L
Clock suspend
Idle
Clock suspend mode exit
CBR (auto) refresh command
Self refresh entry
L
H
H
L
×
REF
H
H
L
H
H
H
×
Idle
SELF
Self refresh
Self refresh exit
H
H
L
L
Idle
Power down entry
Power down exit
H
L
×
Power down
H
H
×
L
H
Remark
H = High level, L = Low level, × = High or Low level (Don't care)
13
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
4.4 Operative Command Table Note1
(1/3)
Current state
Idle
/CS /RAS /CAS /WE
Address
Command
DESL
NOP or BST
Action
Nop or power down
Nop or power down
Notes
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
×
H
H
H
L
×
H
L
×
×
×
×
2
2
3
3
H
L
BA, CA, A10 READ/READA ILLEGAL
L
BA, CA, A10 WRIT/WRITA
ILLEGAL
H
H
L
H
L
BA, RA
ACT
Row activating
L
BA, A10
PRE/PALL
REF/SELF
MRS
Nop
L
H
L
×
CBR (auto) refresh or self refresh
4
L
L
Op-Code
Mode register accessing
Row active
×
×
×
×
×
DESL
Nop
Nop
H
H
H
L
H
L
×
NOP or BST
H
L
BA, CA, A10 READ/READA Begin read : Determine AP
5
5
3
6
L
BA, CA, A10 WRIT/WRITA
Begin write : Determine AP
ILLEGAL
H
H
L
H
L
BA, RA
ACT
L
BA, A10
PRE/PALL
REF/SELF
MRS
Precharge
L
H
L
×
ILLEGAL
L
L
Op-Code
ILLEGAL
Read
×
×
×
×
×
×
DESL
Continue burst to end → Row active
Continue burst to end → Row active
Burst stop → Row active
H
H
H
H
L
H
H
L
H
L
NOP
BST
H
L
BA, CA, A10 READ/READA Terminate burst, new read : Determine AP
7
7, 8
3
L
BA, CA, A10 WRIT/WRITA
Terminate burst, start write : Determine AP
ILLEGAL
H
H
L
H
L
BA, RA
ACT
L
BA, A10
PRE/PALL
REF/SELF
MRS
Terminate burst, precharging
ILLEGAL
L
H
L
×
L
L
Op-Code
ILLEGAL
Write
×
×
×
×
×
×
DESL
Continue burst to end → Write recovering
Continue burst to end → Write recovering
Burst stop → Row active
H
H
H
H
L
H
H
L
H
L
NOP
BST
H
L
BA, CA, A10 READ/READA Terminate burst, start read : Determine AP
7, 8
7
L
BA, CA, A10 WRIT/WRITA
Terminate burst, new write : Determine AP
H
H
L
H
L
BA, RA
BA, A10
×
ACT
ILLEGAL
3
L
PRE/PALL
REF/SELF
MRS
Terminate burst, precharging
ILLEGAL
9
L
H
L
L
L
Op-Code
ILLEGAL
14
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
(2/3)
Current state
Read with auto
precharge
/CS /RAS /CAS /WE
Address
Command
DESL
Action
Notes
H
L
L
L
L
L
L
L
L
×
H
H
H
H
L
×
H
H
L
×
H
L
×
×
×
Continue burst to end → Precharging
Continue burst to end → Precharging
ILLEGAL
NOP
BST
H
L
BA, CA, A10 READ/READA ILLEGAL
3
3
3
3
L
BA, CA, A10 WRIT/WRITA
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
H
H
L
H
L
BA, RA
BA, A10
×
ACT
L
PRE/PALL
REF/SELF
MRS
L
H
L
L
L
Op-Code
×
Write with auto
precharge
H
×
×
×
DESL
Continue burst to end → Write
recovering with auto precharge
L
H
H
H
×
×
NOP
BST
Continue burst to end → Write
recovering with auto precharge
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
H
H
L
H
L
L
H
L
ILLEGAL
BA, CA, A10 READ/READA ILLEGAL
3
3
3
3
L
BA, CA, A10 WRIT/WRITA
ILLEGAL
H
H
L
H
L
BA, RA
ACT
ILLEGAL
L
BA, A10
PRE/PALL
REF/SELF
MRS
ILLEGAL
L
H
L
×
ILLEGAL
L
L
Op-Code
ILLEGAL
Precharging
×
×
×
×
×
×
DESL
Nop → Enter idle after tRP
Nop → Enter idle after tRP
ILLEGAL
H
H
H
H
L
H
H
L
H
L
NOP
BST
H
L
BA, CA, A10 READ/READA ILLEGAL
3
3
3
L
BA, CA, A10 WRIT/WRITA
ILLEGAL
H
H
L
H
L
BA, RA
ACT
ILLEGAL
L
BA, A10
PRE/PALL
REF/SELF
MRS
Nop → Enter idle after tRP
ILLEGAL
L
H
L
×
L
L
Op-Code
ILLEGAL
Row activating
×
×
×
×
×
×
DESL
Nop → Enter bank active after tRCD
Nop → Enter bank active after tRCD
ILLEGAL
H
H
H
H
L
H
H
L
H
L
NOP
BST
H
L
BA, CA, A10 READ/READA ILLEGAL
3
3
L
BA, CA, A10 WRIT/WRITA
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
H
H
L
H
L
BA, RA
BA, A10
×
ACT
3, 10
3
L
PRE/PALL
REF/SELF
MRS
L
H
L
L
L
Op-Code
15
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
(3/3)
Current state
/CS /RAS /CAS /WE
Address
Command
DESL
Action
Notes
Write recovering
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
×
H
H
H
H
L
×
H
H
L
×
H
L
×
×
×
Nop → Enter row active after tDPL
Nop → Enter row active after tDPL
Nop → Enter row active after tDPL
NOP
BST
H
L
BA, CA, A10 READ/READA Start read, Determine AP
8
L
BA, CA, A10 WRIT/WRITA
New write, Determine AP
ILLEGAL
H
H
L
H
L
BA, RA
ACT
3
3
L
BA, A10
PRE/PALL
REF/SELF
MRS
ILLEGAL
L
H
L
×
ILLEGAL
L
L
Op-Code
ILLEGAL
Write recovering
×
×
×
H
L
×
×
×
DESL
Nop → Enter precharge after tDPL
Nop → Enter precharge after tDPL
Nop → Enter precharge after tDPL
with auto precharge
H
H
H
H
L
H
H
L
NOP
BST
H
L
BA, CA, A10 READ/READA ILLEGAL
3, 8
3
L
BA, CA, A10 WRIT/WRITA
ILLEGAL
H
H
L
H
L
BA, RA
ACT
ILLEGAL
3
L
BA, A10
PRE/PALL
REF/SELF
MRS
ILLEGAL
L
H
L
×
ILLEGAL
L
L
Op-Code
ILLEGAL
Refreshing
×
×
×
×
×
×
×
×
H
L
×
×
×
×
×
×
×
×
×
×
DESL
Nop → Enter idle after tRC
Nop → Enter idle after tRC
ILLEGAL
H
H
L
H
L
NOP/BST
READ/WRIT
ACT/PRE/PALL
REF/SELF/MRS
DESL
H
L
ILLEGAL
L
ILLEGAL
Mode register
accessing
×
×
Nop → Enter idle after tRSC
Nop → Enter idle after tRSC
ILLEGAL
H
H
H
H
H
L
NOP
BST
×
READ/WRIT
ILLEGAL
L
L
×
×
ACT/PRE/PALL/
REF/SELF/MRS
ILLEGAL
Notes 1.
2.
All entries assume that CKE was active (High level) during the preceding clock cycle.
If all banks are idle, and CKE is inactive (Low level), µPD4564323 will enter Power down mode.
All input buffers except CKE will be disabled.
3.
4.
Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA),
depending on the state of that bank.
If all banks are idle, and CKE is inactive (Low level), µPD4564323 will enter Self refresh mode. All input
buffers except CKE will be disabled.
5.
6.
7.
8.
9.
Illegal if tRCD is not satisfied.
Illegal if tRAS is not satisfied.
Must satisfy burst interrupt condition.
Must satisfy bus contention, bus turn around, and/or write recovery requirements.
Must mask preceding data which don't satisfy tDPL.
Illegal if tRRD is not satisfied.
10.
Remark
16
H = High level, L = Low level, × = High or Low level (Don’t care), V = Valid data
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
4.5 Command Truth Table for CKE
Current State
CKE
n – 1
/CS /RAS /CAS /WE Address
Action
Notes
n
×
Self refresh
H
L
×
H
L
L
L
×
H
L
L
L
H
L
L
L
×
H
L
×
H
L
L
L
L
H
L
L
L
L
×
×
×
×
×
×
×
×
×
H
H
L
×
×
H
H
L
×
H
H
L
×
×
H
×
×
H
L
L
L
×
H
L
L
L
×
×
×
×
×
×
×
×
×
H
L
×
×
×
H
L
×
×
H
L
×
×
×
H
×
×
×
H
L
L
×
×
H
L
L
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
H
×
×
×
×
H
L
×
×
×
H
L
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
INVALID, CLK (n-1) would exit self refresh
H
H
H
H
L
Self refresh recovery
Self refresh recovery
ILLEGAL
L
L
L
ILLEGAL
L
Maintain self refresh
Idle after tRC
Self refresh recovery
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
Idle after tRC
ILLEGAL
ILLEGAL
ILLEGAL
L
ILLEGAL
L
ILLEGAL
L
ILLEGAL
Power down
All banks idle
×
INVALID, CLK (n – 1) would exit power down
EXIT power down → Idle
H
H
L
×
×
×
L
L
Maintain power down mode
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
CBR (auto) refresh
×
Op-Code Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
Refer to operations in Operative Command Table
L
L
L
×
Self refresh
Op-Code Refer to operations in Operative Command Table
1
1
1
2
L
×
×
×
×
Power down
Row active
H
L
×
Refer to operations in Operative Command Table
Power down
×
Any state other than
listed above
H
H
L
H
L
Refer to operations in Operative Command Table
Begin clock suspend next cycle
Exit clock suspend next cycle
Maintain clock suspend
×
×
×
H
L
L
Notes 1.
2.
Self refresh can be entered only from the all banks idle state. Power down can be entered only from all
banks idle or row active state.
Must be legal command as defined in Operative Command Table.
Remark
H = High level, L = Low level, × = High or Low level (Don't care)
17
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
5. Initialization
The synchronous DRAM is initialized in the power-on sequence according to the following.
(1) To stabilize internal circuits, when power is applied, a 100 µs or longer pause must precede any signal toggling.
(2) After the pause, all banks must be precharged using the Precharge command (The Precharge all banks
command is convenient).
(3) Once the precharge is completed and the minimum tRP is satisfied, the mode register can be programmed. After
the mode register set cycle, tRSC (2 CLK minimum) pause must be satisfied as well.
(4) Two or more CBR (Auto) refresh must be performed.
Remarks 1.
2.
The sequence of Mode register programming and Refresh above may be transposed.
CKE and DQM must be held high until the Precharge command is issued to ensure data-bus Hi-Z.
18
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
6. Programming the Mode Register
The mode register is programmed by the Mode register set command using address bits A10 through A0, BA0 and
BA1 as data inputs. The register retains data until it is reprogrammed or the device loses power.
The mode register has four fields;
Options
/CAS latency : A6 through A4
Wrap type : A3
: A10 through A7, BA0, BA1
Burst length : A2 through A0
Following mode register programming, no command can be issued before at least 2 CLK have elapsed.
/CAS Latency
/CAS latency is the most critical of the parameters being set. It tells the device how many clocks must elapse
before the data will be available.
13.3 Relationship
The value is determined by the frequency of the clock and the speed grade of the device.
between Frequency and Latency
shows the relationship of /CAS latency to the clock period and the speed grade of
the device.
Burst Length
Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is
completed, the output bus will become Hi-Z.
The burst length is programmable as 1, 2, 4, 8 or full page.
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data will be addressed. This order is programmable as either
“Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system.
Some microprocessor cache systems are optimized for sequential addressing and others for interleaved
7.1 Burst Length and Sequence
addressing.
shows the addressing sequence for each burst length using them.
Both sequences support bursts of 1, 2, 4 and 8. Additionally, sequence supports the full page length.
19
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
7. Mode Register
BA1 BA0 A10 A9
A8
0
A7
1
A6
A6
A6
A5
A4
A4
A4
A3
A2
A2
A2
A1
A0
A0
A0
0
0
0
0
JEDEC Standard Test Set (refresh counter test)
BA1 BA0 A10 A9
A8
0
A7
0
A5
A3
A1
BL
x
x
x
1
LTMODE
WT
Burst Read and Single Write
(for Write Through Cache)
BA1 BA0 A10 A9
A8
1
A7
0
A5
A3
A1
Use in future
BA1 BA0 A10 A9
A8
1
A7
1
A6
V
A5
V
A4
V
A3
V
A2
V
A1
V
A0
V
x
x
x
x
Vender Specific
Mode Register Set
V = Valid
x = Don’ t care
BA1 BA0 A10 A9
A8
0
A7
0
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
LTMODE
WT
BL
Bits2-0
000
001
010
011
100
101
110
111
WT = 0
WT = 1
1
1
2
2
4
4
Burst length
8
8
R
R
R
R
R
R
R
Full page
0
1
Sequential
Interleave
Wrap type
Bits6-4
000
001
010
011
100
101
110
111
/CAS latency
R
R
2
3
Latency
mode
R
R
R
R
Remark R : Reserved
Mode Register Set Timing
CLK
CKE
/CS
/RAS
/CAS
/WE
A0 - A10,
BA0, BA1
Mode Register Set
20
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
7.1 Burst Length and Sequence
[Burst of Two]
Starting address
Sequential addressing sequence
(decimal)
Interleave addressing sequence
(column address A0, binary)
(decimal)
0
1
0, 1
1, 0
0, 1
1, 0
[Burst of Four]
Starting address
Sequential addressing sequence
(decimal)
Interleave addressing sequence
(decimal)
(column address A1 - A0, binary)
00
01
10
11
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
[Burst of Eight]
Starting address
Sequential addressing sequence
(decimal)
Interleave addressing sequence
(decimal)
(column address A2 - A0, binary)
000
001
010
011
100
101
110
111
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 4, 5, 6, 7, 0
2, 3, 4, 5, 6, 7, 0, 1
3, 4, 5, 6, 7, 0, 1, 2
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 0, 1, 2, 3, 4
6, 7, 0, 1, 2, 3, 4, 5
7, 0, 1, 2, 3, 4, 5, 6
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
Full page burst is an extension of the above tables of sequential addressing, with the length being 256.
21
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
8. Address Bits of Bank-Select and Precharge
BA1 BA0
Result
Row
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9 A10 BA0 BA1
Select Bank A
“Activate” command
0
0
1
1
0
1
0
1
(Activate command)
Select Bank B
“Activate” command
Select Bank C
“Activate” command
Select Bank D
“Activate” command
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9 A10 BA0 BA1
A10 BA1 BA0 Result
(Precharge command)
0
0
0
0
1
0
0
1
1
x
0
1
0
1
x
Precharge Bank A
Precharge Bank B
Precharge Bank C
Precharge Bank D
Precharge All Banks
x : Don’t care
disables Auto-Precharge
(End of Burst)
0
1
enables Auto-Precharge
(End of Burst)
Col.
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9 A10 BA0 BA1
(/CAS strobes)
BA1 BA0
Result
enables Read/Write
commands for Bank A
0
0
1
1
0
1
0
1
enables Read/Write
commands for Bank B
enables Read/Write
commands for Bank C
enables Read/Write
commands for Bank D
22
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
9. Precharge
The precharge command can be issued anytime after tRAS (MIN.) is satisfied.
Soon after the precharge command is issued, precharge operation performed and the synchronous DRAM enters
the idle state after tRP is satisfied. The parameter tRP is the time required to perform the precharge.
The earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is
as follows.
It is depending on the /CAS latency and clock cycle time.
Burst length=4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
/CAS latency = 2
PRE
Q3
Read
Command
Hi-Z
DQ
Q1
Q2
Q4
Q3
/CAS latency = 3
Command
Read
PRE
Q2
Hi-Z
DQ
Q1
Q4
(tRAS must be satisfied)
In order to write all data to the memory cell correctly, the asynchronous parameter “tDPL” must be satisfied. The
tDPL(MIN.) specification defines the earliest time that a precharge command can be issued. Minimum number of clocks
is calculated by dividing tDPL(MIN.) with clock cycle time.
In summary, the precharge command can be issued relative to reference clock that indicates the last data word is
valid. In the following table, minus means clocks before the reference; plus means time after the reference.
/CAS latency
Read
–1
Write
2
3
+tDPL (MIN.)
+tDPL (MIN.)
–2
23
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
10. Auto Precharge
During a read or write command cycle, A10 controls whether auto precharge is selected. A10 high in the Read or
Write command (Read with Auto precharge command or Write with Auto precharge command), auto precharge is
selected and begins automatically.
The tRAS must be satisfied with a read with auto precharge or a write with auto precharge operation. In addition, the
next activate command to the bank being precharged cannot be executed until the precharge cycle ends.
In read cycle, once auto precharge has started, an activate command to the bank can be issued after tRP has been
satisfied.
In write cycle, the tDAL must be satisfied to issue the next activate command to the bank being precharged.
The timing that begins the auto precharge cycle depends on both the /CAS latency programmed into the mode
register and whether read or write cycle.
10.1 Read with Auto Precharge
During a read cycle, the auto precharge begins one clock earlier (/CAS latency of 2) or two clocks earlier (/CAS
latency of 3) the last data word output.
Burst length = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CLK
/CAS latency = 2
Auto precharge starts
Command
READA B
Hi-Z
DQ
QB1
QB2
QB3
QB4
/CAS latency = 3
Auto precharge starts
Command
READA B
Hi-Z
DQ
QB1
QB2
QB3
QB4
(tRAS must be satisfied)
Remark
READA means Read with Auto precharge
24
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
10.2 Write with Auto Precharge
During a write cycle, the auto precharge starts at the timing that is equal to the value of the tDPL (MIN.) after the last
data word input to the device.
Burst length = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
/CAS latency = 2
Auto precharge starts
Command
WRITA B
DB1
Hi-Z
DQ
DB2
DB3
DB4
t
DPL(MIN.)
/CAS latency = 3
Auto precharge starts
Command
WRITA B
DB1
Hi-Z
DQ
DB2
DB3
DB4
t
DPL(MIN.)
(tRAS must be satisfied)
Remark
WRITA means Write with Auto Precharge
In summary, the auto precharge begins relative to a reference clock that indicates the last data word is valid.
In the table below, minus means clocks before the reference; plus means after the reference.
/CAS latency
Read
–1
Write
2
3
+tDPL (MIN.)
+tDPL (MIN.)
–2
25
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
11. Read / Write Command Interval
11.1 Read to Read Command Interval
During a read cycle, when new Read command is issued, it will be effective after /CAS latency, even if the previous
read operation does not completed. READ will be interrupted by another READ.
The interval between the commands is 1 cycle minimum. Each Read command can be issued in every clock
without any restriction.
Burst length = 4, /CAS latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CLK
Command
Read A
Read B
Hi-Z
DQ
QA1
QB1
QB2
QB3
QB4
1cycle
11.2 Write to Write Command Interval
During a write cycle, when a new Write command is issued, the previous burst will terminate and the new burst will
begin with a new Write command. WRITE will be interrupted by another WRITE.
The interval between the commands is minimum 1 cycle. Each Write command can be issued in every clock
without any restriction.
Burst length = 4, /CAS latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command
DQ
Write A
DA1
Write B
DB1
Hi-Z
DB2
DB3
DB4
1cycle
26
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
11.3 Write to Read Command Interval
Write command and Read command interval is also 1 cycle.
Only the write data before Read command will be written.
The data bus must be Hi-Z at least one cycle prior to the first DOUT.
Burst length = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
/CAS latency = 2
Command
Write A
DA1
Read B
Hi-Z
DQ
QB1
QB2
QB3
QB4
/CAS latency = 3
Command
Write A
DA1
Read B
Hi-Z
DQ
QB1
QB2
QB3
QB4
27
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
11.4 Read to Write Command Interval
During a read cycle, READ can be interrupted by WRITE.
The Read and Write command interval is 1 cycle minimum. There is a restriction to avoid data conflict. The Data
bus must be Hi-Z using DQM before WRITE.
Burst length = 4
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command
DQM
Read
Write
Hi-Z
DQ
D1
D2
D3
D4
1cycle
READ can be interrupted by WRITE. DQM must be High at least 3 clocks prior to the Write command.
Burst length = 8
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CLK
/CAS latency = 2
Command
Read
Write
DQM
DQ
Q1
Q2
Q3
D1
Write
D1
D2
D3
Hi-Z is
necessary
/CAS latency = 3
Command
Read
DQM
DQ
Q1
Q2
D2
D3
Hi-Z is
necessary
28
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
12. Burst Termination
There are two methods to terminate a burst operation other than using a Read or a Write command. One is the
burst stop command and the other is the precharge command.
12.1 Burst Stop Command
During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus
goes to Hi-Z after the /CAS latency from the burst stop command.
Burst length = X
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Command
Read
BST
/CAS latency = 2
Hi-Z
DQ
Q1
Q2
Q1
Q3
/CAS latency = 3
Hi-Z
DQ
Q2
Q3
Remark
BST: Burst stop command
During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes
to Hi-Z at the same clock with the burst stop command.
Burst length = X
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Command
Write
BST
/CAS latency = 2, 3
Hi-Z
DQ
D1
D2
D3
D4
Remark
BST: Burst stop command
29
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
12.2 Precharge Termination
12.2.1 Precharge Termination in READ Cycle
During a read cycle, the burst read operation is terminated by a precharge command.
When the precharge command is issued, the burst read operation is terminated and precharge starts.
The same bank can be activated again after tRP from the precharge command.
To issue a precharge command, tRAS must be satisfied.
When /CAS latency is 2, the read data will remain valid until one clock after the precharge command.
Burst length = X, /CAS latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Command
Read
PRE
ACT
Hi-Z
DQ
Q1
Q2
Q3
Q4
t
RP
(tRAS must be satisfied)
When /CAS latency is 3, the read data will remain valid until two clocks after the precharge command.
Burst length = X, /CAS latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command
Read
PRE
ACT
Hi-Z
DQ
Q1
Q2
Q3
Q4
t
RP
(tRAS must be satisfied)
30
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
12.2.2 Precharge Termination in WRITE Cycle
During a write cycle, the burst write operation is terminated by a precharge command.
When the precharge command is issued, the burst write operation is terminated and precharge starts.
The same bank can be activated again after tRP from the precharge command.
To issue a precharge command, tRAS must be satisfied.
When /CAS latency is 2, the write data written prior to the precharge command will be correctly stored. However,
invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM
must be high at the same clock as the precharge command. This will mask the invalid data.
Burst length = X, /CAS latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Command
Write
PRE
ACT
DQM
DQ
Hi-Z
D1
D2
D3
D4
D5
t
RP
(tRAS must be satisfied)
When /CAS latency is 3, the write data written prior to the precharge command will be correctly stored. However,
invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM
must be high at the same clock as the precharge command. This will mask the invalid data.
Burst length = X, /CAS latency = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command
Write
PRE
ACT
DQM
DQ
Hi-Z
D1
D2
D3
D4
D5
t
RP
(tRAS must be satisfied)
31
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
13. Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 100 µs and then, execute
proper device operation is achieved.
Power on sequence and CBR (auto) Refresh
before
Absolute Maximum Ratings
Parameter
Voltage on power supply pin relative to GND
Voltage on input pin relative to GND
Short circuit output current
Power dissipation
Symbol
Condition
Rating
−0.5 to +4.6
−0.5 to +4.6
50
Unit
VCC, VCCQ
V
V
VT
IO
mA
W
PD
TA
Tstg
1
Operating ambient temperature
Storage temperature
0 to 70
°C
°C
−55 to + 125
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
VCC, VCCQ
VIH
Condition
MIN.
3.0
TYP.
3.3
MAX.
3.6
Unit
V
Supply voltage
High level input voltage
2.0
V
CC + 0.3 Note1
V
Low level input voltage
VIL
−0.3 Note 2
+0.8
V
Operating ambient temperature
TA
0
70
°C
Notes 1.
2.
VIH(MAX.) = VCC + 1.5 V (Pulse width ≤ 5ns)
VIL(MIN.) = –1.5 V (Pulse width ≤ 5ns)
Pin Capacitance (TA = 25 C, f = 1 MHz)
°
Parameter
Symbol
CI1
Condition
MIN.
TYP.
MAX.
Unit
pF
Input capacitance
A0 - A10, BA0, BA1
2.5
2.5
4
4
CI2
CLK, CKE, /CS, /RAS, /CAS,
/WE, DQM0 - DQM3
Data input / output capacitance
CI/O
DQ0 - DQ31
4
6.5
pF
32
Data Sheet M14376EJ2V0DS00
µ
PD4564323 for Rev. E
DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted)
/CAS
latency
Parameter
Symbol
ICC1
Test conditions
Burst length = 1,
Grade
Maximum
Unit
mA
Notes
1
Operating current
CL=2
-A60
-A70
-A80
-A10
-A10B
-A60
-A70
-A80
-A10
-A10B
150
140
130
130
120
160
150
140
140
130
1
tRC ≥ tRC(MIN.),
IO = 0 mA,
One bank active
CL=3
Precharge standby current
in power down mode
ICC2P
CKE ≤ VIL(MAX.), tCK = 15 ns
CKE ≤ VIL(MAX.), tCK = ∞
mA
mA
ICC2PS
1
Precharge standby current in ICC2N
non power down mode
ICC2NS
CKE ≥ VIH(MIN.), tCK = 15 ns,
≥ VIH(MIN.),
20
CS
Input signals are changed one time during 30 ns
CKE ≥ VIH(MIN.), tCK = ∞,
6
Input signals are stable.
Active standby current in
power down mode
ICC3P
ICC3PS
ICC3N
CKE ≤ VIL(MAX.), tCK = 15 ns
5
4
mA
mA
CKE ≤ VIL(MAX.), tCK = ∞
Active standby current in
non power down mode
CKE ≥ VIH(MIN.), tCK = 15 ns, /
≥ VIH(MIN.) ,
30
CS
Input signals are changed one time during 30 ns.
ICC3NS CKE ≥ VIH(MIN.), tCK = ∞, Input signals are stable.
20
Operating current
(Burst mode)
tCK ≥ tCK(MIN.),
IO = 0 mA,
CL=2 -A60
-A70
170
170
170
140
130
240
220
190
180
160
160
150
150
150
130
170
160
160
160
140
1
mA
2
ICC4
ICC5
ICC6
All banks active
-A80
-A10
-A10B
CL=3
CL=2
CL=3
-A60
-A70
-A80
-A10
-A10B
-A60
-A70
-A80
-A10
-A10B
-A60
-A70
-A80
-A10
-A10B
CBR (auto) refresh current
tRC ≥ tRC(MIN.)
mA
3
Self refresh current
CKE ≤ 0.2 V
mA
★
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK(MIN.).
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK(MIN.).
3. ICC5 is measured on condition that addresses are changed only one time during tCK(MIN.).
33
Data Sheet M14376EJ2V0DS00
µ
PD4564323 for Rev. E
DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
II(L)
Test condition
MIN. TYP. MAX. Unit Notes
Input leakage current
0 ≤ VI ≤ VCCQ, VCCQ = VCC,
–1.0
+1.0
µA
All other pins not under test = 0 V
IO(L)
VOH
VOL
Output leakage current
High level output voltage
Low level output voltage
0 ≤ VO ≤ VCCQ, DOUT is disabled
–1.5
2.4
+1.5
µA
V
IO = – 4 mA
IO = + 4 mA
0.4
V
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
Test Conditions
★
Notes
Parameter
Value
2.4 / 0.4
1.4
Unit
AC high level input voltage / low level input voltage
Input timing measurement reference level
Transition time (Input rise and fall time)
Output timing measurement reference level
V
V
1
ns
V
1.4
t
CK
t
CH
t
CL
2.4 V
CLK
1.4 V
0.4 V
t
SETUP
t
HOLD
2.4 V
1.4 V
0.4 V
Input
t
AC
t
OH
Output
34
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
Synchronous Characteristics
Parameter
/CAS Symbol
latency
-A60
-A70
-A80
-A10
-A10B
Unit Note
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Clock cycle time
= 3 tCK3
6
7
8
10
13
10
15
ns
ns
CL
CL
CL
CL
(166MHz)
(100MHz)
5.5
(143MHz)
(100MHz)
5.5
(125MHz)
(100MHz)
(100MHz)
= 2 tCK2
= 3 tAC3
= 2 tAC2
tCH
10
10
10
(100MHz)
(77MHz)
(67MHz)
Access time from CLK
6
6
6
7
7
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
6
6
CLK high level width
CLK low level width
Data-out hold time
2
2
2
2
3
3
3
0
3
3
2
1
2
1
2
1
2
2
3
3
3
0
3
3
2
1
2
1
2
1
2
2
3.5
3.5
3
tCL
tOH
2.5
0
2.5
0
1
Data-out low-impedance time
tLZ
0
Data-out high-impedance
time
= 3 tHZ3
= 2 tHZ2
tDS
2.5
2.5
1.5
0.8
1.5
0.8
2
5.5
6
2.5
2.5
1.5
0.8
1.5
0.8
2
5.5
6
6
6
6
7
3
7
8
CL
CL
3
Data-in setup time
Data-in hold time
Address setup time
Address hold time
CKE setup time
CKE hold time
2.5
1
tDH
tAS
2.5
1
tAH
tCKS
2.5
1
tCKH
1
1
CKE setup time (Power down exit)
tCKSP
tCMS
2
2
2.5
2.5
Command (/ , /
, /
,
1.5
1.5
CS RAS CAS
/
) setup time
WE, DQM
Command (/ , /
, /
,
tCMH
0.8
0.8
1
1
1
ns
CS RAS CAS
/
) hold time
WE, DQM
Note 1.
Output load
1.4V
50Ω
Z = 50Ω
Output
50 pF
35
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
Asynchronous Characteristics
Parameter
/CAS Symbol
latency
-A60
-A70
-A80
-A10
-A10B
Unit Note
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
REF to REF/ACT command
period (Operation)
tRC
60
66
63
70
70
70
70
70
90
90
ns
ns
REF to REF/ACT command
period (Refresh)
tRC1
ACT to PRE command period
PRE to ACT command period
tRAS
tRP
42
18
18
42
20
20
48
20
20
50
20
20
60
30
30
ns
ns
ns
120,000
120,000
120,000
120,000
120,000
Delay time ACT to READ/WRITE
command
tRCD
ACT(one) to ACT(another)
command period
tRRD
12
14
16
20
20
ns
Data-in to PRE command period
tDPL
8
2CLK+18
1CLK+18
2
8
2CLK+20
1CLK+20
2
8
1CLK+20
1CLK+20
2
10
1CLK+20
1CLK+20
2
10
1CLK+30
1CLK+30
2
ns
ns
Data-in to ACT(REF) command
period (Auto precharge)
= 3 tDAL3
= 2 tDAL2
tRSC
CL
CL
ns
Mode register set cycle time
Transition time
CLK
ns
tT
0.5
30
64
0.5
30
64
0.5
30
64
1
30
64
1
30
64
Refresh time (4,096 refresh cycles)
tREF
ms
36
Data Sheet M14376EJ2V0DS00
13.1 AC Parameters for Read Timing (Manual Precharge, Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
t
CK
CLK
t
CH
t
CL
CKE
/CS
t
CKH
t
CKS
t
CMS
t
CMH
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
t
AS
t
AH
µ
µ
L
t
AC
t
AC
t
AC
t
AC
t
HZ
Hi-Z
t
LZ
t
OH
t
OH
t
OH
RP
t
OH
t
RCD
t
RAS
t
t
RC
Activate
Command
for Bank A
Read
Command
for Bank A
Precharge
Command
for Bank A
Activate
Command
for Bank A
AC Parameters for Read Timing (Auto Precharge, Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
t
CK
CLK
t
CH
t
CL
CKE
/CS
Auto Precharge
Start for Bank C
t
CKH
t
CKS
t
CMS
t
CMH
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
t
AS
t
AH
µ
µ
L
t
AC
t
AC
t
AC
t
AC
t
HZ
Hi-Z
tRCD
t
LZ
t
OH
t
OH
t
OH
t
OH
t
RAS
t
RRD
t
RC
Activate
Command
for Bank C
Read with
Auto Precharge
Command
Activate
Command
for Bank D
Activate
Command
for Bank C
for Bank C
13.2 AC Parameters for Write Timing (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
Auto Precharge
Start for Bank C
t
CKH
t
CKS
t
CMS
t
CMH
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
tAS
t
AH
L
µ
µ
t
DS
t
DH
Hi-Z
t
RCD
t
DAL
t
RC
t
RRD
t
RCD
t
DPL
t
RP
t
RAS
t
RC
Write with
Auto Precharge
Command
Activate
Command
for Bank C
Activate
Command
for Bank B
Write
Command
for Bank B
Activate Precharge
Command Command
for Bank C for Bank B
Activate
Command
for Bank B
for Bank C
µPD4564323 for Rev. E
13.3 Relationship between Frequency and Latency
Speed version -A60
Clock cycle time [ns]
-A70
-A80
-A10
-A10B
15
6
166
3
10
100
2
7
143
3
10
100
2
8
125
3
10
100
2
10
100
3
13
77
2
10
100
3
Frequency [MHz]
67
2
2
4
6
6
4
2
2
1
3
2
/CAS latency
[tRCD]
3
2
3
2
3
2
2
2
3
/RAS latency (/CAS latency + [tRCD])
6
4
6
4
6
4
5
4
6
[tRC]
10
11
7
6
9
7
9
7
7
6
9
[tRC1]
[tRAS]
[tRRD]
[tRP]
7
10
6
7
9
7
7
6
9
5
5
6
5
5
4
6
2
2
2
2
2
2
2
2
2
3
2
3
2
3
2
2
2
3
[tDPL]
[tDAL]
[tRSC]
2
1
2
1
1
1
1
1
1
5
3
5
3
4
3
3
3
4
2
2
2
2
2
2
2
2
2
40
Data Sheet M14376EJ2V0DS00
13.4 Mode Register Set (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
t
RSC
2 CLK (MIN.)
/RAS
/CAS
/WE
BA0
BA1
A10
ADDRESS KEY
ADD
DQM
DQ
µ
µ
Hi-Z
Precharge
All Banks
Command
Mode
Register Set
Command
Activate
Command
is valid
t
RP
13.5 Power On Sequence and CBR (Auto) Refresh
CLK
Clock signal is necessary
CKE
t
RSC
High level is necessary
2 refresh cycles are necessary
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
ADDRESS KEY
µ
µ
High level is necessary
Hi-Z
Precharge
All Banks
Command
is necessary
Mode
CBR(Auto)
Refresh
Command
is necessary
CBR (Auto) refresh
Command
Activate
Command
Register Set
Command
is necessary
is necessary
t
RP
t
RC1
t
RC1
13.6 /CS Function (at 100 MHz, Burst Length = 4, /CAS Latency = 3)
Only /CS signal needs to be issued at minimum rate
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
L
L
BA1
A10
ADD
DQM
DQ
RAa
RAa
CAa
CAb
µ
µ
L
Hi-Z
QAa1 QAa2 QAa3 QAa4
DAb1 DAb2 DAb3 DAb4
Activate
Command
for Bank A
Read
Command
for Bank A
Write
Command
for Bank A
Precharge
Command
for Bank A
13.7 Clock Suspension during Burst Read (using CKE Function) (1/2) (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
RAa
RAa
CAa
µ
µ
L
Hi-Z
QAa1 QAa2
QAa3
QAa4
Activate
Command
for Bank A
Read
Command
for Bank A
1-CLOCK
SUSPENDED
2-CLOCK
SUSPENDED
3-CLOCK
SUSPENDED
at the end of burst
Hi-Z (turn off)
Clock Suspension during Burst Read (using CKE Function) (2/2) (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
RAa
RAa
CAa
µ
µ
L
Hi-Z
QAa1 QAa2
QAa3
QAa4
Activate
Read
1-CLOCK
2-CLOCK
3-CLOCK
Hi-Z (turn off)
Command
for Bank A
Command
for Bank A
SUSPENDED
SUSPENDED
SUSPENDED
at the end of burst
13.8 Clock Suspension during Burst Write (using CKE Function) (1/2) (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
RAa
RAa
CAa
µ
µ
L
Hi-Z
DAa1
DAa2
DAa3
DAa4
Activate
Command
for Bank A
Write
Command
for Bank A
1-CLOCK
SUSPENDED
2-CLOCK
SUSPENDED
3-CLOCK
SUSPENDED
Clock Suspension during Burst Write (using CKE Function) (2/2) (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
RAa
RAa
CAa
µ
µ
L
Hi-Z
DAa1
DAa2
DAa3
DAa4
Activate
Command
for Bank A
Write
1-CLOCK
2-CLOCK
SUSPENDED
3-CLOCK
SUSPENDED
Command SUSPENDED
for Bank A
13.9 Power Down Mode and Clock Mask (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
t
CKSP
t
CKSP
CKE
/CS
VALID
/RAS
/CAS
/WE
BA0
BA1
A10
RAa
RAa
ADD
DQM
CAa
L
µ
µ
Hi-Z
QAa1 QAa2 QAa3
QAa4
DQ
Activate
Command
for Bank A
Read
Command
for Bank A
Precharge
Command
for Bank A
Power Down
Mode Entry
Power Down
Mode Exit
Clock Mask
Start
Clock Mask
End
Power Down
Mode Exit
Power Down
Mode Entry
ACTIVE STANDBY
PRECHARGE STANDBY
13.10 CBR (Auto) Refresh
T0
T1
T2
T3
T4
T5
T6
Tn
Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6
Tm Tm + 1 Tm + 2 Tm + 3 Tm + 4 Tm + 5 Tm + 6 Tm + 7
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
µ
µ
L
Hi-Z
Q1
Precharge
Command
CBR (Auto)
Refresh
CBR(Auto)
Refresh
Activate
Command
Read
Command
(if necessary)
t
RP
t
RC1
t
RC1
13.11 Self Refresh (Entry and Exit)
T0
T1
T2
T3
T4
Tn
Tn + 1 Tn + 2
Tm Tm + 1
Tk
Tk + 1 Tk + 2 Tk + 3 Tk + 4
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
µ
µ
L
Hi-Z
Precharge
Command
Self Refresh
Entry
Self Refresh
Exit
Self Refresh Self Refresh
Activate
Command
Entry
Exit
(if necessary)
(or Activate Command)
Next Clock
Enable
Next Clock
Enable
t
RP
t
RC1
t
RC1
13.12 Random Column Read (Page with Same Bank) (1/2) (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
RAd
RAa
RAa
CAa
CAb
CAc
RAd
CAd
µ
µ
L
Hi-Z
QAa1 QAa2 QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4
QAd1 QAd2 QAd3
Activate
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank A
Precharge
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
Random Column Read (Page with Same Bank) (2/2) (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
RAa
RAa
RAa
CAa
CAb
CAc
RAa
CAa
µ
µ
L
Hi-Z
QAa1 QAa2 QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4
Read
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank A
Precharge
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
13.13 Random Column Write (Page with Same Bank) (1/2) (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
RDd
RDa
RDa
CDa
CDb
CDc
RDd
CDd
µ
µ
L
Hi-Z
DDa1 DDa2 DDa3 DDa4 DDb1 DDb2 DDc1 DDc2 DDc3 DDc4
DDd1 DDd2 DDd3 DDd4
Activate
Command
for Bank D
Write
Command
for Bank D
Write
Command
for Bank D
Write
Command
for Bank D
Precharge
Command
for Bank D
Activate
Command
for Bank D
Write
Command
for Bank D
Random Column Write (Page with Same Bank) (2/2) (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
RDd
RDa
RDa
CDa
CDb
CDc
RDd
CDd
µ
µ
L
Hi-Z
DDa1 DDa2 DDa3 DDa4 DDb1 DDb2 DDc1 DDc2 DDc3 DDc4
DDd1 DDd2
Activate
Command
for Bank D
Write
Command
for Bank D
Write
Command
for Bank D
Write
Command
for Bank D
Precharge
Command
for Bank D
Activate
Command
for Bank D
Write
Command
for Bank D
13.14 Random Row Read (Ping-Pong Banks) (1/2) (Burst Length = 8, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
RBa
RBa
RDb
RDa
RDa
CDa
CBa
RDb
CDb
µ
µ
L
Hi-Z
QDa1 QDa2 QDa3 QDa4 QDa5 QDa6 QDa7 QDa8 QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QBa8
Activate
Command
for Bank D
Read
Command
for Bank D
Activate
Command
for Bank B
Read
Command
for Bank B
Activate
Command
for Bank D
Read
Command
for Bank D
Precharge
Command
for Bank D
Random Row Read (Ping-Pong Banks) (2/2) (Burst Length = 8, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
RAa
RAa
RBb
RBa
RBa
CBa
CAa
RBb
CBb
µ
µ
L
Hi-Z
QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QBa8 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7
Activate
Command
for Bank B
Read
Command
for Bank B
Activate
Command
for Bank A
Read
Command
for Bank A
Precharge
Command
for Bank B
Activate
Command
for Bank B
Read
Command
for Bank B
Precharge
Command
for Bank A
13.15 Random Row Write (Ping-Pong Banks) (1/2) (Burst Length = 8, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
RDa
RDa
RAb
RAb
RAa
RAa
CAa
CDa
CAb
µ
µ
L
Hi-Z
DAa1 DAa2 DAa3 DAa4 DAa5 DAa6 DAa7 DAa8 DDa1 DDa2 DDa3 DDa4 DDa5 DDa6 DDa7 DDa8 DAb1 DAb2 DAb3
Activate
Command
for Bank A
Write
Command
for Bank A
Activate
Command
for Bank D
Write
Command
for Bank D
Activate
Command
for Bank A
Write
Command
for Bank A
Precharge
Precharge
Command
for Bank A
Command
for Bank D
Random Row Write (Ping-Pong Banks) (2/2) (Burst Length = 8, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
RDa
RDa
RAb
RAa
RAa
ADD
CAa
CDa
RAb
CAb
µ
µ
L
DQM
Hi-Z
DAa1 DAa2 DAa3 DAa4 DAa5 DAa6 DAa7 DAa8 DDa1 DDa2 DDa3 DDa4 DDa5 DDa6 DDa7 DDa8 DAb1 DAb2
DQ
Activate
Command
for Bank A
Write
Command
for Bank A
Activate
Command
for Bank D
Write
Command
for Bank D
Precharge
Command
for Bank A
Activate
Command
for Bank A
Write
Command
for Bank A
Precharge
Command
for Bank D
13.16 Read and Write (1/2) (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
RAa
RAa
ADD
CAa
CAb
Write Latency = 0
CAc
µ
µ
DQM
DQ
L
Word Masking
Hi-Z
QAa1 QAa2 QAa3 QAa4
DAb1 DAb2
DAb4
QAc1 QAc2
QAc4
Activate
Command
for Bank A
Read
Command
for Bank A
Write
Command
for Bank A
Read
Command
for Bank A
Hi-Z at the end of wrap function
0-Clock Latency
2-Clock Latency
Read and Write (2/2) (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
RAa
RAa
ADD
CAa
CAb
Write Latency = 0
CAc
µ
µ
DQM
DQ
L
Word Masking
Hi-Z
QAa1 QAa2 QAa3 QAa4
DAb1 DAb2
DAb4
QAc1 QAc2
Activate
Read
Write
Read
Command
for Bank A
Command
for Bank A
Command
for Bank A
Command
for Bank A
Hi-Z at the end of wrap function
0-Clock Latency
2-Clock Latency
13.17 Interleaved Column Read Cycle (1/2) (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
RAa
RAa
RDa
RDa
ADD
CAa
CDa
CDb
CDc
CAb
CDd
µ
µ
DQM
DQ
L
Hi-Z
Aa1
Aa2
Aa3
Aa4
Da1
Da2
Db1
Db2
Dc1
Dc2
Ab1
Ab2
Dd1
Dd2
Dd3
Dd4
Activate
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank A
Read
Command
for Bank D
Activate
Command
for bank D
Precharge
Command
for Bank A
Precharge
Command
for Bank D
Interleaved Column Read Cycle (2/2) (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
RAa
RAa
RDa
RDa
ADD
CAa
CDa
CDb
CAb
CDc
µ
µ
DQM
DQ
L
Hi-Z
Aa1
Aa2
Aa3
Aa4
Da1
Da2
Db1
Db2
Dc1
Dc2
Ab1
Ab2
Ab3
Ab4
Activate
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank A
Precharge
Command
for Bank D
Precharge
Command
for Bank A
Activate
Command
for Bank D
13.18 Interleaved Column Write Cycle (1/2) (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
RAa
RAa
RBa
RBa
CAa
Aa1
CBa
Ba1
CBb
Bb1
CBc
CAb
Ab1
CBd
µ
µ
DQM
DQ
L
Hi-Z
Aa2
Aa3
Aa4
Ba2
Bb2
Bc1
Bc2
Ab2
Bd1
Bd2
Bd3
Bd4
Activate
Command
for Bank A
Write
Command
for Bank A
Write
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank A
Write
Command
for Bank B
Activate
Command
for Bank B
Precharge
Command
for Bank A
Precharge
Command
for Bank B
t
DPL
t
DPL
Interleaved Column Write Cycle (2/2) (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
RAa
RAa
RBa
RBa
CAa
Aa1
CBa
Ba1
CBb
Bb1
CAb
CBd
CBc
µ
µ
DQM
DQ
L
Hi-Z
Aa2
Aa3
Aa4
Ba2
Bb2
Bc1
Bc2
Ab1
Ab2
Bd1
Bd2
Bd3
Bd4
Activate
Write
Write
Write
Write
Write
Write
Command
for Bank A
Command
for Bank A
Command
for Bank B
Command
for Bank B
Command
for Bank B
Command
for Bank A
Command
for Bank B
Activate
Command
for Bank B
Precharge
Command
for Bank A
Precharge
Command
for Bank B
13.19 Auto Precharge after Read Burst (1/2) (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
RAa
RAa
RDa
RDa
RDb
RAc
ADD
CAa
CDa
CAb
RDb
CDb
RAc
CAc
µ
µ
DQM
DQ
L
Hi-Z
Activate
Command
for Bank A
Activate
Command
for Bank A
Activate
Command
for Bank D
Activate
Command
for Bank D
Read
Command
for Bank A
Read with
Auto Precharge
Command
Read with
Auto Precharge
Command
Read with
Auto Precharge
Command
Read with
Auto Precharge
Command
for Bank D
for Bank A
for Bank D
for Bank A
Auto Precharge
Start for Bank A
Auto Precharge
Start for Bank D
Auto Precharge
Start for Bank D
Auto Precharge after Read Burst (2/2) (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
RAa
RAa
RDa
RDb
CAa RDa
CDa
CAb
RDb
CDb
L
µ
µ
Hi-Z
Activate
Command
for Bank A
Activate
Command
for Bank D
Read with
Auto Precharge
Command
Read with
Auto Precharge
Command
Auto Precharge
Start for Bank A
Read
Command
for Bank A
Read with
Auto Precharge
Command
for Bank A
for Bank D
Auto Precharge
Start for Bank D
Activate
Command
for Bank D
for Bank D
13.20 Auto Precharge after Write Burst (1/2) (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
RAa
RAa
RDa
RDa
RDb
RAc
ADD
CAa
CDa
CAb
RDb
CDb
RAc
CAc
DQM
DQ
L
µ
µ
Hi-Z
Activate
Command
for Bank A
Activate
Command
for Bank D
Activate
Command
for Bank D
Activate
Command
for Bank A
Write
Command
for Bank A
Write with
Auto Precharge
Command
Write with
Auto Precharge
Command
Write with
Auto Precharge
Command
Write with
Auto Precharge
Command
for Bank D
for Bank D
for Bank A
for Bank A
Auto Precharge
Start for Bank D
Auto Precharge
Start for Bank A
Auto Precharge
Start for Bank D
Auto Precharge after Write Burst (2/2) (Burst Length = 4, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
RAa
RAa
RDa
RDb
CAa RDa
CDa
CAb
RDb
CDb
L
µ
µ
Hi-Z
Activate
Command
for Bank A
Activate
Command
for Bank D
Write with
Auto Precharge
Command
Activate
Command
for bank D
Write with
Auto Precharge
Command
for Bank A
Write
Command
for Bank A
Write with
Auto Precharge
Command
for Bank D
Auto Precharge
Start for Bank D
Auto Precharge
Start for Bank A
for Bank D
13.21 Full Page Read Cycle (1/2) (/CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
Tn
Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8 Tn + 9 Tn + 10 Tn + 11 Tn + 12 Tn + 13
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
RAa
RDa
RDa
RDb
RAa
CAa
CDa
RDb
µ
µ
DQM
DQ
L
Hi-Z
Aa
Aa+1 Aa+2 Aa-2 Aa-1
Aa
Aa+1
Da
Da+1 Da+2 Da+3 Da+4 Da+5 Da+6
Read
Command
for Bank D
Precharge
Command
for Bank D
Activate
Command
for Bank A
Read
Command
for Bank A
Activate
Command
for Bank D
Activate
Command
for Bank D
Burst Stop Command
Full Page Read Cycle (2/2) (/CAS latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
Tn
Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8 Tn + 9 Tn + 10 Tn + 11 Tn + 12
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
RAa
RAa
RDa
RDa
RDb
CAa
CDa
RDb
µ
µ
L
DQM
DQ
Hi-Z
Aa
Aa+1 Aa-3 Aa-2 Aa-1
Aa
Aa+1
Da
Da+1 Da+2 Da+3 Da+4 Da+5
Read
Command
for Bank D
Activate
Command
for Bank A
Read
Command
for Bank A
Activate
Command
for Bank D
Precharge
Command
for Bank D
Activate
Command
for Bank D
Burst Stop Command
13.22 Full Page Write Cycle (1/2) (/CAS latency = 2)
T0
T1
T2
T3
T4
T5
Tn
Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8 Tn + 9 Tn + 10 Tn + 11 Tn + 12 Tn + 13 Tn + 14 Tn + 15
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
RAa
RAa
RDa
RDa
RDb
CAa
Aa
CDa
Da
RDb
µ
µ
DQM
DQ
L
Hi-Z
Aa+1 Aa+2
Aa-2 Aa-1
Aa
Aa+1
Da+1 Da+2 Da+3 Da+4 Da+5
Precharge
Command
for Bank D
Write
Command
for Bank D
Activate
Command
for Bank A
Write
Command
for Bank A
Activate
Command
for Bank D
Activate
Command
for Bank D
Burst Stop Command
Full Page Write Cycle (2/2) (/CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
Tn
Tn + 1 Tn + 2 Tn + 3 Tn + 4 Tn + 5 Tn + 6 Tn + 7 Tn + 8 Tn + 9 Tn + 10 Tn + 11 Tn + 12 Tn + 13
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
RAa
RAa
RDa
RDa
RDb
CAa
Aa
CDa
Da
RDb
µ
µ
DQM
DQ
L
Hi-Z
Aa+1 Aa+2 Aa+3 Aa-1
Aa
Aa+1
Da+1 Da+2 Da+3 Da+4 Da+5
Write
Command
for Bank D
Precharge
Command
for Bank D
Activate
Command
for Bank A
Write
Command
for Bank A
Activate
Command
for Bank D
Activate
Command
for Bank D
Burst Stop Command
Burst is not completed
in the Full Page Mode
13.23 Byte Write Operation (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM0
DQM1
µ
µ
DQ 0-7
DQ 8-15
Activate
Command
for Bank D
Read
Command
for Bank D
Byte 1
not Read
Byte 0
not Write
Byte 1
not Write
Byte 0
not Write
13.24 Burst Read and Single Write (Option) (Burst Length = 4, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
µ
µ
DQM
DQ
Hi-Z
Qa1
Qa2
Qa3
Qa4
D1
Qb1
Qb2
Qb4
D2
Activate
Command
for Bank D
Read
Command
for Bank D
Single
Write
Command
for Bank D
Single
Write
Command
for Bank D
Read
Command
for Bank D
Single
Write
Command
for Bank D
13.25 Full Page Random Column Read (Burst Length = Full Page, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
RAa
RAa
RDa
RDa
CAa
CDa
CAb
CDb
CDc
CAc
t
RCD
t
RRD
t
RCD
µ
µ
L
Hi-Z
Hi-Z
QAa1 QDa1 QAb1 QAb2 QDb1 QDb2 QAc1 QAc2 QAc3 QDc1 QDc2 QDc3
Activate
Command
for Bank D
Activate
Command
for Bank A
Precharge
Command
for Bank D
(PRE Termination of Burst)
Read
Command
for Bank A
Read
Command
for Bank D
Read
Command
for Bank A
Read
Command
for Bank D
Read
Command
for Bank A
Read
Command
for Bank D
13.26 Full Page Random Column Write (Burst Length = Full Page, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
RAa
RAa
RDa
RDa
CAa
CDa
CAb
CDb
CDc
CAc
t
RCD
t
RRD
t
RCD
L
µ
µ
Hi-Z
DAa1 DDa1 DAb1 DAb2 DDb1 DDb2 DAc1 DAc2 DAc3 DDc1 DDc2 DDc3 DDc4
Activate
Command
for Bank A
Activate
Command
for Bank D
Precharge
Command
for Bank D
(PRE Termination of Burst)
Write
Write
Command
for Bank A
Write
Command
for Bank D
Write
Command
for Bank A
Write
Command
for Bank D
Command
for Bank A
Write
Command
for Bank D
13.27 PRE (Precharge) Termination of Burst (1/2) (Burst Length = 8, /CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
RAa
RAa
RAb
RAb
RAc
RAc
CAa
CAb
Write
Masking
L
µ
µ
Hi-Z
Hi-Z
DAa1 DAa2 DAa3 DAa4 DAa5
QAb1 QAb2 QAb3 QAb4 QAb5
Activate
Write
Read
Activate
Command
for Bank A
Command
for Bank A
Command
for Bank A
Command
for Bank A
Precharge
Command
for Bank A
Activate
Command
for Bank A
Precharge
Command
for Bank A
PRE Termination
of Burst
PRE Termination
of Burst
t
RCD
t
DPL
t
RP
t
RAS
t
RAS
PRE (Precharge) Termination of Burst (2/2) (Burst Length = 8, /CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0
BA1
A10
ADD
DQM
DQ
RAa
RAa
RAb
RAc
CAa
RAb
CAb
RAc
L
Write
Mask
µ
µ
Hi-Z
Hi-Z
DAa1 DAa2 DAa3 DAa4 DAa5
QAb1 QAb2 QAb3 QAb4
Write
Command
for Bank A
Read
Command
for Bank A
Activate
Command
for Bank A
Activate
Command
for Bank A
Precharge
Command
PRE Termination
for Bank A
Activate
Command
for Bank A
Precharge
Command
for Bank A
PRE Termination
of Burst
of Burst
t
RCD
t
DPL
t
RP
t
RAS
t
RAS
µ
PD4564323 for Rev. E
★
14. Package Drawing
86-PIN PLASTIC TSOP (II) (10.16 mm (400))
detail of lead end
G
86
44
F
R
P
L
S
E
1
43
A
H
I
J
S
L
C
N
S
K
D
M
M
B
NOTES
1. Each lead centerline is located within 0.08 mm of
ITEM MILLIMETERS
A
B
C
22.22±0.05
0.765 MAX.
0.5 (T.P.)
its true position (T.P.) at maximum material condition.
2. Dimension "A" does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
+0.08
0.22
D
−0.07
E
F
G
H
I
0.10±0.05
1.1±0.1
1.00
11.76±0.20
10.16±0.10
0.80±0.20
J
+0.025
0.145
K
−0.015
L
M
N
0.50
0.08
0.10
+5°
3°
P
−3°
R
S
0.25
0.60±0.15
S86G5-50-9JH-1
79
Data Sheet M14376EJ2V0DS00
µ
PD4564323 for Rev. E
15. Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of the µPD4564323.
Type of Surface Mount Device
µPD4564323G5: 86-pin Plastic TSOP (II) (10.16 mm (400))
16. Revision History
Edition /
Date
Page
Description
This
Previous
edition
Type of
revision
Location
–
edition
1st edition /
June 1999
–
–
–
2nd edition /
December 1999
p.2
p.2
Deletion
µPD4564323G5-A60L-9JH, 4564323G5-A70L-9JH, 4564323G5-A80L-9JH,
µPD4564323G5-A10L-9JH, 4564323G5-A10BL-9JH
L (Low Power)
p.3
p.3
Deletion
Deletion
p.33
p.34
p.79
p.33
p.34
p.79
ICC6 (-AxxL (Maximum))
Modification Test Conditions
Modification Package Drawing
80
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
[MEMO]
81
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
[MEMO]
82
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
83
Data Sheet M14376EJ2V0DS00
µPD4564323 for Rev. E
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8
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