DS1746W-120 [DALLAS]
Y2K-Compliant, Nonvolatile Timekeeping RAMs; Y2K兼容，非易失时钟RAM
| 型号： | DS1746W-120 |
| 厂家： | 
DALLAS SEMICONDUCTOR |
| 描述： | Y2K-Compliant, Nonvolatile Timekeeping RAMs |
| 文件： | 总18页 (文件大小：226K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DS1746/DS1746P
Y2KC Nonvolatile Timekeeping RAM
www.dalsemi.com
FEATURES
PIN ASSIGNMENT
ꢀ Integrated NV SRAM, real time clock,
crystal, power-fail control circuit and lithium
energy source
ꢀ Clock registers are accessed identical to the
static RAM. These registers are resident in the
eight top RAM locations.
ꢀ Century byte register; ie., Y2K compliant
ꢀ Totally nonvolatile with over 10 years of
operation in the absence of power
ꢀ BCD coded century, year, month, date, day,
hours, minutes, and seconds with automatic
leap year compensation valid up to the year
2100
NC
A16
A14
A12
A7
A6
A5
A4
A3
1
32
31
VCC
A15
NC
WE
A13
A8
2
3
4
30
29
5
6
28
27
A9
7
8
26
25
A11
OE
A10
CE
9
10
24
23
A2
A1
11
12
22
21
DQ7
DQ6
DQ5
DQ4
DQ3
A0
13
14
15
16
20
19
18
17
DQ0
DQ1
DQ2
ꢀ Battery voltage level indicator flag
ꢀ Power-fail write protection allows for ±10%
GND
32-Pin Encapsulated Package
VCC power supply tolerance
ꢀ Lithium energy source is electrically
disconnected to retain freshness until power is
applied for the first time
34
NC
NC
A14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
NC
A15
A16
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
ꢀ DIP Module only
-
Standard JEDEC bytewide 128k x 8 static
RAM pinout
A13
A12
A11
A10
A9
RST
VCC
WE
OE
CE
ꢀ PowerCap Module Board only
A8
DQ7
DQ6
DQ5
DQ4
DQ3
-
Surface mountable package for direct
connection to PowerCap containing
battery and crystal
A7
A6
A5
A4
A3
A2
A1
A0
DQ2
DQ1
DQ0
GND
-
-
-
Replaceable battery (PowerCap)
Power-On Reset Output
Pin for pin compatible with other densities
of DS174XP Timekeeping RAM
VBAT X2
X1 GND
34-Pin PowerCap Module Board
(Uses DS9034PCX PowerCap)
1 of 18
022101
DS1746/DS1746P
PIN DESCRIPTION
A0–A16
– Address Input
CE
– Chip Enable
OE
– Output Enable
WE
– Write Enable
VCC
– Power Supply Input
– Ground
– Data Input/Output
– No Connection
GND
DQ0–DQ7
NC
RST
– Power–on Reset Output (Power–
Cap Module board only)
– Crystal Connection
X1, X2
VBAT
– Battery Connection
ORDERING INFORMATION
DS1746P
(5V)
blank 32-pin DIP Module
P
34-pin PowerCap Module board*
DS1746WP (3.3V)
blank 32-pin DIP Module
34-pin PowerCap Module board*
P
*DS9034PCX (PowerCap) Required:
(must be ordered separately)
DESCRIPTION
The DS1746 is a full function, year 2000 compliant (Y2KC), real-time clock/calendar (RTC) and 128k x
8 non-volatile static RAM. User access to all registers within the DS1746 is accomplished with a
bytewide interface as shown in Figure 1. The Real Time Clock (RTC) information and control bits reside
in the eight uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours,
minutes, and seconds data in 24-hour BCD format. Corrections for the date of each month and leap year
are made automatically. The RTC clock registers are double buffered to avoid access of incorrect data
that can occur during clock update cycles. The double buffered system also prevents time loss as the
timekeeping countdown continues unabated by access to time register data. The DS1746 also contains its
own power-fail circuitry which deselects the device when the VCC supply is in an out of tolerance
condition. This feature prevents loss of data from unpredictable system operation brought on by low VCC
as errant access and update cycles are avoided.
2 of 18
DS1746/DS1746P
DS1746 BLOCK DIAGRAM Figure 1
PACKAGES
The DS1746 is available in two packages (32-pin DIP and 34-pin PowerCap module). The 32-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1746P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to the high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.
CLOCK OPERATIONS-READING THE CLOCK
While the double buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1746 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a one is written into the read bit, bit 6 of the century register, see Table 2. As
long as a one remains in that position, updating is halted. After a halt is issued, the registers reflect the
count, that is day, date, and time that was current at the moment the halt command was issued. However,
the internal clock registers of the double buffered system continue to update so that the clock accuracy is
not affected by the access of data. All of the DS1746 registers are updated simultaneously after the
internal clock register updating process has been re-enabled. Updating is within a second after the read bit
is written to zero. The READ bit must be a zero for a minimum of 500 µs to ensure the external registers
will be updated.
3 of 18
DS1746/DS1746P
DS1746 TRUTH TABLE Table 1
VCC
MODE
DQ
POWER
CE
OE
WE
VIH
VIL
VIL
VIL
X
X
X
VIL
VIH
X
X
VIL
VIH
VIH
X
DESELECT
WRITE
READ
READ
DESELECT
DESELECT
HIGH-Z
DATA IN
DATA OUT
HIGH-Z
HIGH-Z
HIGH-Z
STANDBY
ACTIVE
ACTIVE
VCC>VPF
ACTIVE
VSO<VCC<VPF
VCC<VSO<VPF
CMOS STANDBY
DATA RETENTION
MODE
X
X
X
SETTING THE CLOCK
As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a one, like the
read bit, halts updates to the DS1746 registers. The user can then load them with the correct day, date and
time data in 24 hour BCD format. Resetting the write bit to a zero then transfers those values to the actual
clock counters and allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the seconds registers, see
Table 2. Setting it to a one stops the oscillator.
FREQUENCY TEST BIT
As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to
logic “1” and the oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the
seconds register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for
access remain valid (i.e., CE low, OE low, WE high, and address for seconds register remain valid and
stable).
CLOCK ACCURACY (DIP MODULE)
The DS1746 is guaranteed to keep time accuracy to within ±1 minute per month at 25°C. The RTC is
calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not require
additional calibration. For this reason, methods of field clock calibration are not available and not
necessary. Clock accuracy is also effected by the electrical environment and caution should be taken to
place the RTC in the lowest level EMI section of the PCB layout. For additional information please see
application note 58.
CLOCK ACCURACY (POWERCAP MODULE)
The DS1746 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module will typically keep time accuracy to within ±1.53 minutes per month (35 ppm) at 25°C. Clock
accuracy is also effected by the electrical environment and caution should be taken to place the RTC in
the lowest level EMI section of the PCB layout. For additional information please see application note
58.
4 of 18
DS1746/DS1746P
DS1746 REGISTER MAP Table 2
DATA
B4
ADDRESS
FUNCTION/RANGE
B7
B6
B5
10 YEAR
X
B3
X
B2
B1
B0
1FFFF
1FFFE
1FFFD
1FFFC
1FFFB
1FFFA
1FFF9
YEAR
YEAR
MONTH
DATE
00-99
01-12
01-31
01-07
00-23
00-59
00-59
00-39
X
X
BF
X
X
X
FT
X
10 MO
10 DATE
MONTH
DATE
X
X
DAY
DAY
10 HOUR
HOUR
HOUR
X
10 MINUTES
10 SECONDS
10 CENTURY
MINUTES
SECONDS
CENTURY
MINUTES
SECONDS
CENTURY
OSC
W
1FFF8
R
OSC = STOP BIT
= WRITE BIT
R
X
= READ BIT
= SEE NOTE BELOW
FT = FREQUENCY TEST
BF = BATTERY FLAG
W
NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1746 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE
(chip enable) is low. The device architecture allows ripple-through access to any of the address locations
in the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is
stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times
and states are not met, valid data will be available at the latter of chip enable access (tCEA) or at output
enable access time (tOEA). The state of the data input/output pins (DQ) is controlled by CE and OE . If the
outputs are activated before tAA , the data lines are driven to an intermediate state until tAA . If the address
inputs are changed while CE and OE remain valid, output data will remain valid for output data hold
time (tOH) but will then go indeterminate until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1746 is in the write mode whenever WE , and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE , or CE . The addresses must be held valid throughout
the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or
write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDS afterward. In a
typical application, the OE signal will be high during a write cycle. However, OE can be active
provided that care is taken with the data bus to avoid bus contention. If OE is low prior to
WE transitioning low the data bus can become active with read data defined by the address inputs. A low
transition on WE will then disable the output tWEZ after WE goes active.
5 of 18
DS1746/DS1746P
DATA RETENTION MODE
The 5-volt device is fully accessible and data can be written or read only when VCC is greater than VPF
.
However, when VCC is below the power fail point, VPF , (point at which write protection occurs) the
internal clock registers and SRAM are blocked from any access. At this time the power fail reset output
signal (RST) is driven active and will remain active until VCC returns to nominal levels. When VCC falls
below the battery switch point VSO (battery supply level), device power is switched from the VCC pin to
the backup battery. RTC operation and SRAM data are maintained from the battery until VCC is returned
to nominal levels. The 3.3 volt device is fully accessible and data can be written or read only when VCC is
greater than VPF . When VCC falls below the power fail point, VPF , access to the device is inhibited. At this
time the power fail reset output signal (RST ) is driven active and will remain active until VCC returns to
nominal levels. If VPF is less than VSO, the device power is switched from VCC to the backup supply
(VBAT) when VCC drops below VPF
.
If VPF is greater than VSO
,
the device power is switched from VCC to
the backup supply (VBAT when VCC drops below VSO
)
.
RTC operation and SRAM data are maintained
from the battery until VCC is returned to nominal levels. The RST signal is an open drain output and
requires a pull up. Except for the RST , all control, data, and address signals must be powered down
when VCC is powered down.
BATTERY LONGEVITY
The DS1746 has a lithium power source that is designed to provide energy for clock activity, and clock
and RAM data retention when the VCC supply is not present. The capability of this internal power supply
is sufficient to power the DS1746 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at 25°C with the internal clock oscillator running in
the absence of VCC power. Each DS1746 is shipped from Dallas Semiconductor with its lithium energy
source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than
VPF , the lithium energy source is enabled for battery backup operation. Actual life expectancy of the
DS1746 will be much longer than 10 years since no lithium battery energy is consumed when VCC is
present.
BATTERY MONITOR
The DS1746 constantly monitors the battery voltage of the internal battery. The Battery Flag bit (bit 7) of
the day register is used to indicate the voltage level range of the battery. This bit is not writable and
should always be a one when read. If a zero is ever present, an exhausted lithium energy source is
indicated and both the contents of the RTC and RAM are questionable.
6 of 18
DS1746/DS1746P
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Storage Temperature
–0.3V to +6.0V
–40°C to +85°C
Soldering Temperature
260°C for 10 seconds (DIP Package) (See Note 7)
See IPC/JEDEC Standard J-STD-020A for
Surface Mount Devices
* This is a stress rating only and functional operation of the device at these or any other condition above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
OPERATING RANGE
Range
Temperature
VCC
Commercial
0°C to +70°C
3.3V ± 10% or 5V ± 10%
RECOMMENDED DC OPERATING CONDITIONS (Over the Operating Range)
PARAMETER
Logic 1 Voltage All Inputs
VCC = 5V±10%
SYMBOL
MIN
TYP
MAX
VCC+0.3
V
VCC+0.3
V
UNITS NOTES
VIH
2.2
V
V
1
1
VCC = 3.3V±10%
VIH
2.0
Logic 0 Voltage All Inputs
VCC = 5V±10%
VIL
VIL
-0.3
-0.3
0.8
0.6
V
V
1
1
VCC = 3.3V±10%
DC ELECTRICAL CHARACTERISTICS
(Over the Operating Range; VCC = 5.0V ± 10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
Active Supply Current
TTL Standby Current
Icc
85
mA
2,3
Icc1
6
mA
2,3
(CE = VIH)
CMOS Standby Current
Icc2
IIL
4
mA
2,3
(CE ≥VCC-0.2V)
Input Leakage Current (any input)
Output Leakage Current
(any output)
-1
-1
+1
+1
µA
µA
IOL
Output Logic 1 Voltage
(IOUT = -1.0 mA)
Output Logic 0 Voltage
(IOUT = +2.1 mA)
VOH
VOL
2.4
1
1
0.4
Write Protection Voltage
Battery Switch Over Voltage
VPF
VSO
4.25
4.50
V
1
1,4
VBAT
7 of 18
DS1746/DS1746P
DC ELECTRICAL CHARACTERISTICS
(Over the Operating Range; VCC = 3.3V ± 10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
Active Supply Current
TTL Standby Current
Icc
30
mA
2,3
Icc1
2
mA
2,3
(CE = VIH)
CMOS Standby Current
Icc2
IIL
2
mA
2,3
(CE ≥VCC-0.2V)
Input Leakage Current (any input)
Output Leakage Current
(any output)
-1
-1
+1
+1
µA
µA
IOL
Output Logic 1 Voltage
(IOUT = -1.0 mA)
VOH
2.4
1
Output Logic 0 Voltage
(IOUT = +2.1 mA)
Write Protection Voltage
Battery Switch Over Voltage
VOL
VPF
0.4
1
1
2.80
2.97
V
V
VBAT
or
VSO
1,4
VPF
READ CYCLE, AC CHARACTERISTICS
(Over the Operating Range; VCC = 5.0V ± 10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
tRC
70
ns
Read Cycle Time
Address Access Time
CE to DQ Low-Z
CE Access Time
tAA
tCEL
tCEA
tCEZ
tOEL
tOEA
tOEZ
tOH
70
ns
ns
ns
ns
ns
ns
ns
ns
5
5
5
70
25
CE Data Off Time
OE to DQ Low-Z
OE Access Time
35
25
OE Data Off Time
Output Hold from Address
8 of 18
DS1746/DS1746P
READ CYCLE, AC CHARACTERISTICS
(Over the Operating Range; VCC = 3.3V ± 10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
tRC
120
ns
Read Cycle Time
Address Access Time
CE to DQ Low-Z
CE Access Time
tAA
tCEL
tCEA
tCEZ
tOEL
tOEA
tOEZ
tOH
120
ns
ns
ns
ns
ns
ns
ns
ns
5
5
5
120
40
CE Data Off Time
OE to DQ Low-Z
OE Access Time
100
35
OE Data Off Time
Output Hold from Address
READ CYCLE TIMING DIAGRAM
9 of 18
DS1746/DS1746P
WRITE CYCLE, AC CHARACTERISTICS
(Over the Operating Range; VCC = 5.0V ± 10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Write Cycle Time
tWC
70
ns
Address Setup Time
tAS
tWEW
tCEW
tDS
0
50
60
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WE Pulse Width
CE Pulse Width
Data Setup Time
Data Hold Time
Data Hold Time
Address Hold Time
Address Hold Time
tDH1
tDH2
tAH1
tAH2
tWEZ
tWR
8
9
8
9
0
5
5
25
WE Data Off Time
Write Recovery Time
5
WRITE CYCLE, AC CHARACTERISTICS
(Over the Operating Range; VCC = 3.3V ± 10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Write Cycle Time
tWC
120
ns
Address Setup Time
tAS
tWEW
tCEW
tCEW
tDS
0
100
110
110
80
0
120
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WE Pulse Width
CE Pulse Width
CE and CE2 Pulse Width
Data Setup Time
Data Hold Time
tDH1
tDH2
tAH1
tAH2
tWEZ
tWR
8
9
8
9
Data Hold Time
0
Address Hold Time
Address Hold Time
0
10
40
WE Data Off Time
Write Recovery Time
10
10 of 18
DS1746/DS1746P
WRITE CYCLE TIMING DIAGRAM, WRITE ENABLE CONTROLLED
WRITE CYCLE TIMING DIAGRAM, CHIP ENABLE CONTROLLED
11 of 18
DS1746/DS1746P
POWER−UP/DOWN AC CHARACTERISTICS
(Over the Operating Range; VCC = 5.0V ± 10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
tPD
0
µs
CE or WE at VH
Before Power-down
VCC Fall Time: VPF(MAX) to
VPF(MIN)
tF
300
µs
VCC Fall Time: VPF(MIN) to VSO
VCC Rise Time: VPF(MIN) to
VPF(MAX)
tFB
tR
10
0
µs
µs
Power-up Recover Time
Expected Data Retention Time
(Oscillator ON)
tREC
tDR
35
ms
years
10
5,6
POWER–UP/POWER–DOWN TIMING 5 VOLT DEVICE
12 of 18
DS1746/DS1746P
POWER–UP/DOWN CHARACTERISTICS
(Over the Operating Range; VCC = 3.3V ± 10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
tPD
0
µs
CE or WE at VH, Before
Power-down
VCC Fall Time: VPF(MAX) to
VPF(MIN)
VCC Rise Time: VPF(MIN) to
VPF(MAX)
tF
300
0
µs
µs
tR
tREC
tDR
35
ms
VPF to RST High
Expected Data Retention Time
(Oscillator ON)
10
years
5,6
POWER–UP/DOWN WAVEFORM TIMING 3.3 VOLT DEVICE
CAPACITANCE
t A = 25°C)
PARAMETER
SYMBOL
CIN
MIN
TYP
MAX
7
10
UNITS
NOTES
Capacitance on all input pins
Capacitance on all output pins
pF
pF
CO
13 of 18
DS1746/DS1746P
AC TEST CONDITIONS
Output Load:
Input Pulse Levels:
100 pF + 1TTL Gate
0.0 to 3.0V
Timing Measurement Reference Levels:
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5 ns
NOTES:
1. Voltages are referenced to ground.
2. Typical values are at 25°C and nominal supplies.
3. Outputs are open.
4. Battery switch over occurs at the lower of either the battery terminal voltage or VPF
.
5. Data retention time is at 25°C.
6. Each DS1746 has a built–in switch that disconnects the lithium source until VCC is first applied by the
user. The expected tDR is defined for DIP modules and assembled PowerCap modules as a cumulative
time in the absence of V CC starting from the time power is first applied by the user.
7. Real–Time Clock Modules (DIP) can be successfully processed through conventional wave–soldering
techniques as long as temperatures as long as temperature exposure to the lithium energy source
contained within does not exceed +85°C. Post solder cleaning with water washing techniques is
acceptable, provided that ultra-sonic vibration is not used.
In addition, for the PowerCap:
a. Dallas Semiconductor recommends that PowerCap Module bases experience one pass through
solder reflow oriented with the label side up (“live – bug”).
b. Hand Soldering and touch–up: Do not touch or apply the soldering iron to leads for more than
3 (three) seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To
remove the part, apply flux, heat the lead frame pad until the solder reflows and use a solder wick
to remove solder.
8.tAH1 , tDH1 are measured from WE going high.
9. tAH2 , tDH2 are measured from CE going high.
14 of 18
DS1746/DS1746P
DS1647 32–PIN PACKAGE
PKG
DIM
A IN.
MM
32-PIN
MAX
MIN
1.670
38.42
0.715
18.16
0.335
8.51
1.690
38.93
0.740
18.80
0.365
9.27
B
C
D
E
F
IN.
MM
IN.
MM
IN.
MM
IN.
MM
IN.
MM
IN.
MM
IN.
MM
IN.
MM
IN.
MM
0.075
1.91
0.105
0.67
0.015
0.38
0.030
0.76
0.140
3.56
0.180
4.57
G
H
J
0.090
2.29
0.110
2.79
0.590
14.99
0.010
0.25
0.630
16.00
0.018
0.45
K
0.015
0.38
0.025
0.64
15 of 18
DS1746/DS1746P
DS1746P
PKG
DIM
A
B
C
D
E
F
G
INCHES
MIN
0.920
0.980
-
0.052
0.048
0.015
0.025
NOM
0.925
0.985
-
0.055
0.050
0.020
0.027
MAX
0.930
0.990
0.080
0.058
0.052
0.025
0.030
NOTE:
Dallas Semiconductor recommends that PowerCap Module bases experience one pass through solder
reflow oriented with the label side up (“live – bug”).
Hand Soldering and touch–up: Do not touch or apply the soldering iron to leads for more than 3 (three)
seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To remove the part,
apply flux, heat the lead frame pad until the solder reflows and use a solder wick to remove solder.
16 of 18
DS1746/DS1746P
DS1746P WITH DS9034PCX ATTACHED
PKG
INCHES
DIM MIN NOM MAX
A
B
C
D
E
F
0.920 0.925 0.930
0.955 0.960 0.965
0.240 0.245 0.250
0.052 0.055 0.058
0.048 0.050 0.052
0.015 0.020 0.025
0.020 0.025 0.030
G
COMPONENTS AND PLACEMENT MAY
VARY FROM EACH DEVICE TYPE
17 of 18
DS1746/DS1746P
RECOMMENDED POWERCAP MODULE LAND PATTERN
PKG
INCHES
DIM
MIN
NOM MAX
A
B
C
D
E
-
-
-
-
-
1.050
0.826
0.050
0.030
0.112
-
-
-
-
-
18 of 18
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