DS1746W-120IND+ [MAXIM]
Y2K-Compliant, Nonvolatile Timekeeping RAMs; Y2K兼容，非易失时钟RAM
| 型号： | DS1746W-120IND+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Y2K-Compliant, Nonvolatile Timekeeping RAMs |
| 文件： | 总16页 (文件大小：131K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5503; Rev 9/10
DS1746/DS1746P
Y2K-Compliant, Nonvolatile Timekeeping RAMs
www.maxim-ic.com
FEATURES
PIN CONFIGURATIONS
. Integrated NV SRAM, Real-Time Clock,
Crystal, Power-Fail Control Circuit, and
Lithium Energy Source
. Clock Registers are Accessed Identically to
the Static RAM. These Registers are Resident
in the Eight Top RAM Locations.
. Century Byte Register (i.e., Y2K Compliant)
. Totally Nonvolatile with Over 10 Years of
Operation in the Absence of Power
. BCD-Coded Century, Year, Month, Date,
Day, Hours, Minutes, and Seconds with
Automatic Leap Year Compensation Valid
Up to the Year 2100
TOP VIEW
N.C.
A16
A14
A12
A7
VCC
A15
N.C.
WE
A13
A8
1
32
31
Maxim
DS1746
2
3
4
30
29
5
6
28
27
A6
A5
A9
A11
7
8
26
25
A4
A3
OE
A10
CE
9
10
24
23
A2
A1
11
12
22
21
DQ7
DQ6
DQ5
DQ4
DQ3
A0
13
14
15
16
20
19
18
17
DQ0
DQ1
DQ2
. Battery Voltage-Level Indicator Flag
. Power-Fail Write Protection Allows for ±10%
GND
V
CC Power Supply Tolerance
Encapsulated DIP
. Lithium Energy Source is Electrically
Disconnected to Retain Freshness Until
Power is Applied for the First Time
. DIP Module Only
Standard JEDEC Byte-Wide 128k x 8 Static
RAM Pinout
. PowerCap Module Board Only
Surface Mountable Package for Direct
Connection to PowerCap Containing
Battery and Crystal
Replaceable Battery (PowerCap)
Power-On Reset Output
Pin-for-Pin Compatible with Other Densities
of DS174xP Timekeeping RAM
. Also Available in Industrial Temperature
Range: -40°C to +85°C
N.C.
A15
A16
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
N.C.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Maxim
DS1746P
N.C.
A14
A13
A12
A11
A10
A9
RST
VCC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
A8
A7
A6
A5
A4
A3
A2
A1
A0
DQ2
DQ1
DQ0
GND
X1 GND
VBAT
X2
PowerCap Module Board
(Uses DS9034PCX PowerCap)
. Underwriters Laboratories (UL) recognized
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
1 of 16
DS1746/DS1746P Y2K-Compliant, Nonvolatile Timekeeping RAMs
PIN DESCRIPTION
PIN
PowerCap
NAME
FUNCTION
PDIP
1, 30
2
1, 33, 34
3
N.C.
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
A10
A11
A9
No Connection
3
4
5
6
7
8
9
32
30
25
24
23
22
21
20
19
18
28
29
27
26
31
2
16
15
14
13
12
11
10
9
Address Input
10
11
12
23
25
26
27
28
31
13
14
15
17
18
19
20
21
16
22
24
29
32
A8
A13
A15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
GND
CE
Data Input/Output
17
8
7
6
5
Ground
Active-Low Chip Enable Input
Active-Low Output Enable Input
Active-Low Write-Enable Input
Power-Supply Input
OE
WE
VCC
Active-Low Power-Fail Output, Open Drain. Requires a pullup resistor for
proper operation.
—
4
RST
Crystal Connection, VBAT Battery Connection. UL recognized to ensure
against reverse charging when used with a lithium battery. www.maxim-
ic.com/qa/info/ul/
X1, X2,
VBAT
—
2 of 16
DS1746/DS1746P Y2K-Compliant, Nonvolatile Timekeeping RAMs
ORDERING INFORMATION
VOLTAGE
RANGE
(V)
PART
TEMP RANGE
PIN-PACKAGE
TOP MARK†
DS1746-70+
DS1746-70IND+
DS1746P-70+
DS1746P-70IND+
DS1746W-120+
DS1746W-120IND+
DS1746WP-120+
DS1746WP-120IND+
5.0
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
32 EDIP (0.740a)
32 EDIP (0.740a)
34 PowerCap*
34 PowerCap*
32 EDIP (0.740a)
32 EDIP (0.740a)
34 PowerCap*
34 PowerCap*
DS1746+070
DS1746+070 IND
DS1746P+70
DS1746P+070 IND
DS1746W+120
DS1746W+120 IND
DS1746WP+120
DS1746WP+120 IND
5.0
5.0
5.0
3.3
3.3
3.3
3.3
+Denotes a lead(Pb)-free/RoHS-compliant package. The top mark will include a “+” symbol on lead-free devices.
*DS9034-PCX+ or DS9034I-PCX+ required (must be ordered separately).
† An “IND” anywhere on the top mark denotes an industrial temperature grade device.
DESCRIPTION
The DS1746 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) and
128k x 8 nonvolatile static RAM. User access to all registers within the DS1746 is accomplished with a
byte-wide interface as shown in Figure 1. The RTC information and control bits reside in the eight
uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours, minutes,
and seconds data in 24-hour binary-coded decimal (BCD) format. Corrections for the date of each month
and leap year are made automatically. The RTC clock registers are double buffered to avoid access of
incorrect data that can occur during clock update cycles. The double-buffered system also prevents time
loss as the timekeeping countdown continues unabated by access to time register data. The DS1746 also
contains its own power-fail circuitry, which deselects the device when the VCC supply is in an out of
tolerance condition. This feature prevents loss of data from unpredictable system operation brought on by
low VCC as errant access and update cycles are avoided.
3 of 16
DS1746/DS1746P Y2K-Compliant, Nonvolatile Timekeeping RAMs
Figure 1. Block Diagram
PACKAGES
The DS1746 is available in two packages (32-pin DIP and 34-pin PowerCap module). The 32-pin DIP
style module integrates the crystal, lithium energy source, and silicon all in one package. The 34-pin
PowerCap Module Board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1746P after the completion of the surface mount process. Mounting the PowerCap after the surface
mount process prevents damage to the crystal and battery due to the high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap
are ordered separately and shipped in separate containers. The part number for the PowerCap is
DS9034PCX.
CLOCK OPERATIONS—READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1746 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a one is written into the read bit, bit 6 of the century register (see Table 2). As
long as a one remains in that position, updating is halted. After a halt is issued, the registers reflect the
count, that is day, date, and time that was current at the moment the halt command was issued. However,
the internal clock registers of the double-buffered system continue to update so that the clock accuracy is
not affected by the access of data. All of the DS1746 registers are updated simultaneously after the
internal clock register updating process has been re-enabled. Updating is within a second after the read bit
is written to zero. The READ bit must be a zero for a minimum of 500s to ensure the external registers
will be updated.
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DS1746/DS1746P Y2K-Compliant, Nonvolatile Timekeeping RAMs
Table 1. Truth Table
CE
OE
WE
VCC
MODE
DQ
POWER
VIH
VIL
VIL
VIL
X
X
X
VIL
VIH
X
X
VIL
VIH
VIH
X
Deselect
Write
Read
Read
Deselect
Deselect
High-Z
Data In
Data Out
High-Z
High-Z
High-Z
Standby
Active
Active
VCC>VPF
Active
CMOS Standby
Data-Retention Mode
VSO<VCC<VPF
VCC<VSO<VPF
X
X
X
SETTING THE CLOCK
As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a one, like the
read bit, halts updates to the DS1746 registers. The user can then load them with the correct day, date and
time data in 24 hour BCD format. Resetting the write bit to a zero then transfers those values to the actual
clock counters and allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the seconds registers (see
Table 2). Setting it to a one stops the oscillator.
FREQUENCY TEST BIT
As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to
logic “1” and the oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the
seconds register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for
access remain valid (i.e., CE low, OE low, WE high, and address for seconds register remain valid and
stable).
CLOCK ACCURACY (DIP MODULE)
The DS1746 is guaranteed to keep time accuracy to within 1 minute per month at 25C. The RTC is
calibrated at the factory by Maxim using nonvolatile tuning elements, and does not require additional
calibration. For this reason, methods of field clock calibration are not available and not necessary. The
electrical environment also affects clock accuracy and caution should be taken to place the RTC in the
lowest-level EMI section of the PC board layout. For additional information, refer to Application Note
58.
CLOCK ACCURACY (PowerCap MODULE)
The DS1746 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module will typically keep time accuracy to within 1.53 minutes per month (35 ppm) at 25°C. The
electrical environment also affects clock accuracy and caution should be taken to place the RTC in the
lowest-level EMI section of the PC board layout. For additional information, refer to Application Note
58.
5 of 16
DS1746/DS1746P Y2K-Compliant, Nonvolatile Timekeeping RAMs
Table 2. Register Map
DATA
ADDRESS
FUNCTION RANGE
B7
B6
B5
B4
B3
B2
B1
B0
1FFFF
1FFFE
1FFFD
10 Year
Year
Month
Date
Year
Month
Date
00-99
01-12
01-31
X
X
X
X
X
10 Month
10 Date
1FFFC
1FFFB
1FFFA
1FFF9
BF
X
X
FT
X
X
X
X
Day
Day
Hour
Minutes
Seconds
01-07
00-23
00-59
00-59
10 Hour
Hour
10 Minutes
10 Seconds
Minutes
Seconds
Century
OSC
W
1FFF8
R
10 Century
Century
00-39
R = Read Bit
X = See Note
FT = Frequency Test
BF = Battery Flag
OSC = Stop Bit
W = Write Bit
Note: All indicated “X” bits are not used but must be set to “0” during a write cycle to ensure proper clock
operation.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1746 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE
(chip enable) is low. The device architecture allows ripple-through access to any of the address locations
in the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is
stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times and
states are not met, valid data will be available at the latter of chip enable access (tCEA
access time (tOEA . The state of the data input/output pins (DQ) is controlled by CE and OE. If the outputs
are activated before tAA, the data lines are driven to an intermediate state until tAA . If the address inputs
)
or at output enable
)
are changed while CE and OE remain valid, output data will remain valid for output data hold time (tOH
)
but will then go indeterminate until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1746 is in the write mode whenever WE, and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE, or CE. The addresses must be held valid throughout
the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or
write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDS afterward. In a
typical application, the OE signal will be high during a write cycle. However, OE can be active provided
that care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low the
data bus can become active with read data defined by the address inputs. A low transition on WE will
then disable the output tWEZ after WE goes active.
6 of 16
DS1746/DS1746P Y2K-Compliant, Nonvolatile Timekeeping RAMs
DATA-RETENTION MODE
The 5V device is fully accessible and data can be written or read only when VCC is greater than VPF
.
However, when VCC is below the power-fail point, VPF, (point at which write protection occurs) the
internal clock registers and SRAM are blocked from any access. At this time the power fail reset output
signal (RST) is driven active and will remain active until VCC returns to nominal levels. When VCC falls
below the battery switch point VSO (battery supply level), device power is switched from the VCC pin to
the backup battery. RTC operation and SRAM data are maintained from the battery until VCC is returned
to nominal levels. The 3.3V device is fully accessible and data can be written or read only when VCC is
greater than VPF. When VCC falls below the power fail point, VPF, access to the device is inhibited. At this
time the power fail reset output signal (RST) is driven active and will remain active until VCC returns to
nominal levels. If VPF is less than VSO, the device power is switched from VCC to the backup supply
(VBAT) when VCC drops below VPF
.
If VPF is greater than VSO
,
the device power is switched from VCC to
the backup supply (VBAT when VCC drops below VSO
)
.
RTC operation and SRAM data are maintained
from the battery until VCC is returned to nominal levels. The RST signal is an open drain output and
requires a pull up. Except for the RST, all control, data, and address signals must be powered down when
VCC is powered down.
BATTERY LONGEVITY
The DS1746 has a lithium power source that is designed to provide energy for clock activity, and clock
and RAM data retention when the VCC supply is not present. The capability of this internal power supply
is sufficient to power the DS1746 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at 25C with the internal clock oscillator running in
the absence of VCC power. Each DS1746 is shipped from Maxim with its lithium energy source
disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VPF, the
lithium energy source is enabled for battery backup operation. Actual life expectancy of the DS1746 will
be much longer than 10 years since no lithium battery energy is consumed when VCC is present.
BATTERY MONITOR
The DS1746 constantly monitors the battery voltage of the internal battery. The Battery Flag bit (bit 7) of
the day register is used to indicate the voltage level range of the battery. This bit is not writable and
should always be a one when read. If a zero is ever present, an exhausted lithium energy source is
indicated and both the contents of the RTC and RAM are questionable.
7 of 16
DS1746/DS1746P Y2K-Compliant, Nonvolatile Timekeeping RAMs
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground..………………………………..……………………..-0.3V to +6.0V
Storage Temperature Range
EDIP ...................................................……………………...………………..……………….-40°C to +85°C
PowerCap ................................................................................................................………...-55°C to +125°C
Lead Temperature (soldering, 10s)…........................................................................................……………….+260°C
Note: EDIP is hand or wave-soldered only.
Soldering Temperature (reflow, PowerCap)......................................................................................…………+260°C
This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operation sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
OPERATING RANGE
RANGE
Commercial
Industrial
TEMP RANGE
0°C to +70°C, Noncondensing
-40°C to +85°C, Noncondensing
VCC
3.3V 10% or 5V 10%
3.3V 10% or 5V 10%
RECOMMENDED DC OPERATING CONDITIONS
(TA = Over the Operating Range)
PARAMETER
Logic 1 Voltage All Inputs
VCC = 5V 10%
SYMBOL
MIN
TYP
MAX
VCC
0.3V
UNITS
NOTES
+
VIH
2.2
V
1
1
VCC
+
VCC = 3.3V 10%
VIH
2.0
V
0.3V
Logic 0 Voltage All Inputs
VCC = 5V 10%
VIL
VIL
-0.3
-0.3
0.8
0.6
V
V
1
1
VCC = 3.3V 10%
DC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V 10%, TA = Over the Operating Range.)
PARAMETER
Active Supply Current
TTL Standby Current
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Icc
85
mA
2, 3, 10
Icc1
Icc2
6
4
mA
mA
2, 3
2, 3
(CE = VIH)
CMOS Standby Current
(CE VCC-0.2V)
Input Leakage Current (any input)
IIL
-1
-1
+1
+1
A
A
Output Leakage Current
(any output)
IOL
Output Logic 1 Voltage
(IOUT = -1.0 mA)
Output Logic 0 Voltage
(IOUT = +2.1 mA)
VOH
VOL
VPF
VSO
2.4
1
1
0.4
Write Protection Voltage
4.25
4.50
V
1
Battery Switchover Voltage
VBAT
1, 4
8 of 16
DS1746/DS1746P Y2K-Compliant, Nonvolatile Timekeeping RAMs
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.3V 10%, TA = Over the Operating Range.)
PARAMETER
Active Supply Current
TTL Standby Current
SYMBOL
MIN
TYP
MAX
UNITS NOTES
Icc
30
mA
mA
mA
A
A
2, 3, 10
2, 3
Icc1
Icc2
IIL
2
2
(CE = VIH)
CMOS Standby Current
2, 3
(CE VCC-0.2V)
Input Leakage Current (any input)
-1
-1
+1
+1
Output Leakage Current
(any output)
IOL
Output Logic 1 Voltage
(IOUT = -1.0 mA)
VOH
VOL
VPF
VSO
2.4
1
1
Output Logic 0 Voltage
(IOUT = +2.1 mA)
0.4
Write Protection Voltage
2.80
2.97
V
V
1
VBAT
or
Battery Switchover Voltage
1, 4
VPF
AC CHARACTERISTICS—READ CYCLE (5V)
(VCC = 5.0V 10%, TA = Over the Operating Range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
Read Cycle Time
tRC
70
ns
Address Access Time
tAA
tCEL
tCEA
tCEZ
tOEL
tOEA
tOEZ
tOH
70
ns
ns
ns
ns
ns
ns
ns
ns
5
5
5
CE to DQ Low-Z
CE Access Time
70
25
CE Data Off Time
OE to DQ Low-Z
OE Access Time
35
25
OE Data Off Time
Output Hold from Address
9 of 16
DS1746/DS1746P Y2K-Compliant, Nonvolatile Timekeeping RAMs
AC CHARACTERISTICS—READ CYCLE (3.3V)
(VCC = 3.3V 10%, TA = Over the Operating Range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
Read Cycle Time
tRC
120
ns
Address Access Time
CE to DQ Low-Z
tAA
tCEL
tCEA
tCEZ
tOEL
tOEA
tOEZ
tOH
120
ns
ns
ns
ns
ns
ns
ns
ns
5
5
5
CE Access Time
120
40
CE Data Off Time
OE to DQ Low-Z
OE Access Time
100
35
OE Data Off Time
Output Hold from Address
READ CYCLE TIMING DIAGRAM
tRC
A0-A16
VALID
tAA
tOH
tCEZ
tCEA
CE
tCEL
tOEZ
tOEA
OE
tOEL
DQ0-DQ7
VALID
10 of 16
DS1746/DS1746P Y2K-Compliant, Nonvolatile Timekeeping RAMs
AC CHARACTERISTICS—WRITE CYCLE (5V)
(VCC = 5.0V 10%, TA = Over the Operating Range.)
PARAMETER
Write Cycle Time
SYMBOL
tWC
MIN
70
TYP
MAX
UNITS
NOTES
ns
ns
ns
ns
Address Setup Time
tAS
0
tWEW
tCEW
50
WE Pulse Width
CE Pulse Width
Data Setup Time
Data Hold Time
Data Hold Time
60
tDS
30
0
ns
ns
ns
ns
ns
ns
tDH1
tDH2
tWEZ
tWR1
tWR2
8
9
0
25
WE Data Off Time
Write Recovery Time
Write Recovery Time
5
5
8
9
AC CHARACTERISTICS—WRITE CYCLE (3.3V)
(VCC = 3.3V 10%, TA = Over the Operating Range.)
PARAMETER
Write Cycle Time
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
tWC
120
ns
Address Setup Time
tAS
tWEW
tCEW
tCEW
tDS
0
100
110
110
80
0
120
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WE Pulse Width
CE Pulse Width
CE and CE2 Pulse Width
Data Setup Time
Data Hold Time
tDH1
tDH2
tWEZ
tWR1
tWR2
8
9
Data Hold Time
0
40
WE Data Off Time
Write Recovery Time
Write Recovery Time
5
8
9
10
11 of 16
DS1746/DS1746P Y2K-Compliant, Nonvolatile Timekeeping RAMs
WRITE CYCLE TIMING DIAGRAM, WRITE-ENABLE CONTROLLED
tWC
A0-A16
VALID
CE
tAS
tWEW
tWR1
WE
tWEZ
tDS
tDH1
DQ0-DQ7
DATA OUTPUT
DATA INPUT
WRITE CYCLE TIMING DIAGRAM, CHIP-ENABLE CONTROLLED
tWC
A0-A16
VALID
tAS
tCEW
tWR2
CE
WE
tDS
tDH2
DQ0-DQ7
DATA INPUT
12 of 16
DS1746/DS1746P Y2K-Compliant, Nonvolatile Timekeeping RAMs
POWER-UP/DOWN AC CHARACTERISTICS—5V
(VCC = 5.0V 10%, TA = Over the Operating Range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS NOTES
CE or WE at VH
Before Power-Down
tPD
0
s
VCC Fall Time: VPF(MAX) to
VPF(MIN)
tF
tFB
tR
tREC
tDR
300
10
0
s
s
s
ms
VCC Fall Time: VPF(MIN) to VSO
VCC Rise Time: VPF(MIN) to
VPF(MAX)
Power-Up Recover Time
35
Expected Data-Retention Time
(Oscillator ON)
10
years
5, 6
POWER-UP/DOWN TIMING (5V DEVICE)
13 of 16
DS1746/DS1746P Y2K-Compliant, Nonvolatile Timekeeping RAMs
POWER-UP/DOWN CHARACTERISTICS—3.3V
(VCC = 3.3V 10%, TA = Over the Operating Range.)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
CE or WE at VH, Before
Power-Down
tPD
0
s
VCC Fall Time: VPF(MAX) to
VPF(MIN)
VCC Rise Time: VPF(MIN) to
VPF(MAX)
tF
300
0
s
tR
s
ms
tREC
tDR
35
VPF to RST High
Expected Data-Retention Time
(Oscillator ON)
10
years
5, 6
POWER-UP/DOWN WAVEFORM TIMING (3.3V DEVICE)
CAPACITANCE
(TA = +25°C)
PARAMETER
Capacitance on All Input Pins
Capacitance on All Output Pins
SYMBOL
CIN
MIN
TYP
MAX
14
10
UNITS
pF
NOTES
CO
pF
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DS1746/DS1746P Y2K-Compliant, Nonvolatile Timekeeping RAMs
AC TEST CONDITIONS
Output Load: 50pF + 1TTL Gate
Input Pulse Levels: 0 to 3.0V
Timing Measurement Reference Levels:
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5ns
NOTES:
1) Voltages are referenced to ground.
2) Typical values are at +25C and nominal supplies.
3) Outputs are open.
4) Battery switchover occurs at the lower of either the battery terminal voltage or VPF.
5) Data-retention time is at +25C.
6) Each DS1746 has a built-in switch that disconnects the lithium source until VCC is first applied by the
user. The expected tDR is defined for DIP modules and assembled PowerCap modules as a cumulative
time in the absence of VCC starting from the time power is first applied by the user.
7) RTC modules (DIP) can be successfully processed through conventional wave-soldering techniques
as long as temperatures as long as temperature exposure to the lithium energy source contained within
does not exceed +85C. Post-solder cleaning with water-washing techniques is acceptable, provided
that ultra-sonic vibration is not used.
In addition, for the PowerCap:
a) Maxim recommends that PowerCap module bases experience one pass through solder reflow
oriented with the label side up (“live-bug”).
b) Hand soldering and touch-up: Do not touch or apply the soldering iron to leads for more than
3 seconds. To solder, apply flux to the pad, heat the lead frame pad, and apply solder. To remove
the part, apply flux, heat the lead frame pad until the solder reflows, and use a solder wick to
remove solder.
8) tWR1, tDH1 are measured from WE going high.
9) tWR2, tDH2 are measured from CE going high.
10) tWC = 200ns.
PACKAGE INFORMATION
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-”
in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE TYPE
32 EDIP
PACKAGE CODE
MDF32+1
DOCUMENT NO.
21-0245
LAND PATTERN NO.
—
—
34 PWRCP
PC2+6
21-0246
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DS1746/DS1746P Y2K-Compliant, Nonvolatile Timekeeping RAMs
REVISION HISTORY
REVISION
PAGES
DESCRIPTION
CHANGED
DATE
Added UL recognition information and weblink to the Pin Description table;
corrected the top mark for –70 part numbers in the Ordering Information table;
updated the write timing diagrams to show tWR as specified by RAM vendors
080508
9/10
2, 3, 10, 12
3, 8, 9, 15
Updated the Ordering Information table top mark information; updated the Absolute
Maximum Ratings section to include the storage temperature range and lead and
soldering temperatures for EDIP and PowerCap packages; added Note 10 to the ICC
parameter in the DC Electrical Characteristics tables (for 5.0V and 3.3V) and the
Notes section; updated the Package Information table
16 of 16
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