STK16C88-W35I [CYPRESS]
32KX8 NON-VOLATILE SRAM, 35ns, PDIP28, 0.600 INCH, PLASTIC, DIP-28;
| 型号： | STK16C88-W35I |
| 厂家： | 
CYPRESS |
| 描述： | 32KX8 NON-VOLATILE SRAM, 35ns, PDIP28, 0.600 INCH, PLASTIC, DIP-28 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总10页 (文件大小：299K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STK16C88
32K x 8 AutoStorePlus™ nvSRAM
QuantumTrap™ CMOS
Nonvolatile Static RAM
DESCRIPTION
FEATURES
The STK16C88 is a fast SRAM with a nonvolatile
element incorporated in each static memory cell.
The SRAM can be read and written an unlimited
number of times, while independent nonvolatile data
resides in Nonvolatile Elements. Data transfers from
the SRAM to the Nonvolatile Elements (the STORE
operation) can take place automatically on power
down. An internal capacitor guarantees the STORE
operation regardless of power-down slew rate.
Transfers from the Nonvolatile Elements to the
SRAM (the RECALL operation) take place automati-
cally on restoration of power. Initiation of STORE and
RECALL cycles can also be controlled by entering
control sequences on the SRAM inputs. The
STK16C88 is pin-compatible with 32k x 8 SRAMs
and battery-backed SRAMs, allowing direct substitu-
tion while enhancing performance. The STK14C88,
which uses an external capacitor, and the
STK15C88, which uses charge stored in system
capacitance, are alternatives for systems needing
AutoStorePlus™ operation.
• Transparent Data Save on Power Down
• Internal Capacitor Guarantees AutoStore™
Regardless of Power-Down Slew Rate
• Directly Replaces 32K x 8 Static RAM, Battery-
Backed RAM or EEPROM
• 25ns, 35ns and 45ns Access Times
• STORE to Nonvolatile Elements Initiated by
Software or AutoStorePlus™
• No Data Loss from Undershoot
• RECALL to SRAM Initiated by Software or
Power Restore
• 10mA Typical ICC at 200ns Cycle Time
• Unlimited READ, WRITE and RECALL Cycles
• 1,000,000 STORE Cycles to Nonvolatile Ele-
ments (Commercial/Industrial)
• 100-Year Data Retention in nonvolatile ele-
ments (Commercial/Industrial)
• Single 5V + 10% Operation
• 28-Pin PDIP Package
BLOCK DIAGRAM
PIN CONFIGURATIONS
A14
A12
A7
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
W
QUANTUM TRAP
V
512 x 512
3
4
5
6
7
8
9
A13
A8
CC
A6
A5
A5
A9
A6
STORE
A4
A11
G
A10
E
STORE/
RECALL
A7
POWER
A3
A8
STATIC RAM
ARRAY
CONTROL
A2
CONTROL
RECALL
A9
A1
A0
10
11
12
13
14
DQ7
DQ6
DQ5
DQ4
DQ3
A11
A12
A13
A14
512 x 512
DQ0
DQ1
DQ2
VSS
28 - 600 PDIP
INTERNAL
CAPACITOR
DQ
DQ
DQ
PIN NAMES
0
1
2
COLUMN I/O
SOFTWARE
DETECT
A
- A
13
0
A
- A
Address Inputs
0
14
COLUMN DEC
W
Write Enable
Data In/Out
Chip Enable
Output Enable
Power (+ 5V)
Ground
DQ
3
4
DQ
DQ - DQ
0
7
DQ
DQ
DQ
5
6
7
A
A A A
A A
1 4
2 3
10
0
E
G
G
E
W
V
V
CC
SS
September 2003
1
Document Control # ML0018 rev 0.1
STK16C88
ABSOLUTE MAXIMUM RATINGSa
Note a: Stresses greater than those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at conditions
above those indicated in the operational sections of this specifica-
tion is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliability.
Voltage on Input Relative to Ground. . . . . . . . . . . . . .–0.5V to 7.0V
Voltage on Input Relative to VSS . . . . . . . . . . –0.6V to (VCC + 0.5V)
Voltage on DQ0-7. . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration). . . . . . . . 15mA
DC CHARACTERISTICS
(VCC = 5.0V ± 10%)
COMMERCIAL
INDUSTRIAL
SYMBOL
PARAMETER
UNITS
NOTES
MIN
MAX
MIN
MAX
b
I
Average V Current
97
80
70
100
85
70
mA
mA
mA
t
t
t
= 25ns
= 35ns
= 45ns
CC
CC
AVAV
AVAV
AVAV
1
c
I
I
Average V Current during STORE
3
3
mA
All Inputs Don’t Care, V = max
CC
CC
CC
CC
2
3
b
Average V
Current at t
AVAV
= 200ns
W ≥ (V
– 0.2V)
CC
5V, 25°C, Typical
CC
All Others Cycling, CMOS Levels
10
10
mA
d
I
Average V Current
30
25
22
31
26
23
mA
mA
mA
t
t
t
= 25ns, E ≥ V
= 35ns, E ≥ V
= 45ns, E ≥ V
SB
CC
AVAV
AVAV
AVAV
IH
IH
IH
1
(Standby, Cycling TTL Input Levels)
d
I
I
I
V
Standby Current
E ≥ (V
– 0.2V)
IN
SB
CC
CC
All Others V ≤ 0.2V or ≥ (V
2
1.5
±1
±5
1.5
±1
±5
mA
µA
µA
(Standby, Stable CMOS Input Levels)
– 0.2V)
CC
Input Leakage Current
V
V
= max
CC
IN
ILK
= V to V
SS
CC
Off-State Output Leakage Current
V
V
= max
CC
IN
OLK
= V to V , E or G ≥ V
SS CC
IH
V
V
V
V
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
2.2
V
+ .5
2.2
V
+ .5
V
V
All Inputs
All Inputs
IH
CC
0.8
CC
0.8
V
– .5
V
– .5
SS
IL
SS
2.4
2.4
V
I
I
=– 4mA
= 8mA
OH
OL
OUT
OUT
0.4
70
0.4
85
V
T
0
–40
°C
A
Note b: ICC and ICC are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: ICC1 and ICC3 are the average currents required for the duration of the respective STORE cycles (tSTORE ).
4
Note d: E ≥2VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1
5.0V
CAPACITANCEe
(TA = 25°C, f = 1.0MHz)
480 Ohms
SYMBOL
PARAMETER
MAX
UNITS
CONDITIONS
∆V = 0 to 3V
∆V = 0 to 3V
OUTPUT
C
Input Capacitance
5
7
pF
IN
30 pF
INCLUDING
SCOPE AND
FIXTURE
255 Ohms
C
Output Capacitance
pF
OUT
Note e: These parameters are guaranteed but not tested.
Figure 1: AC Output Loading
September 2003
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Document Control # ML0018 rev 0.1
STK16C88
SRAM READ CYCLES #1 & #2
(VCC = 5.0V ± 10%)
SYMBOLS
STK16C88-25 STK16C88-35 STK16C88-45
PARAMETER
UNITS
NO.
#1, #2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
25
35
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
ACS
f
Read Cycle Time
25
35
45
AVAV
RC
AA
g
3
Address Access Time
25
10
35
15
45
20
AVQV
4
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
GLQV
OE
OH
LZ
g
5
5
5
5
5
5
5
AXQX
6
ELQX
h
7
10
10
25
13
13
35
15
15
45
EHQZ
HZ
8
0
0
0
0
0
0
GLQX
OLZ
OHZ
PA
h
9
GHQZ
e
d
10
11
ELICCH
EHICCL
,
e
PS
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note g: I/O state assumes E, G < VIL and W > VIH; device is continuously selected.
Note h: Measured + 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledf, g
2
AVAV
t
ADDRESS
3
t
AVQV
5
t
AXQX
DATA VALID
DQ (DATA OUT)
SRAM READ CYCLE #2: E Controlledf
2
t
AVAV
ADDRESS
E
1
11
t
ELQV
t
6
EHICCL
t
ELQX
7
t
EHQZ
G
9
4
t
GHQZ
t
GLQV
8
t
GLQX
DATA VALID
DQ (DATA OUT)
10
t
ELICCH
ACTIVE
STANDBY
I
CC
September 2003
3
Document Control # ML0018 rev 0.1
STK16C88
SRAM WRITE CYCLES #1 & #2
(VCC = 5.0V ± 10%)
SYMBOLS
STK16C88-25
STK16C88-35
STK16C88-45
NO.
PARAMETER
UNITS
#1
#2
Alt.
MIN
25
20
20
10
0
MAX
MIN
35
25
25
12
0
MAX
MIN
45
30
30
15
0
MAX
12
13
14
15
16
17
18
19
20
21
t
t
t
WC
Write Cycle Time
Write Pulse Width
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVAV
t
t
t
WLWH
WLEH
WP
CW
DW
t
t
t
t
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
ELWH
DVWH
WHDX
ELEH
DVEH
EHDX
t
t
t
t
t
DH
t
t
t
20
0
25
0
30
0
AVWH
AVEH
AW
t
t
t
AVWL
AVEL
EHAX
AS
t
t
t
0
0
0
WHAX
WR
h, i
t
t
10
13
15
WLQZ
WZ
t
t
5
5
5
WHQX
OW
Note i: If W is low when E goes low, the outputs remain in the high-impedance state.
Note j: E or W must be ≥ VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlledj
12
t
AVAV
ADDRESS
19
14
t
WHAX
t
ELWH
E
17
t
AVWH
18
t
AVWL
13
W
t
WLWH
15
16
t
t
DVWH
WHDX
DATA IN
DATA VALID
20
t
WLQZ
21
t
WHQX
HIGH IMPEDANCE
DATA OUT
PREVIOUS DATA
SRAM WRITE CYCLE #2: E Controlledj
12
t
AVAV
ADDRESS
18
14
19
t
t
AVEL
ELEH
t
EHAX
E
17
t
AVEH
13
t
WLEH
W
15
16
t
DVEH
t
EHDX
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
September 2003
4
Document Control # ML0018 rev 0.1
STK16C88
AutoStorePlus™/POWER-UP RECALL
(VCC = 5.0V ± 10%)
SYMBOLS
STK16C88
NO.
PARAMETER
UNITS NOTES
Standard
RESTORE
MIN
MAX
22
23
24
25
t
Power-up RECALL Duration
550
µs
ns
V
k
t
Power-down AutoStore™ Slew Time to Ground
Low Voltage Trigger Level
500
4.0
e, g
stg
V
4.5
3.6
SWITCH
RESET
V
Low Voltage Reset Level
V
Note k: tRESTORE starts from the time VCC rises above VSWITCH
.
AutoStorePlus™/POWER-UP RECALL
VCC
5V
24
VSWITCH
25
VRESET
23
t
stg
AutoStore™
31
t
STORE
POWER-UP RECALL
22
t
RESTORE
W
DQ (DATA OUT)
BROWN OUT
AutoStorePlus™
BROWN OUT
AutoStorePlus™
POWER-UP
RECALL
BROWN OUT
NO STORE DUE TO
NO SRAM WRITES
NO RECALL
RECALL WHEN
NO RECALL
(VCC DID NOT GO
V
RETURNS
CC
(VCC DID NOT GO
BELOW VRESET
)
ABOVE VSWITCH
BELOW VRESET
)
September 2003
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Document Control # ML0018 rev 0.1
STK16C88
SOFTWARE STORE/RECALL MODE SELECTION
E
W
A
- A (hex)
MODE
I/O
NOTES
13
0
0E38
31C7
03E0
3C1F
303F
0FC0
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Read SRAM
L
H
l, m
Read SRAM
Read SRAM
Nonvolatile STORE
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Read SRAM
L
H
l, m
Read SRAM
Read SRAM
Nonvolatile RECALL
Note l: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
Note m: While there are 15 addresses on the STK16C88, only the lower 14 are used to control software modes.
SOFTWARE STORE/RECALL CYCLEn, o
(VCC = 5.0V ± 10%)
STK16C88-25
STK16C88-35
STK16C88-45
NO.
SYMBOLS
PARAMETER
UNITS
MIN
25
0
MAX
MIN
35
0
MAX
MIN
45
0
MAX
26
27
28
29
30
31
t
t
t
t
t
t
STORE/RECALL Initiation Cycle Time
Address Set-up Time
ns
ns
ns
ns
µs
ms
AVAV
AVEL
n
n
Clock Pulse Width
20
20
25
20
30
20
ELEH
ELAX
g, n
Address Hold Time
RECALL Cycle Duration
STORE Cycle Duration
20
10
20
10
20
10
RECALL
STORE
Note n: The software sequence is clocked with E controlled reads.
Note o: The six consecutive addresses must be in the order listed in the Software STORE/RECALL Mode Selection Table: (0E38, 31C7, 03E0, 3C1F,
303F, 0FC0) for a STORE cycle or (0E38, 31C7, 03E0, 3C1F, 303F, 0C63) for a RECALL cycle. W must be high during all six consecutive
cycles.
SOFTWARE STORE/RECALL CYCLE: E Controlledo
26
AVAV
26
AVAV
t
t
ADDRESS #1
ADDRESS #6
ADDRESS
27
AVEL
28
ELEH
t
t
E
29
ELAX
t
31
30
RECALL
t
STORE / t
HIGH IMPEDANCE
DATA VALID
DATA VALID
DQ (DATA
September 2003
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Document Control # ML0018 rev 0.1
STK16C88
DEVICE OPERATION
The AutoStorePlus™ STK16C88 is a fast 32K x 8
SRAM that does not lose its data on power-down.
The data is preserved in integral QuantumTrap™
Nonvolatile Elements while power is unavailable.
The nonvolatility of the STK16C88 does not require
any system intervention or support: AutoStore-
Plus™ on power-down and automatic RECALL on
power-up guarantee data integrity without the use of
batteries
AutoStorePlus™ OPERATION
The STK16C88’s automatic STORE on power-down
is completely transparent to the system. The
AutoStore™ initiation takes less than 500ns when
power is lost (VCC < VSWITCH) at which point the part
depends only on its internal capacitor for STORE
completion. If the power supply drops faster than 20
µs/volt before Vccx reaches Vswitch, then a 2.2 ohm
resistor should be inserted between Vccx and th
system supply to avoid a momentary excess of cur-
rent between Vccx and Vcap. In order to prevent
unneeded STORE operations, automatic STOREs will
be ignored unless at least one WRITE operation has
taken place since the most recent STORE or RECALL
cycle. Softwareinitiated STORE cycles are performed
regardless of whether or not a WRITE operation has
taken place.
NOISE CONSIDERATIONS
Note that the STK16C88 is a high-speed memory
and so must have a high-frequency bypass capaci-
tor of approximately 0.1µF connected between VCC
and VSS, using leads and traces that are as short as
possible. As with all high-speed CMOS ICs, normal
careful routing of power, ground and signals will help
prevent noise problems.
SRAM READ
POWER-UP RECALL
The STK16C88 performs a READ cycle whenever E
and G are low and W is high. The address specified
on pins A0-14 determines which of the 32,768 data
bytes will be accessed. When the READ is initiated
by an address transition, the outputs will be valid
after a delay of tAVQV (READ cycle #1). If the READ is
initiated by E or G, the outputs will be valid at tELQV or
at tGLQV, whichever is later (READ cycle #2). The data
outputs will repeatedly respond to address changes
within the tAVQV access time without the need for tran-
sitions on any control input pins, and will remain valid
until another address change or until E or G is
brought high.
During power up, or after any low-power condition
(VCC < VRESET), an internal RECALL request will be
latched. When VCC once again exceeds the sense
voltage of VSWITCH, a RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
If the STK16C88 is in a WRITE state at the end of
power-up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10kΩ resistor should
be connected either between W and system VCC or
between E and system VCC.
SOFTWARE NONVOLATILE STORE
The STK16C88 software STORE cycle is initiated by
executing sequential READ cycles from six specific
address locations. During the STORE cycle an erase
of the previous nonvolatile data is first performed,
followed by a program of the nonvolatile elements.
The program operation copies the SRAM data into
nonvolatile memory. Once a STORE cycle is initi-
ated, further input and output are disabled until the
cycle is completed.
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ0-7 will be writ-
ten into the memory if it is valid tDVWH before the end
of a W controlled WRITE or tDVEH before the end of an
E controlled WRITE.
Because a sequence of READs from specific
addresses is used for STORE initiation, it is impor-
tant that no other READ or WRITE accesses inter-
vene in the sequence or the sequence will be
aborted and no STORE or RECALL will take place.
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers tWLQZ after W goes low.
September 2003
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Document Control # ML0018 rev 0.1
STK16C88
Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the nonvola-
tile information is transferred into the SRAM cells.
After the tRECALL cycle time the SRAM will once again
be ready for READ and WRITE operations. The
RECALL operation in no way alters the data in the
Nonvolatile Elements. The nonvolatile data can be
recalled an unlimited number of times.
To initiate the software STORE cycle, the following
READ sequence must be performed:
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0FC0 (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE cycle
The software sequence must be clocked with E
controlled READs.
HARDWARE PROTECT
The STK16C88 offers hardware protection against
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ
cycles and not WRITE cycles be used in the
sequence, although it is not necessary that G be
low for the sequence to be valid. After the tSTORE
cycle time has been fulfilled, the SRAM will again be
activated for READ and WRITE operation.
inadvertent STORE operation and SRAM WRITEs
during low-voltage conditions. When VCC < VSWITCH
,
all software STORE operations and SRAM WRITEs
are inhibited.
LOW AVERAGE ACTIVE POWER
The STK16C88 draws significantly less current
when it is cycled at times longer than 50ns. Figure 2
shows the relationship between I and READ cycle
SOFTWARE NONVOLATILE RECALL
CC
time. Worst-case current consumption is shown for
both CMOS and TTL input levels (commercial tem-
A software RECALL cycle is initiated with a
sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the
RECALL cycle, the following sequence of READ
operations must be performed:
perature range, V =5.5V, 100% duty cycle on chip
CC
enable). Figure 3 shows the same relationship for
WRITE cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK16C88 depends on the following items:
1) CMOS vs. TTL input levels; 2) the duty cycle of
chip enable; 3) the overall cycle rate for accesses;
4) the ratio of READs to WRITEs; 5) the operating
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0C63 (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL cycle
temperature; 6) the V level; and 7) I/O loading.
CC
100
80
100
80
60
60
TTL
CMOS
40
40
20
TTL
20
CMOS
150 200
0
0
50
100
150
200
50
100
Cycle Time (ns)
Cycle Time (ns)
Figure 3: ICC (max) Writes
Figure 2: ICC (max) Reads
September 2003
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Document Control # ML0018 rev 0.1
STK16C88
ORDERING INFORMATION
- W F 45 I
STK16C88
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (–40 to 85°C)
Access Time
25 = 25ns
35 = 35ns
45 = 45ns
Lead Finish
Blank = 85%Sn/15%Pb
F = 100% Sn (Matte Tin)
Package
W = Plastic 28-pin 600 mil DIP
September 2003
9
Document Control # ML0018 rev 0.1
STK16C88
Document Revision History
Revision
0.0
Date
December 2002
September 2003
Summary
0.1
Added lead-free lead finish
September 2003
10
Document Control # ML0018 rev 0.1
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