STK16C88-W45I [SIMTEK]
32Kx8 AutoStore+ nvSRAM; 32Kx8自动存储+的nvSRAM
| 型号： | STK16C88-W45I |
| 厂家： | 
SIMTEK CORPORATION |
| 描述： | 32Kx8 AutoStore+ nvSRAM |
| 文件： | 总12页 (文件大小：381K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
STK16C88
32Kx8 AutoStore+ nvSRAM
FEATURES
• 25, 45 ns Read Access & R/W Cycle Time
DESCRIPTION
The Simtek STK16C88 is a 256Kb fast static RAM
with a non-volatile Quantum Trap storage element
included with each memory cell.
• Unlimited Read/Write Endurance
• Directly replaces battery-backed SRAM mod-
ules such as Dallas/Maxim DS1230 AB
The SRAM provides the fast access & cycle times,
ease of use and unlimited read & write endurance of
a normal SRAM.
• Automatic Non-volatile STORE on Power Loss
• Non-Volatile STORE Under Hardware or
Software Control
Data transfers automatically to the non-volatile stor-
age cells when power loss is detected (the STORE
operation). On power up, data is automatically
restored to the SRAM (the RECALL operation). Both
STORE and RECALL operations are also available
under software control.
• Automatic RECALL to SRAM on Power Up
• Unlimited RECALL Cycles
• 1 Million STORE Cycles
• 100-Year Non-volatile Data Retention
• Single 5V ± 10% Power Supply
The Simtek nvSRAM is the first monolithic non-vola-
tile memory to offer unlimited writes and reads. It is
the highest performance, most reliable non-volatile
memory available.
• Commercial and Industrial Temperatures
• 28-pin 600-mil PDIP Package (RoHS-Compliant)
BLOCK DIAGRAM
QUANTUM TRAP
512 x 512
STORE/
RECALL
CONTROL
A5
A6
A7
A8
STORE
RECALL
STATIC RAM
ARRAY
512 X 512
A9
A11
A12
A13
A14
SOFTWARE
DETECT
A13 – A0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A10
G
E
W
This product conforms to specifications per the
terms of Simtek standard warranty. The product
has completed Simtek internal qualification testing
and has reached production status.
Rev 0.3
Document Control #ML0018
February, 2007
1
STK16C88
PIN CONFIGURATIONS
A14
1
28
27
26
25
24
23
22
21
20
19
18
VCC
2
A12
W
3
A13
A8
A7
4
A6
5
A9
A5
A11
6
A4
7
G
A3
8
A10
E
A2
A1
9
10
DQ7
DQ6
DQ5
DQ4
DQ3
A0
DQ0
11
12
DQ1
DQ2
VSS
17
16
15
13
14
28 Pin 600 mil PDIP
PIN CONFIGURATIONS
Pin Name
-A
I/O
Description
A
Input
I/O
Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array
Data: Bi-directional 8-bit data bus for accessing the nvSRAM
Chip Enable: The active low E input selects the device
14
0
DQ -DQ
7
0
E
Input
Input
W
Write Enable: The active low W enables data on the DQ pins to be written to the address
location latched by the falling edge of E
G
Input
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
V
V
Power Supply
Power Supply
Power: 5.0V, ±10%
Ground
CC
SS
Rev 0.3
Document Control #ML0018
February, 2007
2
STK16C88
a
ABSOLUTE MAXIMUM RATINGS
Note a: Stresses greater than those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at conditions
above those indicated in the operational sections of this specifica-
tion is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect reliability.
Voltage on Input Relative to Ground. . . . . . . . . . . . . .–0.5V to 7.0V
Voltage on Input Relative to VSS . . . . . . . . . . –0.6V to (VCC + 0.5V)
Voltage on DQ0-7. . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V)
Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W
DC Output Current (1 output at a time, 1s duration). . . . . . . . 15mA
DC CHARACTERISTICS
(V = 5.0V 10%)
CC
COMMERCIAL
INDUSTRIAL
SYMBOL
PARAMETER
Average V Current
UNITS
NOTES
MIN
MAX
MIN
MAX
b
I
97
70
100
70
mA
mA
t
t
= 25ns
= 45ns
CC
CC
AVAV
AVAV
1
c
I
I
Average V Current during STORE
3
3
mA
mA
All Inputs Don’t Care, V = max
CC
CC
CC
CC
2
3
b
Average V
Current at t
= 200ns
W ≥ (V
– 0.2V)
CC
5V, 25°C, Typical
AVAV
CC
All Others Cycling, CMOS Levels
10
10
d
d
I
I
I
I
Average V Current
(Standby, Cycling TTL Input Levels)
30
22
31
23
mA
mA
t
t
= 25ns, E ≥ V
= 45ns, E ≥ V
SB
SB
CC
AVAV
AVAV
IH
IH
1
2
V
Standby Current
E ≥ (V
– 0.2V)
CC
CC
All Others V ≤ 0.2V or ≥ (V
1.5
1
1.5
1
mA
μA
μA
(Standby, Stable CMOS Input Levels)
– 0.2V)
CC
IN
Input Leakage Current
V
V
= max
CC
ILK
= V to V
IN
SS CC
Off-State Output Leakage Current
V
V
= max
CC
OLK
5
5
= V to V , E or G ≥ V
IN
SS CC
IH
V
V
V
V
T
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
Output Logic “0” Voltage
Operating Temperature
2.2
V
+ .5
2.2
V
+ .5
V
V
All Inputs
All Inputs
IH
CC
CC
V
– .5
0.8
V
– .5
0.8
IL
SS
SS
2.4
2.4
V
I
I
=–4mA
= 8mA
OH
OL
OUT
OUT
0.4
70
0.4
85
V
0
–40
°C
A
Note b: ICC and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded.
Note c: ICC1 and ICC are the average currents required for the duration of the respective STORE cycles (tSTORE ).
4
Note d: E ≥2VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out.
AC TEST CONDITIONS
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns
Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1
e
5.0V
CAPACITANCE
(TA = 25°C, f = 1.0MHz)
SYMBOL
PARAMETER
MAX
UNITS
CONDITIONS
ΔV = 0 to 3V
ΔV = 0 to 3V
480 Ohms
C
Input Capacitance
Output Capacitance
5
7
pF
IN
C
pF
OUT
OUTPUT
30 pF
Note e: These parameters are guaranteed but not tested.
INCLUDING
SCOPE AND
FIXTURE
255 Ohms
Figure 1: AC Output Loading
Rev 0.3
Document Control #ML0018
February, 2007
3
STK16C88
SRAM READ CYCLES #1 & #2
(V = 5.0V 10%)
CC
SYMBOLS
STK16C88-25 STK16C88-45
UNITS
PARAMETER
NO.
#1, #2
Alt.
MIN
MAX
MIN
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
Read Cycle Time
25
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
ACS
f
25
45
AVAV
RC
AA
g
3
Address Access Time
Output Enable to Data Valid
25
10
45
20
AVQV
4
GLQV
AXQX
ELQX
EHQZ
GLQX
OE
OH
LZ
g
h
h
5
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
5
5
5
5
6
7
10
10
25
15
15
45
HZ
8
0
0
0
0
OLZ
OHZ
PA
9
GHQZ
e
d
10
11
ELICCH
EHICCL
,
e
PS
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note g: I/O state assumes E, G < VIL and W > VIH; device is continuously selected.
Note h: Measured + 200mV from steady state output voltage.
f, g
SRAM READ CYCLE #1: Address Controlled
2
AVAV
t
ADDRESS
3
t
AVQV
5
t
AXQX
DATA VALID
DQ (DATA OUT)
f
SRAM READ CYCLE #2: E Controlled
2
AVAV
t
ADDRESS
E
1
ELQV
11
EHICCL
t
t
6
ELQX
t
7
EHQZ
t
G
9
4
GLQV
t
GHQZ
t
8
t
GLQX
DATA VALID
DQ (DATA OUT)
10
ELICCH
t
ACTIVE
STANDBY
I
CC
Rev 0.3
Document Control #ML0018
February, 2007
4
STK16C88
SRAM WRITE CYCLES #1 & #2
(V = 5.0V 10%)
CC
SYMBOLS
NO.
STK16C88-25
STK16C88-45
PARAMETER
UNITS
#1
#2
Alt.
MIN
25
20
20
10
0
MAX
MIN
45
30
30
15
0
MAX
12
13
14
15
16
17
18
19
20
21
t
t
t
WC
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVAV
t
t
t
Write Pulse Width
WLWH
WLEH
WP
CW
DW
t
t
t
t
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
ELWH
DVWH
WHDX
ELEH
DVEH
EHDX
t
t
t
t
t
DH
t
t
t
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
20
0
30
0
AVWH
AVEH
AW
t
t
t
AS
AVWL
AVEL
t
t
t
0
0
WHAX
EHAX
WR
h, i
t
t
10
15
WLQZ
WZ
t
t
5
5
WHQX
OW
Note i: If W is low when E goes low, the outputs remain in the high-impedance state.
Note j: E or W must be ≥ VIH during address transitions.
j
SRAM WRITE CYCLE #1: W Controlled
12
AVAV
t
ADDRESS
19
WHAX
14
ELWH
t
t
E
17
AVWH
t
18
AVWL
t
13
WLWH
W
t
15
DVWH
16
WHDX
t
t
DATA IN
DATA VALID
20
WLQZ
t
21
WHQX
t
HIGH IMPEDANCE
DATA OUT
PREVIOUS DATA
SRAM WRITE CYCLE #2: E Controlledj
12
AVAV
t
ADDRESS
14
ELEH
18
AVEL
19
EHAX
t
t
t
E
17
AVEH
t
13
WLEH
t
W
15
DVEH
16
EHDX
t
t
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
Rev 0.3
Document Control #ML0018
February, 2007
5
STK16C88
AutoStorePluse/POWER-UP RECALL
(V = 5.0V 10%)
CC
SYMBOLS
STK16C88
NO.
PARAMETER
UNITS NOTES
Standard
MIN
MAX
22
23
24
25
t
t
Power-up RECALL Duration
550
μs
ns
k
RESTORE
Power-down AutoStore™ Slew Time to Ground
Low Voltage Trigger Level
500
4.0
e, g
stg
V
V
4.5
3.6
V
V
SWITCH
Low Voltage Reset Level
RESET
Note k: tRESTORE starts from the time VCC rises above VSWITCH
.
AutoStorePluse/POWER-UP RECALL
V
CC
5V
24
V
SWITCH
25
RESET
V
23
t
stg
AutoStore™
31
STORE
t
POWER-UP RECALL
22
RESTORE
t
W
DQ (DATA OUT)
BROWN OUT
BROWN OUT
POWER-UP
BROWN OUT
AutoStorePluse
AutoStorePluse
RECALL
NO STORE DUE TO
NO SRAM WRITES
NO RECALL
RECALL WHEN
NO RECALL
(VCC DID NOT GO
V
RETURNS
CC
(VCC DID NOT GO
BELOW VRESET
)
ABOVE VSWITCH
BELOW VRESET
)
Rev 0.3
Document Control #ML0018
February, 2007
6
STK16C88
SOFTWARE STORE/RECALL MODE SELECTION
E
W
A
- A (hex)
MODE
I/O
NOTES
13
0
0E38
31C7
03E0
3C1F
303F
0FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
L
H
l, m
Nonvolatile STORE
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
L
H
l, m
Nonvolatile RECALL
Note l: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
Note m: While there are 15 addresses on the STK16C88, only the lower 14 are used to control software modes.
n, o
SOFTWARE STORE/RECALL CYCLE
(V = 5.0V 10%)
CC
STK16C88-25
STK16C88-45
NO.
SYMBOLS
PARAMETER
UNITS
MIN
25
0
MAX
MIN
45
0
MAX
26
27
28
29
30
31
t
t
t
t
t
t
STORE/RECALL Initiation Cycle Time
ns
ns
ns
ns
μs
ms
AVAV
n
Address Set-up Time
Clock Pulse Width
AVEL
n
20
20
30
20
ELEH
ELAX
g, n
Address Hold Time
RECALL Cycle Duration
STORE Cycle Duration
20
10
20
10
RECALL
STORE
Note n: The software sequence is clocked with E controlled reads.
Note o: The six consecutive addresses must be in the order listed in the Software STORE/RECALL Mode Selection Table: (0E38, 31C7, 03E0, 3C1F,
303F, 0FC0) for a STORE cycle or (0E38, 31C7, 03E0, 3C1F, 303F, 0C63) for a RECALL cycle. W must be high during all six consecutive
cycles.
o
SOFTWARE STORE/RECALL CYCLE: E Controlled
26
AVAV
26
t
AVAV
t
ADDRESS #1
ADDRESS #6
ADDRESS
27
AVEL
28
t
ELEH
t
E
29
ELAX
t
31
30
RECALL
t
STORE / t
HIGH IMPEDANCE
DATA VALID
DATA VALID
DQ (DATA
Rev 0.3
Document Control #ML0018
February, 2007
7
STK16C88
nvSRAM OPERATION
The AutoStore+ STK16C88 is a fast 32K x 8 SRAM
AutoStore+ OPERATION
that does not lose its data on power-down. The data
is preserved in integral QuantumTrap non-volatile
storage elements when power is lost. Automatic
STORE on power-down and automatic RECALL on
power-up guarantee data integrity without the use of
batteries.
The STK16C88’s automatic STORE on power-down
is completely transparent to the system. The
STORE initiation takes less than 500ns when power
is lost (VCC < VSWITCH) at which point the part depends
only on its internal capacitor for STORE completion.
If the power supply drops faster than 20 μs/volt
before Vcc reaches Vswitch, then a 2.2 ohm resistor
should be inserted between Vcc and th system sup-
ply to avoid a momentary excess of current between
Vcc and internal capacitor.
NOISE CONSIDERATIONS
Note that the STK16C88 is a high-speed memory
and so must have a high-frequency bypass capaci-
tor of approximately 0.1μF connected between VCC
and VSS, using leads and traces that are as short as
possible. As with all high-speed CMOS ICs, normal
careful routing of power, ground and signals will help
prevent noise problems.
In order to prevent unneeded STORE operations,
automatic STOREs will be ignored unless at least
one WRITE operation has taken place since the
most recent STORE or RECALL cycle. Software
initiated STORE cycles are performed regardless of
whether or not a WRITE operation has taken place.
SRAM READ
The STK16C88 performs a READ cycle whenever E
and G are low and W is high. The address specified
on pins A0-14 determines which of the 32,768 data
bytes will be accessed. When the READ is initiated
by an address transition, the outputs will be valid
after a delay of tAVQV (READ cycle #1). If the READ is
initiated by E or G, the outputs will be valid at tELQV or
at tGLQV, whichever is later (READ cycle #2). The data
outputs will repeatedly respond to address changes
within the tAVQV access time without the need for tran-
sitions on any control input pins, and will remain valid
until another address change or until E or G is
brought high.
POWER-UP RECALL
During power up, or after any low-power condition
(VCC < VRESET), an internal RECALL request will be
latched. When VCC once again exceeds the sense
voltage of VSWITCH, a RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
If the STK16C88 is in a WRITE state at the end of
power-up RECALL, the SRAM data will be cor-
rupted. To help avoid this situation, a 10kΩ resistor
should be connected either between W and system
VCC or between E and system VCC.
SOFTWARE NONVOLATILE STORE
SRAM WRITE
The STK16C88 software STORE cycle is initiated
by executing sequential READ cycles from six spe-
cific address locations. During the STORE cycle,
previous non-volatile data is erased and then the
SRAM contents are written to the non-volatile stor-
age elements. Once a STORE cycle is initiated, fur-
ther inputs and outputs are disabled until the cycle is
completed.
A WRITE cycle is performed whenever E and W are
low. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable
until either E or W goes high at the end of the cycle.
The data on the common I/O pins DQ0-7 will be writ-
ten into the memory if it is valid tDVWH before the end
of a W controlled WRITE or tDVEH before the end of an
E controlled WRITE.
Because a sequence of READs from specific
addresses is used for STORE initiation, it is impor-
tant that no other READ or WRITE accesses inter-
vene in the sequence or the sequence will be
aborted and no STORE or RECALL will take place.
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
the common I/O lines. If G is left low, internal circuitry
will turn off the output buffers tWLQZ after W goes low.
To initiate the software STORE cycle, the following
READ sequence must be performed:
Rev 0.3
Document Control #ML0018
February, 2007
8
STK16C88
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0FC0 (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE cycle
RECALL operation in no way alters the data in the
non-volatile storage elements. The nonvolatile data
can be recalled an unlimited number of times.
HARDWARE PROTECT
The STK16C88 offers hardware protection against
inadvertent STORE operation and SRAM WRITEs
The software sequence must be clocked with E
controlled READs.
during low-voltage conditions. When VCC < VSWITCH
,
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ
cycles and not WRITE cycles be used in the
sequence, although it is not necessary that G be
low for the sequence to be valid. After the tSTORE
cycle time has been fulfilled, the SRAM will again be
activated for READ and WRITE operation.
all software STORE operations and SRAM WRITEs
are inhibited.
LOW AVERAGE ACTIVE POWER
The STK16C88 draws significantly less current
when it is cycled at times longer than 50ns. Figure 2
shows the relationship between I and READ cycle
CC
time. Worst-case current consumption is shown for
both CMOS and TTL input levels (commercial tem-
SOFTWARE NONVOLATILE RECALL
perature range, V =5.5V, 100% duty cycle on chip
CC
A software RECALL cycle is initiated with a
sequence of READ operations in a manner similar to
the software STORE initiation. To initiate the RECALL
cycle, the following sequence of READ operations
must be performed:
enable). Figure 3 shows the same relationship for
WRITE cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK16C88 depends on the following items:
1) CMOS vs. TTL input levels; 2) the duty cycle of
chip enable; 3) the overall cycle rate for accesses;
4) the ratio of READs to WRITEs; 5) the operating
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
0E38 (hex)
31C7 (hex)
03E0 (hex)
3C1F (hex)
303F (hex)
0C63 (hex)
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate RECALL cycle
temperature; 6) the V level; and 7) I/O loading.
CC
Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the nonvola-
tile information is transferred into the SRAM cells.
After the tRECALL cycle time the SRAM will once again
be ready for READ and WRITE operations. The
100
80
100
80
60
60
TTL
CMOS
40
40
TTL
20
20
CMOS
150 200
0
0
50
100
150
200
50
100
Cycle Time (ns)
Cycle Time (ns)
Figure 3: ICC (max) Writes
Figure 2: ICC (max) Reads
Rev 0.3
Document Control #ML0018
February, 2007
9
STK16C88
ORDERING INFORMATION
STK16C88 - W F 45 I
Temperature Range
Blank = Commercial (0 to 70°C)
I = Industrial (–40 to 85°C)
Access Time
25 = 25ns
45 = 45ns
Lead Finish
F = 100% Sn (Matte Tin)
Package
W = Plastic 28-pin 600 mil DIP
ORDERING CODES
Part Number
Description
Temperature
Commercial
Commercial
Industrial
STK16C88-WF25
STK16C88-WF45
STK16C88-WF25I
STK16C88-WF45I
5V 32Kx8 AutoStore+ nvSRAM PDIP28-600
5V 32Kx8 AutoStore+ nvSRAM PDIP28-600
5V 32Kx8 AutoStore+ nvSRAM PDIP28-600
5V 32Kx8 AutoStore+ nvSRAM PDIP28-600
Industrial
Rev 0.3
Document Control #ML0018
February, 2007
10
STK16C88
PACKAGE DRAWING
28 Pin 600 mil PDIP
0.530 13.46
0.550 13.97
(
)
Pin 1
Index
Darla
0.040 1.02
0.050(1.27 )
1.440 36.58
1.460 (37.08)
---- ----
(4.57) .180
0.015 (0.38)
----
----
0.125 (3.18)
MIN
0.10
(2.54)
BSC
0.36
0.014
0.022
0.045 1.14
( )
)
(
0.56
0.060 1.52
15.11
15.88
0.595
0.625
(
)
MIN
MAX
DIM = INCHES
MIN
MAX
)
DIM = mm
(
0o
15o
0.20
0.38
0.008
0.015
(
)
0.600
0.660
15.24
16.76
)
(
Rev 0.3
Document Control #ML0018
February, 2007
11
STK16C88
Document Revision History
Revision
0.0
Date
December 2002
September 2003
March 2006
Summary
0.1
Added lead-free lead finish
0.2
Removed 35ns speed Grade, Removed Leaded lead finish
0.3
February 2007
Add fast power-down slew rate information
Add Product Ordering Code Listing
Add Package Drawings
Reformat Entire Document
SIMTEK STK16C88 Datasheet, February 2007
Copyright 2007, Simtek Corporation. All rights reserved.
This datasheet may only be printed for the expressed use of Simtek Customers. No part of the datasheet may be reproduced in any other
form or means without the express written permission from Simtek Corporation. The information contained in this publication is believed to be
accurate, but changes may be made without notice. Simtek does not assume responsibility for, or grant or imply any warranty, including
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE regarding this information, the product or its use. Nothing herein consti-
tutes a license, grant or transfer of any rights to any Simtek patent, copyright, trademark, or other proprietary right.
Rev 0.3
Document Control #ML0018
February, 2007
12
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