S34ML02G2 [CYPRESS]
1 Gb, 2 Gb, 4 Gb, 3 V, 4-bit ECC, SLC NAND Flash Memory for Embedded;
| 型号： | S34ML02G2 |
| 厂家： | 
CYPRESS |
| 描述： | 1 Gb, 2 Gb, 4 Gb, 3 V, 4-bit ECC, SLC NAND Flash Memory for Embedded |
| 文件： | 总76页 (文件大小：7372K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
S34ML01G2
S34ML02G2
S34ML04G2
1 Gb, 2 Gb, 4 Gb, 3 V, 4-bit ECC, SLC
NAND Flash Memory for Embedded
Distinctive Characteristics
Density
– Device Size
– 1 Gb: 1 plane per device or 128 Mbyte
– 2 Gb: 2 planes per device or 256 Mbyte
– 4 Gb: 2 planes per device or 512 Mbyte
– 1 Gb / 2 Gb / 4 Gb
Architecture
– Input / Output Bus Width: 8 bits / 16 bits
– Page size:
NAND Flash interface
– Open NAND Flash Interface (ONFI) 1.0 compliant
– Address, Data, and Commands multiplexed
– ×8:
1 Gb: (2048 + 64) bytes; 64-byte spare area
2 Gb / 4 Gb: (2048 + 128) bytes; 128-byte spare area
– ×16:
Supply Voltage
– 3.3-V device: V = 2.7 V ~ 3.6 V
CC
1 Gb: (1024 + 32) words; 32-word spare area
2 Gb / 4 Gb (1024 + 64) words; 64-word spare area
– Block size: 64 Pages
Security
– One Time Programmable (OTP) area
– Serial number (unique ID) (Contact factory for support)
– Hardware program/erase disabled during power transition
– ×8:
1 Gb: 128 KB+ 4 KB
Additional features
2 Gb / 4 Gb: 128 KB + 8 KB
– ×16
1 Gb: 64k + 2k words
– 2 Gb and 4 Gb parts support Multiplane Program and Erase
commands
2 Gb / 4 Gb: 64k + 4k words
– Plane size
– Supports Copy Back Program
– 2 Gb and 4 Gb parts support Multiplane Copy Back Program
– Supports Read Cache
– ×8
1 Gb: 1024 blocks per plane or (128 MB + 4 MB
2 Gb: 1024 blocks per plane or (128 MB + 8 MB
4 Gb: 2048 blocks per plane or (256 MB + 16 MB
– ×16
1 Gb: 1024 blocks per plane or (64M + 2M) words
2 Gb: 1024 Blocks per Plane or (64M + 4M) words
4 Gb: 2048 Blocks per Plane or (128M + 8M) words
Electronic signature
– Manufacturer ID: 01h
Operating temperature
– Industrial: –40 °C to 85 °C
– Industrial Plus: –40 °C to 105 °C
Performance
Page Read / Program
Reliability
– Random access: 25 µs (Max) (S34ML01G2)
– Random access: 30 µs (Max) (S34ML02G2, S34ML04G2)
– Sequential access: 25 ns (Min)
– 100,000 Program / Erase cycles (Typ)
(with 4-bit ECC per 528 bytes (×8) or 264 words (×16))
– 10 Year Data retention (Typ)
– For one plane structure (1-Gb density)
– Program time / Multiplane Program time: 300 µs (Typ)
– Block zero is valid and will be valid for at least 1,000 program-
erase cycles with ECC
Block Erase (S34ML01G2)
– Block Erase time: 3 ms (Typ)
– For two plane structures (2-Gb and 4-Gb densities)
– Blocks zero and one are valid and will be valid for at least 1,000
program-erase cycles with ECC
Block Erase / Multiplane Erase (S34ML02G2, S34ML04G2)
– Block Erase time: 3.5 ms (Typ)
Package options
– Pb-free and low halogen
– 48-Pin TSOP 12 × 20 × 1.2 mm
– 63-Ball BGA 9 × 11 × 1 mm
– 67-Ball BGA 8 × 6.5 × 1 mm (S34ML01G2, S34ML02G2)
Cypress Semiconductor Corporation
Document Number: 002-00499 Rev. *N
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 30, 2016
S34ML01G2
S34ML02G2
S34ML04G2
Contents
Distinctive Characteristics .................................................. 1
5.6 DC Characteristics........................................................ 37
5.7 Pin Capacitance............................................................ 37
5.8 Program / Erase Characteristics................................... 38
Performance.......................................................................... 1
1.
General Description..................................................... 3
6.
Timing Diagrams......................................................... 39
1.1 Logic Diagram................................................................ 4
1.2 Connection Diagram ...................................................... 5
1.3 Pin Description............................................................... 7
1.4 Block Diagram................................................................ 8
1.5 Array Organization......................................................... 9
1.6 Addressing................................................................... 11
1.7 Mode Selection ............................................................ 14
6.1 Command Latch Cycle.................................................. 39
6.2 Address Latch Cycle..................................................... 40
6.3 Data Input Cycle Timing................................................ 40
6.4 Data Output Cycle Timing (CLE=L, WE#=H, ALE=L,
WP#=H) ........................................................................ 41
6.5 Data Output Cycle Timing (EDO Type, CLE=L, WE#=H,
ALE=L).......................................................................... 42
6.6 Page Read Operation................................................... 42
6.7 Page Read Operation (Interrupted by CE#).................. 43
6.8 Page Read Operation Timing with CE# Don’t Care...... 44
6.9 Page Program Operation.............................................. 44
6.10 Page Program Operation Timing with CE# Don’t Care. 45
6.11 Page Program Operation with Random Data Input ...... 45
6.12 Random Data Output In a Page ................................... 46
6.13 Multiplane Page Program Operation — S34ML02G2 and
S34ML04G2.................................................................. 46
6.14 Block Erase Operation.................................................. 47
6.15 Multiplane Block Erase — S34ML02G2 and S34ML04G2
48
2.
Bus Operation ............................................................ 14
2.1 Command Input ........................................................... 14
2.2 Address Input............................................................... 14
2.3 Data Input .................................................................... 15
2.4 Data Output.................................................................. 15
2.5 Write Protect ................................................................ 15
2.6 Standby........................................................................ 15
3.
Command Set............................................................. 16
3.1 Page Read................................................................... 17
3.2 Page Program.............................................................. 17
3.3 Multiplane Program — S34ML02G2 and S34ML04G2 18
3.4 Page Reprogram.......................................................... 18
3.5 Block Erase.................................................................. 20
3.6 Multiplane Block Erase — S34ML02G2 and
S34ML04G2................................................................. 20
3.7 Copy Back Program..................................................... 21
3.8 Read Status Register................................................... 22
3.9 Read Status Enhanced — S34ML02G2 and
S34ML04G2................................................................. 22
3.10 Read Status Register Field Definition.......................... 22
3.11 Reset............................................................................ 23
3.12 Read Cache................................................................. 23
3.13 Cache Program............................................................ 24
3.14 Multiplane Cache Program — S34ML02G2 and
S34ML04G2................................................................. 25
3.15 Read ID........................................................................ 25
3.16 Read ID2...................................................................... 28
3.17 Read ONFI Signature .................................................. 28
3.18 Read Parameter Page ................................................. 29
3.19 Read Unique ID (Contact Factory)............................... 31
3.20 One-Time Programmable (OTP) Entry ........................ 32
6.16 Copy Back Read with Optional Data Readout.............. 49
6.17 Copy Back Program Operation With Random
Data Input ..................................................................... 49
6.18 Multiplane Copy Back Program — S34ML02G2 and
S34ML04G2.................................................................. 50
6.19 Read Status Register Timing........................................ 51
6.20 Read Status Enhanced Timing ..................................... 52
6.21 Reset Operation Timing................................................ 52
6.22 Read Cache.................................................................. 53
6.23 Cache Program............................................................. 55
6.24 Multiplane Cache Program — S34ML02G2 and
S34ML04G2.................................................................. 56
6.25 Read ID Operation Timing............................................ 58
6.26 Read ID2 Operation Timing.......................................... 58
6.27 Read ONFI Signature Timing........................................ 59
6.28 Read Parameter Page Timing ...................................... 59
6.29 Read Unique ID Timing (Contact Factory).................... 60
6.30 OTP Entry Timing ......................................................... 60
6.31 Power On and Data Protection Timing ......................... 61
6.32 WP# Handling............................................................... 61
4.
Signal Descriptions ................................................... 32
7.
Physical Interface ....................................................... 62
4.1 Data Protection and Power On / Off Sequence ........... 32
4.2 Ready/Busy.................................................................. 33
4.3 Write Protect Operation ............................................... 34
7.1 Physical Diagram.......................................................... 62
8.
9.
System Interface......................................................... 65
Error Management...................................................... 67
5.
Electrical Characteristics.......................................... 35
9.1 System Bad Block Replacement................................... 67
9.2 Bad Block Management................................................ 68
5.1 Valid Blocks ................................................................. 35
5.2 Absolute Maximum Ratings ......................................... 35
5.3 Recommended Operating Conditions.......................... 35
5.4 AC Test Conditions...................................................... 35
5.5 AC Characteristics ....................................................... 36
10. Ordering Information.................................................. 69
11. Document History....................................................... 70
Document Number: 002-00499 Rev. *N
Page 2 of 76
S34ML01G2
S34ML02G2
S34ML04G2
1. General Description
The S34ML01G2, S34ML02G2, and S34ML04G2 series is offered with a 3.3V VCC power supply, and with x8 or x16 I/O interface.
Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into blocks
that can be erased independently so it is possible to preserve valid data while old data is erased. The page size for x8 is (2048 +
spare) bytes; for x16 (1024 + spare) words.
To extend the lifetime of NAND flash devices, the implementation of an ECC is mandatory.
The chip supports CE# don't care function. This function allows the direct download of the code from the NAND flash memory device
by a microcontroller, since the CE# transitions do not stop the read operation.
The devices have a Read Cache feature that improves the read throughput for large files. During cache reading, the devices load
the data in a cache register while the previous data is transferred to the I/O buffers to be read.
Like all other 2-kB page NAND flash devices, a program operation typically writes 2 KB (×8) or 1 kword (×16) in 300 µs and an erase
operation can typically be performed in 3 ms (S34ML01G2) on a 128-kB block (×8) or 64k-word block (×16). In addition, thanks to
multiplane architecture, it is possible to program two pages at a time (one per plane) or to erase two blocks at a time (again, one per
plane). The multiplane architecture allows program time to be reduced by 40% and erase time to be reduced by 50%.
In multiplane operations, data in the page can be read out at 25 ns cycle time per byte. The I/O pins serve as the ports for command
and address input as well as data input/output. This interface allows a reduced pin count and easy migration towards different
densities, without any rearrangement of the footprint.
Commands, Data, and Addresses are asynchronously introduced using CE#, WE#, ALE, and CLE control pins.
The on-chip Program/Erase Controller automates all read, program, and erase functions including pulse repetition, where required,
and internal verification and margining of data. A WP# pin is available to provide hardware protection against program and erase
operations.
The output pin R/B# (open drain buffer) signals the status of the device during each operation. It identifies if the program/erase/read
controller is currently active. The use of an open-drain output allows the Ready/Busy pins from several memories to connect to a
single pull-up resistor. In a system with multiple memories the
R/B# pins can be connected all together to provide a global status signal.
The Reprogram function allows the optimization of defective block management — when a Page Program operation fails the data
can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase.
Multiplane Copy Back is also supported. Data read out after Copy Back Read (both for single and multiplane cases) is allowed.
In addition, Cache Program and Multiplane Cache Program operations improve the programing throughput by programing data
using the cache register.
The devices provide two innovative features: Page Reprogram and Multiplane Page Reprogram. The Page Reprogram re-programs
one page. Normally, this operation is performed after a failed Page Program operation. Similarly, the Multiplane Page Reprogram re-
programs two pages in parallel, one per plane. The first page must be in the first plane while the second page must be in the second
plane. The Multiplane Page Reprogram operation is performed after a failed Multiplane Page Program operation. The Page
Reprogram and Multiplane Page Reprogram guarantee improved performance, since data insertion can be omitted during re-
program operations.
The devices are available in the TSOP48 (12 x 20 mm) package and come with the following security features:
OTP (one time programmable) area, which is a restricted access area where sensitive data/code can be stored permanently.
Serial number (unique identifier), which allows the devices to be uniquely identified. Contact factory for support of this feature.
These security features are subject to an NDA (non-disclosure agreement) and are, therefore, not described in the data sheet. For
more details about them, contact your nearest sales office.
Document Number: 002-00499 Rev. *N
Page 3 of 76
S34ML01G2
S34ML02G2
S34ML04G2
Density (bits)
Number of Blocks per
Plane
Device
Number of Planes
Main
Spare
128M x 8
64M x 16
4M x 8
S34ML01G2
S34ML02G2
S34ML04G2
1
2
2
1024
1024
2048
2M x 16
256M x 8
16M x 8
8M x 16
128M x 16
512M x 8
32M x 8
256M x 16
16M x 16
1.1
Logic Diagram
Figure 1.1 Logic Diagram
VCC
I/O0~I/O7
CE#
WE#
R/B#
RE#
ALE
CLE
WP#
VSS
Table 1.1 Signal Names
I/O7 - I/O0 (×8)
Data Input / Outputs
I/O8 - I/O15 (×16)
CLE
ALE
CE#
RE#
WE#
WP#
R/B#
VCC
VSS
NC
Command Latch Enable
Address Latch Enable
Chip Enable
Read Enable
Write Enable
Write Protect
Read/Busy
Power Supply
Ground
Not Connected
Document Number: 002-00499 Rev. *N
Page 4 of 76
S34ML01G2
S34ML02G2
S34ML04G2
1.2
Connection Diagram
Figure 1.2 48-Pin TSOP1 Contact ×8, ×16 Device
x8
x16
x8
x16
(1)
1
48
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
NC
NC
NC
I/O7
I/O6
VSS
I/O15
I/O14
I/O13
I/O7
I/O6
NC
NC
I/O5
I/O4
NC
I/O5
I/O4
I/O12
R/B#
RE#
CE#
NC
R/B#
RE#
CE#
NC
(1)
(1)
VCC
NC
VCC
VSS
NC
VCC
NC
I/O3
I/O2
I/O1
VCC
NC
VCC
VSS
NC
VCC
I/011
I/O3
I/O2
I/O1
NC
NC
NAND Flash
TSOP1
VCC
VSS
NC
VCC
VSS
NC
12
13
37
36
NC
NC
CLE
ALE
WE#
WP#
NC
CLE
ALE
WE#
WP#
NC
I/O0
NC
I/O0
I/O10
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
I/O9
I/O8
VSS
(1)
24
25
Note:
1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be bonded internally.
Figure 1.3 63-BGA Contact, ×8 Device (Balls Down, Top View)
A2
A9
A1
A10
NC
NC
NC
NC
B1
B9
B10
NC
NC
NC
C3
C4
C5
C6
C7
C8
WP#
ALE
VSS
CE#
WE#
RB#
D3
D4
D5
D6
D7
D8
VCC (1)
RE#
CLE
NC
NC
NC
E3
E4
E5
E6
E7
E8
NC
NC
NC
NC
NC
NC
F3
F4
F5
F6
F7
F8
NC
NC
NC
NC
VSS (1)
NC
G3
NC
G4
G5
NC
G6
NC
G7
NC
G8
NC
VCC (1)
H3
H4
H5
H6
H7
H8
NC
I/O0
NC
NC
NC
V
cc
J3
J4
J5
J6
J7
J8
NC
I/O1
NC
V
I/O5
I/O7
K8
CC
K3
K4
K5
K6
K7
V
I/O2
I/O3
I/O4
I/O6
V
SS
SS
L1
L2
L9
L10
NC
NC
NC
NC
M1
NC
M2
NC
M9
NC
M10
NC
Note:
1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be bonded internally.
Document Number: 002-00499 Rev. *N
Page 5 of 76
S34ML01G2
S34ML02G2
S34ML04G2
Figure 1.4 63-BGA Contact, x16 Device (Balls Down, Top View)
A2
A9
A1
A10
NC
NC
NC
NC
B1
B9
B10
NC
NC
NC
C3
C4
C5
C6
C7
C8
WP#
ALE
VSS
CE#
WE#
RB#
D3
D4
D5
D6
D7
D8
VCC
RE#
CLE
NC
NC
NC
E3
E4
E5
E6
E7
E8
NC
NC
NC
NC
NC
NC
F3
F4
F5
F6
F7
F8
NC
NC
NC
NC
VSS
NC
G3
NC
G4
G5
NC
G6
G7
G8
NC
VCC
I/O13
I/O15
H3
H4
H5
H6
H7
H8
I/O8
I/O0
I/O10
I/O12
I/O14
V
cc
J3
J4
J5
J6
J7
J8
I/O9
I/O1
I/O11
V
I/O5
I/O7
K8
CC
K3
K4
K5
K6
K7
V
I/O2
I/O3
I/O4
I/O6
V
SS
SS
L1
L2
L9
L10
NC
NC
NC
NC
M1
NC
M2
NC
M9
NC
M10
NC
Document Number: 002-00499 Rev. *N
Page 6 of 76
S34ML01G2
S34ML02G2
S34ML04G2
Figure 1.5 67-BGA Contact (Balls Down, Top View)
A2
A3
A6
A7
A8
NC
NC
NC
NC
NC
B1
B2
B3
B4
B5
B6
B7
B8
NC
WP#
ALE
VSS
CE#
WE#
RY/BY#
NC
C1
C2
C3
C4
C5
C6
C7
C8
NC
NC
RE#
CLE
NC
NC
NC
NC
D2
D3
D4
D5
D6
D7
NC
NC
NC
NC
NC
NC
E2
E3
E4
E5
E6
E7
NC
NC
NC
NC
NC
NC
F2
F3
F4
F5
F6
F7
NC
NC
NC
NC
NC
NC
G2
NC
G3
G4
NC
G5
NC
G6
NC
G7
I/O0
VCC
H1
H2
H3
H4
H5
H6
H7
H8
NC
NC
I/O1
NC
VCC
I/O5
I/O7
NC
J1
J2
J3
J4
J5
J6
J7
J8
NC
VSS
I/O2
I/O3
I/O4
I/O6
VSS
NC
K1
K2
K3
K6
K7
K8
NC
NC
NC
NC
NC
NC
1.3
Pin Description
Table 1.2 Pin Description
Pin Name
Description
I/O0 - I/O7 (×8)
Inputs/Outputs. The I/O pins are used for command input, address input, data input, and data output. The
I/O pins float to High-Z when the device is deselected or the outputs are disabled.
I/O8 - I/O15 (×16)
Command Latch Enable. This input activates the latching of the I/O inputs inside the Command Register on the
rising edge of Write Enable (WE#).
CLE
ALE
CE#
WE#
RE#
Address Latch Enable. This input activates the latching of the I/O inputs inside the Address Register on the rising
edge of Write Enable (WE#).
Chip Enable. This input controls the selection of the device. When the device is not busy CE# low selects the
memory.
Write Enable. This input latches Command, Address and Data. The I/O inputs are latched on the rising edge of
WE#.
Read Enable. The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data is
valid t
after the falling edge of RE# which also increments the internal column address counter by one.
REA
Write Protect. The WP# pin, when low, provides hardware protection against undesired data modification
(program / erase).
WP#
R/B#
VCC
Ready Busy. The Ready/Busy output is an Open Drain pin that signals the state of the memory.
Supply Voltage. The V supplies the power for all the operations (Read, Program, Erase). An internal lock circuit
CC
prevents the insertion of Commands when V is less than V
.
CC
LKO
VSS
NC
Ground.
Not Connected.
Notes:
1. A 0.1 µF capacitor should be connected between the V Supply Voltage pin and the V Ground pin to decouple the current surges from the power supply. The PCB
CC
SS
track widths must be sufficient to carry the currents required during program and erase operations.
2. An internal voltage detector disables all functions whenever V is below 1.8V to protect the device from any involuntary program/erase during power transitions.
CC
Document Number: 002-00499 Rev. *N
Page 7 of 76
S34ML01G2
S34ML02G2
S34ML04G2
1.4
Block Diagram
Figure 1.6 Functional Block Diagram
Address
Register/
Counter
Program Erase
Controller
HV Generation
X
1024 Mbit + 32 Mbit (1 Gb Device)
2048 Mbit + 128 Mbit (2 Gb Device)
4096 Mbit + 256 Mbit (4 Gb Device)
D
E
C
O
D
E
R
ALE
CLE
NAND Flash
WE#
CE#
WP#
Memory Array
Command
Interface
Logic
RE#
PAGE Buffer
Y Decoder
I/O Buffer
Command
Register
Data
Register
I/O0~I/O7 (x8)
I/O0~I/O15 (x16)
Document Number: 002-00499 Rev. *N
Page 8 of 76
S34ML01G2
S34ML02G2
S34ML04G2
1.5
Array Organization
Figure 1.7 Array Organization — S34ML01G2 (×8)
1 Page = (2k + 64) Bytes
Plane(s)
1 Block = (2k + 64) Bytes x 64 Pages
= (128k + 4k) Bytes
0
1
1 Plane = (128k + 4k) Bytes x 1024 Blocks
1024
Blocks
per
2
Plane
1022
1023
I/O
[7:0]
Page Buffer
2048 Bytes
64 Bytes
Array Organization (x8)
Figure 1.8 Array Organization — S34ML01G2 (x16)
1 Page = (1k + 32) Words
Plane(s)
1 Block = (1k + 32) Words x 64 Pages
= (64k + 2k) Words
0
1
1 Plane = (64k + 2k) Words x 1024 Blocks
1024
Blocks
per
2
Plane
1022
1023
I/O0~I/O15
Page Buffer
32 Words
1024 Words
Array Organization (x16)
Document Number: 002-00499 Rev. *N
Page 9 of 76
S34ML01G2
S34ML02G2
S34ML04G2
Figure 1.9 Array Organization — S34ML02G2 and S34ML04G2 (×8)
2176 Bytes
2176 Bytes
I/O 7
I/O 0
Cache Register
Data Register
128
128
128
128
2048
2048
2048
2048
1 Page = (2K+128) Bytes
1 Block = (2K+128) Bytes x 64 Pages
= (128K+8K) Bytes
S34ML02G2 has
1024 Blocks per Plane
1 Block
1 Block
S34ML02G2 Device = (128K+8K) x 2048 Blocks
S34ML04G2 Device = (128K+8K) x 4096 Blocks
S34ML04G2 has
2048 Blocks per Plane
Plane 1
Plane 0
Array Organization (x8)
Figure 1.10 Array Organization — S34ML02G2 and S34ML04G2 (x16)
1088 Words
1088 Words
I/O 15
I/O 0
Cache Register
Data Register
64
64
64
64
1024
1024
1024
1024
1 Page = (1K+64) Words
1 Block = (1K+64) Words x 64 Pages
= (64K+4K) Words
S34ML02G2 has
1024 Blocks per Plane
1 Block
1 Block
S34ML04G2 has
2048 Blocks per Plane
S34ML02G2 Device = (64K+4K) x 2048 Blocks
S34ML04G2 Device = (64K+4K) x 4096 Blocks
Plane 1
Plane 0
Array Organization (x16)
Document Number: 002-00499 Rev. *N
Page 10 of 76
S34ML01G2
S34ML02G2
S34ML04G2
1.6
Addressing
S34ML01G2
1.6.1
Table 1.3 Address Cycle Map — 1 Gb Device
Bus Cycle
I/O [15:8] (5)
I/O0
I/O1
I/O2
×8
A2 (CA2)
I/O3
I/O4
I/O5
I/O6
I/O7
1st / Col. Add.1
2nd / Col. Add. 2
3rd / Row Add. 1
4th / Row Add. 2
—
—
—
—
A0 (CA0)
A8 (CA8)
A1 (CA1)
A3 (CA3)
A4 (CA4)
Low
A5 (CA5)
Low
A6 (CA6)
Low
A7 (CA7)
Low
A9 (CA9) A10 (CA10) A11 (CA11)
A12 (PA0) A13 (PA1) A14 (PA2)
A20 (BA2) A21 (BA3) A22 (BA4)
×16
A15 (PA3) A16 (PA4) A17 (PA5) A18 (BA0) A19 (BA1)
A23 (BA5) A24 (BA6) A25 (BA7) A26 (BA8) A27 (BA9)
1st / Col. Add.1
2nd / Col. Add. 2
3rd / Row Add. 1
4th / Row Add. 2
Low
Low
Low
Low
A0 (CA0)
A8 (CA8)
A1 (CA1)
A2 (CA2)
A3 (CA3)
Low
A4 (CA4)
Low
A5 (CA5)
Low
A6 (CA6)
Low
A7 (CA7)
Low
A9 (CA9) A10 (CA10)
A11 (PA0) A12 (PA1) A13 (PA2)
A19 (BA2) A20 (BA3) A21 (BA4)
A14 (PA3) A15 (PA4) A16 (PA5) A17 (BA0) A18 (BA1)
A22 (BA5) A23 (BA6) A24 (BA7) A25 (BA8) A26 (BA9)
Notes:
1. CAx = Column Address bit.
2. PAx = Page Address bit.
3. BAx = Block Address bit.
4. Block address concatenated with page address = actual page address, also known as the row address.
5. I/O[15:8] are not used during the addressing sequence and should be driven Low.
For the ×8 address bits, the following rules apply:
A0 - A11: column address in the page
A12 - A17: page address in the block
A18 - A27: block address
For the x16 address bits, the following rules apply:
A0 - A10: column address in the page
A11 - A16: page address in the block
A17 - A26: block address
1.6.2
S34ML02G2
Table 1.4 Address Cycle Map — 2 Gb Device
Bus Cycle
I/O [15:8] (6)
I/O0
I/O1
I/O2
×8
A2 (CA2)
I/O3
I/O4
I/O5
I/O6
I/O7
1st / Col. Add.1
2nd / Col. Add. 2
—
—
A0 (CA0)
A8 (CA8)
A1 (CA1)
A3 (CA3)
A4 (CA4)
Low
A5 (CA5)
Low
A6 (CA6)
Low
A7 (CA7)
Low
A9 (CA9) A10 (CA10) A11 (CA11)
A18
(PLA0)
3rd / Row Add. 1
—
A12 (PA0) A13 (PA1) A14 (PA2)
A20 (BA1) A21 (BA2) A22 (BA3)
A15 (PA3) A16 (PA4) A17 (PA5)
A19 (BA0)
4th / Row Add. 2
5th / Row Add. 3
—
—
A23 (BA4) A24 (BA5) A25 (BA6) A26 (BA7) A27 (BA8)
A28 (BA9)
Low
Low
×16
A2 (CA2)
Low
Low
Low
Low
Low
1st / Col. Add.1
Low
A0 (CA0)
A1 (CA1)
A3 (CA3)
A4 (CA4)
A5 (CA5)
A6 (CA6)
A7 (CA7)
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Page 11 of 76
S34ML01G2
S34ML02G2
S34ML04G2
Table 1.4 Address Cycle Map — 2 Gb Device
Bus Cycle
I/O [15:8] (6)
I/O0
I/O1
I/O2
×8
A9 (CA9) A10 (CA10)
I/O3
I/O4
I/O5
I/O6
I/O7
2nd / Col. Add. 2
3rd / Row Add. 1
Low
Low
A8 (CA8)
Low
Low
Low
Low
Low
A17
(PLA0)
A11 (PA0) A12 (PA1) A13 (PA2)
A19 (BA1) A20 (BA2) A21 (BA3)
A14 (PA3) A15 (PA4) A16 (PA5)
A18 (BA0)
4th / Row Add. 2
5th / Row Add. 3
Low
Low
A22 (BA4) A23 (BA5) A24 (BA6) A25 (BA7) A26 (BA8)
A27 (BA9)
Low
Low
Low
Low
Low
Low
Low
Notes:
1. CAx = Column Address bit.
2. PAx = Page Address bit.
3. PLA0 = Plane Address bit zero.
4. BAx = Block Address bit.
5. Block address concatenated with page address and plane address = actual page address, also known as the row address.
6. I/O[15:8] are not used during the addressing sequence and should be driven Low.
For the ×8 address bits, the following rules apply:
A0 - A11: column address in the page
A12 - A17: page address in the block
A18: plane address (for multiplane operations) / block address (for normal operations)
A19 - A28: block address
For the x16 address bits, the following rules apply:
A0 - A10: column address in the page
A11 - A16: page address in the block
A17: plane address (for multiplane operations) / block address (for normal operations)
A18 - A27: block address
1.6.3
S34ML04G2
Table 1.5 Address Cycle Map — 4 Gb Device
Bus Cycle
I/O [15:8] (6)
I/O0
I/O1
I/O2
×8
A2 (CA2)
I/O3
I/O4
I/O5
I/O6
I/O7
1st / Col. Add.1
2nd / Col. Add. 2
—
—
A0 (CA0)
A8 (CA8)
A1 (CA1)
A3 (CA3)
A4 (CA4)
Low
A5 (CA5)
Low
A6 (CA6)
Low
A7 (CA7)
Low
A9 (CA9) A10 (CA10) A11 (CA11)
A18
(PLA0)
3rd / Row Add. 1
—
A12 (PA0) A13 (PA1)
A14 (PA2)
A15 (PA3) A16 (PA4) A17 (PA5)
A19 (BA0)
4th / Row Add. 2
5th / Row Add. 3
—
—
A20 (BA1) A21 (BA2)
A28 (BA9) A29 (BA10)
A22 (BA3)
Low
A23 (BA4) A24 (BA5) A25 (BA6) A26 (BA7) A27 (BA8)
Low
Low
Low
Low
Low
×16
1st / Col. Add.1
2nd / Col. Add. 2
Low
Low
A0 (CA0)
A8 (CA8)
A1 (CA1)
A2 (CA2)
A3 (CA3)
Low
A4 (CA4)
Low
A5 (CA5)
Low
A6 (CA6)
Low
A7 (CA7)
Low
A9 (CA9) A10 (CA10)
A17
(PLA0)
3rd / Row Add. 1
Low
A11 (PA0) A12 (PA1)
A13 (PA2)
A14 (PA3) A15 (PA4) A16 (PA5)
A18 (BA0)
4th / Row Add. 2
5th / Row Add. 3
Low
Low
A19 (BA1) A20 (BA2)
A27 (BA9) A28 (BA10)
A21 (BA3)
Low
A22 (BA4) A23 (BA5) A24 (BA6) A25 (BA7) A26 (BA8)
Low Low Low Low Low
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Page 12 of 76
S34ML01G2
S34ML02G2
S34ML04G2
Notes:
1. CAx = Column Address bit.
2. PAx = Page Address bit.
3. PLA0 = Plane Address bit zero.
4. BAx = Block Address bit.
5. Block address concatenated with page address and plane address = actual page address, also known as the row address.
6. I/O[15:8] are not used during the addressing sequence and should be driven Low.
For the ×8 address bits, the following rules apply:
A0 - A11: column address in the page
A12 - A17: page address in the block
A18: plane address (for multiplane operations) / block address (for normal operations)
A19 - A29: block address
For the x16 address bits, the following rules apply:
A0 - A10: column address in the page
A11 - A16: page address in the block
A17: plane address (for multiplane operations) / block address (for normal operations)
A18 - A28: block address
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S34ML01G2
S34ML02G2
S34ML04G2
1.7
Mode Selection
Table 1.6 Mode Selection
Mode
CLE
High
Low
High
Low
Low
Low
X
ALE
Low
High
Low
High
Low
Low
X
CE#
Low
Low
Low
Low
Low
Low
X
WE#
Rising
Rising
Rising
Rising
Rising
High
High
High
X
RE#
High
High
High
High
High
Falling
High
High (3)
X
WP#
X
Command Input
Read Mode
Address Input
Command Input
Address Input
X
High
High
High
X
Program or Erase Mode
Data Input
Data Output (on going)
Data Output (suspended)
Busy Time in Read
Busy Time in Program
Busy Time in Erase
Write Protect
X
X
X
X
X
X
X
X
High
High
Low
X
X
X
X
X
X
X
X
X
X
Stand By
X
X
High
X
X
0V / V (2)
CC
Notes:
1. X can be V or V . High = Logic level high, Low = Logic level low.
IL
IH
2. WP# should be biased to CMOS high or CMOS low for stand-by mode.
3. During Busy Time in Read, RE# must be held high to prevent unintended data out.
2. Bus Operation
There are six standard bus operations that control the device: Command Input, Address Input, Data Input, Data Output, Write
Protect, and Standby. (See Table 1.6.)
Typically glitches less than 5 ns on Chip Enable, Write Enable, and Read Enable are ignored by the memory and do not affect bus
operations.
2.1
Command Input
The Command Input bus operation is used to give a command to the memory device. Commands are accepted with Chip Enable
low, Command Latch Enable high, Address Latch Enable low, and Read Enable high and latched on the rising edge of Write Enable.
Moreover, for commands that start a modify operation (program/erase) the Write Protect pin must be high. See Figure 6.1
on page 39 and Table 5.5 on page 36 for details of the timing requirements. Command codes are always applied on I/O7:0
regardless of the bus configuration (×8 or ×16).
2.2
Address Input
The Address Input bus operation allows the insertion of the memory address. For the S34ML02G2 and S34ML04G2 devices, five
write cycles are needed to input the addresses. For the S34ML01G2, four write cycles are needed to input the addresses. If
necessary, a 5th dummy address cycle can be issued to S34ML01G2, which will be ignored by the NAND device without causing
problems. Addresses are accepted with Chip Enable low, Address Latch Enable high, Command Latch Enable low, and Read
Enable high and latched on the rising edge of Write Enable. Moreover, for commands that start a modify operation (program/erase)
the Write Protect pin must be high. See Figure 6.2 on page 40 and Table 5.5 on page 36 for details of the timing requirements.
Addresses are always applied on I/O7:0 regardless of the bus configuration (×8 or ×16). Refer to Table 1.3 through Table 1.5
on page 12 for more detailed information.
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S34ML01G2
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S34ML04G2
2.3
Data Input
The Data Input bus operation allows the data to be programmed to be sent to the device. The data insertion is serial and timed by
the Write Enable cycles. Data is accepted only with Chip Enable low, Address Latch Enable low, Command Latch Enable low, Read
Enable high, and Write Protect high and latched on the rising edge of Write Enable. See Figure 6.3 on page 41 and Table 5.5
on page 36 for details of the timing requirements.
2.4
Data Output
The Data Output bus operation allows data to be read from the memory array and to check the Status Register content, and the ID
data. Data can be serially shifted out by toggling the Read Enable pin with Chip Enable low, Write Enable high, Address Latch
Enable low, and Command Latch Enable low. See Figure 6.4 on page 41 and Table 5.5 on page 36 for details of the timings
requirements.
2.5
Write Protect
The Hardware Write Protection is activated when the Write Protect pin is low. In this condition, modify operations do not start and the
content of the memory is not altered. The Write Protect pin is not latched by Write Enable to ensure the protection even during power
up.
2.6
Standby
In Standby, the device is deselected, outputs are disabled, and power consumption is reduced.
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S34ML01G2
S34ML02G2
S34ML04G2
3. Command Set
Table 3.1 Command Set
Acceptable
Command
during Busy
Supported on
S34ML01G2
Command
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
Page Read
00h
80h
30h
10h
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
No
Page Program
Random Data Input
85h
Random Data Output
05h
E0h
11h
11h
10h
11h
D0h
60h
D1h
35h
10h
11h
11h
36h
Multiplane Program
80h
81h
80h
10h
10h
ONFI Multiplane Program
Page Reprogram
80h
No
8Bh
Yes
No
Multiplane Page Reprogram
Block Erase
8Bh
8Bh
10h
60h
Yes
No
Multiplane Block Erase
ONFI Multiplane Block Erase
Copy Back Read
60h
D0h
60h
60h
D0h
No
00h
Yes
Yes
No
Copy Back Program
85h
Multiplane Copy Back Program
ONFI Multiplane Copy Back Program
Special Read For Copy Back
Read Status Register
85h
81h
85h
10h
10h
85h
No
00h
No
70h
Yes
No
Read Status Enhanced
Reset
78h
FFh
Yes
Yes
Yes
Yes
Yes
Yes
No
Read Cache
31h
Read Cache Enhanced
Read Cache End
00h
31h
3Fh
Cache Program (End)
Cache Program (Start) / (Continue)
Multiplane Cache Program (Start/Continue)
ONFI Multiplane Cache Program (Start/Continue)
Multiplane Cache Program (End)
ONFI Multiplane Cache Program (End)
Read ID
80h
10h
15h
11h
11h
11h
11h
80h
80h
81h
80h
81h
80h
15h
15h
10h
10h
80h
No
80h
No
80h
No
90h
Yes
Yes
Yes
Yes
Yes
Yes
Read ID2
30h-65h-00h
90h
30h
Read ONFI Signature
Read Parameter Page
Read Unique ID (Contact Factory)
One-time Programmable (OTP) Area Entry
ECh
EDh
29h-17h-04h-19h
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Page 16 of 76
S34ML01G2
S34ML02G2
S34ML04G2
3.1
Page Read
Page Read is initiated by writing 00h and 30h to the command register along with five address cycles (four or five cycles for
S34ML01G2). Two types of operations are available: random read and serial page read. Random read mode is enabled when the
page address is changed. All data within the selected page are transferred to the data registers. The system controller may detect
the completion of this data transfer (tR) by analyzing the output of the R/B pin. Once the data in a page is loaded into the data
registers, they may be read out in 25 ns cycle time by sequentially pulsing RE#. The repetitive high to low transitions of the RE#
signal makes the device output the data, starting from the selected column address up to the last column address.
The device may output random data in a page instead of the sequential data by writing Random Data Output command. The column
address of next data, which is going to be out, may be changed to the address that follows Random Data Output command. Random
Data Output can be performed as many times as needed.
After power up, the device is in read mode, so 00h command cycle is not necessary to start a read operation. Any operation other
than read or Random Data Output causes the device to exit read mode.
See Figure 6.6 on page 42 and Figure 6.12 on page 46 as references.
3.2
Page Program
A page program cycle consists of a serial data loading period in which up to 2 KB (×8) or 1 kword (×16) of data may be loaded into
the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the five cycle address inputs
(four cycles for S34ML01G2) and then serial data. The words other than those to be programmed do not need to be loaded. The
device supports Random Data Input within a page. The column address of next data, which will be entered, may be changed to the
address that follows the Random Data Input command (85h). Random Data Input may be performed as many times as needed.
The Page Program confirm command (10h) initiates the programming process. The internal write state controller automatically
executes the algorithms and controls timings necessary for program and verify, thereby freeing the system controller for other tasks.
Once the program process starts, the Read Status Register commands (70h or 78h) may be issued to read the Status Register. The
system controller can detect the completion of a program cycle by monitoring the
R/B# output, or the Status bit (I/O6) of the Status Register. Only the Read Status commands (70h or 78h) or Reset command are
valid while programming is in progress. When the Page Program is complete, the Write Status Bit (I/O0) may be checked. The
internal write verify detects only errors for 1’s that are not successfully programmed to 0’s. The command register remains in Read
Status command mode until another valid command is written to the command register. Figure 6.9 on page 44 and Figure 6.11
on page 45 detail the sequence.
The device is programmable by page, but it also allows multiple partial page programming of a word or consecutive bytes up to 2 KB
(×8) or 1 kword (×16) in a single page program cycle.
The number of consecutive partial page programming operations (NOP) within the same page must not exceed the number
indicated in Table 5.8 on page 38. Pages may be programmed in any order within a block.
If a Page Program operation is interrupted by hardware reset, power failure or other means, the host must ensure that the
interrupted page is not used for further reading or programming operations until the next uninterrupted block erase is complete.
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Page 17 of 76
S34ML01G2
S34ML02G2
S34ML04G2
3.3
Multiplane Program — S34ML02G2 and S34ML04G2
The S34ML02G2 and S34ML04G2 devices support Multiplane Program, making it possible to program two pages in parallel, one
page per plane.
A Multiplane Program cycle consists of a double serial data loading period in which up to 4352 bytes (×8) or 2176 words (x16) of
data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into
the appropriate cell. The serial data loading period begins with inputting the Serial Data Input command (80h), followed by the five
cycle address inputs and serial data for the 1st page. The address for this page must be in the 1st plane (PLA0 = 0). The device
supports Random Data Input exactly the same as in the case of page program operation. The Dummy Page Program Confirm
command (11h) stops 1st page data input and the device becomes busy for a short time (tDBSY). Once it has become ready again,
the ‘81h’ command must be issued, followed by 2nd page address (5 cycles) and its serial data input. The address for this page
must be in the 2nd plane (PLA0 = 1). The Program Confirm command (10h) starts parallel programming of both pages.
Figure 6.13 on page 46 describes the sequences using the legacy protocol. In this case, the block address bits for the first plane are
all zero and the second address issued selects the block for both planes. Figure 6.14 on page 47 describes the sequences using the
ONFI protocol. For both addresses issued in this protocol, the block address bits must be the same except for the bit(s) that select
the plane.
The user can check operation status by monitoring R/B# pin or reading the Status Register (command 70h or 78h). The Read Status
Register command is also available during Dummy Busy time (tDBSY). In case of failure in either page program, the fail bit of the
Status Register will be set. Refer to Section 3.8 on page 22 for further info.
The number of consecutive partial page programming operations (NOP) within the same page must not exceed the number
indicated in Table 5.8 on page 38. Pages may be programmed in any order within a block.
If a Multiplane Program operation is interrupted by hardware reset, power failure or other means, the host must ensure that the
interrupted pages are not used for further reading or programming operations until the next uninterrupted block erases are complete
for the applicable blocks.
3.4
Page Reprogram
Page Program may result in a fail, which can be detected by Read Status Register. In this event, the host may call Page Reprogram.
This command allows the reprogramming of the same pattern of the last (failed) page into another memory location. The command
sequence initiates with reprogram setup (8Bh), followed by the five cycle address inputs of the target page. If the target pattern for
the destination page is not changed compared to the last page, the program confirm can be issued (10h) without any data input
cycle, as described in Figure 3.1.
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Page 18 of 76
S34ML01G2
S34ML02G2
S34ML04G2
Figure 3.1 Page Reprogram
As defined for Page
Program
A
Din
D0
Din
D1
Din
Din
Dn
CMD
10h
CMD
ADDR ADDR
ADDR
R3
ADDR
ADDR
R2
Cycle Type
I/Ox
tADL
00h
C2
. . .
R1
C1
tWB
tPROG
SR[6]
Page N
A
Cycle Type
Dout
E1
CMD
10h
CMD
ADDR ADDR
ADDR
R3
CMD
70h
ADDR
R2
ADDR
C1
8Bh
C2
R1
I/Ox
tWB
tPROG
SR[6]
FAIL !
Page M
On the other hand, if the pattern bound for the target page is different from that of the previous page, data in cycles can be issued
before program confirm ‘10h’, as described in Figure 3.2.
Figure 3.2 Page Reprogram with Data Manipulation
As defined for Page
A
Program
Din
D0
Din
D1
Din
Din
Dn
CMD
10h
CMD
70h
Dout
E1
CMD
80h
ADDR
C1
ADDR ADDR ADDR
ADDR
R3
Cycle Type
IOx
tADL
. . .
C2
R1
R2
tWB
tPROG
SR[6]
FAIL !
Page N
A
Cycle Type
CMD
8Bh
ADDR ADDR ADDR ADDR ADDR
Din
D0
Din
D1
Din
Din
Dn
CMD
10h
tADL
I/Ox
. . .
C1
C2
R1
R2
R3
tWB
tPROG
SR[6]
Page M
The device supports Random Data Input within a page. The column address of next data, which will be entered, may be changed to
the address which follows the Random Data Input command (85h). Random Data Input may be operated multiple times regardless
of how many times it is done in a page.
The Program Confirm command (10h) initiates the re-programming process. The internal write state controller automatically
executes the algorithms and controls timings necessary for program and verify, thereby freeing the system controller for other tasks.
Once the program process starts, the Read Status Register command may be issued to read the Status Register. The system
controller can detect the completion of a program cycle by monitoring the R/B# output, or the Status bit (I/O6) of the Status Register.
Only the Read Status command and Reset command are valid when programming is in progress. When the Page Program is
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Page 19 of 76
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S34ML04G2
complete, the Write Status Bit (I/O0) may be checked. The internal write verify detects only errors for 1’s that are not successfully
programmed to 0’s. The command register remains in Read Status command mode until another valid command is written to the
command register.
The Page Reprogram must be issued in the same plane as the Page Program that failed. In order to program the data to a different
plane, use the Page Program operation instead. The Multiplane Page Reprogram can re-program two pages in parallel, one per
plane. The Multiplane Page Reprogram operation is performed after a failed Multiplane Page Program operation. The command
sequence is very similar to Figure 6.13, Multiplane Page Program on page 46, except that it requires the Page Reprogram
Command (8Bh) instead of 80h and 81h.
If a Page Reprogram operation is interrupted by hardware reset, power failure or other means, the host must ensure that the
interrupted page is not used for further reading or programming operations until the next uninterrupted block erase is complete.
3.5
Block Erase
The Block Erase operation is done on a block basis. Block address loading is accomplished in three cycles (two cycles for
S34ML01G2) initiated by an Erase Setup command (60h). Only the block address bits are valid while the page address bits are
ignored.
The Erase Confirm command (D0h) following the block address loading initiates the internal erasing process. This two-step
sequence of setup followed by the execution command ensures that memory contents are not accidentally erased due to external
noise conditions.
At the rising edge of WE# after the erase confirm command input, the internal write controller handles erase and erase verify. Once
the erase process starts, the Read Status Register commands (70h or 78h) may be issued to read the Status Register.
The system controller can detect the completion of an erase by monitoring the R/B# output, or the Status bit
(I/O6) of the Status Register. Only the Read Status commands (70h or 78h) and Reset command are valid while erasing is in
progress. When the erase operation is completed, the Write Status Bit (I/O0) may be checked. Figure 6.15 on page 47 details the
sequence.
If a Block Erase operation is interrupted by hardware reset, power failure or other means, the host must ensure that the interrupted
block is erased under continuous power conditions before that block can be trusted for further programming and reading operations.
3.6
Multiplane Block Erase — S34ML02G2 and S34ML04G2
Multiplane Block Erase allows the erase of two blocks in parallel, one block per memory plane.
The Block erase setup command (60h) must be repeated two times, followed by 1st and 2nd block address respectively (3 cycles
each). As for block erase, D0h command makes embedded operation start. In this case, multiplane erase does not need any
Dummy Busy Time between 1st and 2nd block insertion. See Table 5.8 on page 38 for performance information.
For the Multiplane Block Erase operation, the address of the first block must be within the first plane
(PLA0 = 0) and the address of the second block in the second plane (PLA0 = 1). See Figure 6.16 on page 48 for a description of the
legacy protocol. In this case, the block address bits for the first plane are all zero and the second address issued selects the block
for both planes. Figure 6.17 on page 48 describes the sequences using the ONFI protocol. For both addresses issued in this
protocol, the block address bits must be the same except for the bit(s) that select the plane.
The user can check operation status by monitoring R/B# pin or reading the Status Register (command 70h or 78h). The Read Status
Register command is also available during Dummy Busy time (tDBSY). In case of failure in either erase, the fail bit of the Status
Register will be set. Refer to Section 3.7.2 on page 21 for further information.
If a Multiplane Block Erase operation is interrupted by hardware reset, power failure or other means, the host must ensure that the
interrupted blocks are erased under continuous power conditions before those blocks can be trusted for further programming and
reading operations.
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3.7
Copy Back Program
The copy back feature is intended to quickly and efficiently rewrite data stored in one page without utilizing an external memory.
Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is greatly improved.
The benefit is especially obvious when a portion of a block needs to be updated and the rest of the block also needs to be copied to
the newly assigned free block. The operation for performing a copy back is a sequential execution of page-read (without mandatory
serial access) and Copy Back Program with the address of destination page. A read operation with the ‘35h’ command and the
address of the source page moves the whole page of data into the internal data register. As soon as the device returns to the Ready
state, optional data read-out is allowed by toggling RE# (see Figure 6.18 on page 49), or the Copy Back Program command (85h)
with the address cycles of the destination page may be written. The Program Confirm command (10h) is required to actually begin
programming.
The source and the destination pages in the Copy Back Program sequence must belong to the same device plane (same PLA0 for
S34ML02G2 and S34ML04G2). Copy Back Read and Copy Back Program for a given plane must be between odd address pages or
between even address pages for the device to meet the program time (tPROG) specification. Copy Back Program may not meet this
specification when copying from an odd address page (source page) to an even address page (target page) or from an even
address page (source page) to an odd address page (target page).
The data input cycle for modifying a portion or multiple distinct portions of the source page is allowed as shown in Figure 6.19
on page 49.
If a Copy Back Program operation is interrupted by hardware reset, power failure or other means, the host must ensure that the
interrupted page is not used for further reading or programming operations until the next uninterrupted block erase is complete.
3.7.1
Multiplane Copy Back Program — S34ML02G2 and S34ML04G2
The device supports Multiplane Copy Back Program with exactly the same sequence and limitations as the Page Program.
Multiplane Copy Back Program must be preceded by two single page Copy Back Read command sequences (1st page must be
read from the 1st plane and 2nd page from the 2nd plane).
Multiplane Copy Back cannot cross plane boundaries — the contents of the source page of one device plane can be copied only to
a destination page of the same plane.
The Multiplane Copy Back Program sequence represented in Figure 6.20 on page 50 shows the legacy protocol. In this case, the
block address bits for the first plane are all zero and the second address issued selects the block for both planes. Figure 6.21
on page 51 describes the sequence using the ONFI protocol. For both addresses issued in this protocol, the block address bits must
be the same except for the bit(s) that select the plane.
If a Multiplane Copy Back Program operation is interrupted by hardware reset, power failure or other means, the host must ensure
that the interrupted pages are not used for further reading or programming operations until the next uninterrupted block erases are
complete for the applicable blocks.
3.7.2
Special Read for Copy Back — S34ML02G2 and S34ML04G2
The S34ML02G2 and S34ML04G2 devices support Special Read for Copy Back. If Copy Back Read (described in Section 3.7 and
Section 3.7.1 on page 21) is triggered with confirm command ‘36h’ instead ‘35h’, Copy Back Read from target page(s) will be
executed with an increased internal (VPASS) voltage.
This special feature is used in order to minimize the number of read errors due to over-program or read disturb — it shall be used
only if ECC read errors have occurred in the source page using Page Read or Copy Back Read sequences.
Excluding the Copy Back Read confirm command, all other features described in Section 3.7 and Section 3.7.1 for standard copy
back remain valid (including the figures referred to in those sections).
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S34ML01G2
S34ML02G2
S34ML04G2
3.8
Read Status Register
The Status Register is used to retrieve the status value for the last operation issued. After writing 70h command to the command
register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE# or RE#, whichever occurs
last. This two-line control allows the system to poll the progress of each device in multiple memory connections even when R/B#
pins are common-wired. Refer to Section 3.2 on page 23 for specific Status Register definition, and to Figure 6.22 on page 51 for
timings.
If the Read Status Register command is issued during multiplane operations then Status Register polling will return the combined
status value related to the outcome of the operation in the two planes according to the following table:
Status Register Bit
Bit 0, Pass/Fail
Composite Status Value
OR
OR
Bit 1, Cache Pass/Fail
In other words, the Status Register is dynamic; the user is not required to toggle RE# / CE# to update it.
The command register remains in Status Read mode until further commands are issued. Therefore, if the Status Register is read
during a random read cycle, the read command (00h) must be issued before starting read cycles.
Note: The Read Status Register command shall not be used for concurrent operations in multi-die stack configurations (single CE#).
“Read Status Enhanced” shall be used instead.
3.9
Read Status Enhanced — S34ML02G2 and S34ML04G2
Read Status Enhanced is used to retrieve the status value for a previous operation in the specified plane.
Figure 6.23 on page 52 defines the Read Status Enhanced behavior and timings. The plane and die address must be specified in
the command sequence in order to retrieve the status of the die and the plane of interest.
Refer to Table 3.2 for specific Status Register definitions. The command register remains in Status Read mode until further
commands are issued.
The Status Register is dynamic; the user is not required to toggle RE# / CE# to update it.
3.10 Read Status Register Field Definition
Table 3.2 below lists the meaning of each bit of the Read Status Register and Read Status Enhanced (S34ML02G2 and
S34ML04G2).
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Table 3.2 Status Register Coding
Page
Program /
Page
Cache
Program /
Cache
ID
Block Erase
Read
Read Cache
Coding
Reprogram
Reprogram
N Page
Pass: 0
Fail: 1
0
1
Pass / Fail
NA
Pass / Fail
NA
NA
NA
NA
NA
Pass / Fail
Pass / Fail
N - 1 Page
Pass: 0
Fail: 1
2
3
4
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
—
—
—
Internal Data Operation
Active: 0
5
Ready / Busy
Ready / Busy
Ready / Busy
Ready / Busy
Ready / Busy
Idle: 1
Ready / Busy
Busy: 0
Ready: 1
6
7
Ready / Busy
Write Protect
Ready / Busy
Write Protect
Ready / Busy
NA
Ready / Busy
NA
Ready / Busy
Write Protect
Protected: 0
Not Protected: 1
3.11 Reset
The Reset feature is executed by writing FFh to the command register. If the device is in the Busy state during random read,
program, or erase mode, the Reset operation will abort these operations. The contents of memory cells being altered are no longer
valid, as the data may be partially programmed or erased. The command register is cleared to wait for the next command, and the
Status Register is cleared to value E0h when WP# is high or value 60h when WP# is low. If the device is already in reset state a new
Reset command will not be accepted by the command register. The R/B# pin transitions to low for tRST after the Reset command is
written. Refer to Figure 6.24 on page 52 for further details. The Status Register can also be read to determine the status of a Reset
operation.
3.12 Read Cache
Read Cache can be used to increase the read operation speed, as defined in Section 3.1 on page 17, and it cannot cross a block
boundary. As soon as the user starts to read one page, the device automatically loads the next page into the cache register. Serial
data output may be executed while data in the memory is read into the cache register. Read Cache is initiated by the Page Read
sequence (00-30h) on a page M.
After random access to the first page is complete (R/B# returned to high, or Read Status Register I/O6 switches to high), two
command sequences can be used to continue read cache:
Read Cache (command ‘31h’ only): once the command is latched into the command register (see Figure 6.26 on page 53),
device goes busy for a short time (tCBSYR), during which data of the first page is transferred from the data register to the cache
register. At the end of this phase, the cache register data can be output by toggling RE# while the next page (page address M+1)
is read from the memory array into the data register.
Read Cache Enhanced (sequence ‘00h’ <page N address> ‘31’): once the command is latched into the command register (see
Figure 6.27 on page 54), device goes busy for a short time (tCBSYR), during which data of the first page is transferred from the
data register to the cache register. At the end of this phase, cache register data can be output by toggling RE# while page N is
read from the memory array into the data register.
Subsequent pages are read by issuing additional Read Cache or Read Cache Enhanced command sequences. If serial data output
time of one page exceeds random access time (tR), the random access time of the next page is hidden by data downloading of the
previous page.
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On the other hand, if 31h is issued prior to completing the random access to the next page, the device will stay busy as long as
needed to complete random access to this page, transfer its contents into the cache register, and trigger the random access to the
following page.
To terminate the Read Cache operation, 3Fh command should be issued (see Figure 6.28 on page 54). This command transfers
data from the data register to the cache register without issuing next page read.
During the Read Cache operation, the device doesn't allow any other command except for 00h, 31h, 3Fh, Read SR, or Reset (FFh).
To carry out other operations, Read Cache must be terminated by the Read Cache End command (3Fh) or the device must be reset
by issuing FFh.
Read Status command (70h) may be issued to check the status of the different registers and the busy/ready status of the cached
read operations.
The Cache-Busy status bit I/O6 indicates when the cache register is ready to output new data.
The status bit I/O5 can be used to determine when the cell reading of the current data register contents is complete.
Note: The Read Cache and Read Cache End commands reset the column counter, thus, when RE# is toggled to output the data of
a given page, the first output data is related to the first byte of the page (column address 00h). Random Data Output command can
be used to switch column address.
3.13 Cache Program
Cache Program can improve the program throughput by using the cache register. The Cache Program operation cannot cross a
block boundary. The cache register allows new data to be input while the previous data that was transferred to the data register is
programmed into the memory array.
After the serial data input command (80h) is loaded to the command register, followed by five cycles of address, a full or partial page
of data is latched into the cache register.
Once the cache write command (15h) is loaded to the command register, the data in the cache register is transferred into the data
register for cell programming. At this time the device remains in the Busy state for a short time (tCBSYW). After all data of the cache
register is transferred into the data register, the device returns to the Ready state and allows loading the next data into the cache
register through another Cache Program command sequence (80h-15h).
The Busy time following the first sequence 80h - 15h equals the time needed to transfer the data from the cache register to the data
register. Cell programming the data of the data register and loading of the next data into the cache register is consequently
processed through a pipeline model.
In case of any subsequent sequence 80h - 15h, transfer from the cache register to the data register is held off until cell programming
of current data register contents is complete; till this moment the device will stay in a busy state (tCBSYW).
Read Status commands (70h or 78h) may be issued to check the status of the different registers, and the pass/fail status of the
cached program operations.
The Cache-Busy status bit I/O6 indicates when the cache register is ready to accept new data.
The status bit I/O5 can be used to determine when the cell programming of the current data register contents is complete.
The Cache Program error bit I/O1 can be used to identify if the previous page (page N-1) has been successfully programmed or
not in a Cache Program operation. The status bit is valid upon I/O6 status bit changing to 1.
The error bit I/O0 is used to identify if any error has been detected by the program/erase controller while programming page N.
The status bit is valid upon I/O5 status bit changing to 1.
I/O1 may be read together with I/O0.
If the system monitors the progress of the operation only with R/B#, the last page of the target program sequence must be
programmed with Page Program Confirm command (10h). If the Cache Program command (15h) is used instead, the status bit I/O5
must be polled to find out if the last programming is finished before starting any other operation. See Table 3.2 on page 23 and
Figure 6.29 on page 55 for more details.
If a Cache Program operation is interrupted by hardware reset, power failure or other means, the host must ensure that the
interrupted pages are not used for further reading or programming operations until the next uninterrupted block erases are complete
for the applicable blocks.
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S34ML04G2
3.14 Multiplane Cache Program — S34ML02G2 and S34ML04G2
The Multiplane Cache Program enables high program throughput by programming two pages in parallel, while exploiting the data
and cache registers of both planes to implement cache.
The command sequence can be summarized as follows:
Serial Data Input command (80h), followed by the five cycle address inputs and then serial data for the 1st page. Address for this
page must be within 1st plane (PLA0 = 0). The data of 1st page other than those to be programmed do not need to be loaded. The
device supports Random Data Input exactly like Page Program operation.
The Dummy Page Program Confirm command (11h) stops 1st page data input and the device becomes busy for a short time
(tDBSY).
Once device returns to ready again, 81h command must be issued, followed by 2nd page address
(5 cycles) and its serial data input. Address for this page must be within 2nd plane (PLA0 = 1). The data of 2nd page other than
those to be programmed do not need to be loaded.
Cache Program confirm command (15h). Once the cache write command (15h) is loaded to the command register, the data in the
cache registers is transferred into the data registers for cell programming. At this time the device remains in the Busy state for a
short time (tCBSYW). After all data from the cache registers are transferred into the data registers, the device returns to the Ready
state, and allows loading the next data into the cache register through another Cache Program command sequence.
The sequence 80h-...- 11h...-...81h...-...15h can be iterated, and each time the device will be busy for the tCBSYW time needed to
complete programming the current data register contents, and transferring the new data from the cache registers. The sequence to
end Multiplane Cache Program is 80h-...- 11h...-...81h...-...10h.
The Multiplane Cache Program is available only within two paired blocks in separate planes. Figure 6.30 on page 56 shows the
legacy protocol for the Multiplane Cache Program operation. In this case, the block address bits for the first plane are all zero and
the second address issued selects the block for both planes. Figure 6.31 on page 57 shows the ONFI protocol for the Multiplane
Cache Program operation. For both addresses issued in this protocol, the block address bits must be the same except for the bit(s)
that select the plane.
The user can check operation status by R/B# pin or Read Status Register commands (70h or 78h). If the user opts for 70h, Read
Status Register will provide “global” information about the operation in the two planes.
I/O6 indicates when both cache registers are ready to accept new data.
I/O5 indicates when the cell programming of the current data registers is complete.
I/O1 identifies if the previous pages in both planes (pages N-1) have been successfully programmed or not. This status bit is valid
upon I/O6 status bit changing to 1.
I/O0 identifies if any error has been detected by the program/erase controller while programming the two pages N. This status bit
is valid upon I/O5 status bit changing to 1.
See Table 3.2 on page 23 for more details.
If the system monitors the progress of the operation only with R/B#, the last pages of the target program sequence must be
programmed with Page Program Confirm command (10h). If the Cache Program command (15h) is used instead, the status bit I/O5
must be polled to find out if the last programming is finished before starting any other operation. Refer to Section 3.8 on page 22 for
further information.
If a Multiplane Cache Program operation is interrupted by hardware reset, power failure or other means, the host must ensure that
the interrupted pages are not used for further reading or programming operations until the next uninterrupted block erases are
complete for the applicable blocks.
3.15 Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h.
Note: If you want to execute Read Status command (0x70) after Read ID sequence, you should input dummy command (0x00)
before Read Status command (0x70).
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S34ML01G2
S34ML02G2
S34ML04G2
For the S34ML02G2 and S34ML04G2 devices, five read cycles sequentially output the manufacturer code (01h), and the device
code and 3rd, 4th, and 5th cycle ID, respectively. For the S34ML01G2 device, four read cycles sequentially output the manufacturer
code (01h), and the device code and 80h, 4th cycle ID, respectively. The command register remains in Read ID mode until further
commands are issued to it. Figure 6.32 on page 58 shows the operation sequence, while Table 3.3 to Table 3.8 explain the byte
meaning.
Table 3.3 Read ID for Supported Configurations
Density
1 Gb
2 Gb
4 Gb
1 Gb
2 Gb
4 Gb
Org
V
1st
01h
01h
01h
01h
01h
01h
2nd
F1h
3rd
80h
90h
90h
80h
90h
90h
4th
1Dh
95h
95h
5Dh
D5h
D5h
5th
—
CC
×8
DAh
DCh
C1h
CAh
CCh
46h
56h
—
3.3V
×16
46h
56h
Table 3.4 Read ID Bytes
Device Identifier Byte
Description
1st
2nd
3rd
4th
Manufacturer Code
Device Identifier
Internal chip number, cell type, etc.
Page Size, Block Size, Spare Size, Serial Access Time, Organization
ECC, Multiplane information
5th (S34ML02G2, S34ML04G2)
3rd ID Data
Table 3.5 Read ID Byte 3 Description
Description
I/O7
I/O6
I/O5 I/O4
I/O3 I/O2
I/O1 I/O0
1
2
4
8
0 0
0 1
1 0
1 1
Internal Chip Number
2-level cell
4-level cell
8-level cell
16-level cell
0 0
0 1
1 0
1 1
Cell type
1
2
4
8
0 0
0 1
1 0
11
Number of simultaneously
programmed pages
Not supported
Supported
0
1
Interleave program
Between multiple chips
Not supported
Supported
0
1
Cache Program
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4th ID Data
Table 3.6 Read ID Byte 4 Description — S34ML01G2
Description
I/O7
I/O6
I/O5 I/O4
I/O3
I/O2
I/O1 I/O0
1 kB
2 kB
4 kB
8 kB
0 0
0 1
1 0
1 1
Page Size
(without spare area)
64 kB
128 kB
256 kB
512 kB
0 0
0 1
1 0
1 1
Block Size
(without spare area)
8
0
1
Spare Area Size
(byte / 512 byte)
16
45 ns
25 ns
0
0
1
1
0
1
0
1
Serial Access Time
Organization
Reserved
Reserved
×8
0
1
×16
Table 3.7 Read ID Byte 4 Description — S34ML02G2 and S34ML04G2
Description
I/O7
I/O6
I/O5 I/O4
I/O3
I/O2
I/O1 I/O0
1 kB
2 kB
4 kB
8 kB
0 0
0 1
1 0
1 1
Page Size
(without spare area)
64 kB
128 kB
256 kB
512 kB
0 0
0 1
1 0
1 1
Block Size
(without spare area)
16
32
0
1
Spare Area Size
(byte / 512 byte)
50 ns / 30 ns
25 ns
0
1
0
1
0
0
1
1
Serial Access Time
Organization
Reserved
Reserved
×8
0
1
×16
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5th ID Data
Table 3.8 Read ID Byte 5 Description — S34ML02G2 and S34ML04G2
Description
I/O7
I/O6 I/O5 I/O4
I/O3 I/O2
I/O1 I/O0
1 bit / 512 bytes
2 bit / 512 bytes
4 bit / 512 bytes
8 bit / 512 bytes
0 0
0 1
1 0
1 1
ECC Level
1
2
4
8
0 0
0 1
1 0
1 1
Plane Number
64 Mb
128 Mb
256 Mb
512 Mb
1 Gb
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
Plane Size
(without spare area)
2 Gb
4 Gb
Reserved
0
3.16 Read ID2
The device contains an alternate identification mode, initiated by writing 30h-65h-00h to the command register, followed by address
inputs, followed by command 30h. The address for S34ML01G2 will be
00h-02h-02h-00h. The address for S34ML02G2 and S34ML04G2 will be 00h-02h-02h-00h-00h. The ID2 data can then be read from
the device by pulsing RE#. The command register remains in Read ID2 mode until further commands are issued to it. Figure 6.33
on page 58 shows the Read ID2 command sequence. Read ID2 values are all 0xFs, unless specific values are requested when
ordering.
3.17 Read ONFI Signature
To retrieve the ONFI signature, the command 90h together with an address of 20h shall be entered (i.e. it is not valid to enter an
address of 00h and read 36 bytes to get the ONFI signature). The ONFI signature is the ASCII encoding of 'ONFI' where 'O' = 4Fh,
'N' = 4Eh, 'F' = 46h, and 'I' = 49h. Reading beyond four bytes yields indeterminate values. Figure 6.34 on page 59 shows the
operation sequence.
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S34ML02G2
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3.18 Read Parameter Page
The device supports the ONFI Read Parameter Page operation, initiated by writing ECh to the command register, followed by an
address input of 00h. The host may monitor the R/B# pin or wait for the maximum data transfer time (tR) before reading the
Parameter Page data. The command register remains in Parameter Page mode until further commands are issued to it. If the Status
Register is read to determine when the data is ready, the Read Command (00h) must be issued before starting read cycles.
Figure 6.35 on page 59 shows the operation sequence, while Table 3.9 explains the parameter fields.
For x16 devices, the upper eight I/Os are not used and are 0xFF.
Note: For 32 nm Cypress NAND, for a particular condition, the Read Parameter Page command does not give the correct values. To
overcome this issue, the host must issue a Reset command before the Read Parameter Page command. Issuance of Reset before
the Read Parameter Page command will provide the correct values and will not output 00h values.
Table 3.9 Parameter Page Description (Sheet 1 of 3)
Byte
0-3
O/M
M
Description
Values
4Fh, 4Eh, 46h, 49h
02h, 00h
Revision Information and Features Block
Parameter page signature
Byte 0: 4Fh, “O”
Byte 1: 4Eh, “N”
Byte 2: 46h, “F”
Byte 3: 49h, “I”
Revision number
2-15
Reserved (0)
4-5
M
1
0
1 = supports ONFI version 1.0
Reserved (0)
Features supported
S34ML01G200 (×8): 14h, 00h
S34ML02G200 (×8): 1Ch, 00h
S34ML04G200 (×8): 1Ch, 00h
S34ML01G204 (×16): 15h, 00h
S34ML02G204 (×16): 1Dh, 00h
S34ML04G204 (×16): 1Dh, 00h
5-15
Reserved (0)
4
3
2
1
0
1 = supports odd to even page Copyback
1 = supports interleaved operations
1 = supports non-sequential page programming
1 = supports multiple LUN operations
1 = supports 16-bit data bus width
6-7
8-9
M
M
Optional commands supported
6-15
Reserved (0)
5
4
3
2
1
0
1 = supports Read Unique ID (contact factory)
1 = supports Copyback
1 = supports Read Status Enhanced
1 = supports Get Features and Set Features
1 = supports Read Cache commands
1 = supports Page Cache Program command
S34ML01G2: 33h, 00h
S34ML02G2: 3Bh, 00h
S34ML04G2: 3Bh, 00h
10-31
32-43
Reserved (0)
00h
Manufacturer Information Block
53h, 50h, 41h, 4Eh, 53h, 49h,
4Fh, 4Eh, 20h, 20h, 20h, 20h
M
Device manufacturer (12 ASCII characters)
S34ML01G2: 53h, 33h, 34h,
4Dh, 4Ch, 30h, 31h, 47h, 32h,
20h, 20h, 20h, 20h, 20h, 20h,
20h, 20h, 20h, 20h, 20h
S34ML02G2: 53h, 33h, 34h,
4Dh, 4Ch, 30h, 32h, 47h, 32h,
20h, 20h, 20h, 20h, 20h, 20h,
20h, 20h, 20h, 20h, 20h
44-63
M
Device model (20 ASCII characters)
S34ML04G2: 53h, 33h, 34h,
4Dh, 4Ch, 30h, 34h, 47h, 32h,
20h, 20h, 20h, 20h, 20h, 20h,
20h, 20h, 20h, 20h, 20h
64
M
O
JEDEC manufacturer ID
Date code
01h
00h
00h
65-66
67-79
Reserved (0)
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Table 3.9 Parameter Page Description (Sheet 2 of 3)
Byte
O/M
Description
Values
Memory Organization Block
80-83
84-85
M
M
Number of data bytes per page
00h, 08h, 00h, 00h
S34ML01G2: 40h, 00h
S34ML02G2: 80h, 00h
S34ML04G2: 80h, 00h
Number of spare bytes per page
86-89
90-91
92-95
M
M
M
Number of data bytes per partial page
Number of spare bytes per partial page
Number of pages per block
00h, 00h, 00h, 00h
00h, 00h
40h, 00h, 00h, 00h
S34ML01G2: 00h, 04h, 00h, 00h
S34ML02G2: 00h, 08h, 00h, 00h
S34ML04G2: 00h, 10h, 00h, 00h
96-99
100
M
M
M
M
M
Number of blocks per logical unit (LUN)
Number of logical units (LUNs)
Number of address cycles
01h
S34ML01G2: 22h
S34ML02G2: 23h
S34ML04G2: 23h
101
4-7
0-3
Column address cycles
Row address cycles
102
Number of bits per cell
01h
S34ML01G2: 14h, 00h
S34ML02G2: 28h, 00h
S34ML04G2: 50h, 00h
103-104
Bad blocks maximum per LUN
105-106
107
M
M
M
M
Block endurance
01h, 05h
01h
Guaranteed valid blocks at beginning of target
Block endurance for guaranteed valid blocks
Number of programs per page
108-109
110
01h, 03h
04h
Partial programming attributes
5-7
4
Reserved
1 = partial page layout is partial page data followed by
partial page spare
111
M
00h
1-3
0
Reserved
1 = partial page programming has constraints
112
113
M
M
Number of bits ECC correctability
04h
S34ML01G2: 00h
S34ML02G2: 01h
S34ML04G2: 01h
Number of interleaved address bits
4-7
0-3
Reserved (0)
Number of interleaved address bits
Interleaved operation attributes
4-7
3
2
1
0
Reserved (0)
S34ML01G2: 00h
S34ML02G2: 04h
S34ML04G2: 04h
Address restrictions for program cache
1 = program cache supported
1 = no block address restrictions
Overlapped / concurrent interleaving support
114
O
115-127
128
Reserved (0)
00h
0Ah
Electrical Parameters Block
M
M
I/O pin capacitance
Timing mode support
6-15
Reserved (0)
5
4
3
2
1
0
1 = supports timing mode 5
1 = supports timing mode 4
1 = supports timing mode 3
1 = supports timing mode 2
1 = supports timing mode 1
1 = supports timing mode 0, shall be 1
129-130
1Fh, 00h
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Table 3.9 Parameter Page Description (Sheet 3 of 3)
Byte
O/M
Description
Values
Program cache timing mode support
6-15
Reserved (0)
5
4
3
2
1
0
1 = supports timing mode 5
1 = supports timing mode 4
1 = supports timing mode 3
1 = supports timing mode 2
1 = supports timing mode 1
1 = supports timing mode 0
131-132
O
1Fh, 00h
133-134
135-136
M
M
t
t
Maximum page program time (µs)
Maximum block erase time (µs)
BCh, 02h
10h, 27h
PROG
BERS
S34ML01G2: 19h, 00h
S34ML02G2: 1Eh, 00h
S34ML04G2: 1Eh, 00h
137-138
M
M
t
t
Maximum page read time (µs)
R
139-140
141-163
Minimum Change Column setup time (ns)
C8h, 00h
00h
CCS
Reserved (0)
Vendor Block
164-165
166-253
M
M
Vendor specific Revision number
Vendor specific
00h
00h
S34ML01G200 (×8): 68h, 4Eh
S34ML02G200 (×8): 56h, EAh
S34ML04G200 (×8): 28h, A1h
S34ML01G204 (×16): 1Ah, 38h
S34ML02G204 (×16): 24h, 9Ch
S34ML04G204 (×16): 5Ah, D7h
254-255
Integrity CRC
Redundant Parameter Pages
256-511
512-767
768+
M
M
O
Value of bytes 0-255
Value of bytes 0-255
Repeat Value of bytes 0-255
Repeat Value of bytes 0-255
FFh
Additional redundant parameter pages
Note:
1. O” Stands for Optional, “M” for Mandatory.
3.19 Read Unique ID (Contact Factory)
The device supports the ONFI Read Unique ID function, initiated by writing EDh to the command register, followed by an address
input of 00h. The host must monitor the R/B# pin or wait for the maximum data transfer time (tR) before reading the Unique ID data.
The first sixteen bytes returned by the flash is a unique value. The next sixteen bytes returned are the bit-wise complement of the
unique value. The host can verify the Unique ID was read correctly by performing an XOR of the two values. The result should be all
ones. The command register remains in Unique ID mode until further commands are issued to it. Figure 6.36 on page 60 shows the
operation sequence, while Table 3.10 shows the Unique ID data contents. Cypress guarantees unique id support feature with a
special model number shown in the OPN combination in Section 10., Ordering Information on page 69.
Note: For 32nm Cypress NAND, for a particular condition, the Read Unique ID command does not give the correct values. To
overcome this issue, the host must issue a Reset command before the Read Unique ID command. Issuance of Reset before the
Read Unique ID command will provide the correct values and will not output 00h values.
Table 3.10 Unique ID Data Description (Contact Factory) (Sheet 1 of 2)
Byte
0-15
Description
Unique ID
16-31
32-47
48-63
64-79
80-95
ID Complement
Unique ID
ID Complement
Unique ID
ID Complement
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Table 3.10 Unique ID Data Description (Contact Factory) (Sheet 2 of 2)
Byte
Description
Unique ID
96-111
112-127
128-143
144-159
160-175
176-191
192-207
208-223
224-239
240-255
256-271
272-287
288-303
304-319
320-335
336-351
352-367
368-383
384-399
400-415
416-431
432-447
448-463
464-479
480-495
496-511
ID Complement
Unique ID
ID Complement
Unique ID
ID Complement
Unique ID
ID Complement
Unique ID
ID Complement
Unique ID
ID Complement
Unique ID
ID Complement
Unique ID
ID Complement
Unique ID
ID Complement
Unique ID
ID Complement
Unique ID
ID Complement
Unique ID
ID Complement
Unique ID
ID Complement
Note:
1. For 32 nm NAND, for a particular condition, if read unique id does not give the correct values, the host must issue a Reset command before the read unique id
command. Issuance of Reset before the read unique id command will provide the correct values and will not output false values.
3.20 One-Time Programmable (OTP) Entry
The device contains a one-time programmable (OTP) area, which is accessed by writing 29h-17h-04h-19h to the command register.
The device is then ready to accept Page Read and Page Program commands (refer to Page Read and Page Program on page 17).
The OTP area is of a single erase block size (64 pages), and hence only row addresses between 00h and 3Fh are allowed. The host
must issue the Reset command (refer to Reset on page 23) to exit the OTP area and access the normal flash array. The Block Erase
command is not allowed in the OTP area. Refer to Figure 6.37 on page 60 for more detail on the OTP Entry command sequence.
4. Signal Descriptions
4.1
Data Protection and Power On / Off Sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever VCC is below about 1.8V.
The power-up and power-down sequence is shown in Figure 6.38 on page 61.
The Ready/Busy signal shall be valid within 100 µs after the power supplies have reached the minimum values (as specified on),
and shall return to one within 5 ms (max).
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During this busy time, the device executes the initialization process (cam reading), and dissipates a current ICC0 (30 mA max), in
addition, it disregards all commands excluding Read Status Register (70h).
At the end of this busy time, the device defaults into “read setup”, thus if the user decides to issue a page read command, the 00h
command may be skipped.
The WP# pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down. A recovery time
of minimum 100 µs is required before the internal circuit gets ready for any command sequences as shown in Figure 6.38
on page 61. The two-step command sequence for
program/erase provides additional software protection.
4.2
Ready/Busy
The Ready/Busy output provides a method of indicating the completion of a page program, erase, copyback, or read completion.
The R/B# pin is normally high and goes to low when the device is busy (after a reset, read, program, or erase operation). It returns to
high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B#
outputs to be Or-tied. Because the pull-up resistor value is related to tr (R/B#) and the current drain during busy (ibusy), and output
load capacitance is related to tf, an appropriate value can be obtained with the reference chart shown in Figure 4.1.
For example, for a particular system with 20 pF of output load, tf from VCC to VOL at 10% to 90% will be 10 ns, whereas for a
particular load of 50 pF, Cypress measured it to be 20 ns as shown in Figure 4.1.
Figure 4.1 Ready/Busy Pin Electrical Application
Rp
ibusy
V
CC
V
Ready
CC
R/B#
open drain output
V
OH
VOL : 0.4V, VOH : 2.4V
C
L
V
OL
Busy
t
t
f
r
GND
Device
Rp vs. tr, tf and Rp vs. ibusy
@
V = 3.3V, Ta = 25°C, CL=50 pF
CC
ibusy [A]
3m
300n
Legend
= tr (ns)
2.4
= ibusy (mA
= tf (ns)
)
200
200n
100n
2m
1m
150
0.8
20
1.2
100
50
0.6
20
20
20
tr,tf [s]
1k
2k
3k
4k
Rp (ohm)
Rp value guidence
Vcc (Max.) - VOL (Max.)
3.2V
Rp (min.) =
=
I
OL +∑I
L
8mA + ∑I
L
where IL is the sum of the input currents of all devices tied to the R/B# pin.
Rp(max) is determined by maximum permissible limit of tr.
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4.3
Write Protect Operation
Erase and program operations are aborted if WP# is driven low during busy time, and kept low for about
100 ns. Switching WP# low during this time is equivalent to issuing a Reset command (FFh). The contents of memory cells being
altered are no longer valid, as the data will be partially programmed or erased. The
R/B# pin will stay low for tRST (similarly to Figure 6.24 on page 52). At the end of this time, the command register is ready to process
the next command, and the Status Register bit I/O6 will be cleared to 1, while I/O7 value will be related to the WP# value. Refer to
Table 3.2 on page 23 for more information on device status.
Erase and program operations are enabled or disabled by setting WP# to high or low respectively, prior to issuing the setup
commands (80h or 60h). The level of WP# shall be set tWW ns prior to raising the WE# pin for the set up command, as explained in
Figure 6.39 and Figure 6.40 on page 61.
Figure 4.2 WP# Low Timing Requirements during Program/Erase Command Sequence
WE#
I/O[7:0]
WP#
Valid
Sequence
Aborted
> 100 ns
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5. Electrical Characteristics
5.1
Valid Blocks
Table 5.1 Valid Blocks
Device
Symbol
Min
1004
2008
4016
Typ
—
Max
1024
2048
4096
Unit
S34ML01G2
S34ML02G2
S34ML04G2
N
N
N
Blocks
Blocks
Blocks
VB
VB
VB
—
—
5.2
Absolute Maximum Ratings
Table 5.2 Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
°C
°C
°C
V
Ambient Operating Temperature (Industrial Temperature Range)
Temperature under Bias
T
-40 to +85
-50 to +125
-65 to +150
-0.6 to +4.6
-0.6 to +4.6
A
T
BIAS
Storage Temperature
T
STG
Input or Output Voltage
V
(2)
IO
Supply Voltage
V
V
CC
Notes:
1. Except for the rating “Operating Temperature Range”, stresses above those listed in the table Absolute Maximum Ratings “Absolute Maximum Ratings” may cause
permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating
sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
2. Minimum Voltage may undershoot to -2V during transition and for less than 20 ns during transitions.
3. Maximum Voltage may overshoot to V +2.0V during transition and for less than 20 ns during transitions.
CC
5.3
Recommended Operating Conditions
Table 5.3 Recommended Operating Conditions
Parameter
Symbol
Vcc
Min
2.7
0
Typ
3.3
0
Max
3.6
0
Units
Vcc Supply Voltage
V
V
Ground Supply Voltage
Vss
5.4
AC Test Conditions
Table 5.4 AC Test Conditions
Parameter
Value
0.0V to V
5 ns
Input Pulse Levels
CC
Input Rise and Fall Times
Input and Output Timing Levels
Output Load (2.7V - 3.6V)
V
/ 2
CC
1 TTL Gate and CL = 50 pF
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5.5
AC Characteristics
Table 5.5 AC Characteristics
Parameter
Symbol
Min
10
5
Max
—
—
—
—
—
—
30
—
—
—
25
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ALE to RE# delay
ALE hold time
t
AR
t
ALH
ALE setup time
t
10
70
10
5
ALS
ADL
Address to data loading time
CE# low to RE# low
CE# hold time
t
t
CR
t
CH
CE# high to output High-Z
CLE hold time
t
—
5
CHZ
t
t
CLH
CLR
CLE to RE# delay
CLE setup time
10
10
—
15
10
20
5
t
CLS
CE# access time
t
(4)
(3)
CEA
COH
CE# high to output hold
CE# high to ALE or CLE don't care
CE# setup time
t
t
CSD
t
CS
Data hold time
t
DH
Data setup time
t
10
DS
Data transfer from cell to register
(S34ML01G2)
t
t
—
—
25
30
µs
µs
R
R
Data transfer from cell to register (S34ML02G2,
S34ML04G2)
Output High-Z to RE# low
Read cycle time
t
0
25
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
IR
t
RC
RE# access time
t
20
REA
REH
RE# high hold time
t
10
15
100
—
—
RE# high to output hold
RE# high to WE# low
RE# high to output High-Z
RE# low to output hold
RE# pulse width
t
(3)
—
RHOH
t
—
RHW
t
100
—
RHZ
t
5
RLOH
t
12
20
—
—
RP
RR
Ready to RE# low
t
—
Device resetting time (Read/Program/Erase)
WE# high to busy
t
5/10/500
100
—
RST
t
—
WB
WC
WH
Write cycle time
t
t
25
10
60
200
12
100
WE# high hold time
—
WE# high to RE# low
WE# high to RE# low for Random Data Output
WE# pulse width
t
—
WHR
t
—
WHR2
t
—
WP
Write protect time
t
—
WW
Notes:
1. The time to Ready depends on the value of the pull-up resistor tied to R/B# pin.
2. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5 µs.
3. CE# low to high or RE# low to high can be at different times and produce three cases. Depending on which signal comes high first, either t
or t
will be met.
COH
RHOH
4. During data output, t
depends partly on t (CE# low to RE# low). If t exceeds the minimum value specified, then the maximum time for t
may also be
CEA
CR
CR
CEA
exceeded (t
= t + t
).
CEA
CR
REA
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5.6
DC Characteristics
Table 5.6 DC Characteristics and Operating Conditions
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
FFh command input
after power on
50 per
device
Power On Current
Operating Current
I
I
—
—
mA
CC0
CC1
t
= t (min)
RC
RC
Sequential Read
—
15
30
mA
CE# = V , Iout = 0 mA
IL
Normal
Cache
—
—
—
—
15
15
15
30
30
30
mA
mA
mA
Program
Erase
I
I
I
CC2
CC3
CC4
CE#=V
,
IH
Standby Current, (TTL)
—
—
—
1
mA
µA
WP#=0V/Vcc
CE# = V -0.2,
CC
Standby Current, (CMOS)
I
10
50
CC5
WP# = 0/V
CC
Input Leakage Current
Output Leakage Current
Input High Voltage
I
V
= 0 to V (max)
—
—
—
—
—
—
—
—
10
1.8
±10
±10
µA
µA
V
LI
IN
CC
I
V
= 0 to V (max)
LO
OUT CC
V
—
—
V
x 0.8
V
+ 0.3
CC
IH
CC
Input Low Voltage
V
-0.3
2.4
—
V
x 0.2
CC
V
IL
Output High Voltage
Output Low Voltage
Output Low Current (R/B#)
V
I
= -400 µA
= 2.1 mA
OL
—
V
OH
OH
V
I
0.4
—
V
OL
OL(R/B#)
I
V
= 0.4V
—
8
mA
V
OL
Erase and Program Lockout Voltage
V
—
—
LKO
Notes:
1. All V pins, and V pins respectively, are shorted together.
CC
SS
2. Values listed in this table refer to the complete voltage range for V and to a single device in case of device stacking.
CC
3. All current measurements are performed with a 0.1 µF capacitor connected between the V Supply Voltage pin and the V Ground pin.
CC
SS
4. Standby current measurement can be performed after the device has completed the initialization process at power up. Refer to Section 4.1 for more details.
5.7
Pin Capacitance
Table 5.7 Pin Capacitance (TA = 25°C, f=1.0 MHz)
Parameter
Symbol
Test Condition
Min
—
Max
10
Unit
pF
Input
C
V
= 0V
= 0V
IN
IO
IN
Input / Output
C
V
—
10
pF
IL
Note:
1. For the stacked devices version the Input is 10 pF x [number of stacked chips] and the Input/Output is 10 pF x [number of stacked chips].
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5.8
Program / Erase Characteristics
Table 5.8 Program / Erase Characteristics
Parameter
Description
Min
—
—
—
—
—
—
—
—
Typ
300
0.5
5
Max
700
1
Unit
µs
Program Time / Multiplane Program Time (2)
t
PROG
Dummy Busy Time for Multiplane Program (S34ML02G2, S34ML04G2)
Cache Program short busy time
t
µs
DBSY
t
t
µs
CBSYW
PROG
Number of partial Program Cycles in the same page
Block Erase Time / Multiplane Erase Time (S34ML02G2, S34ML04G2)
Block Erase Time (S34ML01G2)
Main + Spare
NOP
—
3.5
3
4
Cycle
ms
ms
µs
t
t
10
10
BERS
BERS
Read Cache busy time (S34ML01G2)
t
3
t
t
CBSYR
CBSYR
R
R
Read Cache busy time (S34ML02G2, S34ML04G2)
t
5
µs
Notes:
1. Typical program time is defined as the time within which more than 50% of the whole pages are programmed (V = 3.3V, 25°C).
CC
2. Copy Back Read and Copy Back Program for a given plane must be between odd address pages or between even address pages for the device to meet the program
time (t ) specification. Copy Back Program may not meet this specification when copying from an odd address page (source page) to an even address page
PROG
(target page) or from an even address page (source page) to an odd address page (target page).
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S34ML01G2
S34ML02G2
S34ML04G2
6. Timing Diagrams
6.1
Command Latch Cycle
Command Input bus operation is used to give a command to the memory device. Commands are accepted with Chip Enable low,
Command Latch Enable High, Address Latch Enable low, and Read Enable High and latched on the rising edge of Write Enable.
Moreover for commands that starts a modify operation
(write/ erase) the Write Protect pin must be high.
Figure 6.1 Command Latch Cycle
tCL
S
tCLH
tCH
CLE
CE#
tCS
tWP
WE#
tALS
tALH
ALE
I/Ox
tDS
tDH
Command
= Don’t Care
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6.2
Address Latch Cycle
Address Input bus operation allows the insertion of the memory address. To insert the 27 (×8 Device) addresses needed to access
the 1 Gb, four write cycles are needed. Addresses are accepted with Chip Enable low, Address Latch Enable High, Command Latch
Enable low, and Read Enable High and latched on the rising edge of Write Enable. Moreover, for commands that start a modify
operation (write/ erase) the Write Protect pin must be high.
Figure 6.2 Address Latch Cycle
tCLS
CLE
tCS
tWC
tWC
tWC
tWC
CE#
tWP
tWP
tWP
tWP
WE#
ALE
tWH
tWH
tWH
tWH
tALH
tALS
tALS tALH
tALS tALH
tALS tALH
tALS tALH
tDH
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDS
Col.
Add2
Col.
Add1
Row.
Add1
Row.
Add2
Row.
Add3
I/Ox
= Don’t Care
6.3
Data Input Cycle Timing
Data Input bus operation allows the data to be programmed to be sent to the device. The data insertion is serially, and timed by the
Write Enable cycles. Data is accepted only with Chip Enable low, Address Latch Enable low, Command Latch Enable low, Read
Enable High, and Write Protect High and latched on the rising edge of Write Enable.
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Figure 6.3 Input Data Latch Cycle
tCLH
CLE
CE#
ALE
tCH
tWC
tALS
tWP
tWP
tWP
WE#
I/Ox
tWH
tDH
tWH
tDH
tDH
tDS
Din
tDS
tDS
Din final
Din 0
= Don’t Care
6.4
Data Output Cycle Timing (CLE=L, WE#=H, ALE=L, WP#=H)
Figure 6.4 Data Output Cycle Timing
tRC
tCHZ
CE#
tREH
tREA
tREA
tREA
tCOH
tRHZ
RE#
tRHZ
tRHOH
I/Ox
Dout
Dout
Dout
tRR
R/B#
Notes:
1. Transition is measured at ± 200 mV from steady state voltage with load.
2. This parameter is sampled and not 100% tested.
3.
t
starts to be valid when frequency is lower than 33 MHz.
RHOH
Document Number: 002-00499 Rev. *N
Page 41 of 76
S34ML01G2
S34ML02G2
S34ML04G2
6.5
Data Output Cycle Timing (EDO Type, CLE=L, WE#=H, ALE=L)
Figure 6.5 Data Output Cycle Timing (EDO)
tCR
CE#
tRC
tCHZ
tCOH
RE#
tRP
tREH
tRHZ
tREA
tREA
tRLOH
tRHOH
I/Ox
Dout
Dout
tRR
R/B#
= Don’t Care
Notes:
1. Transition is measured at ± 200 mV from steady state voltage with load.
2. This parameter is sampled and not 100% tested.
3.
4.
t
t
is valid when frequency is higher than 33 MHz.
RLOH
RHOH
starts to be valid when frequency is lower than 33 MHz.
6.6
Page Read Operation
Figure 6.6 Page Read Operation (Read One Page)
CLE
tCLR
CE#
WE#
ALE
RE#
tWC
tCSD
tWB
tAR
tR
tRC
tRHZ
tRR
Col.
Add. 2
Row
Add. 2
Dout
N +1
Row
Add. 3
Dout
M
Col.
Add. 1
Row
Add. 1
00h
30h
Dout N
I/Ox
Column Address
Row Address
R/B#
= Don’t Care
Busy
Note:
1. If Status Register polling is used to determine completion of the read operation, the Read Command (00h) must be issued before data can be read from the page
buffer.
Document Number: 002-00499 Rev. *N
Page 42 of 76
S34ML01G2
S34ML02G2
S34ML04G2
6.7
Page Read Operation (Interrupted by CE#)
Figure 6.7 Page Read Operation Interrupted by CE#
CLE
tCLR
CE#
WE#
ALE
RE#
I/Ox
tCSD
tCHZ
tCOH
tWB
tAR
tRC
tR
tRR
Dout
N +1
Dout
N +2
Col.
Add. 2
Row
Add. 2
Row
Add. 3
Col.
Add. 1
Row
Add. 1
00h
Dout N
30h
Column Address
Row Address
R/B#
Busy
= Don’t Care
Document Number: 002-00499 Rev. *N
Page 43 of 76
S34ML01G2
S34ML02G2
S34ML04G2
6.8
Page Read Operation Timing with CE# Don’t Care
Figure 6.8 Page Read Operation Timing with CE# Don’t Care
CE# don’t care
CE#
CLE
ALE
WE#
tRC
RE#
tRR
Dout
N
Dout
N + 1
Dout
Dout
M
Dout
M + 1
Col.
Col.
Row
Row
Row
Add. 1 Add. 2 Add. 1 Add. 2 Add. 3
Dout
N + 2
Dout
Dout
N + 5
Dout
M + 2
00h
30h
I/Ox
N + 3 N + 4
tR
R/B#
= Don’t Care (V or V
IH
)
IL
tCR
CE#
tREA
RE#
I/Ox
Dout
6.9
Page Program Operation
Figure 6.9 Page Program Operation
CLE
CE#
tWC
tWC
tWC
WE#
ALE
RE#
I/Ox
tADL
tWHR
tWB
tPROG
Col.
Add2
Row.
Add3
Col.
Add1
Row.
Add2
Row.
Add1
Din
Din
M
80h
10h
70h
I/O0
N
Serial Data
Input Command
1 up to m byte
Serial Input
Program
Command
Read Status
Command
Column Address
Row Address
R/B#
I/O0=0 Successful Program
I/O0=1 Error in Program
= Don’t Care
Note:
1.
t
is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.
ADL
Document Number: 002-00499 Rev. *N
Page 44 of 76
S34ML01G2
S34ML02G2
S34ML04G2
6.10 Page Program Operation Timing with CE# Don’t Care
Figure 6.10 Page Program Operation Timing with CE# Don’t Care
CE# don’t care
CE#
CLE
ALE
WE#
RE#
Din
M
Din
P
Din
P + 1
Din
R
Col.
Add. 1
Col.
Row
Row
Row
Din
N
Din
N + 1
80h
I/Ox
10h
Add. 2 Add. 1 Add. 2 Add. 3
= Don’t Care
tCH
tCS
tWP
CE#
WE#
6.11 Page Program Operation with Random Data Input
Figure 6.11 Random Data Input
CLE
CE#
tWC
tWC
tWC
WE#
ALE
tADL
tADL
tWHR
tWB
tPROG
RE#
I/Ox
Col.
Add1
Col.
Add2
Col.
Add1
Col.
Add2
Row
Add1
Row
Add2
Row
Add3
Din
M
Din
Din
Din
K
85h
10h
80h
70h
IO0
J
N
Read Status
Command
Serial Data
Input Command
Random Data
Input Command
Program
Command
Column Address
Column Address
Row Address
Serial Input
R/B#
= Don’t Care
Note:
1.
t
is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.
ADL
Document Number: 002-00499 Rev. *N
Page 45 of 76
S34ML01G2
S34ML02G2
S34ML04G2
6.12 Random Data Output In a Page
Figure 6.12 Random Data Output
CLE
tCLR
CE#
WE#
tWB
tWHR2
tAR
tRHW
ALE
RE#
tRC
tR
tREA
tRR
Dout
N +1
Dout
M +1
Col.
Add. 2
Row
Add. 2
Row
Add. 3
Col.
Add. 2
Col.
Add. 1
Row
Add. 1
Col.
Add. 1
00h
05h
Dout N
E0h
Dout M
30h
I/Ox
Row Address
Column Address
Column Address
R/B#
= Don’t Care
Busy
6.13 Multiplane Page Program Operation — S34ML02G2 and S34ML04G2
Figure 6.13 Multiplane Page Program
CLE
CE#
tWC
WE#
tDBSY
tWB
tWB
tPROG
tWHR
ALE
RE#
I/Ox
tADL
tADL
Row
Row
Row
Col.
Col.
Col.
Row
Col.
Din
Din
Row
Din
N
Din
Row
81h
80h
11h
Program
Command
(Dummy)
10h
IO
70h
Add1
Add3
Add2
Add1
M
Add1
M
Add2 Add1
Add2
N
Add2
Add3
1 up to full page
Serial Data
Program Confirm
Read Staus
Command
Column Address
Page Row Address
Data Serial Input
Input Command
Command (True)
R/B#
Ex.) Address Restriction for Multiplane Page Program
tDBSY
tPROG
R/B#
I/O0~7
Address & Data Input
10h
80h
Address & Data Input
11h
81h
70h
Col Add 1,2 and Row Add 1,2,3
and Data
Col Add 1,2 and Row Add 1,2,3
and Data
(Note 1)
A0 ~ A11: Valid
A0 ~ A11: Valid
A12 ~ A17: Valid
A18: Fixed ‘High’
A19 ~ A28: Valid
A12 ~ A17: Fixed ‘Low’
A18: Fixed ‘Low’
A19 ~ A28: Fixed ‘Low’
Notes:
1. Any command between 11h and 81h is prohibited except 70h, 78h, and FFh.
2. A18 is the plane address bit for ×8 devices. A17 is the plane address bit for ×16 devices.
Document Number: 002-00499 Rev. *N
Page 46 of 76
S34ML01G2
S34ML02G2
S34ML04G2
Figure 6.14 Multiplane Page Program (ONFI 1.0 Protocol)
ADDR ADDR ADDR
Cycle Type
ADDR ADDR
DIN
...
CMD
11h
CMD
80h
DIN
D0A
DIN
D1A
DIN
DnA
tADL
C1A
C2A
R2A
R3A
DQx
R1A
tADL
tIPBSY
SR[6]
A
Cycle Type
DQx
DIN
...
ADDR ADDR ADDR
DIN
D0B
DIN
D1B
DIN
DnB
CMD
10h
CMD
80h
ADDR ADDR
tADL
C1B
C2B
R1B
R2B
R3B
tADL
tPROG
SR[6]
Notes:
1. C1A-C2A Column address for page A. C1A is the least significant byte.
2. R1A-R3A Row address for page A. R1A is the least significant byte.
3. D0A-DnA Data to program for page A.
4. C1B-C2B Column address for page B. C1B is the least significant byte.
5. R1B-R3B Row address for page B. R1B is the least significant byte.
6. D0B-DnB Data to program for page B.
7. The block address bits must be the same except for the bit(s) that select the plane.
6.14 Block Erase Operation
Figure 6.15 Block Erase Operation (Erase One Block)
CLE
CE#
WE#
tWC
tWHR
tBERS
tWB
ALE
RE#
70h
Row Add1 Row Add2
Row Address
Row Add3
D0h
I/O0
60h
I/Ox
BUSY
R/B#
Auto Block Erase
Setup Command
I/O0=0 Successful Erase
I/O0=1 Error in Erase
Erase Command
Read Status
Command
= Don’t Care
Document Number: 002-00499 Rev. *N
Page 47 of 76
S34ML01G2
S34ML02G2
S34ML04G2
6.15 Multiplane Block Erase — S34ML02G2 and S34ML04G2
Figure 6.16 Multiplane Block Erase
CLE
CE#
tWC
tWC
WE#
ALE
tWHR
tWB
tBERS
RE#
I/Ox
60h Row Add1 Row Add2
D0h
Row Add3
Row Add3
I/O0
60h
Row Add1 Row Add2
70h
Row Address
Row Address
Busy
R/B#
Block Erase Setup Command1
Block Erase Setup Command2
Erase Confirm Command
Read Status Command
I/O 1 = 0 Successful Erase
I/O 1 = 1 Error in plane
Ex.) Address Restriction for Multiplane Block Erase Operation
R/B#
tBERS
I/O0~7
Address
Row Add1,2,3
Address
60h
60h
D0h
70h
Row Add1,2,3
A12 ~ A17 : Fixed ‘Low’
A12 ~ A17 : Fixed ‘Low’
A18
: Fixed ‘Low’
A18
: Fixed ‘High’
A19 ~ A28 : Fixed ‘Low’
A19 ~ A28 : Valid
Note:
1. A18 is the plane address bit for ×8 devices. A17 is the plane address bit for ×16 devices.
Figure 6.17 Multiplane Block Erase (ONFI 1.0 Protocol)
CLE
WE#
ALE
RE#
IOx
R2B R3B
R1A
R1B
D0h
60h
R2A R3A
60h
D1h
t
IEBSY
t
BERS
SR[6]
Notes:
1. R1A-R3A Row address for block on plane 0. R1A is the least significant byte.
2. R1B-R3B Row address for block on plane 1. R1B is the least significant byte.
3. The block address bits must be the same except for the bit(s) that select the plane.
Document Number: 002-00499 Rev. *N
Page 48 of 76
S34ML01G2
S34ML02G2
S34ML04G2
6.16 Copy Back Read with Optional Data Readout
Figure 6.18 Copy Back Read with Optional Data Readout
Source
Add Inputs
Target
Add Inputs
SR0
Read Status Register
10h
00h
35h
Data Outputs
85h
70h
I/O
tR
(Read Busy time)
tPROG
(Program Busy time)
R/B#
Busy
Busy
6.17 Copy Back Program Operation With Random Data Input
Figure 6.19 Copy Back Program with Random Data Input
Source
Add Inputs
Target
Add Inputs
2 Cycle
Add Inputs
85h
10h
70h
Read Status Register
I/O
00h
35h
85h
SR0
Data
Data
Unlimited number of repetitions
tR
(Read Busy time)
tPROG
(Program Busy time)
R/B#
Busy
Busy
Document Number: 002-00499 Rev. *N
Page 49 of 76
S34ML01G2
S34ML02G2
S34ML04G2
6.18 Multiplane Copy Back Program — S34ML02G2 and S34ML04G2
Figure 6.20 Multiplane Copy Back Program
tR
tR
R/B#
I/Ox
35h
35h
00h
00h
Add. (5 cycles)
Add. (5 cycles)
Col. Add. 1, 2 and Row Add. 1, 2, 3
Source Address on Plane 0
Col. Add. 1, 2 and Row Add. 1, 2, 3
Source Address on Plane 1
1
tDBSY
tPROG
R/B#
I/Ox
85h
Add. (5 cycles)
81h
Add. (5 cycles)
10h
11h
70h
(Note 2)
Col. Add. 1, 2 and Row Add. 1, 2, 3
Destination Address
Col. Add. 1, 2 and Row Add. 1, 2, 3
Destination Address
1
A0 ~ A11 : Fixed ‘Low’
A12 ~ A17 : Fixed ‘Low’
A0 ~ A11 : Fixed ‘Low’
A12 ~ A17 : Valid
A18
: Fixed ‘Low’
A18
: Fixed ‘High’
A19 ~ A28 : Fixed ‘Low’
A19 ~ A28 : Valid
Plane 0
Plane 1
Source Page
Source Page
Target Page
(1) : Copy Back Read on Plane 0
(2) : Copy Back Read on Plane 1
(3) : Multiplane Copy Back Program
Target Page
(1)
(2)
(3)
(3)
Data Field
Data Field
Spare Field
Spare Field
Notes:
1. Copy Back Program operation is allowed only within the same memory plane.
2. Any command between 11h and 81h is prohibited except 70h, 78h, and FFh.
3. A18 is the plane address bit for ×8 devices. A17 is the plane address bit for ×16 devices.
Document Number: 002-00499 Rev. *N
Page 50 of 76
S34ML01G2
S34ML02G2
S34ML04G2
Figure 6.21 Multiplane Copy Back Program (ONFI 1.0 Protocol)
CLE
WE#
ALE
RE#
IOx
C2B
C1B
85h
C2A R1A
R3A
85h
R1B
C1A
R2A
11h
R2B
R3B 10h
t
t
IPBSY
PROG
SR[6]
A
Notes:
1. C1A-C2A Column address for page A. C1A is the least significant byte.
2. R1A-R3A Row address for page A. R1A is the least significant byte.
3. C1B-C2B Column address for page B. C1B is the least significant byte.
4. R1B-R3B Row address for page B. R1B is the least significant byte.
5. The block address bits must be the same except for the bit(s) that select the plane.
6.19 Read Status Register Timing
Figure 6.22 Read Status Cycle
tCLR
CLE
CE#
tCLS
tCLH
tCS
tCH
tWP
WE#
tCEA
tCHZ
tCOH
tWHR
RE#
I/Ox
tRHZ
tDH
tREA
tDS
70h
tIR
tRHOH
Status Output
= Don’t Care
Document Number: 002-00499 Rev. *N
Page 51 of 76
S34ML01G2
S34ML02G2
S34ML04G2
6.20 Read Status Enhanced Timing
Figure 6.23 Read Status Enhanced Timing
CLE
WE#
ALE
tWHR
RE#
tAR
I/O0-7
R3
R1
R2
SR
78h
6.21 Reset Operation Timing
Figure 6.24 Reset Operation Timing
WE#
ALE
CLE
RE#
FF
I/O7:0
R/B#
t
RST
Document Number: 002-00499 Rev. *N
Page 52 of 76
S34ML01G2
S34ML02G2
S34ML04G2
6.22 Read Cache
Figure 6.25 Read Cache Operation Timing
A
CE#
CLE
tWC
ALE
WE#
tWB
tWB
tWB
tRC
tRC
RE#
tRR
tRR
Col.
Add 1
Col.
Add 2
Row
Add 1
Row
Add 2
Row
Add 3
Dout
1
Dout
1
Dout
0
Dout
0
00h
30h
31h
31h
Dout
I/Ox
Page N + 1
Col. Add. 0
Page N
Column Address 00h
Page Address N
Col. Add. 0
tCBSYR
tCBSYR
tR
R/B#
5
1
2
3
4
A
CE#
CLE
ALE
WE#
tWB
tWB
tRC
tRC
RE#
I/Ox
tRR
tRR
Dout
1
Dout
1
Dout
0
Dout
0
Dout
Dout
3Fh
Dout
31h
Page N + 2
Page N + 3
Col. Add. 0
Col. Add. 0
tCBSYR
tCBSYR
R/B#
5
6
7
8
9
= Don’t Care
Page N
Page N + 1
Page N + 2
Page N + 3
Data Cache
Page Buffer
8
2
4
9
1
6
3
5
7
Page N + 3
Page N + 1
Page N + 2
Page N + 2
Page N
3
5
1
7
Cell Array
Page N
Page N + 1
Page N + 3
Figure 6.26 “Sequential” Read Cache Timing, Start (and Continuation) of Cache Operation
As defined for
Read
CMD
31h
Cycle Type
Dout
Dn
Dout
D0
CMD
Dout
D0
Dout
...
CMD
31h
30h
I/Ox
tWB
tWB
tWB
tRR
tRR
tCBSYR
tR
tCBSYR
SR[6]
Document Number: 002-00499 Rev. *N
Page 53 of 76
S34ML01G2
S34ML02G2
S34ML04G2
Figure 6.27 “Random” Read Cache Timing, Start (and Continuation) of Cache Operation
As defined
for Read
A
Dout
D0
Dout
CMD
30h
ADDR ADDR ADDR
ADDR
R3
Dout
CMD
00h
CMD
31h
ADDR
C1
Cycle Type
Page N
C2
R1
R2
. . .
Dn
I/Ox
tRR
tR
tRR
tWB
tWB
SR[6]
tCBSYR
A
ADDR ADDR ADDR
Dout
D0
CMD
ADDR
R3
CMD
31h
ADDR
C1
Cycle Type
Page R
C2
R1
R2
00h
I/Ox
tRR
tCBSYR
tWB
SR[6]
Figure 6.28 Read Cache Timing, End Of Cache Operation
As defined for
Read Cache
(Sequential or Random)
Dout
Dn
CMD
3Fh
Dout
D0
CMD
Dout
Dout
D0
Dout
Dout
Cycle Type
31h
. . .
. . .
Dn
I/Ox
tRR
tRR
tCBSYR
tWB
tWB
tCBSYR
SR[6]
Document Number: 002-00499 Rev. *N
Page 54 of 76
S34ML01G2
S34ML02G2
S34ML04G2
6.23 Cache Program
Figure 6.29 Cache Program
CLE
CE#
tWC
tWC
WE#
ALE
tWB
RE#
Col.
Add1
Col.
Add1
Col.
Add2 Add1
Row.
Row.
Add2 Add3
Row.
Col.
Add2 Add1
Row.
Row.
Add2 Add3
Row.
Din
N
Din
M
Din
N
Din
M
80h
15h
15h
80h
I/Ox
Column Address
Row Address
Row Address
Column Address
R/B#
tCBSYW
tCBSYW
1
CLE
CE#
tWC
WE#
ALE
RE#
I/Ox
tADL
Col.
Add1 Add2
Col.
Row.
Add2
Row.
Add3
Row.
Add1
Din
Din
70h
Status
10h
80h
N
M
Column Address
Row Address
R/B#
1
tPROG
Document Number: 002-00499 Rev. *N
Page 55 of 76
S34ML01G2
S34ML02G2
S34ML04G2
6.24 Multiplane Cache Program — S34ML02G2 and S34ML04G2
Figure 6.30 Multiplane Cache Program
Command Input
11h
Address Input
Data Input
81h
Address Input
Data Input
15h
80h
A13~A17: Fixed ‘Low’
A18: Fixed ‘Low’
A19~A31: Fixed ‘Low’
A13~A17: Valid
A18: Fixed ‘High’
A19~A31: Valid
t
t
CBSYW
DBSY
RY/BY#
1
Return to 1
Repeat a max of 63 times
Command Input
80h
11h
Address Input
Data Input
81h
Address Input
Data Input
10h
A13~A17: Fixed ‘Low’
A18: Fixed ‘Low’
A19~A31: Fixed ‘Low’
A13~A17: Valid
A18: Fixed ‘High’
A19~A31: Valid
t
t
PROG
DBSY
RY/BY#
1
CLE
CE#
tWC
tWB
WE#
ALE
tWB
RE#
I/Ox
tADL
tADL
Din
N
Din
M
Din
N
Din
M
Col.
Col.
Row
Row
Row
Col.
Add1
Col.
Row
Row
Row
80h
11h
15h
81h
Add1
Add2
Add1
Add2
Add3
Add2
Add1
Add2
Add3
Column Address
Row Address
Row Address
Column Address
R/B#
1
tDBSY
tCBSYW
CLE
CE#
tWC
tWB
WE#
ALE
RE#
I/Ox
Col.
Add1
Col.
Row
Row
Row
Col.
Col.
Row
Row
Row
Din
N
Din
M
Din
N
Din
M
80h
81h
11h
10h
Status
70h
Add2
Add1
Add2
Add3
Add1
Add2
Add1
Add2
Add3
Column Address
Row Address
Row Address
Column Address
R/B#
1
tPROG
tDBSY
Notes:
1. Read Status Register (70h) is used in the figure. Read Status Enhanced (78h) can be also used.
2. A18 is the plane address bit for ×8 devices. A17 is the plane address bit for ×16 devices.
Document Number: 002-00499 Rev. *N
Page 56 of 76
S34ML01G2
S34ML02G2
S34ML04G2
Figure 6.31 Multiplane Cache Program (ONFI 1.0 Protocol)
Command Input
80h
11h
Address Input
Data Input
80h
Address Input
Data Input
15h
t
t
CBSYW
DBSY
RY/BY#
RY/BY#
1
Return to 1
Repeat a max of 63 times
Command Input
11h
80h
Address Input
Data Input
10h
Address Input
Data Input
80h
t
t
PROG
DBSY
1
CLE
CE#
tWC
tWB
WE#
ALE
tWB
RE#
IOx
tADL
tADL
Din
Din
M
Din
N
Din
M
Col.
Add1
Col.
Row
Row
Row
Col.
Add1
Col.
Row
Row
Row
80h
11h
15h
80h
N
Add2
Add1
Add2
Add3
Add2
Add1
Add2
Add3
Column Address
Row Address
Row Address
Column Address
R/B#
1
tDBSY
tCBSYW
CLE
CE#
tWC
tWB
WE#
ALE
RE#
IOx
Col.
Col.
Row
Row
Row
Din
Din
Din
N
Din
M
Col.
Add1
Col.
Row
Row
Row
80h
80h
11h
10h
Status
70h
Add1
Add2
Add1
Add2
Add3
N
M
Add2
Add1
Add2
Add3
Column Address
Row Address
Row Address
Column Address
R/B#
1
tPROG
tDBSY
Notes:
1. The block address bits must be the same except for the bit(s) that select the plane.
2. Read Status register (70h) is used in the figure. Read Status Enhanced (78h) can be also used.
Document Number: 002-00499 Rev. *N
Page 57 of 76
S34ML01G2
S34ML02G2
S34ML04G2
6.25 Read ID Operation Timing
Figure 6.32 Read ID Operation Timing
CLE
CE#
WE#
tWHR
tAR
ALE
RE#
tREA
1 Gb Device
90h
90h
00h
00h
00h
01h
01h
01h
F1h
DAh
DCh
80h
90h
1Dh
95h
I/Ox
2 Gb Device
4 Gb Device
46h
I/Ox
I/Ox
90h
90h
95h
56h
Read ID
Command
Address 1
Cycle
Maker
Code
Device
Code
3rd Cycle
4th Cycle
5th Cycle
6.26 Read ID2 Operation Timing
Figure 6.33 Read ID2 Operation Timing
CLE
CE#
WE#
tR
ALE
RE#
I/Ox
30h 65h 00h 00h
ID2 Data
ID2 Data
ID2 Data
ID2 Data
ID2 Data
02h 02h 00h 30h
Read ID2
Commands
4 Cycle Address Read ID2
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
5th Cycle
Confirm
Command
R/B#
(Note 1)
Busy
Notes:
1. 4-cycle address is shown for the S34ML01G2. For S34ML02G2 and S34ML04G2, insert an additional address cycle of 00h.
2. If Status Register polling is used to determine completion of the Read ID2 operation, the Read Command (00h) must be issued before ID2 data can be read from the
flash.
Document Number: 002-00499 Rev. *N
Page 58 of 76
S34ML01G2
S34ML02G2
S34ML04G2
6.27 Read ONFI Signature Timing
Figure 6.34 ONFI Signature Timing
CLE
WE#
ALE
RE#
t
WHR
IO0~7
90h
20h
4Fh
4Eh
46h
49h
tREA
6.28 Read Parameter Page Timing
Figure 6.35 Read Parameter Page Timing
CLE
WE#
ALE
RE#
IO0-7
R/B#
...
...
00h
P10
ECh
P00
P01
P1
1
t
R
Note:
1. If Status Register polling is used to determine completion of the read operation, the Read Command (00h) must be issued before data can be read from the page
buffer.
Document Number: 002-00499 Rev. *N
Page 59 of 76
S34ML01G2
S34ML02G2
S34ML04G2
6.29 Read Unique ID Timing (Contact Factory)
Figure 6.36 Read Unique ID Timing
CLE
WE#
ALE
RE#
IO0-7
R/B#
...
...
00h
U10
EDh
U00
U01
U1
1
t
R
6.30 OTP Entry Timing
Figure 6.37 OTP Entry Timing
CLE
WE#
ALE
I/O0-7
29h 17h 04h 19h
Document Number: 002-00499 Rev. *N
Page 60 of 76
S34ML01G2
S34ML02G2
S34ML04G2
6.31 Power On and Data Protection Timing
Figure 6.38 Power On and Data Protection Timing
Vcc(min)
Vcc(min)
VTH
VTH
VCC
0V
don’t
care
don’t
care
CE
V
IH
Operation
5 ms max
V
IL
V
IL
WP
100 µs max
Invalid
don’t
care
Ready/Busy
Note:
1.
V
= 1.8 Volts.
TH
6.32 WP# Handling
Figure 6.39 Program Enabling / Disabling Through WP# Handling
WE#
WE#
t
WW
t
WW
I/Ox
80h
10h
I/Ox
80h
10h
WP#
R/B#
WP#
R/B#
Figure 6.40 Erase Enabling / Disabling Through WP# Handling
WE#
WE#
t
WW
t
WW
I/Ox
60h
D0h
I/Ox
60h
D0h
WP#
R/B#
WP#
R/B#
Document Number: 002-00499 Rev. *N
Page 61 of 76
S34ML01G2
S34ML02G2
S34ML04G2
7. Physical Interface
7.1
Physical Diagram
7.1.1
48-Pin Thin Small Outline Package (TSOP1)
Figure 7.1 TS/TSR 48 — 48-lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline
NOTES:
PACKAGE
TS/TSR 48
JEDEC
MO-142 (D) DD
1. DIMENSIONS ARE IN MILLIMETERS (mm).
(DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y14.5M-1994).
SYMBOL
MIN
---
NOM
---
MAX
1.20
0.15
1.05
0.23
0.27
0.16
0.21
20.20
18.50
12.10
2. PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
A
A1
A2
b1
b
3. PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK.
0.05
0.95
0.17
0.17
0.10
0.10
19.80
18.30
11.90
---
4. TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE LEADS
ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
1.00
0.20
0.22
---
5. DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD
PROTRUSION ON E IS 0.15mm PER SIDE AND ON D1 IS 0.25mm PER SIDE.
c1
c
6. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF b DIMENSION AT MAX.
MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON LOWER RADIUS OR THE
FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07mm.
---
D
20.00
18.40
12.00
0.50 BASIC
0.60
---
D1
E
7. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10mm AND 0.25mm FROM THE LEAD TIP.
e
8. LEAD COPLANARITY SHALL BE WITHIN 0.10mm AS MEASURED FROM
THE SEATING PLANE.
L
0.50
0˚
0.70
8
O
R
9. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
0.08
---
0.20
N
48
5006 \ f16-038 \ 6.5.13
Document Number: 002-00499 Rev. *N
Page 62 of 76
S34ML01G2
S34ML02G2
S34ML04G2
7.1.2
63-Ball, Ball Grid Array (BGA)
Figure 7.2 VBM063 — 63-Pin BGA, 11 mm x 9 mm Package
NOTES:
PACKAGE
JEDEC
VBM 063
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
M0-207(M)
2. ALL DIMENSIONS ARE IN MILLIMETERS.
11.00 mm x 9.00 mm NOM
PACKAGE
3. BALL POSITION DESIGNATION PER JEP95, SECTION
3, SPP-020.
SYMBOL
A
MIN
---
NOM
---
MAX
1.00
---
NOTE
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE
"D" DIRECTION.
A1
D
0.25
---
BALL HEIGHT
11.00 BSC.
9.00 BSC.
8.80 BSC.
7.20 BSC.
12
BODY SIZE
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE
"E" DIRECTION.
E
BODY SIZE
D1
E1
MD
ME
n
MATRIX FOOTPRINT
MATRIX FOOTPRINT
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
n IS THE TOTAL NUMBER OF POPULATED SOLDER
BALL POSITIONS FOR MATRIX SIZE MD X ME.
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
10
“SD” AND “SE” ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
63
ꢀꢀꢀb
eE
eD
SD
SE
0.40
0.45
0.50
BALL DIAMETER
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW “SD” OR “SE” = 0.
0.80 BSC.
0.80 BSC.
0.40 BSC.
0.40 BSC.
BALL PITCH
BALL PITCH
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, “SD” = eD/2 AND “SE” = eE/2.
SOLDER BALL PLACEMENT
SOLDER BALL PLACEMENT
8. "+" INDICATES THE THEORETICAL CENTER OF
DEPOPULATED BALLS.
A3-A8,B2-B8,C1,C2,C9,C10 DEPOPULATED SOLDER BALLS
D1,D2,D9,D10,E1,E2,E9,E10
F1,F2,F9,F10,G1,G2,G9,G10
H1,H2,H9,H10,J1,J2,J9,J10
K1,K2,K9,K10
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
L3-L8,M3-M8
g5011\ 16-038.25 \ 6.5.13
Document Number: 002-00499 Rev. *N
Page 63 of 76
S34ML01G2
S34ML02G2
S34ML04G2
7.1.3
67-Ball, Ball Grid Array (BGA)
Figure 7.3 VBT067 — 67-Ball BGA, 8 x 6.5 mm Package
NOTES:
PACKAGE
JEDEC
VBT 067
N/A
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
NOTE
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D X E
8.00 mm x 6.50 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JEP95, SECTION 3,
SPP-020.
SYMBOL
A
MIN
NOM
---
MAX
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
---
1.00
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
A1
D
0.22
---
BALL HEIGHT
BODY SIZE
BODY SIZE
8.00 BSC
6.50 BSC
7.20 BSC
5.60 BSC
10
n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
D1
E1
MD
ME
n
MATRIX FOOTPRINT
MATRIX FOOTPRINT
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
“SD” AND “SE” ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
8
67
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW, “SD” OR “SE” = 0.
Øb
eE
eD
SD
SE
0.41
0.46
0.51
BALL DIAMETER
0.80 BSC
0.80 BSC
0.40 BSC
0.40 BSC
BALL PITCH
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, “SD” = eD/2 AND “SE” = eE/2.
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
A1,D1,E1,F1,G1
A4,K4,A5,K5
D8,E8,F8,G8
g5019 \ f16-038.25 \ 10.11.13
Document Number: 002-00499 Rev. *N
Page 64 of 76
S34ML01G2
S34ML02G2
S34ML04G2
8. System Interface
To simplify system interface, CE# may be unasserted during data loading or sequential data reading as shown in Figure 8.1. By
operating in this way, it is possible to connect NAND flash to a microprocessor.
Figure 8.1 Program Operation with CE# Don't Care
CLE
CE# don’t care
CE#
WE#
ALE
80h
Start Add. (5 Cycle)
Data Input
Data Input
10h
I/Ox
Figure 8.2 Read Operation with CE# Don't Care
CLE
CE# don’t care
CE#
RE#
ALE
R/B#
tR
WE#
I/Ox
00h
Start Add. (5 Cycle)
30h
Data Output(sequential)
Document Number: 002-00499 Rev. *N
Page 65 of 76
S34ML01G2
S34ML02G2
S34ML04G2
Figure 8.3 Page Programming Within a Block
Page 63
Page 31
(64)
(1)
(64)
Page 63
(32)
Page 31
(3)
(32)
(1)
(3)
(2)
(1)
Page 2
Page 1
Page 0
Page 2
Page 1
Page 0
Data Register
Data Register
Ex.) Random page program (Optional)
DATA IN : Data (1) Data (64)
From the LSB page to MSB page
DATA IN : Data (1) Data (64)
Document Number: 002-00499 Rev. *N
Page 66 of 76
S34ML01G2
S34ML02G2
S34ML04G2
9. Error Management
9.1
System Bad Block Replacement
Over the lifetime of the device, additional Bad Blocks may develop. In this case, each bad block has to be replaced by copying any
valid data to a new block. These additional Bad Blocks can be identified whenever a program or erase operation reports “Fail” in the
Status Register.
The failure of a page program operation does not affect the data in other pages in the same block, thus the block can be replaced by
re-programming the current data and copying the rest of the replaced block to an available valid block. Refer to Table 9.1 and
Figure 9.1 for the recommended procedure to follow if an error occurs during an operation.
Table 9.1 Block Failure
Operation
Erase
Recommended Procedure
Block Replacement
Program
Read
Block Replacement
ECC (4 bit / 512+16 byte)
Figure 9.1 Bad Block Replacement
Block A
Block B
(2)
Data
Data
th
(1)
th
N page
Failure
N page
(3)
FFh
FFh
buffer memory of the controller
Notes:
1. An error occurs on the Nth page of Block A during a program operation.
2. Data in Block A is copied to the same location in Block B, which is a valid block.
3. The Nth page of block A, which is in controller buffer memory, is copied into the Nth page of Block B.
4. Bad block table should be updated to prevent from erasing or programming Block A.
Document Number: 002-00499 Rev. *N
Page 67 of 76
S34ML01G2
S34ML02G2
S34ML04G2
9.2
Bad Block Management
Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are
valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by
a select transistor. The devices are supplied with all the locations inside valid blocks erased (FFh). The Bad Block Information is
written prior to shipping. Any block where the 1st byte in the spare area of the 1st or 2nd or last page does not contain FFh is a Bad
Block. That is, if the first page has an FF value and should have been a non-FF value, then the non-FF value in the second page or
the last page will indicate a bad block.The Bad Block Information must be read before any erase is attempted, as the Bad Block
Information may be erased. For the system to be able to recognize the Bad Blocks based on the original information, it is
recommended to create a Bad Block table following the flowchart shown in Figure 9.2. The host is responsible to detect and track
bad blocks, both factory bad blocks and blocks that may go bad during operation. Once a block is found to be bad, data should not
be written to that block.The 1st block, which is placed on 00h block address is guaranteed to be a valid block.
Figure 9.2 Bad Block Management Flowchart
Start
Block Address=
Block 0
Increment
Block Address
Data(1)
=FFh?
No
Update
Bad Block Table
Yes
No
Last
Block?
Yes
End
Note:
1. Check for FFh at the 1st byte in the spare area of the 1st, 2nd, and last pages.
Document Number: 002-00499 Rev. *N
Page 68 of 76
S34ML01G2
S34ML02G2
S34ML04G2
10. Ordering Information
The ordering part number is formed by a valid combination of the following:
S34ML
04G
2
00
T
F
I
00
0
Packing Type
0
3
=
=
Tray
13” Tape and Reel
Model Number
00
00
01
=
=
=
Standard Interface / ONFI (×8)
Standard Interface (×16)
ONFI (×16)
Temperature Range
I
=
=
=
=
Industrial (-40°C to + 85°C)
A
V
B
Industrial with AECQ-100 and GT Grade (-40˚C to +85˚C)
Industrial Plus (-40°C to + 105°C)
Industrial Plus with AECQ-100 and GT Grade (-40˚C to +105˚C)
Materials Set
F
H
=
=
Lead (Pb)-free
Lead (Pb)-free and Low Halogen
Package
B
G
T
=
=
=
63-Ball BGA
67-Ball BGA
TSOP
Bus Width
00
04
=
=
×8 NAND, single die
×16 NAND, single die
Technology
2
=
Cypress NAND Revision 2 (32 nm)
Density
01G =
02G =
04G =
1 Gb
2 Gb
4 Gb
Device Family
S34ML
Cypress SLC NAND Flash Memory for Embedded
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm
availability of specific valid combinations and to check on newly released combinations.
Device
Family
Density
Technology Bus Width Package Type Temperature Range Additional Ordering Options Packing Type Package Description
01G
01G
02G
02G
04G
04G
04
00
04
00
00
04
TF
BH, GH, TF
TF
I
00, 01
I, A, V, B
Unique ID Support guaranteed:
90 _ Standard
I
S34ML
2
0, 3
TSOP, BGA (1)
BH, GH, TF
BH, TF
BH
I, A, V, B(2)
I, A, V, B
I
Interface / ONFI 1.0 (×8)
91 _ ONFI 1.0 (×16)
Notes:
1. BGA package marking omits the leading “S34” and the Packing Type designator from the ordering part number.
2. Contact sales regarding the availability of S34ML02G2 products in A,V and B temperature ranges.
Document Number: 002-00499 Rev. *N
Page 69 of 76
S34ML01G2
S34ML02G2
S34ML04G2
11. Document History
Document Title:S34ML01G2, S34ML02G2, S34ML04G2
1 Gb, 2 Gb, 4 Gb, 3 V, 4-bit ECC, SLC NAND Flash Memory for Embedded
Document Number: 002-00499
Orig. of Submission
Rev.
ECN No.
Description of Change
Change
Date
**
-
-
XILA
08/03/2012 Initial release
*A
XILA
11/27/2012
Global:
Upgraded data sheet designation from Advance Information to Preliminary
Note the S34ML02G2 is in the Advance Information designation
Added x16 I/O bus width data
Performance
Reliability: changed “with 1 bit ECC” to “with 4 bit ECC”
Connection Diagram: Added 63-VFBGA Contact, x16 Device (Balls
Down, Top View) figure
Array Organization : Added Array Organization — x16 figure
Addressing:
Address Cycle Map 1G/2G/4G Device tables: added x16 data
Multiplane Program — S34ML02G2 and S34ML04G2
Added text
Multiplane Block Erase — S34ML02G2 and S34ML04G2
Added text
Multiplane Copy Back Program —S34ML02G2 and S34ML04G2
Added text
Read ID
Read ID for Supported Configurations table: corrected x8 information
Added x16 information:
Read ID for Supported Configurations table
Read ID Byte 4 Description — S34ML01G2 table
Read ID Byte 4 Description — S34ML02G2 and S34ML04G2
Read Parameter Page
Parameter Page Description table: updated values for Bytes 254-255
Absolute Maximum Ratings
Absolute Maximum Ratings table:
updated Input or Output Voltage, and Supply Voltage values
added note
AC Characteristics
AC Characteristics table:
added CE# access time
added note for tCOH and tRHOH
Document Number: 002-00499 Rev. *N
Page 70 of 76
S34ML01G2
S34ML02G2
S34ML04G2
11. Document History (Continued)
Document Title:S34ML01G2, S34ML02G2, S34ML04G2
1 Gb, 2 Gb, 4 Gb, 3 V, 4-bit ECC, SLC NAND Flash Memory for Embedded
Document Number: 002-00499
Orig. of Submission
Rev.
ECN No.
Description of Change
Change
Date
*A
-
XILA
11/27/2012
Multiplane Page Program Operation —S34ML02G2 and S34ML04G2
Added note to Multiplane Page Program figure
Added note to Multiplane Page Program (ONFI 1.0 Protocol) figure
Multiplane Block Erase — S34ML02G2 and S34ML04G2
Added note to Multiplane Block Erase figure
Added note to Multiplane Block Erase (ONFI 1.0 Protocol) figure
Multiplane Copy Back Program —S34ML02G2 and S34ML04G2
Added note to Multiplane Copy Back Program figure
Multiplane Copy Back Program (ONFI 1.0 Protocol) figure:
Changed IOx values
Updated notes
Error Management :Block Failure table: Changed ECC 1 bit to 4 bit
Multiplane Cache Program —S34ML02G2 and S34ML04G2
Multiplane Cache Program figure:
Removed A13-A31 Address Input values
Added note
Ordering Information :
Added x16 Model Numbers
*B
-
XILA
12/19/2012
Command Set
Added Page Reprogram command
Reorganized Command Set table
Page Reprogram
Moved section
Added paragraph
Copy Back Program :Added paragraph
Reset: Updated paragraph
Read ID2: Added text
Read Parameter Page
Parameter Page Description table:
fixed Values of Bytes 6-7 and 254-255
fixed Description of Bytes 129-130 and 131-132
Absolute Maximum Ratings Fixed Value for VIO and VCC
DC Characteristics
DC Characteristics and Operating Conditions table: Changed Power On
Current Test Conditions
and Typ/Max values
AC Characteristics
AC Characteristics table: added note
Page Read Operation Page Read Operation (Read One Page) figure:
added note
Read ID2 Operation Timing
Read ID2 Operation Timing figure:
replaced tWHR with tR and added R/B# timing signal added note
Bad Block Management
Added text
Bad Block Management Flowchart: updated note
Document Number: 002-00499 Rev. *N
Page 71 of 76
S34ML01G2
S34ML02G2
S34ML04G2
11. Document History (Continued)
Document Title:S34ML01G2, S34ML02G2, S34ML04G2
1 Gb, 2 Gb, 4 Gb, 3 V, 4-bit ECC, SLC NAND Flash Memory for Embedded
Document Number: 002-00499
Orig. of Submission
Rev.
ECN No.
Description of Change
Change
Date
*C
XILA
-
02/14/2013
Distinctive Characteristics:
Corrected Plane Size for x16
Page Program Added paragraph
Multiplane Program — S34ML02G2 andS34ML04G2
Added paragraph
Page Reprogram: Added paragraph
Block Erase Added paragraph
Multiplane Block Erase — S34ML02G2 and S34ML04G2
Added paragraph
Copy Back Program Added paragraph
Multiplane Copy Back Program —S34ML02G2 and S34ML04G2
Added paragraph
Multiplane Cache Program —S34ML02G2 and S34ML04G2
Added paragraph
Read Parameter Page
Added paragraphs
Parameter Page Description table: corrected value for bytes 129-130, 131-
132, and 254-255
Valid Blocks Updated table
AC Characteristics
AC Characteristics table:
corrected Min value for tALS, tCLS, and tDS
corrected Max value for tCEA
*D
-
XILA
06/19/2013
Distinctive Characteristics Operating Temperature: removed
Commercial and Extended temperatures
Performance Updated Page Read / Program and Reliability sections
General Description Updated section
Block Diagram Updated Functional Block Diagram figure
Array Organization
Updated figures
Added two figures:
Array Organization — S34ML02G2 and S34ML04G2 (x8)
Array Organization — S34ML02G2 and S34ML04G2 (x16)
Addressing
Appended Note in all Address Cycle Map tables
Added text to Bus Cycle column in all Address Cycle Map tables
Page Read Updated section
Page Program Updated section
Multiplane Program — S34ML02G2 andS34ML04G2
Updated section
Page Reprogram
Corrected Page Reprogram figure
Corrected Page Reprogram with Data Manipulation figure
Copy Back Program Updated section
Read Status Register Field Definition Updated Status Register Coding
table
Document Number: 002-00499 Rev. *N
Page 72 of 76
S34ML01G2
S34ML02G2
S34ML04G2
11. Document History (Continued)
Document Title:S34ML01G2, S34ML02G2, S34ML04G2
1 Gb, 2 Gb, 4 Gb, 3 V, 4-bit ECC, SLC NAND Flash Memory for Embedded
Document Number: 002-00499
Orig. of Submission
Rev.
ECN No.
Description of Change
Change
Date
*D
-
XILA
06/19/2013
Read ID
Read ID for Supported Configurations table: corrected 2nd cycle for 1 Gb
x16
Read ID Byte 5 Description — S34ML02G2 and S34ML04G2 table:
corrected Description for Plane Size
Read Parameter Page
Parameter Page Description table: corrected value for bytes 8-9, 114, 137-
138, 139-140, and 254-255
Read Unique ID Added section
Ready/Busy
Updated section
Updated Ready/Busy Pin Electrical Application figure
Electrical Characteristics
Absolute Maximum Ratings table: removed Ambient Operating
Temperature (Commercial
Temperature Range) and Ambient Operating Temperature (Extended
Temperature Range)
AC Characteristics
AC Characteristics table: updated ‘Data transfer from cell to register’
Parameter
Program / Erase Characteristics
Program / Erase Characteristics table: added Dummy Busy Time for
Multiplane Program(S34MS02G2, S34MS04G2)
Multiplane Page Program Operation —S34MS02G2 and S34MS04G2
Updated Multiplane Page Program figure
Updated Multiplane Page Program (ONFI 1.0 Protocol) figure
Copy Back Read with Optional Data Readout
Corrected Copy Back Read with Optional Data Readout figure
Copy Back Program Operation With Random Data Input
Corrected Copy Back Program Operation With Random Data Input figure
Read Status Register Timing : Removed Read Status Enhanced Cycle
figure
Read Status Enhanced Timing: Removed Read Status Timing figure
Read Cache
Corrected Read Cache Operation Timing figure
Removed Cache Timing heading
Cache Program: Updated Cache Program figure
Read Parameter Page Timing
Added Note to Read Parameter Page Timing figure
Read Unique ID Timing Added section
Read Parameter Page Timing Added Note to Read Parameter Page
Timing figure
Document Number: 002-00499 Rev. *N
Page 73 of 76
S34ML01G2
S34ML02G2
S34ML04G2
11. Document History (Continued)
Document Title:S34ML01G2, S34ML02G2, S34ML04G2
1 Gb, 2 Gb, 4 Gb, 3 V, 4-bit ECC, SLC NAND Flash Memory for Embedded
Document Number: 002-00499
Orig. of Submission
Rev.
ECN No.
Description of Change
Change
Date
*D
-
XILA
06/19/2013
Read Unique ID Timing Added section
Physical Interface
Updated figures:
TS/TSR 48 — 48-lead Plastic Thin Small Outline, 12 x 20 mm, Package
Outline
VBM063 — 63-Pin BGA, 11 mm x 9 mm Package
Ordering Information
Clarified Bus Width and Technology
Added Note to Valid Combinations table
*E
*F
-
-
XILA
XILA
08/09/2013
11/01/2013
Mode Selection: Changed ‘Busy Time in Read’ WE# from X to High
System Interface:
Updated paragraph
Updated Read Operation with CE# Don’t Care figure
Performance
Package Options: added 67-Ball BGA 8 x 6 x 1 mm
Connection Diagram :Added figure: 67-BGA Contact (Balls Down, Top
View)
Physical Diagram : Added figure: 67-Ball, Ball Grid Array (BGA)
Ordering Information: Added to ‘Package’
Valid Combinations
Added ‘GH’ to Package Type
Added ‘Unique ID support guaranteed’ to Additional Ordering Options
*G
*H
*I
-
-
-
XILA
XILA
XILA
01/06/2014
07/03/2014
09/05/2014
Global
Upgraded data sheet designation from Preliminary to Full Production
Note the S34ML02G2 is in the Advance Information designation
Ordering Information
Added A, V, B to Temperature Range
Valid Combinations table: added A to Temperature Range of 01G Density
Ordering Information
Valid Combinations table:
added Package Type BH and TF for 01G Density
corrected Package Type for 02G Density
*J
-
XILA
XILA
04/17/2015
12/02/2015
Distinctive Characteristics
Operating Temperature: added Industrial Plus
Read Parameter :Page Updated Note
Read Unique ID (Contact Factory):
Unique ID Data Description (Contact Factory) table: added Note
Ordering Information: Valid Combinations table: updated table
*K
5030732
Updated to Cypress template
Document Number: 002-00499 Rev. *N
Page 74 of 76
S34ML01G2
S34ML02G2
S34ML04G2
11. Document History (Continued)
Document Title:S34ML01G2, S34ML02G2, S34ML04G2
1 Gb, 2 Gb, 4 Gb, 3 V, 4-bit ECC, SLC NAND Flash Memory for Embedded
Document Number: 002-00499
Orig. of Submission
Rev.
ECN No.
Description of Change
Change
Date
*L
5160512
XILA
04/25/2016
Added Recommended Operating Conditions section.
Updated DC Characteristics section - updated “VCC supply Voltage (erase
and program lockout)” to "Erase and Program Lockout voltage”.
Updated Ordering Information.
Updated “Read Parameter Page” section.
Updated copyright information at the end of the document.
*M
*N
5290473
5409174
XILA
XILA
05/31/2016
08/30/2016
Updated the part numbers under Package Options in the ‘Performance”
section.
Updated “Valid Combinations”.
Updated Reliability features in Performance.
Document Number: 002-00499 Rev. *N
Page 75 of 76
S34ML01G2
S34ML02G2
S34ML04G2
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Document Number: 002-00499 Rev. *N
Revised August 30, 2016
Page 76 of 76
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