S34ML04G100BFI010 [SPANSION]
Spansion® SLC NAND Flash Memory for Embedded;
| 型号： | S34ML04G100BFI010 |
| 厂家： | 
SPANSION |
| 描述： | Spansion® SLC NAND Flash Memory for Embedded |
| 文件： | 总73页 (文件大小：2766K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Spansion® SLC NAND Flash Memory for
Embedded
1 Gb, 2 Gb, 4 Gb Densities:
1-bit ECC, x8 and x16 I/O, 3V V
CC
S34ML01G1, S34ML02G1, S34ML04G1
Spansion® SLC NAND Flash Memory for Embedded Cover Sheet
Data Sheet (Preliminary)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S34ML01G1_04G1
Revision 10
Issue Date September 6, 2012
D a t a S h e e t ( P r e l i m i n a r y )
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
2
Spansion® SLC NAND Flash Memory for Embedded
S34ML01G1_04G1_10 September 6, 2012
Spansion® SLC NAND Flash Memory for
Embedded
1 Gb, 2 Gb, 4 Gb Densities:
1-bit ECC, x8 and x16 I/O, 3V V
CC
S34ML01G1, S34ML02G1, S34ML04G1
Data Sheet (Preliminary)
Distinctive Characteristics
Density
NAND Flash Interface
– 1 Gbit / 2 Gbit / 4 Gbit
– Open NAND Flash Interface (ONFI) 1.0 compliant
– Address, Data and Commands multiplexed
Architecture
Supply Voltage
– Input / Output Bus Width: 8-bits / 16-bits
– Page Size:
– 3.3V device: Vcc = 2.7V ~ 3.6V
– x8 = 2112 (2048 + 64) bytes; 64 bytes is spare area
– x16 = 1056 (1024 + 32) words; 32 words is spare area
– Block Size: 64 Pages
Security
– One Time Programmable (OTP) area
– Serial number (unique ID)
– x8 = 128k + 4k bytes
– Hardware program/erase disabled during power transition
– x16 = 64k + 2k words
– Plane Size:
Additional Features
– 2 Gb and 4 Gb parts support Multiplane Program and Erase
commands
– Supports Copy Back Program
– 2 Gb and 4 Gb parts support Multiplane Copy Back Program
– Supports Read Cache
– 1 Gbit / 2 Gbit: 1024 Blocks per Plane
x8 = 128M + 4M bytes
x16 = 64M + 2M words
– 4 Gbit: 2048 Blocks per Plane
x8 = 256M + 8M bytes
Electronic Signature
x16 = 128M + 4M words
– Device Size:
– Manufacturer ID: 01h
Operating Temperature
– Commercial: 0°C to 70°C
– Extended: -25°C to 85°C
– Industrial: -40°C to 85°C
– 1 Gbit: 1 Plane per Device or 128 Mbyte
– 2 Gbit: 2 Planes per Device or 256 Mbyte
– 4 Gbit: 2 Planes per Device or 512 Mbyte
Performance
Page Read / Program
Reliability
– Random access: 25 µs (Max)
– Sequential access: 25 ns (Min)
– Program time / Multiplane Program time: 200 µs (Typ)
– 100,000 Program / Erase cycles (Typ)
(with 1 bit ECC per 528 bytes (x8) or 264 words (x16))
– 10 Year Data retention (Typ)
– Block zero is a valid block and will be valid for at least 1000
program-erase cycles
Block Erase (S34ML01G1)
– Block Erase time: 2.0 ms (Typ)
Package Options
Block Erase / Multiplane Erase (S34ML02G1, S34ML04G1)
– Block Erase time: 3.5 ms (Typ)
– Lead Free and Low Halogen
– 48-Pin TSOP 12 x 20 x 1.2 mm
– 63-Ball BGA 9 x 11 x 1 mm
Publication Number S34ML01G1_04G1
Revision 10
Issue Date September 6, 2012
This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qual-
ification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document
may be revised by subsequent versions or modifications due to changes in technical specifications.
D a t a S h e e t ( P r e l i m i n a r y )
Table of Contents
Distinctive Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1
1.2
1.3
1.4
1.5
1.6
Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Array Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.6.1 S34ML01G1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.6.2 S34ML02G1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.6.3 S34ML04G1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.7
2.
3.
Bus Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1
2.2
2.3
2.4
2.5
2.6
Command Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Address Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1
3.2
3.3
3.4
3.5
3.6
Page Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Multiplane Program — S34ML02G1 and S34ML04G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Multiplane Block Erase — S34ML02G1 and S34ML04G1 . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Copy Back Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.6.1 Multiplane Copy Back Program — S34ML02G1 and S34ML04G1 . . . . . . . . . . . . . . . . . .22
3.6.2 Special Read for Copy Back — S34ML02G1 and S34ML04G1 . . . . . . . . . . . . . . . . . . . .22
EDC Operation — S34ML02G1 and S34ML04G1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.7.1 Read EDC Status Register — S34ML02G1 and S34ML04G1 . . . . . . . . . . . . . . . . . . . . .24
Read Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Read Status Enhanced — S34ML02G1 and S34ML04G1 . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.7
3.8
3.9
3.10 Read Status Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.11 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.12 Read Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.13 Cache Program — S34ML02G1 and S34ML04G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.14 Multiplane Cache Program — S34ML02G1 and S34ML04G1 . . . . . . . . . . . . . . . . . . . . . . . 28
3.15 Page Reprogram — S34ML02G1 and S34ML04G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.16 Read ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.17 Read ID2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.18 Read ONFI Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.19 Read Parameter Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.20 One-Time Programmable (OTP) Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.
5.
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.1
4.2
4.3
Data Protection and Power On / Off Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Ready/Busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Write Protect Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.1
5.2
5.3
5.4
5.5
5.6
Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Pin Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4
Spansion® SLC NAND Flash Memory for Embedded
S34ML01G1_04G1_10 September 6, 2012
D a t a S h e e t ( P r e l i m i n a r y )
5.7
Program / Erase Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
Command Latch Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Address Latch Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Data Input Cycle Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Data Output Cycle Timing (CLE=L, WE#=H, ALE=L, WP#=H) . . . . . . . . . . . . . . . . . . . . . . . 44
Data Output Cycle Timing (EDO Type, CLE=L, WE#=H, ALE=L) . . . . . . . . . . . . . . . . . . . . . 44
Page Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Page Read Operation (Intercepted by CE#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Page Read Operation Timing with CE# Don’t Care. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Page Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.10 Page Program Operation Timing with CE# Don’t Care . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.11 Page Program Operation with Random Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.12 Random Data Output In a Page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.13 Multiplane Page Program Operation — S34ML02G1 and S34ML04G1 . . . . . . . . . . . . . . . . 48
6.14 Block Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.15 Multiplane Block Erase — S34ML02G1 and S34ML04G1 . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.16 Copy Back Read with Optional Data Readout — S34ML02G1 and S34ML04G1. . . . . . . . . 51
6.17 Copy Back Program Operation With Random Data Input — S34ML02G1 and S34ML04G1 51
6.18 Multiplane Copy Back Program — S34ML02G1 and S34ML04G1 . . . . . . . . . . . . . . . . . . . . 52
6.19 Read Status Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.20 Read Status Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.21 Reset Operation Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.22 Read Cache Operation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.23 Cache Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.24 Cache Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.25 Multiplane Cache Program — S34ML02G1 and S34ML04G1 . . . . . . . . . . . . . . . . . . . . . . . 58
6.26 Read ID Operation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.27 Read ID2 Operation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.28 Read ONFI Signature Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.29 Read Parameter Page Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.30 OTP Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.31 Power On and Data Protection Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.32 WP# Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.
Physical Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.1
Physical Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.1.1 48-Pin Thin Small Outline Package (TSOP1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
7.1.2 63-Pin Ball Grid Array (BGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
8.
9.
System Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Error Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.1
9.2
System Bad Block Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Bad Block Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
11. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
September 6, 2012 S34ML01G1_04G1_10
Spansion® SLC NAND Flash Memory for Embedded
5
D a t a S h e e t ( P r e l i m i n a r y )
Figures
Figure 1.1
Figure 1.2
Figure 1.3
Figure 1.4
Figure 1.5
Figure 1.6
Figure 1.7
Figure 3.1
Figure 3.2
Figure 4.1
Figure 4.2
Figure 6.1
Figure 6.2
Figure 6.3
Figure 6.4
Figure 6.5
Figure 6.6
Figure 6.7
Figure 6.8
Figure 6.9
Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
48-Pin TSOP1 Contact x8, x16 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
63-BGA Contact, x8 Device (Balls Down, Top View). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
63-VFBGA Contact, x16 Device (Balls Down, Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Array Organization — x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Array Organization — x16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Page Reprogram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Page Reprogram with Data Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Ready/Busy Pin Electrical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
WP# Low Timing Requirements during Program/Erase Command Sequence . . . . . . . . . . . 37
Command Latch Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Address Latch Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Input Data Latch Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Data Output Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Data Output Cycle Timing (EDO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Page Read Operation (Read One Page). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Page Read Operation Intercepted by CE# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Page Read Operation Timing with CE# Don’t Care. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Page Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 6.10 Page Program Operation Timing with CE# Don’t Care . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 6.11 Random Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 6.12 Random Data Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 6.13 Multiplane Page Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 6.14 Multiplane Page Program (ONFI 1.0 Protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 6.15 Block Erase Operation (Erase One Block). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 6.16 Multiplane Block Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 6.17 Multiplane Block Erase (ONFI 1.0 Protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 6.18 Copy Back Read with Optional Data Readout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 6.19 Copy Back Program with Random Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 6.20 Multiplane Copy Back Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 6.21 Multiplane Copy Back Program (ONFI 1.0 Protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 6.22 Status / EDC Read Cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 6.23 Read Status Enhanced Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 6.24 Read Status Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 6.25 Read Status Enhanced Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 6.26 Reset Operation Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 6.27 Read Cache Operation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 6.28 “Sequential” Read Cache Timing, Start (and Continuation) of Cache Operation . . . . . . . . . 56
Figure 6.29 “Random” Read Cache Timing, Start (and Continuation) of Cache Operation . . . . . . . . . . . 56
Figure 6.30 Read Cache Timing, End Of Cache Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 6.31 Cache Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 6.32 Multiplane Cache Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 6.33 Multiplane Cache Program (ONFI 1.0 Protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 6.34 Read ID Operation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 6.35 Read ID2 Operation Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 6.36 ONFI Signature Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 6.37 Read Parameter Page Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 6.38 OTP Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 6.39 Power On and Data Protection Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 6.40 Program Enabling / Disabling Through WP# Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 6.41 Erase Enabling / Disabling Through WP# Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 7.1
Figure 7.2
TS/TSR 48 — 48-lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline . . . . . . . . 64
VBM063 — 63-Pin BGA, 11 mm x 9 mm Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6
Spansion® SLC NAND Flash Memory for Embedded
S34ML01G1_04G1_10 September 6, 2012
D a t a S h e e t ( P r e l i m i n a r y )
Figure 8.1
Figure 8.2
Figure 8.3
Figure 9.1
Figure 9.2
Program Operation with CE# Don't Care. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Read Operation with CE# Don't Care . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Page Programming Within a Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Bad Block Replacement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Bad Block Management Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
September 6, 2012 S34ML01G1_04G1_10
Spansion® SLC NAND Flash Memory for Embedded
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D a t a S h e e t ( P r e l i m i n a r y )
Tables
Table 1.1
Table 1.2
Table 1.3
Table 1.4
Table 1.5
Table 1.6
Table 3.1
Table 3.2
Table 3.3
Table 3.4
Table 3.5
Table 3.6
Table 3.7
Table 3.8
Table 3.9
Table 3.10
Table 3.11
Table 3.12
Table 5.1
Table 5.2
Table 5.3
Table 5.4
Table 5.5
Table 5.6
Table 5.7
Table 9.1
Signal Names. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Address Cycle Map — 1 Gb Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Address Cycle Map — 2 Gb Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Address Cycle Map — 4 Gb Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
EDC Register Coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Page Organization in EDC Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Page Organization in EDC Units by Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Status Register Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Read ID for Supported Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Read ID Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Read ID Byte 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Read ID Byte 4 Description — S34ML01G1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Read ID Byte 4 Description — S34ML02G1 and S34ML04G1 . . . . . . . . . . . . . . . . . . . . . . . 32
Read ID Byte 5 Description — S34ML02G1 and S34ML04G1 . . . . . . . . . . . . . . . . . . . . . . . 32
Parameter Page Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
DC Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Pin Capacitance (TA = 25°C, f=1.0 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Program / Erase Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Block Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
8
Spansion® SLC NAND Flash Memory for Embedded
S34ML01G1_04G1_10 September 6, 2012
D a t a S h e e t ( P r e l i m i n a r y )
1. General Description
The Spansion S34ML01G1, S34ML02G1, and S34ML04G1 series is offered in 3.3 VCC and VCCQ power
supply, and with x8 or x16 I/O interface. Its NAND cell provides the most cost-effective solution for the solid
state mass storage market. The memory is divided into blocks that can be erased independently so it is
possible to preserve valid data while old data is erased. The page size for x8 is (2048 + 64 spare) bytes; for
x16 (1024 + 32) words.
Each block can be programmed and erased up to 100,000 cycles with ECC (error correction code) on. To
extend the lifetime of NAND flash devices, the implementation of an ECC is mandatory.
The chip supports CE# don't care function. This function allows the direct download of the code from the
NAND flash memory device by a microcontroller, since the CE# transitions do not stop the read operation.
The devices have a Read Cache feature that improves the read throughput for large files. During cache
reading, the devices load the data in a cache register while the previous data is transferred to the I/O buffers
to be read.
Like all other 2 kB-page NAND flash devices, a program operation typically writes to the 2112-byte page (x8),
or 1056 words (x16) in 200 µs and an erase operation can typically be performed in 2 ms (S34ML01G1) on a
128-kB block (x8) or 64-kword block (x16). In addition, thanks to multiplane architecture, it is possible to
program two pages at a time (one per plane) or to erase two blocks at a time (again, one per plane). The
multiplane architecture allows program time to be reduced by 40% and erase time to be reduced by 50%.
In multiplane operations, data in the page can be read out at 25 ns cycle time per byte. The I/O pins serve as
the ports for command and address input as well as data input/output. This interface allows a reduced pin
count and easy migration towards different densities, without any rearrangement of the footprint.
Commands, Data, and Addresses are asynchronously introduced using CE#, WE#, ALE, and CLE control
pins.
The on-chip Program/Erase Controller automates all read, program, and erase functions including pulse
repetition, where required, and internal verification and margining of data. A WP# pin is available to provide
hardware protection against program and erase operations.
The output pin R/B# (open drain buffer) signals the status of the device during each operation. It identifies if
the program/erase/read controller is currently active. The use of an open-drain output allows the Ready/Busy
pins from several memories to connect to a single pull-up resistor. In a system with multiple memories the
R/B# pins can be connected all together to provide a global status signal.
The Reprogram function allows the optimization of defective block management — when a Page Program
operation fails the data can be directly programmed in another page inside the same array section without the
time consuming serial data insertion phase. The Copy Back operation automatically executes embedded
error detection operation: 1-bit error out of every 528 bytes (x8) or 256 words (x16) can be detected. With this
feature it is no longer necessary to use an external mechanism to detect Copy Back operation errors.
Multiplane Copy Back is also supported. Data read out after Copy Back Read (both for single and multiplane
cases) is allowed.
In addition, Cache Program and Multiplane Cache Program operations improve the programing throughput by
programing data using the cache register.
The devices provide two innovative features: Page Reprogram and Multiplane Page Reprogram. The Page
Reprogram re-programs one page. Normally, this operation is performed after a failed Page Program
operation. Similarly, the Multiplane Page Reprogram re-programs two pages in parallel, one per plane. The
first page must be in the first plane while the second page must be in the second plane. The Multiplane Page
Reprogram operation is performed after a failed Multiplane Page Program operation. The Page Reprogram
and Multiplane Page Reprogram guarantee improved performance, since data insertion can be omitted
during re-program operations.
Note: The S34ML01G1 device does not support EDC.
September 6, 2012 S34ML01G1_04G1_10
Spansion® SLC NAND Flash Memory for Embedded
9
D a t a S h e e t ( P r e l i m i n a r y )
The devices come with the following security features:
OTP (one time programmable) area, which is a restricted access area where sensitive data/code can be
stored permanently.
Serial number (unique identifier), which allows the devices to be uniquely identified.
Read ID2 extension.
These security features are subject to an NDA (non-disclosure agreement) and are, therefore, not described
in the data sheet. For more details about them, contact your nearest Spansion sales office.
Density (bits)
Number of Blocks
Device
Number of Planes
EDC Support
per Plane
Main
Spare
128M x 8
64M x 16
4M x 8
S34ML01G1
S34ML02G1
S34ML04G1
1
2
2
1024
No
Yes
Yes
2M x 16
256M x 8
8M x 8
1024
2048
128M x 16
4M x 16
512M x 8
16M x 8
8M x 16
256M x 16
1.1
Logic Diagram
Figure 1.1 Logic Diagram
VCC
CE#
I/O0~I/O7
WE#
R/B#
RE#
ALE
CLE
WP#
VSS
Table 1.1 Signal Names
I/O7 - I/O0 (x8)
Data Input / Outputs
I/O8 - I/O15 (x16)
CLE
ALE
CE#
RE#
WE#
WP#
R/B#
VCC
VSS
NC
Command Latch Enable
Address Latch Enable
Chip Enable
Read Enable
Write Enable
Write Protect
Read/Busy
Power Supply
Ground
Not Connected
10
Spansion® SLC NAND Flash Memory for Embedded
S34ML01G1_04G1_10 September 6, 2012
D a t a S h e e t ( P r e l i m i n a r y )
1.2
Connection Diagram
Figure 1.2 48-Pin TSOP1 Contact x8, x16 Devices
x8
x16
x8
x16
1
48
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS (1) VSS
NC
NC
NC
I/O7
I/O6
I/O15
I/O14
I/O13
I/O7
I/O6
NC
NC
I/O5
I/O4
NC
I/O5
I/O4
I/O12
R/B#
RE#
CE#
NC
R/B#
RE#
CE#
NC
VCC (1) VCC
NC
NC
NC
NC
NAND Flash
TSOP1
VCC
VSS
NC
VCC
VSS
NC
VCC
VSS
NC
VCC
VSS
NC
12
13
37
36
NC
NC
VCC (1) VCC
CLE
ALE
WE#
WP#
NC
CLE
ALE
WE#
WP#
NC
NC
I/011
I/O3
I/O2
I/O1
I/O0
I/O10
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
NC
NC
NC
NC
NC
NC
I/O9
I/O8
NC
NC
VSS (1) VSS
24
25
Note:
1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be
bonded internally.
Figure 1.3 63-BGA Contact, x8 Device (Balls Down, Top View)
A2
A9
A1
A10
NC
NC
NC
NC
B1
B9
B10
NC
NC
NC
C3
C4
C5
C6
C7
C8
WP#
ALE
VSS
CE#
WE#
RB#
D3
D4
D5
D6
D7
D8
VCC (1)
RE#
CLE
NC
NC
NC
E3
E4
E5
E6
E7
E8
NC
NC
NC
NC
NC
NC
F3
F4
F5
F6
F7
F8
NC
NC
NC
NC
VSS (1)
NC
G3
NC
G4
G5
NC
G6
NC
G7
NC
G8
NC
VCC (1)
H3
H4
H5
H6
H7
H8
NC
I/O0
NC
NC
NC
V
cc
J3
J4
J5
J6
J7
J8
NC
I/O1
NC
V
I/O5
I/O7
K8
CC
K3
K4
K5
K6
K7
V
I/O2
I/O3
I/O4
I/O6
V
SS
SS
L1
L2
L9
L10
NC
NC
NC
NC
M1
NC
M2
NC
M9
NC
M10
NC
Note:
1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be
bonded internally.
September 6, 2012 S34ML01G1_04G1_10
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D a t a S h e e t ( P r e l i m i n a r y )
Figure 1.4 63-VFBGA Contact, x16 Device (Balls Down, Top View)
A2
A9
A1
A10
NC
NC
NC
NC
B1
B9
B10
NC
NC
NC
C3
C4
C5
C6
C7
C8
WP#
ALE
VSS
CE#
WE#
RB#
D3
D4
D5
D6
D7
D8
VCC
RE#
CLE
NC
NC
NC
E3
E4
E5
E6
E7
E8
NC
NC
NC
NC
NC
NC
F3
F4
F5
F6
F7
F8
NC
NC
NC
NC
VSS
NC
G3
NC
G4
G5
NC
G6
G7
G8
NC
VCC
I/O13
I/O15
H3
H4
H5
H6
H7
H8
I/O8
I/O0
I/O10
I/O12
I/O14
V
cc
J3
J4
J5
J6
J7
J8
I/O9
I/O1
I/O11
V
I/O5
I/O7
K8
CC
K3
K4
K5
K6
K7
V
I/O2
I/O3
I/O4
I/O6
V
SS
SS
L1
L2
L9
L10
NC
NC
NC
NC
M1
NC
M2
NC
M9
NC
M10
NC
1.3
Pin Description
Table 1.2 Pin Description
Pin Name
Description
I/O0 - I/O7 (x8)
I/O8 - I/O15 (x16)
Inputs/Outputs. The I/O pins are used for command input, address input, data input, and data output. The
I/O pins float to High-Z when the device is deselected or the outputs are disabled.
Command Latch Enable. This input activates the latching of the I/O inputs inside the Command Register on the rising
edge of Write Enable (WE#).
CLE
ALE
Address Latch Enable. This input activates the latching of the I/O inputs inside the Address Register on the rising
edge of Write Enable (WE#).
CE#
Chip Enable. This input controls the selection of the device. When the device is not busy CE# low selects the memory.
Write Enable. This input latches Command, Address and Data. The I/O inputs are latched on the rising edge of WE#.
Read Enable. The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data is
WE#
RE#
valid t
after the falling edge of RE# which also increments the internal column address counter by one.
REA
Write Protect. The WP# pin, when low, provides hardware protection against undesired data modification
(program / erase).
WP#
R/B#
VCC
Ready Busy. The Ready/Busy output is an Open Drain pin that signals the state of the memory.
Supply Voltage. The V supplies the power for all the operations (Read, Program, Erase). An internal lock circuit
CC
prevents the insertion of Commands when V is less than V
.
CC
LKO
VSS
NC
Ground.
Not Connected.
Notes:
1. A 0.1 µF capacitor should be connected between the V Supply Voltage pin and the V Ground pin to decouple the current surges from
CC
SS
the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations.
2. An internal voltage detector disables all functions whenever V is below 1.8V (3V device) to protect the device from any involuntary
CC
program/erase during power transitions.
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Spansion® SLC NAND Flash Memory for Embedded
S34ML01G1_04G1_10 September 6, 2012
D a t a S h e e t ( P r e l i m i n a r y )
1.4
Block Diagram
Figure 1.5 Functional Block Diagram
Address
Register/
Counter
Program Erase
Controller
HV Generation
X
1024 Mbit + 32 Mbit (1 Gb Device)
2048 Mbit + 64 Mbit (2 Gb Device)
4096 Mbit + 128 Mbit (4 Gb Device)
D
E
C
O
D
E
R
ALE
CLE
NAND Flash
WE#
CE#
WP#
Memory Array
Command
Interface
Logic
RE#
PAGE Buffer
Y Decoder
Command
Register
I/O Buffer
Data
Register
I/O0~I/O7 (x8)
I/O0~I/O15 (x16)
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Spansion® SLC NAND Flash Memory for Embedded
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D a t a S h e e t ( P r e l i m i n a r y )
1.5
Array Organization
Figure 1.6 Array Organization — x8
1 Page = (2k + 64) bytes
Plane(s)
1 Block = (2k + 64) bytes x 64 pages
= (128k + 4k) bytes
0
1
1 Plane = (128k + 4k) bytes x 1024 Blocks
1024
Blocks
per
2
Note:
For 1 Gb and 2 Gb devices there are 1024 Blocks per Plane
For 4 Gb device there are 2048 Blocks per Plane
2 Gb and 4 Gb devices have two Planes
Plane
1022
1023
I/O
[7:0]
Page Buffer
2048 bytes
64 bytes
Array Organization(x8)
Figure 1.7 Array Organization — x16
1 Page = (1k + 32) words
Plane(s)
1 Block = (1k + 32) words x 64 pages
= (64k + 2k) words
0
1
1 Plane = (64k + 2k) words x 1024 Blocks
1024
Blocks
per
2
Note:
For 1 Gb and 2 Gb devices there are 1024 Blocks per Plane
For 4 Gb device there are 2048 Blocks per Plane
2 Gb and 4 Gb devices have two Planes
Plane
1022
1023
I/O0~I/O15
Page Buffer
32 words
1024 words
Array Organization(x16)
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Spansion® SLC NAND Flash Memory for Embedded
S34ML01G1_04G1_10 September 6, 2012
D a t a S h e e t ( P r e l i m i n a r y )
1.6
1.6.1
Addressing
S34ML01G1
Table 1.3 Address Cycle Map — 1 Gb Device
Bus Cycle
I/O [15:8] (3)
I/O0
I/O1
I/O2
x8
I/O3
I/O4
I/O5
I/O6
I/O7
1st
2nd
3rd
4th
—
—
—
—
A0
A8
A1
A9
A2
A3
A4
A5
A6
A7
A10
A14
A22
x16
A2
A11
A15
A23
L (1)
A16
A24
L (1)
A17
A25
L (1)
A18
A26
L (1)
A19
A27
A12
A20
A13
A21
1st
2nd
3rd
4th
Low
Low
Low
Low
A0
A8
A1
A9
A3
A4
A5
A6
A7
A10
A13
A21
L (2)
A14
A22
L (2)
A15
A23
L (2)
A16
A24
L (2)
A17
A25
L (2)
A18
A26
A11
A19
A12
A20
Notes:
1. L must be set to low.
2. Block address concatenated with page address = actual page address.
3. I/O[15:8] are not used during the addressing sequence and should be driven Low.
For the address bits, the following rules apply:
A0 - A11: column address in the page
A12 - A17: page address in the block
A18 - A27: block address
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D a t a S h e e t ( P r e l i m i n a r y )
Table 1.4 Address Cycle Map — 2 Gb Device
1.6.2
S34ML02G1
Bus Cycle
I/O [15:8] (3)
I/O0
I/O1
I/O2
x8
I/O3
I/O4
I/O5
I/O6
I/O7
1st
2nd
3rd
4th
5th
—
—
—
—
—
A0
A8
A1
A9
A2
A3
A4
A5
A6
A7
A10
A14
A22
L (1)
x16
A2
A11
A15
A23
L (1)
L (1)
A16
A24
L (1)
L (1)
A17
A25
L (1)
L (1)
A18
A26
L (1)
L (1)
A19
A27
L (1)
A12
A20
A28
A13
A21
L (1)
1st
2nd
Low
Low
Low
Low
Low
A0
A8
A1
A9
A3
A4
A5
A6
A7
A10
A13
A21
L (2)
L (2)
A14
A22
L (2)
L (2)
A15
A23
L (2)
L (2)
A16
A24
L (2)
L (2)
A17
A25
L (2)
L (2)
A18
A26
L (2)
3rd
A11
A19
A27
A12
A20
L (2)
4th
5th
Notes:
1. L must be set to low.
2. Block address concatenated with page address = actual page address.
3. I/O[15:8] are not used during the addressing sequence and should be driven Low.
For the address bits, the following rules apply:
A0 - A11: column address in the page
A12 - A17: page address in the block
A18: plane address (for multiplane operations) / block address (for normal operations)
A19 - A28: block address
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Spansion® SLC NAND Flash Memory for Embedded
S34ML01G1_04G1_10 September 6, 2012
D a t a S h e e t ( P r e l i m i n a r y )
1.6.3
S34ML04G1
Table 1.5 Address Cycle Map — 4 Gb Device
Bus Cycle
I/O [15:8] (3)
I/O0
I/O1
I/O2
x8
I/O3
I/O4
I/O5
I/O6
I/O7
1st
2nd
3rd
4th
5th
—
—
—
—
—
A0
A8
A1
A9
A2
A3
A4
A5
A6
A7
A10
A14
A22
A30
x16
A2
A11
A15
A23
L (1)
L (1)
A16
A24
L (1)
L (1)
A17
A25
L (1)
L (1)
A18
A26
L (1)
L (1)
A19
A27
L (1)
A12
A20
A28
A13
A21
A29
1st
2nd
3rd
4th
5th
Low
Low
Low
Low
Low
A0
A8
A1
A9
A3
A4
A5
A6
A7
A10
A13
A21
A29
L (2)
A14
A22
L (2)
L (2)
A15
A23
L (2)
L (2)
A16
A24
L (2)
L (2)
A17
A25
L (2)
L (2)
A18
A26
L (2)
A11
A19
A27
A12
A20
A28
Notes:
1. L must be set to low.
2. Block address concatenated with page address = actual page address.
3. I/O[15:8] are not used during the addressing sequence and should be driven Low.
For the address bits, the following rules apply:
A0 - A11: column address in the page
A12 - A17: page address in the block
A18: plane address (for multiplane operations) / block address (for normal operations)
A19 - A30: block address
1.7
Mode Selection
Table 1.6 Mode Selection
Mode
CLE
High
Low
High
Low
Low
Low
X
ALE
Low
High
Low
High
Low
Low
X
CE#
Low
Low
Low
Low
Low
Low
X
WE#
Rising
Rising
Rising
Rising
Rising
High
High
X
RE#
WP#
X
Command Input
Address Input
Command Input
Address Input
High
High
High
High
High
Falling
High
High (3)
X
Read Mode
X
High
High
High
X
Program or Erase Mode
Data Input
Data Output (on going)
Data Output (suspended)
Busy Time in Read
Busy Time in Program
Busy Time in Erase
Write Protect
X
X
X
X
X
X
X
X
X
High
High
Low
X
X
X
X
X
X
X
X
X
X
Stand By
X
X
High
X
X
0V / V (2)
CC
Notes:
1. X can be V or V . H = Logic level HIGH. L = Logic level LOW.
IL
IH
2. WP# should be biased to CMOS high or CMOS low for stand-by mode.
3. During Busy Time in Read, RE# must be held high to prevent unintended data out.
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D a t a S h e e t ( P r e l i m i n a r y )
2. Bus Operation
There are six standard bus operations that control the device: Command Input, Address Input, Data Input,
Data Output, Write Protect, and Standby. (See Table 1.6.)
Typically glitches less than 5 ns on Chip Enable, Write Enable, and Read Enable are ignored by the memory
and do not affect bus operations.
2.1
2.2
Command Input
The Command Input bus operation is used to give a command to the memory device. Commands are
accepted with Chip Enable low, Command Latch Enable high, Address Latch Enable low, and Read Enable
high and latched on the rising edge of Write Enable. Moreover, for commands that start a modify operation
(program/erase) the Write Protect pin must be high. See Figure 6.1 on page 42 and Table 5.4 on page 39 for
details of the timing requirements. Command codes are always applied on I/O7:0 regardless of the bus
configuration (x8 or x16).
Address Input
The Address Input bus operation allows the insertion of the memory address. For the S34ML02G1 and
S34ML04G1 devices, five write cycles are needed to input the addresses. For the S34ML01G1, four write
cycles are needed to input the addresses. If necessary, a 5th dummy address cycle can be issued to
S34ML01G1, which will be ignored by the NAND device without causing problems. Addresses are accepted
with Chip Enable low, Address Latch Enable high, Command Latch Enable low, and Read Enable high and
latched on the rising edge of Write Enable. Moreover, for commands that start a modify operation (program/
erase) the Write Protect pin must be high. See Figure 6.2 on page 43 and Table 5.4 on page 39 for details of
the timing requirements. Addresses are always applied on I/O7:0 regardless of the bus configuration (x8 or
x16). Refer to Table 1.3 through Table 1.5 on page 17 for more detailed information.
2.3
2.4
Data Input
The Data Input bus operation allows the data to be programmed to be sent to the device. The data insertion is
serial and timed by the Write Enable cycles. Data is accepted only with Chip Enable low, Address Latch
Enable low, Command Latch Enable low, Read Enable high, and Write Protect high and latched on the rising
edge of Write Enable. See Figure 6.3 on page 43 and Table 5.4 on page 39 for details of the timing
requirements.
Data Output
The Data Output bus operation allows data to be read from the memory array and to check the Status
Register content, the EDC register content, and the ID data. Data can be serially shifted out by toggling the
Read Enable pin with Chip Enable low, Write Enable high, Address Latch Enable low, and Command Latch
Enable low. See Figure 6.4 on page 44 to Figure 6.23 and Table 5.4 on page 39 for details of the timings
requirements.
2.5
2.6
Write Protect
The Hardware Write Protection is activated when the Write Protect pin is low. In this condition, modify
operations do not start and the content of the memory is not altered. The Write Protect pin is not latched by
Write Enable to ensure the protection even during power up.
Standby
In Standby, the device is deselected, outputs are disabled, and power consumption is reduced.
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Spansion® SLC NAND Flash Memory for Embedded
S34ML01G1_04G1_10 September 6, 2012
D a t a S h e e t ( P r e l i m i n a r y )
3. Command Set
Table 3.1 Command Set
Acceptable
Command
during Busy
Supported on
S34ML01G1
Command
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
Page Read
00h
80h
85h
05h
80h
80h
8Bh
60h
60h
60h
00h
85h
85h
85h
00h
7Bh
70h
78h
FFh
31h
00h
3Fh
80h
80h
80h
80h
80h
80h
8Bh
8Bh
8Ah
30h
10h
Yes
Yes
Yes
Yes
No
No
No
Yes
No
No
Yes
Yes
No
No
No
No
Yes
No
Yes
Yes
No
Yes
No
No
No
No
No
No
No
No
No
Page Program
Random Data Input
Random Data Output
E0h
11h
11h
11h
D0h
60h
D1h
35h
10h
11h
11h
36h
Multiplane Program
81h
80h
8Bh
10h
10h
10h
ONFI Multiplane Program
Multiplane Page Reprogram
Block Erase
Multiplane Block Erase
D0h
60h
ONFI Multiplane Block Erase
Copy Back Read
D0h
Copy Back Program
Multiplane Copy Back Program
ONFI Multiplane Copy Back Program
Special Read For Copy Back
Read EDC Status Register
Read Status Register
81h
85h
10h
10h
Yes
Yes
Yes
Read Status Enhanced
Reset
Read Cache
Read Cache Enhanced
31h
Read Cache End
Cache Program (End)
10h
15h
11h
11h
11h
11h
11h
11h
11h
Cache Program (Start) / (Continue)
Multiplane Cache Program (Start/Continue)
ONFI Multiplane Cache Program (Start/Continue)
Multiplane Cache Program (End)
ONFI Multiplane Cache Program (End)
Nth Pages Multiplane Cache Reprogram (Cont)
Nth Pages Multiplane Cache Reprogram (End)
N-1th Pages Multiplane Cache Reprogram (Cont)
81h
80h
81h
80h
8Bh
8Bh
8Ah
15h
15h
10h
10h
15h
10h
15h
Page Reprogram / Nth Page Cache Reprogram
(End)
8Bh
10h
No
Nth Page Cache Reprogram (Continue)
N-1th Page Cache Reprogram (Continue)
Read ID
8Bh
8Ah
15h
15h
No
No
90h
Yes
No
Read ID2
30h-65h-00h
90h
30h
Read ONFI Signature
Yes
Yes
Yes
Read Parameter Page
ECh
One-time Programmable (OTP) Area Entry
29h-17h-04h-19h
September 6, 2012 S34ML01G1_04G1_10
Spansion® SLC NAND Flash Memory for Embedded
19
D a t a S h e e t ( P r e l i m i n a r y )
3.1
Page Read
Page Read is initiated by writing 00h and 30h to the command register along with five address cycles
(S34ML02G1 and S34ML04G1). Two types of operations are available: random read and serial page read.
Random read mode is enabled when the page address is changed. The 2112 bytes (x8) or 1056 words (x16)
of data within the selected page are transferred to the data registers in less than 25 µs (tR). The system
controller may detect the completion of this data transfer (tR) by analyzing the output of the R/B pin. Once the
data in a page is loaded into the data registers, they may be read out in 25 ns (x8) or 40 ns (x16) cycle time
by sequentially pulsing RE#. The repetitive high to low transitions of the RE# signal makes the device output
the data, starting from the selected column address up to the last column address.
The device may output random data in a page instead of the sequential data by writing Random Data Output
command. The column address of next data, which is going to be out, may be changed to the address that
follows Random Data Output command. Random Data Output can be performed as many times as needed.
After power up, the device is in read mode, so 00h command cycle is not necessary to start a read operation.
Any operation other than read or Random Data Output causes the device to exit read mode.
See Figure 6.6 on page 45 and Figure 6.12 on page 48 as references.
3.2
Page Program
A page program cycle consists of a serial data loading period in which up to 2112 bytes (x8) or 1056 words
(x16) of data may be loaded into the data register, followed by a non-volatile programming period where the
loaded data is programmed into the appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the five
cycle address inputs (four cycles for S34ML01G1) and then serial data. The words other than those to be
programmed do not need to be loaded. The device supports Random Data Input within a page. The column
address of next data, which will be entered, may be changed to the address that follows the Random Data
Input command (85h). Random Data Input may be performed as many times as needed.
The Page Program confirm command (10h) initiates the programming process. The internal write state
controller automatically executes the algorithms and controls timings necessary for program and verify,
thereby freeing the system controller for other tasks.
Once the program process starts, the Read Status Register commands (70h or 78h) may be issued to read
the Status Register. The system controller can detect the completion of a program cycle by monitoring the
R/B# output, or the Status bit (I/O6) of the Status Register. Only the Read Status commands (70h or 78h) or
Reset command are valid while programming is in progress. When the Page Program is complete, the Write
Status Bit (I/O0) may be checked. The internal write verify detects only errors for 1’s that are not successfully
programmed to 0’s. The command register remains in Read Status command mode until another valid
command is written to the command register. Figure 6.9 on page 46 and Figure 6.11 on page 47 detail the
sequence.
The device is programmable by page, but it also allows multiple partial page programming of a word or
consecutive bytes up to 2112 bytes (x8) or 1056 words (x16) in a single page program cycle.
The number of consecutive partial page programming operations (NOP) within the same page must not
exceed the number indicated in Table 5.7 on page 41. In addition, pages must be sequentially programmed
within a block.
Users who use “EDC check” (for S34ML02G1 and S34ML04G1 only) in copy back must comply with some
limitations related to data handling during one page program sequence. Refer to Section 3.7 on page 23 for
details.
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Spansion® SLC NAND Flash Memory for Embedded
S34ML01G1_04G1_10 September 6, 2012
D a t a S h e e t ( P r e l i m i n a r y )
3.3
Multiplane Program — S34ML02G1 and S34ML04G1
The S34ML02G1 and S34ML04G1 devices support Multiplane Program, making it possible to program two
pages in parallel, one page per plane.
A Multiplane Program cycle consists of a double serial data loading period in which up to 4224 bytes (x8) or
2112 words (x16) of data may be loaded into the data register, followed by a non-volatile programming period
where the loaded data is programmed into the appropriate cell. The serial data loading period begins with
inputting the Serial Data Input command (80h), followed by the five cycle address inputs and serial data for
the 1st page. The address for this page must be in the 1st plane (A18=0). The device supports Random Data
Input exactly the same as in the case of page program operation. The Dummy Page Program Confirm
command (11h) stops 1st page data input and the device becomes busy for a short time (tDBSY). Once it has
become ready again, the ‘81h’ command must be issued, followed by 2nd page address (5 cycles) and its
serial data input. The address for this page must be in the 2nd plane (A18=1). Program Confirm command
(10h) makes parallel programming of both pages to start. Figure 6.13 on page 48 describes the sequences.
The user can check operation status by monitoring R/B# pin or reading Status Register commands (70h or
78h), as if it were a normal page program. The Read Status Register command is also available during
Dummy Busy time (tDBSY). In case of failure in any of 1st and 2nd page program, the fail bit of the Status
Register will be set. Refer to Section 3.8 on page 25 for further info.
The number of consecutive partial page programming operations (NOP) within the same page must not
exceed the number indicated in Table 5.7 on page 41. In addition, pages must be programmed sequentially
within a block.
3.4
Block Erase
The Block Erase operation is done on a block basis. Block address loading is accomplished in three cycles
(two cycles for S34ML01G1) initiated by an Erase Setup command (60h). Only addresses A18 to A29 (A18 to
A27 for S34ML01G1) are valid while A12 to A17 are ignored.
The Erase Confirm command (D0h) following the block address loading initiates the internal erasing process.
This two-step sequence of setup followed by the execution command ensures that memory contents are not
accidentally erased due to external noise conditions.
At the rising edge of WE# after the erase confirm command input, the internal write controller handles erase
and erase verify. Once the erase process starts, the Read Status Register commands (70h or 78h) may be
issued to read the Status Register.
The system controller can detect the completion of an erase by monitoring the R/B# output, or the Status bit
(I/O6) of the Status Register. Only the Read Status commands (70h or 78h) and Reset command are valid
while erasing is in progress. When the erase operation is completed, the Write Status Bit (I/O0) may be
checked. Figure 6.15 on page 49 details the sequence.
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3.5
Multiplane Block Erase — S34ML02G1 and S34ML04G1
Multiplane Block Erase allows the erase of two blocks in parallel, one block per memory plane.
The Block erase setup command (60h) must be repeated two times, followed by 1st and 2nd block address
respectively (3 cycles each). As for block erase, D0h command makes embedded operation start. In this
case, multiplane erase does not need any Dummy Busy Time between 1st and 2nd block insertion. See
Table 5.7 on page 41 and Figure 6.16 on page 50 for details.
For the Multiplane Block Erase operation, the address of the first block must be within the first plane (A18 = 0
for x8 devices, A17 = 0 for x16 devices) and the address of the second block in the second plane (A18 = 1 for
x8 devices, A17 = 1 for x16 devices). Also, operation progress can be checked as in the Multiplane Program
through the Read Status Register command.
3.6
Copy Back Program
The copy back feature is intended to quickly and efficiently rewrite data stored in one page without utilizing an
external memory. Since the time-consuming cycles of serial access and re-loading cycles are removed, the
system performance is greatly improved. The benefit is especially obvious when a portion of a block needs to
be updated and the rest of the block also needs to be copied to the newly assigned free block. The operation
for performing a copy back is a sequential execution of page-read (without mandatory serial access) and
Copy Back Program with the address of destination page. A read operation with the ‘35h’ command and the
address of the source page moves the whole 2112-byte (x8) or 1056-word (x16) data into the internal data
buffer. As soon as the device returns to Ready state, optional data read-out is allowed by toggling RE# (see
Figure 6.18 on page 51), or Copy Back Program command (85h) with the address cycles of destination page
may be written. The Program Confirm command (10h) is required to actually begin the programming
operation.
Source and Destination page in the Copy Back Program sequence must belong to the same device plane
(x8 = same A18, x16 = same A17).
The data input cycle for modifying a portion or multiple distinct portions of the source page is allowed as
shown in Figure 6.19 on page 51. As noted in Section 1. on page 9 the device may include an automatic EDC
(for S34ML02G1 and S34ML04G1) check during the copy back operation, to detect single bit errors in EDC
units contained within the source page. More details on EDC operation and limitations related to data input
handling during one Copy Back Program sequence are available in Section 3.7 on page 23.
3.6.1
Multiplane Copy Back Program — S34ML02G1 and S34ML04G1
The device supports Multiplane Copy Back Program with exactly the same sequence and limitations as the
Page Program. Multiplane Copy Back Program must be preceded by two single page Copy Back Read
command sequences (1st page must be read from the 1st plane and 2nd page from the 2nd plane).
Multiplane Copy Back cannot cross plane boundaries — the contents of the source page of one device plane
can be copied only to a destination page of the same plane. EDC check is available also for Multiplane Copy
Back Program only for S34ML02G1 and S34ML04G1.
When “EDC check” is used in copy back, it must comply with some limitations related to data handling during
one Multiplane Copy Back Program sequence. The sequence is (85h, first plane address 11h, 81h, second
plane address, 10h) represented in Figure 6.20. Please refer to Section 3.7 on page 23 for details.
3.6.2
Special Read for Copy Back — S34ML02G1 and S34ML04G1
The device features the “Special Read for Copy Back.” If Copy Back Read (described in Section 3.6 and
Section 3.6.1 on page 22) is triggered with confirm command ‘36h’ instead ‘35h’, Copy Back Read from target
page(s) will be executed with an increased internal (VPASS) voltage.
This special feature is used in order to minimize the number of read errors due to over-program or read
disturb — it shall be used only if ECC read errors have occurred in the source page using Page Read or Copy
Back Read sequences.
Excluding the Copy Back Read confirm command, all other features described in Section 3.6 and
Section 3.6.1 for standard copy back remain valid (including the figures referred to in those sections).
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3.7
EDC Operation — S34ML02G1 and S34ML04G1
Error Detection Code check is a feature that can be used during the copy back operation (both single and
multiplane) to detect single bit errors occurring in the source page(s).
Note: The S34ML01G1 device does not support EDC.
EDC check allows detection of up to 1 single bit error every 528 bytes, where each 528 byte group is
composed of 512 bytes of main array and 16 bytes of spare area (see Table 3.3 and Table 3.4
on page 24). The described 528-byte area is called an “EDC unit.”
In the x16 device, EDC allows detection of up to 1 single bit error every 264 words, where each 264 word
group is composed by 256 words of main array and 8 words of spare area see Table 3.3 and Table 3.4
on page 24). The described 264-word area is called “EDC unit.”
EDC results can be checked through a specific Read EDC register command, available only after issuing a
Copy Back Program or a Multiplane Copy Back Program. The EDC register can be queried during the copy
back program busy time (tPROG).
For the “EDC check” feature to operate correctly, specific conditions on data input handling apply for program
operations.
For the case of Page Program, Multiplane Page Program, Page Reprogram, Multiplane Page Reprogram,
Cache Program, and Multiplane Cache Program operations:
In Section 3.2 on page 20 it was explained that a number of consecutive partial program operations (NOP)
is allowed within the same page. In case this feature is used, the number of partial program operations
occurring in the same EDC unit must not exceed 1. In other words, page program operations must be
performed on the whole page, or on whole EDC unit at a time.
“Random Data Input” in a given EDC unit can be executed several times during one page program
sequence, but data cannot be written to any column address more than once before the program is
initiated.
For the case of Copy Back Program or Multiplane Copy Back Program operations:
If Random Data Input is applied in a given EDC unit, the entire EDC unit must be written to the page buffer.
In other words, the EDC check is possible only if the whole EDC unit is modified during one Copy Back
Program sequence.
“Random Data Input” in a given EDC unit can be executed several times during one Copy Back Program
sequence, but data insertion in each column address of the EDC unit must not exceed 1.
If you use copy back without EDC check, none of the limitations described above apply.
After a Copy Back Program operation, the host can use Read EDC Status Register to check the status of
both the program operation and the Copy Back Read. If the EDC was valid and an error was reported in the
EDC (see Table 3.2 on page 24), the host may perform Special Read For Copy Back on the source page and
attempt the Copy Back Program again. If this also fails, the host can execute a Page Read operation in order
to correct a single bit error with external ECC software or hardware.
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3.7.1
Read EDC Status Register — S34ML02G1 and S34ML04G1
This operation is available only after issuing a Copy Back Program and it allows the detection of errors during
Copy Back Read. In the case of multiplane copy back, it is not possible to know which of the two read
operations caused the error.
After writing the Read EDC Status Register command (7Bh) to the command register, a read cycle outputs
the content of the EDC Register to the I/O pins on the falling edge of CE# or RE#, whichever occurs last.
The operation is the same as the Read Status Register command. Refer to Table 3.2 for specific EDC
Register definitions:
Table 3.2 EDC Register Coding
ID
0
1
2
3
4
5
6
7
Copy Back Program
Pass / Fail
EDC status
EDC validity
NA
Coding
Pass: 0; Fail: 1
No error: 0; Error: 1
Invalid: 0; Valid: 1
—
NA
—
Ready / Busy
Ready / Busy
Write Protect
Busy: 0; Ready: 1
Busy: 0; Ready: 1
Protected: 0; Not Protected: 1
Table 3.3 Page Organization in EDC Units
Main Field (2048 Byte)
Spare Field (64 Byte)
“A” area
“B” area
“C” area
“D” area
“E” area
“F” area
“G” area
“H” area
(1st sector)
(2nd sector)
(3rd sector)
(4th sector)
(1st sector)
(2nd sector)
(3rd sector)
(4th sector)
x8
512 byte
512 byte
512 byte
512 byte
16 byte
8 words
16 byte
8 words
16 byte
8 words
16 byte
8 words
x16
256 words
256 words
256 words
256 words
Table 3.4 Page Organization in EDC Units by Address
Main Field (Column 0-2047)
Area Name Column Address
x8
0-511
Spare Field (Column 2048-2111)
Sector
Area Name
Column Address
1st 528-byte Sector
2nd 528-byte Sector
3rd 528-byte Sector
4th 528-byte Sector
A
B
C
D
E
F
2048-2063
2064-2079
2080-2095
2096-2111
512-1023
1024-1535
1536-2047
x16
G
H
1st 256-word Sector
2nd 256-word Sector
3rd 256-word Sector
4th 256-word Sector
A
B
C
D
0-255
E
F
1024-1031
1032-1039
1040-1047
1048-1055
256-511
512-767
768-1023
G
H
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3.8
Read Status Register
The Status Register is used to retrieve the status value for the last operation issued. After writing 70h
command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on
the falling edge of CE# or RE#, whichever occurs last. This two-line control allows the system to poll the
progress of each device in multiple memory connections even when R/B# pins are common-wired. Refer to
Section 3.5 on page 26 for specific Status Register definition, and to Figure 6.22 on page 53 and Figure 6.24
on page 54 for timings.
If the Read Status Register command is issued during multiplane operations then Status Register polling will
return the combined status value related to the outcome of the operation in the two planes according to the
following table:
Status Register Bit
Bit 0, Pass/Fail
Composite Status Value
OR
OR
Bit 1, Cache Pass/Fail
In other words, the Status Register is dynamic; the user is not required to toggle RE# / CE# to update it.
The command register remains in Status Read mode until further commands are issued. Therefore, if the
Status Register is read during a random read cycle, the read command (00h) should be given before starting
read cycles.
Note: The Read Status Register command shall not be used for concurrent operations in multi-die stack
configurations (single CE#). “Read Status Enhanced” shall be used instead.
3.9
Read Status Enhanced — S34ML02G1 and S34ML04G1
Read Status Enhanced is an additional feature used to retrieve the status value for a previous operation in
the case of multiplane operations in the same die.
Figure 6.25 on page 54 defines the Read Status Enhanced behavior and timings. The plane and die address
must be specified in the command sequence in order to retrieve the status of the die and the plane of interest.
Refer to Table 3.5 for specific Status Register definitions. The command register remains in Status Read
mode until further commands are issued.
The Status Register is dynamic; the user is not required to toggle RE# / CE# to update it.
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3.10 Read Status Register Field Definition
Table 3.5 below lists the meaning of each bit of the Read Status Register and Read Status Enhanced
(S34ML02G1 and S34ML04G1).
Table 3.5 Status Register Coding
Page
Program /
Page
Cache
Program /
Cache
ID
Block Erase
Read
Read Cache
Coding
Reprogram
Reprogram
N Page
Pass: 0
Fail: 1
0
1
Pass / Fail
NA
Pass / Fail
NA
NA
NA
NA
NA
Pass / Fail
Pass / Fail
N - 1 Page
Pass: 0
Fail: 1
2
3
4
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
—
—
—
Internal Data Operation
Active: 0
5
Ready / Busy
Ready / Busy
Ready / Busy
Ready / Busy
Ready / Busy
Idle: 1
Ready/Busy
Busy: 0
Ready: 1
6
7
Ready / Busy
Write Protect
Ready / Busy
Write Protect
Ready / Busy
Write Protect
Ready / Busy
Write Protect
Ready / Busy
Write Protect
Protected: 0
Not Protected: 1
3.11 Reset
The Reset feature is executed by writing FFh to the command register. If the device is in Busy state during
random read, program, or erase mode, the Reset operation will abort these operations. The contents of
memory cells being altered are no longer valid, as the data may be partially programmed or erased. The
command register is cleared to wait for the next command, and the Status Register is cleared to value E0h
when WP# is high. Refer to Table 3.8 on page 31 for device status after reset operation. If the device is
already in reset state a new Reset command will not be accepted by the command register. The R/B# pin
transitions to low for tRST after the Reset command is written. Refer to Figure 6.26 on page 55 for further
details.
3.12 Read Cache
Read Cache can be used to increase the read operation speed, as defined in Section 3.1 on page 20, and it
cannot cross a block boundary. As soon as the user starts to read one page, the device automatically loads
the next page into the cache register. Serial data output may be executed while data in the memory is read
into the cache register. Read Cache is initiated by the Page Read sequence (00-30h) on a page M.
After random access to the first page is complete (R/B# returned to high, or Read Status Register I/O6
switches to high), two command sequences can be used to continue read cache:
Read Cache (command ‘31h’ only): once the command is latched into the command register (see
Figure 6.28 on page 56), device goes busy for a short time (tCBSYR), during which data of the first page is
transferred from the data register to the cache register. At the end of this phase, the cache register data
can be output by toggling RE# while the next page (page address M+1) is read from the memory array into
the data register.
Read Cache Enhanced (sequence ‘00h’ <page N address> ‘31’): once the command is latched into the
command register (see Figure 6.29 on page 56), device goes busy for a short time (tCBSYR), during which
data of the first page is transferred from the data register to the cache register. At the end of this phase,
cache register data can be output by toggling RE# while page N is read from the memory array into the
data register.
Note: The S34ML01G1 device does not support Read Cache Enhanced.
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Subsequent pages are read by issuing additional Read Cache or Read Cache Enhanced command
sequences. If serial data output time of one page exceeds random access time (tR), the random access time
of the next page is hidden by data downloading of the previous page.
On the other hand, if 31h is issued prior to completing the random access to the next page, the device will
stay busy as long as needed to complete random access to this page, transfer its contents into the cache
register, and trigger the random access to the following page.
To terminate the Read Cache operation, 3Fh command should be issued (see Figure 6.30 on page 56). This
command transfers data from the data register to the cache register without issuing next page read.
During the Read Cache operation, the device doesn't allow any other command except for 00h, 31h, 3Fh,
Read SR, or Reset (FFh). To carry out other operations, Read Cache must be terminated by the Read Cache
End command (3Fh) or the device must be reset by issuing FFh.
Read Status command (70h) may be issued to check the status of the different registers and the busy/ready
status of the cached read operations.
The Cache-Busy status bit I/O6 indicates when the cache register is ready to output new data.
The status bit I/O5 can be used to determine when the cell reading of the current data register contents is
complete.
Note: The Read Cache and Read Cache End commands reset the column counter, thus, when RE# is
toggled to output the data of a given page, the first output data is related to the first byte of the page (column
address 00h). Random Data Output command can be used to switch column address.
3.13 Cache Program — S34ML02G1 and S34ML04G1
Cache Program can be used with S34ML02G1 and S34ML04G1 devices to improve the program throughput
by programing data using the cache register. The cache program operation cannot cross a block boundary.
The cache register allows new data to be input while the previous data that was transferred to the data
register is programmed into the memory array.
After the serial data input command (80h) is loaded to the command register, followed by five cycles of
address, a full or partial page of data is latched into the cache register.
Once the cache write command (15h) is loaded to the command register, the data in the cache register is
transferred into the data register for cell programming. At this time the device remains in the Busy state for a
short time (tCBSYW). After all data of the cache register is transferred into the data register, the device returns
to the Ready state and allows loading the next data into the cache register through another cache program
command sequence (80h-15h).
The Busy time following the first sequence 80h - 15h equals the time needed to transfer the data from the
cache register to the data register. Cell programming the data of the data register and loading of the next data
into the cache register is consequently processed through a pipeline model.
In case of any subsequent sequence 80h - 15h, transfer from the cache register to the data register is held off
until cell programming of current data register contents is complete; till this moment the device will stay in a
busy state (tCBSYW).
Read Status commands (70h or 78h) may be issued to check the status of the different registers, and the
pass/fail status of the cached program operations.
The Cache-Busy status bit I/O6 indicates when the cache register is ready to accept new data.
The status bit I/O5 can be used to determine when the cell programming of the current data register
contents is complete.
The cache program error bit I/O1 can be used to identify if the previous page (page N-1) has been
successfully programmed or not in a cache program operation. The status bit is valid upon I/O6 status bit
changing to 1.
The error bit I/O0 is used to identify if any error has been detected by the program/erase controller while
programming page N. The status bit is valid upon I/O5 status bit changing to 1.
I/O1 may be read together with I/O0.
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If the system monitors the progress of the operation only with R/B#, the last page of the target program
sequence must be programmed with Page Program Confirm command (10h). If the Cache Program
command (15h) is used instead, the status bit I/O5 must be polled to find out if the last programming is
finished before starting any other operation. See Table 3.5 on page 26 and Figure 6.31 on page 57 for more
details.
3.14 Multiplane Cache Program — S34ML02G1 and S34ML04G1
The Multiplane Cache Program enables high program throughput by programming two pages in parallel,
while exploiting the data and cache registers of both planes to implement cache.
The command sequence can be summarized as follows:
Serial Data Input command (80h), followed by the five cycle address inputs and then serial data for the 1st
page. Address for this page must be within 1st plane (A18=0). The data of 1st page other than those to be
programmed do not need to be loaded. The device supports Random Data Input exactly like Page Program
operation.
The Dummy Page Program Confirm command (11h) stops 1st page data input and the device becomes
busy for a short time (tDBSY).
Once device returns to ready again, 81h command must be issued, followed by 2nd page address
(5 cycles) and its serial data input. Address for this page must be within 2nd plane (A18=1). The data of
2nd page other than those to be programmed do not need to be loaded.
Cache Program confirm command (15h). Once the cache write command (15h) is loaded to the command
register, the data in the cache registers is transferred into the data registers for cell programming. At this
time the device remains in the Busy state for a short time (tCBSYW). After all data from the cache registers
are transferred into the data registers, the device returns to the Ready state, and allows loading the next
data into the cache register through another cache program command sequence.
The sequence 80h-...- 11h...-...81h...-...15h can be iterated, and each time the device will be busy for the
tCBSYW time needed to complete programming the current data register contents, and transferring the new
data from the cache registers.
The sequence to end Multiplane Cache Program is 80h-...- 11h...-...81h...-...10h. Figure 6.32 on page 58
shows the command sequence for the multiplane cache program operation.
The Multiplane Cache Program is available only within two paired blocks in separate planes.
The user can check operation status by R/B# pin or Read Status Register commands (70h or 78h). If the user
opts for 70h, Read Status Register will provide “global” information about the operation in the two planes.
I/O6 indicates when both cache registers are ready to accept new data.
I/O5 indicates when the cell programming of the current data registers is complete.
I/O1 identifies if the previous pages in both planes (pages N-1) have been successfully programmed or not.
This status bit is valid upon I/O6 status bit changing to 1.
I/O0 identifies if any error has been detected by the program/erase controller while programming the two
pages N. This status bit is valid upon I/O5 status bit changing to 1.
See Table 3.5 on page 26 for more details.
If the system monitors the progress of the operation only with R/B#, the last pages of the target program
sequence must be programmed with Page Program Confirm command (10h). If the Cache Program
command (15h) is used instead, the status bit I/O5 must be polled to find out if the last programming is
finished before starting any other operation. Refer to Section 3.8 on page 25 for further information.
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3.15 Page Reprogram — S34ML02G1 and S34ML04G1
Page Program may result in a fail, which can be detected by Read Status Register. In this event, the host
may call Page Reprogram. This command allows the reprogramming of the same pattern of the last (failed)
page into another memory location. The command sequence initiates with reprogram setup (8Bh), followed
by the five cycle address inputs of the target page. If the target pattern for the destination page is not changed
compared to the last page, the program confirm can be issued (10h) without any data input cycle, as
described in Figure 3.1.
Figure 3.1 Page Reprogram
As defined for Page
A
Program
Din
D0
Din
D1
Din
Din
Dn
CMD
10h
CMD
00h
ADDR ADDR ADDR
ADDR
C1
Cycle Type
I/Ox
tASL
C2
. . .
R1
R2
tWB
tPROG
SR[6]
Page N
A
Cycle Type
Dout
CMD
10h
CMD
ADDR ADDR ADDR
CMD
70h
ADDR
C1
E1
8Bh
C2
R1
R2
I/Ox
tWB
tPROG
SR[6]
FAIL !
Page M
On the other hand, if the pattern bound for the target page is different from that of the previous page, data in
cycles can be issued before program confirm ‘10h’, as described in Figure 3.2.
Figure 3.2 Page Reprogram with Data Manipulation
As defined for Page
A
Program
Din
D0
Din
D1
Din
Din
Dn
ADDR ADDR ADDR
CMD
10h
CMD
70h
Dout
CMD
ADDR
C1
Cycle Type
IOx
tADL
. . .
80h
C2
R1
R2
E1
tWB
tPROG
SR[6]
FAIL !
Page N
A
Cycle Type
CMD
10h
CMD
ADDR ADDR ADDR
ADDR
C1
Din
D0
Din
Din
Dn
Din
D1
tADL
I/Ox
. . .
8Bh
C2
R1
R2
tWB
tPROG
SR[6]
Page M
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D a t a S h e e t ( P r e l i m i n a r y )
The device supports Random Data Input within a page. The column address of next data, which will be
entered, may be changed to the address which follows the Random Data Input command (85h). Random
Data Input may be operated multiple times regardless of how many times it is done in a page.
The Program Confirm command (10h) initiates the re-programming process. The internal write state
controller automatically executes the algorithms and controls timings necessary for program and verify,
thereby freeing the system controller for other tasks. Once the program process starts, the Read Status
Register command may be issued to read the Status Register. The system controller can detect the
completion of a program cycle by monitoring the R/B# output, or the Status bit (I/O6) of the Status Register.
Only the Read Status command and Reset command are valid when programming is in progress. When the
Page Program is complete, the Write Status Bit (I/O0) may be checked. The internal write verify detects only
errors for 1’s that are not successfully programmed to 0’s. The command register remains in Read Status
command mode until another valid command is written to the command register.
3.16 Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed
by an address input of 00h.
Note: If you want to execute Read Status command (0x70) after Read ID sequence, you should input dummy
command (0x00) before Read Status command (0x70).
For the S34ML02G1 and S34ML04G1 devices, five read cycles sequentially output the manufacturer code
(01h), and the device code and 3rd, 4th, and 5th cycle ID, respectively. For the S34ML01G1 device, four read
cycles sequentially output the manufacturer code (01h), and the device code and 80h, 4th cycle ID,
respectively. The command register remains in Read ID mode until further commands are issued to it.
Figure 6.34 on page 60 shows the operation sequence, while Table 3.6 to Table 3.11 explain the byte
meaning.
Table 3.6 Read ID for Supported Configurations
Density
1 Gb
2 Gb
4 Gb
1 Gb
2 Gb
4 Gb
Org
V
1st
01h
01h
01h
01h
01h
01h
2nd
F1h
3rd
00h
90h
90h
00h
90h
90h
4th
1Dh
95h
95h
5Dh
D5h
D5h
5th
—
CC
x8
DAh
DCh
C1h
CAh
CCh
44h
54h
—
3.3V
x16
44h
54h
Table 3.7 Read ID Bytes
Device Identifier Byte
Description
1st
2nd
3rd
4th
Manufacturer Code
Device Identifier
Internal chip number, cell type, etc.
Page Size, Block Size, Spare Size, Organization
Multiplane information
5th (S34ML02G1, S34ML04G1)
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3rd ID Data
Table 3.8 Read ID Byte 3 Description
Description
I/O7
I/O6
I/O5 I/O4
I/O3 I/O2
I/O1 I/O0
1
2
4
8
0 0
0 1
1 0
1 1
Internal Chip Number
2-level cell
4-level cell
8-level cell
16-level cell
0 0
0 1
1 0
1 1
Cell type
1
2
4
8
0 0
0 1
1 0
11
Number of simultaneously
programmed pages
Not supported
Supported
0
1
Interleave program
Between multiple chips
Not supported
Supported
0
1
Cache Program
4th ID Data
Table 3.9 Read ID Byte 4 Description — S34ML01G1
Description
I/O7
I/O6
I/O5 I/O4
I/O3
I/O2
I/O1 I/O0
1 kB
2 kB
4 kB
8 kB
0 0
0 1
1 0
1 1
Page size
(without spare area)
64 kB
128 kB
256 kB
512 kB
0 0
0 1
1 0
1 1
Block Size
(without spare area)
8
0
1
Spare Area Size (byte /
512 byte)
16
45 ns
25 ns
0
0
1
1
0
1
0
1
Serial Access Time
Organization
Reserved
Reserved
x8
0
1
x16
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D a t a S h e e t ( P r e l i m i n a r y )
Table 3.10 Read ID Byte 4 Description — S34ML02G1 and S34ML04G1
Description
I/O7
I/O6
I/O5 I/O4
I/O3
I/O2
I/O1 I/O0
1 kB
2 kB
4 kB
8 kB
0 0
0 1
1 0
1 1
Page size
(without spare area)
64 kB
128 kB
256 kB
512 kB
0 0
0 1
1 0
1 1
Block Size
(without spare area)
8
0
1
Spare Area size
(byte / 512 byte)
16
50 ns / 30 ns
25 ns
0
1
0
1
0
0
1
1
Serial Access Time
Organization
Reserved
Reserved
x8
0
1
x16
5th ID Data
Table 3.11 Read ID Byte 5 Description — S34ML02G1 and S34ML04G1
Description
I/O7
I/O6 I/O5 I/O4
I/O3 I/O2
I/O1
I/O0
1
2
4
8
0 0
0 1
1 0
1 1
Plane Number
64 Mb
128 Mb
256 Mb
512 Mb
1 Gb
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
Plane Size
(without spare area)
2 Gb
4 Gb
Reserved
0
0
0
3.17 Read ID2
The device contains an alternate identification mode, initiated by writing 30h-65h-00h to the command
register, followed by address inputs, followed by command 30h. The address for S34ML01G1 will be
00h-02h-02h-00h. The address for S34ML02G1 and S34ML04G1 will be 00h-02h-02h-00h-00h. The ID2 data
can then be read from the device by pulsing RE#. The command register remains in Read ID2 mode until
further commands are issued to it. Figure 6.35 on page 60 shows the Read ID2 command sequence.
3.18 Read ONFI Signature
To retrieve the ONFI signature, the command 90h together with an address of 20h shall be entered (i.e. it is
not valid to enter an address of 00h and read 36 bytes to get the ONFI signature). The ONFI signature is the
ASCII encoding of 'ONFI' where 'O' = 4Fh, 'N' = 4Eh, 'F' = 46h, and 'I' = 49h. Reading beyond four bytes yields
indeterminate values. Figure 6.36 on page 61 shows the operation sequence.
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Spansion® SLC NAND Flash Memory for Embedded
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D a t a S h e e t ( P r e l i m i n a r y )
3.19 Read Parameter Page
The device supports the ONFI Read Parameter Page operation, initiated by writing ECh to the command
register, followed by an address input of 00h. The command register remains in Parameter Page mode until
further commands are issued to it. Figure 6.37 on page 61 shows the operation sequence, while Table 3.12
explains the parameter fields.
Table 3.12 Parameter Page Description (Sheet 1 of 3)
Byte
0-3
O/M
M
Description
Values
4Fh, 4Eh, 46h, 49h
02h, 00h
Revision Information and Features Block
Parameter page signature
Byte 0: 4Fh, “O”
Byte 1: 4Eh, “N”
Byte 2: 46h, “F”
Byte 3: 49h, “I”
Revision number
2-15
Reserved (0)
4-5
M
1
0
1 = supports ONFI version 1.0
Reserved (0)
Features supported
5-15
Reserved (0)
1 = supports odd to even page Copyback
1 = supports interleaved operations
1 = supports non-sequential page programming
1 = supports multiple LUN operations
1 = supports 16-bit data bus width
S34ML01G1: 14h, 00h
S34ML02G1: 1Ch, 00h
S34ML04G1: 1Ch, 00h
4
3
2
1
0
6-7
8-9
M
M
Optional commands supported
6-15
Reserved (0)
5
4
3
2
1
0
1 = supports Read Unique ID
1 = supports Copyback
1 = supports Read Status Enhanced
1 = supports Get Features and Set Features
1 = supports Read Cache commands
1 = supports Page Cache Program command
S34ML01G1: 12h, 00h
S34ML02G1: 1Bh, 00h
S34ML04G1: 1Bh, 00h
10-31
32-43
Reserved (0)
00h
Manufacturer Information Block
53h, 50h, 41h, 4Eh, 53h, 49h,
4Fh, 4Eh, 20h, 20h, 20h, 20h
M
Device manufacturer (12 ASCII characters)
S34ML01G1: 53h, 33h, 34h,
4Dh, 4Ch, 30h, 31h, 47h, 31h,
20h, 20h, 20h, 20h, 20h, 20h,
20h, 20h, 20h, 20h, 20h
S34ML02G1: 53h, 33h, 34h,
4Dh, 4Ch, 30h, 32h, 47h, 31h,
20h, 20h, 20h, 20h, 20h, 20h,
20h, 20h, 20h, 20h, 20h
44-63
M
Device model (20 ASCII characters)
S34ML04G1: 53h, 33h, 34h,
4Dh, 4Ch, 30h, 34h, 47h, 31h,
20h, 20h, 20h, 20h, 20h, 20h,
20h, 20h, 20h, 20h, 20h
64
M
O
JEDEC manufacturer ID
Date code
01h
00h
00h
65-66
67-79
Reserved (0)
Memory Organization Block
80-83
84-85
86-89
90-91
92-95
M
M
M
M
M
Number of data bytes per page
Number of spare bytes per page
Number of data bytes per partial page
Number of spare bytes per partial page
Number of pages per block
00h, 08h, 00h, 00h
40h, 00h
00h, 02h, 00h, 00h
10h, 00h
40h, 00h, 00h, 00h
September 6, 2012 S34ML01G1_04G1_10
Spansion® SLC NAND Flash Memory for Embedded
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D a t a S h e e t ( P r e l i m i n a r y )
Table 3.12 Parameter Page Description (Sheet 2 of 3)
Byte
96-99
100
O/M
M
Description
Values
S34ML01G1: 00h, 04h, 00h, 00h
S34ML02G1: 00h, 08h, 00h, 00h
S34ML04G1: 00h, 10h, 00h, 00h
Number of blocks per logical unit (LUN)
M
Number of logical units (LUNs)
Number of address cycles
01h
S34ML01G1: 22h
S34ML02G1: 23h
S34ML04G1: 23h
101
M
4-7
0-3
Column address cycles
Row address cycles
102
M
Number of bits per cell
01h
S34ML01G1: 14h, 00h
S34ML02G1: 28h, 00h
S34ML04G1: 50h, 00h
103-104
M
Bad blocks maximum per LUN
105-106
107
M
M
M
M
Block endurance
01h, 05h
01h
Guaranteed valid blocks at beginning of target
Block endurance for guaranteed valid blocks
Number of programs per page
108-109
110
01h, 03h
04h
Partial programming attributes
5-7
4
Reserved
1 = partial page layout is partial page data followed by
partial page spare
Reserved
111
M
00h
01h
1-3
0
1 = partial page programming has constraints
112
113
M
M
Number of bits ECC correctability
S34ML01G1: 00h
S34ML02G1: 01h
S34ML04G1: 01h
Number of interleaved address bits
4-7
0-3
Reserved (0)
Number of interleaved address bits
Interleaved operation attributes
4-7
3
2
1
0
Reserved (0)
S34ML01G1: 00h
S34ML02G1: 04h
S34ML04G1: 04h
Address restrictions for program cache
1 = program cache supported
1 = no block address restrictions
Overlapped / concurrent interleaving support
114
O
115-127
128
Reserved (0)
00h
0Ah
Electrical Parameters Block
M
M
I/O pin capacitance
Timing mode support
6-1
5
4
3
2
Reserved (0)
1 = supports timing mode 5
1 = supports timing mode 4
1 = supports timing mode 3
1 = supports timing mode 2
1 = supports timing mode 1
1 = supports timing mode 0, shall be 1
129-130
07h, 00h
1
0
Program cache timing mode support
6-1
5
4
3
2
Reserved (0)
1 = supports timing mode 5
1 = supports timing mode 4
1 = supports timing mode 3
1 = supports timing mode 2
1 = supports timing mode 1
1 = supports timing mode 0
131-132
O
07h, 00h
BCh, 02h
1
0
133-134
135-136
M
M
t
t
Maximum page program time (µs)
Maximum block erase time (µs)
PROG
S34ML01G1: B8h, 0Bh
S34ML02G1: 10h, 27h
S34ML04G1: 10h, 27h
BERS
137-138
139-140
141-163
M
M
t
t
Maximum page read time (µs)
19h, 00h
64h, 00h
00h
R
Minimum Change Column setup time (ns)
CCS
Reserved (0)
Vendor Block
164-165
M
Vendor specific Revision number
00h
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Spansion® SLC NAND Flash Memory for Embedded
S34ML01G1_04G1_10 September 6, 2012
D a t a S h e e t ( P r e l i m i n a r y )
Table 3.12 Parameter Page Description (Sheet 3 of 3)
Byte
O/M
Description
Values
166-253
Vendor specific
00h
S34ML01G1: 57h, F5h
S34ML02G1: 85h, 3Ah
S34ML04G1: FBh, 71h
254-255
M
Integrity CRC
Redundant Parameter Pages
256-511
512-767
768+
M
M
O
Value of bytes 0-255
Value of bytes 0-255
Repeat Value of bytes 0-255
Repeat Value of bytes 0-255
FFh
Additional redundant parameter pages
Note:
1. O” Stands for Optional, “M” for Mandatory.
3.20 One-Time Programmable (OTP) Entry
The device contains a one-time programmable (OTP) area, which is accessed by writing 29h-17h-04h-19h to
the command register. The device is then ready to accept Page Read and Page Program commands (refer to
Page Read and Page Program on page 20). The OTP area is of a single erase block size (64 pages), and
hence only row addresses between 00h and 3Fh are allowed. The host must issue the Reset command (refer
to Reset on page 26) to exit the OTP area and access the normal flash array. The Block Erase command is
not allowed in the OTP area. Refer to Figure 6.38 on page 62 for more detail on the OTP Entry command
sequence.
4. Signal Descriptions
4.1
Data Protection and Power On / Off Sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An
internal voltage detector disables all functions whenever VCC is below about 1.8V (3V device).
The power-up and power-down sequence is shown in Figure 6.39 on page 62, in this case VCC and VCCQ on
the one hand (and VSS and VSSQ on the other hand) are shorted together at all times.
The Ready/Busy signal shall be valid within 100 µs after the power supplies have reached the minimum
values (as specified on), and shall return to one within 5 ms (max).
During this busy time, the device executes the initialization process (cam reading), and dissipates a current
ICC0 (30 mA max), in addition, it disregards all commands excluding Read Status Register (70h).
At the end of this busy time, the device defaults into “read setup”, thus if the user decides to issue a page
read command, the 00h command may be skipped.
The WP# pin provides hardware protection and is recommended to be kept at VIL during power-up and
power-down. A recovery time of minimum 100 µs is required before the internal circuit gets ready for any
command sequences as shown in Figure 6.39 on page 62. The two-step command sequence for
program/erase provides additional software protection.
September 6, 2012 S34ML01G1_04G1_10
Spansion® SLC NAND Flash Memory for Embedded
35
D a t a S h e e t ( P r e l i m i n a r y )
4.2
Ready/Busy
The Ready/Busy output provides a method of indicating the completion of a page program, erase, copyback,
or read completion. The R/B# pin is normally high and goes to low when the device is busy (after a reset,
read, program, erase operation). It returns to high when the internal controller has finished the operation. The
pin is an open-drain driver thereby allowing two or more R/B# outputs to be Or-tied. Because pull-up resistor
value is related to tr (R/B#) and current drain during busy (ibusy), an appropriate value can be obtained with
the reference chart shown in Figure 4.1.
Figure 4.1 Ready/Busy Pin Electrical Application
Rp
3.3V device - VOL : 0.4V. VOH : 2.4V
ibusy
Vcc
Ready
VCC
R/B#
open drain output
VOL : 0.4V, VOH : 2.4V
VOH
C
L
VOL
Busy
tf
tr
GND
Device
Rp vs. tr, tf and Rp vs. ibusy
@ Vcc = 3.3V, Ta = 25°C, C
L
=50 pF
200
ibusy [A]
ibusy [A]
3m
2.4
ibusy
300n
3m
2m
1m
150
1.2
200n
100n
2m
1m
100
0.8
tr
50
0.6
1.8
1.8
1.8
tf
1.8
tr,tf [c]
1k
2k
3k
4k
Rp(ohm)
Rp value guidence
Vcc (Max.) - VOL (Max.)
3.2V
Rp (min. 3.3V part) =
=
I
OL +∑I
L
8mA + ∑I
L
where IL is the sum of the input currents of all devices tied to the R/B# pin.
Rp(max) is determined by maximum permissible limit of tr.
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Spansion® SLC NAND Flash Memory for Embedded
S34ML01G1_04G1_10 September 6, 2012
D a t a S h e e t ( P r e l i m i n a r y )
4.3
Write Protect Operation
Erase and program operations are aborted if WP# is driven low during busy time, and kept low for about
100 ns. Switching WP# low during this time is equivalent to issuing a Reset command (FFh). The contents of
memory cells being altered are no longer valid, as the data will be partially programmed or erased. The
R/B# pin will stay low for tRST (similarly to Figure 6.26 on page 55). At the end of this time, the command
register is ready to process the next command, and the Status Register bit I/O6 will be cleared to 1, while I/O7
value will be related to the WP# value. Refer to Table 3.5 on page 26 for more information on device status.
Erase and program operations are enabled or disabled by setting WP# to high or low respectively, prior to
issuing the setup commands (80h or 60h). The level of WP# shall be set tWW ns prior to raising the WE# pin
for the set up command, as explained in Figure 6.40 and Figure 6.41 on page 63.
Figure 4.2 WP# Low Timing Requirements during Program/Erase Command Sequence
WE#
I/O[7:0]
WP#
Valid
Sequence
Aborted
> 100 ns
September 6, 2012 S34ML01G1_04G1_10
Spansion® SLC NAND Flash Memory for Embedded
37
D a t a S h e e t ( P r e l i m i n a r y )
5. Electrical Characteristics
5.1
Valid Blocks
Table 5.1 Valid Blocks
Parameter
Symbol
Min
S34ML01G1 Device
1004
Typ
—
Max
1024
2048
4096
Unit
Valid Block Number, 1 Gb
Valid Block, 2 Gb
N
N
N
Blocks
Blocks
Blocks
VB
VB
VB
S34ML02G1 Device
2008
—
S34ML04G1 Device
4016
Valid Block, 4 Gb
—
5.2
Absolute Maximum Ratings
Table 5.2 Absolute Maximum Ratings
Parameter
Symbol
Value 3.0
Unit
Ambient Operating Temperature (Commercial Temperature Range)
0 to 70
°C
Ambient Operating Temperature (Extended Temperature Range)
(S34ML01G1)
T
-25 to +85
°C
A
Ambient Operating Temperature (Industrial Temperature Range)
Temperature under Bias
-40 to +85
°C
°C
T
-50 to +125
BIAS
-60 to +150 (S34ML02G1,
S34ML04G1)
Storage Temperature
T
°C
STG
-65 to +150 (S34ML01G1)
-0.6 to +4.6
Input or Output Voltage
Supply Voltage
V
(2)
V
V
IO
V
-0.6 to +4.6
CC
Notes:
1. Except for the rating “Operating Temperature Range”, stresses above those listed in the table Absolute Maximum Ratings “Absolute
Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any
other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability.
2. Minimum Voltage may undershoot to -2V during transition and for less than 20 ns during transitions.
5.3
AC Test Conditions
Table 5.3 AC Test Conditions
Parameter
Value
0.0V to V
5 ns
Input Pulse Levels
CC
Input Rise And Fall Times
Input And Output Timing Levels
Output Load (2.7V - 3.6V)
V
/ 2
CC
1 TTL Gate and CL = 50 pF
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Spansion® SLC NAND Flash Memory for Embedded
S34ML01G1_04G1_10 September 6, 2012
D a t a S h e e t ( P r e l i m i n a r y )
5.4
AC Characteristics
Table 5.4 AC Characteristics
Parameter
Symbol
Min
10
5
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ALE to RE# delay
t
AR
ALE hold time
t
—
ALH
ALE setup time
t
10
70
10
5
—
ALS
ADL
Address to data loading time
CE# low to RE# low
CE# hold time
t
—
t
—
CR
CH
t
—
CE# high to output High-Z
CLE hold time
t
—
5
30
—
CHZ
t
t
CLH
CLR
CLE to RE# delay
10
12
15
10
20
5
—
CLE setup time
t
—
CLS
CE# high to output hold
CE# high to ALE or CLE don't care
CE# setup time
t
—
COH
t
—
CSD
t
—
CS
DH
DS
Data hold time
t
t
—
Data setup time
10
—
0
—
Data transfer from cell to register
Output High-Z to RE# low
Read cycle time
t
25
—
R
t
IR
t
25
—
10
15
100
—
5
—
RC
RE# access time
t
20
—
REA
REH
RE# high hold time
RE# high to output hold
RE# high to WE# low
RE# high to output High-Z
RE# low to output hold
RE# pulse width
t
t
—
RHOH
t
—
RHW
t
100
—
RHZ
t
RLOH
t
12
20
—
—
25
10
60
12
100
—
RP
RR
Ready to RE# low
t
—
Device resetting time (Read/Program/Erase)
WE# high to busy
t
5/10/500
100
—
RST
t
WB
WC
WH
Write cycle time
t
WE# high hold time
WE# high to RE# low
WE# pulse width
t
—
t
—
WHR
t
—
WP
Write protect time
t
—
WW
Notes:
1. The time to Ready depends on the value of the pull-up resistor tied to R/B# pin.
2. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5 µs.
September 6, 2012 S34ML01G1_04G1_10
Spansion® SLC NAND Flash Memory for Embedded
39
D a t a S h e e t ( P r e l i m i n a r y )
5.5
DC Characteristics
Table 5.5 DC Characteristics and Operating Conditions (Sheet 1 of 2)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
Power-Up Current
Power-On Current
(S34ML02G1, S34ML04G1)
I
—
15
30
mA
CC0
CC0
(Refer to Section 4.1)
Power-On-Reset Current
(S34ML01G1)
FFh command input after
power on
50 per
device
I
—
—
—
mA
mA
t
= see Table 5.4
RC
CE#=V , I
= 0 mA
IL OUT
15
30
30
(S34ML02G1,
S34ML04G1)
Sequential
Read
I
CC1
t
= t (min)
RC
RC
CE# =V , I
= 0 mA
—
15
mA
IL OUT
(S34ML01G1)
Normal (S34ML01G1)
Normal (S34ML02G1)
Normal (S34ML04G1)
Cache (S34ML01G1)
Cache (S34ML02G1)
Cache (S34ML04G1)
— (S34ML01G1)
—
—
—
—
—
—
—
—
—
15
15
—
15
20
—
15
—
15
30
30
30
30
40
40
30
30
30
mA
mA
mA
mA
mA
mA
mA
mA
mA
Operating Current
Program
I
I
CC2
Erase
— (S34ML02G1)
CC3
— (S34ML04G1)
CE# = V
,
IH
Standby Current, (TTL)
I
I
—
—
1
mA
CC4
WP# = 0V/Vcc
CE# = V –0.2,
CC
Standby Current, CMOS
Input Leakage Current
—
—
—
—
—
10
—
—
—
—
50
10
10
10
10
µA
µA
µA
µA
µA
CC5
WP# = 0/V
CC
V
= 0 to V (max)
CC
IN
(S34ML01G1, S34ML02G1)
I
LI
Input Leakage Current
(S34ML04G1)
V
= 0 to 3.6V
IN
Output Leakage Current
(S34ML01G1, S34ML02G1)
V
= 0 to V (max)
CC
OUT
I
LO
Output Leakage Current
(S34ML04G1)
V
= 0 to 3.6V
OUT
Input High Voltage
Input Low Voltage
V
—
V
x 0.8
—
—
V + 0.3
CC
V
V
IH
CC
V
—
-0.3
V
x 0.2
CC
IL
I
= –100 µA
OH
—
—
—
—
V
V
(S34ML02G1,
S34ML04G1)
V
OH
I
= –400 µA
OH
—
—
—
(S34ML02G1,
S34ML04G1)
Output High Voltage
I
= –400 µA
OH
V
V
(S34ML01G1)
V
OH
I
= 100 µA
OH
V
-0.1
—
CC
(S34ML01G1)
40
Spansion® SLC NAND Flash Memory for Embedded
S34ML01G1_04G1_10 September 6, 2012
D a t a S h e e t ( P r e l i m i n a r y )
Table 5.5 DC Characteristics and Operating Conditions (Sheet 2 of 2)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
V
I
= –100 µA
= 2.1 mA
OL
Output Low Voltage
V
OL
I
—
—
8
—
—
10
0.4
—
V
OL
V
V
= 0.1V
= 0.4V
mA
mA
OL
OL
Output Low Current (R/B#)
I
OL(R/B#)
—
V
Supply Voltage
CC
V
—
—
1.8
—
V
(erase and program lockout)
LKO
(S34ML01G1)
Notes:
1. All V
and V pins, and V and V
pins respectively are shorted together.
SSQ
CCQ
CC
SS
2. Values listed in this table refer to the complete voltage range for V and V
and to a single device in case of device stacking.
CC
CCQ
3. All current measurements are performed with a 0.1 µF capacitor connected between the V Supply Voltage pin and the V Ground pin.
CC
SS
4. Standby current measurement can be performed after the device has completed the initialization process at power up. Refer to
Section 4.1 for more details.
5.6
5.7
Pin Capacitance
Table 5.6 Pin Capacitance (TA = 25°C, f=1.0 MHz)
Parameter
Symbol
Test Condition
Min
—
Max
10
Unit
pF
Input
C
V
= 0V
= 0V
IN
IO
IN
Input / Output
C
V
—
10
pF
IL
Note:
1. For the stacked devices version the Input is 10 pF x [number of stacked chips] and the Input/Output is 10 pF x [number of stacked chips].
Program / Erase Characteristics
Table 5.7 Program / Erase Characteristics
Parameter
Description
Min
—
Typ
200
0.5
5
Max
700
1
Unit
µs
Program Time / Multiplane Program Time (2)
t
PROG
Dummy Busy Time for Two Plane Program (S34ML02G1, S34ML04G1)
Cache Program short busy time (S34ML02G1, S34ML04G1)
t
—
µs
DBSY
t
—
t
µs
CBSYW
NOP
PROG
4
Main + Spare
Array
Number of partial Program Cycles in the same page
—
—
Cycle
Block Erase Time / Multiplane Erase Time (S34ML02G1, S34ML04G1)
Block Erase Time (S34ML01G1)
t
t
—
—
—
3.5
2
10
3
ms
ms
µs
BERS
BERS
Read Cache busy time
t
3
t
R
CBSYR
Notes:
1. Typical program time is defined as the time within which more than 50% of the whole pages are programmed (V = 3.3V, 25°C).
CC
2. Copy Back Read and Copy Back Program for a given plane must be between odd address pages or between even address pages for the
device to meet the program time (t ) specification. Copy Back Program may not meet this specification when copying from an odd
PROG
address page (source page) to an even address page (target page) or from an even address page (source page) to an odd address page
(target page).
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D a t a S h e e t ( P r e l i m i n a r y )
6. Timing Diagrams
6.1
Command Latch Cycle
Command Input bus operation is used to give a command to the memory device. Commands are accepted
with Chip Enable low, Command Latch Enable High, Address Latch Enable low, and Read Enable High and
latched on the rising edge of Write Enable. Moreover for commands that starts a modify operation (write/
erase) the Write Protect pin must be high.
Figure 6.1 Command Latch Cycle
tCL
S
tCLH
tCH
CLE
CE#
tCS
tWP
WE#
tALS
tALH
ALE
I/Ox
tDS
tDH
Command
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Spansion® SLC NAND Flash Memory for Embedded
S34ML01G1_04G1_10 September 6, 2012
D a t a S h e e t ( P r e l i m i n a r y )
6.2
Address Latch Cycle
Address Input bus operation allows the insertion of the memory address. To insert the 27 (x8 Device)
addresses needed to access the 1 Gb, four write cycles are needed. Addresses are accepted with Chip
Enable low, Address Latch Enable High, Command Latch Enable low, and Read Enable High and latched on
the rising edge of Write Enable. Moreover, for commands that start a modify operation (write/ erase) the Write
Protect pin must be high.
Figure 6.2 Address Latch Cycle
tCLS
CLE
tCS
tWC
tWC
tWC
tWC
CE#
tWP
tWP
tWP
tWP
WE#
ALE
tWH
tWH
tWH
tWH
tALH
tALS
tALS tALH
tALS tALH
tALS tALH
tALS tALH
tDH
tDH
tDH
tDH
tDH
tDS
tDS
tDS
tDS
tDS
Col.
Add2
Col.
Add1
Row.
Add1
Row.
Add2
Row.
Add3
I/Ox
6.3
Data Input Cycle Timing
Data Input bus operation allows the data to be programmed to be sent to the device. The data insertion is
serially, and timed by the Write Enable cycles. Data is accepted only with Chip Enable low, Address Latch
Enable low, Command Latch Enable low, Read Enable High, and Write Protect High and latched on the rising
edge of Write Enable.
Figure 6.3 Input Data Latch Cycle
tCLH
CLE
tCH
CE#
tWC
tALS
ALE
tWP
tWP
tWP
WE#
I/Ox
tWH
tDH
tWH
tDH
tDH
tDS
Din
tDS
tDS
Din final
Din 0
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D a t a S h e e t ( P r e l i m i n a r y )
6.4
Data Output Cycle Timing (CLE=L, WE#=H, ALE=L, WP#=H)
Figure 6.4 Data Output Cycle Timing
tRC
tCHZ
CE#
tREH
tREA
tREA
tREA
tCOH
RE#
tRHZ
tRHZ
tRHOH
I/Ox
Dout
Dout
Dout
tRR
R/B#
Notes:
1. Transition is measured at 200 mV from steady state voltage with load.
2. This parameter is sampled and not 100% tested.
3.
4.
t
t
is valid when frequency is higher than 33 MHz.
RLOH
starts to be valid when frequency is lower than 33 MHz.
RHOH
6.5
Data Output Cycle Timing (EDO Type, CLE=L, WE#=H, ALE=L)
Figure 6.5 Data Output Cycle Timing (EDO)
tCR
CE#
tRC
tCHZ
tCOH
RE#
tRP
tREH
tRHZ
tREA
tREA
tRLOH
tRHOH
I/Ox
Dout
Dout
tRR
R/B#
Notes:
1. Transition is measured at 200 mV from steady state voltage with load.
2. This parameter is sampled and not 100% tested.
3.
4.
t
t
is valid when frequency is higher than 33 MHz.
RLOH
starts to be valid when frequency is lower than 33 MHz.
RHOH
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Spansion® SLC NAND Flash Memory for Embedded
S34ML01G1_04G1_10 September 6, 2012
D a t a S h e e t ( P r e l i m i n a r y )
6.6
Page Read Operation
Figure 6.6 Page Read Operation (Read One Page)
CLE
tCLR
CE#
WE#
ALE
RE#
tWC
tCSD
tWB
tAR
tR
tRC
tRHZ
tRR
Col.
Add. 2
Row
Add. 2
Dout
N +1
Row
Add. 3
Dout
M
Col.
Add. 1
Row
Add. 1
00h
30h
Dout N
I/Ox
Column Address
Row Address
R/B#
Busy
6.7
Page Read Operation (Intercepted by CE#)
Figure 6.7 Page Read Operation Intercepted by CE#
CLE
tCLR
CE#
WE#
ALE
RE#
I/Ox
tCSD
tCHZ
tCOH
tWB
tAR
tRC
tR
tRR
Dout
N +1
Dout
N +2
Col.
Add. 2
Row
Add. 2
Row
Add. 3
Col.
Add. 1
Row
Add. 1
00h
Dout N
30h
Column Address
Row Address
R/B#
Busy
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D a t a S h e e t ( P r e l i m i n a r y )
6.8
Page Read Operation Timing with CE# Don’t Care
Figure 6.8 Page Read Operation Timing with CE# Don’t Care
CE# don’t care
CE#
CLE
ALE
WE#
tRC
RE#
tRR
Dout
N
Dout
N + 1
Dout
Dout
M
Dout
M + 1
Col.
Col.
Row
Row
Row
Add. 1 Add. 2 Add. 1 Add. 2 Add. 3
Dout
N + 2
Dout
Dout
N + 5
Dout
M + 2
00h
30h
I/Ox
N + 3 N + 4
tR
R/B#
: Don’t Care (V or V
)
IL
IH
tCR
CE#
tREA
RE#
I/Ox
Dout
6.9
Page Program Operation
Figure 6.9 Page Program Operation
CLE
CE#
tWC
tWC
tWC
WE#
ALE
RE#
tADL
tWHR
tWB
tPROG
Col.
Add2
Row.
Add3
Col.
Add1
Row.
Add2
Row.
Add1
Din
Din
M
I/Ox
80h
10h
70h
I/O0
N
Serial Data
Input Command
1 up to m byte
Serial Input
Program
Command
Read Status
Command
Column Address
Row Address
R/B#
I/O0=0 Successful Program
I/O0=1 Error in Program
Note:
1.
t
is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.
ADL
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Spansion® SLC NAND Flash Memory for Embedded
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6.10 Page Program Operation Timing with CE# Don’t Care
Figure 6.10 Page Program Operation Timing with CE# Don’t Care
CE# don’t care
CE#
CLE
ALE
WE#
RE#
Din
M
Din
P
Din
P + 1
Din
R
Col.
Add. 1
Col.
Row
Row
Row
Din
N
Din
N + 1
80h
I/Ox
10h
Add. 2 Add. 1 Add. 2 Add. 3
: Don’t Care
tCH
tCS
tWP
CE#
WE#
6.11 Page Program Operation with Random Data Input
Figure 6.11 Random Data Input
CLE
CE#
tWC
tWC
tWC
WE#
ALE
tADL
tADL
tWHR
tWB
tPROG
RE#
I/Ox
Col.
Add1
Col.
Add2
Col.
Add1
Col.
Add2
Row
Add1
Row
Add2
Row
Add3
Din
M
Din
Din
Din
K
85h
10h
80h
70h
IO0
J
N
Read Status
Command
Serial Data
Input Command
Random Data
Input Command
Program
Command
Column Address
Column Address
Column Address
Serial Input
R/B#
Notes:
1.
t
is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.
ADL
2. For EDC operation only one time Random Data Input is possible at same address.
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D a t a S h e e t ( P r e l i m i n a r y )
6.12 Random Data Output In a Page
Figure 6.12 Random Data Output
CLE
tCLR
CE#
WE#
tWB
tWHR
tAR
tRHW
ALE
RE#
tRC
tR
tREA
tRR
Dout
N +1
Dout
M +1
Col.
Add. 2
Row
Add. 2
Row
Add. 3
Col.
Add. 2
Col.
Add. 1
Row
Add. 1
Col.
Add. 1
00h
05h
Dout N
E0h
Dout M
30h
I/Ox
Row Address
Column Address
Column Address
R/B#
Busy
6.13 Multiplane Page Program Operation — S34ML02G1 and S34ML04G1
Figure 6.13 Multiplane Page Program
CLE
CE#
tWC
WE#
tDBSY
tWB
tWB
tPROG
tWHR
ALE
RE#
I/Ox
tADL
tADL
Row
Row
Row
Col.
Col.
Col.
Row
Col.
Din
M
Din
M
Row
Din
N
Din
Row
81h
80h
11h
Program
Command
(Dummy)
10h
IO
Read Staus
70h
Add1
Add3
Add2
Add1
Add1
Add2 Add1
Add2
N
Add2
Add3
1 up to 2112 byte
Serial Data
Program Confirm
Column Address
Page Row Address
Data Serial Input
Input Command
Command (True)
Command
R/B#
tDBSY: typ. 500 µs
max. 1 µs
Ex.) Two-Plane Page Program
tDBSY
tPROG
R/B#
I/O0~7
Address & Data Input
10h
80h
Address & Data Input
11h
81h
70h
Col Add 1,2 & Row Add 1,2,3
(2112 byte data)
Col Add 1,2 & Row Add 1,2,3
(2112 byte data)
Note
A0 ~ A11: Valid
A0 ~ A11: Valid
A12 ~ A17: Valid
A18: Fixed ‘High’
A19 ~ A28: Valid
A12 ~ A17: Fixed ‘Low’
A18: Fixed ‘Low’
A19 ~ A28: Fixed ‘Low’
Note:
1. Any command between 11h and 81h is prohibited except 70h, 78h, and FFh.
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Spansion® SLC NAND Flash Memory for Embedded
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D a t a S h e e t ( P r e l i m i n a r y )
Figure 6.14 Multiplane Page Program (ONFI 1.0 Protocol)
ADDR ADDR ADDR
Cycle Type
ADDR ADDR
DIN
...
CMD
11h
CMD
80h
DIN
D0A
DIN
D1A
DIN
DnA
tADL
C1A
C2A
R2A
R3A
DQx
R1A
tADL
tIPBSY
SR[6]
A
Cycle Type
DQx
DIN
...
ADDR ADDR ADDR
DIN
D0B
DIN
DIN
DnB
CMD
10h
CMD
80h
ADDR ADDR
tADL
D1BA
C1B
C2B
R1B
R2B
R3B
tADL
tPROG
SR[6]
Notes:
1. C1A-C2A Column address for page A. C1A is the least significant byte.
2. R1A-R3A Row address for page A. R1A is the least significant byte.
3. D0A-DnA Data to program for page A.
4. C1B-C2B Column address for page B. C1B is the least significant byte.
5. R1B-R3B Row address for page B. R1B is the least significant byte.
6. D0B-DnB Data to program for page B.
6.14 Block Erase Operation
Figure 6.15 Block Erase Operation (Erase One Block)
CLE
CE#
tWC
WE#
tWHR
tBERS
tWB
ALE
RE#
70h
Row Add1 Row Add2
Row Add3
D0h
I/O0
60h
I/Ox
Row Address
BUSY
R/B#
Auto Block Erase
Setup Command
I/O0=0 Successful Erase
I/O0=1 Error in Erase
Erase Command
Read Status
Command
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D a t a S h e e t ( P r e l i m i n a r y )
6.15 Multiplane Block Erase — S34ML02G1 and S34ML04G1
Figure 6.16 Multiplane Block Erase
CLE
CE#
tWC
tWC
WE#
ALE
tWHR
tWB
tBERS
RE#
I/Ox
60h Row Add1 Row Add2
D0h
Row Add3
Row Add3
I/O0
60h
Row Add1 Row Add2
70h
Row Address
Row Address
Busy
R/B#
Block Erase Setup Command1
Block Erase Setup Command2
Erase Confirm Command
Read Status Command
I/O 1 = 0 Successful Erase
I/O 1 = 1 Error in plane
Ex.) Address Restriction for Two-Plane Block Erase Operation
R/B#
tBERS
I/O0~7
Address
Row Add1,2,3
Address
60h
60h
D0h
70h
Row Add1,2,3
A12 ~ A17 : Fixed ‘Low’
A12 ~ A17 : Fixed ‘Low’
A18
: Fixed ‘Low’
A18
: Fixed ‘High’
A19 ~ A28 : Fixed ‘Low’
A19 ~ A28 : Valid
Figure 6.17 Multiplane Block Erase (ONFI 1.0 Protocol)
CLE
WE#
ALE
RE#
IOx
R2B R3B
R1A
R1B
D0h
60h
R2A R3A
60h
D1h
t
IEBSY
t
BERS
SR[6]
Notes:
1. R1A-R3A Row address for block on plane 0. R1A is the least significant byte.
2. R1B-R3B Row address for block on plane 1. R1B is the least significant byte.
3. Same restrictions on address of blocks on plane 0(A) and 1(B) and allowed commands as Figure 6.21 apply.
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Spansion® SLC NAND Flash Memory for Embedded
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6.16 Copy Back Read with Optional Data Readout — S34ML02G1 and
S34ML04G1
Figure 6.18 Copy Back Read with Optional Data Readout
Source
Add Inputs
Target
Add Inputs
SR0/
EDC Reg
70h/
7Bh
10h
00h
35h
Data Outputs
85h
I/O
Copy Back
Code
Read
Code
Read Status Register/
EDC Register
tR
(Read Busy time)
tPROG
(Program Busy time)
R/B#
Busy
Busy
6.17 Copy Back Program Operation With Random Data Input — S34ML02G1 and
S34ML04G1
Figure 6.19 Copy Back Program with Random Data Input
Source
Add Inputs
Target
Add Inputs
70h/
7Bh
SR0/
EDC Reg
00h
35h
Data Outputs
85h
10h
I/O
Read
Code
Copy Back
Code
Read Status Register/
EDC Register
tR
(Read Busy time)
tPROG
(Program Busy time)
R/B#
Busy
Busy
Source
Add Inputs
Target
Add Inputs
2 Cycle
Add Inputs
85h
10h
70h
I/O
00h
35h
85h
SR0
Data
Data
Read
Code
Copy Back
Code
Unlimited number of repetitions
Read Status Register
tR
(Read Busy time)
tPROG
(Program Busy time)
R/B#
Busy
Busy
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D a t a S h e e t ( P r e l i m i n a r y )
6.18 Multiplane Copy Back Program — S34ML02G1 and S34ML04G1
Figure 6.20 Multiplane Copy Back Program
tR
tR
R/B#
I/Ox
35h
35h
00h
00h
Add. (5 cycles)
Add. (5 cycles)
Col. Add. 1, 2 and Row Add. 1, 2, 3
Source Address on Plane 0
Col. Add. 1, 2 and Row Add. 1, 2, 3
Source Address on Plane 1
1
tDBSY
tPROG
R/B#
I/Ox
85h
Add. (5 cycles)
81h
Add. (5 cycles)
10h
11h
70h
Note 3
Col. Add. 1, 2 and Row Add. 1, 2, 3
Destination Address
Col. Add. 1, 2 and Row Add. 1, 2, 3
Destination Address
1
A0 ~ A11 : Fixed ‘Low’
A12 ~ A17 : Fixed ‘Low’
A0 ~ A11 : Fixed ‘Low’
A12 ~ A17 : Valid
A18
: Fixed ‘Low’
A18
: Fixed ‘High’
A19 ~ A28 : Fixed ‘Low’
A19 ~ A28 : Valid
Plane 0
Plane 1
Source Page
Source Page
Target Page
(1) : Copy Back Read on Plane 0
(2) : Copy Back Read on Plane 1
(3) : Multiplane Copy Back Program
Target Page
(1)
(2)
(3)
(3)
Data Field
Data Field
Spare Field
Spare Field
Notes:
1. Copy Back Program operation is allowed only within the same memory plane.
2. Any command between 11h and 81h is prohibited except 70h, 78h, and FFh.
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Spansion® SLC NAND Flash Memory for Embedded
S34ML01G1_04G1_10 September 6, 2012
D a t a S h e e t ( P r e l i m i n a r y )
Figure 6.21 Multiplane Copy Back Program (ONFI 1.0 Protocol)
CLE
WE#
ALE
RE#
IOx
C2D
C1D
85h
C2C R1C
R3C
85h
R1D
C1C
R2C
11h
R2
D
R3D 10h
t
t
IPBSY
PROG
SR[6]
A
Notes:
1. C1C-C2C Column address for page C. C1A is the least significant byte.
2. R1C-R3C Row address for page C. R1A is the least significant byte.
3. D0C-DnC Data to program for page C.
4. C1D-C2D Column address for page D. C1B is the least significant byte.
5. R1D-R3D Row address for page D. R1B is the least significant byte.
6. D0D-DnD Data to program for page D.
7. Same restrictions on address of pages C and D, and allowed commands as Figure 6.14 apply.
6.19 Read Status Cycle Timing
Figure 6.22 Status / EDC Read Cycle
tCLR
CLE
CE#
tCLS
tCLH
tCS
tCH
tWP
WE#
tCEA
tCHZ
tCOH
tWHR
RE#
I/Ox
tRHZ
tDH
tREA
tDS
tIR
tRHOH
70h or 7Bh
(Note 1)
Status Output
Note:
1. Extended Status Read commands F2h, F3h, F4h, and F5h are also valid for multi-die stacks.
September 6, 2012 S34ML01G1_04G1_10
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D a t a S h e e t ( P r e l i m i n a r y )
Figure 6.23 Read Status Enhanced Cycle
CLE
WE#
ALE
RE#
I/O0-7
R1 R2
78h
R3
SR
6.20 Read Status Timing
Figure 6.24 Read Status Timing
CLE
WE#
ALE
tWHR
RE#
70h
I/O0-7
SR
tREA
Figure 6.25 Read Status Enhanced Timing
CLE
WE#
ALE
tWHR
RE#
tAR
I/O0-7
R3
R1
R2
SR
78h
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Spansion® SLC NAND Flash Memory for Embedded
S34ML01G1_04G1_10 September 6, 2012
D a t a S h e e t ( P r e l i m i n a r y )
6.21 Reset Operation Timing
Figure 6.26 Reset Operation Timing
WE#
ALE
CLE
RE#
FF
I/O7:0
t
RST
R/B#
6.22 Read Cache Operation Timing
Figure 6.27 Read Cache Operation Timing
A
CE#
CLE
ALE
WE#
tWC
tWB
tWB
tWB
tRC
tRC
RE#
I/Ox
tRR
tRR
Col.
Add 1
Col.
Add 2
Row
Add 1
Row
Add 2
Row
Add 3
Dout
1
Dout
1
Dout
0
Dout
0
00h
30h
31h
31h
Dout
Page Address M + 1
Col. Add. 0
Page Address M
Column Address 00h
Page Address M
Col. Add. 0
tCBSYR
tCBSYR
tR
R/B#
1
2
3
A
CE#
CLE
ALE
WE#
tWB
tWB
tWB
tRC
tRC
tRC
RE#
I/Ox
tRR
tRR
tRR
Dout
1
Dout
1
Dout
0
Dout
1
Dout
0
Dout
0
Dout
Dout
31h
Dout
3Fh
31h
Page Address M + 2
Page Address M + 4
Col. Add. 0
Page Address M + 3
Col. Add. 0
Col. Add. 0
tCBSYR
tCBSYR
tCBSYR
R/B#
7
9
5
6
8
4
: Don’t Care
Page N
Page N + 1
Page N
Page N + 3
Data Cache
Page Buffer
8
2
4
9
1
6
3
5
7
Page N + 3
Page N + 1
Page N + 2
Page N + 2
Page N
3
5
1
7
Cell Array
Page N
Page N + 1
Page N + 3
September 6, 2012 S34ML01G1_04G1_10
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55
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6.23 Cache Timing
Figure 6.28 “Sequential” Read Cache Timing, Start (and Continuation) of Cache Operation
As defined for
Read
CMD
31h
Cycle Type
Dout
Dn
Dout
D0
CMD
Dout
D0
Dout
...
CMD
31h
30h
I/Ox
tWB
tWB
tWB
tRR
tRR
tCBSYR
tR
tCBSYR
SR[6]
Figure 6.29 “Random” Read Cache Timing, Start (and Continuation) of Cache Operation
As defined
for Read
A
ADDR ADDR ADDR
Dout
Dout
CMD
ADDR
Dout
CMD
00h
CMD
ADDR
C1
Cycle Type
Page N
C2
R1
R2
D0
. . .
30h
R3
Dn
31h
I/Ox
tRR
tR
tRR
tWB
tWB
SR[6]
tCBSYR
A
ADDR ADDR ADDR
Dout
CMD
ADDR
CMD
ADDR
C1
Cycle Type
Page R
C2
R1
R2
D0
00h
R3
31h
I/Ox
tRR
tCBSYR
tWB
SR[6]
Figure 6.30 Read Cache Timing, End Of Cache Operation
As defined for
Read Cache
(Sequential or Random)
Dout
CMD
Dout
CMD
Dout
Dout
Dout
Dout
Cycle Type
Dn
3Fh
31h
D0
D0
. . .
. . .
Dn
I/Ox
tRR
tRR
tCBSYR
tWB
tWB
tCBSYR
SR[6]
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Spansion® SLC NAND Flash Memory for Embedded
S34ML01G1_04G1_10 September 6, 2012
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6.24 Cache Program
Figure 6.31 Cache Program
CLE
CE#
tWC
tWC
WE#
ALE
tWB
RE#
I/Ox
Col.
Add1
Col.
Add1
Col.
Add2 Add1
Row.
Row.
Add2 Add3
Row.
Col.
Add2 Add1
Row.
Row.
Add2 Add3
Row.
Din
N
Din
M
Din
N
Din
M
80h
15h
15h
80h
Column Address
Row Address
Row Address
Column Address
R/B#
tCBSYW
tCBSYW
1
CLE
CE#
tWC
WE#
ALE
RE#
I/Ox
tADL
Col.
Add1 Add2
Col.
Row.
Add2
Row.
Add3
Row.
Add1
Din
Din
70h
I/O
Q
10h
80h
N
M
Column Address
Row Address
R/B#
1
tPROG
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6.25 Multiplane Cache Program — S34ML02G1 and S34ML04G1
Figure 6.32 Multiplane Cache Program
Command Input
11h
Address Input
Data Input
81h
Address Input
Data Input
15h
80h
A13~A17: Fixed ‘Low’
A18: Fixed ‘Low’
A19~A31: Fixed ‘Low’
A13~A17: Valid
A18: Fixed ‘High’
A19~A31: Valid
t
t
CBSYW
DBSY
RY/BY#
1
Return to 1
Repeat a max of 63 times
Command Input
80h
11h
Address Input
Data Input
81h
Address Input
Data Input
10h
A13~A17: Fixed ‘Low’
A18: Fixed ‘Low’
A19~A31: Fixed ‘Low’
A13~A17: Valid
A18: Fixed ‘High’
A19~A31: Valid
t
t
PROG
DBSY
RY/BY#
1
CLE
CE#
tWC
tWB
WE#
ALE
tWB
RE#
I/Ox
tADL
tADL
Din
N
Din
M
Din
N
Din
M
Col.
Col.
Row
Row
Row
Col.
Add1
Col.
Row
Row
Row
80h
11h
15h
81h
Add1
Add2
Add1
Add2
Add3
Add2
Add1
Add2
Add3
Column Address
Row Address
Row Address
Column Address
R/B#
1
tDBSY
tCBSYW
CLE
CE#
tWC
tWB
WE#
ALE
RE#
I/Ox
Col.
Add1
Col.
Row
Row
Row
Col.
Col.
Row
Row
Row
Din
N
Din
M
Din
N
Din
M
80h
81h
11h
10h
I/OQ
70h
Add2
Add1
Add2
Add3
Add1
Add2
Add1
Add2
Add3
Column Address
Row Address
Row Address
Column Address
R/B#
1
tPROG
tDBSY
Note:
1. Read Status Register (70h) is used in the figure. Read Status Enhanced (78h) can be also used.
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Figure 6.33 Multiplane Cache Program (ONFI 1.0 Protocol)
Command Input
80h
11h
Address Input
Data Input
80h
Address Input
Data Input
15h
A13~A17:Fixed”Low”
A18:Fixed”Low”
A19~A31:Fixed”Low”
A13~A17:Valid
A18:Fixed”Low”
A19~A31:Fixed”Low”
t
t
PCBSY
DBSY
RY/BY#
1
Return to 1
Repeat a max of 63 times
Command Input
11h
Address Input
Data Input
80h
Address Input
Data Input
10h
80h
A13~A17:Fixed”Low”
A18:Fixed”Low”
A19~A31:Fixed”Low”
A13~A17:Valid
A18:Fixed”Low”
A19~A31:Fixed”Low”
t
t
PROG
DBSY
RY/BY#
1
CLE
CE#
tWC
tWB
WE#
ALE
tWB
RE#
IOx
tADL
tADL
Din
N
Din
M
Din
N
Din
M
Col.
Add1
Col.
Row
Row
Row
Col.
Add1
Col.
Row
Row
Row
80h
11h
15h
80h
Add2
Add1
Add2
Add3
Add2
Add1
Add2
Add3
Column Address
Row Address
Row Address
Column Address
R/B#
1
tDBSY
tCBSY
CLE
CE#
tWC
tWB
WE#
ALE
RE#
IOx
Col.
Col.
Row
Row
Row
Din
Din
Din
N
Din
M
Col.
Add1
Col.
Row
Row
Row
80h
80h
11h
10h
I/OQ
F1h
Add1
Add2
Add1
Add2
Add3
N
M
Add2
Add1
Add2
Add3
Column Address
Row Address
Row Address
Column Address
R/B#
1
tPROG
tDBSY
Notes:
1. Figure 6.33 refers to x8 case.
2. Read Status register (70h) is used in the figure. Read Status Enhanced (78h) can be also used.
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6.26 Read ID Operation Timing
Figure 6.34 Read ID Operation Timing
CLE
CE#
WE#
tWHR
tAR
ALE
RE#
tREA
1 Gb Device
90h
00h
00h
00h
01h
01h
01h
F1h
DAh
DCh
00h
90h
1Dh
95h
I/Ox
2 Gb Device
90h
44h
I/Ox
4 Gb Device
09h
I/Ox
90h
95h
54h
Read ID
Command
Address 1
Cycle
Maker
Code
Device
Code
3rd Cycle
4th Cycle
5th Cycle
6.27 Read ID2 Operation Timing
Figure 6.35 Read ID2 Operation Timing
CLE
CE#
WE#
tWHR
ALE
RE#
tREA
I/Ox
30h 65h 00h 00h
ID2 Data
ID2 Data
ID2 Data
ID2 Data
ID2 Data
02h 02h 00h 30h
Read ID2
Commands
4 Cycle Address
(Note 1)
Read ID2
Confirm
1st Cycle
2nd Cycle
3rd Cycle
4th Cycle
5th Cycle
Command
Note:
1. 4-cycle address is shown for the S34ML01G1. For S34ML02G1 and S34ML04G1, insert an additional address cycle of 00h.
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6.28 Read ONFI Signature Timing
Figure 6.36 ONFI Signature Timing
CLE
WE#
ALE
RE#
t
WHR
IO0~7
90h
20h
4Fh
4Eh
46h
49h
tREA
6.29 Read Parameter Page Timing
Figure 6.37 Read Parameter Page Timing
CLE
WE#
ALE
RE#
IO0-7
R/B#
...
...
00h
P10
ECh
P00
P01
P1
1
t
R
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D a t a S h e e t ( P r e l i m i n a r y )
6.30 OTP Entry Timing
Figure 6.38 OTP Entry Timing
CLE
WE#
ALE
I/O0-7
29h 17h 04h 19h
6.31 Power On and Data Protection Timing
Figure 6.39 Power On and Data Protection Timing
Vcc(min)
Vcc(min)
Vth
Vth
VCC
0V
don’t
care
don’t
care
CE
V
IH
Operation
5 ms max
V
IL
V
IL
WP
100 µs max
Invalid
don’t
care
Ready/Busy
Note:
1.
V
= 1.8 Volt for 3.0V supply devices.
TH
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Spansion® SLC NAND Flash Memory for Embedded
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D a t a S h e e t ( P r e l i m i n a r y )
6.32 WP# Handling
Figure 6.40 Program Enabling / Disabling Through WP# Handling
WE#
I/Ox
WE#
t
WW
t
WW
80h
10h
I/Ox
80h
10h
WP#
R/B#
WP#
R/B#
Figure 6.41 Erase Enabling / Disabling Through WP# Handling
WE#
WE#
t
WW
t
WW
I/Ox
60h
D0h
I/Ox
60h
D0h
WP#
R/B#
WP#
R/B#
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D a t a S h e e t ( P r e l i m i n a r y )
7. Physical Interface
7.1
7.1.1
Physical Diagram
48-Pin Thin Small Outline Package (TSOP1)
Figure 7.1 TS/TSR 48 — 48-lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline
NOTES:
PACKAGE
TS/TSR 48
JEDEC
MO-142 (D) DD
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).
(DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y14.5M-1982)
SYMBOL
MIN
---
NOM
---
MAX
1.20
0.15
1.05
0.23
0.27
0.16
0.21
20.20
18.50
12.10
2. PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
A
A1
A2
b1
b
3. PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK.
0.05
0.95
0.17
0.17
0.10
0.10
19.80
18.30
11.90
---
4. TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE LEADS
ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
1.00
0.20
0.22
---
5. DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD
PROTUSION IS 0.15mm (.0059") PER SIDE.
c1
c
6. DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR
PROTUSION SHALL BE 0.08mm (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX.
MATERIAL CONDITION. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT
LEAD TO BE 0.07mm (0.0028").
---
D
20.00
18.40
12.00
0.50 BASIC
0.60
---
D1
E
7. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10mm (.0039") AND 0.25mm (0.0098") FROM THE LEAD TIP.
e
8. LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM
THE SEATING PLANE.
L
0.50
0˚
0.70
8
Θ
9. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
R
0.08
---
0.20
N
48
3664 \ f16-038.10 \ 11.6.7
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Spansion® SLC NAND Flash Memory for Embedded
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7.1.2
63-Pin Ball Grid Array (BGA)
Figure 7.2 VBM063 — 63-Pin BGA, 11 mm x 9 mm Package
NOTES:
PACKAGE
JEDEC
VBM 063
1. DIMENSIONING AND TOLERANCING METHODS PER
ASME Y14.5M-1994.
M0-207(M)
NOTE
2. ALL DIMENSIONS ARE IN MILLIMETERS.
D X E
11.00 mm x 9.00 mm
PACKAGE
3. BALL POSITION DESIGNATION PER JEP 95, SECTION 4.3,
SPP-010.
SYMBOL
A
MIN
NOM
---
MAX
4.
e REPRESENTS THE SOLDER BALL GRID PITCH.
---
1.00
---
PROFILE
5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
A1
D
0.25
---
BALL HEIGHT
BODY SIZE
BODY SIZE
11.00 BSC
9.00 BSC
8.80 BSC
7.20 BSC
12
n IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS
FOR MATRIX SIZE MD X ME.
E
D1
E1
MD
ME
n
MATRIX FOOTPRINT
MATRIX FOOTPRINT
MATRIX SIZE D DIRECTION
MATRIX SIZE E DIRECTION
BALL COUNT
6
7
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
10
63
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = 0.000.
Øb
eE
eD
SD
SE
0.40
0.45
0.50
BALL DIAMETER
0.80 BSC
0.80 BSC
0.40 BSC
0.40 BSC
BALL PITCH
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
BALL PITCH
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
SOLDER BALL PLACEMENT
SOLDER BALL PLACEMENT
DEPOPULATED SOLDER BALLS
9
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
A3-A8,B2-B8,C1,C2,C9,C10
D1,D2,D9,D10,E1,E2,E9,E10
F1,F2,F9,F10,G1,G2,G9,G10
H1,H2,H9,H10,J1,J2,J9,J10
K1,K2,K9,K10,L3-L8,M3-M8
g1018-1 \ f16-038.25 \ 11.04.11
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65
D a t a S h e e t ( P r e l i m i n a r y )
8. System Interface
To simplify system interface, CE# may be unasserted during data loading or sequential data reading as
shown in Figure 8.1. By operating in this way, it is possible to connect NAND flash to a microprocessor.
Contrary to standard NAND, CE# don't care devices do not allow sequential read function.
Figure 8.1 Program Operation with CE# Don't Care
CLE
CE# don’t care
CE#
WE#
ALE
80h
Start Add. (5 Cycle)
Data Input
Data Input
10h
I/Ox
Figure 8.2 Read Operation with CE# Don't Care
CLE
If sequential row read enabled,
CE must be held low during tR.
CE# don’t care
CE#
RE#
ALE
R/B#
tR
WE#
I/Ox
00h
Start Add. (5 Cycle)
30h
Data Output(sequential)
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D a t a S h e e t ( P r e l i m i n a r y )
Figure 8.3 Page Programming Within a Block
Page 63
Page 31
(64)
(1)
(64)
Page 63
(32)
Page 31
(3)
(32)
(1)
(3)
(2)
(1)
Page 2
Page 1
Page 0
Page 2
Page 1
Page 0
Data Register
Data Register
Ex.) Random page program (Optional)
DATA IN : Data (1) Data (64)
From the LSB page to MSB page
DATA IN : Data (1) Data (64)
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D a t a S h e e t ( P r e l i m i n a r y )
9. Error Management
9.1
System Bad Block Replacement
Over the lifetime of the device, additional Bad Blocks may develop. In this case, each bad block has to be
replaced by copying any valid data to a new block. These additional Bad Blocks can be identified whenever a
program or erase operation reports “Fail” in the Status Register.
The failure of a page program operation does not affect the data in other pages in the same block, thus the
block can be replaced by re-programming the current data and copying the rest of the replaced block to an
available valid block. Refer to Table 9.1 and Figure 9.1 for the recommended procedure to follow if an error
occurs during an operation.
Table 9.1 Block Failure
Operation
Erase
Recommended Procedure
Block Replacement
Program
Read
Block Replacement
ECC (1 bit / 512+16 byte)
Figure 9.1 Bad Block Replacement
Block B
Block A
(2)
Data
Data
th
th
(1)
N page
Failure
N page
(3)
FFh
FFh
buffer memory of the controller
Notes:
1. An error occurs on the Nth page of Block A during a program operation.
2. Data in Block A is copied to the same location in Block B, which is a valid block.
3. The Nth page of block A, which is in controller buffer memory, is copied into the Nth page of Block B.
4. Bad block table should be updated to prevent from erasing or programming Block A.
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9.2
Bad Block Management
Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices
where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because it is
isolated from the bit line and common source line by a select transistor. The devices are supplied with all the
locations inside valid blocks erased (FFh). The Bad Block Information is written prior to shipping. Any block
where the 1st byte in the spare area of the 1st or 2nd page does not contain FFh is a Bad Block. That is, if the
first page has an FF value and should have been a non-FF value, then the non-FF value in the second page
will indicate a bad block.The Bad Block Information must be read before any erase is attempted, as the Bad
Block Information may be erased. For the system to be able to recognize the Bad Blocks based on the
original information, it is recommended to create a Bad Block table following the flowchart shown in
Figure 9.2. The host is responsible to detect and track bad blocks, both factory bad blocks and blocks that
may go bad during operation. Once a block is found to be bad, data should not be written to that block.The 1st
block, which is placed on 00h block address is guaranteed to be a valid block.
Figure 9.2 Bad Block Management Flowchart
Start
Block Address=
Block 0
Increment
Block Address
Data(1)
No
Update
Bad Block Table
=FFh?
Yes
No
Last
Block?
Yes
End
Note:
1. Check FFh at 1st byte in the spare area of the 1st and 2nd page.
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D a t a S h e e t ( P r e l i m i n a r y )
10. Ordering Information
The ordering part number is formed by a valid combination of the following:
S34ML
04G
1
00
T
F
I
00
0
Packing Type
0
3
=
=
Tray
13” Tape and Reel
Model Number
00
00
01
=
=
=
Standard Interface / ONFI (x8)
Standard Interface (x16)
ONFI (x16)
Temperature Range
Industrial (–40°C to + 85°C)
I
=
Materials Set
F
H
=
=
Lead (Pb)-free
Low Halogen
Package
B
T
=
=
BGA
TSOP
Bus Width
00
04
=
=
x8 NAND, single die
x16 NAND, single die
Technology
1
=
Spansion NAND Revision 1 (4x nm)
Density
01G
02G
04G
=
=
=
1 Gb
2 Gb
4 Gb
Device Family
S34ML - 3V
Spansion SLC NAND Flash Memory for Embedded
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local
sales office to confirm availability of specific valid combinations and to check on newly released
combinations.
Valid Combinations
Device
Family
Bus
Width
Package Temperature
Additional
Ordering Options
Packing
Type
Package
Description
Density
Technology
Type
Range
01G
02G
04G
S34ML
1
00, 04
TF, BH
I
00
0, 3
TSOP, BGA
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11. Revision History
Section
Description
Revision 01 (April 16, 2012)
Initial release
Revision 02 (May 4, 2012)
Global
Removed Spansion Confidential designation
Updated text
Read Status Enhanced
Command Set
Read ID
Updated table: Command Set
Updated table: Read ID for Supported Configurations
Removed section heading: Legacy Read ID
Updated table: Valid Blocks
Legacy Read ID
Valid Blocks
Revision 03 (May 23, 2012)
Global
Changed Cache Read to Read Cache
Updated text
General Description
Block Diagram
Addressing
Combined three block diagrams into one
Updated Address Cycle Map tables
Updated table: Busy Time in Read; updated note
Mode Selection
Updated table
Command Set
Added ‘Supported in S34ML01G1’ column
Copy Back Program
Updated text
Updated text
Updated text
Updated text
Multiplane Copy Back Program
Special Read for Copy Back
Read EDC Status Register
Read ID Byte 4 Description — S34ML01G1 table: changed Number of I/O to Spare Area Size (byte
/ 512 byte)
Read ID
Absolute Maximum Ratings
Program / Erase Characteristics
Revision 04 (May 24, 2012)
Performance
Updated Input or Output Voltage and Supply Voltage rows
Updated table
Updated Performance section
Updated Read ID for Supported Configurations table
Modified tables: Read ID Byte 3 Description, Read ID Byte 4 Description – S34ML01G1, Read ID
Byte 4 Description – S34ML02G1 and S34ML04G1, Read ID Byte 5 Description – S34ML02G1 and
S34ML04G1
Read ID
AC Test Conditions
Revision 05 (May 31, 2012)
Global
Updated table
Data Sheet designation updated from Advance Information to Preliminary
Distinctive Characteristics/Performance Updated Distinctive Characteristics and Performance section
Pin Description
Updated Pin Description table
Updated Address Cycle Map — 1 Gb Device table
Updated Address Cycle Map — 2 Gb Device table
Updated Address Cycle Map — 4 Gb Device table
Addressing
Command Set
Updated Command Set table
Revision 06 (July 13, 2012)
Performance
Corrected Page Read/Program - Sequential access: from 25ns (Max) to 25 ns (Min)
Corrected figure: 48-Pin TSOP1 Contact x8 Device
Connection Diagram
Mode Selection
Mode selection table: corrected Busy Time in Read, WE# from High to X; corrected Notes
Command Set table: added ONFI, Extended Read Status, and Read ID2 commands
Command Set
Note that all ONFI information is in the Advanced Information designation
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Spansion® SLC NAND Flash Memory for Embedded
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D a t a S h e e t ( P r e l i m i n a r y )
Section
Copy Back Program
Description
Updated section
Multiplane Copy Back Program —
S34ML02G1 and S34ML04G1
Updated section
Read ID2
Added section
Added Section
Read ONFI Signature
Note that all ONFI information is in the Advanced Information designation
Added section
Read Parameter Page
Note that all ONFI information is in the Advanced Information designation
Added section
One-Time Programmable (OTP) Entry
Program/Erase Characteristics
Note that all ONFI information is in the Advanced Information designation
Added note to table
Rearranged section
Added timing diagrams: Multiplane Block Erase (ONFI 1.0 Protocol), Multiplane Cache Program
(ONFI 1.0 Protocol), Read ID2 Operation Timing, ONFI Signature Timing, Read Parameter Page
Timing, Read ID2 Operation Timing, OTP Entry Timing
Updated timing diagrams: Page Read Operation (Read One Page), Page Read Operation
Intercepted by CE#, Page Read Operation Timing with CE# Don’t Care, Page Program Operation,
Page Program Operation Timing with CE# Don’t Care, Random Data Input, Random Data Output,
Multiplane Page Program, Block Erase Operation (Erase One Block), Reset Operation Timing, Read
Cache Operation Timing, Cache Program, Multiplane Cache Program, Read ID Operation Timing
Timing Diagrams
Note that all ONFI information is in the Advanced Information designation
Revision 07 (July 23, 2012)
Command Set
Command Set table: changed Read ONFI Signature to ‘Yes’ for Supported on S34ML01G1
Parameter Page Description table: changed Byte 254-255 Values
Valid Blocks table: removed Note 1 and Note 3
Read Parameter Page
Valid Blocks
DC Characteristics and Operating Conditions table:
corrected Output low voltage Test Conditions
DC Characteristics
corrected Output low current (R/B#) Typ and Max values
Revision 08 (August 2, 2012)
Global
Note that all ONFI information is now in the Preliminary designation
Read Parameter Page
Parameter Page Description table: updated values for bytes 6-7, 108-109, 254-255
Added TSOP (2 CE 8 Gb) diagram
Added BGA diagram
Physical Interface
Ordering Information
Appendix A
Updated data
Added Errata
Revision 09 (August 29, 2012)
Removed 8 Gb data
Global
Added x16 I/O bus width data
Revision 10 (September 6, 2012)
Connection Diagram
48-Pin TSOP1 Contact x8, x16 Devices figure: corrected pinouts
63-VFBGA Contact, x16 Device (Balls Down, Top View) figure: corrected pinouts, removed note
Command Set
Reorganized section
AC Characteristics
Corrected TALS Min and TDS Min
72
Spansion® SLC NAND Flash Memory for Embedded
S34ML01G1_04G1_10 September 6, 2012
D a t a S h e e t ( P r e l i m i n a r y )
Colophon
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limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
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September 6, 2012 S34ML01G1_04G1_10
Spansion® SLC NAND Flash Memory for Embedded
73
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