PALCE22V10-5 [CYPRESS]
Flash-erasable Reprogrammable CMOS PAL Device; 闪存擦除可再编程的CMOS PAL器件
| 型号： | PALCE22V10-5 |
| 厂家： | 
CYPRESS |
| 描述： | Flash-erasable Reprogrammable CMOS PAL Device |
| 文件： | 总13页 (文件大小：350K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PALCE22V10 is
a replacement device for
PALC22V10, PALC22V10B, and PALC22V10D.
USE ULTRA37000TM FOR
ALL NEW DESIGNS
PALCE22V10
Flash-erasable Reprogrammable
CMOS PAL® Device
• DIP, LCC, and PLCC available
Features
— 5 ns commercial version
4 ns tCO
• Low power
— 90 mA max. commercial (10 ns)
— 130 mA max. commercial (5 ns)
3 ns tS
5 ns tPD
181-MHz state machine
• CMOS Flash EPROM technology for electrical erasabil-
ity and reprogrammability
— 10 ns military and industrial versions
7 ns tCO
6 ns tS
• Variable product terms
10 ns tPD
110-MHz state machine
— 2 ×(8 through 16) product terms
• User-programmable macrocell
— Output polarity control
— 15-ns commercial, industrial, and military versions
— 25-ns commercial, industrial, and military versions
• High reliability
— Individually selectable for registered or combina-
torial operation
— Proven Flash EPROM technology
• Up to 22 input terms and 10 outputs
— 100% programming and functional testing
Logic Block Diagram (PDIP/CDIP)
V
I
I
I
I
I
I
I
I
I
I
CP/I
1
SS
12
11
10
9
8
7
6
5
4
3
2
PROGRAMMABLE
AND ARRAY
(132 X 44)
8
10
12
14
16
16
14
12
10
8
Reset
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Preset
13
I
14
15
16
17
18
19
20
21
22
23
24
I/O
9
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
I/O
0
V
CC
PLCC
Top View
LCC
Top View
Pin Configuration
4
3
2
1
2827 26
25
4
3 2 1 282726
I
I
I
5
6
7
8
9
10
11
25 I/O
24 I/O
23 I/O
2
3
4
5
6
7
8
9
10
11
I
I
I/O
I/O
I/O
2
3
4
24
23
22
21
20
19
I
NC
I
I
I
22
NC
I
I
I
N/C
N/C
21 I/O
20 I/O
19 I/O
5
6
7
I/O
I/O
I/O
5
6
7
121314 1516 1718
12131415161718
Cypress Semiconductor Corporation
Document #: 38-03027 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised April 9, 2004
USE ULTRA37000TM FOR
ALL NEW DESIGNS
PALCE22V10
Selection Guide
Generic Part Number
tPD ns
Mil/Ind
tS ns
tCO ns
Mil/Ind
ICC mA
Com’l
5
Com’l
Mil/Ind
Com’l
Com’l
130
130
90
Mil/Ind
PALCE22V10-5
PALCE22V10-7
PALCE22V10-10
PALCE22V10-15
PALCE22V10-25
3
5
4
5
7.5
10
10
15
25
6
6
7
7
8
150
120
120
15
10
15
10
15
8
90
25
15
15
90
implement logic functions in the 500- to 800-gate-array
complexity. Since each of the ten output pins may be individ-
ually configured as inputs on a temporary or permanent basis,
functions requiring up to 21 inputs and only a single output and
down to twelve inputs and ten outputs are possible. The ten
potential outputs are enabled using product terms. Any output
pin may be permanently selected as an output or arbitrarily
enabled as an output and an input through the selective use
of individual product terms associated with each output. Each
of these outputs is achieved through an individual program-
mable macrocell. These macrocells are programmable to
provide a combinatorial or registered inverting or non-inverting
output. In a registered mode of operation, the output of the
register is fed back into the array, providing current status
information to the array. This information is available for estab-
lishing the next result in applications such as control state
machines. In a combinatorial configuration, the combinatorial
output or, if the output is disabled, the signal present on the I/O
pin is made available to the array. The flexibility provided by
both programmable product term control of the outputs and
variable product terms allows a significant gain in functional
density through the use of programmable logic.
Functional Description
The Cypress PALCE22V10 is a CMOS Flash-erasable
second-generation programmable array logic device. It is
implemented with the familiar sum-of-products (AND-OR)
logic structure and the programmable macrocell.
The PALCE22V10 is executed in a 24-pin 300-mil molded DIP,
a 300-mil cerDIP, a 28-lead square ceramic leadless chip
carrier, a 28-lead square plastic leaded chip carrier, and
provides up to 22 inputs and 10 outputs. The PALCE22V10
can be electrically erased and reprogrammed. The program-
mable macrocell provides the capability of defining the archi-
tecture of each output individually. Each of the ten potential
outputs may be specified as “registered” or “combinatorial.”
Polarity of each output may also be individually selected,
allowing complete flexibility of output configuration. Further
configurability is provided through “array” configurable “output
enable” for each potential output. This feature allows the 10
outputs to be reconfigured as inputs on an individual basis, or
alternately used as a combination I/O controlled by the
programmable array.
PALCE22V10 features a variable product term architecture.
There are 5 pairs of product term sums beginning at 8 product
terms per output and incrementing by 2 to 16 product terms
per output. By providing this variable structure, the
PALCE22V10 is optimized to the configurations found in a
majority of applications without creating devices that burden
the product term structures with unusable product terms and
lower performance.
Along with this increase in functional density, the Cypress
PALCE22V10 provides lower-power operation through the use
of CMOS technology, and increased testability with Flash
reprogrammability.
Configuration Table
Registered/Combinatorial
Additional features of the Cypress PALCE22V10 include a
synchronous preset and an asynchronous reset product term.
These product terms are common to all macrocells, elimi-
nating the need to dedicate standard product terms for initial-
ization functions. The device automatically resets upon
power-up.
C1
0
C0
0
Configuration
Registered/Active LOW
Registered/Active HIGH
Combinatorial/Active LOW
Combinatorial/Active HIGH
0
1
1
0
1
1
The PALCE22V10, featuring programmable macrocells and
variable product terms, provides a device with the flexibility to
Document #: 38-03027 Rev. *B
Page 2 of 13
USE ULTRA37000TM FOR
ALL NEW DESIGNS
PALCE22V10
Macrocell
AR
OUTPUT
SELECT
MUX
D
Q
Q
S
S
0
CP
1
SP
INPUT/
FEEDBACK
MUX
S
1
C
1
C
0
MACROCELL
Document #: 38-03027 Rev. *B
Page 3 of 13
USE ULTRA37000TM FOR
ALL NEW DESIGNS
PALCE22V10
Output Current into Outputs (LOW)............................. 16 mA
DC Programming Voltage............................................. 12.5V
Latch-up Current.....................................................> 200 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ............................>2001V
Operating Range
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) ........................................... –0.5V to +7.0V
Range
Commercial
Industrial
Temperature
VCC
0°C to +75°C
–40°C to +85°C
–55°C to +125°C
5V ±5%
5V ±10%
5V ±10%
DC Voltage Applied to Outputs
in High-Z State ............................................... –0.5V to +7.0V
Military[1]
DC Input Voltage............................................ –0.5V to +7.0V
Electrical Characteristics Over the Operating Range[2]
Parameter
Description
Test Conditions
Min. Max. Unit
VOH
Output HIGH Voltage
VCC = Min.,
IN = VIH or VIL
IOH = –3.2 mA
Com’l
Mil/Ind
Com’l
Mil/Ind
2.4
V
V
I
OH = –2 mA
VOL
VIH
Output LOW Voltage
VCC = Min.,
VIN = VIH or VIL
IOL = 16 mA
0.5
V
I
OL = 12 mA
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for All Inputs[3]
Guaranteed Input Logical LOW Voltage for All Inputs[3]
VSS < VIN < VCC, VCC = Max.
2.0
–0.5
–10
–40
V
V
[4]
VIL
Input LOW Level
0.8
10
40
IIX
Input Leakage Current
µA
µA
IOZ
ISC
ICC1
Output Leakage Current
Output Short Circuit Current VCC = Max., VOUT = 0.5V[5,6]
VCC = Max., VSS < VOUT < VCC
–30 –130 mA
90 mA
Standby Power Supply
Current
VCC = Max.,
IN = GND,
10, 15, 25 ns
5, 7.5 ns
15, 25 ns
10 ns
Com’l
V
130 mA
120 mA
120 mA
110 mA
140 mA
130 mA
130 mA
Outputs Open in Unprogrammed
Device
Mil/Ind
[6]
ICC2
Operating Power Supply
Current
VCC = Max., VIL = 0V, VIH = 3V,
Output Open, Device Programmed
as a 10-bit Counter,
10, 15, 25 ns
5, 7.5 ns
15, 25 ns
10 ns
Com’l
Com’l
Mil/Ind
Mil/Ind
f = 25 MHz
Capacitance[6]
Parameter
CIN
Description
Input Capacitance
Output Capacitance
Test Conditions
Min.
Max.
Unit
pF
VIN = 2.0V @ f = 1 MHz
VOUT = 2.0V @ f = 1 MHz
10
10
COUT
pF
Endurance Characteristics[6]
Parameter
Description
Minimum Reprogramming Cycles
Test Conditions
Normal Programming Conditions
Min.
Max.
Unit
N
100
Cycles
Notes:
1. T is the “instant on” case temperature.
A
2. See the last page of this specification for Group A subgroup testing information.
3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
4. V (Min.) is equal to –3.0V for pulse durations less than 20 ns.
IL
5. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. V
caused by tester ground degradation.
= 0.5V has been chosen to avoid test problems
OUT
6. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-03027 Rev. *B
Page 4 of 13
USE ULTRA37000TM FOR
ALL NEW DESIGNS
PALCE22V10
AC Test Loads and Waveforms
R1238Ω
(319Ω MIL)
R1238Ω
(319Ω MIL)
5V
5V
OUTPUT
OUTPUT
OUTPUT
750Ω
R2170Ω
(236Ω MIL)
R2170Ω
(236Ω MIL)
(1.2KΩ
C
L
5pF
C
L
MIL)
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(a)
(b)
(c)
ALL INPUT PULSES
90%
3.0V
90%
10%
10%
GND
< 2ns
< 2ns
(d)
Equivalent to:THÉVENIN Equivalent (Commercial)
Equivalent to: THÉVENIN Equivalent (Military)
99Ω
136Ω
OUTPUT
2.08V = VTHC
OUTPUT
2.13V = VTHM
Load Speed
CL
Package
5, 7.5, 10, 15, 25 ns
50 pF
PDIP, CDIP,
PLCC, LCC
Parameter VX
Output Waveform Measurement Level
tER (- )
tER (+)
tEA (+)
tEA (- )
1.5V
2.6V
0V
VOH
VX
VX
0.5V
0.5V
VOL
1.5V
VOH
VX
VX
Vthc
VOL
0.5V
(e) Test Waveforms
[2, 7]
Commercial Switching Characteristics PALCE22V10
22V10-5
22V10-7
22V10-10
22V10-15
22V10-25
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tPD
Input to Output
3
5
3
7.5
3
10
3
15
3
25
ns
Propagation Delay[8]
tEA
tER
Input to Output Enable Delay[9]
Input to Output Disable Delay[10]
Clock to Output Delay[8]
6
6
4
8
8
5
10
10
7
15
15
8
25
25
15
ns
ns
ns
tCO
2
2
2
2
2
Notes:
7. Part (a) of AC Test Loads and Waveforms is used for all parameters except t and t
. Part (b) of AC Test Loads and Waveforms is used for t . Part (c) of AC Test
ER
ER
EA(+)
Loads and Waveforms is used for t
.
EA(+)
8. Min. times are tested initially and after any design or process changes that may affect these parameters.
9. The test load of (a) of AC Test Loads and Waveforms is used for measuring t . The test load of (c) of AC Test Loads and Waveforms is used for measuring t
only.
EA(+)
EA(-)
Please see (e) of AC Test Loads and Waveforms for enable and disable test waveforms and measurement reference levels.
10. This parameter is measured as the time after output disable input that the previous output data state remains stable on the output. This delay is measured to
the point at which a previous HIGH level has fallen to 0.5V below V min. or a previous LOW level has risen to 0.5V above V max. Please see (e) of AC Test Loads
OH
OL
and Waveforms for enable and disable test waveforms and measurement reference levels.
Document #: 38-03027 Rev. *B
Page 5 of 13
USE ULTRA37000TM FOR
ALL NEW DESIGNS
PALCE22V10
Commercial Switching Characteristics PALCE22V10 (continued)[2, 7]
22V10-5
22V10-7
22V10-10
22V10-15
22V10-25
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tS1
tS2
Input or Feedback Set-Up Time
3
4
5
6
6
7
10
10
15
15
ns
ns
Synchronous Preset Set-Up
Time
tH
Input Hold Time
0
0
10
3
0
12
3
0
20
6
0
30
ns
ns
tP
External Clock Period (tCO + tS)
Clock Width HIGH[6]
Clock Width LOW[6]
7
tWH
tWL
fMAX1
2.5
2.5
143
13
ns
3
3
6
13
ns
External Maximum
100
76.9
55.5
33.3
MHz
Frequency (1/(tCO + tS))[11]
fMAX2
fMAX3
tCF
Data Path Maximum Frequency 200
(1/(tWH + tWL))[6, 12]
166
133
142
111
83.3
68.9
35.7
38.5
MHz
MHz
ns
Internal Feedback Maximum
Frequency (1/(tCF + tS))[6,13]
181
Register Clock to
2.5
7.5
2.5
12
3
4.5
20
13
25
Feedback Input[6,14]
tAW
tAR
Asynchronous Reset Width
8
4
8
5
10
6
15
10
25
25
ns
ns
Asynchronous Reset
Recovery Time
tAP
Asynchronous Reset to
Registered Output Delay
13
ns
ns
µs
tSPR
tPR
Synchronous Preset
Recovery Time
Power-up Reset Time[6,15]
4
1
6
1
8
1
10
1
15
1
[2, 7]
Military and Industrial Switching Characteristics PALCE22V10
22V10-10
22V10-15
Min. Max.
22V10-25
Parameter
Description
Min.
Max.
Min.
Max.
Unit
tPD
Input to Output
3
10
3
15
3
25
ns
Propagation Delay[8]
tEA
tER
tCO
tS1
tS2
tH
Input to Output Enable Delay[9]
Input to Output Disable Delay[10]
Clock to Output Delay[8]
Input or Feedback Set-up Time
Synchronous Preset Set-up Time
Input Hold Time
10
10
7
15
15
8
25
25
15
ns
ns
2
6
2
10
10
0
2
18
18
0
ns
ns
7
ns
0
ns
tP
External Clock Period (tCO + tS)
Clock Width HIGH[6]
Clock Width LOW[6]
12
3
20
6
33
14
14
30.3
ns
tWH
tWL
ns
3
6
ns
fMAX1
External Maximum Frequency
(1/(tCO + tS))[11]
76.9
50.0
MHz
fMAX2
Data Path Maximum Frequency
(1/(tWH + tWL))[6, 12 ]
142
83.3
35.7
MHz
Notes:
11. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate.
12. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode.
13. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate.
14. This parameter is calculated from the clock period at f internal (1/f ) as measured (see Note above) minus t .
MAX
MAX3
S
15. The registers in the PALCE22V10 have been designed with the capability to reset during system power-up. Following power-up, all registers will be reset to a
logic LOW state. The output state will depend on the polarity of the output buffer. This feature is useful in establishing state machine initialization. To insure proper
operation, the rise in V must be monotonic and the timing constraints depicted in Power-Up Reset Waveform must be satisfied.
CC
Document #: 38-03027 Rev. *B
Page 6 of 13
USE ULTRA37000TM FOR
ALL NEW DESIGNS
PALCE22V10
Military and Industrial Switching Characteristics PALCE22V10 (continued)[2, 7]
22V10-10
22V10-15
22V10-25
Parameter
fMAX3
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Internal Feedback Maximum
Frequency (1/(tCF + tS))[6, 13]
111
68.9
32.2
MHz
tCF
Register Clock to
3
4.5
13
ns
Feedback Input[6, 14]
tAW
tAR
Asynchronous Reset Width
10
6
15
12
25
25
ns
ns
Asynchronous Reset
Recovery Time
tAP
Asynchronous Reset to
Registered Output Delay
12
20
25
ns
ns
µs
tSPR
tPR
Synchronous Preset
Recovery Time
Power-up Reset Time[6, 15]
8
1
20
1
25
1
Switching Waveforms
INPUTS I/O,
REGISTERED
FEEDBACK
SYNCHRONOUS
PRESET
tWH
tWL
tS
tH
CP
tSPR
tP
tAR
tAW
ASYNCHRONOUS
RESET
tCO
tAP
t
t
t
[9]
EA
[10]
ER
REGISTERED
OUTPUTS
tPD
t
[10]
EA [9]
ER
COMBINATORIAL
OUTPUTS
Power-Up Reset Waveform[15]
VCC
90%
10%
POWER
SUPPLY VOLTAGE
tPR
REGISTERED
ACTIVE LOW
OUTPUTS
tS
CLOCK
tWL
t
MAX = 1 µs
PR
Document #: 38-03027 Rev. *B
Page 7 of 13
USE ULTRA37000TM FOR
ALL NEW DESIGNS
PALCE22V10
Functional Logic Diagram for PALCE22V10
1
32
36
40
0
4
8
12
16
20
24
28
AR
OE
0
S
S
S
7
Macro–
23
22
cell
OE
0
S
S
S
Macro–
cell
9
2
3
OE
0
S
S
S
Macro–
cell
21
20
11
OE
0
Macro–
cell
S
S
S
13
4
5
OE
0
Macro–
cell
S
19
18
S
S
15
OE
0
Macro–
cell
S
S
S
15
6
7
OE
0
Macro–
cell
S
S
17
16
S
13
OE
0
S
Macro–
cell
S
S
11
8
9
OE
0
S
S
S
Macro–
cell
15
14
9
OE
0
S
S
S
7
Macro–
cell
10
11
SP
13
Document #: 38-03027 Rev. *B
Page 8 of 13
USE ULTRA37000TM FOR
ALL NEW DESIGNS
PALCE22V10
Ordering Information
ICC
tPD
tS
tCO
Package
Name
Operating
Range
(mA) (ns)
(ns)
(ns)
Ordering Code
PALCE22V10-5PC
PALCE22V10-5JC
PALCE22V10-7JC
PALCE22V10-7PC
PALCE22V10-10JC
PALCE22V10-10PC
PALCE22V10-10JI
PALCE22V10-10PI
Package Type
130
130
90
5
3
5
6
6
4
5
7
7
P13
J64
J64
P13
J64
P13
J64
P13
L64
24-lead (300 MIL) Molded DIP
Commercial
28-lead Plastic Leaded Chip Carrier
28-lead Plastic Leaded Chip Carrier
24-lead (300-Mil) Molded DIP
7.5
10
10
Commercial
Commercial
Industrial
28-lead Plastic Leaded Chip Carrier
24-lead (300-Mil) Molded DIP
150
28-lead Plastic Leaded Chip Carrier
24-lead (300-Mil) Molded DIP
PALCE22V10-10LMB
5962-89841063X
28-Square Leadless Chip Carrier
Military
PALCE22V10-10KMB
5962-8984106KX
K73
D14
24-lead Rectangular Cerpack
24-lead (300 MIL) CerDIP
PALCE22V10-10DMB
5962-8984106LX
90
15
15
10
10
8
8
PALCE22V10-15JC
PALCE22V10-15PC
J64
P13
K73
28-lead Plastic Leaded Chip Carrier
24-lead (300-Mil) Molded DIP
24-lead Rectangular Cerpack
Commercial
Military
120
PALCE22V10-15KMB
5962-8984102KX
PALCE22V10-15KMB
5962-8984103KX
K73
K73
D14
D14
L64
L64
24-lead Rectangular Cerpack
24-lead Rectangular Cerpack
24-lead (300 MIL) CerDIP
PALCE22V10-15KMB
5962-8984105KX
PALCE22V10-15DMB
5962-8984102LX
PALCE22V10-15DMB
5962-8984103LX
24-lead (300 MIL) CerDIP
PALCE22V10-15LMB
5962-89841033X
28-Square Leadless Chip Carrier
28-Square Leadless Chip Carrier
PALCE22V10-15LMB
5962-89841053X
90
25
25
15
15
15 PALCE22V10-25JC
PALCE22V10-25PC
J64
P13
L64
28-lead Plastic Leaded Chip Carrier
24-lead (300-Mil) Molded DIP
Commercial
Military
120
15 PALCE22V10-25LMB
5962-89841043X
28-square Leadless Chip Carrier
DC Characteristics
MILITARYSPECIFICATIONSGroupASubgroup
Testing
Parameter
Subgroups
ICC
1, 2, 3
DC Characteristics
Parameter
VOH
VOL
Subgroups
1, 2, 3
Switching Characteristics
Parameter
Subgroups
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
1, 2, 3
tPD
tCO
tS
VIH
1, 2, 3
VIL
1, 2, 3
IIX
1, 2, 3
tH
IOZ
1, 2, 3
Document #: 38-03027 Rev. *B
Page 9 of 13
USE ULTRA37000TM FOR
ALL NEW DESIGNS
PALCE22V10
Package Diagrams
24-lead (300-mil) CerDIP D14
MIL-STD-1835D-9 Config.A
51-80031-**
28-lead Plastic Leaded Chip Carrier J64
51-85001-*A
Document #: 38-03027 Rev. *B
Page 10 of 13
USE ULTRA37000TM FOR
ALL NEW DESIGNS
PALCE22V10
Package Diagrams (continued)
24-Lead Rectangular Cerpack K73
MIL-STD-1835 F-6 Config. A
PIN 1 I.D.
DIMENSIONS IN INCHES
PIN 1 I.D.
MIN.
MAX.
PIN 1 I.D OPTION
PIN 1 I.D.
(SEE OPTION)
.005
.015
.045 MAX.
.015
.019
.050 BSC
.590
.620
.005 MIN.
.360
.400
BASE AND
SEATING
PLANE
.026
.040
.004
.009
.260
.325
.260
.325
.060
.090
51-80060-*A
Document #: 38-03027 Rev. *B
Page 11 of 13
USE ULTRA37000TM FOR
ALL NEW DESIGNS
PALCE22V10
Package Diagrams (continued)
28-Square Leadless Chip Carrier L64
MIL-STD-1835 C-4
51-80051-**
Ultra37000 is a trademark of Cypress Semiconductor Corporation. PAL is a registered trademark of Advanced Micro Devices.
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-03027 Rev. *B
Page 12 of 13
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
USE ULTRA37000TM FOR
ALL NEW DESIGNS
PALCE22V10
Document History Page
Document Title: PALCE22V10 Flash-erasable Reprogrammable CMOS PAL® Device
Document Number: 38-03027
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
106372
114640
07/11/01
06/25/02
SZV
Change from Spec Number: 38-00447 to 38-03027
*A
OOR
Added a note on the title page referring all new designs to this device
Added Military Part Numbers
*B
213375
See ECN
FSG
Added note to title page: “Use Ultra37000 For All New Designs”
Document #: 38-03027 Rev. *B
Page 13 of 13
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