PALCE22V10-5JCT [CYPRESS]
Flash PLD, 5ns, CMOS, PQCC28, PLASTIC, LCC-28;
| 型号： | PALCE22V10-5JCT |
| 厂家： | 
CYPRESS |
| 描述： | Flash PLD, 5ns, CMOS, PQCC28, PLASTIC, LCC-28 闪存 |
| 文件： | 总13页 (文件大小：387K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
22V10
PALCE22V10
Flash Erasable,
Reprogrammable CMOS PAL® Device
5 ns tPD
Features
181-MHz state machine
• Low power
—10 ns military and industrial versions
— 90 mA max. commercial (10 ns)
— 130 mA max. commercial (5 ns)
7 ns tCO
6 ns tS
10 ns tPD
110-MHz state machine
• CMOS Flash EPROM technology for electrical erasabil-
ity and reprogrammability
—15-ns commercial, industrial, and military versions
—25-ns commercial, industrial, and military versions
• High reliability
• Variable product terms
— 2 x(8 through 16) product terms
• User-programmable macrocell
— Output polarity control
—Proven Flash EPROM technology
—100% programming and functional testing
— Individually selectable for registered or combinato-
rial operation
Functional Description
• Up to 22 input terms and 10 outputs
• DIP, LCC, and PLCC available
The Cypress PALCE22V10 is a CMOS Flash Erasable sec-
ond-generation programmable array logic device. It is imple-
mented with the familiar sum-of-products (AND-OR) logic
structure and the programmable macrocell.
— 5 ns commercial version
4 ns tCO
3 ns tS
Logic Block Diagram (PDIP/CDIP)
V
I
I
I
I
I
I
I
I
I
I
CP/I
1
SS
12
11
10
9
8
7
6
5
4
3
2
PROGRAMMABLE
AND ARRAY
(132 X 44)
8
10
12
14
16
16
14
12
10
8
Reset
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Preset
13
I
14
15
16
17
18
19
20
21
22
23
24
I/O
9
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
I/O
0
V
CC
PLCC
Top View
LCC
Top View
Pin Configuration
CE22V10–1
4
3
2
1
2827 26
25
4
3 2 1 282726
I
I
I
5
6
7
8
9
10
11
25 I/O
2
5
6
7
8
9
10
11
I
I
I/O
I/O
I/O
2
3
4
24 I/O
23 I/O
3
4
N/C
24
23
22
21
20
19
I
NC
I
I
I
22
NC
I
I
I
N/C
21 I/O
20 I/O
19 I/O
5
6
7
I/O
I/O
I/O
5
6
7
12131415161718
121314 1516 1718
CE22V10–3
CE22V10–2
PAL is a registered trademark of Advanced Micro Devices.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-03027 Rev. **
Revised September 1996
PALCE22V10
Selection Guide
tPD ns
tS ns
tCO ns
ICC mA
Generic Part Number
Com’l
Mil/Ind
Com’l
Mil/Ind
Com’l
Mil/Ind
Com’l
130
130
90
Mil/Ind
PALCE22V10-5
PALCE22V10-7
PALCE22V10-10
PALCE22V10-15
PALCE22V10-25
5
3
5
4
5
7.5
10
15
25
10
15
25
6
6
7
7
8
150
120
120
10
15
10
15
8
90
15
15
90
tions requiring up to 21 inputs and only a single output and
down to 12 inputs and 10 outputs are possible. The 10 poten-
tial outputs are enabled using product terms. Any output pin
may be permanently selected as an output or arbitrarily en-
abled as an output and an input through the selective use of
individual product terms associated with each output. Each of
these outputs is achieved through an individual programmable
macrocell. These macrocells are programmable to provide a
combinatorial or registered inverting or non-inverting output. In
a registered mode of operation, the output of the register is fed
back into the array, providing current status information to the
array. This information is available for establishing the next
result in applications such as control state machines. In a com-
binatorial configuration, the combinatorial output or, if the out-
put is disabled, the signal present on the I/O pin is made avail-
able to the array. The flexibility provided by both
programmable product term control of the outputs and variable
product terms allows a significant gain in functional density
through the use of programmable logic.
Functional Description (continued)
The PALCE22V10 is executed in a 24-pin 300-mil molded DIP,
a 300-mil cerDIP, a 28-lead square ceramic leadless chip car-
rier, a 28-lead square plastic leaded chip carrier, and provides
up to 22 inputs and 10 outputs. The PALCE22V10 can be elec-
trically erased and reprogrammed. The programmable macro-
cell provides the capability of defining the architecture of each
output individually. Each of the 10 potential outputs may be
specified as “registered” or “combinatorial.” Polarity of each
output may also be individually selected, allowing complete
flexibility of output configuration. Further configurability is pro-
vided through “array” configurable “output enable” for each po-
tential output. This feature allows the 10 outputs to be recon-
figured as inputs on an individual basis, or alternately used as
a combination I/O controlled by the programmable array.
PALCE22V10 features a variable product term architecture.
There are 5 pairs of product term sums beginning at 8 product
terms per output and incrementing by 2 to 16 product terms
per output. By providing this variable structure, the PALCE
22V10 is optimized to the configurations found in a majority of
applications without creating devices that burden the product
term structures with unusable product terms and lower perfor-
mance.
Along with this increase in functional density, the Cypress
PALCE22V10 provides lower-power operation through the use
of CMOS technology, and increased testability with Flash re-
programmability.
Configuration Table
Additional features of the Cypress PALCE22V10 include a
synchronous preset and an asynchronous reset product term.
These product terms are common to all macrocells, eliminat-
ing the need to dedicate standard product terms for initializa-
tion functions. The device automatically resets upon pow-
er-up.
Registered/Combinatorial
C1
0
C0
0
Configuration
Registered/Active LOW
Registered/Active HIGH
Combinatorial/Active LOW
Combinatorial/Active HIGH
0
1
The PALCE22V10, featuring programmable macrocells and
variable product terms, provides a device with the flexibility to
implement logic functions in the 500- to 800-gate-array com-
plexity. Since each of the 10 output pins may be individually
configured as inputs on a temporary or permanent basis, func-
1
0
1
1
Document #: 38-03027 Rev. **
Page 2 of 13
PALCE22V10
Macrocell
AR
OUTPUT
SELECT
MUX
D
Q
Q
S1 S0
CP
SP
INPUT/
FEEDBACK
MUX
S1
C1
C0
MACROCELL
CE22V10–4
DC Programming Voltage............................................. 12.5V
Latch-Up Current..................................................... >200 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ............................. >2001V
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Ambient
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) ........................................... –0.5V to +7.0V
Range
Commercial
Industrial
Temperature
VCC
0°C to +75°C
5V ±5%
5V ±10%
5V ±10%
DC Voltage Applied to Outputs
in High Z State............................................... –0.5V to +7.0V
–40°C to +85°C
–55°C to +125°C
Military[1]
DC Input Voltage............................................ –0.5V to +7.0V
Output Current into Outputs (LOW) .............................16 mA
Note:
1. TA is the “instant on” case temperature.
Document #: 38-03027 Rev. **
Page 3 of 13
PALCE22V10
]
Electrical Characteristics Over the Operating Range[2]
Parameter
Description
Test Conditions
IOH = –3.2 mA
IOH = –2 mA
IOL = 16 mA
Min.
Max. Unit
VOH
Output HIGH Voltage
VCC = Min.,
VIN = VIH or VIL
Com’l
Mil/Ind
Com’l
Mil/Ind
2.4
V
VOL
Output LOW Voltage
VCC = Min.,
VIN = VIH or VIL
0.5
V
IOL = 12 mA
VIH
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for All Inputs[3]
Guaranteed Input Logical LOW Voltage for All Inputs[3]
VSS < VIN < VCC, VCC = Max.
2.0
–0.5
–10
–40
–30
V
V
[4]
VIL
Input LOW Level
0.8
10
40
IIX
Input Leakage Current
Output Leakage Current
Output Short Circuit Current VCC = Max., VOUT = 0.5V[5,6]
µA
µA
IOZ
ISC
ICC1
VCC = Max., VSS < VOUT < VCC
–130 mA
Standby Power Supply
Current
VCC = Max.,
VIN = GND,
Outputs Open in
Unprogrammed
Device
10, 15, 25 ns
5, 7.5 ns
15, 25 ns
10 ns
Com’l
90
mA
mA
mA
mA
mA
mA
mA
mA
130
120
120
110
140
130
130
Mil/Ind
[6]
ICC2
Operating Power Supply
Current
VCC = Max., VIL
0V, VIH = 3V,
Output Open, De-
vice Programmed
as a 10-Bit
=
10, 15, 25 ns
5, 7.5 ns
15, 25 ns
10 ns
Com’l
Com’l
Mil/Ind
Mil/Ind
Counter,
f = 25 MHz
Capacitance[6]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Min.
Max.
Unit
CIN
VIN = 2.0V @ f = 1 MHz
VOUT = 2.0V @ f = 1 MHz
10
10
pF
pF
COUT
]
Endurance Characteristics[6]
Parameter
Description
Minimum Reprogramming Cycles
Test Conditions
Normal Programming Conditions
Min.
Max.
Unit
N
100
Cycles
Notes:
2. See the last page of this specification for Group A subgroup testing information.
3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
4. VIL (Min.) is equal to -3.0V for pulse durations less than 20 ns.
5. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid test problems
caused by tester ground degradation.
6. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-03027 Rev. **
Page 4 of 13
PALCE22V10
AC Test Loads and Waveforms
R1238Ω
R1238Ω
(319Ω MIL)
(319Ω MIL)
5V
5V
OUTPUT
OUTPUT
OUTPUT
750Ω
(1.2KΩ
MIL)
R2170Ω
(236Ω MIL)
R2170Ω
(236Ω MIL)
C
5 pF
C
L
L
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(a)
(b)
(c)
ALL INPUT PULSES
90%
10%
3.0V
90%
10%
GND
< 2 ns
< 2 ns
CE22V10–5
(d)
Equivalent to: THÉVENIN EQUIVALENT (Commercial)
99Ω
Equivalent to: THÉVENIN EQUIVALENT (Military)
136Ω
OUTPUT
2.08V=V
OUTPUT
2.13V=V
CE22V10–7
thc
CE22V10–6
thm
Load Speed
CL
Package
5, 7.5, 10, 15, 25
ns
50 pF
PDIP, CDIP,
PLCC, LCC
Parameter VX
Output Waveform Measurement Level
tER (- )
tER (+)
tEA (+)
tEA (- )
1.5V
2.6V
0V
VOH
VX
VX
0.5V
0.5V
VOL
1.5V
VOH
VX
VX
Vthc
VOL
0.5V
(e) Test Waveforms
Document #: 38-03027 Rev. **
Page 5 of 13
PALCE22V10
]
Commercial Switching Characteristics PALCE22V10[2,7]
22V10-5
22V10-7
22V10-10
22V10-15
22V10-25
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tPD
Input to Output
3
5
6
6
4
3
7.5
3
10
10
10
7
3
15
15
15
8
3
25
25
25
15
ns
ns
ns
Propagation Delay[8]
tEA
tER
Input to Output
Enable Delay[9]
8
Input to Output
8
Disable Delay[10]
tCO
tS1
tS2
Clock to Output Delay[8]
2
3
4
2
5
6
5
2
6
7
2
2
ns
ns
ns
Input or Feedback Set-Up Time
10
10
15
15
Synchronous Preset Set-Up
Time
tH
Input Hold Time
0
7
0
10
3
0
12
3
0
20
6
0
30
ns
ns
tP
External Clock Period (tCO + tS)
Clock Width HIGH[6]
Clock Width LOW[6]
tWH
tWL
fMAX1
2.5
2.5
143
13
ns
3
3
6
13
ns
External Maximum
100
76.9
55.5
33.3
MHz
Frequency (1/(tCO + tS))[11]
fMAX2
fMAX3
tCF
Data Path Maximum Frequency 200
(1/(tWH + tWL))[6, 12]
166
133
142
111
83.3
68.9
35.7
38.5
MHz
MHz
ns
Internal Feedback Maximum
Frequency (1/(tCF + tS))[6,13]
181
Register Clock to
2.5
7.5
2.5
12
3
4.5
20
13
25
Feedback Input[6,14]
tAW
tAR
Asynchronous Reset Width
8
4
8
5
10
6
15
10
25
25
ns
ns
Asynchronous Reset
Recovery Time
tAP
Asynchronous Reset to
Registered Output Delay
13
ns
ns
µs
tSPR
Synchronous Preset
Recovery Time
Power-Up Reset Time[6,15]
4
1
6
1
8
1
10
1
15
1
tPR
Notes:
7. Part (a) of AC Test Loads and Waveforms is used for all parameters except tER and tEA(+). Part (b) of AC Test Loads and Waveforms is used for tER. Part (c) of AC Test
Loads and Waveforms is used for tEA(+)
.
8. Min. times are tested initially and after any design or process changes that may affect these parameters.
9. The test load of part (a) of AC Test Loads and Waveforms is used for measuring tEA(-). The test load of part (c) of AC Test Loads and Waveforms is used for measuring
tEA(+) only. Please see part (e) of AC Test Loads and Waveforms for enable and disable test waveforms and measurement reference levels.
10. This parameter is measured as the time after output disable input that the previous output data state remains stable on the output. This delay is measured to
the point at which a previous HIGH level has fallen to 0.5 volts below VOH min. or a previous LOW level has risen to 0.5 volts above VOL max. Please see part (e) of AC
Test Loads and Waveforms for enable and disable test waveforms and measurement reference levels.
11. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate.
12. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode.
13. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate.
14. This parameter is calculated from the clock period at fMAX internal (1/fMAX3) as measured (see Note above) minus tS.
15. The registers in the PALCE22V10 have been designed with the capability to reset during system power-up. Following power-up, all registers will be reset to a
logic LOW state. The output state will depend on the polarity of the output buffer. This feature is useful in establishing state machine initialization. To insure
proper operation, the rise in VCC must be monotonic and the timing constraints depicted in Power-Up Reset Waveform must be satisfied
Document #: 38-03027 Rev. **
Page 6 of 13
PALCE22V10
Military and Industrial Switching Characteristics PALCE22V10[2,7]
22V10-10
22V10-15
22V10-25
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tPD
Input to Output
3
10
3
15
3
25
ns
Propagation Delay[8]
tEA
tER
tCO
tS1
tS2
Input to Output Enable Delay[9]
Input to Output Disable Delay[10]
Clock to Output Delay[8]
10
10
7
15
15
8
25
25
15
ns
ns
ns
ns
ns
2
6
7
2
2
Input or Feedback Set-Up Time
10
10
18
18
Synchronous Preset Set-Up
Time
tH
Input Hold Time
0
12
3
0
20
6
0
33
ns
ns
tP
External Clock Period (tCO + tS)
Clock Width HIGH[6]
Clock Width LOW[6]
tWH
tWL
14
ns
3
6
14
ns
fMAX1
fMAX2
fMAX3
tCF
External Maximum Frequency
(1/(tCO + tS))11]
76.9
50.0
30.3
MHz
Data Path Maximum Frequency
(1/(tWH + tWL))[6,12 ]
142
111
83.3
68.9
35.7
32.2
MHz
MHz
ns
Internal Feedback Maximum
Frequency (1/(tCF + tS))[6,13]
Register Clock to
3
4.5
20
13
25
Feedback Input[6,14]
tAW
tAR
Asynchronous Reset Width
10
6
15
12
25
25
ns
ns
Asynchronous Reset
Recovery Time
tAP
Asynchronous Reset to
Registered Output Delay
12
ns
ns
µs
tSPR
tPR
Synchronous Preset
Recovery Time
Power-Up Reset Time[6,15]
8
1
20
1
25
1
Document #: 38-03027 Rev. **
Page 7 of 13
PALCE22V10
Switching Waveforms
INPUTS I/O,
REGISTERED
FEEDBACK
SYNCHRONOUS
PRESET
tWH
tWL
tS
tH
CP
tSPR
tP
tAR
tAW
ASYNCHRONOUS
RESET
tCO
[9]
tAP
[10]
[10]
t
t
t
t
ER
EA
REGISTERED
OUTPUTS
[9]
tPD
EA
ER
COMBINATORIAL
OUTPUTS
CE22V10–8
Power-Up Reset Waveform[15]
VCC
90%
10%
POWER
SUPPLY VOLTAGE
tPR
REGISTERED
ACTIVE LOW
OUTPUTS
tS
CLOCK
tWL
t
MAX= 1 µs
PR
CE22V10–9
Document #: 38-03027 Rev. **
Page 8 of 13
PALCE22V10
Functional Logic Diagram for PALCE22V10
1
32
36
40
0
4
8
12
16
20
24
28
AR
OE
0
S
S
S
7
Macro–
23
22
cell
OE
0
S
S
S
Macro–
cell
9
2
3
OE
0
S
S
S
Macro–
21
20
cell
11
OE
0
Macro–
cell
S
S
S
13
4
5
OE
0
Macro–
S
19
18
17
cell
S
S
15
OE
0
Macro–
cell
S
S
S
15
6
7
OE
0
Macro–
cell
S
S
S
13
OE
0
S
Macro–
S
16
15
cell
S
11
8
9
OE
0
S
S
S
Macro–
cell
9
OE
0
S
S
S
7
Macro–
cell
14
13
10
11
SP
CE22V10–10
Document #: 38-03027 Rev. **
Page 9 of 13
PALCE22V10
Ordering Information
ICC
tPD
tS
tCO
Package
Name
Operating
Range
(mA) (ns)
(ns)
(ns)
Ordering Code
PALCE22V10-5PC
PALCE22V10-5JC
PALCE22V10-7JC
PALCE22V10-7PC
PALCE22V10-10JC
PALCE22V10-10PC
PALCE22V10-10JI
PALCE22V10-10PI
PALCE22V10-10DMB
PALCE22V10-10KMB
PALCE22V10-10LMB
Package Type
130
130
90
5
3
5
6
6
6
4
5
7
7
7
P13
J64
J64
P13
J64
P13
J64
P13
D14
K73
L64
J64
P13
J64
P13
D14
K73
L64
J64
P13
J64
P13
D14
K73
L64
24-Lead (300 MIL) Molded DIP
Commercial
28-Lead Plastic Leaded Chip Carrier
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) CerDIP
7.5
10
10
10
Commercial
Commercial
Industrial
150
150
Military
24-Lead Rectangular Cerpack
28-Square Leadless Chip Carrier
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) CerDIP
90
15
15
15
7.5
7.5
7.5
10 PALCE22V10-15JC
PALCE22V10-15PC
Commercial
Industrial
Military
120
120
10 PALCE22V10-15JI
PALCE22V10-15PI
10 PALCE22V10-15DMB
PALCE22V10-15KMB
PALCE22V10-15LMB
15 PALCE22V10-25JC
PALCE22V10-25PC
24-Lead Rectangular Cerpack
28-Square Leadless Chip Carrier
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
28-Lead Plastic Leaded Chip Carrier
24-Lead (300-Mil) Molded DIP
24-Lead (300-Mil) CerDIP
90
25
25
25
15
15
15
Commercial
Industrial
Military
120
120
15 PALCE22V10-25JI
PALCE22V10-25PI
15 PALCE22V10-25DMB
PALCE22V10-25KMB
PALCE22V10-25LMB
24-Lead Rectangular Cerpack
28-Square Leadless Chip Carrier
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Switching Characteristics
Parameter
Subgroups
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
DC Characteristics
tPD
tCO
tS
Parameter
VOH
VOL
Subgroups
1, 2, 3
1, 2, 3
tH
VIH
1, 2, 3
VIL
1, 2, 3
IIX
1, 2, 3
IOZ
1, 2, 3
ICC
1, 2, 3
Document #: 38-03027 Rev. **
Page 10 of 13
PALCE22V10
Package Diagrams
24–Lead (300–Mil) CerDIP D14
28–Lead Plastic Leaded Chip Carrier J64
MIL-STD-1835 D- 9 Config.A
24–Lead Rectangular Cerpack K73
MIL-STD-1835 F-6 Config.A
28–Square Leadless Chip Carrier L64
MIL-STD-1835 C-4
Document #: 38-03027 Rev. **
Page 11 of 13
PALCE22V10
Package Diagrams (continued)
24–Lead (300–Mil) Molded DIP P13/P13A
Document #: 38-03027 Rev. **
Page 12 of 13
© Cypress Semiconductor Corporation, 1996. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PALCE22V10
Document Title: PALCE22V10 Flash Erasable, Reprogrammable CMOS PAL® Device
Document Number: 38-03027
Issue
Date
Orig. of
Change
REV.
ECN NO.
Description of Change
Change from Spec Number: 38-00447 to 38-03027
**
106372
07/11/01
SZV
Document #: 38-03027 Rev. **
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