CYUSB3324-BVXI [CYPRESS]
HX3 USB 3.0 Hub;
| 型号： | CYUSB3324-BVXI |
| 厂家： | 
CYPRESS |
| 描述： | HX3 USB 3.0 Hub |
| 文件： | 总43页 (文件大小：1393K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
HX3 USB 3.0 Hub
HX3 USB 3.0 Hub
General Description
HX3 is a family of USB 3.0 hub controllers compliant with the USB 3.0 specification revision 1.0. HX3 supports SuperSpeed (SS),
Hi-Speed (HS), Full-Speed (FS), and Low-Speed (LS) on all the ports. It has integrated termination, pull-up, and pull-down resistors,
and supports configuration options through pin-straps to reduce the overall BOM of the system.
HX3 includes the following Cypress-proprietary features:
Shared Link™: Enables extra downstream (DS) ports for on-board connections in embedded applications
Ghost Charge™: Enables charging of devices connected to the DS ports when no host is connected on the upstream (US) port
HX3 USB 3.0 Hub
■ Vendor-Command Support to Implement a USB-to-I2C Bridge
❐ Firmware upgrade of an external ASSP connected to HX3
through USB
Features
■ USB-IF Certified Hub, TID# 330000060, 30000074
❐ In-System Programming (ISP) of the EEPROM connected to
■ Supports up to Four USB 3.0-Compliant DS ports
❐ All ports support SS (5 Gbps), and are backward-compatible
with HS (480 Mbps), FS (12 Mbps), and LS (1.5 Mbps)
❐ SS and USB 2.0 Link Power Management (LPM)
❐ Dedicated Hi-Speed Transaction Translators (Multi-TT)
❐ LED status indicators – suspend, SS, and USB 2.0 operation
HX3 through USB
■ Extensive Configuration Support
❐ Pin-strap configuration for the following functions:
• Vendor ID (VID)
• Charging support for each DS port
• Number of active ports
■ Shared Link™ for Embedded Applications
• Number of non-removable devices
• Ganged or individual power switch enables for DS ports
• Power switch polarity selection
❐ Each DS port can simultaneously connect to an embedded
SS device and a removable USB 2.0 device
❐ Enables up to eight device connections
❐ Custom configuration modes supported with eFuse, I2C
■ Enhanced Battery Charging
❐ Each DS port complies with the USB Battery Charging v1.2
(BC v1.2) specification
❐ Ghost Charge™: Each DS port can emulate a Dedicated
Charging Port (DCP) when the host is not connected to the
US port
EEPROM, or I2C slave
• SS and USB 2.0 PHY parameters
• Product ID (PID)/VID, manufacturer, and product string
descriptors
• Swap DP/DM signals for flexible PCB routing
❐ Accessory Charger Adapter Dock (ACA-Dock): Enables
charging and simultaneous data transfer for a smart phone
or a tablet acting as a host compliant to BC v1.2
■ Software Features
❐ Microsoft WHQL-certified for Windows XP/Vista/7/8/8.1
❐ Compatible with Mac OS 10.9 and Linux kernel version 3.11
❐ Apple charging supported on all DS ports
■ Integrated ARM® Cortex™-M0 CPU
❐ 16 KB RAM, 32 KB ROM
❐ Customize configuration parameters with the easy-to-use
Cypress’s “Blaster Plus” software tool
■ Flexible Packaging Options
❐ 68-pin QFN (8 × 8 × 1.0 mm)
❐ 88-pin QFN (10 × 10 × 1.0 mm)
❐ 100-ball BGA (6 × 6 × 1.0 mm)
❐ Industrial temperature range (–40 °C to +85 °C)
❐ Configure GPIOs for overcurrent protection, power enable,
and LEDs
❐ Upgrade firmware using (a) I2C EEPROM or (b) an external
I2C master
Cypress Semiconductor Corporation
Document Number: 001-73643 Rev. *R
•
198 Champion Court
•
San Jose, CA 95134-1709
• +1-408-943-2600
Revised January 25, 2018
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Block Diagram
US Port
USB 2.0
SS
ARM
Cortex-M0
USB 2.0
PHY
SS
PHY
VBUS
Detect
RAM
ROM
I2C
I2C_DATA
I2C_CLK
USB 2.0 Controller
SS Controller
US Port Control Routing
Hub Controller
PHY Interface
Hub Controller
3.3 V
1.2 V
Four Transaction
Translators
Repeater
US Buffers
DS Buffers
26 MHz
PLL
Routing Logic
Buffer and Routing Logic
USB 2.0
PHY
SS
PHY
Port
Control
USB 2.0
PHY
SS
PHY
Port
Control
USB 2.0
PHY
SS
PHY
Port
Control
USB 2.0
PHY
SS
PHY
Port
Control
DS Port 1
DS Port 2
DS Port 3
DS Port 4
Document Number: 001-73643 Rev. *R
Page 2 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Contents
Architecture Overview .....................................................4
SS Hub Controller .......................................................4
USB 2.0 Hub Controller ...............................................4
CPU .............................................................................4
I2C Interface ................................................................4
Port Controller .............................................................4
Applications ......................................................................4
HX3 Product Options .......................................................5
Product Features ..............................................................6
Shared Link .................................................................6
Ghost Charge ..............................................................6
Vendor-Command Support .........................................7
ACA-Dock Support ......................................................7
Pin Information .................................................................8
System Interfaces ...........................................................24
Upstream Port (US) ...................................................24
Downstream Ports (DS1, 2, 3, 4) ..............................24
Communication Interfaces (I2C) ................................24
Oscillator ...................................................................24
GPIOs ........................................................................24
Power Control ............................................................24
Reset .........................................................................24
Configuration Mode Select ........................................24
Configuration Options ................................................24
EMI ...................................................................................31
ESD ..................................................................................31
Absolute Maximum Ratings ..........................................32
Electrical Specifications ................................................32
DC Electrical Characteristics .....................................32
Power Consumption ..................................................33
Ordering Information ......................................................34
Ordering Code Definitions .........................................35
Packaging ........................................................................36
Package Diagrams ..........................................................37
Acronyms ........................................................................39
Reference Documents ....................................................39
Document Conventions .................................................39
Units of Measure .......................................................39
Silicon Revision History ................................................40
Method of Identification .............................................40
Document History Page .................................................41
Sales, Solutions, and Legal Information ......................43
Worldwide Sales and Design Support .......................43
Products ....................................................................43
PSoC® Solutions ......................................................43
Cypress Developer Community .................................43
Technical Support .....................................................43
Document Number: 001-73643 Rev. *R
Page 3 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
2
I C Interface
Architecture Overview
2
The I C interface in HX3 supports the following:
The Block Diagram on page 2 shows the HX3 architecture. HX3
consists of two independent hub controllers (SS and USB 2.0),
the Cortex-M0 CPU subsystem, an I C interface, and port
2
■ I C Slave, Master, and Multi-master configurations
2
2
2
❐ Configure HX3 by an external I C master in I C slave mode
❐ Configure HX3 from an I C EEPROM
❐ Multi-master mode to share EEPROM with other I C masters
2
controller blocks.
2
SS Hub Controller
2
■ In-System Programming of the I C EEPROM from HX3’s
This block supports the SS hub functionality based on the
USB 3.0 specification. The SS hub controller supports the
following:
US port
Port Controller
The port controller block controls DS port power to comply with
the BC v1.2 and USB 3.0 specifications. This block also controls
the US port power in the ACA-Dock mode. Control signals for
external power switches are implemented within the chip. HX3
controls the external power switches at power-on to reduce
in-rush current.
■ SS link power management (U0, U1, U2, U3 states)
■ Full-duplex data transmission
USB 2.0 Hub Controller
This block supports the LS, FS, and HS hub functionalities. It
includes the repeater, frame timer, and four transaction trans-
lators.
The port controller block supports the following:
■ Overcurrent detection
The USB 2.0 hub controller block supports the following:
■ USB 2.0 link power management (L0, L1, L2, L3 states)
■ Suspend, resume, and remote wake-up signaling
■ Multi-TT (one TT for each DS port)
■ SS and USB 2.0 port indicators for each DS port
■ Ganged and individual power control modes
■ Automatic port numbering based on active ports
Applications
CPU
The ARM Cortex-M0 CPU subsystem is used for the following
functions:
■ Standalone hubs
■ PC and tablet motherboards
■ Docking station
■ Hand-held cradles
■ Monitors
■ System configuration and initialization
■ Battery charging control
2
■ Vendor-specific commands for the USB-to-I C bridge
■ String-descriptor support
■ Digital TVs
■ Suspend status indicator
■ Set-top boxes
■ Printers
■ Shared Link support in embedded systems
Document Number: 001-73643 Rev. *R
Page 4 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
HX3 Product Options
Table 1. HX3 Product Options
Features
CYUSB3302
CYUSB3304
CYUSB3312 CYUSB3314 CYUSB3324
CYUSB3326
CYUSB3328
CYUSB2302
CYUSB2304
6 (2 USB 3.0,
2 SS,
Number of DS
ports
8 (4 SS,
2 (USB 3.0)
4 (USB 3.0)
2 (USB 3.0)
0
4 (USB 3.0)
0
4 (USB 3.0)
0
2 (USB 2.0)
4 (USB 2.0)
4 USB 2.0)
2 USB 2.0)
Number of
Shared Link
ports
[1]
2
0
0
4
0
0
BC v1.2
Yes
No
Yes
No
Yes
No
Yes
No
Yes
Yes
Yes
No
Yes
Yes
Yes
No
Yes
No
ACA-Dock
External Power
Switch Control
Individual and Individual and Individual and
Ganged
Ganged
Individual
Individual
Ganged
Ganged
Ganged
Ganged
Ganged
Pin-Strap
support
No
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
No
Yes
Yes
2
I C
Yes
Yes
Yes
Vendor
command
Yes
Yes
Yes
Port indicators
No
No
Yes
Yes
Yes
No
No
No
68-QFN,
68-QFN,
88-QFN,
88-QFN,
88-QFN,
88-QFN,
88-QFN, 100-ball
BGA
68-QFN,
68-QFN,
[2]
Packages
100-ball BGA 100-ball BGA 100-ball BGA 100-ball BGA 100-ball BGA 100-ball BGA
100-ball BGA 100-ball BGA
Industrial
(88-QFN only)
and Commercial
Temperature
range
Industrial and Industrial and Industrial and Industrial and Industrial and Industrial and
Industrial and Industrial and
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Notes
1. DS1 and DS2 are Shared link Ports.
2. BGA Industrial Grade packages are limited to 1 W of active power. For power calculations refer to Table 10 on page 33.
Document Number: 001-73643 Rev. *R
Page 5 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Product Features
Shared Link
Figure 1. Application of Shared Link in a Notebook
Example: Shared Link Provides Six USB Ports in a Notebook
USB 3.0 Port Split Into SS Port and Standard USB 2.0 Port
Notebook PC
Motherboard
USB 3.0
Camera
USB 2.0
WiFi Module
Standard
USB 2.0 Port
SS
(internal)
4
USB 2.0
2
6
USB 3.0
DS4
6
6
Internal
SS Port
USB 3.0
USB 3.0
6
PC
Chipset
HX3
DS3
6
4
USB 3.0
2
USB 2.0
SS
(internal)
HX3
USB 3.0 Port
USB 3.0
Card Reader
Shared Link is a Cypress-proprietary feature that enables a
USB 3.0 port to be split into an embedded SS port and a
standard USB 2.0 port. Shared Link enables a maximum of eight
DS ports from a four-port USB 3.0 hub.
DSx_PWREN is another output signal generated by HX3 and
controls VBUS for the removable USB 2.0 device. For example,
when an overcurrent condition occurs, DSx_PWREN turns off
the port power.
For example, if one of the DS ports is connected to an embedded
SS device, such as a USB 3.0 camera, HX3 enables the system
designer to reuse the USB 2.0 signals of that specific port to
connect to a standard USB 2.0 port. Figure 1 shows how Shared
Link can be used in an application.
Ghost Charge
Ghost Charge is a Cypress-proprietary feature for charging USB
devices on the DS port when the US port is not connected to a
host. For example, in a docking station with HX3 as shown in
Figure 3, when the laptop is undocked, HX3 will emulate a
dedicated charging port (DCP) to provide charge to a phone
connected on a DS port.
Figure 2. DS Port VBUS Control in Shared Link
HX3
USB 3.0 DS Port
Figure 3. Ghost Charge
SuperSpeed
PHY
USB 2.0
PHY
Power to Smartphone
(HX3’s Downstream Port)
VBUS
VBUS
USB Cable
HX3
Removable
USB 2.0
Device
Embedded
SuperSpeed
Device
Notebook PC
Undocked
The Shared Link mode requires a separate VBUS control for the
removable USB 2.0 device and the embedded SS device.
Figure 2 shows the VBUS control implementation.
Charge a smartphone without docking the notebook
To ensure that the embedded SS device does not fall back to
USB 2.0 operation, an external power switch is required. This
switch is controlled by HX3, which generates an output signal
called DSx_VBUSEN_SL. This signal controls the VBUS for the
embedded device.
Document Number: 001-73643 Rev. *R
Page 6 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
When the US port is disconnected from the host, HX3 detects if
any of the DS ports are connected to a device requesting
charging. It determines the charging method and then switches
to the appropriate signaling based on the detected charging
specification as shown in Figure 4. The hub either emulates a
USB-compliant dedicated charging port by connecting DP and
DM (see the BC v1.2 specification) or other supported
proprietary charging schemes.
ACA-Dock Support
In traditional USB topologies, the host provides VBUS to enable
and charge the connected devices. For OTG hosts, however, an
ACA-Dock provides VBUS and a method to charge the host.
HX3 supports the ACA-Dock standard (see BC v1.2 specifi-
cation) by integrating the functions of the adapter controller.
Figure 5 shows the ACA-Dock system. If the ACA-Dock feature
is enabled, HX3 turns on the external power switch to drive
VBUS on the US port. To inform the OTG host that it is connected
to an ACA-Dock, the ID pin is tied to ground using a resistor
Figure 4. Ghost Charge Implementation in HX3
HX3 DS PORT
3
RID_A, as shown in Figure 5. The ACA-Dock feature can be
disabled using the Configuration Options on page 24.
Other
BC v1.2
Charging
Scheme
Scheme
For example, a BC v1.2 compliant phone such as a Sony Xperia
(neo V) can be docked to a HX3-based ACA-Dock system. The
phone acts as an OTG host and the ACA-Dock charges the
phone connected to the US port while also powering the four DS
ports.
Charging
Scheme
Detector
Figure 5. ACA-Dock Support
5 V
VBUS
Power
Source
Power
Switch
VBUS
5 V
US_PWREN
Battery
Power
Switch
HX3
Wall Charger
Charger
Detector
USB Battery-Powered Device
VBUS
To US OTG
Enabled Device
RID_A
Ghost Charge is enabled by default and can be disabled through
configuration. Refer to Configuration Options on page 24.
ID
VBUS
Micro A Plug
PCB
Vendor-Command Support
HX3 supports vendor-specific requests and can also enumerate
as a vendor-specific device. The vendor-specific request can be
2
used to (a) bridge USB and I C and (b) configure HX3. This
feature can be used for the following applications:
■ Firmware upgrade of an external ASSP connected to HX3
through USB
■ In-System programming (ISP) of an EEPROM connected to
HX3 through USB
Note
3. 124 k is the recommended RID_A value as per BC v1.2 specification, but some portable devices use custom RID_A values.
Document Number: 001-73643 Rev. *R
Page 7 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Pin Information
Figure 6. HX3 68-Pin QFN 2-Port Pinout
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
DVDD12
1
2
3
51 DS1_RXP
RREF_USB2
DVDD12
DS1_RXM
DVDD12
50
49
DS1_TXM
DS1_TXP
AVDD12
4
5
48
47
AVDD33
US_TXM
6
7
46
US_TXP
DVDD12
45 DS2_RXP
DS2_RXM
8
9
44
43 DVDD12
DS2_TXM
US_RXM
US_RXP
68-Pin QFN
10
42
41 DS2_TXP
40
AVDD12
NC 11
NC 12
GND
13
NC 14
NC
39 NC
38 NC
DVDD12
DVDD12
15
37
AVDD12 16
36 NC
NC
35
VBUS_US 17
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Document Number: 001-73643 Rev. *R
Page 8 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Figure 7. HX3 68-Pin QFN 4-Port Pinout
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
DVDD12
RREF_USB2
DVDD12
1
2
3
51 DS1_RXP
DS1_RXM
DVDD12
50
49
DS1_TXM
DS1_TXP
AVDD12
4
5
48
47
AVDD33
US_TXM
US_TXP
DVDD12
6
7
46
45 DS2_RXP
DS2_RXM
8
9
44
43 DVDD12
DS2_TXM
US_RXM
US_RXP
68-Pin QFN
10
42
41 DS2_TXP
40
AVDD12
DS4_TXP 11
DS4_TXM 12
GND
13
DS4_RXM 14
DS4_RXP
39 DS3_TXM
38 DS3_TXP
DVDD12
DVDD12
15
37
36
35
DS3_RXM
AVDD12 16
DS3_RXP
VBUS_US 17
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Document Number: 001-73643 Rev. *R
Page 9 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Figure 8. HX3 100-Ball BGA Pinout for CYUSB3302
A1
NC
A2
NC
B2
NC
C2
NC
D2
NC
E2
A3
NC
B3
NC
C3
NC
D3
NC
E3
A4
AVDD33
B4
A5
DS2_DM
B5
A6
DS2_DP
B6
A7
AVDD33
B7
A8
US_DM
B8
A9
US_DP
B9
A10
AVDD12
B10
B1
NC
VDD_IO
C4
VSS
C5
AVDD33
C6
NC
NC
NC
DVDD12
C10
C1
C7
C8
C9
US_TXM
D1
NC
NC
VSS
DS1_DP
D7
DS1_DM
D8
AVDD12
D9
DS1_RXM
D10
D4
D5
D6
US_TXP
E1
DVDD12
E4
VSS
E5
DVDD12
E6
VSS
E7
DVDD12
E8
VSS
E9
DS1_RXP
E10
RREF_US
B2
DVDD12
F1
NC
F3
NC
XTL_IN
F5
XTL_OUT
VDD_IO
F7
DS1_TXM
F8
VSS
F9
DVDD12
F10
F2
VSS
G2
F4
F6
MODE_SE
L[1]
OVRCUR
R
US_RXM
G1
AVDD33
G3
DVDD12
G5
RESETN
G7
DS1_TXP
G8
AVDD12
G9
DS2_RXP
G10
G4
G6
VDD_IO
H6
RESERVE MODE_SE
US_RXP VBUS_DS SUSPEND
PWR_EN I2C_DATA
H7 H8
DS2_TXM DS2_TXP
VSS
H9
DS2_RXM
H10
D1
L[0]
H1
H2
H3
H4
H5
VDD_EFU RESERVE
AVDD12
VBUS_US
RREF_SS
VSS
NC
AVDD12
SE
D2
J1
VSS
K1
J2
AVDD12
K2
J3
J4
J5
NC
K5
NC
J6
I2C_CLK
K6
J7
NC
K7
NC
J8
NC
K8
NC
J9
VSS
J10
NC
VSS
K3
GPIO
K4
K9
K10
NC
NC
NC
DVDD12
NC
NC
DVDD12
Document Number: 001-73643 Rev. *R
Page 10 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Figure 9. HX3 100-Ball BGA Pinout for CYUSB3304
A1
NC
A2
DS4_DM
B2
A3
DS4_DP
B3
A4
AVDD33
B4
A5
DS2_DM
B5
A6
DS2_DP
B6
A7
AVDD33
B7
A8
US_DM
B8
A9
US_DP
B9
A10
AVDD12
B10
B1
NC
NC
NC
VDD_IO
C4
VSS
AVDD33
C6
NC
NC
NC
DVDD12
10
C1
C2
C3
C5
C7
C8
C9
US_TXM
D1
NC
NC
DS3_DP
D4
DS3_DM
D5
VSS
DS1_DP
D7
DS1_DM
D8
AVDD12
D9
DS1_RXM
D10
D2
D3
D6
US_TXP
E1
NC
NC
DVDD12
E4
VSS
DVDD12
E6
VSS
E7
DVDD12
E8
VSS
E9
DS1_RXP
E10
E2
E3
E5
RREF_US
B2
DVDD12
F1
NC
F3
NC
XTL_IN
F5
XTL_OUT
VDD_IO
F7
DS1_TXM
F8
VSS
F9
DVDD12
F10
F2
VSS
G2
F4
F6
MODE_SE
L[1]
OVRCUR
R
US_RXM
G1
AVDD33
G3
DVDD12
G5
RESETN
G7
DS1_TXP
G8
AVDD12
G9
DS2_RXP
G10
G4
G6
VDD_IO
H6
RESERVE MODE_SE
US_RXP VBUS_DS SUSPEND
PWR_EN I2C_DATA
H7 H8
DS2_TXM DS2_TXP
VSS
H9
DS2_RXM
H10
D1
L[0]
H1
H2
H3
H4
H5
VDD_EFU RESERVE
AVDD12
VBUS_US
RREF_SS
VSS
NC
AVDD12
SE
D2
J1
VSS
K1
J2
AVDD12
K2
J3
J4
J5
NC
K5
J6
I2C_CLK
K6
J7
NC
K7
J8
NC
K8
J9
VSS
J10
VSS
K3
GPIO
K4
DS3_RXM
K10
K9
DS4_TXP DS4_TXM
DVDD12
DS4_RXP DS4_RXM
NC
DS3_TXP DS3_TXM
DVDD12
DS3_RXP
Document Number: 001-73643 Rev. *R
Page 11 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Table 2. 68-Pin QFN, 100-Ball BGA Pinout for CYUSB3302 and CYUSB3304
Pin Name
100-BGA
CYUSB3302 CYUSB3304
Type 68-QFN Pin#
Description
Ball #
US Port
US_RXP
US_RXM
US_TXP
US_TXM
US_DP
I
9
8
G1
F1
D1
C1
A9
A8
SuperSpeed receive plus
I
SuperSpeed receive minus
SuperSpeed transmit plus
SuperSpeed transmit minus
USB 2.0 data plus
O
6
O
5
I/O
I/O
57
58
US_DM
USB 2.0 data minus
DS1 Port
DS1_RXP
DS1_RXM
DS1_TXP
DS1_TXM
DS1_DP
I
51
50
47
48
60
59
D10
C10
F8
SuperSpeed receive plus
SuperSpeed receive minus
SuperSpeed transmit plus
SuperSpeed transmit minus
USB 2.0 data plus
I
O
O
E8
I/O
I/O
C7
DS1_DM
C8
USB 2.0 data minus
DS2 Port
DS2_RXP
DS2_RXM
DS2_TXP
DS2_TXM
DS2_DP
I
45
44
41
42
62
63
F10
G10
H8
SuperSpeed receive plus
SuperSpeed receive minus
SuperSpeed transmit plus
SuperSpeed transmit minus
USB 2.0 data plus
I
O
O
H7
I/O
I/O
A6
DS2_DM
A5
USB 2.0 data minus
DS3 Port
NC
NC
NC
NC
NC
NC
DS3_RXP
I
35
36
38
39
65
64
K10
J10
K7
SuperSpeed receive plus
SuperSpeed receive minus
SuperSpeed transmit plus
SuperSpeed transmit minus
USB 2.0 data plus
DS3_RXM
DS3_TXP
DS3_TXM
DS3_DP
I
O
O
K8
I/O
I/O
C4
C5
DS3_DM
USB 2.0 data minus
DS4 Port
NC
NC
NC
NC
NC
NC
DS4_RXP
DS4_RXM
DS4_TXP
DS4_TXM
DS4_DP
I
15
14
11
12
67
68
30
29
25
K4
K5
K1
K2
A3
A2
F6
G7
NA
SuperSpeed receive plus
SuperSpeed receive minus
SuperSpeed transmit plus
SuperSpeed transmit minus
USB 2.0 data plus
I
O
O
I/O
I/O
I
DS4_DM
USB 2.0 data minus
OVRCURR
Ganged overcurrent input
Ganged power enable output
NC
PWR_EN
NC
I/O
I/O
Document Number: 001-73643 Rev. *R
Page 12 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Table 2. 68-Pin QFN, 100-Ball BGA Pinout for CYUSB3302 and CYUSB3304 (continued)
Pin Name
CYUSB3302 CYUSB3304
RESERVED1
100-BGA
Ball #
Type 68-QFN Pin#
Description
G4
H4
This pin must be pulled HIGH using a 10 k to VDD_IO.
This pin must be pulled HIGH using a 10 k to VDD_IO.
I/O
I
21
22
RESERVED2
Mode Select, Clock, and Reset
MODE_SEL[0]
MODE_SEL[1]
XTL_OUT
XTL_IN
I
I
23
24
54
55
31
32
33
G5
F4
E6
E5
F7
J6
Device operation mode select bit 0; refer to Table 5 on page 24
Device operation mode select bit 1; refer to Table 5 on page 24
A
Crystal out
A
Crystal in
RESETN
I
Active LOW reset input
2
I2C_CLK
I/O
I/O
I C clock
2
I2C_DATA
G8
I C data
Hub suspend status indicator. This pin is asserted if both the
SS and USB 2.0 hubs are in the suspend state and is
de-asserted when either of the hubs comes out of the suspend
state.
SUSPEND
I/O
20
G3
Power and Ground
1.2 V normal operation, 2.5 V for programming. Customers
VDD_EFUSE
AVDD12
PWR
PWR
19
H3
should connect to 1.2 V.
10, 16, 34, 46, A10, C9, F9,
1.2 V analog supply
52, 53
H1, H10, J2
B5,C6,D5,D7,
D9,E9,F2,G9, GND pin
H6, J1, J3, J9
GND
PWR
40
B10, D4, D6,
D8, E1, E10, 1.2 V core supply
F5, K3, K9
1, 3, 7, 13, 27,
37, 43, 49,
DVDD12
VBUS _US
VBUS_DS
PWR
PWR
PWR
17
18
H2
This pin must be connected to VBUS from US port
This pin is used to power the Apple-charging circuit in HX3.
For BC v1.2 compliance testing, connect pin to GND. For
normal operation, connect pin to local 5 V supply.
G2
AVDD33
VDD_IO
PWR 4, 56, 61, 66 A4, A7, B6, F3 3.3 V analog supply
PWR
28
B4, E7, G6 3.3 V I/O supply
USB Precision Resistors
Connect pin to a precision resistor (6.04 k±1%) to generate
RREF_USB2
RREF_SS
A
A
2
E2
H5
a current reference for USB 2.0 PHY.
Connect pin to a precision resistor (200 ±1%) for SS PHY
termination impedance calibration.
26
Note
4. These pins are Do Not Use (DNU); they must be left floating.
Document Number: 001-73643 Rev. *R
Page 13 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Table 3. 68-Pin QFN, 100-Ball BGA Pinout for CYUSB2302 and CYUSB2304
Pin Name
100-BGA
CYUSB2302 CYUSB2304
Type 68-QFN Pin#
Description
Ball #
US Port
NC
NC
I
I
9
8
G1
F1
D1
C1
A9
A8
SuperSpeed receive plus
SuperSpeed receive minus
SuperSpeed transmit plus
SuperSpeed transmit minus
USB 2.0 data plus
NC
O
6
NC
O
5
US_DP
US_DM
I/O
I/O
57
58
USB 2.0 data minus
DS1 Port
NC
NC
I
51
50
47
48
60
59
D10
C10
F8
SuperSpeed receive plus
SuperSpeed receive minus
SuperSpeed transmit plus
SuperSpeed transmit minus
USB 2.0 data plus
I
NC
O
NC
O
E8
DS1_DP
DS1_DM
I/O
I/O
C7
C8
USB 2.0 data minus
DS2 Port
NC
NC
I
45
44
41
42
62
63
F10
G10
H8
SuperSpeed receive plus
SuperSpeed receive minus
SuperSpeed transmit plus
SuperSpeed transmit minus
USB 2.0 data plus
I
NC
O
NC
O
H7
DS2_DP
DS2_DM
I/O
I/O
A6
A5
USB 2.0 data minus
DS3 Port
I
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
35
36
38
39
65
64
K10
J10
K7
SuperSpeed receive plus
SuperSpeed receive minus
SuperSpeed transmit plus
SuperSpeed transmit minus
USB 2.0 data plus
I
O
O
K8
DS3_DP
DS3_DM
I/O
I/O
C4
C5
USB 2.0 data minus
DS4 Port
NC
NC
NC
NC
NC
NC
NC
NC
I
15
14
11
12
67
68
30
29
25
K4
K5
K1
K2
A3
A2
F6
G7
NA
SuperSpeed receive plus
SuperSpeed receive minus
SuperSpeed transmit plus
SuperSpeed transmit minus
USB 2.0 data plus
I
NC
O
NC
O
DS4_DP
DS4_DM
I/O
I/O
I
USB 2.0 data minus
OVRCURR
Ganged overcurrent input
Ganged power enable output
NC
PWR_EN
NC
I/O
I/O
Document Number: 001-73643 Rev. *R
Page 14 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Table 3. 68-Pin QFN, 100-Ball BGA Pinout for CYUSB2302 and CYUSB2304 (continued)
Pin Name
CYUSB2302 CYUSB2304
RESERVED1
100-BGA
Ball #
Type 68-QFN Pin#
Description
G4
H4
This pin must be pulled HIGH using a 10 k to VDD_IO.
This pin must be pulled HIGH using a 10 k to VDD_IO.
I/O
I
21
22
RESERVED2
Mode Select, Clock, and Reset
MODE_SEL[0]
MODE_SEL[1]
XTL_OUT
XTL_IN
I
I
23
24
54
55
31
32
33
G5
F4
E6
E5
F7
J6
Device operation mode select bit 0; refer to Table 5 on page 24
Device operation mode select bit 1; refer to Table 5 on page 24
A
Crystal out
A
Crystal in
RESETN
I
Active LOW reset input
2
I2C_CLK
I/O
I/O
I C clock
2
I2C_DATA
G8
I C data
Hub suspend status indicator. This pin is asserted if both the
SS and USB 2.0 hubs are in the suspend state and is
de-asserted when either of the hubs comes out of the suspend
state.
SUSPEND
I/O
20
G3
Power and Ground
1.2 V normal operation, 2.5 V for programming. Customers
VDD_EFUSE
AVDD12
PWR
PWR
19
H3
should connect to 1.2 V.
10, 16, 34, 46, A10, C9, F9,
1.2 V analog supply
52, 53
H1, H10, J2
B5,C6,D5,D7,
D9,E9,F2,G9, GND pin
H6, J1, J3, J9
GND
PWR
40
B10, D4, D6,
D8, E1, E10, 1.2 V core supply
F5, K3, K9
1, 3, 7, 13, 27,
37, 43, 49,
DVDD12
VBUS _US
VBUS_DS
PWR
PWR
PWR
17
18
H2
This pin must be connected to VBUS from US port
This pin is used to power the Apple-charging circuit in HX3.
For BC v1.2 compliance testing, connect pin to GND. For
normal operation, connect pin to local 5 V supply.
G2
AVDD33
VDD_IO
PWR 4, 56, 61, 66 A4, A7, B6, F3 3.3 V analog supply
PWR
28
B4, E7, G6 3.3 V I/O supply
USB Precision Resistors
Connect pin to a precision resistor (6.04 k±1%) to generate
RREF_USB2
RREF_SS
A
A
2
E2
H5
a current reference for USB 2.0 PHY.
Connect pin to a precision resistor (200 ±1%) for SS PHY
termination impedance calibration.
26
Document Number: 001-73643 Rev. *R
Page 15 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Figure 10. HX3 88-Pin QFN 2-Port Pinout
88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
70 69 68 67
72 71
DS2_OVRCURR
DS1_AMBER
DS1_GREEN
1
2
3
66 VDD_IO
65 DS3_OVRCURR
64 DS3_GREEN
DS1_LED_SS
DS2_AMBER
4
5
63 DS3_LED_SS
62
61
AVDD12
DS1_RXP
DS2_GREEN
RREF_USB2
6
7
60 DS1_RXM
DVDD12
AVDD33
8
9
59 DVDD12
58 DS1_TXM
US_TXM
10
57 DS1_TXP
56 AVDD12
55 DS2_RXP
US_TXP 11
DVDD12 12
US_RXM 13
US_RXP 14
88-Pin QFN
54
53 DVDD12
DS2_TXM
52
DS2_RXM
AVDD12 15
NC 16
51 DS2_TXP
50 GND
49 NC
NC 17
DVDD12 18
NC 19
48 NC
NC
DVDD12
20
47
AVDD12 21
46 NC
45 NC
VBUS_US 22
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Document Number: 001-73643 Rev. *R
Page 16 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Figure 11. HX3 88-Pin QFN 4-Port Pinout
88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
70 69 68 67
72 71
DS2_OVRCURR
DS1_AMBER
1
2
3
66 VDD_IO
65 DS3_OVRCURR
64 DS3_GREEN
DS1_GREEN
DS1_LED_SS
DS2_AMBER
4
5
63 DS3_LED_SS
62 AVDD12
DS1_RXP
61
DS2_GREEN
RREF_USB2
6
7
60 DS1_RXM
DVDD12
AVDD33
8
9
59 DVDD12
58 DS1_TXM
US_TXM
10
57 DS1_TXP
56 AVDD12
55 DS2_RXP
US_TXP 11
DVDD12 12
US_RXM 13
US_RXP 14
88-Pin QFN
54
53 DVDD12
DS2_TXM
52
DS2_RXM
AVDD12 15
DS4_TXP 16
DS4_TXM 17
DVDD12 18
51 DS2_TXP
50 GND
49 DS3_TXM
48 DS3_TXP
DS4_RXM
DS4_RXP
19
20
DVDD12
46 DS3_RXM
47
AVDD12 21
VBUS_US 22
45
DS3_RXP
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Document Number: 001-73643 Rev. *R
Page 17 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Figure 12. HX3 100-Ball BGA Pinout for CYUSB3312
A1
A2
NC
B2
A3
NC
B3
A4
AVDD33
B4
A5
DS2_DM
B5
A6
DS2_DP
B6
A7
AVDD33
B7
A8
US_DM
B8
A9
US_DP
B9
A10
AVDD12
B10
DS3_PWR
EN
B1
DS2_OVR DS2_PWR DS3_AMBE
DS3_OVR DS3_GREE DS3_LED_
VDD_IO
C4
VSS
C5
AVDD33
C6
DVDD12
C10
CURR
EN
R
CURR
N
SS
C1
C2
C3
C7
C8
C9
DS1_AMBE DS2_LED_
US_TXM
D1
NC
NC
VSS
DS1_DP
D7
DS1_DM
D8
AVDD12
D9
DS1_RXM
D10
R
SS
D2
D3
D4
D5
D6
DS1_LED_ DS1_GREE
US_TXP
E1
DVDD12
VSS
E5
DVDD12
E6
VSS
DVDD12
E8
VSS
E9
DS1_RXP
E10
SS
N
E2
E3
E4
E7
RREF_USB DS2_GREE DS2_AMBE
DVDD12
F1
XTL_IN
F5
XTL_OUT
F6
VDD_IO
F7
DS1_TXM
F8
VSS
F9
DVDD12
F10
2
N
R
F2
F3
F4
MODE_SE
L[1]
DS4_OVR
CURR
US_RXM
G1
VSS
AVDD33
DVDD12
G5
RESETN
G7
DS1_TXP
G8
AVDD12
G9
DS2_RXP
G10
G2
G3
G4
G6
VDD_IO
H6
RESERVE MODE_SE
DS4_PWR
EN
US_RXP VBUS_DS SUSPEND
I2C_DATA
H8
VSS
H9
DS2_RXM
H10
D1
L[0]
H1
AVDD12
J1
H2
VBUS_US
J2
H3
H4
H5
H7
VDD_EFUS DS4_LED_
DS4_GREE
N
RREF_SS
VSS
DS2_TXM DS2_TXP
J7 J8
DS1_PWR DS1_OVR
AVDD12
J10
E
SS
J3
J4
J5
J6
J9
DS4_AMBE US_PWRE
VSS
K1
AVDD12
K2
VSS
K3
I2C_CLK
K6
VSS
NC
R
N
EN
CURR
K4
K5
K7
K8
K9
K10
US_OVRC
URR
NC
NC
DVDD12
NC
NC
NC
NC
DVDD12
NC
Document Number: 001-73643 Rev. *R
Page 18 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Figure 13. HX3 100-Ball BGA Pinout for CYUSB3314, CYUSB332x
A1
A2
DS4_DM
B2
A3
DS4_DP
B3
A4
AVDD33
B4
A5
DS2_DM
B5
A6
DS2_DP
B6
A7
AVDD33
B7
A8
US_DM
B8
A9
US_DP
B9
A10
AVDD12
B10
DS3_PWR
EN
B1
DS2_OVR DS2_PWR DS3_AMB
DS3_OVR DS3_GRE DS3_LED
VDD_IO
C4
VSS
AVDD33
C6
DVDD12
C10
CURR
EN
ER
CURR
EN
_SS
C1
C2
C3
C5
C7
C8
C9
DS1_AMB DS2_LED
US_TXM
D1
DS3_DP
D4
DS3_DM
D5
VSS
DS1_DP
D7
DS1_DM
D8
AVDD12
D9
DS1_RXM
D10
ER
_SS
D2
D3
D6
DS1_LED DS1_GRE
US_TXP
E1
DVDD12
E4
VSS
DVDD12
E6
VSS
DVDD12
E8
VSS
E9
DS1_RXP
E10
_SS
EN
E2
E3
E5
E7
RREF_US DS2_GRE DS2_AMB
DVDD12
F1
XTL_IN
F5
XTL_OUT
VDD_IO
F7
DS1_TXM
F8
VSS
F9
DVDD12
F10
B2
EN
ER
F2
F3
F4
F6
MODE_SE
L[1]
DS4_OVR
CURR
US_RXM
G1
VSS
AVDD33
DVDD12
G5
RESETN
G7
DS1_TXP
G8
AVDD12
G9
DS2_RXP
G10
G2
G3
G4
G6
VDD_IO
H6
RESERVE MODE_SE
DS4_PWR
EN
US_RXP VBUS_DS SUSPEND
I2C_DATA
H8
VSS
DS2_RXM
H10
D1
L[0]
H1
AVDD12
J1
H2
VBUS_US
J2
H3
H4
H5
H7
H9
VDD_EFU DS4_LED
DS4_GRE
EN
RREF_SS
VSS
DS2_TXM DS2_TXP
J7 J8
DS1_PWR DS1_OVR
AVDD12
J10
SE
_SS
J3
J4
J5
J6
J9
DS4_AMB US_PWR
VSS
K1
AVDD12
K2
VSS
K3
I2C_CLK
K6
VSS
DS3_RXM
K10
ER
EN
EN
CURR
K4
K5
K7
K8
K9
US_OVRC
URR
DS4_TXP DS4_TXM
DVDD12
DS4_RXP DS4_RXM
DS3_TXP DS3_TXM
DVDD12
DS3_RXP
Document Number: 001-73643 Rev. *R
Page 19 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Table 4. 88-Pin QFN, 100-Ball BGA Pinout for CYUSB331X and CYUSB332X
Pin Name
CYUSB3314
CYUSB3324 Type
CYUSB3326
Pin#
Ball#
Description
CYUSB3312
CYUSB3328
US Port
US_RXP
US_RXM
I
I
14
13
11
10
71
72
G1
F1
D1
C1
A9
A8
SuperSpeed receive plus
SuperSpeed receive minus
SuperSpeed transmit plus
SuperSpeed transmit minus
USB 2.0 data plus
US_TXP
US_TXM
US_DP
O
O
I/O
I/O
US_DM
USB 2.0 data minus
CYUSB3324/3328: Overcurrent detect input for US port in ACA-Dock
mode. If ACA-Dock mode is disabled using Configuration Options on
page 24, this pin must be pulled HIGH using a 10 k to VDD_IO.
Other part numbers: This pin must be pulled HIGH using a 10 k to
VDD_IO.
US_OVRCURR
I
39
K6
CYUSB3324/3328: VBUS power enable output for US port in ACA-Dock
mode. If ACA-Dock mode is disabled using Configuration Options on
page 24, this pin can be left floating if Pin-Strap is not enabled.
Other part numbers: This pin can be left floating if Pin-Strap (Pin# 63) is
not enabled.
[5]
US_PWREN
I/O
31
J5
[6]
PWR_SW_POL
This pin is called PWR_SW_POL in pin-strap configuration mode.
DS1 Port
DS1_RXP
DS1_RXM
DS1_TXP
I
I
61
60
57
58
74
73
42
D10
C10
F8
SuperSpeed receive plus
SuperSpeed receive minus
SuperSpeed transmit plus
SuperSpeed transmit minus
USB 2.0 data plus
O
O
I/O
I/O
I
DS1_TXM
DS1_DP
E8
C7
C8
J8
DS1_DM
USB 2.0 data minus
DS1_OVRCURR
Overcurrent detect input for DS1 port
VBUS power enable output for DS1 port. When the port is disabled, this
pin is in tristate.
[5]
DS1_PWREN
I/O
38
J7
[6]
DS1_CDP_EN
This pin is called DS1_CDP_EN in pin-strap configuration mode.
[5]
DS1_AMBER
LED_AMBER output for DS1 port
I/O
I/O
2
3
C2
D3
[6]
ACA_DOCK
This pin is called ACA-DOCK in pin-strap configuration mode.
CYUSB3312/3314/3324: LED_GREEN output for DS1 port
CYUSB3326/3328: VBUS power enable output for SS port 1
This pin is called PORT_DISABLE[0] in pin-strap configuration mode.
LED_SS output for DS1 port
[5]
DS1_GREEN
[5]
[6]
DS1_VBUSEN_SL
PORT_DISABLE[0]
[5]
DS1_LED_SS
I/O
4
D2
[6]
PORT_DISABLE[1]
This pin is called PORT_DISABLE[1] in pin-strap configuration mode.
Notes
5. This pin can be configured as a GPIO using custom firmware. For information contact www.cypress.com/support.
6. For pin-strap configuration details, refer to Table 6 on page 25.
Document Number: 001-73643 Rev. *R
Page 20 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Table 4. 88-Pin QFN, 100-Ball BGA Pinout for CYUSB331X and CYUSB332X (continued)
Pin Name
CYUSB3314
CYUSB3324 Type
CYUSB3326
Pin#
Ball#
Description
CYUSB3312
CYUSB3328
DS2 Port
DS2_RXP
DS2_RXM
I
I
55
54
51
52
76
77
1
F10
G10
H8
SuperSpeed receive plus
SuperSpeed receive minus
SuperSpeed transmit plus
SuperSpeed transmit minus
USB 2.0 data plus
DS2_TXP
DS2_TXM
O
O
I/O
I/O
I
H7
DS2_DP
A6
DS2_DM
A5
USB 2.0 data minus
DS2_OVRCURR
B1
Overcurrent detect input for DS2 port
VBUS power enable output for DS2 port. When the port is disabled, this
pin is in tristate.
[7]
DS2_PWREN
I/O
I/O
86
5
B2
E4
[8]
DS2_CDP_EN
This pin is called DS2_CDP_EN in the pin-strap configuration mode.
LED_AMBER output for DS2 port
[7]
DS2_AMBER
This pin is called NON_REMOVABLE[0] in the pin-strap configuration
mode.
[8]
NON_REMOVABLE[0]
[7]
DS2_GREEN
CYUSB3312/3314/3324: LED_GREEN output for DS2 port
CYUSB3326/3328: VBUS power enable output for SS port 2
[7]
DS2_VBUSEN_SL
I/O
I/O
6
E3
C3
This pin is called NON_REMOVABLE[1] in the pin-strap configuration
mode.
[8]
NON_REMOVABLE[1]
[7]
DS2_LED_SS
LED_SS output for DS2 port
This pin is called PWR_EN_SEL in the pin-strap configuration mode.
DS3 Port
84
[8]
PWR_EN_SEL
NC
NC
NC
NC
NC
NC
DS3_RXP
DS3_RXM
DS3_TXP
DS3_TXM
DS3_DP
I
I
45
46
48
49
79
78
K10
J10
K7
SuperSpeed receive plus
SuperSpeed receive minus
SuperSpeed transmit plus
SuperSpeed transmit minus
USB 2.0 data plus
O
O
K8
I/O
I/O
C4
C5
DS3_DM
USB 2.0 data minus
CYUSB3314/3324/3326/3328: Overcurrent detect input for DS3 port
CYUSB3312: This pin must be pulled HIGH using a 10 k to VDD_IO.
DS3_OVRCURR
I
65
B7
VBUS power enable output for DS3 port. When the port is disabled, this
pin is in tristate.
[7]
DS3_PWREN
I/O
87
A1
[8]
DS3_CDP_EN
This pin is called DS3_CDP_EN in the pin-strap configuration mode.
LED_AMBER output for DS3 port
[7]
DS3_AMBER
I/O
85
B3
[8]
VID_SEL[2]
This pin is called VID_SEL[2] in the pin-strap configuration mode.
Notes
7. This pin can be configured as a GPIO using custom firmware. For information contact www.cypress.com/support.
8. For pin-strap configuration details, refer to Table 6 on page 25.
Document Number: 001-73643 Rev. *R
Page 21 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Table 4. 88-Pin QFN, 100-Ball BGA Pinout for CYUSB331X and CYUSB332X (continued)
Pin Name
CYUSB3314
CYUSB3324 Type
Pin#
Ball#
Description
CYUSB3312
CYUSB3326
CYUSB3328
[9]
DS3_GREEN
CYUSB3312/3314/3324: LED_GREEN output for DS3 port
CYUSB3328: VBUS power enable output for SS port 3
[9]
DS3_VBUSEN_SL
I/O
I/O
64
63
B8
B9
This pin is called VID_SEL[1] in the pin-strap configuration mode. For
pin-strap configuration details, refer to Table 6 on page 25.
[10]
VID_SEL[1]
[9]
DS3_LED_SS
LED_SS output for DS3 port
This pin is called PIN_STRAP in pin-strap configuration mode. When
connected to VDD_IO through a 10-k resistor, this pin enables
pin-strap configuration mode for HX3.
[10]
PIN_STRAP
DS4 Port
NC
NC
NC
NC
NC
NC
DS4_RXP
DS4_RXM
DS4_TXP
DS4_TXM
DS4_DP
I
I
20
19
16
17
81
82
K4
K5
K1
K2
A3
A2
SuperSpeed receive plus
SuperSpeed receive minus
SuperSpeed transmit plus
SuperSpeed transmit minus
USB 2.0 data plus
O
O
I/O
I/O
DS4_DM
USB 2.0 data minus
CYUSB3314/3324/3326/3328: Overcurrent detect input for DS4 port.
CYUSB3312: This pin must be pulled HIGH using a 10 k to VDD_IO.
DS4_OVRCURR
I
36
F6
VBUS power enable output for DS4 port. This pin is also used as power
enable output when configured in ganged power mode using the Blaster
Plus tool. When the port is disabled, this pin is in tristate.
DS4_PWREN/PWR_EN4
I/O
35
G7
[10]
DS4_CDP_EN
This pin is called DS4_CDP_EN in the pin-strap configuration mode.
LED_AMBER output for DS4 port
[9]
DS4_AMBER
I/O
I/O
30
43
J4
[10]
I2C_DEV_ID
This pin is called I2C_DEV_ID in the pin-strap configuration mode.
CYUSB3312/3314/3324: LED_GREEN output for DS4 port
CYUSB3328: VBUS power enable output for SS port 4
This pin is called VID_SEL[0] in the pin-strap configuration mode.
[9]
DS4_GREEN
DS4_VBUSEN_SL
H9
[10]
VID_SEL[0]
LED_SS output for DS4 port. The LED must be connected to GND as
shown in Figure 16 on page 25. If LED is not used, this pin must be pulled
HIGH using a 10 k to VDD_IO.
DS4_LED_SS
RESERVED1
H4
G4
I/O
I
26
27
This pin must be pulled HIGH using a 10 k to VDD_IO.
Mode Select, Clock, and Reset
MODE_SEL[0]
MODE_SEL[1]
XTL_OUT
XTL_IN
I
I
28
29
68
69
37
40
41
G5
F4
E6
E5
F7
J6
Device operation mode select bit 0; refer to Table 5 on page 24
Device operation mode select bit 1; refer to Table 5 on page 24
A
Crystal out
A
Crystal in
RESETN
I
Active LOW reset input
2
I2C_CLK
I/O
I/O
I C clock
2
I2C_DATA
G8
I C data
Notes
9. This pin can be configured as a GPIO using custom firmware. For information contact www.cypress.com/support.
10. For pin-strap configuration details, refer to Table 6 on page 25.
Document Number: 001-73643 Rev. *R
Page 22 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Table 4. 88-Pin QFN, 100-Ball BGA Pinout for CYUSB331X and CYUSB332X (continued)
Pin Name
CYUSB3314
CYUSB3324 Type
CYUSB3326
Pin#
Ball#
Description
CYUSB3312
CYUSB3328
Hub suspend status indicator. This pin is asserted if both the SS and
USB 2.0 hubs are in the suspend state and is de-asserted when either
of the hubs comes out of the suspend state.
SUSPEND
I/O
25
24
G3
Power and Ground
1.2 V normal operation, 2.5 V for programming. Customers should
connect to 1.2 V
VDD_EFUSE
PWR
H3
15, 21, A10, C9,
AVDD12
PWR 44, 56,
62, 67
F9, H1, 1.2 V analog supply
H10, J2
B5, C6,
D5, D7,
D9, E9,
GND pin
F2, G9,
H6, J1,
J3, J9
GND
PWR
PWR
50
B10, D4,
D6, D8,
E1, E10, 1.2 V core supply
F5, K3,
K9
8, 12,
18, 33,
47, 53,
59, 83
DVDD12
CYUSB3324/3328: Connect the VBUS_US pin to the local 5 V supply.
If ACA-Dock mode is disabled using Configuration Options on page 24,
this pin must be connected to VBUS from US port.
Other part numbers: This pin must be connected to VBUS from US port.
VBUS _US
VBUS_DS
PWR
PWR
22
23
H2
This pin is used to power the Apple-charging circuit in HX3.
For BC v1.2 compliance testing, connect pin to GND. For normal
operation, connect pin to local 5 V supply.
G2
9, 70,
75, 80
A4, A7,
B6, F3
AVDD33
VDD_IO
PWR
PWR
3.3 V analog supply
3.3 V I/O supply
34, 66,
88
B4, E7,
G6
USB Precision Resistors
Connect pin to a precision resistor (6.04 k ±1%) to generate a current
RREF_USB2
RREF_SS
A
A
7
E2
H5
reference for USB 2.0 PHY.
Connect pin to a precision resistor (200 ±1%) for SS PHY termination
impedance calibration.
32
Document Number: 001-73643 Rev. *R
Page 23 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
The RESETN pin can be tied to VDD_IO through an external
resistor and to ground (GND) through an external capacitor
(minimum 5 ms time constant), as shown in Figure 15. This
creates a clean reset signal for power-on reset (POR).
System Interfaces
Upstream Port (US)
This port is compliant with the USB 3.0 specification and includes
an integrated 1.5 k pull-up and termination resistors. It also
supports ACA-Dock to enable charging an OTG host connected
on the US port.
HX3 does not support internal brown-out detection. If the system
requires this feature, an external reset should be provided on the
RESETN pin when supplies are below their valid operating
ranges.
Downstream Ports (DS1, 2, 3, 4)
Figure 15. Reset Connection
DS ports are compliant with the USB 3.0 specification and
integrate 15 k pull-down and termination resistors. Ports can
be disabled or enabled, and can be set to removable or
non-removable options. BC v1.2 charging is enabled by default
and can be disabled on each DS port using the configuration
options (see Configuration Options).
VDD_IO
10 k
RESETN
1.5 µF
2
Communication Interfaces (I C)
The interface follows the Inter-IC Bus specification, version 3.0,
with support for the standard mode (100 kHz) and the fast mode
2
(400 kHz) frequencies. HX3 supports I C in the slave and master
2
modes. The I C interface supports the multi-master mode of
Configuration Mode Select
operation. Both the SCL and SDA signals require external
pull-up resistors based on the specification. VDD_IO for HX3 is
3.3 V and it is expected that the I C pull-up resistors will be
Configuration options are selected through the MODE_SEL pins
and the pin-strap enable pin (PIN_STRAP). After power-up,
these pins are sampled by an on-chip bootloader to determine
the configuration options (see Table 5).
2
connected to the same supply.
Oscillator
Table 5. HX3 Boot Sequence
HX3 requires an external crystal with a frequency of 26 MHz and
an accuracy of ±150 ppm in parallel resonant, fundamental
mode. The crystal drive circuit is capable of a low-power drive
level (<200 µW). The crystal connection to the XTL_OUT and
XTL_IN pins is shown in Figure 14.
MODE
SEL[1]
MODE
SEL[0]
HX3 Configuration Modes
0
1
0
1
Reserved. Do not use this mode.
Internal ROM configuration
Figure 14. Crystal Connection
2
2
I C Master, read configuration from I C
EEPROM
0
1
1
0
*
26 MHz
XTL_OUT
10 pF
2
2
XTL_IN
10 pF
I C Slave, configure from an external I C
*
Master
*
Download Cypress-provided firmware from www.cypress.com/hx3.
Configuration Options
HX3 can be configured by using one of the following:
GPIOs
HX3 GPIOs are used for overcurrent sensing, controlling
external power switches, and driving LEDs. These pins can sink
up to 4 mA current each. GPIOs also enable pin-straps for input
configuration. Refer to Table 6 for more details.
■ eFuse (one-time programmable memory)
■ Pin-Strap (read configuration from dedicated pins at power on)
2
■ External I C slave such as an EEPROM
2
Power Control
■ External I C master
2
The PWR_EN[1-4] and OV_CURR[1-4] pins interface HX3 to
external power switches. These pins are used to control power
switches for DS port power and monitor overcurrent conditions.
The power switch polarity and the power control mode (individual
and ganged) can be changed using the configuration options.
The I C master/slave configuration overrides the pin-strap
configuration. Pin-straps override the eFuse configuration, and
the eFuse configuration overrides the internal ROM
configuration.
eFuse Configuration
Reset
HX3 contains eFuses, which are OTP elements on the chip that
can be electrically blown. The eFuses are read by the bootloader
to determine the customer-specific configurations. eFuse
programming is supported only at factory and distributor
locations where programming conditions can be controlled.
eFuse programming is supported under the following conditions:
HX3 operates with two external power supplies, 3.3 V and 1.2 V.
There is no power sequencing requirement between these two
supplies. However, the RESETN pin should be held LOW until
both these supplies become stable.
Document Number: 001-73643 Rev. *R
Page 24 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Temperature range of 25 °C–70 °C and programming voltage of
2.5 V–2.7 V.
Figure 16. Pin-Strap With LED or LED-Only Connection
To GPIO
VDD_IO
Pin-Strap Configuration
800 –
1 k
10 k
Pin-straps are supported for select product options (see Table 1
on page 5) to provide reconfigurability without an additional
EEPROM. The pin-strap configuration is enabled by pulling the
Pin #63 of 88-pin QFN HIGH. Table 6 on page 25 shows the
configuration options supported through pin-straps and the
GPIOs used for this purpose. Figure 16 and Figure 17 show how
the GPIOs need to be connected if pin-strap and LED connection
are required or only pin-strap is required.
10 k
800 –
1 k
VSS
To GPIO
Pin-Strap HIGH
with LED
Pin-Strap LOW
with LED
Figure 17. Pin-Strap Connection
HX3 samples pin-strap GPIOs at power-up. Floating straps are
considered as invalid and the default configuration is used. If
PIN_STRAP (Pin #63 of 88-pin QFN) is floating, all strap inputs
are considered invalid. A GPIO is considered strapped “1” or “0”
when connected with a weak pull-up (10 k) or pull-down
(10 k) respectively. After the initial sampling at power-up and
reset, the GPIOs are used in their normal functions.
To GPIO
VDD_IO
10 k
10 k
To GPIO
VSS
Pin-Strap HIGH
Pin-Strap LOW
Table 6. Pin-Strap Configuration
88-QFN
[11]
[11]
Pin-Strap Name
Strapped ‘0’
Strapped ‘1’
Pin #
2
ID 0: HX3 I C slave address (7 bits) is 0x60.
This is also the default I C slave address for ID 1: HX3 I C slave address (7 bits) is 0x58
[12]
2
2
30
I2C_DEV_ID
the 68-pin QFN package.
Power enable and overcurrent will be active Power enable and overcurrent will be active
31
PWR_SW_POL
LOW
HIGH
2
ACA_DOCK
Disabled
Individual
Enabled
Gang
84
63
4
PWR_EN_SEL
[13]
PIN_STRAP
No pin-strapping
Pin-strapping configuration enabled
PORT_DISABLE[1]
PORT_DISABLE[1:0] =
b’00: DS1, DS2, DS3, DS4 active
b’01: DS1, DS2, DS3 active
b’10: DS1, DS2 active
3
PORT_DISABLE[0]
b’11: DS1 active
Pin-straps cannot enable ports disabled by factory setting.
[14]
[14]
6
5
NON_REMOVABLE[1]
NON_REMOVABLE[1:0] =
b’00: DS1, DS2, DS3, DS4 removable
b’01: DS1, DS2, DS3 removable
b’10: DS1, DS2 removable
b’11: DS1 removable
NON_REMOVABLE[0]
85
64
43
VID[2]
VID[1]
VID[0]
Reserved. If PIN_STRAP is enabled and CY VID is required, strap VID[2:0] to ‘1’.
strapped ‘0’
DS1 CDP enabled
DS2 CDP enabled
DS3 CDP enabled
DS4 CDP enabled
strapped ‘1’
strapped ‘0’
strapped ‘1’
DS1 CDP enabled
DS2 CDP enabled
DS3 CDP enabled
DS4 CDP enabled
[15]
38
DS1_CDP_EN
DS1 CDP disabled
DS2 CDP disabled
DS3 CDP disabled
DS4 CDP disabled
DS1 CDP disabled
DS2 CDP disabled
DS3 CDP disabled
DS4 CDP disabled
[15]
86
87
35
DS2_CDP_EN
[15]
DS3_CDP_EN
[15]
DS4_CDP_EN
Notes
11. See Figure 16 and Figure 17.
12. I2C_DEV_ID is valid only when HX3 is in I C slave mode.
2
13. VID, PORT_DISABLE, NON_REMOVABLE are group straps. If one of the pins in a group strap is floating (INVALID), that group input will be INVALID and the default
will not be overwritten.
14. These DS ports are exposed ports and the connected devices can be removed.
15. DSx_CDP_EN will be active LOW input when PWR_SW_POL is set to active LOW; similarly DSx_CDP_EN will be active HIGH input when PWR_SW_POL is set to
active HIGH.
Document Number: 001-73643 Rev. *R
Page 25 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
I2C Configuration
GUI-based tool to configure HX3. This tool allows to do the
following:
2
When enabled for I C configuration through the MODE_SEL
pins (See Table 5 on page 24), HX3 can be configured as an I C
master or as an I C slave. HX3’s configuration data is a
maximum of 197 bytes and HX3’s firmware is 10 KB. Note that
HX3’s firmware also includes configuration settings.
2
■ Download the Cypress-provided firmware from a PC via HX3's
2
2
US port and store it on an EEPROM connected to HX3’s I C
port.
■ Read the configuration settings from the EEPROM. These
settings are displayed in the Blaster Plus GUI. Modify settings
as required.
HX3 as I2C Master
2
HX3 reads configurations from an external I C EEPROM with
sizes ranging from 16 to 64 KB. An example of a supported
EEPROM is 24LC128. Based on the contents of the bSignature
and bImageType fields in Table 7 on page 26, HX3 performs one
of the following actions:
■ WritebacktheupdatedsettingsontotheEEPROM. Inaddition,
an image file can be created for external use.
The Blaster Plus tool, user guide, and the Cypress-provided
firmware are available at www.cypress.com/hx3.
■ Loads custom configuration settings from the EEPROM when
bSignature is “CY” and bImageType is 0xD4.
HX3 as I2C Slave
2
An external I C master can program the configuration settings
■ LoadstheCypress-providedfirmwarefromtheEEPROMwhen
bSignatureis“CY”andbImageTypeis0xB0. Thisfirmwarealso
includes configuration settings.
into HX3 according to the EEPROM map in Table 7 on page 26.
Alternatively, the HX3 firmware (<10 KB), which includes config-
uration settings, can also be programmed. It is recommended to
use the Blaster Plus tool to create the HX3 firmware or configu-
ration image file. HX3’s I C slave address needs to be provided
while creating the image file. Refer to Table 6 for HX3’s I C slave
■ If bSignature “CY”, HX3 enumerates in the vendor-specific
2
mode.
2
The contents of the EEPROM can be updated with the
easy-to-use Cypress Blaster Plus tool. Blaster Plus is a
address.
Table 7. EEPROM Map
I2C Offset Bits
Name
Default
Description
0
7:0 bSignature LSB (“C”)
0x43 The first byte of the 2-byte signature initialized with “CY” ASCII
text.
When the signature is not valid, the hub enumerates as a
vendor-specific device.
1
2
7:0 bSignature MSB (“Y”)
7:6 bImageCTL
0x59 The second byte of the 2-byte signature initialized with “CY”
ASCII text. When the signature is not valid, the hub enumerates
as a vendor-specific device.
b’00
b’11
Reserved
b’01: 400 kHz
b’11: 100 kHz
2
5:4 I C Speed
3:1 bImageCTL
b’000 Reserved
0: Execution binary file
1: Data file
0
bImageCTL
0
3
4
7:0 bImageType
7:0 bD4Length
0xD4 0xD4: Load only configuration
0xB0: Load firmware boot image
All other bImageType will return an error code.
40
bD4Length is defined in bytes as the length from offset 5.
I C offset bytes 0–4 are the header bytes.
2
bD4Length = 6: Only update VID, PID, and DID
bD4Length = 18: Configuration options (no PHY trim)
bD4Length = 40: Configuration options with PHY trim options
bD4Length > 40: User must provide valid string descriptors
bD4Length > 192: Error
5
6
7
8
7:0 VID [7:0]
7:0 VID [15:8]
7:0 PID [7:0]
7:0 PID [15:8]
0xB4 Custom Vendor ID - LSB
0x04 Custom Vendor ID - MSB
0x04 Custom Product ID (PID)
Default: 0x6504
0x65
If separate PID is used for USB 2.0, the USB 2.0 PID will be read
from offset 35 and 36.
Else, USB 2.0 PID = PID+2; Default: 0x6506
Document Number: 001-73643 Rev. *R
Page 26 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Table 7. EEPROM Map (continued)
I2C Offset Bits
Name
Default
Description
9
7:0 DID [7:0]
00 -
88-pin
QFN,
10 -
Custom Device ID - revision - LSB
68-pin
QFN
10
11
12
7:0 DID [15:8]
7:0 Reserved
7:4 SHARED_LINK_EN
50
0
Custom Device ID - revision - MSB
Reserved
b’0000 Enable Shared Link on DS port
bit[7:4]=DS4, DS3, DS2, DS1
0: Shared Link not enabled
1: Shared Link enabled
3:0 SHC_ACTIVE_PORTS [3:0]
b’1111 Indicates if a SuperSpeed port is active.
bit[3:0] = DS4, DS3, DS2, DS1
0: Not active
1: Active
13
14
7:0 POWER_ON_TIME
0x32 Time (in 2-ms intervals) from the time the power-on sequence
begins on a port until power is good on that port
(bPwron2PwrGood)
b’1111 Indicates if the port is removable.
bit[7:4]=DS4, DS3, DS2, DS1
0: Non-removable
7:4 REMOVABLE_PORTS [3:0]
1: Removable
3:0 UHC_ACTIVE_PORTS [3:0]
b’1111 Indicates if a USB 2.0 port is active.
bit[3:0]=DS4, DS3, DS2, DS1
0: Not active
1: Active
15
7
SS_LED_PIN_CONTROL
0
Port 1–4: SS LED disable
0: DS[1:4]_LED_SS are LEDs. The LED glows when the SS port
is active and not in disabled state.
1: DS[1:4]_LED_SS are not LEDs
6
5
4
GREEN_LED_PIN_CONTROL
AMBER_LED_PIN_CONTROL
PORT_INDICATORS
0
0
1
Port 1–4: USB 2.0 Green LED disable
0: DS[1:4]_GREEN are LEDs
1: DS[1:4]_GREEN are not LEDs
Port 1–4: USB 2.0 Amber LED disable
0: DS[1:4]_AMBER are LEDs
1: DS[1:4]_AMBER are not LEDs
Port indicators supported
0: Port indicators are not supported on its DS-facing ports and
the USB 2.0 PORT_INDICATOR request has no effect.
1: Port indicators are supported on its DS-facing ports and the
USB 2.0 PORT_INDICATOR request controls the indicators.
3
COMPOUND_HUB
0
Identifies a compound device.
0: Hub is not part of a compound device.
1: Hub is part of a compound device.
2:1 Reserved
GANG
0
0
Reserved
0
1: Ganged power switch enable for all DS ports
0: Individual port power switch enable for each DS port
Document Number: 001-73643 Rev. *R
Page 27 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Table 7. EEPROM Map (continued)
I2C Offset Bits
Name
Default
Description
16
7
SUSPEND_INDICATOR_DISABLE
0
0: Suspend indicator enabled
1: Suspend indicator disabled
6
SS_US_DISABLE
0
0
Hub mode of operation (USB 3.0 or USB 2.0)
0: USB 3.0 hub and USB 2.0 hub enabled
1: USB 3.0 hub disabled and USB 2.0 hub enabled
Power switch control output polarity
0: Active LOW
5
PWR_EN_POLARITY
1: Active HIGH
4:0 PORT_POLARITY
b’00000 USB 2.0 DP and DM swapped
bit[4:0]=DS4, DS3, DS2, DS1, US
1: Port polarity swapped
0: Port polarity not swapped
17
7:5 Reserved
0
1
Reserved
0: BC v1.2 disabled
1: BC v1.2 enabled
4
BC_ENABLE
3
2
ACA_DOCK
APPLE_XA
0
0
If this bit is set, enable ACA-Dock on the US port
0: Max limit for Apple charging 2.1 A
1: Max limit for Apple charging 1 A
1
0
Reserved
GHOST_CHARGE_EN
0
1
Reserved
0: Ghost Charging disabled
1: Ghost Charging enabled
18
19
7:4 CDP_EN[3:0]
3:0 DCP_EN[3:0]
b’1111 Per-port charging setting
bit[7:4]=DS4, DS3, DS2, DS1
0: CDP disabled
1: CDP enabled
b’0000 Per-port charging setting
bit[3:0]=DS4, DS3, DS2, DS1
0: DCP disabled
1: DCP enabled
7
6
EMBEDDED_HUB
0
1
If this bit is set, the US is as an embedded port and VBUS
connected to VBUS_US pin is ignored.
If this bit is set, the USB 2.0 hub controller will accept both 0x00
and 0x29 as valid descriptor types. If '0', only 0x29 will be
accepted as a valid descriptor type.
ILLEGAL_DESCRIPTOR
5
4
Reserved
OC_POLARITY
1
0
Reserved
Overcurrent input polarity
0: Active LOW
1: Active HIGH
3:0 OC_TIMER
b’1000 Time in milliseconds for which the overcurrent inputs will be
filtered
20
21
7:0 Reserved
7:4 Reserved
0
0
0
Reserved
Reserved
0: String descriptor support is disabled
[16]
3
STRING_DESCRIPTOR_ENABLE
1: String descriptor support is enabled
When string descriptors are not supported, the hub controller
returns a non-zero index (compile-time programmable) for each
string which is supported, and 0x00 for each string not
supported, as indicated by this field.
2:0 Reserved
7:0 Reserved
0
0
Reserved
Reserved
22
Note
16. When the string descriptor supports LangID, Manufacturer, Product and Serial Number, the serial number must be unique for each device.
Document Number: 001-73643 Rev. *R
Page 28 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Table 7. EEPROM Map (continued)
I2C Offset Bits
Name
7:6 HS_AMPLITUDE_DS4
Default
b’00
b’00
b’00
b’00
Description
23
HS driver amplitude control; HS driver current: +0% to +7.5%
b’00: Default
b’01: +2.5%
b’10: +5%
5:4 HS_AMPLITUDE_DS3
3:2 HS_AMPLITUDE_DS2
1:0 HS_AMPLITUDE_DS2
7:6 HS_AMPLITUDE_US
5:2 HS_SLOPE
b’11: +7.5%
24
b’00
b'0100 HS driver slope control for all ports
b’0000: +15%
b’0001: +5%
b’0100: Default
b’0101: -5%
b’1111: -7.5%
1:0 HS_TX_VREF
b’10
Reference voltage for HS squelch (transmission envelope
detector) for all ports
b’00: 96 mV
b’01: 108 mV
b’10: 120 mV
b’11: 132 mV
25
26
7:3 HS_PREEMP_EN[4:0]
b’00000 HS driver pre-emphasis enable – for ports DS4, DS3, DS2, DS1,
and US
0: pre-emphasis is disabled
1: pre-emphasis is enabled
[17]
[17]
[17]
[17]
2
1
0
7
6
5
HS_PREEMP_DEPTH_DS4
HS_PREEMP_DEPTH_DS3
HS_PREEMP_DEPTH_DS2
HS_PREEMP_DEPTH_DS1
HS_PREEMP_DEPTH_US
Reserved
0
0
0
HS driver pre-emphasis depth
0: +10%
1: +20%
0
0
[17]
1
Reserved
4:1 PCS_TX_DEEMPH_DS4
0x6
USB 3.0 Tx driver de-emphasis value
0x3: -2.75 dB
0x6: -3.4 dB (Default)
0x9: -4.0 dB
0
Reserved
0
Reserved
27
28
29
7:4 PCS_TX_DEEMPH_DS3
3:0 PCS_TX_DEEMPH_DS2
7:4 PCS_TX_DEEMPH_DS1
3:0 PCS_TX_DEEMPH_US
0x6
0x6
0x6
0x6
0
USB 3.0 Tx driver de-emphasis value
0x3: -2.75 dB
0x6: -3.4 dB (Default)
0x9: -4.0 dB
7
6
Reserved
Reserved
Reserved
Reserved
1
5:0 PCS_TX_SWING_FULL_DS4
0x29 Adjust launch amplitude of the transmitter
0x1F – 0.9 V
0x29 – 1.0 V (Default)
0x35 – 1.1 V
0x3F – 1.2 V
30
7:6 Reserved
0
Reserved
5:0 PCS_TX_SWING_FULL_DS3
0x29 Adjust launch amplitude of the transmitter
0x1F – 0.9 V
0x29 – 1.0 V (Default)
0x35 – 1.1 V
0x3F – 1.2 V
Note
17. HS_PREEMP_DEPTH is valid only when corresponding HS_PREEMP_EN is set for that port.
Document Number: 001-73643 Rev. *R
Page 29 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Table 7. EEPROM Map (continued)
I2C Offset Bits
Name
Default
Description
31
32
33
7:6 Reserved
5:0 PCS_TX_SWING_FULL_DS2
0
Reserved
0x29 Adjust launch amplitude of the transmitter
0x1F – 0.9 V
0x29 – 1.0 V (Default)
0x35 – 1.1 V
0x3F – 1.2 V
Reserved
7:6 Reserved
5:0 PCS_TX_SWING_FULL_DS1
0
0x29 Adjust launch amplitude of the transmitter
0x1F – 0.9 V
0x29 – 1.0 V (Default)
0x35 – 1.1 V
0x3F – 1.2 V
Reserved
7:6 Reserved
0
5:0 PCS_TX_SWING_FULL_US
0x29 Adjust launch amplitude of the transmitter
0x1F – 0.9 V
0x29 – 1.0 V (Default)
0x35 – 1.1 V
0x3F – 1.2 V
34
35
36
37–44
45
46
7:0 Reserved
0
Reserved
7:0 UHC_PID [7:0]_LSB
7:0 UHC_PID [15:8]_MSB
7:0 Reserved
7:0 bLength: LangID
7:0 DescType
0x06 USB 2.0 PID. If bD4Length 40, USB 2.0 PID will be read from
0x65
0
4
3
this location.
Eight bytes reserved for future expansion
Size of LangID (defined by spec as N+2)
String descriptor type (constant value)
String language ID - MSB of wLangID
String language ID - MSB of wLangID
47
48
7:0 LangID - MSB
7:0 LangID - LSB
9
4
49
7:0 bLength: Manufacturer (X)
54
Manufacturer string length (“bLength: LangID + bLength:
Manufacturer + bLength: Product + bLength: Serial Number”
should be less than or equal to 152 bytes). X ≤ 66.
50
51
7:0 DescType
7:0 bString: Manufacturer
3
String descriptor type (constant value)
‘2’, 0, ‘0’, Manufacturer string: UNICODE UTF-16LE per USB 2.0 specifi-
0, ‘1’, 0, cation: “2014 Cypress Semiconductor”
‘4’, 0, ‘ ‘,
0, ‘C’, 0,
‘y’, 0, ‘p’,
0, ‘r’, 0,
‘e’, 0, ‘s’,
0, ‘s’, 0,
‘ ‘, 0, ‘S’,
0, ‘e’, 0,
‘m’, 0, ‘i’,
0, ‘c’, 0,
‘o’, 0, ‘n’,
0, ‘d’, 0,
‘u’, 0, ‘c’,
0, ‘t’, 0,
‘o’, 0, ‘r’,
0
49 + X
50 + X
7:0 bLength: Product (Y)
7:0 DescType
22
Product string length (“bLength: LangID + bLength: Manufac-
turer + bLength: Product + bLength: Serial Number” should be
less than or equal to 152 bytes). Y ≤ 66.
3
String descriptor type (constant value)
Document Number: 001-73643 Rev. *R
Page 30 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Table 7. EEPROM Map (continued)
I2C Offset Bits
Name
7:0 bString: Product
Default
Description
51 + X
‘C’, 0, Product string: UNICODE UTF-16LE per USB 2.0 specification:
‘Y’, 0, ‘-’, “CY-HX3 HUB”
0, ‘H’, 0,
‘X’, 0, ‘3’,
0, ‘ ‘, 0,
‘H’, 0,
‘U’, 0,
‘B’, 0
49 + X + Y 7:0 bLength: Serial Number (Z)
22
3
Serial number string length (“bLength: LangID + bLength:
Manufacturer + bLength: Product + bLength: Serial Number”
should be less than or equal to 152 bytes). Z ≤ 66.
50 + X + Y 7:0 DescType
String descriptor type (constant value)
51 + X + Y 7:0 bString: Serial Number
‘1’, 0, ‘2’, Serial number string: UNICODE UTF-16LE per USB 2.0 speci-
0, ‘3’, 0, fication: “123456789A”
‘4’, 0, ‘5’,
0, ‘6’, 0,
‘7’, 0, ‘8’,
0, ‘9’, 0,
‘A’, 0
EMI
ESD
HX3 meets the EMI requirements outlined by FCC 15B (USA)
and EN55022 (Europe) for consumer electronics. HX3 tolerates
EMI conducted by aggressors outlined by the above specifica-
tions and continues to function as expected.
HX3 has a built-in ESD protection on all pins. The ESD protection
level provided on these ports is 2.2 kV Human Body Model
(HBM) based on the JESD22-A114 specification.
Document Number: 001-73643 Rev. *R
Page 31 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Electrostatic discharge voltage ................................. 2200 V
Oscillator or crystal frequency ................. 26 MHz ±150 ppm
I/O voltage supply ...............................................3 V to 3.6 V
Maximum input sink current per I/O .............................. 4 mA
Storage temperature................................... –65 °C to +150 °C
Operating temperature .............................. –40 °C to +85 °C
Electrical Specifications
HX3 meets all USB-IF Electrical Compliance specifications.
DC Electrical Characteristics
Table 8. DC Electrical Characteristics
Parameter
Description
1.2 V core supply
Conditions
Min
Typ
1.2
1.2
2.6
1.2
3.3
3.3
–
Max
Units
V
DVDD12
–
1.14
1.26
Normal operation
Programming
1.14
1.26
V
VDD_EFUSE eFuse supply
2.5
2.7
V
AVDD12
VDD_IO
AVDD33
1.2 V analog supply
–
–
–
–
–
1.14
1.26
V
3.3 V I/O supply
3
3.6
V
3.3 V analog supply
Input HIGH voltage
Input LOW voltage
Output HIGH voltage
Output LOW voltage
Input sink current
3
3.6
V
V
V
V
V
0.7 × VDD_IO
VDD_IO
V
IH
0
2.4
–
–
0.3 × VDD_IO
V
IL
Output HIGH voltage at I +4 mA
–
–
0.4
4
V
OH
OL
OH
Output LOW voltage at I –4 mA
–
V
OL
I
I
I
I
LED GPIO usage
–
–
mA
OS
All I/O signals held at VDD_IO or
GND
Input leakage current
–1
–
–
–
1
µA
µA
IX
Output HI-Z leakage current
–
10
OZ
CC
1.2 V supplies combined
operating current
–
–
410
526
mA
3.3 V supplies combined
operating current
I
–
–
0.2
–
260
–
286
50
mA
V/ms
mV
CC
Voltage ramp rate on core and I/O
supplies
V
V
V
Voltage ramp must be monotonic
RAMP
N
Noise level permitted on core and Max p-p noise level permitted on all
I/O supplies supplies except AVDD
–
100
20
Noise level permitted on AVDD12 Max p-p noise level permitted USB
and AVDD33 supply supply
–
–
mV
N_USB
Document Number: 001-73643 Rev. *R
Page 32 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Power Consumption
Table 9 provides the power consumption estimates for HX3 under different conditions. Table 10 summarizes the power consumption
for various combinations of devices connected to DS ports.
For example, to calculate the HX3 power consumption for three SS devices connected to DS ports (and no device connected to one
DS port), and a US port connected to a USB 3.0 host:
Power consumption = [a] + 2*[g] = 492.5 + 2*76 = 644 mW
[a] is the active power consumption for the US port connected to a USB 3.0 host and the SS device connected to the DS port.
[g] is the incremental power consumption for an additional SS device connected to the DS port.
Table 9. Power Consumption Estimates for Various Usage Scenarios
Typical Consumption
Number and Speed of
Device Condition
Supply Current (mA)
Comments
DS Ports Connected
Power (mW)
1.2 V
12.0
204.1
51.2
51.2
218.0
51.2
51.2
39.4
7.0
3.3 V
7.1
[18]
Suspend
NA
37.8
492.5
210.7
173.7
602.9
210.7
173.7
76.0
–
1 SS
1 HS
1 FS
1 SS + 1 HS
1 HS
1 FS
SS
75.0
45.2
34.0
103.4
45.2
34.0
8.7
[a]
[b]
[c]
[d]
[e]
[f]
[19]
[19,
Active power with USB 3.0 host
Active power with USB 2.0 host
20]
[g]
[h]
[i]
Incremental active power for
additional DS port
HS
19.8
14.2
73.7
FS
7.0
55.2
Active power saving per disabled DS
port
–
10.6
9.6
44.4
[j]
[21]
Table 10. Power Consumption Under Various Configurations
Number of DS Devices
Typical Consumption
Supply Current (mA)
Configuration
Connected With Data
Transfer
Comments
Power (mW)
1.2 V
322
297
283
272
3.3 V
101
121
92
4 SS devices
720
755
644
600
[a] + 3*[g]
[d] + 2*[g]
[a] + 2*[g]
[a] + 2*[g] - [j]
USB 3.0
4-Port Hub
(USB 3.0 host)
3 SS + 1 HS devices
3 SS devices
USB 3.0
3 SS devices
83
4-Port Hub with one port disabled
(USB 3.0 host)
2 SS + 1 HS devices
247
103
634
[d] + [g] - [j]
Shared Link with eight DS ports
4 SS + 4 HS devices
4 HS devices
357
72
189
105
1052
432
[d] + 3*([g] + [h])
[e] + 3*[h]
USB 2.0
4-Port Hub
(USB 2.0 host)
3 HS + 1 FS devices
72
99
413
[e] + 2*[h] + [i]
Notes
18. US port in low-power state (SS in U3 and USB 2.0 in L2).
19. All four DS ports are enabled.
20. US SS disabled using configuration options. Refer to Table 7 on page 26 for I C configuration options.
2
21. Power saving applicable only with a USB 3.0 host. DS ports can be disabled through configuration options. Refer to Table 6 on page 25 for pin-strapping and
2
Table 7 on page 26 for I C configuration options.
Document Number: 001-73643 Rev. *R
Page 33 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Ordering Information
Table 11 lists HX3’s ordering information. The table contains only the part numbers that are currently available for order. Additional
part numbers for industrial temperature range can be made available on request. For more information, visit the Cypress website or
contact the local sales representative.
Table 11. Ordering Information
Number of
Shared Link
Ports
Serial
No.
Ghost ACA-
Charge Dock
Ordering Part Number
Number of DS Ports
Temperature
Package
1.
CYUSB3302-68LTXC
CYUSB3302-68LTXI
CYUSB3304-68LTXC
CYUSB3304-68LTXI
CYUSB3312-88LTXC
CYUSB3312-88LTXCT
CYUSB3312-88LTXI
CYUSB3312-88LTXIT
CYUSB3314-88LTXC
CYUSB3314-88LTXCT
CYUSB3314-88LTXI
CYUSB3314-88LTXIT
CYUSB3324-88LTXC
CYUSB3324-88LTXCT
CYUSB3324-88LTXI
CYUSB3324-88LTXIT
CYUSB3326-88LTXC
CYUSB3326-88LTXCT
CYUSB3326-88LTXI
CYUSB3326-88LTXIT
CYUSB3328-88LTXC
CYUSB3328-88LTXCT
CYUSB3328-88LTXI
CYUSB3328-88LTXIT
CYUSB3302-BVXC
CYUSB3302-BVXI
2 (USB 3.0)
2 (USB 3.0)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
2
2
2
4
4
4
4
0
0
0
0
0
0
0
0
0
0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
0 °C–70 °C
68-pin QFN
2.
No –40 °C–85 °C 68-pin QFN
No 0 °C–70 °C 68-pin QFN
No –40 °C–85 °C 68-pin QFN
3.
4 (USB 3.0)
4.
4 (USB 3.0)
5.
2 (USB 3.0)
No
No
0 °C–70 °C
0 °C–70 °C
88-pin QFN
88-pin QFN
6.
2 (USB 3.0)
7.
2 (USB 3.0)
No –40 °C–85 °C 88-pin QFN
No –40 °C–85 °C 88-pin QFN
8.
2 (USB 3.0)
9.
4 (USB 3.0)
No
No
0 °C–70 °C
0 °C–70 °C
88-pin QFN
88-pin QFN
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
4 (USB 3.0)
4 (USB 3.0)
No –40 °C–85 °C 88-pin QFN
No –40 °C–85 °C 88-pin QFN
4 (USB 3.0)
4 (USB 3.0)
Yes
Yes
0 °C–70 °C
0 °C–70 °C
88-pin QFN
88-pin QFN
4 (USB 3.0)
4 (USB 3.0)
Yes –40 °C–85 °C 88-pin QFN
Yes –40 °C–85 °C 88-pin QFN
4 (USB 3.0)
6 (2 USB 3.0, 2 SS, 2 USB 2.0)
6 (2 USB 3.0, 2 SS, 2 USB 2.0)
6 (2 USB 3.0, 2 SS, 2 USB 2.0)
6 (2 USB 3.0, 2 SS, 2 USB 2.0)
8 (4 SS, 4 USB 2.0)
8 (4 SS, 4 USB 2.0)
8 (4 SS, 4 USB 2.0)
8 (4 SS, 4 USB 2.0)
2 (USB 3.0)
No
No
0 °C–70 °C
0 °C–70 °C
88-pin QFN
88-pin QFN
No –40 °C–85 °C 88-pin QFN
No –40 °C–85 °C 88-pin QFN
Yes
Yes
0 °C–70 °C
0 °C–70 °C
88-pin QFN
88-pin QFN
Yes –40 °C–85 °C 88-pin QFN
Yes –40 °C–85 °C 88-pin QFN
No
No
No
0 °C–70 °C 100-ball BGA
–40-85 °C 100-ball BGA
0 °C–70 °C 100-ball BGA
2 (USB 3.0)
CYUSB3304-BVXC
CYUSB3304-BVXI
4 (USB 3.0)
4 (USB 3.0)
No –40 °C–85 °C 100-ball BGA
No 0 °C–70 °C 100-ball BGA
No –40 °C–85 °C 100-ball BGA
No 0 °C–70 °C 100-ball BGA
No –40 °C–85 °C 100-ball BGA
Yes 0 °C–70 °C 100-ball BGA
CYUSB3312-BVXC
CYUSB3312-BVXI
2 (USB 3.0)
2 (USB 3.0)
CYUSB3314-BVXC
CYUSB3314-BVXI
4 (USB 3.0)
4 (USB 3.0)
CYUSB3324-BVXC
CYUSB3324-BVXI
4 (USB 3.0)
4 (USB 3.0)
Yes –40 °C–85 °C 100-ball BGA
Document Number: 001-73643 Rev. *R
Page 34 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Table 11. Ordering Information (continued)
Number of
Shared Link
Ports
Serial
No.
Ghost ACA-
Charge Dock
Ordering Part Number
Number of DS Ports
Temperature
Package
35.
CYUSB3326-BVXC
CYUSB3326-BVXI
CYUSB3328-BVXC
CYUSB2302-68LTXI
CYUSB2304-68LTXI
6 (2 USB 3.0, 2 SS, 2 USB 2.0)
6 (2 USB 3.0, 2 SS, 2 USB 2.0)
8 (4 SS, 4 USB 2.0)
2 (USB 2.0)
2
2
4
0
0
Yes
Yes
Yes
Yes
Yes
No
No –40 °C–85 °C 100-ball BGA
Yes 0 °C–70 °C 100-ball BGA
0 °C–70 °C 100-ball BGA
36.
37.
38.
39.
No –40 °C–85 °C 68-pin QFN
No –40 °C–85 °C 68-pin QFN
4 (USB 2.0)
Ordering Code Definitions
CY USB X - XXXX
X
X
X
X
3
X
X = blank or T
blank = Tube; T = Tape and Reel
Temperature Range: X = C or I
C= Commercial; I= Industrial
Pb-free
Package Type: XXXX = 68LT or 88LT or BV
68LT = 68-pin QFN
88LT = 88-pin QFN
BV = 100-ball BGA
Number of Ports
Feature list: X = 0 or 1 or 2
0 = Basic, 1 = Intermediate, 2 = Advanced
Hub Family
USB speed: X = 3 or 2
3 = USB 3.0; 2 = USB 2.0
Marketing Code: USB
Company ID: CY = Cypress
Document Number: 001-73643 Rev. *R
Page 35 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Packaging
Table 12. Package Characteristics
Parameter
Description
Min
–40
–40
–
Typ
–
Max
85
125
–
Units
°C
T
Operating ambient temperature
Operating junction temperature
Package J (68-pin QFN)
A
T
T
T
T
T
T
T
–
°C
J
16.2
15.7
35
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
JA
JA
JA
JC
JC
JC
A
Package J (88-pin QFN)
–
–
A
Package J (100-ball BGA)
–
–
A
Package J (68-pin QFN)
–
23.8
18.9
12
–
C
Package J (88-pin QFN)
–
–
C
Package J (100-ball BGA)
–
–
C
Table 13. Solder Reflow Peak Temperature
Package
68-pin QFN
88-pin QFN
100-ball BGA
Maximum Peak Temperature
Maximum Time at Peak Temperature
30 seconds
260 °C
260 °C
260 °C
30 seconds
30 seconds
Table 14. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
68-pin QFN
88-pin QFN
100-ball BGA
MSL
MSL 3
MSL 3
MSL 3
Document Number: 001-73643 Rev. *R
Page 36 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Package Diagrams
Figure 18. 68-pin QFN (8 × 8 × 1.0 mm) LT68B 5.1 × 5.1 mm EPAD (Sawn) Package Outline
NOTES:
1. HATCH AREA IS SOLDERABLE EXPOSED PAD
2. REFERENCE JEDEC#: MO-220
001-78925 *B
3. ALL DIMENSIONS ARE IN MILLIMETERS
Figure 19. 88-pin QFN (10 × 10 × 1.0 mm) LT88B 5.3 × 5.3 EPAD (Sawn) Package Outline
001-76569 *B
Document Number: 001-73643 Rev. *R
Page 37 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Figure 20. 100-Ball BGA (6.0 × 6.0 × 1.0 mm) BZ100 Package Outline
E1
2X
0.10 C
(datum B)
A1 CORNER
E
B
A
D
10
9
8
7
6
5
4 3 2 1
7
A
A1 CORNER
6
B
C
D
E
SD
D1
F
(datum A)
G
H
J
K
eD
6
2X
0.10 C
eE
SE
TOP VIEW
BOTTOM VIEW
DETAIL A
0.10 C
A
A1
0.08 C
C
100XØb
5
SIDE VIEW
Ø0.15 M C A B
Ø0.05 M C
DETAIL A
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS
NOM.
SYMBOL
2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.
MIN.
MAX.
1.00
-
A
A1
D
-
-
-
4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
SIZE MD X ME.
0.16
6.00 BSC
6.00 BSC
4.50 BSC
4.50 BSC
10
E
D1
E1
MD
ME
N
5.
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE
PARALLEL TO DATUM C.
6.
"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
10
100
0.30
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW
"SD" OR "SE" = 0.
b
0.25
0.35
eD
eE
SD
SE
0.50 BSC
0.50 BSC
0.25 BSC
0.25 BSC
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" = eD/2 AND "SE" = eE/2.
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK
METALIZED MARK, INDENTATION OR OTHER MEANS.
7.
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER
BALLS.
9. JEDEC SPECIFICATION NO. REF. : MO-195C.
51-85209 *F
Document Number: 001-73643 Rev. *R
Page 38 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Acronyms
Reference Documents
Table 15. Acronyms Used in this Document
USB 2.0 Specification
USB 3.0 Specification
Acronym
ACA
Description
Accessory Charging Adapter
Application-Specific Standard Product
Battery Charging
Battery Charging Specification
ASSP
BC
Document Conventions
Units of Measure
CDP
Charging Downstream Port
DownStream
Table 16. Units of Measure
DS
Symbol
°C
Unit of Measure
DCP
Dedicated Charging Port
Do Not Use
degree celsius
ohm
DNU
DWG
EEPROM
Device Working Group
Gbps
KB
gigabit per second
kilobyte
Electrically Erasable Programmable Read-Only
Memory
kHz
k
kilohertz
FS
Full-Speed
kiloohm
FW
GND
GPIO
HS
FirmWare
Mbps
MHz
µA
megabit per second
megahertz
microampere
milliampere
millisecond
milliwatt
GrouND
General-Purpose Input/Output
Hi-Speed
mA
ms
ISP
I/O
In-System Programming
Input/Output
mW
ns
LS
Low-Speed
nanosecond
parts per million
volt
NC
No Connect
ppm
V
OTG
PID
POR
ROM
SCL
SDA
SS
On-The-Go
Product ID
Power-On Reset
Read-Only Memory
Serial CLock
Serial DAta
SuperSpeed
TT
Transaction Translator
UpStream
US
VID
Vendor ID
Document Number: 001-73643 Rev. *R
Page 39 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Silicon Revision History
This datasheet is applicable for the USB-IF certified (TID# 330000060) HX3 Rev. *D and Rev. *C Silicon.
Rev. *D: This Silicon revision improves the yield of HX3, and is drop-in compatible for all the part numbers. There is no need to change
the board design or layout to use the HX3 Rev. *D Silicon. Products are completely compatible with the HX3 Rev. *C Silicon.
Rev. *C: This Silicon revision fixes the errata applicable to the Rev. *A Silicon.
The following table defines the changes between Rev. *A, Rev. *C, and Rev. *D Silicon.
No.
Items
Part Numbers
Rev. *A
Rev. *C
Rev. *D
Requires firmware on
external EEPROM
No external EEPROM No external EEPROM
1
USB-IF Compliance
All
required
required
FS-only hub or host connected to
HX3 Upstream Port
2
3
All
All
Not supported
90 mW
Supported
37.8 mW
Supported
37.8 mW
Suspend Power
Method of Identification
Markings on row 3 of the HX3 package differentiate Rev. *D Silicon from Rev. *C Silicon and Rev. *A Silicon as indicated in the
example below. Cypress maintains traceability of product to wafer level, including wafer fabrication location, through the lot number
marked on the package.
HX3 REV *A SILICON
HX3 REV *C SILICON
HX3 REV *D SILICON
Document Number: 001-73643 Rev. *R
Page 40 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Document History Page
Document Title: CYUSB330x/CYUSB331x/CYUSB332x/CYUSB230x, HX3 USB 3.0 Hub
Document Number: 001-73643
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
*E
4271496
MURT
02/21/2014 Changed status from Preliminary to Final.
*F
4291210
4308926
MURT
MURT
02/25/2014 Post to external web.
*G
03/14/2014 Updated System Interfaces:
Updated Configuration Options:
Updated HX3 as I2C Slave:
Updated Table 7.
*H
4463533
MURT
08/01/2014 Updated Features:
Updated TID#.
Updated Electrical Specifications:
Updated Power Consumption:
Updated Table 9:
Updated details corresponding to suspend power.
Removed Errata.
*I
4483117
4499514
RAJM
RAJM
08/22/2014 Added Silicon Revision History.
*J
09/15/2014 Added 100-ball BGA package information in all instances across the document.
Updated Ordering Information:
Updated Table 11:
Updated part numbers.
Updated Package Diagrams:
Added spec 51-85209 Rev. *D.
*K
*L
4582512
4632890
PRJI
HBM
11/28/2014 Updated HX3 Product Options:
Updated Table 1.
Updated Pin Information:
Updated Table 4.
01/20/2015 Updated Pin Information:
Updated Figure 12.
Updated Figure 13.
Updated Table 4.
Added Packaging.
Updated Package Diagrams:
spec 51-85209 – Changed revision from *D to *E.
*M
*N
4669639
4764583
HBM
HBM
02/24/2015 No technical updates.
Completing Sunset Review.
05/13/2015 Updated Package Diagrams:
spec 001-76569 – Changed revision from *A to *B.
Updated Silicon Revision History.
Updated Method of Identification.
*O
4941772
HBM
11/25/2015 Updated HX3 Product Options:
Updated Table 1:
Included CYUSB2302-68LTXI and CYUSB2304-68LTXI part numbers related
information.
Updated Ordering Information:
Updated Table 11:
Updated part numbers.
Document Number: 001-73643 Rev. *R
Page 41 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Document History Page (continued)
Document Title: CYUSB330x/CYUSB331x/CYUSB332x/CYUSB230x, HX3 USB 3.0 Hub
Document Number: 001-73643
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
*P
5466603
HBM
10/20/2016 Updated Features:
Replaced “USB 3.0-Certified Hub, TID# 330000060” with “USB-IF Certified
Hub, TID# 330000060, 30000074”.
Updated Package Diagrams:
spec 51-85209 – Changed revision from *E to *F.
Updated to new template.
Completing Sunset Review.
*Q
*R
5725383
6045135
GNKK
HBM
05/03/2017 Updated the Cypress logo and copyright information.
01/25/2018 Updated HX3 Product Options:
Updated Table 1:
Replaced “CYUSB2302-68LTXI” with “CYUSB2302” in column heading.
Replaced “CYUSB2304-68LTXI” with “CYUSB2304” in column heading.
Updated Ordering Information:
Updated Table 11:
Updated part numbers.
Updated Ordering Code Definitions.
Updated to new template.
Document Number: 001-73643 Rev. *R
Page 42 of 43
CYUSB330x/CYUSB331x
CYUSB332x/CYUSB230x
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2011-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
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Document Number: 001-73643 Rev. *R
Revised January 25, 2018
Page 43 of 43
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