CYUSB3343-BZXI [CYPRESS]
USB Bus Controller, CMOS, PBGA121, BGA-121;
| 型号： | CYUSB3343-BZXI |
| 厂家： | 
CYPRESS |
| 描述： | USB Bus Controller, CMOS, PBGA121, BGA-121 数据传输 外围集成电路 |
| 文件： | 总26页 (文件大小：2110K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CYUSB3333
CYUSB3343
PRELIMINARY
HX3C USB Type-C Hub with PD
HX3C USB Type-C Hub with PD
Functional Description
HX3C is a family of USB 3.1 Gen 1 Type-C hub with USB Power Delivery (PD) that complies with the USB 3.1 Gen 1 specification,
and the latest Type-C and PD standards. HX3C supports SuperSpeed (SS), Hi-Speed (HS), Full-Speed (FS), and Low-Speed (LS)
on all the ports. HX3C provides a complete Type-C and USB PD port controller solution in Upstream (US) and one Downstream (DS)
port.
■ Downstream: One Type-C and 2 Type-A or 3 Type-A ports
Features
■ Integrated DFP (RP), UFP (RD) termination resistors
■ USB 3.1 Gen 1-compliant Hub Controller
■ Charging Standard support:
❐ USB Power Delivery (PD) 2.0, Battery Charging v1.2 Apple
Charging Standard
❐ All ports support SS (5 Gbps), and are backward-compatible
with HS (480 Mbps), FS (12 Mbps), and LS (1.5 Mbps)
❐ SS and USB 2.0 Link Power Management (LPM)
❐ Dedicated Hi-Speed Transaction Translators (Multi-TT)
❐ Configurable USB SS and USB 2.0 PHY.
■ PD policy engine configures power profiles dynamically
■ Ghost Charge™: Charging DS without US connection
■ Firmware upgradable over USB
■ Integrated Type-C transceiver, supporting two Type-C ports
❐ Type-C supported in two ports (1 US port and 1 DS port)
❐ Integrated transceiver (baseband PHY)
■ System-level ESD protection on CC pins: 8-kV contact, 15-kV
Air Gap IEC61000-4-2 level 4C
❐ Integrated UFP (RD), and current sources for DFP (RP)
■ Upstream: Type-C or Type-B port
■ 121-ball BGA (10 mm × 10 mm, 0.8-mm ball-pitch)
Block Diagram
UPSTREAM PORT
USB 2.0 Specific
USB 3.0 (SS) Specific
CC1_P1
TYPE-C PD
CONTROLLER
USB2.0
PHY
USB3.0
PHY
VBUS
DETECT
CC2_P1
CPU
3.3V
ROM
RAM
UPSTREAM PORT CONTROL
ROUTING
1.2V
PHY INTERFACE
I2C_SDAx
I2C_SCLx
I2C I/Fs
PLL
HUB CONTROLLER
HUB CONTROLLER
TRANSACTION
TRANSLATORS
UPSTREAM
BUFFERS
DOWNSTREAM
BUFFERS
26
MHz
REPEATER
CC1_P2
CC2_P2
ROUTING LOGIC
BUFFER AND ROUTING LOGIC
TYPE-C PD
CONTROLLER
USB 2.0 USB 3.0
USB 2.0 USB 3.0
USB 2.0
PHY
USB
BILLBOARD
PORT
CONTROL
PORT
CONTROL
USB 2.0 USB 3.0
PORT
CONTROL
PHY
PHY
PHY
PHY
PHY
PHY
PORT1
PORT2
PORT3
PORT4
Cypress Semiconductor Corporation
Document Number: 002-10462 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
• +1-408-943-2600
Revised June 17, 2016
CYUSB3333
CYUSB3343
PRELIMINARY
Contents
Architecture Overview .....................................................3
USB-PD Controller ......................................................3
SS Hub Controller .......................................................3
USB 2.0 Hub Controller ...............................................3
USB Billboard ..............................................................3
CPU .............................................................................3
Flash ............................................................................3
I2C Interfaces ..............................................................3
Port Controller .............................................................3
Applications ......................................................................4
HX3C Product Options .....................................................4
Product Features ..............................................................5
Ghost Charge in Type-A DS Port ................................5
Vendor-Command Support .........................................5
Pin Information .................................................................6
Pin Description .................................................................7
System Interfaces ...........................................................11
Upstream Port (US) ...................................................11
Downstream Ports (DS1, 2, 3, 4) ..............................11
Communication Interfaces (I2C) ................................11
Oscillator ...................................................................11
Power Control ............................................................11
Reset .........................................................................11
Configuration Mode Select ........................................11
Configuration Options ................................................12
EMI ...................................................................................17
ESD ..................................................................................17
Absolute Maximum Ratings ..........................................18
Electrical Specifications ................................................18
DC Electrical Characteristics .....................................18
Power Consumption ..................................................20
Ordering Information ......................................................21
Ordering Code Definitions .........................................21
Packaging ........................................................................22
Package Diagrams ..........................................................23
Acronyms ........................................................................24
Reference Documents ....................................................24
Document Conventions .................................................24
Units of Measure .......................................................24
Document History ...........................................................25
Sales, Solutions, and Legal Information ......................26
Worldwide Sales and Design Support .......................26
Products ....................................................................26
PSoC® Solutions ......................................................26
Cypress Developer Community .................................26
Technical Support .....................................................26
Document Number: 002-10462 Rev. *A
Page 2 of 26
CYUSB3333
CYUSB3343
PRELIMINARY
USB Billboard
Architecture Overview
HX3C has integrated USB Billboard controller. This is USB 2.0
certified Full-Speed (12 Mbps) controller, which supports native
Billboard device class driver.
The Block Diagram on page 1 shows the HX3C architecture.
HX3C consists of two independent hub controllers (SS and USB
2.0), the Cortex-M0 CPU subsystem, two USB Type-C PD
controllers, USB billboard, I2C interface, and port controller
blocks.
CPU
The Cortex-M0 CPUs in HX3C are part of the 32-bit MCU
controller, which is optimized for low-power operation with
extensive clock gating. It mostly uses 16-bit instructions and
executes a subset of the Thumb-2 instruction set. This enables
fully compatible binary upward migration of the code to higher
performance processors such as the Cortex-M3 and M4, thus
enabling upward compatibility. The Cypress implementation
includes a hardware multiplier that provides a 32-bit result in one
cycle. It includes a nested vectored interrupt controller (NVIC)
block with 32 interrupt inputs and also includes a Wakeup
Interrupt Controller (WIC). The WIC can wake the processor up
from the Deep Sleep mode, allowing power to be switched off to
the main processor when the chip is in the Deep Sleep mode.
The Cortex-M0 CPU provides a Non-Maskable Interrupt (NMI)
input, which is made available to the user when it is not in use
for system functions requested by the user.
USB-PD Controller
HX3C has two USB-PD controllers consisting of a USB Type-C
baseband transceiver and physical-layer logic. This transceiver
performs the BMC and the 4b/5b encoding and decoding
functions as well as the 1.2-V front end. These controllers
integrate the required termination resistors to identify the role of
the EZ-PD solutions on two Type-C ports of the HX3C device.
RD is used to identify a UFP in a dock or a dongle. When
configured as a DFP, integrated current sources perform the role
of RP or pull-up resistors. These current sources can be
programmed to indicate the complete range of current capacity
on VBUS defined in the Type-C spec. HX3C PD ports respond
to all USB-PD communication.
The CPUs also include a serial wire debug (SWD) interface,
which is a two-wire form of JTAG.
The USB-PD controller contains a 8-bit Successive Approxi-
mation Register (SAR) ADC for analog-to-digital conversions
(ADC). The ADC includes a 8-bit DAC and a comparator. The
DAC output forms the positive input of the comparator. The
negative input of the comparator is from a 4-input multiplexer.
The four inputs of the multiplexer are a pair of global analog
multiplex busses an internal bandgap voltage and an internal
voltage proportional to the absolute temperature. All GPIO inputs
can be connected to the global Analog Multiplex Busses through
a switch at each GPIO that can enable that GPIO to be
connected to the mux bus for ADC use. The CC1, and CC2 pins
are not available to connect to the mux busses.
Flash
HX3C has one flash module each for both USB-PD controllers
and one for Billboard; with a flash accelerator, tightly coupled to
the CPU to improve average access times from the flash block.
The flash block is designed to deliver 1 wait-state (WS) access
time at 48 MHz and with 0-WS access time at 24 MHz. The flash
accelerator delivers 85% of single-cycle SRAM access
performance on average.
2
I C Interfaces
HX3C supports two I2C interfaces, which supports I2C slave,
master and multi-master configurations. One of the I2C inter-
faces is used for configuration of the hub during boot-up. Config-
uration can be from an external I2C EEPROM or from an external
I2C master. Second I2C interface shall be used to configure
external I2C slave device from HX3C.
SS Hub Controller
This block supports the SS hub functionality based on the
USB 3.0 specification. The SS hub controller supports the
following:
■ SS link power management (U0, U1, U2, U3 states)
■ Full-duplex data transmission
Port Controller
The port controller block controls the DS port power to comply
with the BC v1.2 and USB 3.1 Gen 1 specifications. Control
signals for external power switches are implemented within the
chip. HX3C controls the external power switches at power-on to
reduce in-rush current.
USB 2.0 Hub Controller
This block supports the LS, FS, and HS hub functionalities. It
includes the repeater, frame timer, and four transaction trans-
lators.
The USB 2.0 hub controller block supports the following:
■ USB 2.0 link power management (L0, L1, L2, L3 states)
■ Suspend, resume, and remote wake-up signaling
■ Multi-TT (one TT for each DS port)
Document Number: 002-10462 Rev. *A
Page 3 of 26
CYUSB3333
CYUSB3343
PRELIMINARY
■ Retail hub boxes
■ Printers, scanners
Applications
■ Docking stations for notebook PCs and tablets
■ PC motherboards, servers
■ Set-top boxes, home gateways, routers, game consoles
■ Dongles and adapters
■ Digital TV, monitors
HX3C Product Options
Table 1. HX3C Product Options
Features
CYUSB3333 (Dongle-DRP)
CYUSB3343 (Dock-DFP)
Application
Dongles
Self-powered Docks, Monitors
Number of DS ports
3 (USB 3.0)
3 (USB 3.0)
Battery Charging on DS ports
External Power Switch Control
Number of I2C ports
Apple/BC v1.2
Apple/BC v1.2
Individual or Ganged
Individual or Ganged
2
2
Number of PD/Type-C ports
PD port-1 power role
2
2
DRP
DRP
DRP
DFP
PD port-2 power role
[1]
[1]
Termination Resistor on CC1 line of PD port-1
Termination Resistor on CC2 line of PD port-1
Termination Resistor on CC1 line of PD port-2
Termination Resistor on CC2 line of PD port-2
Billboard device
RP[1], RD
RP[1], RD
[2]
[1]
RA
RP[1], RD
[1]
[3]
RP[1], RD
Rp
[1]
[3]
RP[1], RD
Rp
Yes
Yes
Package
121-ball BGA
121-ball BGA
Temperature range
Industrial and Commercial
Industrial and Commercial
Notes
1. Termination resistor denoting the PD port as dual role port for power, power provider/consumer.
2. Termination resistor denoting the PD port as a VCONN powered accessory.
3. Termination resistor denoting the PD port as downstream facing port, power provider only.
Document Number: 002-10462 Rev. *A
Page 4 of 26
CYUSB3333
CYUSB3343
PRELIMINARY
Product Features
Figure 2. Ghost Charge Implementation in HX3C
Ghost Charge in Type-A DS Port
Ghost Charge is a Cypress-proprietary feature for charging USB
devices on the DS port when the US port is not connected to a
host. For example, in a docking station with HX3C as shown in
Figure 1, when the laptop is undocked, HX3C will emulate a
dedicated charging port (DCP) to provide charge to a phone
connected on a Type-A DS port.
HX3C DS PORT
Other
Charging
Scheme
BC v1.2
Scheme
Charging
Scheme
Detector
Figure 1. Ghost Charge
Power to Smartphone
5 V
(HX3C’s Downstream Port)
Power
Switch
USB Cable
VBUS
HX3C
Battery
Charger
Wall Charger
Detector
Notebook PC
Undocked
USB Battery-Powered Device
Ghost Charge is enabled by default and can be disabled through
configuration. Refer to Hub Configuration Options on page 12.
Charge a smartphone without docking the notebook
Vendor-Command Support
The hub supports vendor-specific requests and can also
enumerate as a vendor-specific device. The vendor-specific
request can be used to (a) bridge USB and I2C and (b) configure
HX3C. This feature can be used for the following applications:
When the US port is disconnected from the host, HX3C detects
if any of the DS ports are connected to a device requesting
charging. It determines the charging method and then switches
to the appropriate signaling based on the detected charging
specification as shown in Figure 2. The hub either emulates a
USB-compliant dedicated charging port by connecting DP and
DM (see the BC v1.2 specification) or other supported
proprietary charging schemes.
■ Firmware upgrade of an external ASSP connected to HX3C
through USB
■ In-System programming (ISP) of an EEPROM connected to
HX3C through USB
Document Number: 002-10462 Rev. *A
Page 5 of 26
CYUSB3333
CYUSB3343
PRELIMINARY
Pin Information
Figure 3. HX3C 121-ball BGA pinout for CYUSB3333/CYUSB3343
1
2
3
4
5
6
7
8
DS1_DP
9
10
11
A
B
C
D
E
F
DS4_DM
DS2_OVRCURR
US_TXM
DS4_DP
AVDD33
DS2_DM
DS2_DP
AVDD12
DS3_GREEN
AVDD12
VSS
AVDD33
DS1_DM
AVDD33
VSS
US_DM
VSS
US_DP
DVDD12
DS1_RXP
DS1_RXM
VSS
DVDD12
DS3_OVRCURR
DS3_DP
VSS
VDDIO
VSS
XTAL_IN
XTAL_OUT
VSS
DS4_OVRCURR
MODE_SEL[1]
AVDD33
DS3_DM
DS1_PWREN
DVDD12
SWDCLK_BB
XRES_BB
I2C_SCL2
I2C_SDA
AVDD12
VCCD_BB
I2C_SDA2
DS1_OVRCURR
VDDIO_BB
GPIO0
GPIO2
US_TXP
DS2_PWREN
SWDCLK
RESET_N
USB2_RESREF
MODE_SEL[0]
VBUS_US
SWDIO_BB
GPIO6
DVDD12
XRES_P1
DS4_GREEN
GPIO1
GPIO5
VSEL1_P2
US_RXM
SUSPEND
SWDIO
USB3_RESREF
VDD_EFUSE
DS4_PWREN
DVDD12
VBUS_MON_P2
DS1_TXM
DS1_TXP
US_RXP
VBUS_DISCHAR VBUS_DISCHAR
G
H
GE_P1
GE_P2
AVDD12
DS2_GREEN
VDDIO_P1
VBUS_DS
CC1_P1
CC2/VCONN1_P
1
VSEL2_P1
HOTPLUG_DET_ VBUS_MON_P1
P2
GPIO7
VBUS_P_CTRL_ VBUS_C_CTRL_
DVDD12
P1
P2
DS4_TXP
SWDIO_P1
VBUS_C_CTRL_
P1
VSEL2_P2
CC1_P2
CC2_P2
XRES_P2
VBUS_P_CTRL_
P2
DS2_RXP
J
K
L
DS4_TXM
DVDD12
VSS
AVDD12
VDDD_P1
VSS
VSEL1_P1
VCCD_P1
SWDCLK_P1
SWDIO_P2
VCCD_P2
VDDIO_P2
I2C_SCL
VSS
VSS
DS2_RXM
DS4_RXM
DS4_RXP
HOTPLUG_DET_
P1
DS2_TXP
DS2_TXM
SWDCLK_P2
Document Number: 002-10462 Rev. *A
Page 6 of 26
CYUSB3333
CYUSB3343
PRELIMINARY
Pin Description
Table 2. 121-ball BGA Pinout for CYUSB3333/CYUSB3343
Pin Name
Type
Ball #
Description
USB 3.0 Upstream Port
US_RXP
I
G1
F1
Upstream port SuperSpeed receive plus
Upstream port SuperSpeed receive minus
Upstream port SuperSpeed transmit plus
Upstream port SuperSpeed transmit minus
Upstream port USB 2.0 data plus
US_RXM
US_TXP
US_TXM
US_DP
I
O
D1
O
C1
I/O
I/O
A11
A10
US_DM
Upstream port USB 2.0 data minus
USB 3.0 Downstream Port 1
DS1_RXP
DS1_RXM
DS1_TXP
I
I
C11
D11
G11
F11
A8
Downstream port 1 SuperSpeed receive plus
Downstream port 1 SuperSpeed receive minus
Downstream port 1 SuperSpeed transmit plus
Downstream port 1 SuperSpeed transmit minus
Downstream port 1 USB 2.0 data plus
O
O
I/O
I/O
I
DS1_TXM
DS1_DP
DS1_DM
A7
Downstream port 1 USB 2.0 data minus
Downstream port 1 Active low Over current detect
Downstream port 1 Active low VBUS Power enable
USB 3.0 Downstream Port 2
DS1_OVRCURR
DS1_PWREN
E8
O
C6
DS2_RXP
I
I
J11
K11
L9
Downstream port 2 SuperSpeed receive plus
Downstream port 2 SuperSpeed receive minus
Downstream port 2 SuperSpeed transmit plus
Downstream port 2 SuperSpeed transmit minus
Downstream port 2 USB 2.0 data plus
DS2_RXM
DS2_TXP
O
O
I/O
I/O
I
DS2_TXM
L10
A5
DS2_DP
DS2_DM
A4
Downstream port 2 USB 2.0 data minus
Downstream port 2 Active low Over current detect
Downstream port 2 Active low VBUS Power enable
Downstream port 2 USB 2.0 Green LED indicator
USB 3.0 Downstream Port 3
DS2_OVRCURR
DS2_PWREN
DS2_GREEN
B1
O
O
D3
H2
DS3_DP
I/O
I/O
I
C3
C4
B3
C5
Downstream port 3 USB 2.0 data plus
This pin is NC when Billboard function is used
DS3_DM
Downstream port 3 USB 2.0 data minus
This pin is NC when Billboard function is used
DS3_OVRCURR
DS3_GREEN
Downstream port 3 Active low Over current detect
Pull-up this pin to 3.3 V when Billboard function is used
O
Downstream port3 USB 2.0 Green LED indicator
USB 3.0 Downstream Port 4
DS4_RXP
DS4_RXM
DS4_TXP
DS4_TXM
I
L3
L2
J1
K1
Downstream port 4 SuperSpeed receive plus
Downstream port 4 SuperSpeed receive minus
Downstream port 4 SuperSpeed transmit plus
Downstream port 4 SuperSpeed transmit minus
I
O
O
Document Number: 002-10462 Rev. *A
Page 7 of 26
CYUSB3333
CYUSB3343
PRELIMINARY
Table 2. 121-ball BGA Pinout for CYUSB3333/CYUSB3343 (continued)
Pin Name
Type
I/O
I/O
I
Ball #
A2
Description
Downstream port 4 USB 2.0 data plus
DS4_DP
DS4_DM
A1
Downstream port 4 USB 2.0 data minus
Downstream port 4 Active low Over current detect
Downstream port 4 Active low VBUS Power enable
Downstream port 4 USB 2.0 Green LED indicator
Precision Resistors
DS4_OVRCURR
DS4_PWREN
DS4_GREEN
C2
O
F5
O
F6
USB2_RESREF
USB3_RESREF
A
A
E4
F3
Connect pin to a precision resistor (6.04 kΩ ±1%) to generate a current reference
for USB 2.0 PHY.
Connect pin to a precision resistor (200 Ω ±1%) for SS PHY termination
impedance calibration.
PD Controller Port 1
CC1_P1
A
A
J3
USB PD port 1 connector detect/Configuration Channel 1
CC2/VCONN1_P1
H4
CYUSB3333: USB PD port 1 VCONN1 input (4.0 V to 5.5 V)
CYUSB3343: USB PD port 1 connector detect/Configuration Channel 2
VBUS_MON_P1
A
H7
VBUS monitor for PD port 1, connect PD port 1 VBUS through 100K:10K resistor
divider network
VBUS_P_CTRL_P1
VBUS_C_CTRL_P1
VBUS_DISCHARGE_P1
VSEL1_P1
I/O
I/O
I/O
I/O
I/O
I/O
H9
J5
GPIO, used for controlling provider power switch of PD port 1
GPIO, used for controlling consumer power switch of PD port 1
GPIO, used for controlling VBUS discharge switch of PD port 1
GPIO, used for selecting VBUS voltage level of PD port 1
GPIO, used for selecting VBUS voltage level of PD port 1
GPIO, used as Hot plug detect input from display port of PD port 1
PD Controller Port 2
G5
K5
H5
L6
VSEL2_P1
HOTPLUG_DET_P1
CC1_P2
A
A
A
J7
J8
USB PD port 2 connector detect/Configuration Channel 2
USB PD port 2 connector detect/Configuration Channel 2
CC2_P2
VBUS_MON_P2
G10
VBUS monitor for PD port 2, connect PD port 2 VBUS through 100K:10K resistor
divider network
VBUS_P_CTRL_P2
VBUS_C_CTRL_P2
VBUS_DISCHARGE_P2
VSEL1_P2
I/O
I/O
I/O
I/O
I/O
I/O
J10
H10
G6
G9
J6
GPIO, used for controlling provider power switch of PD port 2
GPIO, used for controlling consumer power switch of PD port 2
GPIO, used for controlling VBUS discharge switch of PD port 2
GPIO, used for selecting VBUS voltage level of PD port 2
GPIO, used for selecting VBUS voltage level of PD port 2
GPIO, used as Hot plug detect input from display port of PD port 2
Mode select, Clock and Reset
VSEL2_P2
HOTPLUG_DET_P2
H6
MODE_SEL[0]
MODE_SEL[1]
I
I
F4
D2
Hub firmware source
MODE_SEL[1:0] = 11: Internal ROM firmware
MODE_SEL[1:0] = 01: Firmware from external I2C EEPROM
MODE_SEL[1:0] = 10: Firmware from external I2C Master
MODE_SEL[1:0] = 00: Reserved, do not use this mode
XTAL_OUT
XTAL_IN
A
A
I
C9
B9
D4
E6
Crystal out
Crystal In
RESET_N
XRES_P1
Active Low reset input of hub controller
Active Low reset input of port1 PD controller
I
Document Number: 002-10462 Rev. *A
Page 8 of 26
CYUSB3333
CYUSB3343
PRELIMINARY
Table 2. 121-ball BGA Pinout for CYUSB3333/CYUSB3343 (continued)
Pin Name
XRES_P2
Type
Ball #
J9
Description
Active Low reset input of port 2 PD controller
Active Low reset input of Billboard device
I2C, Debug, and GPIOs
I
I
XRES_BB
D7
I2C_SCL
I2C_SDA
I2C_SCL2
I2C_SDA2
SWDCLK
SWDIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L8
F7
I2C Clock, connect to I2C EEPROM to download hub firmware
I2C Data, connect to I2C EEPROM to download hub firmware
GPIO, used as I2C clock for configuring DP/Flip MUX on Type-C ports
GPIO, used for I2C data for configuring DP/Flip MUX on Type-C ports
GPIO, used as SWD clock input for hub
GPIO, used as SWD data I/O for hub
GPIO, used as SWD clock input for port1 PD controller
GPIO, used as SWD data I/O for port1 PD controller
GPIO, used as SWD clock input for port2 PD controller
GPIO, used as SWD data I/O for port2 PD controller
GPIO, used as SWD clock input for Billboard device
GPIO, used as SWD data I/O for Billboard device
GPIO
E7
D8
E3
G2
K6
SWDCLK_P1
SWDIO_P1
SWDCLK_P2
SWDIO_P2
SWDCLK_BB
SWDIO_BB
GPIO0
J4
L11
K7
C7
D10
G8
E9
GPIO1
GPIO
GPIO2
C10
F9
GPIO
GPIO5
GPIO
GPIO6
E10
H8
F2
GPIO
GPIO7
GPIO
SUSPEND
Hub suspend status indicator. This pin is asserted if both the SS and USB 2.0
hubs are in the suspend state
Power Supply
VBUS_US
VBUS_DS
VDD_EFUSE
DVDD12
PWR
PWR
PWR
PWR
G4
H3
G3
This pin must be connected to VBUS from Type-B port. For Type-C port this pin
should be connected to 5 V on Type-C attach and to GND on deattach.
This pin is used to power the Apple-charging circuit. For BC v1.2 compliance
testing, connect pin to GND. For normal operation, connect pin to local 5-V supply.
1.2 V for normal operation, 2.5 V for eFuse programming. Customers should
connect this pin to 1.2 V
B2, B11, 1.2-V digital supply
D6, E1,
F10, H11,
L1
AVDD12
AVDD33
PWR B5,D5,G7, 1.2-V analog supply
H1, K3
PWR A3, A6, B7, 3.3-V analog supply
E2
VDDIO
PWR
PWR
PWR
PWR
B6
J2
3.3-V I/O supply
VDDIO_P1
VDDIO_P2
VDDIO_BB
K8
F8
Document Number: 002-10462 Rev. *A
Page 9 of 26
CYUSB3333
CYUSB3343
PRELIMINARY
Table 2. 121-ball BGA Pinout for CYUSB3333/CYUSB3343 (continued)
Pin Name
VDDD_P1
Type
Ball #
Description
PWR
K4
CYUSB3343: Connect to 3.3-V power supply
CYUSB3333: Connect to VCONN1/5-V power supply
VCCD_P1
VCCD_P2
VCCD_BB
VSS
PWR
PWR
PWR
L5
L7
C8
1.8-V regulator output of port 1 PD controller. This pin should be decoupled to
ground using a 1-μF
1.8-V regulator output of port 2 PD controller. This pin should be decoupled to
ground using a 1-μF
1.8-V regulator output of Billboard device. This pin should be decoupled to ground
using a 1-μF
PWR A9, B4, B8, Supply ground
B10, D9,
E11, E5,
K10, K2,
K9, L4
Document Number: 002-10462 Rev. *A
Page 10 of 26
CYUSB3333
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PRELIMINARY
Reset
System Interfaces
There are four reset pins for the HX3C device. These pins control
independently reset operations for Hub controller, two USBPD
controllers and Billboard section of the product. If any particular
section of the device function not required, then that section
alone can be kept in reset by asserting correspond reset pin to
LOW.
Upstream Port (US)
The HX3C US port can function in Type-C or Type-B modes. This
port includes an integrated 1.5-k pull-up resistor and termi-
nation resistors.
Downstream Ports (DS1, 2, 3, 4)
HX3C operates with two external power supplies, 3.3 V and
1.2 V. There is no power sequencing requirement between these
two supplies. However, all reset pins should be held LOW until
both these supplies become stable.
One HX3C DS port works in Type-C mode and remaining ports
work in Type-A mode. Selection of Type-C port is made by
firmware at the time of device boot-up. The DS ports integrate
15-k pull-down and termination resistors. Type-A DS ports can
be disabled or enabled, and can be set to removable or
non-removable options. BC v1.2 charging is enabled by default
on Type-A DS ports and can be disabled using the configuration
options (see Hub Configuration Options). DS3 is internally
connected to Billboard device. This port can be used for external
connection if Billboard device is disabled.
The reset pins can be tied to VDD_IO through an external
resistor and to ground (GND) through an external capacitor
(minimum 5 ms time constant), as shown in Figure 5. This
creates a clean reset signal for power-on reset (POR).
HX3C does not support internal brown-out detection. If the
system requires this feature, an external reset should be
provided on the reset pins when supplies are below their valid
operating ranges.
2
Communication Interfaces (I C)
There are two I2C interfaces. The interfaces follow the Inter-IC
Bus specification, version 3.0, with support for the standard
mode (100 kHz) and the fast mode (400 kHz) frequencies. HX3C
supports I2C in the slave and master modes. The I2C interface
supports the multi-master mode of operation. Both the SCL and
SDA signals require external pull-up resistors based on the
specification. VDD_IO for HX3C is 3.3 V and I2C pull-up resistors
shall be connected to the same supply.
Figure 5. Reset Connection
VDD_IO
10 k
RESETN
1.5 µF
Oscillator
HX3C requires an external crystal with a frequency of 26 MHz
and an accuracy of ±150 ppm in parallel resonant, fundamental
mode. The crystal drive circuit is capable of a low-power drive
level (<200 µW). The crystal connection to the XTAL_OUT and
XTAL_IN pins is shown in Figure 4.
Hub Configuration Mode Select
Configuration options are selected through the MODE_SEL pins.
After power-up, these pins are sampled by an on-chip bootloader
to determine the configuration options (see Table 3).
Figure 4. Crystal Connection
26 MHz
Table 3. Hub Boot Sequence
XTAL_IN
10 pF
XTAL_OUT
10 pF
MODE
SEL[1]
MODE
SEL[0]
Hub Configuration Modes
0
1
0
1
Reserved. Do not use this mode.
Internal ROM configuration
I2C Master, read configuration from I2C
EEPROM
I2C Slave, configure from an external I2C
Master
Power Control
0
1
1
0
The DS[1, 2 or 4]_PWREN and DS[1, 2, 3 or 4]_OVRCURR pins
interface HX3C to external power switches. These pins are used
to control power switches for DS port power and monitor
overcurrent conditions. The power switch polarity and the power
control mode can be changed using the configuration options.
Document Number: 002-10462 Rev. *A
Page 11 of 26
CYUSB3333
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The contents of the EEPROM can be updated with the
easy-to-use Cypress Blaster Plus tool. Blaster Plus is a
GUI-based tool to configure HX3C. This tool allows to do the
following:
Hub Configuration Options
The Hub can be configured by using one of the following:
■ External I2C slave such as an EEPROM
■ External I2C master
■ Download the Cypress-provided firmware from a PC via
HX3C’s US port and store it on an EEPROM connected to
HX3C’s I2C port.
I2C Configuration
When enabled for I2C configuration through the MODE_SEL
pins (See Table 3 on page 11), HX3C can be configured as an
I2C master or as an I2C slave using I2C_SCL and I2C_SDA pins.
Hub’s configuration data is a maximum of 197 bytes and Hub’s
firmware is 10 KB. Note that Hub’s firmware also includes config-
uration settings.
■ Read the configuration settings from the EEPROM. These
settings are displayed in the Blaster Plus GUI. Modify settings
as required.
■ WritebacktheupdatedsettingsontotheEEPROM. Inaddition,
an image file can be created for external use.
The Blaster Plus tool, user guide, and the Cypress-provided
firmware are available at www.cypress.com/hx3.
HX3C as I2C Master
HX3C reads configurations from an external I2C EEPROM with
sizes ranging from 16 to 64 KB using I2C_SCL and I2C_SDA
pins. An example of a supported EEPROM is 24LC128. Based
on the contents of the bSignature and bImageType fields in Table
4 on page 12, HX3C performs one of the following actions:
HX3C as I2C Slave
An external I2C master can program the configuration settings
into the Hub according to the EEPROM map in Table 4 on
page 12. Alternatively, the Hub firmware (<10 KB), which
includes configuration settings, can also be programmed. It is
recommended to use the Blaster Plus tool to create the HX3C
firmware or configuration image file. Hub’s I2C slave address
needs to be provided while creating the image file.
■ Loads custom configuration settings from the EEPROM when
bSignature is “CY” and bImageType is 0xD4.
■ LoadstheCypress-providedfirmwarefromtheEEPROMwhen
bSignatureis“CY”andbImageTypeis0xB0. Thisfirmwarealso
includes configuration settings.
■ If bSignature “CY”, the Hub enumerates in the
vendor-specific mode.
Table 4. EEPROM Map
I2C Offset
Bits
Name
Default
Description
0
7:0 bSignature LSB (“C”)
0x43
The first byte of the 2-byte signature initialized
with “CY” ASCII text.
When the signature is not valid, the hub
enumerates as a vendor-specific device.
1
2
7:0 bSignature MSB (“Y”)
0x59
The second byte of the 2-byte signature
initialized with “CY” ASCII text. When the
signature is not valid, the hub enumerates as a
vendor-specific device.
7:6 bImageCTL
5:4 I2C Speed
b’00
b’11
Reserved
b’01: 400 kHz
b’11: 100 kHz
3:1 bImageCTL
b’000
0
Reserved
0
bImageCTL
0: Execution binary file
1: Data file
3
7:0 bImageType
0xD4
0xD4: Load only configuration
0xB0: Load firmware boot image
All other bImageType will return an error code.
Document Number: 002-10462 Rev. *A
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CYUSB3333
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Table 4. EEPROM Map (continued)
I2C Offset
Bits
Name
Default
Description
4
7:0 bD4Length
40
bD4Length is defined in bytes as the length from
offset 5.
I2C offset bytes 0–4 are the header bytes.
bD4Length = 6: Only update VID, PID, and DID
bD4Length = 18: Configuration options (no
PHY trim)
bD4Length = 40: Configuration options with
PHY trim options
bD4Length > 40: User must provide valid string
descriptors
bD4Length > 192: Error
5
6
7
8
7:0 VID [7:0]
7:0 VID [15:8]
7:0 PID [7:0]
7:0 PID [15:8]
0xB4
0x04
0x04
0x65
Custom Vendor ID - LSB
Custom Vendor ID - MSB
Custom Product ID (PID)
Default: 0x6504
If separate PID is used for USB 2.0, the USB 2.0
PID will be read from offset 35 and 36.
Else, USB 2.0 PID = PID+2; Default: 0x6506
9
7:0 DID [7:0]
7:0 DID [15:8]
7:0 Reserved
7:4 Reserved
00
50
Custom Device ID - revision - LSB
Custom Device ID - revision - MSB
Reserved
10
11
12
0
b’0000
b’1111
Reserved
3:0 SHC_ACTIVE_PORTS [3:0]
Indicates if a SuperSpeed port is active.
bit[3:0] = DS4, Reserved, DS2, DS1
0: Not active
1: Active
13
14
7:0 POWER_ON_TIME
0x32
Time (in 2-ms intervals) from the time the
power-on sequence begins on a port until power
is good on that port (bPwron2PwrGood)
7:4 REMOVABLE_PORTS [3:0]
b’1011
Indicates if the port is removable.
bit[7:4] = DS4, DS3, DS2, DS1
0: Non-removable
1: Removable
3:0 UHC_ACTIVE_PORTS [3:0]
7:4 Reserved
b’1111
Indicates if a USB 2.0 port is active.
bit[3:0] = DS4, DS3, DS2, DS1
0: Not active
1: Active
15
0
1
Reserved
3
COMPOUND_HUB
Identifies a compound device.
0: Hub is not part of a compound device.
1: Hub is part of a compound device.
2:1 Reserved
GANG
0
0
Reserved
0
1: Ganged power switch enable for all DS ports
0: Individual port power switch enable for each
DS port
Document Number: 002-10462 Rev. *A
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CYUSB3333
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Table 4. EEPROM Map (continued)
I2C Offset
Bits
Name
Default
Description
16
7
SUSPEND_INDICATOR_DISABLE
0
0: Suspend indicator enabled
1: Suspend indicator disabled
6
5
SS_US_DISABLE
0
Hub mode of operation (USB 3.0 or USB 2.0)
0: USB 3.0 hub and USB 2.0 hub enabled
1: USB 3.0 hub disabled and USB 2.0 hub
enabled
PWR_EN_POLARITY
0
Power switch control output polarity
0: Active LOW
1: Active HIGH
4:0 PORT_POLARITY
b’00000
USB 2.0 DP and DM swapped
bit[4:0] = DS4, DS3, DS2, DS1, US
1: Port polarity swapped
0: Port polarity not swapped
17
7:5 Reserved
0
1
Reserved
4
BC_ENABLE
0: BC v1.2 disabled
1: BC v1.2 enabled
3
2
ACA_DOCK
APPLE_XA
0
0
If this bit is set, enable ACA-Dock on the US port
0: Max limit for Apple charging 2.1 A
1: Max limit for Apple charging 1 A
1
0
Reserved
0
1
Reserved
GHOST_CHARGE_EN
0: Ghost Charging disabled
1: Ghost Charging enabled
18
19
7:4 CDP_EN[3:0]
3:0 DCP_EN[3:0]
b’1111
Per-port charging setting
bit[7:4] = DS4, DS3, DS2, DS1
0: CDP disabled
1: CDP enabled
b’0000
Per-port charging setting
bit[3:0] = DS4, DS3, DS2, DS1
0: DCP disabled
1: DCP enabled
7
6
EMBEDDED_HUB
0
1
If this bit is set, the US is as an embedded port
and VBUS connected to VBUS_US pin is
ignored.
ILLEGAL_DESCRIPTOR
If this bit is set, the USB 2.0 hub controller will
accept both 0x00 and 0x29 as valid descriptor
types. If ‘0’, only 0x29 will be accepted as a valid
descriptor type.
5
4
Reserved
1
0
Reserved
OC_POLARITY
Overcurrent input polarity
0: Active LOW
1: Active HIGH
3:0 OC_TIMER
7:0 Reserved
b’1000
0
Time in milliseconds for which the overcurrent
inputs will be filtered
20
Reserved
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CYUSB3333
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Table 4. EEPROM Map (continued)
I2C Offset
Bits
Name
Default
Description
21
7:4 Reserved
0
0
Reserved
3
STRING_DESCRIPTOR_ENABLE[4]
0: String descriptor support is disabled
1: String descriptor support is enabled
When string descriptors are not supported, the
hub controller returns a non-zero index
(compile-time programmable) for each string
which is supported, and 0x00 for each string not
supported, as indicated by this field.
2:0 Reserved
0
0
Reserved
Reserved
22
23
7:0 Reserved
7:6 HS_AMPLITUDE_DS4
5:4 HS_AMPLITUDE_DS3
3:2 HS_AMPLITUDE_DS2
1:0 HS_AMPLITUDE_DS2
7:6 HS_AMPLITUDE_US
5:2 HS_SLOPE
b’00
b’00
b’00
b’00
b’00
b'0100
HS driver amplitude control; HS driver current:
+0% to +7.5%
b’00: Default
b’01: +2.5%
b’10: +5%
b’11: +7.5%
24
HS driver slope control for all ports
b’0000: +15%
b’0001: +5%
b’0100: Default
b’0101: -5%
b’1111: -7.5%
1:0 HS_TX_VREF
b’10
Reference voltage for HS squelch (transmission
envelope detector) for all ports
b’00: 96 mV
b’01: 108 mV
b’10: 120 mV
b’11: 132 mV
25
26
7:3 HS_PREEMP_EN[4:0]
b’00000
HS driver pre-emphasis enable – for ports DS4,
DS3, DS2, DS1, and US
0: pre-emphasis is disabled
1: pre-emphasis is enabled
2
1
0
7
6
5
HS_PREEMP_DEPTH_DS4[5]
HS_PREEMP_DEPTH_DS3[5]
HS_PREEMP_DEPTH_DS2[5]
HS_PREEMP_DEPTH_DS1[5]
HS_PREEMP_DEPTH_US[5]
Reserved
0
0
HS driver pre-emphasis depth
0: +10%
1: +20%
0
0
0
1
Reserved
4:1 PCS_TX_DEEMPH_DS4
0x6
USB 3.0 Tx driver de-emphasis value
0x3: –2.75 dB
0x6: –3.4 dB (Default)
0x9: –4.0 dB
0
Reserved
0
Reserved
Notes
4. When the string descriptor supports LangID, Manufacturer, Product and Serial Number, the serial number must be unique for each device.
5. HS_PREEMP_DEPTH is valid only when corresponding HS_PREEMP_EN is set for that port.
Document Number: 002-10462 Rev. *A
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CYUSB3333
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PRELIMINARY
Table 4. EEPROM Map (continued)
I2C Offset
Bits
Name
Default
Description
27
7:4 Reserved
0x6
0x6
0x6
0x6
0
USB 3.0 Tx driver de-emphasis value
0x3: –2.75 dB
0x6: –3.4 dB (Default)
0x9: –4.0 dB
3:0 PCS_TX_DEEMPH_DS2
7:4 PCS_TX_DEEMPH_DS1
3:0 PCS_TX_DEEMPH_US
28
29
7
6
Reserved
Reserved
Reserved
Reserved
1
5:0 PCS_TX_SWING_FULL_DS4
0x29
Adjust launch amplitude of the transmitter
0x1F - 0.9 V
0x29 - 1.0 V (Default)
0x35 - 1.1 V
0x3F - 1.2 V
30
31
7:6 Reserved
0
Reserved
Reserved
Reserved
5:0 Reserved
0x29
0
7:6 Reserved
5:0 PCS_TX_SWING_FULL_DS2
0x29
Adjust launch amplitude of the transmitter
0x1F - 0.9 V
0x29 - 1.0 V (Default)
0x35 - 1.1 V
0x3F - 1.2 V
32
33
7:6 Reserved
0
Reserved
5:0 PCS_TX_SWING_FULL_DS1
0x29
Adjust launch amplitude of the transmitter
0x1F - 0.9 V
0x29 - 1.0 V (Default)
0x35 - 1.1 V
0x3F - 1.2 V
7:6 Reserved
0
Reserved
5:0 PCS_TX_SWING_FULL_US
0x29
Adjust launch amplitude of the transmitter
0x1F - 0.9 V
0x29 - 1.0 V (Default)
0x35 - 1.1 V
0x3F - 1.2 V
34
35
7:0 Reserved
0
0x06
0x65
0
Reserved
7:0 UHC_PID [7:0]_LSB
7:0 UHC_PID [15:8]_MSB
7:0 Reserved
USB 2.0 PID. If bD4Length 40, USB 2.0 PID will
be read from this location.
36
37–44
45
Eight bytes reserved for future expansion
Size of LangID (defined by spec as N + 2)
String descriptor type (constant value)
String language ID - MSB of wLangID
String language ID - MSB of wLangID
7:0 bLength: LangID
7:0 DescType
4
46
3
47
7:0 LangID - MSB
7:0 LangID - LSB
9
48
4
49
7:0 bLength: Manufacturer (X)
54
Manufacturer string length (“bLength: LangID +
bLength: Manufacturer + bLength: Product +
bLength: Serial Number” should be less than or
equal to 152 bytes). X ≤ 66.
50
7:0 DescType
3
String descriptor type (constant value)
Document Number: 002-10462 Rev. *A
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CYUSB3333
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PRELIMINARY
Table 4. EEPROM Map (continued)
I2C Offset
Bits
Name
Default
Description
51
7:0 bString: Manufacturer
‘2’, 0, ‘0’, 0, ‘1’, 0, Manufacturer string: UNICODE UTF-16LE per
‘4’, 0, ‘ ‘, 0, ‘C’, 0, USB 2.0 specification: “2014 Cypress Semicon-
‘y’, 0, ‘p’, 0, ‘r’, 0, ductor”
‘e’, 0, ‘s’, 0, ‘s’, 0,
‘ ‘, 0, ‘S’, 0, ‘e’, 0,
‘m’, 0, ‘i’, 0, ‘c’, 0,
‘o’, 0, ‘n’, 0, ‘d’, 0,
‘u’, 0, ‘c’, 0, ‘t’, 0,
‘o’, 0, ‘r’, 0
49 + X
7:0 bLength: Product (Y)
22
Product string length (“bLength: LangID +
bLength: Manufacturer + bLength: Product +
bLength: Serial Number” should be less than or
equal to 152 bytes). Y ≤ 66.
50 + X
51 + X
7:0 DescType
3
String descriptor type (constant value)
7:0 bString: Product
‘C’, 0, ‘Y’, 0, ‘-’, 0, Product string: UNICODE UTF-16LE per USB
‘H’, 0, ‘X’, 0, ‘3’, 0, 2.0 specification: “CY-HX3 HUB”
‘ ‘, 0, ‘H’, 0, ‘U’, 0,
‘B’, 0
49 + X + Y
7:0 bLength: Serial Number (Z)
22
Serial number string length (“bLength: LangID +
bLength: Manufacturer + bLength: Product +
bLength: Serial Number” should be less than or
equal to 152 bytes). Z ≤ 66.
50 + X + Y
51 + X + Y
7:0 DescType
3
String descriptor type (constant value)
7:0 bString: Serial Number
‘1’, 0, ‘2’, 0, ‘3’, 0, Serial number string: UNICODE UTF-16LE per
‘4’, 0, ‘5’, 0, ‘6’, 0, USB 2.0 specification: “123456789A”
‘7’, 0, ‘8’, 0, ‘9’, 0,
‘A’, 0
EMI
HX3C meets the EMI requirements outlined by FCC 15B (USA) and EN55022 (Europe) for consumer electronics. HX3C tolerates EMI
conducted by aggressors outlined by the above specifications and continues to function as expected.
ESD
HX3C has a built-in ESD protection on all pins. The ESD protection level provided on these ports is 2.2 kV Human Body Model (HBM)
based on the JESD22-A114 specification.
Document Number: 002-10462 Rev. *A
Page 17 of 26
CYUSB3333
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PRELIMINARY
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Electrostatic discharge voltage ................................. 2200 V
Oscillator or crystal frequency ................. 26 MHz ±150 ppm
I/O voltage supply ...............................................3 V to 3.6 V
Maximum input sink current per I/O .............................. 4 mA
Storage temperature................................... –65 °C to +150 °C
Operating temperature .............................. –40 °C to +85 °C
Electrical Specifications
HX3C meets all USB-IF Electrical Compliance specifications.
DC Electrical Characteristics
Table 5. DC Electrical Characteristics
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
Power supply Voltage Specs
VDD_EFUSE eFuse supply
1.14
2.5
1.2
2.6
5.0
1.2
1.2
3.3
3.3
1.26
2.7
V
V
V
V
V
V
V
Normal operation
Programming
VBUS
VBUS supply voltage
4.35
1.14
1.14
3.0
5.5
–
–
–
–
–
DVDD12
AVDD12
AVDD33
VDDIO
1.2 V core supply
1.2 V analog supply
3.3 V analog supply
3.3 V I/O supply
1.26
1.26
3.6
3
3.6
VDDIO_P1
VDDIO_P2
VDDIO_BB
VDDD_P1
PD Port-1 power supply
2.7
3.0
–
–
–
5.5
5.5
–
V
V
V
UFP Applications
DFP/DRP Applications
VCCD_P1
VCCD_P2
VCCD_BB
Output voltage (for core logic)
Output voltage (for core logic)
Output voltage (for core logic)
VCONN supply voltage
1.8
Connect a 1-µF capacitor between
this pin and ground
–
–
1.8
1.8
–
–
V
V
V
Connect a 1-µF capacitor between
this pin and ground
Connect a 1-µF capacitor between
this pin and ground
VCONN1
VRAMP
4
5.0
–
5.5
50
–
Voltage ramp rate on core and I/O
supplies
0.2
V/ms Voltage ramp must be monotonic
VN
Noise level permitted on core and
I/O supplies
–
–
–
–
100
20
mV Max p-p noise level permitted on all
supplies except AVDD
VN_USB
Noise level permitted on AVDD12
and AVDD33 supply
mV Max p-p noise level permitted USB
supplies
Power supply Current Specs
ICC12 1.2 V supplies combined
–
–
320
230
420
300
mA Upstream connected to USB 3.0
Host and DS connected to Hubs
(both SS and USB 2.0 in active
state)
operating current
ICC33
3.3 V supplies combined
operating current
mA All USB ports active, PD ports and
BB device in active state
Document Number: 002-10462 Rev. *A
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Table 5. DC Electrical Characteristics (continued)
Parameter
ICCVBUS
Description
Min
Typ
Max
Units
Details/Conditions
VBUS supply operating current
–
3
5
mA Current consumed through VBUS
supply pin when USB is in Active
state
ISB12
ISB33
1.2Vsuppliescombinedsuspend
current
–
–
–
12
13
5
–
–
–
mA USB in suspend state, CPUs are in
SLEEP mode, CC I/O ON, no I/O
sourcing current
3.3Vsuppliescombinedsuspend
current
mA
ISBVBUS
VBUS supply suspend current
µA
I/O Specs
[6]
VIH
Input voltage HIGH threshold
Input voltage LOW threshold
Output voltage HIGH level
0.7 × VDDIO
–
–
–
–
V
V
V
CMOS input
CMOS input
VIL
–
0.3 × VDDIO
–
VOH
2.4
Output HIGH voltage at IOH ≤ +4
mA
VOL
IIL
Output voltage LOW level
Input leakage current
–
–
–
0.6
1
V
Output LOW voltage at IOL ≥ –4 mA
–1
µA I/O signals held at VDDIO or GND
Note
6.
V
should not exceed VDDIO + 0.2 V.
IH
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Power Consumption
Table 6 provides the power consumption estimates for HX3C under different conditions. Table 7 summarizes the power consumption
for various combinations of devices connected to DS ports.
For example, to calculate the HX3C power consumption for three SS devices connected to DS ports (and no device connected to one
DS port), and a US port connected to a USB 3.0 host:
Power consumption = [a] + (2 × [g]) = 492.5 + (2 × 76) = 644 mW
[a] is the active power consumption for the US port connected to a USB 3.0 host and the SS device connected to the DS port.
[g] is the incremental power consumption for an additional SS device connected to the DS port.
Table 6. Power Consumption Estimates for Various Usage Scenarios
Typical Consumption
Number and Speed of DS Ports
Device Condition
Suspend [7]
Supply Current (mA)
Comments
Connected
Power (mW)
1.2 V
12.0
204.0
52.0
51.0
218.0
52.0
51.0
40.0
7.0
3.3 V
13.0
75.0
46.0
34.0
104.0
46.0
34.0
9.0
–
57
492
214
173
605
214
173
78
–
Active with USB 3.0 host
upstream [8]
1 SS
1 HS
1 FS
[a]
[b]
[c]
[d]
[e]
[f]
1 SS + 1 HS
Active with USB 2.0 host
upstream [8, 9]
1 HS
1 FS
SS
HS
FS
–
Incremental active power for
every DS port connected
[g]
[h]
[i]
20.0
14.0
7.5
74
7.0
55
Active power for each PD port
–
25
[j]
Active power for Bill board
function
–
–
20.0
66
[k]
Table 7. Power Consumption Under Various Configurations
Typical Consumption
Number of DS Devices
Configuration
Supply Current (mA)
Comments
Connected With Data Transfer
Power (mW)
1.2 V
284.0
258.0
59.0
3.3 V
100.5
120.5
73.5
US connected to USB 3.0 Type-C 3 SS Type-A devices
673
707
313
732
a + (2 × g) + j
d + g + j
host
2 SS + 1 HS Type-A devices
2 HS Type-A devices
b + h + j
1 SS Type-C + 1 SS Type-A +
1 HS Type-A devices
258.0
128
d + g + (2 × j)
1 SS Type-C + 1 SS Type-A +
1 HS Type-A devices +
Billboard enumerated
265.0
162
853
d + g + i + (2 × j)
+ k
US connected to USB 2.0 Type-C 3 HS Type-A devices
66.0
66.0
93.5
95
388
393
e + (2 × h) + j
host
1 HS Type-C + 1 HS Type-A +
e + h + i + (2 × j)
1 FS Type-A devices
1 HS Type-C + 1 HS Type-A +
1 FS Type-A devices +
Billboard enumerated
80.0
149
588
e + h + (2 × i) +
(2 × j)
Notes
7. Suspend means US port SS in U3 state, USB2.0 in L2 power states, no PD activity and no I/O sourcing current.
8. All DS ports are enabled.
9. US USB 3.0 disabled.
Document Number: 002-10462 Rev. *A
Page 20 of 26
CYUSB3333
CYUSB3343
PRELIMINARY
Ordering Information
Table 8 lists HX3C’s ordering information. The table contains only the part numbers that are currently available for order. Additional
part numbers with customized configurations can be made available on request. For more information, visit the Cypress website or
contact the local sales representative.
Table 8. Ordering Information
Serial No.
Ordering Part Number
CYUSB3333-BZXI
Application
Dongles
PD Port-2 Power Roles
DRP
Type-C Ports
Package
1
US and 1 DS 121-ball BGA
US and 1 DS 121-ball BGA
2
CYUSB3343-BZXI
Self-Powered Docks, DFP
Monitors
Ordering Code Definitions
CY USB X - BZ
X
X
X
3
X
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type:
BZ = 121-ball BGA
Number of Ports
Feature list: X = 3 or 4
3 = Dongle; 4 = Dock DFP
Hub Family
USB speed: X = 3 or 2
3 = USB 3.0; 2 = USB 2.0
Marketing Code: USB
Company ID: CY = Cypress
Document Number: 002-10462 Rev. *A
Page 21 of 26
CYUSB3333
CYUSB3343
PRELIMINARY
Packaging
Table 9. Package Characteristics
Parameter
Description
Min
–40
–40
–
Typ
–
Max
85
125
–
Units
°C
TA
Operating ambient temperature
Operating junction temperature
TJ
–
°C
TJA
TJC
Package JA (121-ball BGA)
Package JC (121-ball BGA)
44.05
19.65
°C/W
°C/W
–
–
Table 10. Solder Reflow Peak Temperature
Package
Maximum Peak Temperature
260 °C
Maximum Time at Peak Temperature
121-ball BGA
30 seconds
Table 11. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
MSL
121-ball BGA
MSL 3
Document Number: 002-10462 Rev. *A
Page 22 of 26
CYUSB3333
CYUSB3343
PRELIMINARY
Package Diagram
Figure 6. 121-ball FBGA (10.0 × 10.0 × 1.20 mm (0.30 Ball Diameter)) Package Outline, 001-54471
2X
0.10 C
E1
6
E
B
(datum B)
A1 CORNER
A
11 10
9
8
7
5
4
3
2
1
7
A1 CORNER
A
B
C
D
E
F
6
SD
D1
D
(datum A)
G
H
J
K
eD
L
2X
0.10 C
6
eE
TOP VIEW
SE
BOTTOM VIEW
0.20 C
DETAIL A
A1
0.08 C
C
121XØb
5
A
Ø0.15 M C A B
Ø0.08 M C
SIDE VIEW
DETAIL A
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
DIMENSIONS
SYMBOL
2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.
MIN.
-
NOM.
MAX.
1.20
-
A
-
4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
SIZE MD X ME.
A1
D
0.15
-
10.00 BSC
E
10.00 BSC
8.00 BSC
8.00 BSC
11
D1
E1
MD
ME
N
5.
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A
PLANE PARALLEL TO DATUM C.
6.
"SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
11
121
0.30
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" OR "SE" = 0.
b
0.25
0.35
eD
eE
SD
SE
0.80 BSC
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" = eD/2 AND "SE" = eE/2.
0.80 BSC
0.00
A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK
METALIZED MARK, INDENTATION OR OTHER MEANS.
7.
0.00
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER
BALLS.
001-54471 *E
Document Number: 002-10462 Rev. *A
Page 23 of 26
CYUSB3333
CYUSB3343
PRELIMINARY
Acronyms
Reference Documents
Table 12. Acronyms Used in this Document
USB 2.0 Specification
USB 3.1 Specification
Acronym
ACA
Description
Accessory Charging Adapter
Application-Specific Standard Product
Battery Charging
Battery Charging Specification
ASSP
BC
Document Conventions
Units of Measure
CDP
Charging Downstream Port
DownStream
Table 13. Units of Measure
DS
Symbol
°C
Unit of Measure
DCP
Dedicated Charging Port
Do Not Use
degree Celsius
ohm
DNU
DWG
EEPROM
Device Working Group
Gbps
KB
gigabit per second
kilobyte
Electrically Erasable Programmable Read-Only
Memory
kHz
k
kilohertz
FBGA
FS
Fine-Pitch Ball Grid Array
Full-Speed
kiloohm
Mbps
MHz
µA
megabit per second
megahertz
microampere
milliampere
millisecond
milliwatt
FW
FirmWare
GND
GPIO
HS
GrouND
General-Purpose Input/Output
Hi-Speed
mA
ms
ISP
I/O
In-System Programming
Input/Output
mW
ns
nanosecond
parts per million
volt
LS
Low-Speed
ppm
V
NC
No Connect
OTG
PID
POR
ROM
SCL
SDA
SS
On-The-Go
Product ID
Power-On Reset
Read-Only Memory
Serial CLock
Serial DAta
SuperSpeed
TT
Transaction Translator
UpStream
US
VID
Vendor ID
Document Number: 002-10462 Rev. *A
Page 24 of 26
CYUSB3333
CYUSB3343
PRELIMINARY
Document History
Document Title: CYUSB3333/CYUSB3343, HX3C USB Type-C Hub with PD
Document Number: 002-10462
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
5147085
5312423
HBM
HBM
03/30/2016 New datasheet.
*A
06/17/2016 Corrected typo in 121-ball BGA Pinout for CYUSB3333/CYUSB3343.
Document Number: 002-10462 Rev. *A
Page 25 of 26
CYUSB3333
CYUSB3343
PRELIMINARY
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
ARM® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/powerpsoc
cypress.com/memory
cypress.com/psoc
cypress.com/psoc
Automotive
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Clocks & Buffers
Interface
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Lighting & Power Control
Memory
Technical Support
cypress.com/support
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation 2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including
any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide.
Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual
property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby
grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and
reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided
by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the
Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners..
Document Number: 002-10462 Rev. *A
Revised June 17, 2016
Page 26 of 26
Ghost Charge™ and Shared Link™ are trademarks of Cypress Semiconductor Corporation.
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