CY8C3666LTI-027T_技术文档

PSoC^®3: CY8C36 Family

Data Sheet

Programmable System-on-Chip (PSoC^®)

General Description

With its unique array of configurable blocks, PSoC^®3 is a true system level solution providing microcontroller unit (MCU), memory,

analog, and digital peripheral functions in a single chip. The CY8C36 family offers a modern method of signal acquisition, signal

processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples

(near DC voltages) to ultrasonic signals. The CY8C36 family can handle dozens of data acquisition channels and analog inputs on

every general-purpose input/output (GPIO) pin. The CY8C36 family is also a high-performance configurable digital system with some

part numbers including interfaces such as USB, multi-master inter-integrated circuit (I²C), and controller area network (CAN). In

addition to communication interfaces, the CY8C36 family has an easy to configure logic array, flexible routing to all I/O pins, and

current DAC a high-performance single cycle 8051 microprocessor core. You can easily create system-level designs using a rich

library of prebuilt components and boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C36

family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute

design changes through simple firmware updates.

67-MHz, 24-bit fixed point digital filter block (DFB) to

implement finite impulse response (FIR) and infinite impulse

response (IIR) filters

Library of standard peripherals

Features

Single cycle 8051 CPU core

DC to 67 MHz operation

Multiply and divide instructions

Flash program memory, up to 64 KB, 100,000 write cycles,

20 years retention, and multiple security features

Up to 8-KB flash error correcting code (ECC) or configuration

storage

• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs

• Serial peripheral interface (SPI), universal asynchronous

transmitter receiver (UART), I²C

• Many others available in catalog

Library of advanced peripherals

Up to 8 KB SRAM

• Cyclic redundancy check (CRC)

Up to 2 KB electrically erasable programmable

read-only memory (EEPROM), 1 M cycles, and 20 years

retention

• Pseudo random sequence (PRS) generator

• Local interconnect network (LIN) bus 2.0

• Quadrature decoder

24-channel direct memory access (DMA) with multilayer

Analog peripherals (1.71 V ≤ V_DDA≤ 5.5 V)

1.024 V ± 0.1% internal voltage reference across –40 °C to

+85 °C (14 ppm/°C)

Configurable delta-sigma ADC with 8- to12-bit resolution

• Programmable gain stage: ×0.25 to ×16

• 12-bit mode, 192-ksps, 66-dB signal to noise and distortion

ratio (SINAD), ±1-bit INL/DNL

Up to four 8-bit, 8-Msps IDACs or 1-Msps VDACs

Four comparators with 95-ns response time

Up to four uncommitted opamps with 25 mA drive capability

Up to four configurable multifunction analog blocks. Example

configurations are programmable gain amplifier (PGA),

transimpedance amplifier (TIA), mixer, and sample and hold

CapSense support

AHB^[1]bus access

• Programmable chained descriptors and priorities

• High bandwidth 32-bit transfer support

Low voltage, ultra low-power

Wide operating voltage range: 0.5 V to 5.5 V

High efficiency boost regulator from 0.5-V input through

1.8-V to 5.0-V output

0.8 mA at 3 MHz, 1.2 mA at 6 MHz, 6.6 mA at 48 MHz

Low-power modes including:

• 1-µA sleep mode with real-time clock (RTC) and

low-voltage detect (LVD) interrupt

• 200-nA hibernate mode with RAM retention

Versatile I/O system

28 to 72 I/O (62 GPIOs, eight special input/outputs (SIO), two

USBIOs^[2]

Programming, debug, and trace

JTAG (4-wire), serial wire debug (SWD) (2-wire), and single

Any GPIO to any digital or analog peripheral routability

LCD direct drive from any GPIO, up to 46 × 16 segments^[2]

CapSense^®support from any GPIO^[3]

1.2-V to 5.5-V I/O interface voltages, up to four domains

Maskable, independent interrupt request (IRQ) on any pin or

port

Schmitt-trigger transistor-transistor logic (TTL) inputs

All GPIO configurable as open drain high/low,

pull-up/pull-down, High Z, or strong output

Configurable GPIO pin state at power-on reset (POR)

25 mA sink on SIO

wire viewer (SWV) interfaces

Eight address and one data breakpoint

4-KB instruction trace buffer

Bootloader programming supportable through I²C, SPI,

UART, USB, and other interfaces

Precision, programmable clocking

3- to 62-MHz internal oscillator over full temperature and

voltage range

4- to 25-MHz crystal oscillator for crystal PPM accuracy

Internal PLL clock generation up to 67 MHz

32.768 kHz watch crystal oscillator

Low-power internal oscillator at 1, 33, and 100 kHz

Temperature and packaging

–40 °C to +85 °C degrees industrial temperature

48-pin SSOP, 48-pin QFN, 68-pin QFN, and 100-pin TQFP

package options

Digital peripherals

20 to 24 programmable logic devices (PLD) based universal

digital blocks (UDB)

Full CAN 2.0b 16-receive (Rx), 8-transmit (Tx) buffers^[2]

Full-Speed (FS) USB 2.0 12 Mbps using internal oscillator^[2]

Up to four 16-bit configurable timer, counter, and PWM blocks

Notes

1. AHB – AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus

2. This feature on select devices only. See Ordering Information on page 114 for details.

3. GPIOs with opamp outputs are not recommended for use with CapSense.

Cypress Semiconductor Corporation

Document Number: 001-53413 Rev. *L

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 20, 2011

PSoC^®3: CY8C36 Family

Data Sheet

Contents

1. Architectural Overview ..................................................... 3

2. Pinouts ............................................................................... 5

3. Pin Descriptions .............................................................. 10

8.6 LCD Direct Drive ...................................................... 56

8.7 CapSense ................................................................. 57

8.8 Temp Sensor ............................................................ 57

8.9 DAC .......................................................................... 57

8.10 Up/Down Mixer ....................................................... 58

8.11 Sample and Hold .................................................... 58

4. CPU ................................................................................... 11

4.1 8051 CPU ................................................................. 11

4.2 Addressing Modes .................................................... 11

4.3 Instruction Set .......................................................... 11

4.4 DMA and PHUB ....................................................... 15

4.5 Interrupt Controller ................................................... 17

9. Programming, Debug Interfaces, Resources ................ 59

9.1 JTAG Interface ......................................................... 59

9.2 Serial Wire Debug Interface ..................................... 61

9.3 Debug Features ........................................................ 62

9.4 Trace Features ......................................................... 62

9.5 Single Wire Viewer Interface .................................... 62

9.6 Programming Features ............................................. 62

9.7 Device Security ........................................................ 62

5. Memory ............................................................................. 20

5.1 Static RAM ............................................................... 20

5.2 Flash Program Memory ............................................ 20

5.3 Flash Security ........................................................... 20

5.4 EEPROM .................................................................. 21

5.5 Nonvolatile Latches (NVLs) ...................................... 21

5.6 External Memory Interface ....................................... 22

5.7 Memory Map ............................................................ 22

10. Development Support ................................................... 63

10.1 Documentation ....................................................... 63

10.2 Online ..................................................................... 63

10.3 Tools ....................................................................... 63

6. System Integration .......................................................... 25

6.1 Clocking System ....................................................... 25

6.2 Power System .......................................................... 28

6.3 Reset ........................................................................ 31

6.4 I/O System and Routing ........................................... 32

11. Electrical Specifications ............................................... 64

11.1 Absolute Maximum Ratings .................................... 64

11.2 Device Level Specifications .................................... 65

11.3 Power Regulators ................................................... 69

11.4 Inputs and Outputs ................................................. 73

11.5 Analog Peripherals ................................................. 80

11.6 Digital Peripherals .................................................. 97

11.7 Memory ................................................................ 101

11.8 PSoC System Resources ..................................... 107

11.9 Clocking ................................................................ 110

7. Digital Subsystem ........................................................... 38

7.1 Example Peripherals ................................................ 39

7.2 Universal Digital Block .............................................. 42

7.3 UDB Array Description ............................................. 45

7.4 DSI Routing Interface Description ............................ 45

7.5 CAN .......................................................................... 47

7.6 USB .......................................................................... 48

7.7 Timers, Counters, and PWMs .................................. 49

7.8 I²C ............................................................................ 49

7.9 Digital Filter Block ..................................................... 50

12. Ordering Information ................................................... 114

12.1 Part Numbering Conventions ............................... 115

13. Packaging ..................................................................... 116

14. Acronyms ..................................................................... 119

15. Reference Documents ................................................. 120

8. Analog Subsystem .......................................................... 50

8.1 Analog Routing ......................................................... 51

8.2 Delta-sigma ADC ...................................................... 53

8.3 Comparators ............................................................. 54

8.4 Opamps .................................................................... 55

8.5 Programmable SC/CT Blocks .................................. 55

16. Document Conventions .............................................. 121

16.1 Units of Measure .................................................. 121

17. Revision History .......................................................... 122

18. Sales, Solutions, and Legal Information ................... 126

Document Number: 001-53413 Rev. *L

Page 2 of 126

PSoC^®3: CY8C36 Family

Data Sheet

1. Architectural Overview

Introducing the CY8C36 family of ultra low-power, flash Programmable System-on-Chip (PSoC^®) devices, part of a scalable 8-bit

PSoC 3 and 32-bit PSoC 5 platform. The CY8C36 family provides configurable blocks of analog, digital, and interconnect circuitry

around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables

a high level of integration in a wide variety of consumer, industrial, and medical applications.

Figure 1-1. Simplified Block Diagram

Analog Interconnect

Digital Interconnect

Digital System

System Wide

Resources

I2C

Master/

Slave

Universal Digital Block Array (24x UDB)

CAN

2.0

8- Bit

Timer

Quadrature Decoder

16- Bit PRS

16- Bit

PWM

to 25 MHz

( Optional)

4

UDB

22 Ω

Xtal

Osc

USB

PHY

UDB

FS USB

2.0

UDB

I2C Slave

UDB

8- Bit

Timer

4x

8- Bit SPI

Logic

Timer

Counter

PWM

12- Bit SPI

UDB

IMO

Logic

32.768 KHz

( Optional)

UDB

UART

12- Bit PWM

RTC

Timer

System Bus

Program &

Debug

Memory System

CPU System

WDT

and

Wake

8051or

Cortex M3CPU

Interrupt

Controller

EEPROM

SRAM

Program

Debug

Trace

&

PHUB

DMA

FLASH

EMIF

Boundary

Scan

ILO

Clocking System

Analog System

ADC

Digital

Filter

Block

Power Management

System

LCD Direct

Drive

+

4 x

Opamp

POR and

LVD

3 per

Opamp

-

4 x SC/ CT Blocks

(TIA, PGA, Mixer etc)

Sleep

Power

Del Sig

ADC

+

4 x

CMP

-

Temperature

Sensor

1.8 V LDO

SMP

4 x DAC

CapSense

0. 5 to5.5V

(Optional)

Figure 1-1 illustrates the major components of the CY8C36

family. They are:

PSoC’s digital subsystem provides half of its unique

configurability. It connects a digital signal from any peripheral to

any pin through the digital system interconnect (DSI). It also

provides functional flexibility through an array of small, fast,

low-power UDBs. PSoC Creator provides a library of prebuilt and

tested standard digital peripherals (UART, SPI, LIN, PRS, CRC,

timer, counter, PWM, AND, OR, and so on) that are mapped to

the UDB array. You can also easily create a digital circuit using

boolean primitives by means of graphical design entry. Each

UDB contains programmable array logic (PAL)/programmable

logic device (PLD) functionality, together with a small state

machine engine to support a wide variety of peripherals.

8051 CPU subsystem

Nonvolatile subsystem

Programming, debug, and test subsystem

Inputs and outputs

Clocking

Power

Digital subsystem

Analog subsystem

Document Number: 001-53413 Rev. *L

Page 3 of 126

PSoC^®3: CY8C36 Family

Data Sheet

In addition to the flexibility of the UDB array, PSoC also provides

configurable digital blocks targeted at specific functions. For the

CY8C36 family these blocks can include four 16-bit timers,

counters, and PWM blocks; I²C slave, master, and multi-master;

FS USB; and Full CAN 2.0b.

See the “Analog Subsystem” section on page 50 of this data

sheet for more details.

PSoC’s 8051 CPU subsystem is built around a single-cycle

pipelined 8051 8-bit processor running at up to 67 MHz. The

CPU subsystem includes a programmable nested vector

interrupt controller, DMA controller, and RAM. PSoC’s nested

vector interrupt controller provides low latency by allowing the

CPU to vector directly to the first address of the interrupt service

routine, bypassing the jump instruction required by other

architectures. The DMA controller enables peripherals to

exchange data without CPU involvement. This allows the CPU

to run slower (saving power) or use those CPU cycles to improve

the performance of firmware algorithms. The single cycle 8051

CPU runs ten times faster than a standard 8051 processor. The

processor speed itself is configurable, allowing you to tune active

power consumption for specific applications.

For more details on the peripherals see the “Example

Peripherals” section on page 39 of this data sheet. For

information on UDBs, DSI, and other digital blocks, see the

“Digital Subsystem” section on page 38 of this data sheet.

PSoC’s analog subsystem is the second half of its unique

configurability. All analog performance is based on a highly

accurate absolute voltage reference with less than 0.1-percent

error over temperature and voltage. The configurable analog

subsystem includes:

Analog muxes

Comparators

Voltage references

ADC

PSoC’s nonvolatile subsystem consists of flash, byte-writeable

EEPROM, and nonvolatile configuration options. It provides up

to 64 KB of on-chip flash. The CPU can reprogram individual

blocks of flash, enabling bootloaders. You can enable an ECC

for high reliability applications. A powerful and flexible protection

model secures the user's sensitive information, allowing

DACs

DFB

selective memory block locking for read and write protection. Up

to 2 KB of byte-writeable EEPROM is available on-chip to store

application data. Additionally, selected configuration options

such as boot speed and pin drive mode are stored in nonvolatile

memory. This allows settings to activate immediately after POR.

All GPIO pins can route analog signals into and out of the device

using the internal analog bus. This allows the device to interface

up to 62 discrete analog signals. The heart of the analog

subsystem is a fast, accurate, configurable delta-sigma ADC

with these features:

The three types of PSoC I/O are extremely flexible. All I/Os have

many drive modes that are set at POR. PSoC also provides up

to four I/O voltage domains through the V_DDIOpins. Every GPIO

has analog I/O, LCD drive^[4], CapSense^[5], flexible interrupt

generation, slew rate control, and digital I/O capability. The SIOs

on PSoC allow V_OHto be set independently of V_DDIOwhen used

as outputs. When SIOs are in input mode they are high

impedance. This is true even when the device is not powered or

when the pin voltage goes above the supply voltage. This makes

the SIO ideally suited for use on an I²C bus where the PSoC may

not be powered when other devices on the bus are. The SIO pins

also have high current sink capability for applications such as

LED drives. The programmable input threshold feature of the

SIO can be used to make the SIO function as a general purpose

analog comparator. For devices with FS USB the USB physical

interface is also provided (USBIO). When not using USB these

pins may also be used for limited digital functionality and device

programming. All of the features of the PSoC I/Os are covered

in detail in the “I/O System and Routing” section on page 32 of

this data sheet.

Less than 100 µV offset

A gain error of 0.2 percent

INL less than ±1 LSB

DNL less than ±1 LSB

SINAD better than 66 dB

This converter addresses a wide variety of precision analog

applications, including some of the most demanding sensors.

The output of the ADC can optionally feed the programmable

DFB through the DMA without CPU intervention. You can

configure the DFB to perform IIR and FIR digital filters and

several user-defined custom functions. The DFB can implement

filters with up to 64 taps. It can perform a 48-bit

multiply-accumulate (MAC) operation in one clock cycle.

Four high-speed voltage or current DACs support 8-bit output

signals at an update rate of up to 8 Msps. They can be routed

out of any GPIO pin. You can create higher resolution voltage

PWM DAC outputs using the UDB array. This can be used to

create a PWM DAC of up to 10 bits, at up to 48 kHz. The digital

DACs in each UDB support PWM, PRS, or delta-sigma

algorithms with programmable widths.

The PSoC device incorporates flexible internal clock generators,

designed for high stability and factory trimmed for high accuracy.

The internal main oscillator (IMO) is the master clock base for

the system, and has 1-percent accuracy at 3 MHz. The IMO can

be configured to run from 3 MHz up to 62 MHz. Multiple clock

derivatives can be generated from the main clock frequency to

meet application needs. The device provides a PLL to generate

system clock frequencies up to 67 MHz from the IMO, external

crystal, or external reference clock. It also contains a separate,

very low-power internal low speed oscillator (ILO) for the sleep

and watchdog timers. A 32.768-kHz external watch crystal is

also supported for use in RTC applications. The clocks, together

with programmable clock dividers, provide the flexibility to

integrate most timing requirements.

In addition to the ADC, DACs, and DFB, the analog subsystem

provides multiple:

Uncommitted opamps

Configurable switched capacitor/continuous time (SC/CT)

blocks. These support:

Transimpedance amplifiers

Programmable gain amplifiers

Mixers

Other similar analog components

Document Number: 001-53413 Rev. *L

Page 4 of 126

PSoC^®3: CY8C36 Family

Data Sheet

The CY8C36 family supports a wide supply operating range from

1.71 to 5.5 V. This allows operation from regulated supplies such

as 1.8 ± 5%, 2.5 V ±10%, 3.3 V ± 10%, or 5.0 V ± 10%, or directly

from a wide range of battery types. In addition, it provides an

integrated high efficiency synchronous boost converter that can

power the device from supply voltages as low as 0.5 V. This

enables the device to be powered directly from a single battery

or solar cell. In addition, you can use the boost converter to

generate other voltages required by the device, such as a 3.3-V

supply for LCD glass drive. The boost’s output is available on the

(4-wire) or SWD (2-wire) interfaces for programming, debug, and

test. The 1-wire SWV may also be used for ‘printf’ style

debugging. By combining SWD and SWV, you can implement a

full debugging interface with just three pins. Using these

standard interfaces enables you to debug or program the PSoC

with a variety of hardware solutions from Cypress or third party

vendors. PSoC supports on-chip break points and 4-KB

instruction and data race memory for debug. Details of the

programming, test, and debugging interfaces are discussed in

the “Programming, Debug Interfaces, Resources” section on

page 59 of this data sheet.

V_BOOSTpin, allowing other devices in the application to be

powered from the PSoC.

2. Pinouts

PSoC supports a wide range of low-power modes. These include

a 200-nA hibernate mode with RAM retention and a 1-µA sleep

mode with RTC. In the second mode the optional 32.768-kHz

watch crystal runs continuously and maintains an accurate RTC.

The Vddio pin that supplies a particular set of pins is indicated

by the black lines drawn on the pinout diagrams in Figure 2-1

through Figure 2-4. Using the Vddio pins, a single PSoC can

support multiple interface voltage levels, eliminating the need for

off-chip level shifters. Each Vddio may sink up to 100 mA total to

its associated I/O pins and opamps. On the 68-pin and 100-pin

devices each set of Vddio associated pins may sink up to

100 mA. The 48-pin device may sink up to 100 mA total for all

Vddio0 plus Vddio2 associated I/O pins and 100 mA total for all

Vddio1 plus Vddio3 associated I/O pins.

Power to all major functional blocks, including the programmable

digital and analog peripherals, can be controlled independently

by firmware. This allows low-power background processing

when some peripherals are not in use. This, in turn, provides a

total device current of only 1.2 mA when the CPU is running at

6 MHz, or 0.8 mA running at 3 MHz.

The details of the PSoC power modes are covered in the “Power

System” section on page 28 of this data sheet. PSoC uses JTAG

Figure 2-1. 48-pin SSOP Part Pinout

(SIO) P12[2]

(SIO) P12[3]

1

2

3

4

5

6

7

8

9

48 Vdda

47 Vssa

46 Vcca

Lines show

Vddio to I/O

supply

(OpAmp2out, GPIO) P0[0]

(OpAmp0out, GPIO) P0[1]

(OpAmp0+, GPIO) P0[2]

(OpAmp0-/Extref0, GPIO) P0[3]

Vddio0

P15[3] (GPIO, kHz XTAL: Xi)

45

44 P15[2] (GPIO, kHz XTAL: Xo)

43 P12[1] (SIO, I2C1: SDA)

association

P12[0] (SIO, I2C1: SCL)

42

(OpAmp2+, GPIO) P0[4]

(OpAmp2-, GPIO) P0[5]

41 Vddio3

40 P15[1] (GPIO, MHz XTAL: Xi)

39 P15[0] (GPIO, MHz XTAL: Xo)

38 Vccd

(IDAC0, GPIO) P0[6] 10

(IDAC2, GPIO) P0[7] 11

Vccd 12

37 Vssd

36 Vddd

SSOP

Vssd 13

[6]

Vddd

P15[7] (USBIO, D-, SWDCK)

P15[6] (USBIO, D+, SWDIO)

14

15

35

34

[6]

(GPIO) P2[3]

(GPIO) P2[4] 16

33 P1[7] (GPIO)

Vddio2

(GPIO) P2[5]

(GPIO) P2[6]

(GPIO) P2[7]

Vssb

P1[6] (GPIO)

17

18

19

20

21

22

23

32

31

30

29

28

27

26

Vddio1

P1[5] (GPIO, nTRST)

P1[4] (GPIO, TDI)

P1[3] (GPIO, TDO, SWV)

P1[2] (GPIO, configurable XRES)

P1[1] (GPIO, TCK, SWDCK)

Ind

Vboost

Vbat 24

25 P1[0] (GPIO, TMS, SWDIO)

Notes

4. This feature on select devices only. See Ordering Information on page 114 for details.

5. GPIOs with opamp outputs are not recommended for use with CapSense.

Document Number: 001-53413 Rev. *L

Page 5 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Figure 2-2. 48-pin QFN Part Pinout^[7]

(GPIO) P2[6]

(GPIO) P2[7]

36

1

2

P0[3] (OpAmp0-/Extref0, GPIO)

35 P0[2] (OpAmp0+, GPIO)

34 P0[1] (OpAmp0out, GPIO)

33

32

31

Lines show

Vddio to I/O

supply

Vssb

3

4

5

6

Ind

Vboost

P0[0] (OpAmp2out, GPIO)

P12[3] (SIO)

P12[2] (SIO)

association

Vbat

QFN

( Top View)

(GPIO, TMS, SWDIO) P1[0]

(GPIO, TCK, SWDCK) P1[1]

30 Vdda

29

28

27

7

8

9

10

Vssa

Vcca

(GPIO, Configurable XRES) P1[2]

(GPIO, TDO, SWV) P1[3]

P15[3] (GPIO, kHz XTAL: Xi)

P15[2] (GPIO, kHz XTAL: Xo)

P12[1] (SIO, I2C1: SDA)

(GPIO, TDI) P1[4]

26

25

11

12

(GPIO, nTRST) P1[5]

Notes

6. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.

7. The center pad on the QFN package should be connected to digital ground (Vssd) for best mechanical, thermal, and electrical performance. If not connected to

ground, it should be electrically floated and not connected to any other signal.

Document Number: 001-53413 Rev. *L

Page 6 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Figure 2-3. 68-pin QFN Part Pinout^[10]

(GPIO) P2[6]

(GPIO) P2[7]

(I2C0: SCL, SIO) P12[4]

P0[3] (GPIO, OpAmp0-/Extref0)

P0[2] (GPIO, OpAmp0+)

1

2

3

4

5

6

51

50

P0[1] (GPIO, OpAmp0out)

P0[0] (GPIO, OpAmp2out)

49

48

47

Lines show Vddio

to I/O supply

association

(I2C0: SDA, SIO) P12[5]

Vssb

Ind

P12[3] (SIO)

P12[2] (SIO)

Vssd

Vdda

Vssa

46

45

Vboost

Vbat

7

8

9

44

43

42

41

QFN

(Top View)

Vssd

Vcca

10

XRES

(TMS, SWDIO, GPIO) P1[0]

(TCK, SWDCK, GPIO) P1[1]

(configurable XRES, GPIO) P1[2]

P15[3] (GPIO, kHz XTAL: Xi)

P15[2] (GPIO, kHz XTAL: Xo)

11

12

13

40

39

P12[1] (SIO, I2C1: SDA)

(TDO, SWV, GPIO) P1[3] 14

38

37

36

35

P12[0] (SIO, 12C1: SCL)

[9]

(TDI, GPIO) P1[4]

(nTRST, GPIO) P1[5]

Vddio1

15

16

17

P3[7] (GPIO, OpAmp3out)

[9]

P3[6] (GPIO, OpAmp1out)

Vddio3

Notes

8. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.

9. This feature on select devices only. See Ordering Information on page 114 for details.

10. The center pad on the QFN package should be connected to digital ground (Vssd) for best mechanical, thermal, and electrical performance. If not connected to ground,

it should be electrically floated and not connected to any other signal.

Document Number: 001-53413 Rev. *L

Page 7 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Figure 2-4. 100-pin TQFP Part Pinout

(GPIO) P2[5]

(GPIO) P2[6]

(GPIO) P2[7]

Vddio0

1

2

3

4

5

6

75

74

P0[3] (GPIO, OpAmp0-/Extref0)

P0[2] (GPIO, OpAmp0+)

73

72

71

Lines show Vddio

to I/O supply

association

(I2C0: SCL, SIO) P12[4]

(I2C0: SDA, SIO) P12[5]

(GPIO) P6[4]

P0[1] (GPIO, OpAmp0out)

P0[0] (GPIO, OpAmp2out)

P4[1] (GPIO)

P4[0] (GPIO)

P12[3] (SIO)

P12[2] (SIO)

Vssd

70

69

(GPIO) P6[5]

(GPIO) P6[6]

(GPIO) P6[7]

7

8

9

68

67

10

66

65

Vssb

Ind

Vboost

Vbat

Vdda

Vssa

11

12

13

14

15

16

17

64

63

Vcca

NC

TQFP

Vssd

XRES

(GPIO) P5[0]

(GPIO) P5[1]

62

61

60

NC

59

58

57

56

55

(GPIO) P5[2]

(GPIO) P5[3]

(TMS, SWDIO, GPIO) P1[0]

18

19

20

21

22

NC

P15[3] (GPIO, kHz XTAL: Xi)

P15[2] (GPIO, kHz XTAL: Xo)

(TCK, SWDCK, GPIO) P1[1]

(configurable XRES, GPIO) P1[2]

(TDO, SWV, GPIO) P1[3]

P12[1] (SIO, I2C1: SDA)

P12[0] (SIO, I2C1: SCL)

P3[7] (GPIO, OpAmp3out)

54

53

23

[12]

52

51

(TDI, GPIO) P1[4]

(nTRST, GPIO) P1[5]

24

25

P3[6] (GPIO, OpAmp1out)

Figure 2-5 and Figure 2-6 on page 10 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal

analog performance on a two-layer board.

The two pins labeled Vddd must be connected together.

The two pins labeled Vccd must be connected together, with capacitance added, as shown in Figure 2-5 and Power System on

page 28. The trace between the two Vccd pins should be as short as possible.

The two pins labeled Vssd must be connected together.

For information on circuit board layout issues for mixed signals, refer to the application note AN57821 - Mixed Signal Circuit Board

Layout Considerations for PSoC® 3 and PSoC 5.

Notes

11. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.

12. This feature on select devices only. See Ordering Information on page 114 for details.

13. The center pad on the QFN package should be connected to digital ground (Vssd) for best mechanical, thermal, and electrical performance. If not connected to ground,

it should be electrically floated and not connected to any other signal.

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PSoC^®3: CY8C36 Family

Data Sheet

Figure 2-5. Example Schematic for 100-pin TQFP Part With Power Connections

Vddd

C1

1 uF

C2

0.1 uF

Vddd

Vccd

C6

0.1 uF

Vssd

U2

CY8C55xx

Vssd

Vdda

Vddd

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

P2[5]

P2[6]

P2[7]

P12[4], SIO

P12[5], SIO

P6[4]

P6[5]

P6[6]

P6[7]

Vssb

Ind

Vboost

Vbat

Vssd

XRES

P5[0]

P5[1]

P5[2]

P5[3]

P1[0], SWIO, TMS

P1[1], SWDIO, TCK

P1[2]

P1[3], SWV, TDO

P1[4], TDI

P1[5], nTRST

Vddio0

OA0-, REF0, P0[3]

C8

0.1 uF

C17

1 uF

OA0+, P0[2]

OA0out, P0[1]

OA2out, P0[0]

P4[1]

Vssd

P4[0]

Vssa

Vdda

SIO, P12[3]

SIO, P12[2]

Vssd

Vdda

Vssa

Vcca

Vdda

Vssa

Vcca

NC

Vssd

C9

1 uF

C10

0.1 uF

NC

Vssa

kHzXin, P15[3]

kHzXout, P15[2]

SIO, P12[1]

SIO, P12[0]

OA3out, P3[7]

OA1out, P3[6]

Vddd

C11

0.1 uF

C12

0.1 uF

C13

10 uF, 6.3 V 0.1 uF Vssd

C14

C15

1 uF

Vssd

C16

0.1 uF

Vssa

Vssd

Note The two Vccd pins must be connected together with as short a trace as possible. A trace under the device is recommended, as

shown in Figure 2-6 on page 10.

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PSoC^®3: CY8C36 Family

Data Sheet

Figure 2-6. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance

Vssa

Vssd

Vdda

Vddd

Vssa

Plane

Vssd

Plane

SIO. Special I/O provides interfaces to the CPU, digital

peripherals and interrupts with a programmable high threshold

voltage, analog comparator, high sink current, and high

impedance state when the device is unpowered.

3. Pin Descriptions

IDAC0, IDAC1, IDAC2, IDAC3. Low resistance output pin for

high current DACs (IDAC).

OpAmp0out, OpAmp1out^[15], OpAmp2out, OpAmp3out^[15]

High current output of uncommitted opamp.^[14]

.

SWDCK. Serial wire debug clock programming and debug port

connection.

SWDIO. Serial wire debug input and output programming and

debug port connection.

Extref0, Extref1. External reference input to the analog system.

OpAmp0–, OpAmp1–^[15], OpAmp2–, OpAmp3–^[15]. Inverting

SWV. Single wire viewer debug output.

input to uncommitted opamp.

TCK. JTAG test clock programming and debug port connection.

TDI. JTAG test data in programming and debug port connection.

OpAmp0+, OpAmp1+^[15], OpAmp2+, OpAmp3+^[15]

.

Noninverting input to uncommitted opamp.

TDO. JTAG test data out programming and debug port

connection.

GPIO. General purpose I/O pin provides interfaces to the CPU,

digital peripherals, analog peripherals, interrupts, LCD segment

drive, and CapSense.^[14]

TMS. JTAG test mode select programming and debug port

connection.

I2C0: SCL, I2C1: SCL. I²C SCL line providing wake from sleep

on an address match. Any I/O pin can be used for I²C SCL if

wake from sleep is not required.

USBIO, D+. Provides D+ connection directly to a USB 2.0 bus.

May be used as a digital I/O pin. Pins are Do Not Use (DNU) on

devices without USB.

I2C0: SDA, I2C1: SDA. I²C SDA line providing wake from sleep

on an address match. Any I/O pin can be used for I²C SDA if

wake from sleep is not required.

USBIO, D–. Provides D– connection directly to a USB 2.0 bus.

May be used as a digital I/O pin. Pins are Do Not Use (DNU) on

devices without USB.

Ind. Inductor connection to boost pump.

Vboost. Power sense connection to boost pump.

Vbat. Battery supply to boost pump.

kHz XTAL: Xo, kHz XTAL: Xi. 32.768 kHz crystal oscillator pin.

MHz XTAL: Xo, MHz XTAL: Xi. 4 to 25 MHz crystal oscillator pin.

Vcca. Output of analog core regulator and input to analog core.

Requires a 1-µF capacitor to Vssa. Regulator output not for

external use.

nTRST. Optional JTAG Test Reset programming and debug port

connection to reset the JTAG connection.

Notes

14. GPIOs with opamp outputs are not recommended for use with CapSense.

15. This feature on select devices only. See Ordering Information on page 114 for details.

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Page 10 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Vccd. Output of digital core regulator and input to digital core.

The two Vccd pins must be shorted together, with the trace

between them as short as possible, and a 1-µF capacitor to

Vssd; see Power System on page 28. Regulator output not for

external use.

4.2 Addressing Modes

The following addressing modes are supported by the 8051:

Direct addressing: The operand is specified by a direct 8-bit

address field. Only the internal RAM and the SFRs can be

accessed using this mode.

Vdda. Supply for all analog peripherals and analog core

regulator. Vdda must be the highest voltage present on the

device. All other supply pins must be less than or equal to

Vdda.

Indirectaddressing:Theinstructionspecifiestheregisterwhich

contains the address of the operand. The registers R0 or R1

are used to specify the 8-bit address, while the data pointer

(DPTR) register is used to specify the 16-bit address.

Vddd. Supply for all digital peripherals and digital core regulator.

V_DDDmust be less than or equal to Vdda.

Register addressing: Certain instructions access one of the

registers (R0 to R7) in the specified register bank. These

instructions are more efficient because there is no need for an

address field.

Vssa. Ground for all analog peripherals.

Vssb. Ground connection for boost pump.

Vssd. Ground for all digital logic and I/O pins.

Register specific instructions: Some instructions are specific to

certain registers. For example, some instructions always act

on the accumulator. In this case, there is no need to specify the

operand.

Vddio0, Vddio1, Vddio2, Vddio3. Supply for I/O pins. See

pinouts for specific I/O pin to Vddio mapping. Each Vddio must

be tied to a valid operating voltage (1.71 V to 5.5 V), and must

be less than or equal to Vdda. If the I/O pins associated with

Vddio0, Vddio2 or Vddio3 are not used then that Vddio should

be tied to ground (Vssd or Vssa).

Immediate constants: Some instructions carry the value of the

constants directly instead of an address.

Indexed addressing: This type of addressing can be used only

for a read of the program memory. This mode uses the Data

Pointer as the base and the accumulator value as an offset to

read a program memory.

XRES (and configurable XRES). External reset pin. Active low

with internal pull-up. Pin P1[2] may be configured to be a XRES

pin; see “Nonvolatile Latches (NVLs)” on page 21.

Bit addressing: In this mode, the operand is one of 256 bits.

4. CPU

4.3 Instruction Set

4.1 8051 CPU

The 8051 instruction set is highly optimized for 8-bit handling and

Boolean operations. The types of instructions supported include:

The CY8C36 devices use a single cycle 8051 CPU, which is fully

compatible with the original MCS-51 instruction set. The

CY8C36 family uses a pipelined RISC architecture, which

executes most instructions in 1 to 2 cycles to provide peak

performance of up to 33 MIPS with an average of 2 cycles per

instruction. The single cycle 8051 CPU runs ten times faster than

a standard 8051 processor.

Arithmetic instructions

Logical instructions

Data transfer instructions

Boolean instructions

The 8051 CPU subsystem includes these features:

Program branching instructions

Single cycle 8051 CPU

4.3.1 Instruction Set Summary

4.3.1.1 Arithmetic Instructions

Up to 64 KB of flash memory, up to 2 KB of EEPROM, and up

to 8 KB of SRAM

Arithmetic instructions support the direct, indirect, register,

immediate constant, and register-specific instructions.

Arithmetic modes are used for addition, subtraction,

Programmable nested vector interrupt controller

DMA controller

multiplication, division, increment, and decrement operations.

Table 4-1 on page 12 lists the different arithmetic instructions.

Peripheral HUB (PHUB)

External memory interface (EMIF)

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PSoC^®3: CY8C36 Family

Data Sheet

Table 4-1. Arithmetic Instructions

Mnemonic

Description

Bytes

Cycles

ADD A,Rn

Add register to accumulator

Add direct byte to accumulator

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

3

1

2

3

1

2

6

3

ADD A,Direct

ADD A,@Ri

ADD A,#data

ADDC A,Rn

Add indirect RAM to accumulator

Add immediate data to accumulator

Add register to accumulator with carry

Add direct byte to accumulator with carry

Add indirect RAM to accumulator with carry

Add immediate data to accumulator with carry

Subtract register from accumulator with borrow

Subtract direct byte from accumulator with borrow

Subtract indirect RAM from accumulator with borrow

Subtract immediate data from accumulator with borrow

Increment accumulator

ADDC A,Direct

ADDC A,@Ri

ADDC A,#data

SUBB A,Rn

SUBB A,Direct

SUBB A,@Ri

SUBB A,#data

INC

A

INC Rn

Increment register

INC Direct

INC @Ri

Increment direct byte

Increment indirect RAM

DEC

A

Decrement accumulator

DEC Rn

DEC Direct

DEC @Ri

INC DPTR

MUL

Decrement register

Decrement direct byte

Decrement indirect RAM

Increment data pointer

Multiply accumulator and B

DIV

Divide accumulator by B

DAA

Decimal adjust accumulator

4.3.1.2 Logical Instructions

The logical instructions perform Boolean operations such as AND, OR, XOR on bytes, rotate of accumulator contents, and swap of

nibbles in an accumulator. The Boolean operations on the bytes are performed on the bit-by-bit basis. Table 4-2 on page 12 shows

the list of logical instructions and their description.

Table 4-2. Logical Instructions

Mnemonic

ANL A,Rn

Description

AND register to accumulator

Bytes

Cycles

1

2

1

2

3

1

2

1

2

3

1

2

ANL A,Direct

ANL A,@Ri

AND direct byte to accumulator

AND indirect RAM to accumulator

AND immediate data to accumulator

AND accumulator to direct byte

AND immediate data to direct byte

OR register to accumulator

ANL A,#data

ANL Direct, A

ANL Direct, #data

ORL A,Rn

ORL A,Direct

ORL A,@Ri

OR direct byte to accumulator

OR indirect RAM to accumulator

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PSoC^®3: CY8C36 Family

Data Sheet

Table 4-2. Logical Instructions (continued)

Mnemonic

Description

OR immediate data to accumulator

OR accumulator to direct byte

Bytes

Cycles

ORL A,#data

ORL Direct, A

ORL Direct, #data

XRL A,Rn

2

3

1

2

1

2

3

1

2

3

1

2

3

1

OR immediate data to direct byte

XOR register to accumulator

XOR direct byte to accumulator

XOR indirect RAM to accumulator

XOR immediate data to accumulator

XOR accumulator to direct byte

XOR immediate data to direct byte

Clear accumulator

XRL A,Direct

XRL A,@Ri

XRL A,#data

XRL Direct, A

XRL Direct, #data

CLR

CPL

RL

A

Complement accumulator

Rotate accumulator left

RLC

RR

Rotate accumulator left through carry

Rotate accumulator right

RRC A

SWAP A

Rotate accumulator right though carry

Swap nibbles within accumulator

4.3.1.3 Data Transfer Instructions

4.3.1.4 Boolean Instructions

The data transfer instructions are of three types: the core RAM,

xdata RAM, and the lookup tables. The core RAM transfer

includes transfer between any two core RAM locations or SFRs.

These instructions can use direct, indirect, register, and

immediate addressing. The xdata RAM transfer includes only the

transfer between the accumulator and the xdata RAM location.

It can use only indirect addressing. The lookup tables involve

nothing but the read of program memory using the Indexed

addressing mode. Table 4-3 lists the various data transfer

instructions available.

The 8051 core has a separate bit-addressable memory location.

It has 128 bits of bit addressable RAM and a set of SFRs that are

bit addressable. The instruction set includes the whole menu of

bit operations such as move, set, clear, toggle, OR, and AND

instructions and the conditional jump instructions. Table 4-4 on

page 14 lists the available Boolean instructions.

Table 4-3. Data Transfer Instructions

Mnemonic

MOV A,Rn

Description

Bytes

Cycles

Move register to accumulator

Move direct byte to accumulator

Move indirect RAM to accumulator

Move immediate data to accumulator

Move accumulator to register

Move direct byte to register

1

2

1

2

1

2

3

2

3

1

2

1

3

2

3

2

MOV A,Direct

MOV A,@Ri

MOV A,#data

MOV Rn,A

MOV Rn,Direct

MOV Rn, #data

MOV Direct, A

MOV Direct, Rn

MOV Direct, Direct

MOV Direct, @Ri

MOV Direct, #data

MOV @Ri, A

Move immediate data to register

Move accumulator to direct byte

Move register to direct byte

Move direct byte to direct byte

Move indirect RAM to direct byte

Move immediate data to direct byte

Move accumulator to indirect RAM

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PSoC^®3: CY8C36 Family

Data Sheet

Table 4-3. Data Transfer Instructions (continued)

Mnemonic

Description

Bytes

Cycles

MOV @Ri, Direct

MOV @Ri, #data

MOV DPTR, #data16

MOVC A, @A+DPTR

MOVC A, @A + PC

MOVX A,@Ri

Move direct byte to indirect RAM

2

3

1

2

1

2

1

3

2

3

5

4

3

5

4

3

2

3

Move immediate data to indirect RAM

Load data pointer with 16 bit constant

Move code byte relative to DPTR to accumulator

Move code byte relative to PC to accumulator

Move external RAM (8-bit) to accumulator

Move external RAM (16-bit) to accumulator

Move accumulator to external RAM (8-bit)

Move accumulator to external RAM (16-bit)

Push direct byte onto stack

MOVX A, @DPTR

MOVX @Ri, A

MOVX @DPTR, A

PUSH Direct

POP Direct

Pop direct byte from stack

XCH A, Rn

Exchange register with accumulator

XCH A, Direct

XCH A, @Ri

Exchange direct byte with accumulator

Exchange indirect RAM with accumulator

Exchange low order indirect digit RAM with accumulator

XCHD A, @Ri

Table 4-4. Boolean Instructions

Mnemonic

Description

Bytes

Cycles

CLR

C

Clear carry

1

2

1

2

1

2

3

1

3

1

3

1

3

2

3

5

CLR bit

SETB C

SETB bit

Clear direct bit

Set carry

Set direct bit

CPL

C

Complement carry

Complement direct bit

AND direct bit to carry

CPL bit

ANL C, bit

ANL C, /bit

ORL C, bit

ORL C, /bit

MOV C, bit

MOV bit, C

AND complement of direct bit to carry

OR direct bit to carry

OR complement of direct bit to carry

Move direct bit to carry

Move carry to direct bit

JC

rel

Jump if carry is set

JNC rel

Jump if no carry is set

JB

bit, rel

Jump if direct bit is set

JNB bit, rel

JBC bit, rel

Jump if direct bit is not set

Jump if direct bit is set and clear bit

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Data Sheet

4.3.1.5 Program Branching Instructions

The 8051 supports a set of conditional and unconditional jump instructions that help to modify the program execution flow. Table 4-5

shows the list of jump instructions.

Table 4-5. Jump Instructions

Mnemonic

ACALL addr11

Description

Bytes

Cycles

Absolute subroutine call

Long subroutine call

Return from subroutine

Return from interrupt

Absolute jump

2

3

1

2

3

2

1

2

3

2

3

1

4

3

4

3

5

4

5

4

5

4

5

1

LCALL addr16

RET

RETI

AJMP addr11

LJMP addr16

SJMP rel

Long jump

Short jump (relative address)

JMP @A + DPTR

JZ rel

Jump indirect relative to DPTR

Jump if accumulator is zero

JNZ rel

Jump if accumulator is nonzero

CJNE A,Direct, rel

CJNE A, #data, rel

CJNE Rn, #data, rel

CJNE @Ri, #data, rel

DJNZ Rn,rel

DJNZ Direct, rel

NOP

Compare direct byte to accumulator and jump if not equal

Compare immediate data to accumulator and jump if not equal

Compare immediate data to register and jump if not equal

Compare immediate data to indirect RAM and jump if not equal

Decrement register and jump if not zero

Decrement direct byte and jump if not zero

No operation

Simultaneous CPU and DMA access to peripherals located on

different spokes

4.4 DMA and PHUB

The PHUB and the DMA controller are responsible for data

transfer between the CPU and peripherals, and also data

transfers between peripherals. The PHUB and DMA also control

device configuration during boot. The PHUB consists of:

Simultaneous DMA source and destination burst transactions

on different spokes

Supports 8-, 16-, 24-, and 32-bit addressing and data

Table 4-6. PHUB Spokes and Peripherals

A central hub that includes the DMA controller, arbiter, and

router

PHUB Spokes

Peripherals

Multiple spokes that radiate outward from the hub to most

peripherals

0

1

2

SRAM

IOs, PICU, EMIF

There are two PHUB masters: the CPU and the DMA controller.

Both masters may initiate transactions on the bus. The DMA

channels can handle peripheral communication without CPU

intervention. The arbiter in the central hub determines which

DMA channel is the highest priority if there are multiple requests.

PHUB local configuration, Power manager,

Clocks, IC, SWV, EEPROM, Flash

programming interface

3

4

5

6

7

Analog interface and trim, Decimator

USB, CAN, I²C, Timers, Counters, and PWMs

4.4.1 PHUB Features

DFB

CPU and DMA controller are both bus masters to the PHUB

UDBs group 1

UDBs group 2

Eight Multi-layer AHB Bus parallel access paths (spokes) for

peripheral access

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Data Sheet

4.4.2 DMA Features

Table 4-7. Priority Levels

24 DMA channels

Priority Level

% Bus Bandwidth

Each channel has one or more transaction descriptors (TD) to

configure channel behavior. Up to 128 total TDs can be defined

0

1

2

3

4

5

6

7

100.0

50.0

25.0

12.5

6.2

TDs can be dynamically updated

Eight levels of priority per channel

Anydigitallyroutablesignal, theCPU, oranotherDMAchannel,

can trigger a transaction

Each channel can generate up to two interrupts per transfer

Transactions can be stalled or canceled

3.1

1.5

Supports transaction size of infinite or 1 to 64 KB

TDs may be nested and/or chained for complex transactions

When the fairness algorithm is disabled, DMA access is granted

based solely on the priority level; no bus bandwidth guarantees

are made.

4.4.3 Priority Levels

The CPU always has higher priority than the DMA controller

when their accesses require the same bus resources. Due to the

system architecture, the CPU can never starve the DMA. DMA

channels of higher priority (lower priority number) may interrupt

current DMA transfers. In the case of an interrupt, the current

transfer is allowed to complete its current transaction. To ensure

latency limits when multiple DMA accesses are requested

simultaneously, a fairness algorithm guarantees an interleaved

minimum percentage of bus bandwidth for priority levels 2

through 7. Priority levels 0 and 1 do not take part in the fairness

algorithm and may use 100% of the bus bandwidth. If a tie occurs

on two DMA requests of the same priority level, a simple round

robin method is used to evenly share the allocated bandwidth.

The round robin allocation can be disabled for each DMA

channel, allowing it to always be at the head of the line. Priority

levels 2 to 7 are guaranteed the minimum bus bandwidth shown

in Table 4-7 after the CPU and DMA priority levels 0 and 1 have

satisfied their requirements.

4.4.4 Transaction Modes Supported

The flexible configuration of each DMA channel and the ability to

chain multiple channels allow the creation of both simple and

complex use cases. General use cases include, but are not

limited to:

4.4.4.1 Simple DMA

In a simple DMA case, a single TD transfers data between a

source and sink (peripherals or memory location). The basic

timing diagrams of DMA read and write cycles shown in

Figure 4-1. For more description on other transfer modes, refer

to the Technical Reference Manual.

Figure 4-1. DMA Timing Diagram

ADDRESS Phase

DATA Phase

ADDRESS Phase

DATA Phase

CLK

ADDR 16/32

WRITE

ADDR 16/32

A

B

A

B

WRITE

DATA

DATA (A)

DATA

READY

Basic DMA Read Transfer without wait states

Basic DMA Write Transfer without wait states

4.4.4.2 Auto Repeat DMA

data previously received in the other buffer. In its simplest form,

this is done by chaining two TDs together so that each TD calls

the opposite TD when complete.

Auto repeat DMA is typically used when a static pattern is

repetitively read from system memory and written to a peripheral.

This is done with a single TD that chains to itself.

4.4.4.4 Circular DMA

4.4.4.3 Ping Pong DMA

Circular DMA is similar to ping pong DMA except it contains more

than two buffers. In this case there are multiple TDs; after the last

TD is complete it chains back to the first TD.

A ping pong DMA case uses double buffering to allow one buffer

to be filled by one client while another client is consuming the

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Data Sheet

4.4.4.5 Scatter Gather DMA

4.5 Interrupt Controller

In the case of scatter gather DMA, there are multiple

The interrupt controller provides a mechanism for hardware

resources to change program execution to a new address,

independent of the current task being executed by the main

code. The interrupt controller provides enhanced features not

found on original 8051 interrupt controllers:

noncontiguous sources or destinations that are required to

effectively carry out an overall DMA transaction. For example, a

packet may need to be transmitted off of the device and the

packet elements, including the header, payload, and trailer, exist

in various noncontiguous locations in memory. Scatter gather

DMA allows the segments to be concatenated together by using

multiple TDs in a chain. The chain gathers the data from the

multiple locations. A similar concept applies for the reception of

data onto the device. Certain parts of the received data may need

to be scattered to various locations in memory for software

processing convenience. Each TD in the chain specifies the

location for each discrete element in the chain.

Thirty-two interrupt vectors

Jumps directly to ISR anywhere in code space with dynamic

vector addresses

Multiple sources for each vector

Flexible interrupt to vector matching

Each interrupt vector is independently enabled or disabled

4.4.4.6 Packet Queuing DMA

Each interrupt can be dynamically assigned one of eight

priorities

Packet queuing DMA is similar to scatter gather DMA but

specifically refers to packet protocols. With these protocols,

there may be separate configuration, data, and status phases

associated with sending or receiving a packet.

Eight level nestable interrupts

Multiple I/O interrupt vectors

Software can send interrupts

Software can clear pending interrupts

For instance, to transmit a packet, a memory mapped

configuration register can be written inside a peripheral,

specifying the overall length of the ensuing data phase. The CPU

can set up this configuration information anywhere in system

memory and copy it with a simple TD to the peripheral. After the

configuration phase, a data phase TD (or a series of data phase

TDs) can begin (potentially using scatter gather). When the data

phase TD(s) finish, a status phase TD can be invoked that reads

some memory mapped status information from the peripheral

and copies it to a location in system memory specified by the

CPU for later inspection. Multiple sets of configuration, data, and

status phase “subchains” can be strung together to create larger

chains that transmit multiple packets in this way. A similar

concept exists in the opposite direction to receive the packets.

When an interrupt is pending, the current instruction is

completed and the program counter is pushed onto the stack.

Code execution then jumps to the program address provided by

the vector. After the ISR is completed, a RETI instruction is

executed and returns execution to the instruction following the

previously interrupted instruction. To do this the RETI instruction

pops the program counter from the stack.

If the same priority level is assigned to two or more interrupts,

the interrupt with the lower vector number is executed first. Each

interrupt vector may choose from three interrupt sources: Fixed

Function, DMA, and UDB. The fixed function interrupts are direct

connections to the most common interrupt sources and provide

the lowest resource cost connection. The DMA interrupt sources

provide direct connections to the two DMA interrupt sources

provided per DMA channel. The third interrupt source for vectors

is from the UDB digital routing array. This allows any digital signal

available to the UDB array to be used as an interrupt source.

Fixed function interrupts and all interrupt sources may be routed

to any interrupt vector using the UDB interrupt source

connections.

4.4.4.7 Nested DMA

One TD may modify another TD, as the TD configuration space

is memory mapped similar to any other peripheral. For example,

a first TD loads a second TD’s configuration and then calls the

second TD. The second TD moves data as required by the

application. When complete, the second TD calls the first TD,

which again updates the second TD’s configuration. This

process repeats as often as necessary.

Figure 4-2 on page 18 represents typical flow of events when an

interrupt triggered. Figure 4-3 on page 19 shows the interrupt

structure and priority polling.

Document Number: 001-53413 Rev. *L

Page 17 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Figure 4-3. Interrupt Structure

Interrupt Polling logic

Interrupts form Fixed

function blocks, DMA and

UDBs

Highest Priority

Interrupt Enable/

Disable, PEND and

POST logic

Interrupts 0 to 30

from UDBs

0

Interrupts 0 to 30

from Fixed

1

Function Blocks

IRQ

0 to 30

ACTIVE_INT_NUM

INT_VECT_ADDR

Individual

Enable Disable

bits

8 Level

Priority

decoder

for all

Interrupt

routing logic

to select 31

sources

Interrupts 0 to

30 from DMA

[15:0]

interrupts

IRA

IRC

30

Global Enable

disable bit

Lowest Priority

Table 4-8. Interrupt Vector Table

#

Fixed Function

DMA

UDB

0

1

2

3

4

5

6

7

LVD

ECC

Reserved

Sleep (Pwr Mgr)

PICU[0]

PICU[1]

PICU[2]

PICU[3]

PICU[4]

PICU[5]

PICU[6]

PICU[12]

PICU[15]

Comparators Combined

Switched Caps Combined

I²C

phub_termout0[0]

phub_termout0[1]

phub_termout0[2]

phub_termout0[3]

phub_termout0[4]

phub_termout0[5]

phub_termout0[6]

phub_termout0[7]

phub_termout0[8]

phub_termout0[9]

phub_termout0[10]

phub_termout0[11]

phub_termout0[12]

phub_termout0[13]

phub_termout0[14]

phub_termout0[15]

phub_termout1[0]

phub_termout1[1]

phub_termout1[2]

phub_termout1[3]

phub_termout1[4]

phub_termout1[5]

udb_intr[0]

udb_intr[1]

udb_intr[2]

udb_intr[3]

udb_intr[4]

udb_intr[5]

udb_intr[6]

udb_intr[7]

udb_intr[8]

udb_intr[9]

udb_intr[10]

udb_intr[11]

udb_intr[12]

udb_intr[13]

udb_intr[14]

udb_intr[15]

udb_intr[16]

udb_intr[17]

udb_intr[18]

udb_intr[19]

udb_intr[20]

udb_intr[21]

8

9

10

11

12

13

14

15

16

17

18

19

20

21

CAN

Timer/Counter0

Timer/Counter1

Timer/Counter2

Timer/Counter3

USB SOF Int

Document Number: 001-53413 Rev. *L

Page 19 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Table 4-8. Interrupt Vector Table (continued)

Fixed Function

#

DMA

UDB

udb_intr[22]

udb_intr[23]

udb_intr[24]

udb_intr[25]

udb_intr[26]

udb_intr[27]

udb_intr[28]

udb_intr[29]

udb_intr[30]

udb_intr[31]

22

23

24

25

26

27

28

29

30

31

USB Arb Int

USB Bus Int

USB Endpoint[0]

USB Endpoint Data

Reserved

LCD

DFB Int

Decimator Int

PHUB Error Int

EEPROM Fault Int

phub_termout1[6]

phub_termout1[7]

phub_termout1[8]

phub_termout1[9]

phub_termout1[10]

phub_termout1[11]

phub_termout1[12]

phub_termout1[13]

phub_termout1[14]

phub_termout1[15]

The device offers the ability to assign one of four protection

levels to each row of flash. Table 5-1 lists the protection modes

available. Flash protection levels can only be changed by

performing a complete flash erase. The Full Protection and Field

Upgrade settings disable external access (through a debugging

tool such as PSoC Creator, for example). If your application

requires code update through a boot loader, then use the Field

Upgrade setting. Use the Unprotected setting only when no

security is needed in your application. The PSoC device also

offers an advanced security feature called Device Security that

permanently disables all test, programming, and debug ports,

protecting your application from external access (see Device

Security on page 62). For information about how to take full

advantage of the security features in PSoC, see the PSoC 3

TRM.

5. Memory

5.1 Static RAM

CY8C36 Static RAM (SRAM) is used for temporary data storage.

Up to 8 KB of SRAM is provided and can be accessed by the

8051 or the DMA controller. See Memory Map on page 22.

Simultaneous access of SRAM by the 8051 and the DMA

controller is possible if different 4-KB blocks are accessed.

5.2 Flash Program Memory

Flash memory in PSoC devices provides nonvolatile storage for

user firmware, user configuration data, bulk data storage, and

optional ECC data. The main flash memory area contains up to

64 KB of user program space.

Table 5-1. Flash Protection

Protection

Up to an additional 8 KB of flash space is available for ECC. If

ECC is not used this space can store device configuration data

and bulk user data. User code may not be run out of the ECC

flash memory section. ECC can correct one bit error and detect

two bit errors per 8 bytes of firmware memory; an interrupt can

be generated when an error is detected.

Allowed

Not Allowed

Setting

Unprotected

External read and write

+ internal read and write

–

Factory

Upgrade

External write + internal External read

read and write

Flash is read in units of rows; each row is 9 bytes wide with 8

bytes of data and 1 byte of ECC data. When a row is read, the

data bytes are copied into an 8-byte instruction buffer. The CPU

fetches its instructions from this buffer, for improved CPU

performance.

Field Upgrade Internal read and write External read and

write

Full Protection Internal read

External read and

write + internal write

Flash programming is performed through a special interface and

preempts code execution out of flash. The flash programming

interface performs flash erasing, programming and setting code

protection levels. Flash in-system serial programming (ISSP),

typically used for production programming, is possible through

both the SWD and JTAG interfaces. In-system programming,

typically used for bootloaders, is also possible using serial

interfaces such as I²C, USB, UART, and SPI, or any

communications protocol.

Disclaimer

Note the following details of the flash code protection features on

Cypress devices.

Cypress products meet the specifications contained in their

particular Cypress data sheets. Cypress believes that its family

of products is one of the most secure families of its kind on the

market today, regardless of how they are used. There may be

methods, unknown to Cypress, that can breach the code

protection features. Any of these methods, to our knowledge,

would be dishonest and possibly illegal. Neither Cypress nor any

other semiconductor manufacturer can guarantee the security of

their code. Code protection does not mean that we are

guaranteeing the product as “unbreakable.”

5.3 Flash Security

All PSoC devices include a flexible flash-protection model that

prevents access and visibility to on-chip flash memory. This

prevents duplication or reverse engineering of proprietary code.

Flash memory is organized in blocks, where each block contains

256 bytes of program or data and 32 bytes of ECC or

configuration data. A total of up to 256 blocks is provided on

64-KB flash devices.

Cypress is willing to work with the customer who is concerned

about the integrity of their code. Code protection is constantly

evolving. We at Cypress are committed to continuously

improving the code protection features of our products.

Document Number: 001-53413 Rev. *L

Page 20 of 126

PSoC^®3: CY8C36 Family

Data Sheet

5.4 EEPROM

PSoC EEPROM memory is a byte-addressable nonvolatile memory. The CY8C36 has up to 2 KB of EEPROM memory to store user

data. Reads from EEPROM are random access at the byte level. Reads are done directly; writes are done by sending write commands

to an EEPROM programming interface. CPU code execution can continue from flash during EEPROM writes. EEPROM is erasable

and writeable at the row level. The EEPROM is divided into 128 rows of 16 bytes each.

The CPU can not execute out of EEPROM. There is no ECC hardware associated with EEPROM. If ECC is required it must be handled

in firmware.

5.5 Nonvolatile Latches (NVLs)

PSoC has a 4-byte array of nonvolatile latches (NVLs) that are used to configure the device at reset. The NVL register map is shown

in Table 5-2.

Table 5-2. Device Configuration NVL Register Map

Register Address

7

6

5

4

3

2

1

0

0x00

0x01

0x02

0x03

PRT3RDM[1:0]

PRT12RDM[1:0]

PRT2RDM[1:0]

PRT6RDM[1:0]

PRT1RDM[1:0]

PRT5RDM[1:0]

PRT0RDM[1:0]

PRT4RDM[1:0]

PRT15RDM[1:0]

XRESMEN

DIG_PHS_DLY[3:0]

ECCEN

DPS[1:0]

CFGSPEED

The details for individual fields and their factory default settings are shown in Table 5-3:.

Table 5-3. Fields and Factory Default Settings

Field

Description

Settings

PRTxRDM[1:0]

Controls reset drive mode of the corresponding IO port. 00b (default) - high impedance analog

See “Reset Configuration” on page 38. All pins of the port 01b - high impedance digital

are set to the same mode.

10b - resistive pull up

11b - resistive pull down

XRESMEN

CFGSPEED

DPS{1:0]

Controls whether pin P1[2] is used as a GPIO or as an

external reset. See “Pin Descriptions” on page 10, XRES 1 (default for 48-pin parts) - external reset

description.

0 (default for 68-pin and 100-pin parts) - GPIO

Controls the speed of the IMO-based clock during the

device boot process, for faster boot or low-power

operation

0 (default) - 12 MHz IMO

1 - 48 MHz IMO

Controls the usage of various P1 pins as a debug port. 00b - 5-wire JTAG

See “Programming, Debug Interfaces, Resources” on

page 59.

01b (default) - 4-wire JTAG

10b - SWD

11b - debug ports disabled

ECCEN

Controls whether ECC flash is used for ECC or for general 0 (default) - ECC disabled

configuration and data storage. See “Flash Program

Memory” on page 20.

1 - ECC enabled

DIG_PHS_DLY[3:0]

Selects the digital clock phase delay.

See the TRM for details.

Although PSoC Creator provides support for modifying the device configuration NVLs, the number of NVL erase / write cycles is limited

– see “Nonvolatile Latches (NVL))” on page 102.

Document Number: 001-53413 Rev. *L

Page 21 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Figure 5-1 is the EMIF block diagram. The EMIF supports

synchronous and asynchronous memories. The CY8C36

supports only one type of external memory device at a time.

5.6 External Memory Interface

CY8C36 provides an external memory interface (EMIF) for

connecting to external memory devices. The connection allows

read and write accesses to external memories. The EMIF

operates in conjunction with UDBs, I/O ports, and other

hardware to generate external memory address and control

signals. At 33 MHz, each memory access cycle takes four bus

clock cycles.

External memory can be accessed through the 8051 xdata

space; up to 24 address bits can be used. See xdata Space on

page 24. The memory can be 8 or 16 bits wide.

Figure 5-1. EMIF Block Diagram

External_MEM_ ADDR[23:0]

External_MEM_DATA[15:0]

Address Signals

IO

PORTs

Data,

Address,

and Control

Signals

Data Signals

IO IF

IO

PORTs

Control Signals

Control

IO

PORTs

PHUB

Data,

Address,

and Control

Signals

DSI Dynamic Output

Control

UDB

DSI to Port

Other

EM Control

Signals

Control

Signals

Data,

Address,

and Control

Signals

EMIF

5.7.2 Internal Data Space

5.7 Memory Map

The CY8C36 8051 internal data space is 384 bytes, compressed

within a 256-byte space. This space consists of 256 bytes of

RAM (in addition to the SRAM mentioned in “Static RAM” on

page 20) and a 128-byte space for Special Function Registers

(SFRs). See Figure 5-2. The lowest 32 bytes are used for four

banks of registers R0-R7. The next 16 bytes are bit-addressable.

The CY8C36 8051 memory map is very similar to the MCS-51

memory map.

5.7.1 Code Space

The CY8C36 8051 code space is 64 KB. Only main flash exists

in this space. See the “Flash Program Memory” section on

page 20.

Document Number: 001-53413 Rev. *L

Page 22 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Figure 5-2. 8051 Internal Data Space

In addition to the register or bit address modes used with the

lower 48 bytes, the lower 128 bytes can be accessed with direct

or indirect addressing. With direct addressing mode, the upper

128 bytes map to the SFRs. With indirect addressing mode, the

upper 128 bytes map to RAM. Stack operations use indirect

addressing; the 8051 stack space is 256 bytes. See the

“Addressing Modes” section on page 11.

0x00

4 Banks, R0-R7 Each

0x1F

0x20

0x2F

0x30

Bit-Addressable Area

Lower Core RAM Shared with Stack Space

(direct and indirect addressing)

0x7F

0x80

SFR

Upper Core RAM Shared

with Stack Space

(indirect addressing)

Special Function Registers

(direct addressing)

0xFF

5.7.3 SFRs

The special function register (SFR) space provides access to frequently accessed registers. The memory map for the SFR memory

space is shown in Table 5-4.

Table 5-4. SFR Map

Address

0×F8 SFRPRT15DR

0×F0

0/8

1/9

2/A

SFRPRT15SEL

SFRPRT12SEL

MXAX

3/B

4/C

5/D

6/E

7/F

SFRPRT15PS

–

B

–

0×E8 SFRPRT12DR

0×E0 ACC

SFRPRT12PS

–

0×D8 SFRPRT6DR

0×D0 PSW

SFRPRT6PS

SFRPRT6SEL

–

0×C8 SFRPRT5DR

0×C0 SFRPRT4DR

SFRPRT5PS

SFRPRT5SEL

SFRPRT4SEL

–

SFRPRT4PS

0×B8

–

0×B0 SFRPRT3DR

0×A8 IE

SFRPRT3PS

SFRPRT3SEL

–

0×A0 P2AX

–

SFRPRT1SEL

SFRPRT2SEL

–

0×98 SFRPRT2DR

0×90 SFRPRT1DR

SFRPRT2PS

SFRPRT1PS

SFRPRT0PS

SP

DPX0

–

DPX1

–

0×88

–

SFRPRT0SEL

DPL0

0×80 SFRPRT0DR

DPH0

DPL1

DPH1

DPS

The CY8C36 family provides the standard set of registers found

on industry standard 8051 devices. In addition, the CY8C36

devices add SFRs to provide direct access to the I/O ports on the

device. The following sections describe the SFRs added to the

CY8C36 family.

JMP @A+DPTR

INC DPTR

MOV DPTR, #data16

The extended data pointer SFRs, DPX0, DPX1, MXAX, and

P2AX, hold the most significant parts of memory addresses

during access to the xdata space. These SFRs are used only

with the MOVX instructions.

XData Space Access SFRs

The 8051 core features dual DPTR registers for faster data

transfer operations. The data pointer select SFR, DPS, selects

which data pointer register, DPTR0 or DPTR1, is used for the

following instructions:

During a MOVX instruction using the DPTR0/DPTR1 register,

the most significant byte of the address is always equal to the

contents of DPX0/DPX1.

MOVX @DPTR, A

MOVX A, @DPTR

MOVC A, @A+DPTR

During a MOVX instruction using the R0 or R1 register, the most

significant byte of the address is always equal to the contents of

MXAX, and the next most significant byte is always equal to the

contents of P2AX.

Document Number: 001-53413 Rev. *L

Page 23 of 126

PSoC^®3: CY8C36 Family

Data Sheet

I/O Port SFRs

Table 5-5. XDATA Data Address Map

The I/O ports provide digital input sensing, output drive, pin

interrupts, connectivity for analog inputs and outputs, LCD, and

access to peripherals through the DSI. Full information on I/O

ports is found in I/O System and Routing on page 32.

Address Range

0×00 0000 – 0×00 1FFF

0×00 4000 – 0×00 42FF

0×00 4300 – 0×00 43FF

0×00 4400 – 0×00 44FF

0×00 4500 – 0×00 45FF

0×00 4700 – 0×00 47FF

0×00 4900 – 0×00 49FF

0×00 4E00 – 0×00 4EFF

0×00 4F00 – 0×00 4FFF

0×00 5000 – 0×00 51FF

0×00 5400 – 0×00 54FF

Purpose

SRAM

Clocking, PLLs, and oscillators

Power management

Interrupt controller

I/O ports are linked to the CPU through the PHUB and are also

available in the SFRs. Using the SFRs allows faster access to a

limited set of I/O port registers, while using the PHUB allows boot

configuration and access to all I/O port registers.

Ports interrupt control

Flash programming interface

I²C controller

Each SFR supported I/O port provides three SFRs:

SFRPRTxDR sets the output data state of the port (where × is

port number and includes ports 0–6, 12 and 15).

Decimator

Fixed timer/counter/PWMs

I/O ports control

The SFRPRTxSEL selects whether the PHUB PRTxDR

register or the SFRPRTxDR controls each pin’s output buffer

within the port. If a SFRPRTxSEL[y] bit is high, the

corresponding SFRPRTxDR[y] bit sets the output state for that

pin. If a SFRPRTxSEL[y] bit is low, the corresponding

PRTxDR[y] bit sets the output state of the pin (where y varies

from 0 to 7).

External Memory Interface

(EMIF) control registers

0×00 5800 – 0×00 5FFF

0×00 6000 – 0×00 60FF

0×00 6400 – 0×00 6FFF

0×00 7000 – 0×00 7FFF

0×00 8000 – 0×00 8FFF

0×00 A000 – 0×00 A400

0×00 C000 – 0×00 C800

0×01 0000 – 0×01 FFFF

Analog Subsystem interface

USB controller

The SFRPRTxPS is a read only register that contains pin state

values of the port pins.

UDB configuration

PHUB configuration

EEPROM

5.7.3.1 xdata Space

The 8051 xdata space is 24-bit, or 16 MB in size. The majority of

this space is not “external”—it is used by on-chip components.

See Table 5-5. External, that is, off-chip, memory can be

accessed using the EMIF. See External Memory Interface on

page 22.

CAN

Digital Filter Block

Digital Interconnect

configuration

0×05 0220 – 0×05 02F0

0×08 0000 – 0×08 1FFF

0×80 0000 – 0×FF FFFF

Debug controller

flash ECC bytes

External Memory Interface

Document Number: 001-53413 Rev. *L

Page 24 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Key features of the clocking system include:

6. System Integration

Seven general purpose clock sources

3- to 62-MHz IMO, ±1% at 3 MHz

4- to 25-MHz external crystal oscillator (MHzECO)

Clock doubler provides a doubled clock frequency output for

the USB block, see USB Clock Domain on page 28.

DSI signal from an external I/O pin or other logic

24- to 67-MHz fractional PLL sourced from IMO, MHzECO,

or DSI

6.1 Clocking System

The clocking system generates, divides, and distributes clocks

throughout the PSoC system. For the majority of systems, no

external crystal is required. The IMO and PLL together can

generate up to a 66 MHz clock, accurate to ±1% over voltage and

temperature. Additional internal and external clock sources allow

each design to optimize accuracy, power, and cost. All of the

system clock sources can be used to generate other clock

frequencies in the 16-bit clock dividers and UDBs for anything

the user wants, for example a UART baud rate generator.

1-kHz, 33-kHz, 100-kHz ILO for WDT and sleep timer

32.768-kHz external crystal oscillator (kHzECO) for RTC

IMO has a USB mode that auto locks to the USB bus clock

requiring no external crystal for USB. (USB equipped parts only)

Clock generation and distribution is automatically configured

through the PSoC Creator IDE graphical interface. This is based

on the complete system’s requirements. It greatly speeds the

design process. PSoC Creator allows you to build clocking

systems with minimal input. You can specify desired clock

frequencies and accuracies, and the software locates or builds a

clock that meets the required specifications. This is possible

because of the programmability inherent PSoC.

Independently sourced clock in all clock dividers

Eight 16-bit clock dividers for the digital system

Four 16-bit clock dividers for the analog system

Dedicated 16-bit divider for the bus clock

Dedicated 4-bit divider for the CPU clock

Automatic clock configuration in PSoC Creator

Document Number: 001-53413 Rev. *L

Page 25 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Figure 6-1. Clocking Subsystem

External IO

or DSI

0-66 MHz

3-62 MHz

IMO

4-25 MHz

ECO

1,33,100 kHz

ILO

32 kHz ECO

CPU

Clock

CPU Clock Divider

4 bit

48 MHz

Doubler for

USB

24-67 MHz

PLL

System

Clock Mux

Bus

Clock

Bus Clock Divider

16 bit

s

k

e

Digital Clock

Divider 16 bit

Digital Clock

Divider 16 bit

Analog Clock

Divider 16 bit

w

s

k

e

w

Digital Clock

Divider 16 bit

Digital Clock

Divider 16 bit

Analog Clock

Divider 16 bit

7

s

k

e

w

7

Analog Clock

Divider 16 bit

Digital Clock

Divider 16 bit

Digital Clock

Divider 16 bit

s

k

e

w

Analog Clock

Divider 16 bit

Digital Clock

Divider 16 bit

Digital Clock

Divider 16 bit

Table 6-1. Oscillator Summary

Source

IMO

Fmin

3 MHz

4 MHz

Tolerance at Fmin

±1% over voltage and temperature

Crystal dependent

Fmax

62 MHz

25 MHz

Tolerance at Fmax

±7%

Startup Time

10 µs max

MHzECO

Crystal dependent

5 ms typ, max is

crystal dependent

DSI

PLL

0 MHz

Input dependent

66 MHz

67 MHz

48 MHz

100 kHz

Input dependent

–55%, +100%

Input dependent

250 µs max

1 µs max

24 MHz Input dependent

48 MHz Input dependent

Doubler

ILO

1 kHz

–50%, +100%

15 ms max in lowest

power mode

kHzECO

32 kHz

Crystal dependent

32 kHz

Crystal dependent

500 ms typ, max is

crystal dependent

6.1.1 Internal Oscillators

6.1.1.2 Clock Doubler

The clock doubler outputs a clock at twice the frequency of the

input clock. The doubler worksat input frequency of 24 MHz,

providing 48 MHz for the USB. It can be configured to use a clock

from the IMO, MHzECO, or the DSI (external pin).

6.1.1.1 Internal Main Oscillator

In most designs the IMO is the only clock source required, due

to its ±1% accuracy. The IMO operates with no external

components and outputs a stable clock. A factory trim for each

frequency range is stored in the device. With the factory trim,

tolerance varies from ±1% at 3 MHz, up to ±7% at 62 MHz. The

IMO, in conjunction with the PLL, allows generation of CPU and

system clocks up to the device's maximum frequency (see

Phase-Locked Loop).

6.1.1.3 Phase-Locked Loop

The PLL allows low frequency, high accuracy clocks to be

multiplied to higher frequencies. This is a tradeoff between

higher clock frequency and accuracy and, higher power

consumption and increased startup time.

The IMO provides clock outputs at 3, 6, 12, 24, 48, and 62 MHz.

Document Number: 001-53413 Rev. *L

Page 26 of 126

PSoC^®3: CY8C36 Family

Data Sheet

The PLL block provides a mechanism for generating clock

frequencies based upon a variety of input sources. The PLL

outputs clock frequencies in the range of 24 to 67 MHz. Its input

and feedback dividers supply 4032 discrete ratios to create

almost any desired system clock frequency. The accuracy of the

PLL output depends on the accuracy of the PLL input source.

The most common PLL use is to multiply the IMO clock at 3 MHz,

where it is most accurate, to generate the CPU and system

clocks up to the device’s maximum frequency.

Figure 6-2. MHzECO Block Diagram

XCLK_MHZ

4 – 25 MHz

Crystal Osc

The PLL achieves phase lock within 250 µs (verified by bit

setting). It can be configured to use a clock from the IMO,

MHzECO or DSI (external pin). The PLL clock source can be

used until lock is complete and signaled with a lock bit. The lock

signal can be routed through the DSI to generate an interrupt.

Disable the PLL before entering low-power modes.

Xo

(Pin P15[0])

Xi

(Pin P15[1])

4 – 25 MHz

crystal

External

Components

Capacitors

6.1.1.4 Internal Low-Speed Oscillator

The ILO provides clock frequencies for low-power consumption,

including the watchdog timer, and sleep timer. The ILO

generates up to three different clocks: 1 kHz, 33 kHz, and

100 kHz.

6.1.2.2 32.768-kHz ECO

The 32.768-kHz external crystal oscillator (32kHzECO) provides

precision timing with minimal power consumption using an

external 32.768-kHz watch crystal (see Figure 6-3). The

32kHzECO also connects directly to the sleep timer and provides

the source for the RTC. The RTC uses a 1-second interrupt to

implement the RTC functionality in firmware.

The 1-kHz clock (CLK1K) is typically used for a background

‘heartbeat’ timer. This clock inherently lends itself to low-power

supervisory operations such as the watchdog timer and long

sleep intervals using the central timewheel (CTW).

The central timewheel is a 1-kHz, free-running, 13-bit counter

clocked by the ILO. The central timewheel is always enabled,

except in hibernate mode and when the CPU is stopped during

debug on chip mode. It can be used to generate periodic

interrupts for timing purposes or to wake the system from a

low-power mode. Firmware can reset the central timewheel.

Systems that require accurate timing should use the RTC

capability instead of the central timewheel.

The oscillator works in two distinct power modes. This allows

users to trade off power consumption with noise immunity from

neighboring circuits. The GPIO pins connected to the external

crystal and capacitors are fixed.

Figure 6-3. 32kHzECO Block Diagram

The 100-kHz clock (CLK100K) works as a low-power system

clock to run the CPU. It can also generate time intervals such as

fast sleep intervals using the fast timewheel.

XCLK32K

32 kHz

Crystal Osc

The fast timewheel is a 100-kHz, 5-bit counter clocked by the ILO

that can also be used to wake the system. The fast timewheel

settings are programmable, and the counter automatically resets

when the terminal count is reached. This enables flexible,

periodic wakeups of the CPU at a higher rate than is allowed

using the central timewheel. The fast timewheel can generate an

optional interrupt each time the terminal count is reached.

Xo

Xi

(Pin P15[2])

(Pin P15[3])

The 33-kHz clock (CLK33K) comes from a divide-by-3 operation

on CLK100K. This output can be used as a reduced accuracy

version of the 32.768-kHz ECO clock with no need for a crystal.

32 kHz

crystal

External

Components

Capacitors

6.1.2 External Oscillators

6.1.2.1 MHz External Crystal Oscillator

6.1.2.3 Digital System Interconnect

The MHzECO provides high frequency, high precision clocking

using an external crystal (see Figure 6-2). It supports a wide

variety of crystal types, in the range of 4 to 25 MHz. When used

in conjunction with the PLL, it can generate CPU and system

clocks up to the device's maximum frequency (see

Phase-Locked Loop). The GPIO pins connecting to the external

crystal and capacitors are fixed. MHzECO accuracy depends on

the crystal chosen.

The DSI provides routing for clocks taken from external clock

oscillators connected to I/O. The oscillators can also be

generated within the device in the digital system and UDBs.

While the primary DSI clock input provides access to all clocking

resources, up to eight other DSI clocks (internally or externally

generated) may be routed directly to the eight digital clock

dividers. This is only possible if there are multiple precision clock

sources.

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Page 27 of 126

PSoC^®3: CY8C36 Family

Data Sheet

6.1.3 Clock Distribution

Each clock divider consists of an 8-input multiplexer, a 16-bit

clock divider (divide by 2 and higher) that generates ~50% duty

cycle clocks, system clock resynchronization logic, and deglitch

logic. The outputs from each digital clock tree can be routed into

the digital system interconnect and then brought back into the

clock system as an input, allowing clock chaining of up to 32 bits.

All seven clock sources are inputs to the central clock distribution

system. The distribution system is designed to create multiple

high precision clocks. These clocks are customized for the

design’s requirements and eliminate the common problems

found with limited resolution prescalers attached to peripherals.

The clock distribution system generates several types of clock

trees.

6.1.4 USB Clock Domain

The USB clock domain is unique in that it operates largely

asynchronously from the main clock network. The USB logic

contains a synchronous bus interface to the chip, while running

on an asynchronous clock to process USB data. The USB logic

requires a 48 MHz frequency. This frequency can be generated

from different sources, including DSI clock at 48 MHz or doubled

value of 24 MHz from internal oscillator, DSI signal, or crystal

oscillator.

The system clock is used to select and supply the fastest clock

in the system for general system clock requirements and clock

synchronization of the PSoC device.

Bus clock 16-bit divider uses the system clock to generate the

system's bus clock used for data transfers. Bus clock is the

source clock for the CPU clock divider.

Eight fully programmable 16-bit clock dividers generate digital

system clocks for general use in the digital system, as

configured by the design’s requirements. Digital system clocks

can generate custom clocks derived from any of the seven

clock sources for any purpose. Examples include baud rate

generators, accurate PWM periods, and timer clocks, and

many others. If more than eight digital clock dividers are

required, theUniversalDigitalBlocks(UDBs)andfixedfunction

timer/counter/PWMs can also generate clocks.

Four16-bitclockdividersgenerateclocksfortheanalogsystem

components that require clocking, such as ADC and mixers.

The analog clock dividers include skew control to ensure that

critical analog events do not occur simultaneously with digital

switching events. This is done to reduce analog system noise.

6.2 Power System

The power system consists of separate analog, digital, and I/O

supply pins, labeled Vdda, Vddd, and Vddio×, respectively. It

also includes two internal 1.8 V regulators that provide the digital

(Vccd) and analog (Vcca) supplies for the internal core logic. The

output pins of the regulators (Vccd and Vcca) and the Vddio pins

must have capacitors connected as shown in Figure 6-4. The

two Vccd pins must be shorted together, with as short a trace as

possible, and connected to a 1-µF ±10% ×5R capacitor. The

power system also contains a sleep regulator, an I²C regulator,

and a hibernate regulator.

Figure 6-4. PSoC Power System

µF

Vddd

1

Vddio2

Vddio0

0.1µF

I/O Supply

Vddio0

0.1µF

I2C

Regulator

Sleep

Regulator

Digital

Vdda

Domain

Vdda

Vcca

Analog

Regulator

0.1µF

Digital

Regulators

Vssb

.

µF

1

Vssa

Analog

Domain

Hibernate

Regulator

I/O Supply

0.1µF

0.1 µF

Vddd

Vddio1

Vddio3

Note The two Vccd pins must be connected together with as short a trace as possible. A trace under the device is recommended, as

shown in Figure 2-6 on page 10.

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Page 28 of 126

PSoC^®3: CY8C36 Family

Data Sheet

6.2.1 Power Modes

Active is the main processing mode. Its functionality is

configurable. Each power controllable subsystem is enabled or

disabled by using separate power configuration template

registers. In alternate active mode, fewer subsystems are

enabled, reducing power. In sleep mode most resources are

disabled regardless of the template settings. Sleep mode is

optimized to provide timed sleep intervals and RTC functionality.

The lowest power mode is hibernate, which retains register and

SRAM state, but no clocks, and allows wakeup only from I/O

pins. Figure 6-5 illustrates the allowable transitions between

power modes.

PSoC 3 devices have four different power modes, as shown in

Table 6-2 and Table 6-3. The power modes allow a design to

easily provide required functionality and processing power while

simultaneously minimizing power consumption and maximizing

battery life in low-power and portable devices.

PSoC 3 power modes, in order of decreasing power

consumption are:

Active

Alternate Active

Sleep

.

Hibernate

Table 6-2. Power Modes

Power

Wakeup

Source

Description

Entry Condition

Active Clocks

Regulator

Modes

Active

Primary mode of operation, all periph- Wakeup, reset,

Any interrupt Any

All regulators available. Digital

erals available (programmable)

manual register

entry

(programmable) and analog regulators can be

disabled if external regulation

used.

Alternate

Active

Similar to Active mode, and is typically Manual register

configured to have fewer peripherals entry

active to reduce power. One possible

Any interrupt Any

All regulators available. Digital

(programmable) and analog regulators can be

disabled if external regulation

configuration is to use the UDBs for

used.

processing, with the CPU turned off

Sleep

Allsubsystemsautomaticallydisabled Manual register

entry

Comparator, ILO/kHzECO

Both digital and analog

regulators buzzed.

Digital and analog regulators

can be disabled if external

regulation used.

2

PICU, I C,

RTC, CTW,

LVD

Hibernate Allsubsystemsautomaticallydisabled Manual register

Lowest power consuming mode with entry

all peripherals and internal regulators

disabled, excepthibernateregulatoris

enabled

PICU

–

Only hibernate regulator active.

Configuration and memory contents

retained

Table 6-3. Power Modes Wakeup Time and Power Consumption

Sleep

Modes

Wakeup

Time

Current

(Typ)

Code

Digital

Analog

ClockSources

Available

Reset

Wakeup Sources

Sources

Execution Resources Resources

Active

–

1.2 mA^[16]

Yes

All

–

All

Alternate

Active

–

User

defined

<15 µs

1 µA

No

I²C

Comparator ILO/kHzECO

Comparator,

PICU, I²C, RTC,

CTW, LVD

XRES, LVD,

WDR

Sleep

Hibernate <100 µs

200 nA

No

None

PICU

XRES

Note

16. Bus clock off. Execute from CPU instruction buffer at 6 MHz. See Table 11-2 on page 65.

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Page 29 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Figure 6-5. Power Mode Transitions

central timewheel provides periodic interrupts to allow the

system to wake up, poll peripherals, or perform real-time

functions. Reset event sources include the external reset I/O pin

(XRES), WDT, and precision reset (PRES).

Active

6.2.2 Boost Converter

Applications that use a supply voltage of less than 1.71 V, such

as solar or single cell battery supplies, may use the on-chip boost

converter. The boost converter may also be used in any system

that requires a higher operating voltage than the supply provides.

For instance, this includes driving 5.0 V LCD glass in a 3.3 V

system. The boost converter accepts an input voltage as low as

0.5 V. With one low cost inductor it produces a selectable output

voltage sourcing enough current to operate the PSoC and other

on-board components.

Manual

Sleep

Hibernate

Buzz

Alternate

Active

The boost converter accepts an input voltage from 0.5 V to 5.5 V

(Vbat), and can start up with Vbat as low as 0.5 V. The converter

provides a user configurable output voltage of 1.8 to 5.0 V

(Vboost). Vbat is typically less than Vboost; if Vbat is greater than

or equal to Vboost, then Vboost will be the same as Vbat. The

block can deliver up to 50 mA (Iboost) depending on

configuration.

6.2.1.1 Active Mode

Active mode is the primary operating mode of the device. When

in active mode, the active configuration template bits control

which available resources are enabled or disabled. When a

resource is disabled, the digital clocks are gated, analog bias

currents are disabled, and leakage currents are reduced as

appropriate. User firmware can dynamically control subsystem

power by setting and clearing bits in the active configuration

template. The CPU can disable itself, in which case the CPU is

automatically reenabled at the next wakeup event.

Four pins are associated with the boost converter: Vbat, Vssb,

Vboost, and Ind. The boosted output voltage is sensed at the

Vboost pin and must be connected directly to the chip’s supply

inputs. An inductor is connected between the Vbat and Ind pins.

You can optimize the inductor value to increase the boost

converter efficiency based on input voltage, output voltage,

current and switching frequency. The external Schottky diode

shown in Figure 6-6 is required only in cases when Vboost >

3.6 V.

When a wakeup event occurs, the global mode is always

returned to active, and the CPU is automatically enabled,

regardless of its template settings. Active mode is the default

global power mode upon boot.

6.2.1.2 Alternate Active Mode

Figure 6-6. Application for Boost Converter

Alternate Active mode is very similar to Active mode. In alternate

active mode, fewer subsystems are enabled, to reduce power

consumption. One possible configuration is to turn off the CPU

and flash, and run peripherals at full speed.

Vdda Vddd Vddio

Vboost

Ind

Optional

Schottky Diode

Only required

Vboost>3.6 V

6.2.1.3 Sleep Mode

Sleep mode reduces power consumption when a resume time of

15 µs is acceptable. The wake time is used to ensure that the

regulator outputs are stable enough to directly enter active

mode.

22 µF 0. 1µF

PSoC

10 µH

22µF

SMP

6.2.1.4 Hibernate Mode

Vbat

Vssb

In hibernate mode nearly all of the internal functions are

disabled. Internal voltages are reduced to the minimal level to

keep vital systems alive. Configuration state is preserved in

hibernate mode and SRAM memory is retained. GPIOs

configured as digital outputs maintain their previous values and

external GPIO pin interrupt settings are preserved. The device

can only return from hibernate mode in response to an external

I/O interrupt. The resume time from hibernate mode is less than

100 µs.

Vssa

Vssd

The switching frequency can be set to 100 kHz, 400 kHz, 2 MHz,

or 32 kHz to optimize efficiency and component cost. The

100 kHz, 400 kHz, and 2 MHz switching frequencies are

generated using oscillators internal to the boost converter block.

When the 32-kHz switching frequency is selected, the clock is

derived from a 32 kHz external crystal oscillator. The 32-kHz

external clock is primarily intended for boost standby mode.

6.2.1.5 Wakeup Events

Wakeup events are configurable and can come from an interrupt

or device reset. A wakeup event restores the system to active

mode. Firmware enabled interrupt sources include internally

generated interrupts, power supervisor, central timewheel, and

I/O interrupts. Internal interrupt sources can come from a variety

of peripherals, such as analog comparators and UDBs. The

At 2 MHz the Vboost output is limited to 2 × Vbat, and at 400 kHz

Vboost is limited to 4 × Vbat.

The boost converter can be operated in two different modes:

active and standby. Active mode is the normal mode of operation

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PSoC^®3: CY8C36 Family

Data Sheet

where the boost regulator actively generates a regulated output

voltage. In standby mode, most boost functions are disabled,

thus reducing power consumption of the boost circuit. The

converter can be configured to provide low-power, low-current

regulation in the standby mode. The external 32 kHz crystal can

be used to generate inductor boost pulses on the rising and

falling edge of the clock when the output voltage is less than the

programmed value. This is called automatic thump mode (ATM).

Figure 6-7. Resets

Vddd Vdda

Power

Voltage

Level

Processor

Interrupt

Monitors

The boost typically draws 200 µA in active mode and 12 µA in

standby mode. The boost operating modes must be used in

conjunction with chip power modes to minimize the total chip

power consumption. Table 6-4 lists the boost power modes

available in different chip power modes.

Reset

External

Reset

Controller

System

Reset

Table 6-4. Chip and Boost Power Modes Compatibility

Watchdog

Timer

Chip Power Modes

Boost Power Modes

Chip – Active mode

Boost can be operated in either active

or standby mode.

Software

Reset

Register

Chip – Sleep mode

Boost can be operated in either active

or standby mode. However, it is recom-

mended to operate boost in standby

mode for low-power consumption

Chip – Hibernate mode Boost can only be operated in active

mode. However, it is recommended not

to use boost in chip hibernate mode

due to high current consumption in

boost active mode

The term device reset indicates that the processor as well as

analog and digital peripherals and registers are reset.

A reset status register holds the source of the most recent reset

or power voltage monitoring interrupt. The program may

examine this register to detect and report exception conditions.

This register is cleared after a power on reset.

If the boost converter is not used in a given application, tie the

Vbat, Vssb, and Vboost pins to ground and leave the Ind pin

unconnected.

6.3.1 Reset Sources

6.3.1.1 Power Voltage Level Monitors

IPOR – Initial POR

6.3 Reset

CY8C36 has multiple internal and external reset sources

available. The reset sources are:

At initial power on, IPOR monitors the power voltages Vddd

and Vdda, both directly at the pins and at the outputs of the

corresponding internal regulators. The trip level is not precise.

It is set to approximately 1 volt, which is below the lowest

specified operating voltage but high enough for the internal

circuits to be reset and to hold their reset state. The monitor

generates a reset pulse that is at least 100 ns wide. It may be

much wider if one or more of the voltages ramps up slowly.

Power source monitoring – The analog and digital power

voltages, Vdda, Vddd, Vcca, and Vccd are monitored in several

different modes during power up, active mode, and sleep mode

(buzzing). If any of the voltages goes outside predetermined

ranges then a reset is generated. The monitors are

programmable to generate an interrupt to the processor under

To save power the IPOR circuit is disabled when the internal

digital supply is stable. Voltage supervision is then handed off

to the precise low voltage reset (PRES) circuit. When the

voltage is high enough for PRES to release, the IMO starts.

certain conditions before reaching the reset thresholds.

External – The device can be reset from an external source by

pulling the reset pin (XRES) low. The XRES pin includes an

internal pull-up to Vddio1. Vddd, Vdda, and Vddio1 must all

have voltage applied before the part comes out of reset.

PRES – Precise Low Voltage Reset

This circuit monitors the outputs of the analog and digital

internal regulators after power up. The regulator outputs are

compared to a precise reference voltage. The response to a

PRES trip is identical to an IPOR reset.

Watchdog timer – A watchdog timer monitors the execution of

instructions by the processor. If the watchdog timer is not reset

by firmware within a certain period of time, the watchdog timer

generates a reset.

In normal operating mode, the program cannot disable the

digital PRES circuit. The analog regulator can be disabled,

which also disables the analog portion of the PRES. The PRES

circuit is disabled automatically during sleep and hibernate

modes, with one exception: During sleep mode the regulators

are periodically activated (buzzed) to provide supervisory

services and to reduce wakeup time. At these times the PRES

circuit is also buzzed to allow periodic voltage monitoring.

Software – The device can be reset under program control.

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Page 31 of 126

PSoC^®3: CY8C36 Family

Data Sheet

ALVI, DLVI, AHVI – Analog/Digital Low Voltage Interrupt,

Analog High Voltage Interrupt

6.4 I/O System and Routing

PSoC I/Os are extremely flexible. Every GPIO has analog and

digital I/O capability. All I/Os have a large number of drive modes,

which are set at POR. PSoC also provides up to four individual

I/O voltage domains through the Vddio pins.

Interrupt circuits are available to detect when Vdda and Vddd

go outside a voltage range. For AHVI, Vdda is compared to a

fixed trip level. For ALVI and DLVI, Vdda and Vddd are

compared to trip levels that are programmable, as listed in

Table 6-5. ALVI and DLVI can also be configured to generate

a device reset instead of an interrupt.

There are two types of I/O pins on every device; those with USB

provide a third type. Both General Purpose I/O (GPIO) and

Special I/O (SIO) provide similar digital functionality. The primary

differences are their analog capability and drive strength.

Devices that include USB also provide two USBIO pins that

support specific USB functionality as well as limited GPIO

capability.

Table 6-5. Analog/Digital Low Voltage Interrupt, Analog High

Voltage Interrupt

Normal

Voltage

Range

Available Trip

Interrupt Supply

Accuracy

Settings

All I/O pins are available for use as digital inputs and outputs for

both the CPU and digital peripherals. In addition, all I/O pins can

generate an interrupt. The flexible and advanced capabilities of

the PSoC I/O, combined with any signal to any pin routability,

greatly simplify circuit design and board layout. All GPIO pins can

be used for analog input, CapSense^[17], and LCD segment drive,

while SIO pins are used for voltages in excess of V_DDAand for

programmable output voltages.

DLVI

ALVI

AHVI

Vddd 1.71 V–5.5 V 1.70V–5.45 Vin

±2%

250 mV

increments

Vdda 1.71 V–5.5 V 1.70V–5.45 Vin

±2%

250 mV

increments

Vdda 1.71 V–5.5 V 5.75 V

Features supported by both GPIO and SIO:

User programmable port reset state

The monitors are disabled until after IPOR. During sleep mode

these circuits are periodically activated (buzzed). If an interrupt

occurs during buzzing then the system first enters its wake up

sequence. The interrupt is then recognized and may be

serviced.

SeparateI/OsuppliesandvoltagesforuptofourgroupsofI/O

Digital peripherals use DSI to connect the pins

Input or output or both for CPU and DMA

Eight drive modes

Every pin can be an interrupt source configured as rising

edge, falling edge or both edges. If required, level sensitive

interrupts are supported through the DSI

Dedicated port interrupt vector for each port

Slew rate controlled digital output drive mode

Access port control and configuration registers on either port

basis or pin basis

Separateportread(PS)andwrite(DR)dataregisterstoavoid

read modify write errors

Special functionality on a pin by pin basis

Additional features only provided on the GPIO pins:

LCD segment drive on LCD equipped devices

CapSense^[17]

Analog input and output capability

Continuous 100 µA clamp current capability

6.3.1.2 Other Reset Sources

XRES – External Reset

PSoC 3 has either a single GPIO pin that is configured as an

external reset or a dedicated XRES pin. Either the dedicated

XRES pin or the GPIO pin, if configured, holds the part in reset

while held active (low). The response to an XRES is the same

as to an IPOR reset.

The external reset is active low. It includes an internal pull-up

resistor. XRES is active during sleep and hibernate modes.

SRES – Software Reset

A reset can be commanded under program control by setting

a bit in the software reset register. This is done either directly

by the program or indirectly by DMA access. The response to

a SRES is the same as after an IPOR reset.

Another register bit exists to disable this function.

Standard drive strength down to 1.7 V

WRES – Watchdog Timer Reset

Additional features only provided on SIO pins:

Higher drive strength than GPIO

Hot swap capability (5 V tolerance at any operating V_DD

Programmable and regulated high input and output drive

levels down to 1.2 V

No analog input, CapSense, or LCD capability

Over voltage tolerance up to 5.5 V

SIO can act as a general purpose analog comparator

USBIO features:

Full speed USB 2.0 compliant I/O

The watchdog reset detects when the software program is no

longer being executed correctly. To indicate to the watchdog

timer that it is running correctly, the program must periodically

reset the timer. If the timer is not reset before a user-specified

amount of time, then a reset is generated.

)

Note IPOR disables the watchdog function. The program must

enable the watchdog function at an appropriate point in the

code by setting a register bit. When this bit is set, it cannot be

cleared again except by an IPOR power on reset event.

Highest drive strength for general purpose use

Input, output, or both for CPU and DMA

Input, output, or both for digital peripherals

Digital output (CMOS) drive mode

Each pin can be an interrupt source configured as rising

edge, falling edge, or both edges

Note

17. GPIOs with opamp outputs are not recommended for use with CapSense

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Page 32 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Figure 6-8. GPIO Block Diagram

Digital Input Path

Naming Convention

PRT[x]CTL

PRT[x]DBL_SYNC_IN

‘x’ = Port Number

‘y’ = Pin Number

PRT[x]PS

Digital System Input

PICU[x]INTTYPE[y]

PICU[x]INTSTAT

Pin Interrupt Signal

PICU[x]INTSTAT

Input Buffer Disable

Interrupt

Logic

Digital Output Path

PRT[x]SLW

PRT[x]SYNC_OUT

Vddio Vddio

PRT[x]DR

0

1

In

Digital System Output

PRT[x]BYP

Vddio

Drive

Logic

PRT[x]DM2

PRT[x]DM1

PRT[x]DM0

Slew

Cntl

Bidirectional Control

PRT[x]BIE

OE

Analog

1

0

1

0

1

Capsense Global Control

CAPS[x]CFG1

Switches

PRT[x]AG

Analog Global Enable

PRT[x]AMUX

Analog Mux Enable

LCD

Display

Data

Logic & MUX

PRT[x]LCD_COM_SEG

PRT[x]LCD_EN

LCD Bias Bus

5

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Page 33 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Figure 6-9. SIO Input/Output Block Diagram

Digital Input Path

Naming Convention

‘x’ = Port Number

‘y’ = Pin Number

PRT[x]SIO_HYST_EN

PRT[x]SIO_DIFF

Buffer

Thresholds

Reference Level

PRT[x]DBL_SYNC_IN

PRT[x]PS

Digital System Input

PICU[x]INTTYPE[y]

PICU[x]INTSTAT

Pin Interrupt Signal

PICU[x]INTSTAT

Input Buffer Disable

Interrupt

Logic

Digital Output Path

Reference Level

PRT[x]SIO_CFG

PRT[x]SLW

Driver

Vhigh

PRT[x]SYNC_OUT

PRT[x]DR

0

1

In

Digital System Output

PRT[x]BYP

Drive

Logic

PRT[x]DM2

PRT[x]DM1

PRT[x]DM0

Slew

Cntl

Bidirectional Control

PRT[x]BIE

OE

Figure 6-10. USBIO Block Diagram

Digital Input Path

Naming Convention

‘x’ = Port Number

‘y’ = Pin Number

USB Receiver Circuitry

PRT[x]DBL_SYNC_IN

USBIO_CR1[0,1]

Digital System Input

PICU[x]INTTYPE[y]

PICU[x]INTSTAT

Pin Interrupt Signal

PICU[x]INTSTAT

Interrupt

Logic

Digital Output Path

PRT[x]SYNC_OUT

USBIO_CR1[7]

D+ pin only

Vddd Vddd

USB or I/O

Vddd

5 k

USB SIE Control for USB Mode

Vddd

USBIO_CR1[4,5]

Digital System Output

PRT[x]BYP

0

1

In

Drive

1.5 k

Logic

USBIO_CR1[2]

USBIO_CR1[3]

USBIO_CR1[6]

D+ 1.5 k

D+D- 5 k

Open Drain

Document Number: 001-53413 Rev. *L

Page 34 of 126

PSoC^®3: CY8C36 Family

Data Sheet

6.4.1 Drive Modes

Each GPIO and SIO pin is individually configurable into one of the eight drive modes listed in Table 6-6. Three configuration bits are

used for each pin (DM[2:0]) and set in the PRTxDM[2:0] registers. Figure 6-11 depicts a simplified pin view based on each of the eight

drive modes. Table 6-6 shows the I/O pin’s drive state based on the port data register value or digital array signal if bypass mode is

selected. Note that the actual I/O pin voltage is determined by a combination of the selected drive mode and the load at the pin. For

example, if a GPIO pin is configured for resistive pull-up mode and driven high while the pin is floating, the voltage measured at the

pin is a high logic state. If the same GPIO pin is externally tied to ground then the voltage unmeasured at the pin is a low logic state.

Figure 6-11. Drive Mode

Vddio

DR

PS

DR

PS

DR

PS

DR

PS

0. High Impedance 1. High Impedance

Analog Digital

2. Resistive

Pull-Up

3. Resistive

Pull-Down

Vddio

DR

PS

DR

PS

DR

PS

DR

PS

4. Open Drain,

Drives Low

5. Open Drain,

Drives High

6. Strong Drive

7. Resistive

Pull-Up and Pull-Down

Table 6-6. Drive Modes

Diagram

Drive Mode

PRTxDM2

PRTxDM1

PRTxDM0

PRTxDR = 1

PRTxDR = 0

High Z

0

1

2

3

4

5

6

7

High impedence analog

High Impedance digital

Resistive pull-up^[18]

Resistive pull-down^[18]

Open drain, drives low

Open drain, drive high

Strong drive

0

1

0

1

0

1

0

1

0

1

0

1

0

1

High Z

Res High (5K)

Strong High

High Z

Strong Low

Res Low (5K)

Strong Low

High Z

Strong High

Res High (5K)

Strong Low

Res Low (5K)

Resistive pull-up and pull-down^[18]

Note

18. Resistive pull-up and pull-down are not available with SIO in regulated output mode.

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Page 35 of 126

PSoC^®3: CY8C36 Family

Data Sheet

High Impedance Analog

second user selected drive mode such as strong drive (set using

PRT×DM[2:0] registers) for output signals on the same pin,

based on the state of an auxiliary control bus signal. The

bidirectional capability is useful for processor busses and

communications interfaces such as the SPI Slave MISO pin that

requires dynamic hardware control of the output buffer.

The default reset state with both the output driver and digital

input buffer turned off. This prevents any current from flowing

in the I/O’s digital input buffer due to a floating voltage. This

state is recommended for pins that are floating or that support

an analog voltage. High impedance analog pins do not provide

digital input functionality.

The auxiliary control bus routes up to 16 UDB or digital peripheral

generated output enable signals to one or more pins.

To achieve the lowest chip current in sleep modes, all I/Os

must either be configured to the high impedance analog mode,

or have their pins driven to a power supply rail by the PSoC

device or by external circuitry.

6.4.4 Slew Rate Limited Mode

GPIO and SIO pins have fast and slow output slew rate options

for strong and open drain drive modes, not resistive drive modes.

Because it results in reduced EMI, the slow edge rate option is

recommended for signals that are not speed critical, generally

less than 1 MHz. The fast slew rate is for signals between 1 MHz

and 33 MHz. The slew rate is individually configurable for each

pin, and is set by the PRT×SLW registers.

High Impedance Digital

The input buffer is enabled for digital signal input. This is the

standard high impedance (HiZ) state recommended for digital

inputs.

Resistive pull-up or resistive pull-down

6.4.5 Pin Interrupts

Resistive pull-up or pull-down, respectively, provides a series

resistance in one of the data states and strong drive in the

other. Pins can be used for digital input and output in these

modes. Interfacing to mechanical switches is a common

application for these modes. Resistive pull-up and pull-down

are not available with SIO in regulated output mode.

All GPIO and SIO pins are able to generate interrupts to the

system. All eight pins in each port interface to their own Port

Interrupt Control Unit (PICU) and associated interrupt vector.

Each pin of the port is independently configurable to detect rising

edge, falling edge, both edge interrupts, or to not generate an

interrupt.

Open Drain, Drives High and Open Drain, Drives Low

Depending on the configured mode for each pin, each time an

interrupt event occurs on a pin, its corresponding status bit of the

interrupt status register is set to “1” and an interrupt request is

sent to the interrupt controller. Each PICU has its own interrupt

vector in the interrupt controller and the pin status register

providing easy determination of the interrupt source down to the

pin level.

Open drain modes provide high impedance in one of the data

states and strong drive in the other. Pins can be used for digital

input and output in these modes. A common application for

these modes is driving the I²C bus signal lines.

Strong Drive

Provides a strong CMOS output drive in either high or low

state. This is the standard output mode for pins. Strong Drive

mode pins must not be used as inputs under normal

circumstances. This mode is often used to drive digital output

signals or external FETs.

Port pin interrupts remain active in all sleep modes allowing the

PSoC device to wake from an externally generated interrupt.

While level sensitive interrupts are not directly supported;

universal digital blocks (UDB) provide this functionality to the

system when needed.

Resistive pull-up and pull-down

Similar to the resistive pull-up and resistive pull-down modes

except the pin is always in series with a resistor. The high data

state is pull-up while the low data state is pull-down. This mode

is most often used when other signals that may cause shorts

can drive the bus. Resistive pull-up and pull-down are not

available with SIO in regulated output mode.

6.4.6 Input Buffer Mode

GPIO and SIO input buffers can be configured at the port level

for the default CMOS input thresholds or the optional LVTTL

input thresholds. All input buffers incorporate Schmitt triggers for

input hysteresis. Additionally, individual pin input buffers can be

disabled in any drive mode.

6.4.2 Pin Registers

6.4.7 I/O Power Supplies

Registers to configure and interact with pins come in two forms

that may be used interchangeably.

Up to four I/O pin power supplies are provided depending on the

device and package. Each I/O supply must be less than or equal

to the voltage on the chip’s analog (V_DDA) pin. This feature allows

users to provide different I/O voltage levels for different pins on

the device. Refer to the specific device package pinout to

determine Vddio capability for a given port and pin.

All I/O registers are available in the standard port form, where

each bit of the register corresponds to one of the port pins. This

register form is efficient for quickly reconfiguring multiple port

pins at the same time.

I/O registers are also available in pin form, which combines the

eight most commonly used port register bits into a single register

for each pin. This enables very fast configuration changes to

individual pins with a single register write.

The SIO port pins support an additional regulated high output

capability, as described in Adjustable Output Level.

6.4.8 Analog Connections

These connections apply only to GPIO pins. All GPIO pins may

be used as analog inputs or outputs. The analog voltage present

on the pin must not exceed the Vddio supply voltage to which the

GPIO belongs. Each GPIO may connect to one of the analog

6.4.3 Bidirectional Mode

High speed bidirectional capability allows pins to provide both

the high impedance digital drive mode for input signals and a

Document Number: 001-53413 Rev. *L

Page 36 of 126

PSoC^®3: CY8C36 Family

Data Sheet

global busses or to one of the analog mux buses to connect any

pin to any internal analog resource such as ADC or comparators.

In addition, select pins provide direct connections to specific

analog features such as the high current DACs or uncommitted

opamps.

Figure 6-12. SIO Reference for Input and Output

Input Path

Digital

Input

6.4.9 CapSense

Vinref

This section applies only to GPIO pins. All GPIO pins may be

used to create CapSense buttons and sliders^[19]. See the

“CapSense” section on page 57 for more information.

6.4.10 LCD Segment Drive

Reference

Generator

SIO_Ref

This section applies only to GPIO pins. All GPIO pins may be

used to generate Segment and Common drive signals for direct

glass drive of LCD glass. See the “LCD Direct Drive” section on

page 56 for details.

Voutref

Output Path

Driver

Vhigh

6.4.11 Adjustable Output Level

This section applies only to SIO pins. SIO port pins support the

ability to provide a regulated high output level for interface to

external signals that are lower in voltage than the SIO’s

respective Vddio. SIO pins are individually configurable to output

either the standard Vddio level or the regulated output, which is

based on an internally generated reference. Typically a voltage

DAC (VDAC) is used to generate the reference (see Figure

6-12). The “DAC” section on page 57 has more details on VDAC

use and reference routing to the SIO pins. Resistive pull-up and

pull-down drive modes are not available with SIO in regulated

output mode.

Digital

Output

Drive

Logic

6.4.12 Adjustable Input Level

6.4.13 SIO as Comparator

This section applies only to SIO pins. SIO pins by default support

the standard CMOS and LVTTL input levels but also support a

differential mode with programmable levels. SIO pins are

grouped into pairs. Each pair shares a reference generator block

which, is used to set the digital input buffer reference level for

interface to external signals that differ in voltage from Vddio. The

reference sets the pins voltage threshold for a high logic level

(see Figure 6-12). Available input thresholds are:

This section applies only to SIO pins. The adjustable input level

feature of the SIOs as explained in the Adjustable Input Level

section can be used to construct a comparator. The threshold for

the comparator is provided by the SIO's reference generator. The

reference generator has the option to set the analog signal

routed through the analog global line as threshold for the

comparator. Note that a pair of SIO pins share the same

threshold.

0.5 × Vddio

0.4 × Vddio

0.5 × V_REF

V_REF

The digital input path in Figure 6-9 on page 34 illustrates this

functionality. In the figure, ‘Reference level’ is the analog signal

routed through the analog global. The hysteresis feature can

also be enabled for the input buffer of the SIO, which increases

noise immunity for the comparator.

Typically a voltage DAC (VDAC) generates the V_REFreference.

“DAC” section on page 57 has more details on VDAC use and

reference routing to the SIO pins.

6.4.14 Hot Swap

This section applies only to SIO pins. SIO pins support ‘hot swap’

capability to plug into an application without loading the signals

that are connected to the SIO pins even when no power is

applied to the PSoC device. This allows the unpowered PSoC to

maintain a high impedance load to the external device while also

preventing the PSoC from being powered through a GPIO pin’s

protection diode.

Note

19. GPIOs with opamp outputs are not recommended for use with CapSense

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PSoC^®3: CY8C36 Family

Data Sheet

6.4.15 Over Voltage Tolerance

High current IDAC outputs

External reference inputs

All I/O pins provide an over voltage tolerance feature at any

operating V_DD

.

6.4.19 JTAG Boundary Scan

There are no current limitations for the SIO pins as they present a

The device supports standard JTAG boundary scan chains on all

I/O pins for board level test.

high impedance load to the external circuit where Vddio < V_IN

5.5 V.

<

7. Digital Subsystem

TheGPIOpinsmustbelimitedto100µAusingacurrentlimiting

resistor. GPIO pins clamp the pin voltage to approximately one

The digital programmable system creates application specific

combinations of both standard and advanced digital peripherals

and custom logic functions. These peripherals and logic are then

interconnected to each other and to any pin on the device,

providing a high level of design flexibility and IP security.

diode above the Vddio supply where Vddio < V_IN< V_DDA

.

In case of a GPIO pin configured for analog input/output, the

analog voltage on the pin must not exceed the Vddio supply

voltage to which the GPIO belongs.

A common application for this feature is connection to a bus such

as I²C where different devices are running from different supply

voltages. In the I²C case, the PSoC chip is configured into the

Open Drain, Drives Low mode for the SIO pin. This allows an

external pull-up to pull the I²C bus voltage above the PSoC pin

supply. For example, the PSoC chip could operate at 1.8 V, and

an external device could run from 5 V. Note that the SIO pin’s V_IH

and V_ILlevels are determined by the associated Vddio supply

pin.

The features of the digital programmable system are outlined

here to provide an overview of capabilities and architecture. You

do not need to interact directly with the programmable digital

system at the hardware and register level. PSoC Creator

provides a high level schematic capture graphical interface to

automatically place and route resources similar to PLDs.

The main components of the digital programmable system are:

Universal Digital Blocks (UDB) – These form the core

functionality of the digital programmable system. UDBs are a

collection of uncommitted logic (PLD) and structural logic

(Datapath) optimized to create all common embedded

peripherals and customized functionality that are application or

design specific.

The I/O pin must be configured into a high impedance drive

mode, open drain low drive mode, or pull-down drive mode, for

over voltage tolerance to work properly. Absolute maximum

ratings for the device must be observed for all I/O pins.

6.4.16 Reset Configuration

Universal Digital Block Array – UDB blocks are arrayed within

a matrix of programmable interconnect. The UDB array

structure is homogeneous and allows for flexible mapping of

digital functions onto the array. The array supports extensive

and flexible routing interconnects between UDBs and the

Digital System Interconnect.

While reset is active all I/Os are reset to and held in the High

Impedance Analog state. After reset is released, the state can be

reprogrammed on a port-by-port basis to pull-down or pull-up. To

ensure correct reset operation, the port reset configuration data

is stored in special nonvolatile registers. The stored reset data is

automatically transferred to the port reset configuration registers

at reset release.

Digital System Interconnect (DSI) – Digital signals from

Universal Digital Blocks (UDBs), fixed function peripherals, I/O

pins, interrupts, DMA, and other system core signals are

attached to the Digital System Interconnect to implement full

featureddeviceconnectivity.TheDSIallowsanydigitalfunction

to any pin or other feature routability when used with the

Universal Digital Block Array.

6.4.17 Low-Power Functionality

In all low-power modes the I/O pins retain their state until the part

is awakened and changed or reset. To awaken the part, use a

pin interrupt, because the port interrupt logic continues to

function in all low-power modes.

Figure 7-1. CY8C36 Digital Programmable Architecture

6.4.18 Special Pin Functionality

Some pins on the device include additional special functionality

in addition to their GPIO or SIO functionality. The specific special

function pins are listed in Pinouts on page 5. The special features

are:

Digital Core System

and Fixed Function Peripherals

DSI Routing Interface

Digital

UDB

4- to 25-MHz crystal oscillator

32.768-kHz crystal oscillator

Wake from sleep on I²C address match. Any pin can be used

for I²C if wake from sleep is not required.

JTAG interface pins

SWD interface pins

SWV interface pins

External reset

DSI Routing Interface

Analog

Digital Core System

and Fixed Function Peripherals

Opamp inputs and outputs

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PSoC^®3: CY8C36 Family

Data Sheet

Voltage

PWM

7.1 Example Peripherals

The flexibility of the CY8C36 family’s Universal Digital Blocks

(UDBs) and Analog Blocks allow the user to create a wide range

of components (peripherals). The most common peripherals

were built and characterized by Cypress and are shown in the

PSoC Creator component catalog, however, users may also

create their own custom components using PSoC Creator. Using

PSoC Creator, users may also create their own components for

reuse within their organization, for example sensor interfaces,

proprietary algorithms, and display interfaces.

Comparators

Mixers

7.1.3 Example System Function Components

The following is a sample of the system function components

available in PSoC Creator for the CY8C36 family. The exact

amount of hardware resources (UDBs, DFB taps, SC/CT blocks,

routing, RAM, flash) used by a component varies with the

features selected in PSoC Creator for the component.

The number of components available through PSoC Creator is

too numerous to list in the data sheet, and the list is always

growing. An example of a component available for use in

CY8C36 family, but, not explicitly called out in this data sheet is

the UART component.

CapSense

LCD Drive

LCD Control

Filters

7.1.1 Example Digital Components

The following is a sample of the digital components available in

PSoC Creator for the CY8C36 family. The exact amount of

hardware resources (UDBs, routing, RAM, flash) used by a

component varies with the features selected in PSoC Creator for

the component.

7.1.4 Designing with PSoC Creator

7.1.4.1 More Than a Typical IDE

A successful design tool allows for the rapid development and

deployment of both simple and complex designs. It reduces or

eliminates any learning curve. It makes the integration of a new

design into the production stream straightforward.

Communications

I²C

UART

PSoC Creator is that design tool.

SPI

PSoC Creator is a full featured Integrated Development

Environment (IDE) for hardware and software design. It is

optimized specifically for PSoC devices and combines a modern,

powerful software development platform with a sophisticated

graphical design tool. This unique combination of tools makes

PSoC Creator the most flexible embedded design platform

available.

Functions

EMIF

PWMs

Timers

Counters

Logic

NOT

OR

XOR

AND

Graphical design entry simplifies the task of configuring a

particular part. You can select the required functionality from an

extensive catalog of components and place it in your design. All

components are parameterized and have an editor dialog that

allows you to tailor functionality to your needs.

7.1.2 Example Analog Components

PSoC Creator automatically configures clocks and routes the I/O

to the selected pins and then generates APIs to give the

application complete control over the hardware. Changing the

PSoC device configuration is as simple as adding a new

component, setting its parameters, and rebuilding the project.

The following is a sample of the analog components available in

PSoC Creator for the CY8C36 family. The exact amount of

hardware resources (SC/CT blocks, routing, RAM, flash) used

by a component varies with the features selected in PSoC

Creator for the component.

At any stage of development you are free to change the

hardware configuration and even the target processor. To

retarget your application (hardware and software) to new

devices, even from 8- to 32-bit families, just select the new

device and rebuild.

Amplifiers

TIA

PGA

opamp

You also have the ability to change the C compiler and evaluate

an alternative. Components are designed for portability and are

validated against all devices, from all families, and against all

supported tool chains. Switching compilers is as easy as editing

the from the project options and rebuilding the application with

no errors from the generated APIs or boot code.

ADC

Delta-Sigma

DACs

Current

Document Number: 001-53413 Rev. *L

Page 39 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Figure 7-2. PSoC Creator Framework

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Page 40 of 126

PSoC^®3: CY8C36 Family

Data Sheet

7.1.4.2 Component Catalog

7.1.4.4 Software Development

Figure 7-3. Component Catalog

Figure 7-4. Code Editor

Anchoring the tool is a modern, highly customizable user

interface. It includes project management and integrated editors

for C and assembler source code, as well the design entry tools.

Project build control leverages compiler technology from top

commercial vendors such as ARM^®Limited, Keil™, and

CodeSourcery (GNU). Free versions of Keil C51 and GNU C

Compiler (GCC) for ARM, with no restrictions on code size or end

product distribution, are included with the tool distribution.

Upgrading to more optimizing compilers is a snap with support

for the professional Keil C51 product and ARM RealView™

compiler.

The component catalog is a repository of reusable design

elements that select device functionality and customize your

PSoC device. It is populated with an impressive selection of

content; from simple primitives such as logic gates and device

registers, through the digital timers, counters and PWMs, plus

analog components such as ADC, DACs, and filters, and

communication protocols, such as I²C, USB, and CAN. See

Example Peripherals on page 39 for more details about available

peripherals. All content is fully characterized and carefully

documented in data sheets with code examples, AC/DC

specifications, and user code ready APIs.

7.1.4.5 Nonintrusive Debugging

Figure 7-5. PSoC Creator Debugger

7.1.4.3 Design Reuse

The symbol editor gives you the ability to develop reusable

components that can significantly reduce future design time. Just

draw a symbol and associate that symbol with your proven

design. PSoC Creator allows for the placement of the new

symbol anywhere in the component catalog along with the

content provided by Cypress. You can then reuse your content

as many times as you want, and in any number of projects,

without ever having to revisit the details of the implementation.

With JTAG (4-wire) and SWD (2-wire) debug connectivity

available on all devices, the PSoC Creator debugger offers full

control over the target device with minimum intrusion.

Breakpoints and code execution commands are all readily

available from toolbar buttons and an impressive lineup of

windows—register, locals, watch, call stack, memory and

peripherals—make for an unparalleled level of visibility into the

system.

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PSoC^®3: CY8C36 Family

Data Sheet

PSoC Creator contains all the tools necessary to complete a

design, and then to maintain and extend that design for years to

come. All steps of the design flow are carefully integrated and

optimized for ease-of-use and to maximize productivity.

Status and control module – The primary role of this block is to

provide a way for CPU firmware to interact and synchronize

with UDB operation.

Clock and reset module – This block provides the UDB clocks

and reset selection and control.

7.2 Universal Digital Block

The universal digital block (UDB) represents an evolutionary

step to the next generation of PSoC embedded digital peripheral

functionality. The architecture in first generation PSoC digital

blocks provides coarse programmability in which a few fixed

functions with a small number of options are available. The new

UDB architecture is the optimal balance between configuration

granularity and efficient implementation. A cornerstone of this

approach is to provide the ability to customize the devices digital

operation to match application requirements.

7.2.1 PLD Module

The primary purpose of the PLD blocks is to implement logic

expressions, state machines, sequencers, lookup tables, and

decoders. In the simplest use model, consider the PLD blocks as

a standalone resource onto which general purpose RTL is

synthesized and mapped. The more common and efficient use

model is to create digital functions from a combination of PLD

and datapath blocks, where the PLD implements only the

random logic and state portion of the function while the datapath

(ALU) implements the more structured elements.

To achieve this, UDBs consist of a combination of uncommitted

logic (PLD), structured logic (Datapath), and a flexible routing

scheme to provide interconnect between these elements, I/O

connections, and other peripherals. UDB functionality ranges

from simple self contained functions that are implemented in one

UDB, or even a portion of a UDB (unused resources are

available for other functions), to more complex functions that

require multiple UDBs. Examples of basic functions are timers,

counters, CRC generators, PWMs, dead band generators, and

communications functions, such as UARTs, SPI, and I²C. Also,

the PLD blocks and connectivity provide full featured general

purpose programmable logic within the limits of the available

resources.

Figure 7-7. PLD 12C4 Structure

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

IN9

IN10

IN11

T C T C T C T C T C T C T C T C

AND

Array

Figure 7-6. UDB Block Diagram

PLD

Chaining

SELIN

(carry in)

PLD

12C4

(8 PTs)

PLD

12C4

(8 PTs)

Clock

and Reset

Control

OUT0

OUT1

OUT2

OUT3

MC0

MC1

MC2

MC3

T

Status and

Control

Datapath

Chaining

SELOUT

(carry out)

OR

Array

One 12C4 PLD block is shown in Figure 7-7. This PLD has 12

inputs, which feed across eight product terms. Each product term

(AND function) can be from 1 to 12 inputs wide, and in a given

product term, the true (T) or complement (C) of each input can

be selected. The product terms are summed (OR function) to

create the PLD outputs. A sum can be from 1 to 8 product terms

wide. The 'C' in 12C4 indicates that the width of the OR gate (in

this case 8) is constant across all outputs (rather than variable

as in a 22V10 device). This PLA like structure gives maximum

flexibility and insures that all inputs and outputs are permutable

for ease of allocation by the software tools. There are two 12C4

PLDs in each UDB.

Routing Channel

The main component blocks of the UDB are:

PLD blocks – There are two small PLDs per UDB. Theseblocks

take inputs from the routing array and form registered or

combinational sum-of-products logic. PLDs are used to

implement state machines, state bits, and combinational logic

equations. PLD configuration is automatically generated from

graphical primitives.

Datapathmodule–This8-bitwidedatapathcontainsstructured

logic to implement a dynamically configurable ALU, a variety

ofcompare configurations andconditiongeneration. Thisblock

alsocontainsinput/outputFIFOs, whicharetheprimaryparallel

data interface between the CPU/DMA system and the UDB.

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PSoC^®3: CY8C36 Family

Data Sheet

7.2.2 Datapath Module

The datapath contains an 8-bit single cycle ALU, with associated compare and condition generation logic. This datapath block is

optimized to implement embedded functions, such as timers, counters, integrators, PWMs, PRS, CRC, shifters and dead band

generators and many others.

Figure 7-8. Datapath Top Level

PHUB System Bus

R/W Access to All

Registers

F1

FIFOs

Output

Muxes

Input

Muxes

F0

A0

A1

D0

D1

Input from

Programmable

Routing

Output to

Programmable

Routing

6

D1

Data Registers

D0

To/From

Chaining

A1

Accumulators

A0

PI

Parallel Input/Output

(To/From Programmable Routing)

PO

ALU

Shift

Mask

7.2.2.1 Working Registers

7.2.2.2 Dynamic Datapath Configuration RAM

Dynamic configuration is the ability to change the datapath

function and internal configuration on a cycle-by-cycle basis,

under sequencer control. This is implemented using the

8-word × 16-bit configuration RAM, which stores eight unique

16-bit wide configurations. The address input to this RAM

controls the sequence, and can be routed from any block

connected to the UDB routing matrix, most typically PLD logic,

I/O pins, or from the outputs of this or other datapath blocks.

The datapath contains six primary working registers, which are

accessed by CPU firmware or DMA during normal operation.

Table 7-1. Working Datapath Registers

Name

Function

Description

A0 and A1 Accumulators

These are sources and sinks for

the ALU and also sources for the

compares.

ALU

D0 and D1 Data Registers These are sources for the ALU

and sources for the compares.

The ALU performs eight general purpose functions. They are:

Increment

Decrement

Add

F0 and F1 FIFOs

These are the primary interface

to the system bus. They can be a

data source for the data registers

and accumulators or they can

capture data from the

Subtract

Logical AND

Logical OR

Logical XOR

accumulatorsorALU. EachFIFO

is four bytes deep.

Pass, used to pass a value through the ALU to the shift register,

mask, or another UDB register

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PSoC^®3: CY8C36 Family

Data Sheet

Independent of the ALU operation, these functions are available:

7.2.2.8 Time Multiplexing

In applications that are over sampled, or do not need high clock

rates, the single ALU block in the datapath can be efficiently

shared with two sets of registers and condition generators. Carry

and shift out data from the ALU are registered and can be

selected as inputs in subsequent cycles. This provides support

for 16-bit functions in one (8-bit) datapath.

Shift left

Shift right

Nibble swap

Bitwise OR mask

7.2.2.9 Datapath I/O

7.2.2.3 Conditionals

There are six inputs and six outputs that connect the datapath to

the routing matrix. Inputs from the routing provide the

configuration for the datapath operation to perform in each cycle,

and the serial data inputs. Inputs can be routed from other UDB

blocks, other device peripherals, device I/O pins, and so on. The

outputs to the routing can be selected from the generated

conditions, and the serial data outputs. Outputs can be routed to

other UDB blocks, device peripherals, interrupt and DMA

controller, I/O pins, and so on.

Each datapath has two compares, with bit masking options.

Compare operands include the two accumulators and the two

data registers in a variety of configurations. Other conditions

include zero detect, all ones detect, and overflow. These

conditions are the primary datapath outputs, a selection of which

can be driven out to the UDB routing matrix. Conditional

computation can use the built in chaining to neighboring UDBs

to operate on wider data widths without the need to use routing

resources.

7.2.3 Status and Control Module

7.2.2.4 Variable MSB

The primary purpose of this circuitry is to coordinate CPU

firmware interaction with internal UDB operation.

The most significant bit of an arithmetic and shift function can be

programmatically specified. This supports variable width CRC

and PRS functions, and in conjunction with ALU output masking,

can implement arbitrary width timers, counters and shift blocks.

Figure 7-10. Status and Control Registers

System Bus

7.2.2.5 Built in CRC/PRS

The datapath has built in support for single cycle CRC

computation and PRS generation of arbitrary width and arbitrary

polynomial. CRC/PRS functions longer than 8 bits may be

implemented in conjunction with PLD logic, or built in chaining

may be use to extend the function into neighboring UDBs.

8-bit Status Register

(Read Only)

8-bit Control Register

(Write/Read)

Routing Channel

7.2.2.6 Input/Output FIFOs

Each datapath contains two four-byte deep FIFOs, which can be

independently configured as an input buffer (system bus writes

to the FIFO, datapath internal reads the FIFO), or an output

buffer (datapath internal writes to the FIFO, the system bus reads

from the FIFO). The FIFOs generate status that are selectable

as datapath outputs and can therefore be driven to the routing,

to interact with sequencers, interrupts, or DMA.

The bits of the control register, which may be written to by the

system bus, are used to drive into the routing matrix, and thus

provide firmware with the opportunity to control the state of UDB

processing. The status register is read-only and it allows internal

UDB state to be read out onto the system bus directly from

internal routing. This allows firmware to monitor the state of UDB

processing. Each bit of these registers has programmable

connections to the routing matrix and routing connections are

made depending on the requirements of the application.

Figure 7-9. Example FIFO Configurations

System Bus

7.2.3.1 Usage Examples

F0

F1

As an example of control input, a bit in the control register can

be allocated as a function enable bit. There are multiple ways to

enable a function. In one method the control bit output would be

routed to the clock control block in one or more UDBs and serve

as a clock enable for the selected UDB blocks. A status example

is a case where a PLD or datapath block generated a condition,

such as a “compare true” condition that is captured and latched

by the status register and then read (and cleared) by CPU

firmware.

D0/D1

D0

A0

D1

A1

A0/A1/ALU

F0

A0/A1/ALU

F1

System Bus

Dual Capture

TX/RX

Dual Buffer

7.2.3.2 Clock Generation

Each subcomponent block of a UDB including the two PLDs, the

datapath, and Status and Control, has a clock selection and

control block. This promotes a fine granularity with respect to

allocating clocking resources to UDB component blocks and

allows unused UDB resources to be used by other functions for

maximum system efficiency.

7.2.2.7 Chaining

The datapath can be configured to chain conditions and signals

such as carries and shift data with neighboring datapaths to

create higher precision arithmetic, shift, CRC/PRS functions.

Document Number: 001-53413 Rev. *L

Page 44 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Figure 7-12. Function Mapping Example in a Bank of UDBs

7.3 UDB Array Description

Figure 7-11 shows an example of a 16-UDB array. In addition to

the array core, there are a DSI routing interfaces at the top and

bottom of the array. Other interfaces that are not explicitly shown

include the system interfaces for bus and clock distribution. The

UDB array includes multiple horizontal and vertical routing

channels each comprised of 96 wires. The wire connections to

UDBs, at horizontal/vertical intersection and at the DSI interface

are highly permutable providing efficient automatic routing in

PSoC Creator. Additionally the routing allows wire by wire

segmentation along the vertical and horizontal routing to further

increase routing flexibility and capability.

8-Bit

Timer

16-Bit

PWM

Quadrature Decoder

16-Bit PYRS

UDB

HV

A

HV

B

HV

A

HV

B

UDB

8-Bit

UDB

8-Bit SPI

UDB

Timer

Logic

Figure 7-11. Digital System Interface Structure

I2C Slave

UDB

12-Bit SPI

UDB

System Connections

HV

B

HV

A

HV

B

HV

A

HV

B

HV

A

HV

B

HV

A

Logic

UDB

HV

A

HV

B

HV

A

HV

B

UART

12-Bit PWM

UDB

7.4 DSI Routing Interface Description

The DSI routing interface is a continuation of the horizontal and

vertical routing channels at the top and bottom of the UDB array

core. It provides general purpose programmable routing

between device peripherals, including UDBs, I/Os, analog

peripherals, interrupts, DMA and fixed function peripherals.

HV

B

HV

A

HV

B

HV

A

Figure 7-13 illustrates the concept of the digital system

interconnect, which connects the UDB array routing matrix with

other device peripherals. Any digital core or fixed function

peripheral that needs programmable routing is connected to this

interface.

UDB

HV

A

HV

B

HV

A

HV

B

Signals in this category include:

System Connections

Interrupt requests from all digital peripherals in the system.

DMA requests from all digital peripherals in the system.

Digital peripheral data signals that need flexible routing to I/Os.

Digital peripheral data signals that need connections to UDBs.

Connections to the interrupt and DMA controllers.

Connection to I/O pins.

7.3.1 UDB Array Programmable Resources

Figure 7-12 shows an example of how functions are mapped into

a bank of 16 UDBs. The primary programmable resources of the

UDB are two PLDs, one datapath and one status/control register.

These resources are allocated independently, because they

have independently selectable clocks, and therefore unused

blocks are allocated to other unrelated functions.

Connection to analog system digital signals.

An example of this is the 8-bit Timer in the upper left corner of

the array. This function only requires one datapath in the UDB,

and therefore the PLD resources may be allocated to another

function. A function such as a Quadrature Decoder may require

more PLD logic than one UDB can supply and in this case can

utilize the unused PLD blocks in the 8-bit Timer UDB.

Programmable resources in the UDB array are generally

homogeneous so functions can be mapped to arbitrary

boundaries in the array.

Document Number: 001-53413 Rev. *L

Page 45 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Figure 7-13. Digital System Interconnect

7.4.1 I/O Port Routing

There are a total of 20 DSI routes to a typical 8-bit I/O port, 16

for data and four for drive strength control.

Timer

Counters

Interrupt

Controller

DMA

Controller

IO Port

Pins

Global

Clocks

CAN

I2C

When an I/O pin is connected to the routing, there are two

primary connections available, an input and an output. In

conjunction with drive strength control, this can implement a

bidirectional I/O pin. A data output signal has the option to be

single synchronized (pipelined) and a data input signal has the

option to be double synchronized. The synchronization clock is

the system clock (see Figure 6-1 on page 26). Normally all inputs

from pins are synchronized as this is required if the CPU

interacts with the signal or any signal derived from it.

Asynchronous inputs have rare uses. An example of this is a

feed through of combinational PLD logic from input pins to output

pins.

Digital System Routing I/F

UDB ARRAY

Figure 7-15. I/O Pin Synchronization Routing

Digital System Routing I/F

DO

DI

Global

Clocks

IO Port

Pins

SC/CT

Blocks

EMIF

Del-Sig

DACs

Comparators

Figure 7-16. I/O Pin Output Connectivity

Interrupt and DMA routing is very flexible in the CY8C36

8 IO Data Output Connections from the

UDB Array Digital System Interface

programmable architecture. In addition to the numerous fixed

function peripherals that can generate interrupt requests, any

data signal in the UDB array routing can also be used to generate

a request. A single peripheral may generate multiple

independent interrupt requests simplifying system and firmware

design. Figure 7-14 shows the structure of the IDMUX

(Interrupt/DMA Multiplexer).

Figure 7-14. Interrupt and DMA Processing in the IDMUX

Interrupt and DMA Processing in IDMUX

Fixed Function IRQs

0

DO

PIN 0

DO

PIN1

DO

PIN2

DO

PIN3

DO

PIN4

DO

PIN5

DO

PIN6

DO

PIN7

1

Interrupt

Controller

IRQs

2

3

Port i

UDB Array

Edge

Detect

There are four more DSI connections to a given I/O port to

implement dynamic output enable control of pins. This

connectivity gives a range of options, from fully ganged 8-bits

controlled by one signal, to up to four individually controlled pins.

The output enable signal is useful for creating tri-state

bidirectional pins and buses.

DRQs

DMA termout (IRQs)

0

Fixed Function DRQs

DMA

Controller

1

2

Edge

Detect

Document Number: 001-53413 Rev. *L

Page 46 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Figure 7-17. I/O Pin Output Enable Connectivity

7.5 CAN

The CAN peripheral is a fully functional CAN supporting

communication baud rates up to 1 Mbps. The CAN controller

implements the CAN2.0A and CAN2.0B specifications as

defined in the Bosch specification and conforms to the

ISO-11898-1 standard. The CAN protocol was originally

designed for automotive applications with a focus on a high level

of fault detection. This ensures high communication reliability at

a low cost. Because of its success in automotive applications,

CAN is used as a standard communication protocol for motion

oriented machine control networks (CANOpen) and factory

automation applications (DeviceNet). The CAN controller

features allow the efficient implementation of higher level

protocols without affecting the performance of the

4 IO Control Signal Connections from

UDB Array Digital System Interface

OE

PIN1

OE

PIN2

OE

PIN3

OE

PIN4

OE

PIN5

OE

PIN6

OE

PIN7

PIN 0

microcontroller CPU. Full configuration support is provided in

PSoC Creator.

Port i

Figure 7-18. CAN Bus System Implementation

CAN Node 1

PSoC

CAN Node 2

CAN Node n

CAN

Drivers

CAN Controller

En

Tx Rx

CAN Transceiver

CAN_H

CAN_L

CAN_H

CAN_L

CAN Bus

7.5.1 CAN Features

CAN2.0A/B protocol implementation – ISO 11898 compliant

Standard and extended frames with up to 8 bytes of data per

frame

Message filter capabilities

Remote Transmission Request (RTR) support

Programmable bit rate up to 1 Mbps

Receive path

16 receive buffers each with its own message filter

Enhanced hardware message filter implementation that

covers the ID, IDE, and RTR

DeviceNet addressing support

Multiple receive buffers linkable to build a larger receive

message array

Automatic transmission request (RTR) response handler

Lost received message notification

Listen Only mode

SW readable error counter and indicator

Transmit path

Eight transmit buffers

Programmable transmit priority

• Round robin

• Fixed priority

Message transmissions abort capability

Sleep mode: Wake the device from sleep with activity on the

Rx pin

Supports two or three wire interface to external transceiver (Tx,

Rx, and Enable). The three-wire interface is compatible with

the Philips PHY; the PHY is not included on-chip. The three

wires can be routed to any I/O

7.5.2 Software Tools Support

Enhanced interrupt controller

CAN receive and transmit buffers status

CAN controller error status including BusOff

CAN Controller configuration integrated into PSoC Creator:

CAN Configuration walkthrough with bit timing analyzer

Receive filter setup

Document Number: 001-53413 Rev. *L

Page 47 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Figure 7-19. CAN Controller Block Diagram

TxMessage0

TxReq

TxAbort

TxMessage1

TxReq

TxAbort

Tx Buffer

Status

TxReq

Bit Timing

Pending

Priority

Arbiter

Tx

TxMessage6

TxReq

Tx

CAN

Framer

CRC

Generator

TxInterrupt

Request

TxAbort

(if enabled)

TxMessage7

TxReq

TxAbort

Error Status

Error Active

Error Passive

Bus Off

Tx Error Counter

Rx Error Counter

RTR RxMessages

0-15

Acceptance Code 0

RxMessage0

RxMessage1

Acceptance Mask 0

Acceptance Mask 1

Rx Buffer

Status

RxMessage

Available

Acceptance Code 1

Rx

RxMessage

Handler

CAN

Framer

CRC Check

RxMessage14

RxMessage15

Acceptance Mask 14

Acceptance Mask 15

Acceptance Code 14

Acceptance Code 15

RxInterrupt

Request

(if enabled)

WakeUp

Request

Error Detection

CRC

Form

ACK

Bit Stuffing

Bit Error

Overload

Arbitration

ErrInterrupt

Request

(if enabled)

Internal 48-MHz main oscillator mode that auto locks to USB

bus clock, requiring no external crystal for USB (USB equipped

parts only)

7.6 USB

PSoC includes a dedicated Full-Speed (12 Mbps) USB 2.0

transceiver supporting all four USB transfer types: control,

interrupt, bulk, and isochronous. PSoC Creator provides full

configuration support. USB interfaces to hosts through two

dedicated USBIO pins, which are detailed in the “I/O System and

Routing” section on page 32.

Interrupts on bus and each endpoint event, with device wakeup

USB reset, suspend, and resume operations

Bus-powered and self-powered modes

Figure 7-20. USB

USB includes the following features:

Eight unidirectional data endpoints

One bidirectional control endpoint 0 (EP0)

Shared 512-byte buffer for the eight data endpoints

Dedicated 8-byte buffer for EP0

512 X 8

Arbiter

SRAM

External 22 Ω

Resistors

D+

S I E

(Serial Interface

Engine)

Three memory modes

Manual Memory Management with No DMA Access

Manual Memory Management with Manual DMA Access

Automatic Memory Management with Automatic DMA

Access

USB

I/O

D–

Interrupts

48 MHz

IMO

Internal 3.3-V regulator for transceiver

Document Number: 001-53413 Rev. *L

Page 48 of 126

PSoC^®3: CY8C36 Family

Data Sheet

2

7.7 Timers, Counters, and PWMs

7.8 I C

The Timer/Counter/PWM peripheral is a 16-bit dedicated

peripheral providing three of the most common embedded

peripheral features. As almost all embedded systems use some

combination of timers, counters, and PWMs. Four of them have

been included on this PSoC device family. Additional and more

advanced functionality timers, counters, and PWMs can also be

instantiated in Universal Digital Blocks (UDBs) as required.

PSoC Creator allows you to choose the timer, counter, and PWM

features that they require. The tool set utilizes the most optimal

resources available.

The I²C peripheral provides a synchronous two wire interface

designed to interface the PSoC device with a two wire I²C serial

communication bus. The bus is compliant with Philips ‘The I²C

Specification’ version 2.1. Additional I²C interfaces can be

instantiated using Universal Digital Blocks (UDBs) in PSoC

Creator, as required.

To eliminate the need for excessive CPU intervention and

overhead, I²C specific support is provided for status detection

and generation of framing bits. I²C operates as a slave, a master,

or multimaster (Slave and Master). In slave mode, the unit

always listens for a start condition to begin sending or receiving

data. Master mode supplies the ability to generate the Start and

Stop conditions and initiate transactions. Multimaster mode

provides clock synchronization and arbitration to allow multiple

masters on the same bus. If Master mode is enabled and Slave

mode is not enabled, the block does not generate interrupts on

externally generated Start conditions. I²C interfaces through DSI

routing and allows direct connections to any GPIO or SIO pins.

I²C provides hardware address detect of a 7-bit address without

CPU intervention. Additionally the device can wake from

low-power modes on a 7-bit hardware address match. If wakeup

functionality is required, I²C pin connections are limited to the

two special sets of SIO pins.

The Timer/Counter/PWM peripheral can select from multiple

clock sources, with input and output signals connected through

the DSI routing. DSI routing allows input and output connections

to any device pin and any internal digital signal accessible

through the DSI. Each of the four instances has a compare

output, terminal count output (optional complementary compare

output), and programmable interrupt request line. The

Timer/Counter/PWMs are configurable as freerunning, one shot,

or Enable input controlled. The peripheral has timer reset and

capture inputs, and a kill input for control of the comparator

outputs. The peripheral supports full 16-bit capture.

Timer/Counter/PWM features include:

16-bit Timer/Counter/PWM (down count only)

Selectable clock source

I²C features include:

Slave and master, transmitter, and receiver operation

Byte processing for low CPU overhead

Interrupt or polling CPU interface

PWM comparator (configurable for LT, LTE, EQ, GTE, GT)

Period reload on start, reset, and terminal count

Interrupt on terminal count, compare true, or capture

Dynamic counter reads

Support for bus speeds up to 1 Mbps (3.4 Mbps in UDBs)

7 or 10-bit addressing (10-bit addressing requires firmware

support)

Timer capture mode

Count while enable signal is asserted mode

Free run mode

SMBus operation (through firmware support – SMBus

supported in hardware in UDBs)

One Shot mode (stop at end of period)

Complementary PWM outputs with deadband

PWM output kill

7-bit hardware address compare

Wake from low-power modes on address match

Data transfers follow the format shown in Figure 7-22. After the

START condition (S), a slave address is sent. This address is 7

bits long followed by an eighth bit which is a data direction bit

(R/W) - a 'zero' indicates a transmission (WRITE), a 'one'

indicates a request for data (READ). A data transfer is always

terminated by a STOP condition (P) generated by the master.

However, if a master still wishes to communicate on the bus, it

can generate a repeated START condition (Sr) and address

another slave without first generating a STOP condition. Various

combinations of read/write formats are then possible within such

a transfer.

Figure 7-21. Timer/Counter/PWM

Clock

Reset

Enable

Capture

Kill

IRQ

Timer / Counter /

PWM 16-bit

TC / Compare!

Compare

Figure 7-22. I²C Complete Transfer Timing

SDA

SCL

8

9

1 - 7

8

9

1 - 7

8

9

1 - 7

START

Condition

STOP

Condition

ADDRESS

R/W

ACK

DATA

ACK

DATA

ACK

Document Number: 001-53413 Rev. *L

Page 49 of 126

PSoC^®3: CY8C36 Family

Data Sheet

The DFB processes this data and passes the result to another

on chip resource such as a DAC or main memory through DMA

on the system bus.

7.9 Digital Filter Block

Some devices in the CY8C36 family of devices have a dedicated

HW accelerator block used for digital filtering. The DFB has a

dedicated multiplier and accumulator that calculates a 24-bit by

24-bit multiply accumulate in one system clock cycle. This

enables the mapping of a direct form FIR filter that approaches

a computation rate of one FIR tap for each clock cycle. The MCU

can implement any of the functions performed by this block, but

at a slower rate that consumes MCU bandwidth.

Data movement in or out of the DFB is typically controlled by the

system DMA controller but can be moved directly by the MCU.

8. Analog Subsystem

The analog programmable system creates application specific

combinations of both standard and advanced analog signal

processing blocks. These blocks are then interconnected to

each other and also to any pin on the device, providing a high

level of design flexibility and IP security. The features of the

analog subsystem are outlined here to provide an overview of

capabilities and architecture.

The PSoC Creator interface provides a wizard to implement FIR

and IIR digital filters with coefficients for LPF, BPF, HPF, Notch

and arbitrary shape filters. 64 pairs of data and coefficients are

stored. This enables a 64 tap FIR filter or up to 4 16 tap filters of

either FIR or IIR formulation.

Flexible, configurable analog routing architecture provided by

analog globals, analog mux bus, and analog local buses.

Figure 7-23. DFB Application Diagram (pwr/gnd not shown)

High resolution Delta-Sigma ADC.

BUSCLK

read_data

write_data

Up to four 8-bit DACs that provide either voltage or current

output.

Data

Source

(PHUB)

Fourcomparatorswithoptional connectiontoconfigurableLUT

outputs.

System

Bus

addr

Digital

Routing

Digital Filter

Block

Data

Dest

(PHUB)

Up to four configurable switched capacitor/continuous time

(SC/CT) blocks for functions that include opamp, unity gain

buffer, programmablegainamplifier, transimpedanceamplifier,

and mixer.

DMA

Request

DMA

CTRL

Up to four opamps for internal use and connection to GPIO that

can be used as high current output buffers.

CapSense subsystem to enable capacitive touch sensing.

The typical use model is for data to be supplied to the DFB over

the system bus from another on-chip system data source such

as an ADC. The data typically passes through main memory or

is directly transferred from another chip resource through DMA.

Precision reference for generating an accurate analog voltage

for internal analog blocks.

Document Number: 001-53413 Rev. *L

Page 50 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Figure 8-1. Analog Subsystem Block Diagram

DAC

Precision

Reference

A

N

A

L

O

G

A

N

A

L

O

G

DAC

SC/CT Block

GPIO

Port

GPIO

Port

SC/CT Block

R

O

U

T

I

R

O

U

T

I

Comparators

CMP CMP

N

G

N

G

CMP

CapSense Subsystem

Config&

Status

Registers

Analog

Interface

PHUB

CPU

DSI

Array

Clock

Distribution

Decimator

The PSoC Creator software program provides a user friendly

interface to configure the analog connections between the GPIO

and various analog resources and connections from one analog

resource to another. PSoC Creator also provides component

libraries that allow you to configure the various analog blocks to

perform application specific functions (PGA, transimpedance

amplifier, voltage DAC, current DAC, and so on). The tool also

generates API interface libraries that allow you to write firmware

that allows the communication between the analog peripheral

and CPU/Memory.

Eight analog local buses (abus) to route signals between the

different analog blocks

Multiplexers and switches for input and output selection of the

analog blocks

8.1.2 Functional Description

Analog globals (AGs) and analog mux buses (AMUXBUS)

provide analog connectivity between GPIOs and the various

analog blocks. There are 16 AGs in the CY8C36 family. The

analog routing architecture is divided into four quadrants as

shown in Figure 8-2. Each quadrant has four analog globals

(AGL[0..3], AGL[4..7], AGR[0..3], AGR[4..7]). Each GPIO is

connected to the corresponding AG through an analog switch.

The analog mux bus is a shared routing resource that connects

to every GPIO through an analog switch. There are two

AMUXBUS routes in CY8C36, one in the left half (AMUXBUSL)

and one in the right half (AMUXBUSR), as shown in Figure 8-2.

8.1 Analog Routing

The CY8C36 family of devices has a flexible analog routing

architecture that provides the capability to connect GPIOs and

different analog blocks, and also route signals between different

analog blocks. One of the strong points of this flexible routing

architecture is that it allows dynamic routing of input and output

connections to the different analog blocks.

For information on how to make pin selections for optimal analog

routing, refer to the application note, AN58304 - PSoC® 3 and

PSoC® 5 - Pin Selection for Analog Designs.

8.1.1 Features

Flexible, configurable analog routing architecture

16 analog globals (AG) and two analog mux buses

(AMUXBUS) to connect GPIOs and the analog blocks

Each GPIO is connected to one analog global and one analog

mux bus

Document Number: 001-53413 Rev. *L

Page 51 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Figure 8-2. CY8C36 Analog Interconnect

*

swinp

*

swinn

*

AMUXBUSR

AMUXBUSL

AGL[4]

AGL[5]

AGL[6]

AGL[7]

AGR[4]

AGR[5]

AGR[6]

AGR[7]

ExVrefL

ExVrefL1

ExVrefL2

44

swinp

swinn

GPIO

P3[5]

GPIO

P3[4]

GPIO

P3[3]

GPIO

P3[2]

GPIO

P3[1]

GPIO

P3[0]

GPXT

opamp1

swfol

opamp3

swfol

opamp0

swfol

opamp2

swfol

swinp

swinn

0123

3210

76543210

01234567

GPIO

P0[4]

GPIO

P0[5]

GPIO

P0[6]

GPIO

swinp

swinn

LPF

swout

in0

in1

abuf_vref_int

(1.024V)

abuf_vref_int

(1.024V)

i0

i2

*

5

ExVrefR

swin

out0

out1

comp0

comp1

+

-

+

-

*

P0[7]

i3

i1

COMPARATOR

cmp0_vref

(1.024V)

cmp0_vref

(1.024V)

+

-

+

-

GPIO

P4[2]

GPIO

P4[3]

GPIO

cmp_muxvn[1:0]

vref_cmp1

_{bg_v}(_d0_a._{_}2_re5_s6_{_e}V_n)

comp2

90 comp3

cmp1_vref

*

P15[1]

GPXT

P15[0]

bg_vda_swabusl0

Vdda

Vdda/2

out

ref

in

out

ref

in

refbuf_vref1 (1.024V)

CAPSENSE

refbufl

refbuf_vref1 (1.024V)

refbuf_vref2 (1.2V)

*

refbuf_vref2 (1.2V)

refbufr

refsel[1:0]

P4[4]

GPIO

P4[5]

GPIO

P4[6]

GPIO

P4[7]

vssa

Vssa

sc0

Vin

Vref

out

sc1

Vin

Vref

sc2_bgref

(1.024V)

sc0_bgref

(1.024V)

*

out

sc1_bgref

(1.024V)

sc3_bgref

(1.024V)

Vccd

SC/CT

Vin

Vref

out

sc2

Vin

Vref

out

sc3

*

Vssd

*

104

*

Vccd

Vddd

*

Vssd

ABUSL0

ABUSL1

ABUSL2

ABUSL3

ABUSR0

ABUSR1

ABUSR2

ABUSR3

*

Vddd

GPIO

P6[0]

GPIO

v0

i0

v1

DAC1

i1

USB IO

DAC0

*

P15[7]

VIDAC

USB IO

v2

i2

36

v3

DAC3

i3

*

DAC2

P15[6]

GPIO

P6[1]

GPIO

P6[2]

GPIO

P6[3]

GPIO

P15[4]

GPIO

P15[5]

GPIO

P2[0]

GPIO

P2[1]

GPIO

P2[2]

GPIO

dac_vref (0.256V)

P5[7]

GPIO

P5[6]

GPIO

P5[5]

GPIO

P5[4]

SIO

P12[7]

SIO

P12[6]

GPIO

vcmsel[1:0]

en_resvpwra

+

DSM0

vpwra

vpwra/2

dsm0_vcm_vref1

(0.8V)

DSM

refs

-

vssa

28

vcm

qtz_ref

vref_vss_ext

dsm0_vcm_vref2 (0.7V)

dsm0_qtz_vref2 (1.2V)

dsm0_qtz_vref1 (1.024V)

Vdda

Vdda/4

ExVrefL

ExVrefR

refmux[2:0]

en_resvda

CY8C55 only

*

P1[7]

GPIO

AMUXBUSL

AMUXBUSR

76543210

0123

ANALOG

BUS

*

P1[6]

01234567

3210

ANALOG

ANALOG ANALOG

BUS GLOBALS

*

P2[3]

GPIO

P2[4]

GLOBALS

*

VBE

TS

ADC

*

:

Vss ref

Vddio2

LPF

AGR[3]

AGR[2]

AGL[3]

AGL[2]

AGR[1]

AGL[1]

AGR[0]

AGL[0]

AMUXBUSR

AMUXBUSL

*

13

Mux Group

Switch Group

*

Connection

*

Switch Resistance

Notes:

Small ( ~870 Ohms )

Large ( ~200 Ohms)

* Denotes pins on all packages

LCD signals are not shown.

Rev #51

2-April-2010

Document Number: 001-53413 Rev. *L

Page 52 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Analog local buses (abus) are routing resources located within

the analog subsystem and are used to route signals between

different analog blocks. There are eight abus routes in CY8C36,

four in the left half (abusl [0:3]) and four in the right half (abusr

[0:3]) as shown in Figure 8-2. Using the abus saves the analog

globals and analog mux buses from being used for

actual analog to digital conversion. The modulator over-samples

the input and generates a serial data stream output. This high

speed data stream is not useful for most applications without

some type of post processing, and so is passed to the decimator

through the Analog Interface block. The decimator converts the

high speed serial data stream into parallel ADC results. The

modulator/decimator frequency response is [(sin x)/x]⁴; a typical

frequency response is shown in Figure 8-5.

interconnecting the analog blocks.

Multiplexers and switches exist on the various buses to direct

signals into and out of the analog blocks. A multiplexer can have

only one connection on at a time, whereas a switch can have

multiple connections on simultaneously. In Figure 8-2,

multiplexers are indicated by grayed ovals and switches are

indicated by transparent ovals.

Figure 8-4. Delta-sigma ADC Block Diagram

Positive

Input Mux

Delta

Sigma

Modulator

Input

Buffer

12 to 20 Bit

Result

Decimator

SOC

(Analog Routing)

8.2 Delta-sigma ADC

Negative

EOC

Input Mux

The CY8C36 device contains one delta-sigma ADC. This ADC

offers differential input, high resolution and excellent linearity,

making it a good ADC choice for measurement applications. The

converter can be configured to output 12-bit resolution at data

rates of up to 192 ksps. At a fixed clock rate, resolution can be

traded for faster data rates as shown in Table 8-1 and Figure 8-3.

Figure 8-5. Delta-sigma ADC Frequency Response,

Normalized to Output, Sample Rate = 48 kHz

Table 8-1. Delta-sigma ADC Performance

MaximumSampleRate

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

Bits

SINAD (dB)

(sps)

192 k

384 k

12

8

66

43

Figure8-3. Delta-sigmaADCSampleRates, Range=±1.024 V

1,000,000

100

1,000

10,000

Input Frequency,

100,000

1,000,000

100,000

10,000

1,000

Input frequency,^HH^zz

Resolution and sample rate are controlled by the Decimator.

Data is pipelined in the decimator; the output is a function of the

last four samples. When the input multiplexer is switched, the

output data is not valid until after the fourth sample after the

switch.

8.2.2 Operational Modes

Continuous

The ADC can be configured by the user to operate in one of four

modes: Single Sample, Multi Sample, Continuous, or Multi

Sample (Turbo). All four modes are started by either a write to

the start bit in a control register or an assertion of the Start of

Conversion (SoC) signal. When the conversion is complete, a

status bit is set and the output signal End of Conversion (EoC)

asserts high and remains high until the value is read by either the

DMA controller or the CPU.

Multi-Sample

100

7

8

9

10

11

12

13

Resolution, bits

8.2.1 Functional Description

8.2.2.1 Single Sample

The ADC connects and configures three basic components,

input buffer, delta-sigma modulator, and decimator. The basic

block diagram is shown in Figure 8-4. The signal from the input

muxes is delivered to the delta-sigma modulator either directly or

through the input buffer. The delta-sigma modulator performs the

In Single Sample mode, the ADC performs one sample

conversion on a trigger. In this mode, the ADC stays in standby

state waiting for the SoC signal to be asserted. When SoC is

signaled the ADC performs four successive conversions. The

first three conversions prime the decimator. The ADC result is

Document Number: 001-53413 Rev. *L

Page 53 of 126

PSoC^®3: CY8C36 Family

Data Sheet

valid and available after the fourth conversion, at which time the

EoC signal is generated. To detect the end of conversion, the

system may poll a control register for status or configure the

external EoC signal to generate an interrupt or invoke a DMA

request. When the transfer is done the ADC reenters the standby

state where it stays until another SoC event.

hardware. This signal is optional and does not need to be

connected if ADC is running in a continuous mode.

8.2.4 End of Conversion Output

The EoC signal goes high at the end of each ADC conversion.

This signal may be used to trigger either an interrupt or DMA

request.

8.2.2.2 Continuous

Continuous sample mode is used to take multiple successive

samples of a single input signal. Multiplexing multiple inputs

should not be done with this mode. There is a latency of three

conversion times before the first conversion result is available.

This is the time required to prime the decimator. After the first

result, successive conversions are available at the selected

sample rate.

8.3 Comparators

The CY8C36 family of devices contains four comparators in a

device. Comparators have these features:

Input offset factory trimmed to less than 5 mV

Rail-to-rail common mode input range (V_SSAto V_DDA

)

Speed and power can be traded off by using one of three

modes: fast, slow, or ultra low-power

8.2.2.3 Multi Sample

Multi sample mode is similar to continuous mode except that the

ADC is reset between samples. This mode is useful when the

input is switched between multiple signals. The decimator is

re-primed between each sample so that previous samples do not

affect the current conversion. Upon completion of a sample, the

next sample is automatically initiated. The results can be

transferred using either firmware polling, interrupt, or DMA.

Comparator outputs can be routed to lookup tables to perform

simple logic functions and then can also be routed to digital

blocks

The positive input ofthe comparators may be optionally passed

through a low pass filter. Two filters are provided

Comparator inputs can be connections to GPIO, DAC outputs

and SC block outputs

More information on output formats is provided in the Technical

Reference Manual.

8.3.1 Input and Output Interface

The positive and negative inputs to the comparators come from

the analog global buses, the analog mux line, the analog local

bus and precision reference through multiplexers. The output

from each comparator could be routed to any of the two input

LUTs. The output of that LUT is routed to the UDB Digital System

Interface.

8.2.3 Start of Conversion Input

The SoC signal is used to start an ADC conversion. A digital

clock or UDB output can be used to drive this input. It can be

used when the sampling period must be longer than the ADC

conversion time or when the ADC must be synchronized to other

Figure 8-6. Analog Comparator

ANAIF

From

Analog

Routing

+

comp0

_

+

_

From

Analog

Routing

comp1

From

Analog

Routing

+

comp3

_

+

From

Analog

Routing

comp2

_

4

LUT0

LUT1

LUT2

LUT3

UDBs

Document Number: 001-53413 Rev. *L

Page 54 of 126

PSoC^®3: CY8C36 Family

Data Sheet

8.3.2 LUT

Figure 8-8. Opamp Configurations

The CY8C36 family of devices contains four LUTs. The LUT is a

two input, one output lookup table that is driven by any one or

two of the comparators in the chip. The output of any LUT is

routed to the digital system interface of the UDB array. From the

digital system interface of the UDB array, these signals can be

connected to UDBs, DMA controller, I/O, or the interrupt

controller.

a) Voltage Follower

Opamp

Vout to Pin

Vin

The LUT control word written to a register sets the logic function

on the output. The available LUT functions and the associated

control word is shown in Table 8-2.

b) External Uncommitted

Opamp

Table 8-2. LUT Function vs. Program Word and Inputs

Control Word

0000b

0001b

0010b

0011b

0100b

0101b

0110b

0111b

Output (A and B are LUT inputs)

FALSE (‘0’)

A AND B

Vout to GPIO

Opamp

A AND (NOT B)

A

(NOT A) AND B

B

Vp to GPIO

Vn to GPIO

A XOR B

A OR B

c) Internal Uncommitted

Opamp

1000b

1001b

1010b

1011b

1100b

1101b

1110b

A NOR B

A XNOR B

NOT B

Vn

A OR (NOT B)

NOT A

To Internal Signals

Vout to Pin

GPIO Pin

Opamp

(NOT A) OR B

A NAND B

TRUE (‘1’)

Vp

1111b

8.4 Opamps

The opamp has three speed modes, slow, medium, and fast. The

slow mode consumes the least amount of quiescent power and

the fast mode consumes the most power. The inputs are able to

swing rail-to-rail. The output swing is capable of rail-to-rail

operation at low current output, within 50 mV of the rails. When

driving high current loads (about 25 mA) the output voltage may

only get within 500 mV of the rails.

The CY8C36 family of devices contain up to four general

purpose opamps in a device.

Figure 8-7. Opamp

GPIO

8.5 Programmable SC/CT Blocks

Analog

Global Bus

The CY8C36 family of devices contains up to four switched

capacitor/continuous time (SC/CT) blocks in a device. Each

switched capacitor/continuous time block is built around a single

rail-to-rail high bandwidth opamp.

Opamp

Analog

Global Bus

GPIO

VREF

Analog

Internal Bus

Switched capacitor is a circuit design technique that uses

capacitors plus switches instead of resistors to create analog

functions. These circuits work by moving charge between

capacitors by opening and closing different switches.

Nonoverlapping in phase clock signals control the switches, so

that not all switches are ON simultaneously.

=

Analog Switch

GPIO

The opamp is uncommitted and can be configured as a gain

stage or voltage follower, or output buffer on external or internal

signals.

The PSoC Creator tool offers a user friendly interface, which

allows you to easily program the SC/CT blocks. Switch control

and clock phase control configuration is done by PSoC Creator

so users only need to determine the application use parameters

such as gain, amplifier polarity, V_REFconnection, and so on.

See Figure 8-8. In any configuration, the input and output signals

can all be connected to the internal global signals and monitored

with an ADC, or comparator. The configurations are

implemented with switches between the signals and GPIO pins.

Document Number: 001-53413 Rev. *L

Page 55 of 126

PSoC^®3: CY8C36 Family

Data Sheet

The same opamps and block interfaces are also connectable to

an array of resistors which allows the construction of a variety of

continuous time functions.

The PGA is used in applications where the input signal may not

be large enough to achieve the desired resolution in the ADC, or

dynamic range of another SC/CT block such as a mixer. The gain

is adjustable at runtime, including changing the gain of the PGA

prior to each ADC sample.

The opamp and resistor array is programmable to perform

various analog functions including

Naked operational amplifier – Continuous mode

Unity-gain buffer – Continuous mode

8.5.4 TIA

The Transimpedance Amplifier (TIA) converts an internal or

external current to an output voltage. The TIA uses an internal

feedback resistor in a continuous time configuration to convert

input current to output voltage. For an input current Iin, the output

voltage is Iin × Rfb +V_REF, where V_REFis the value placed on the

non inverting input. The feedback resistor Rfb is programmable

between 20 KΩ and 1 MΩ through a configuration register.

Table 8-4 shows the possible values of Rfb and associated

configuration settings.

Programmable gain amplifier (PGA) – Continuous mode

Transimpedance amplifier (TIA) – Continuous mode

Up/down mixer – Continuous mode

Sample and hold mixer (NRZ S/H) – Switched cap mode

First order analog to digital modulator – Switched cap mode

8.5.1 Naked Opamp

The Naked Opamp presents both inputs and the output for

connection to internal or external signals. The opamp has a unity

gain bandwidth greater than 6.0 MHz and output drive current up

to 650 µA. This is sufficient for buffering internal signals (such as

DAC outputs) and driving external loads greater than 7.5 kΩ.

Table 8-4. Feedback Resistor Settings

Configuration Word

Nominal R_fb(KΩ)

000b

001b

010b

011b

100b

101b

110b

111b

20

30

8.5.2 Unity Gain

40

The Unity Gain buffer is a Naked Opamp with the output directly

connected to the inverting input for a gain of 1.00. It has a –3 dB

bandwidth greater than 6.0 MHz.

60

120

250

500

1000

8.5.3 PGA

The PGA amplifies an external or internal signal. The PGA can

be configured to operate in inverting mode or noninverting mode.

The PGA function may be configured for both positive and

negative gains as high as 50 and 49 respectively. The gain is

adjusted by changing the values of R1 and R2 as illustrated in

Figure 8-9 on page 56. The schematic in Figure 8-9 on page 56

shows the configuration and possible resistor settings for the

PGA. The gain is switched from inverting and non inverting by

changing the shared select value of the both the input muxes.

The bandwidth for each gain case is listed in Table 8-3.

Figure 8-10. Continuous Time TIA Schematic

R

fb

I

in

Table 8-3. Bandwidth

V

out

V

ref

Gain

1

Bandwidth

6.0 MHz

340 kHz

220 kHz

215 kHz

24

48

50

The TIA configuration is used for applications where an external

sensor's output is current as a function of some type of stimulus

such as temperature, light, magnetic flux etc. In a common

application, the voltage DAC output can be connected to the

V_REFTIA input to allow calibration of the external sensor bias

current by adjusting the voltage DAC output voltage.

Figure 8-9. PGA Resistor Settings

R1

R2

V_in

0

1

8.6 LCD Direct Drive

The PSoC Liquid Crystal Display (LCD) driver system is a highly

configurable peripheral designed to allow PSoC to directly drive

a broad range of LCD glass. All voltages are generated on chip,

eliminating the need for external components. With a high

multiplex ratio of up to 1/16, the CY8C36 family LCD driver

system can drive a maximum of 736 segments. The PSoC LCD

driver module was also designed with the conservative power

budget of portable devices in mind, enabling different LCD drive

modes and power down modes to conserve power.

V_ref

20 k or 40 k

20 k to 980 k

S

V_ref

V_in

0

1

Document Number: 001-53413 Rev. *L

Page 56 of 126

PSoC^®3: CY8C36 Family

Data Sheet

PSoC Creator provides an LCD segment drive component. The

component wizard provides easy and flexible configuration of

LCD resources. You can specify pins for segments and

commons along with other options. The software configures the

device to meet the required specifications. This is possible

because of the programmability inherent to PSoC devices.

8.6.2 Display Data Flow

The LCD segment driver system reads display data and

generates the proper output voltages to the LCD glass to

produce the desired image. Display data resides in a memory

buffer in the system SRAM. Each time you need to change the

common and segment driver voltages, the next set of pixel data

moves from the memory buffer into the Port Data Registers

through DMA.

Key features of the PSoC LCD segment system are:

LCD panel direct driving

8.6.3 UDB and LCD Segment Control

Type A (standard) and Type B (low-power) waveform support

A UDB is configured to generate the global LCD control signals

and clocking. This set of signals is routed to each LCD pin driver

through a set of dedicated LCD global routing channels. In

addition to generating the global LCD control signals, the UDB

also produces a DMA request to initiate the transfer of the next

frame of LCD data.

Wide operating voltage range support (2 V to 5 V) for LCD

panels

Static, 1/2, 1/3, 1/4, 1/5 bias voltage levels

Internal biasvoltage generationthrough internal resistorladder

Up to 62 total common and segment outputs

8.6.4 LCD DAC

Up to 1/16 multiplex for a maximum of 16 backplane/common

outputs

The LCD DAC generates the contrast control and bias voltage

for the LCD system. The LCD DAC produces up to five LCD drive

voltages plus ground, based on the selected bias ratio. The bias

voltages are driven out to GPIO pins on a dedicated LCD bias

bus, as required.

Up to 62 front plane/segment outputs for direct drive

Drives upto 736 total segments (16 backplane× 46 front plane)

Up to 64 levels of software controlled contrast

8.7 CapSense

Ability to move display data from memory buffer to LCD driver

through DMA (without CPU intervention)

The CapSense system provides a versatile and efficient means

for measuring capacitance in applications such as touch sense

buttons, sliders, proximity detection, etc. The CapSense system

uses a configuration of system resources, including a few

hardware functions primarily targeted for CapSense. Specific

resource usage is detailed in the CapSense component in PSoC

Creator.

Adjustable LCD refresh rate from 10 Hz to 150 Hz

Ability to invert LCD display for negative image

Three LCD driver drive modes, allowing power optimization

Figure 8-11. LCD System

A capacitive sensing method using a Delta-Sigma Modulator

(CSD) is used. It provides capacitance sensing using a switched

capacitor technique with a delta-sigma modulator to convert the

sensing current to a digital code.

LCD

Global

DAC

Clock

8.8 Temp Sensor

Die temperature is used to establish programming parameters

for writing flash. Die temperature is measured using a dedicated

sensor based on a forward biased transistor. The temperature

sensor has its own auxiliary ADC.

UDB

LCD Driver

Block

Display

DMA

RAM

8.9 DAC

The CY8C36 parts contain up to four Digital to Analog

Convertors (DACs). Each DAC is 8-bit and can be configured for

either voltage or current output. The DACs support CapSense,

power supply regulation, and waveform generation. Each DAC

has the following features:

PHUB

Adjustable voltage or current output in 255 steps

Programmable step size (range selection)

Eight bits of calibration to correct ± 25% of gain error

Source and sink option for current output

8 Msps conversion rate for current output

1 Msps conversion rate for voltage output

Monotonic in nature

8.6.1 LCD Segment Pin Driver

Each GPIO pin contains an LCD driver circuit. The LCD driver

buffers the appropriate output of the LCD DAC to directly drive

the glass of the LCD. A register setting determines whether the

pin is a common or segment. The pin’s LCD driver then selects

one of the six bias voltages to drive the I/O pin, as appropriate

for the display data.

Data and strobe inputs can be provided by the CPU or DMA,

or routed directly from the DSI

Dedicated low-resistance output pin for high-current mode

Document Number: 001-53413 Rev. *L

Page 57 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Figure 8-12. DAC Block Diagram

I

Range

source

1x,8x, 64x

Vout

Iout

Reference

Source

Scaler

R

3R

I _sinkRange

1x,8x, 64x

8.9.1 Current DAC

Figure 8-13. Mixer Configuration

The current DAC (IDAC) can be configured for the ranges 0 to

32 µA, 0 to 256 µA, and 0 to 2.048 mA. The IDAC can be

configured to source or sink current.

C2 = 1.7 pF

C1 = 850 fF

8.9.2 Voltage DAC

R^mix0 20 k or 40 k

For the voltage DAC (VDAC), the current DAC output is routed

through resistors. The two ranges available for the VDAC are 0

to 1.024 V and 0 to 4.096 V. In voltage mode any load connected

to the output of a DAC should be purely capacitive (the output of

the VDAC is not buffered).

sc_clk

R^mix0 20 k or 40 k

Vin

Vout

0

1

8.10 Up/Down Mixer

Vref

In continuous time mode, the SC/CT block components are used

to build an up or down mixer. Any mixing application contains an

input signal frequency and a local oscillator frequency. The

polarity of the clock, Fclk, switches the amplifier between

inverting or noninverting gain. The output is the product of the

input and the switching function from the local oscillator, with

frequency components at the local oscillator plus and minus the

signal frequency (Fclk + Fin and Fclk – Fin) and reduced-level

frequency components at odd integer multiples of the local

oscillator frequency. The local oscillator frequency is provided by

the selected clock source for the mixer.

sc_clk

8.11 Sample and Hold

The main application for a sample and hold, is to hold a value

stable while an ADC is performing a conversion. Some

applications require multiple signals to be sampled

simultaneously, such as for power calculations (V and I).

Figure 8-14. Sample and Hold Topology

(Φ1 and Φ2 are opposite phases of a clock)

Continuous time up and down mixing works for applications with

input signals and local oscillator frequencies up to 1 MHz.

Φ₁

Φ ₂

Φ₁

Φ²

C₁

C₂

V ⁱ

V_ref

n

V_out

Φ ₁

Φ₂

Φ¹

Φ₂

Φ₁

Φ₂

Φ ₁

Φ²

V _ref

V

ref

C₃

C₄

Document Number: 001-53413 Rev. *L

Page 58 of 126

PSoC^®3: CY8C36 Family

Data Sheet

8.11.1 Down Mixer

The PSoC Creator IDE software provides fully integrated

programming and debug support for PSoC devices. The low cost

MiniProg3 programmer and debugger is designed to provide full

programming and debug support of PSoC devices in conjunction

with the PSoC Creator IDE. PSoC JTAG, SWD, and SWV

interfaces are compatible with industry standard third party tools.

The SC/CT block can be used as a mixer to down convert an

input signal. This circuit is a high bandwidth passive sample

network that can sample input signals up to 14 MHz. This

sampled value is then held using the opamp with a maximum

clock rate of 4 MHz. The output frequency is at the difference

between the input frequency and the highest integer multiple of

the Local Oscillator that is less than the input.

All DOC circuits are disabled by default and can only be enabled

in firmware. If not enabled, the only way to reenable them is to

erase the entire device, clear flash protection, and reprogram the

device with new firmware that enables DOC. Disabling DOC

features, robust flash protection, and hiding custom analog and

digital functionality inside the PSoC device provide a level of

security not possible with multichip application solutions.

Additionally, all device interfaces can be permanently disabled

(Device Security) for applications concerned about phishing

attacks due to a maliciously reprogrammed device. Permanently

disabling interfaces is not recommended in most applications

because the you cannot access the device later. Because all

programming, debug, and test interfaces are disabled when

Device Security is enabled, PSoCs with Device Security enabled

may not be returned for failure analysis.

8.11.2 First Order Modulator – SC Mode

A first order modulator is constructed by placing the SC/CT block

in an integrator mode and using a comparator to provide a 1-bit

feedback to the input. Depending on this bit, a reference voltage

is either subtracted or added to the input signal. The block output

is the output of the comparator and not the integrator in the

modulator case. The signal is downshifted and buffered and then

processed by a decimator to make a delta-sigma converter or a

counter to make an incremental converter. The accuracy of the

sampled data from the first-order modulator is determined from

several factors.

The main application for this modulator is for a low frequency

ADC with high accuracy. Applications include strain gauges,

thermocouples, precision voltage, and current measurement.

Table 9-1. Debug Configurations

Debug and Trace Configuration

GPIO Pins Used

All debug and trace disabled

0

9. Programming, Debug Interfaces,

Resources

JTAG

4 or 5

SWD

2

1

3

PSoC devices include extensive support for programming,

testing, debugging, and tracing both hardware and firmware.

Three interfaces are available: JTAG, SWD, and SWV. JTAG and

SWD support all programming and debug features of the device.

JTAG also supports standard JTAG scan chains for board level

test and chaining multiple JTAG devices to a single JTAG

connection.

SWV

SWD + SWV

9.1 JTAG Interface

The IEEE 1149.1 compliant JTAG interface exists on four or five

pins (the nTRST pin is optional). The JTAG clock frequency can

be up to 8 MHz, or 1/3 of the CPU clock frequency for 8 and 16-bit

transfers, or 1/5 of the CPU clock frequency for 32-bit transfers,

whichever is least. By default, the JTAG pins are enabled on new

devices but the JTAG interface can be disabled, allowing these

pins to be used as General Purpose I/O (GPIO) instead. The

JTAG interface is used for programming the flash memory,

debugging, I/O scan chains, and JTAG device chaining.

For more information on PSoC 3 Programming, refer to the

application note AN62391 - In-System Programming for

PSoC^®3.

Complete Debug on Chip (DoC) functionality enables full device

debugging in the final system using the standard production

device. It does not require special interfaces, debugging pods,

simulators, or emulators. Only the standard programming

connections are required to fully support debug.

Document Number: 001-53413 Rev. *L

Page 59 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Figure 9-1. JTAG Interface Connections between PSoC 3 and Programmer

V_DD

Host Programmer

PSoC 3

1, 2, 3, 4

V_DD

V

_DDD, V_DDA, V_DDIO0, V_DDIO1, V_DDIO2, V_DDIO3

TCK (P1[1]

TCK

5

TMS

TMS (P1[0])

TDO

TDI

TDI (P1[4])

TDO (P1[3])

nTRST (P1[5]) ⁶

nTRST ⁶

XRES or P1[2] ^{4, 7}

V_SSD, V_SSA

XRES

GND

¹The voltage levels of Host Programmer and the PSoC 3 voltage domains involved in Programming should be same. The

Port 1 JTAG pins, XRES pin (XRES_N or P1[2]) are powered by V_DDIO1. So, V_DDIO1of PSoC 3 should be at same voltage

level as host V_DD. Rest of PSoC 3 voltage domains ( V_DDD, V_DDA, V_DDIO0, V_DDIO2, V_DDIO3) need not be at the same voltage level as

host Programmer.

2

Vdda must be greater than or equal to all other power supplies (Vddd, Vddio’s) in PSoC 3.

3

For Power cycle mode Programming, XRES pin is not required. But the Host programmer must have

the capability to toggle power (Vddd, Vdda, All Vddio’s) to PSoC 3. This may typically require external

interface circuitry to toggle power which will depend on the programming setup. The power supplies can

be brought up in any sequence, however, once stable, VDDA must be greater than or equal to all other

supplies.

4

For JTAG Programming, Device reset can also be done without connecting to the XRES pin or Power cycle mode by

using the TMS,TCK,TDI, TDO pins of PSoC 3, and writing to a specific register. But this requires that the DPS setting in

NVL is not equal to “Debug Ports Disabled”.

5

By default, PSoC 3 is configured for 4-wire JTAG mode unless user changes the DPS setting. So the TMS pin is

unidirectional. But if the DPS setting is changed to non-JTAG mode, the TMS pin in JTAG is bi-directional as the SWD

Protocol has to be used for acquiring the PSoC 3 device initially. After switching from SWD to JTAG mode, the TMS pin

will be uni-directional. In such a case, unidirectional buffer should not be used on TMS line.

6

nTRST JTAG pin (P1[5]) cannot be used to reset the JTAG TAP controlller during first time programming of PSoC 3 as

the default setting is 4-wire JTAG (nTRST disabled). Use the TMS, TCK pins to do a reset of JTAG TAP controller.

7

If XRES pin is used by host, P1[2] will be configured as XRES by default only for 48-pin devices (without dedicated XRES

pin). For devices with dedicated XRES pin, P1[2] is GPIO pin by default. So use P1[2] as Reset pin only for 48-pin

devices, but use dedicated XRES pin for rest of devices.

Document Number: 001-53413 Rev. *L

Page 60 of 126

PSoC^®3: CY8C36 Family

Data Sheet

SWD can be enabled on only one of the pin pairs at a time. This

only happens if, within 8 µs (key window) after reset, that pin pair

(JTAG or USB) receives a predetermined sequence of 1s and 0s.

SWD is used for debugging or for programming the flash

memory.

9.2 Serial Wire Debug Interface

The SWD interface is the preferred alternative to the JTAG

interface. It requires only two pins instead of the four or five

needed by JTAG. SWD provides all of the programming and

debugging features of JTAG at the same speed. SWD does not

provide access to scan chains or device chaining. The SWD

clock frequency can be up to 1/3 of the CPU clock frequency.

The SWD interface can be enabled from the JTAG interface or

disabled, allowing its pins to be used as GPIO. Unlike JTAG, the

SWD interface can always be reacquired on any device during

the key window. It can then be used to reenable the JTAG

interface, if desired. When using SWD or JTAG pins as standard

GPIO, make sure that the GPIO functionality and PCB circuits do

not interfere with SWD or JTAG use.

SWD uses two pins, either two of the JTAG pins (TMS and TCK)

or the USBIO D+ and D– pins. The USBIO pins are useful for in

system programming of USB solutions that would otherwise

require a separate programming connector. One pin is used for

the data clock and the other is used for data input and output.

Figure 9-2. SWD Interface Connections between PSoC 3 and Programmer

V_DD

Host Programmer

PSoC 3

1, 2, 3

V_DD

V_DDD, V_DDA, V_DDIO0, V_DDIO1, V_DDIO2, V_DDIO3

SWDCK

SWDCK (P1[1] or P15[7])

SWDIO (P1[0] or P15[6])

SWDIO

XRES

3, 4

XRES or P1[2]

GND

V_SSD, V_SSA

GND

1

The voltage levels of the Host Programmer and the PSoC 3 voltage domains involved in Programming

should be the same. XRES pin (XRES_N or P1[2]) is powered by V_DDIO1. The USB SWD pins are

powered by V_DDD. So for Programming using the USB SWD pins with XRES pin, the V_DDD, V_DDIO1of

PSoC 3 should be at the same voltage level as Host V_DD. Rest of PSoC 3 voltage domains ( V_DDA, V_DDIO0

V_DDIO2, V_DDIO3) need not be at the same voltage level as host Programmer. The Port 1 SWD pins are

powered by V_DDIO1. So V_DDIO1of PSoC 3 should be at same voltage level as host V_DDfor Port 1 SWD

,

programming. Rest of PSoC 3 voltage domains ( V_DDD, V_DDA, V_DDIO0, V_DDIO2, V_DDIO3) need not be at the same

voltage level as host Programmer.

2

Vdda must be greater than or equal to all other power supplies (Vddd, Vddio’s) in PSoC 3.

3

For Power cycle mode Programming, XRES pin is not required. But the Host programmer must have

the capability to toggle power (Vddd, Vdda, All Vddio’s) to PSoC 3. This may typically require external

interface circuitry to toggle power which will depend on the programming setup. The power supplies can

be brought up in any sequence, however, once stable, VDDA must be greater than or equal to all other

supplies.

4

P1[2] will be configured as XRES by default only for 48-pin devices (without dedicated XRES pin). For

devices with dedicated XRES pin, P1[2] is GPIO pin by default. So use P1[2] as Reset pin only for 48-

pin devices, but use dedicated XRES pin for rest of devices.

Document Number: 001-53413 Rev. *L

Page 61 of 126

PSoC^®3: CY8C36 Family

Data Sheet

9.3 Debug Features

9.6 Programming Features

Using the JTAG or SWD interface, the CY8C36 supports the

following debug features:

The JTAG and SWD interfaces provide full programming

support. The entire device can be erased, programmed, and

verified. You can increase flash protection levels to protect

firmware IP. Flash protection can only be reset after a full device

erase. Individual flash blocks can be erased, programmed, and

verified, if block security settings permit.

Halt and single-step the CPU

View and change CPU and peripheral registers, and RAM

addresses

9.7 Device Security

Eight program address breakpoints

PSoC 3 offers an advanced security feature called device

security, which permanently disables all test, programming, and

debug ports, protecting your application from external access.

The device security is activated by programming a 32-bit key

(0×50536F43) to a Write Once Latch (WOL).

One memory access breakpoint—break on reading or writing

any memory address and data value

Break on a sequence of breakpoints (non recursive)

Debugging at the full speed of the CPU

The WOL is a type of nonvolatile latch (NVL). The cell itself is an

NVL with additional logic wrapped around it. Each WOL device

contains four bytes (32 bits) of data. The wrapper outputs a ‘1’ if

a super-majority (28 of 32) of its bits match a pre-determined

pattern (0×50536F43); it outputs a ‘0’ if this majority is not

reached. When the output is 1, the Write Once NV latch locks the

part out of Debug and Test modes; it also permanently gates off

the ability to erase or alter the contents of the latch. Matching all

bits is intentionally not required, so that single (or few) bit failures

do not deassert the WOL output. The state of the NVL bits after

wafer processing is truly random with no tendency toward 1 or 0.

Debug operations are possible while the device is reset, or in

low-power modes

CompatiblewithPSoCCreatorandMiniProg3programmerand

debugger

Standard JTAG programming and debugging interfaces make

CY8C36 compatible with other popular third-party tools (for

example, ARM / Keil)

9.4 Trace Features

The WOL only locks the part after the correct 32-bit key

(0×50536F43) is loaded into the NVL's volatile memory,

programmed into the NVL's nonvolatile cells, and the part is

reset. The output of the WOL is only sampled on reset and used

to disable the access. This precaution prevents anyone from

reading, erasing, or altering the contents of the internal memory.

The user can write the key into the WOL to lock out external

access only if no flash protection is set (see “Flash Security” on

page 20). However, after setting the values in the WOL, a user

still has access to the part until it is reset. Therefore, a user can

write the key into the WOL, program the flash protection data,

and then reset the part to lock it.

The CY8C36 supports the following trace features when using

JTAG or SWD:

Trace the 8051 program counter (PC), accumulator register

(ACC), and one SFR / 8051 core RAM register

Trace depth up to 1000 instructions if all registers are traced,

or 2000 instructions if only the PC is traced (on devices that

include trace memory)

Program address trigger to start tracing

Trace windowing, that is, only trace when the PC is within a

given range

If the device is protected with a WOL setting, Cypress cannot

perform failure analysis and, therefore, cannot accept RMAs

from customers. The WOL can be read out through the SWD port

to electrically identify protected parts. The user can write the key

in WOL to lock out external access only if no flash protection is

set. For more information on how to take full advantage of the

security features in PSoC see the PSoC 3 TRM.

Two modes for handling trace buffer full: continuous (overwriting

the oldest trace data) or break when trace buffer is full

9.5 Single Wire Viewer Interface

The SWV interface is closely associated with SWD but can also

be used independently. SWV data is output on the JTAG

interface’s TDO pin. If using SWV, you must configure the device

for SWD, not JTAG. SWV is not supported with the JTAG

interface.

Disclaimer

Note the following details of the flash code protection features on

Cypress devices.

SWV is ideal for application debug where it is helpful for the

firmware to output data similar to 'printf' debugging on PCs. The

SWV is ideal for data monitoring, because it requires only a

single pin and can output data in standard UART format or

Manchester encoded format. For example, it can be used to tune

a PID control loop in which the output and graphing of the three

error terms greatly simplifies coefficient tuning.

Cypress products meet the specifications contained in their

particular Cypress data sheets. Cypress believes that its family

of products is one of the most secure families of its kind on the

market today, regardless of how they are used. There may be

methods, unknown to Cypress, that can breach the code

protection features. Any of these methods, to our knowledge,

would be dishonest and possibly illegal. Neither Cypress nor any

other semiconductor manufacturer can guarantee the security of

their code. Code protection does not mean that we are

guaranteeing the product as “unbreakable.”

Cypress is willing to work with the customer who is concerned

about the integrity of their code. Code protection is constantly

evolving. We at Cypress are committed to continuously

improving the code protection features of our products.

The following features are supported in SWV:

32 virtual channels, each 32 bits long

Simple, efficient packing and serializing protocol

Supports standard UART format (N81)

Document Number: 001-53413 Rev. *L

Page 62 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Application Notes: PSoC application notes discuss a particular

application of PSoC in depth; examples include brushless DC

motor control and on-chip filtering. Application notes often

include example projects in addition to the application note

document.

10. Development Support

The CY8C36 family has a rich set of documentation,

development tools, and online resources to assist you during

your development process. Visit

psoc.cypress.com/getting-started to find out more.

Technical Reference Manual: The Technical Reference Manual

(TRM) contains all the technical detail you need to use a PSoC

device, including a complete description of all PSoC registers.

10.1 Documentation

A suite of documentation, supports the CY8C36 family to ensure

that you can find answers to your questions quickly. This section

contains a list of some of the key documents.

10.2 Online

In addition to print documentation, the Cypress PSoC forums

connect you with fellow PSoC users and experts in PSoC from

around the world, 24 hours a day, 7 days a week.

Software User Guide: A step-by-step guide for using PSoC

Creator. The software user guide shows you how the PSoC

Creator build process works in detail, how to use source control

with PSoC Creator, and much more.

10.3 Tools

With industry standard cores, programming, and debugging

interfaces, the CY8C36 family is part of a development tool

ecosystem. Visit us at www.cypress.com/go/psoccreator for the

latest information on the revolutionary, easy to use PSoC Creator

IDE, supported third party compilers, programmers, debuggers,

and development kits.

Component data sheets: The flexibility of PSoC allows the

creation of new peripherals (components) long after the device

has gone into production. Component data sheets provide all of

the information needed to select and use a particular component,

including a functional description, API documentation, example

code, and AC/DC specifications.

Document Number: 001-53413 Rev. *L

Page 63 of 126

PSoC^®3: CY8C36 Family

Data Sheet

11. Electrical Specifications

Specifications are valid for –40 °C ≤ T_A≤ 85 °C and T_J≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

except where noted. The unique flexibility of the PSoC UDBs and analog blocks enable many functions to be implemented in PSoC

Creator components, see the component data sheets for full AC/DC specifications of individual functions. See the “Example

Peripherals” section on page 39 for further explanation of PSoC Creator components.

11.1 Absolute Maximum Ratings

Table 11-1. Absolute Maximum Ratings DC Specifications

Parameter

T_STG

Description

Storage temperature

Conditions

Min

Typ

Max

Units

Higher storage temperatures

reduce NVL data retention time.

Recommended storage temper-

ature is +25 °C ±25 °C. Extended

duration storage temperatures

above 85 °C degrade reliability.

–55

25

100

°C

V_DDA

V_DDD

Analog supply voltage relative to

V_SSA

–0.5

–

6

V

Digital supply voltage relative to

V_SSD

V_DDIO

V_CCA

V_CCD

V_SSA

I/O supply voltage relative to V_SSD

Direct analog core voltage input

Direct digital core voltage input

Analog ground voltage

–0.5

–

6

V

1.95

–0.5

V_SSD– 0.5

V_SSD

0.5

+

[20]

V_GPIO

DC input voltage on GPIO

DC input voltage on SIO

Includes signals sourced by V_DDAV_SSD– 0.5

and routed internal to the pin

–

V_DDIO

0.5

+

V

V_SIO

Output disabled

Output enabled

V_SSD– 0.5

–

7

6

V

V_SSD– 0.5

V_IND

Voltage at boost converter input

Boost converter supply

0.5

5.5

100

2

V

V_BAT

Ivddio

V_SSD– 0.5

V

Current per V_DDIOsupply pin

ADC external reference inputs

Latch up current^[21]

–

mA

V

Vextref

LU

Pins P0[3], P3[2]

–140

750

500

140

–

mA

V

ESD_HBM

ESD_CDM

Electrostatic discharge voltage

Human body model

Charge device model

–

V

Note Usage above the absolute maximum conditions listed in Table 11-1 may cause permanent damage to the device. Exposure to

maximum conditions for extended periods of time may affect device reliability. When used below maximum conditions but above

normal operating conditions the device may not operate to specification.

Notes

20. The V_DDIOsupply voltage must be greater than the maximum analog voltage on the associated GPIO pins. Maximum analog voltage on GPIO pin ≤ V_DDIO≤ V_DDA

21. Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch-up Test.

.

Document Number: 001-53413 Rev. *L

Page 64 of 126

PSoC^®3: CY8C36 Family

Data Sheet

11.2 Device Level Specifications

Specifications are valid for –40 °C ≤ T_A≤ 85 °C and T_J≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

except where noted.

11.2.1 Device Level Specifications

Table 11-2. DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

V_DDA

Analog supply voltage and input to Analog core regulator enabled

analog core regulator

1.8

–

5.5

V

V_DDA

V_DDD

Analog supply voltage, analog

regulator bypassed

Analog core regulator disabled

Digital core regulator enabled

Digital core regulator disabled

1.71

1.8

–

1.89

V

[22]

Digital supply voltage relative to

V_SSD

V_DDA

Digital supply voltage, digital

regulator bypassed

1.71

1.8

1.89

[23]

[22]

V_DDIO

I/O supply voltage relative to V_SSIO

1.71

–

V_DDA

1.89

V

V_CCA

Direct analog core voltage input

(Analog regulator bypass)

Analog core regulator disabled

Digital core regulator disabled

1.8

V_CCD

Direct digital core voltage input

(Digital regulator bypass)

1.71

1.8

1.89

V

[24]

I_DD

Active Mode, V_DD= 1.71 V–5.5 V

Bus clock off. Execute from CPU

instruction buffer. See “Flash

Program Memory” on page 20.

CPU at 3 MHz

CPU at 6 MHz

CPU at 12 MHz

CPU at 24 MHz

CPU at 48 MHz

CPU at 62.6 MHz

T = –40 °C

–

0.8

–

mA

T = 25 °C

T = 85 °C

T = –40 °C

T = 25 °C

T = 85 °C

T = –40 °C

T = 25 °C

T = 85 °C

T = –40 °C

T = 25 °C

T = 85 °C

T = –40 °C

T = 25 °C

T = 85 °C

T = –40 °C

T = 25 °C

T = 85 °C

–

1.2

–

2.0

–

3.5

–

6.6

–

9.0

–

V_DD= 3.3 V, T = 25 °C, IMO and bus CPU at 3 MHz

clock enabled, ILO = 1 kHz, CPU

executing from flash and accessing

SRAM, all other blocks off, all I/Os

1.4

2.2

3.6

6.4

11.8

15.8

CPU at 6 MHz

CPU at 12 MHz

CPU at 24 MHz

CPU at 48 MHz

CPU at 62.6 MHz

tied low.

Notes

22. The power supplies can be brought up in any sequence however once stable V_DDAmust be greater than or equal to all other supplies.

23. The V_DDIOsupply voltage must be greater than the maximum analog voltage on the associated GPIO pins. Maximum analog voltage on GPIO pin ≤ V_DDIO≤ V_DDA

.

24. The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective data sheets, available in

PSoC Creator, the integrated design environment. To estimate total current, find CPU current at frequency of interest and add peripheral currents for your particular

system from the device data sheet and component data sheets.

Document Number: 001-53413 Rev. *L

Page 65 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Table 11-2. DC Specifications (continued)

Parameter

Description

Sleep Mode^[26]

Conditions

Min

Typ

Max

Units

CPU = OFF

V

_DD= V_DDIO= 4.5–5.5 V T = –40 °C

–

1

–

µA

RTC = ON (= ECO32K ON, in

low-power mode)

Sleep timer = ON (= ILO ON at

1 kHz)^[27]

T = 25 °C

T = 85 °C

V_DD= V_DDIO= 2.7–3.6 V T = –40 °C

WDT = OFF

T = 25 °C

I²C Wake = OFF

T = 85 °C

V_DD= V_DDIO= 1.71–1.95 V T = –40 °C

T = 25 °C

Comparator = OFF

POR = ON

Boost = OFF

SIO pins in single ended input,

unregulated output mode

T = 85 °C

Comparator = ON

CPU = OFF

V_DD= V_DDIO= 2.7–3.6 V T = 25 °C

–

µA

RTC = OFF

Sleep timer = OFF

WDT = OFF

I2C Wake = OFF

POR = ON

Boost = OFF

SIO pins in single ended input,

unregulated output mode

I2C Wake = ON

CPU = OFF

V_DD= V_DDIO= 2.7–3.6 V T = 25 °C

–

µA

RTC = OFF

Sleep timer = OFF

WDT = OFF

Comparator = OFF

POR = ON

Boost = OFF

SIO pins in single ended input,

unregulated output mode

Hibernate Mode^[26]

V

_DD= V_DDIO= 4.5–5.5 V T = –40 °C

–

nA

T = 25 °C

T = 85 °C

Hibernate mode current

All regulators and oscillators off.

SRAM retention

GPIO interrupts are active

Boost = OFF

SIO pins in single ended input,

unregulated output mode

–

V_DD= V_DDIO= 2.7–3.6 V T = –40 °C

–

T = 25 °C

200

–

T = 85 °C

V_DD= V_DDIO= 1.71–1.95 V T = –40 °C

T = 25 °C

–

T = 85 °C

–

Notes

25. The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective data sheets, available in

PSoC Creator, the integrated design environment. To compute total current, find CPU current at frequency of interest and add peripheral currents for your particular

system from the device data sheet and component data sheets.

26. If V_CCDand V_CCAare externally regulated, the voltage difference between V_CCDand V_CCAmust be less than 50 mV.

27. Sleep timer generates periodic interrupts to wake up the CPU. This specification applies only to those times that the CPU is off.

Document Number: 001-53413 Rev. *L

Page 66 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Figure 11-1. Active Mode Current vs F_CPU, V_DD= 3.3 V,

Temperature = 25 °C

Figure 11-2. Active Mode Current vs Temperature and F_CPU

V_DD= 3.3 V

,

Figure 11-3. Active Mode Current vs V_DDand Temperature,

F_CPU= 24 MHz

Document Number: 001-53413 Rev. *L

Page 67 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Table 11-3. AC Specifications^[28]

Parameter Description

F_CPU

Conditions

1.71 V ≤ V_DDD≤ 5.5 V

Min

DC

–

Typ

–

Max

67.01

1

Units

MHz

V/ns

µs

CPU frequency

Bus frequency

F_BUSCLK

Svdd

–

V_DDramp rate

–

T_{IO_INIT}

Time from V_DDD/V_DDA/V_CCD/V_CCA

≥ IPOR to I/O ports set to their reset

states

–

10

T_STARTUP

Time from V_DDD/V_DDA/V_CCD/V_CCA

≥ PRES to CPU executing code at V_DDA/V_DDD, no PLL used, fast IMO

reset vector

V

_CCA/V_DDA= regulated from

–

33

66

15

µs

boot mode (48 MHz typ.)

V

_CCA/V_CCD= regulated from

_DDA/V_DDD, no PLL used, slow

IMO boot mode (12 MHz typ.)

T_SLEEP

Wakeup from sleep mode –

Application of non–LVD interrupt to

beginning of execution of next CPU

instruction

T_HIBERNATE

Wakeup from hibernate mode –

Application of external interrupt to

beginning of execution of next CPU

instruction

–

100

µs

Figure 11-4. F_CPUvs. V_DD

5.5 V

Valid Operating Region

3.3 V

1.71 V

0.5 V

Valid Operating Region with SMP

0 V

DC

1 MHz

10 MHz

67 MHz

CPU Frequency

Note

28. Based on device characterization (Not production tested).

Document Number: 001-53413 Rev. *L

Page 68 of 126

PSoC^®3: CY8C36 Family

Data Sheet

11.3 Power Regulators

Specifications are valid for –40 °C ≤ T_A≤ 85 °C and T_J≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

except where noted.

11.3.1 Digital Core Regulator

Table 11-4. Digital Core Regulator DC Specifications

Parameter

V_DDD

Description

Input voltage

Conditions

Min

1.8

–

Typ

–

Max

5.5

–

Units

V

V_CCD

Output voltage

1.80

1

V

Regulator output capacitor

± 10%, ×5R ceramic or better. The two

–

µF

V

_CCDpins must be shorted together, with

as short a trace as possible, see Power

System on page 28

Figure 11-5. Regulators V_CCvs V_DD

Figure 11-6. Digital Regulator PSRR vs Frequency and V_DD

11.3.2 Analog Core Regulator

Table 11-5. Analog Core Regulator DC Specifications

Parameter

V_DDA

Description

Input voltage

Conditions

Min

1.8

–

Typ

–

Max

5.5

–

Units

V

V_CCA

Output voltage

1.80

1

V

Regulator output capacitor

±10%, ×5R ceramic or better

–

µF

Figure 11-7. Analog Regulator PSRR vs Frequency and V_DD

Document Number: 001-53413 Rev. *L

Page 69 of 126

PSoC^®3: CY8C36 Family

Data Sheet

11.3.3 Inductive Boost Regulator.

Table 11-6. Inductive Boost Regulator DC Specifications

Unless otherwise specified, operating conditions are: V_BAT= 2.4 V, V_OUT= 2.7 V, I_OUT= 40 mA, F_SW= 400 kHz, L_BOOST= 10 µH,

_BOOST= 22 µF || 0.1 µF

C

Parameter Description

V_BAT

Conditions

T=-35 °C to +65 °C

Min

0.5

0.68

–

Typ

–

Max

3.6

50

Units

V

Input voltage

Includes startup

Over entire temperature range

–

V

I_OUT

Load current^{[29, 30]}

V_BAT= 1.6 – 3.6 V, V_OUT= 3.6 – 5.0 V,

external diode

–

mA

V_BAT= 1.6 – 3.6 V, V_OUT= 1.6 – 3.6 V,

internal diode

–

75

30

20

15

mA

V_BAT= 0.8 – 1.6 V, V_OUT= 1.6 – 3.6 V,

internal diode

V_BAT= 0.8 – 1.6 V, V_OUT= 3.6 – 5.0 V,

external diode

V_BAT= 0.5 – 0.8 V, V_OUT= 1.6 – 3.6 V,

internal diode

I_LPK

I_Q

Inductor peak current

Quiescent current

–

700

–

mA

µA

Boost active mode

200

12

Boost standby mode, 32 khz external crystal

oscillator, I_OUT< 1 µA

–

V_OUT

Boost voltage range^{[33, 32]}

1.8 V

1.71

1.81

1.90

2.28

2.57

2.85

3.14

3.42

4.75

–

1.80

1.90

2.00

2.40

2.70

3.00

3.30

3.60

5.00

–

1.89

2.00

2.10

2.52

2.84

3.15

3.47

3.78

5.25

3.8

V

1.9 V

2.0 V

V

2.4 V

V

2.7 V

V

3.0 V

V

3.3 V

V

3.6 V

V

5.0 V

External diode required

V

Reg_LOAD

Reg_LINE

η

Load regulation

Line regulation

Efficiency

%

–

4.1

L_BOOST= 10 µH

L_BOOST= 22 µH

70

85

–

82

90

–

Notes

29. For output voltages above 3.6 V, an external diode is required.

30. Maximum output current applies for output voltages ≤ 4x input voltage.

31. Based on device characterization (Not production tested).

32. At boost frequency of 2 MHz, V_OUTis limited to 2 x V_BAT. At 400 kHz, V_OUTis limited to 4 x V_BAT

.

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PSoC^®3: CY8C36 Family

Data Sheet

Table 11-7. Inductive Boost Regulator AC Specifications

Unless otherwise specified, operating conditions are: V_BAT= 2.4 V, V_OUT= 2.7 V, I_OUT= 40 mA, F_SW= 400 kHz, L_BOOST= 10 µH,

_BOOST= 22 µF || 0.1 µF.

Parameter Description

V_RIPPLE

C

Conditions

Min

Typ

Max

Units

Ripple voltage

(peak-to-peak)

V_OUT= 1.8 V, F_SW= 400 kHz, I_OUT= 10 mA

–

100

mV

F_SW

Switching frequency

–

0.1, 0.4,

or 2

–

MHz

Table 11-8. Recommended External Components for Boost Circuit

Parameter

L_BOOST

C_BOOST

I_F

Description

Boost inductor

Filter capacitor^[33]

Conditions

Min

4.7

10

1

Typ

10

22

–

Max

Units

µH

µF

47

–

External Schottky diode

average forward current

External Schottky diode is required for

A

V_OUT> 3.6 V

V_R

20

–

V

Figure 11-8. Efficiency vs V_OUT

I_OUT= 30 mA, V_BATranges from 0.7 V to V_OUT, L_BOOST= 22 µH

Figure 11-9. Efficiency vs V_BAT

I_OUT= 30 mA, V_OUT= 3.3 V, L_BOOST= 22 µH

Note

33. Based on device characterization (Not production tested).

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PSoC^®3: CY8C36 Family

Data Sheet

Figure 11-10. Efficiency vs I_OUT

V_BAT= 2.4 V, V_OUT= 3.3 V

Figure 11-11. Efficiency vs I_OUT

V_BATranges from 0.7 V to 3.3 V, L_BOOST= 22 µH

Figure 11-12. Efficiency vs Switching Frequency

V_OUT= 3.3 V, V_BAT= 2.4 V, I_OUT= 40 mA

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PSoC^®3: CY8C36 Family

Data Sheet

11.4 Inputs and Outputs

Specifications are valid for –40 °C ≤ T_A≤ 85 °C and T_J≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

except where noted. Unless otherwise specified, all charts and graphs show typical values.

11.4.1 GPIO

Table 11-9. GPIO DC Specifications

Parameter

Description

Input voltage high threshold

Input voltage low threshold

Input voltage high threshold

Conditions

Min

Typ

–

Max

Units

V_IH

V_IL

V_IH

CMOS Input, PRT[×]CTL = 0 0.7 × V_DDIO

CMOS Input, PRT[×]CTL = 0

–

V

–

0.3 × V_DDIO

LVTTL Input, PRT[×]CTL =

1,V_DDIO< 2.7 V

0.7 × V_DDIO

–

V_IH

V_IL

Input voltage high threshold

Input voltage low threshold

Output voltage high

LVTTL Input, PRT[×]CTL = 1,

V_DDIO≥ 2.7V

LVTTL Input, PRT[×]CTL =

1,V_DDIO< 2.7 V

2.0

–

0.3 × V_DDIO

0.8

V

V_IL

LVTTL Input, PRT[×]CTL = 1,

V_DDIO≥ 2.7V

I_OH= 4 mA at 3.3 V_DDIO

I_OH= 1 mA at 1.8 V_DDIO

I_OL= 8 mA at 3.3 V_DDIO

I_OL= 4 mA at 1.8 V_DDIO

–

V_OH

V_DDIO– 0.6

–

V

V_DDIO– 0.5

V_OL

Output voltage low

–

0.6

8.5

2

V

–

V

Rpullup

Pull-up resistor

3.5

–

5.6

–

kΩ

nA

pF

mV

Rpulldown Pull-down resistor

I_IL

Input leakage current (absolute value)^[34]25 °C, V_DDIO= 3.0 V

Input capacitance^[34]

C_IN

GPIOs without opamp outputs

GPIOs with opamp outputs

–

7

–

18

–

V_H

Input voltage hysteresis

(Schmitt-Trigger)^[34]

–

40

Idiode

Current through protection diode to

–

100

µA

V_DDIOand V_SSIO

Rglobal

Rmux

Resistance pin to analog global bus

Resistance pin to analog mux bus

25 °C, V_DDIO= 3.0 V

–

320

220

–

Ω

Figure 11-13. GPIO Output High Voltage and Current

Figure 11-14. GPIO Output Low Voltage and Current

Note

34. Based on device characterization (Not production tested).

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Data Sheet

Table 11-10. GPIO AC Specifications

Parameter

TriseF

Description

Conditions

Min

–

Typ

–

Max

12

60

–

Units

ns

Rise time in Fast Strong Mode^[35]

Fall time in Fast Strong Mode^[35]

Rise time in Slow Strong Mode^[35]

Fall time in Slow Strong Mode^[35]

GPIO output operating frequency

3.3 V V_DDIOCload = 25 pF

TfallF

–

ns

TriseS

TfallS

–

ns

–

ns

–

2.7 V < V_DDIO< 5.5 V, fast strong drive 90/10% V_DDIOinto 25 pF

mode

–

33

MHz

1.71 V < V_DDIO< 2.7 V, fast strong drive 90/10% V_DDIOinto 25 pF

mode

–

20

7

MHz

Fgpioout

3.3 V < V_DDIO< 5.5 V, slow strong drive 90/10% V_DDIOinto 25 pF

mode

1.71 V < V_DDIO< 3.3 V, slow strong

drive mode

90/10% V_DDIOinto 25 pF

3.5

GPIO input operating frequency

1.71 V < V_DDIO< 5.5 V

Fgpioin

90/10% V_DDIO

–

66

MHz

Figure 11-15. GPIO Output Rise and Fall Times, Fast Strong

Mode, V_DDIO= 3.3 V, 25 pF Load

Figure 11-16. GPIO Output Rise and Fall Times, Slow Strong

Mode, V_DDIO= 3.3 V, 25 pF Load

Note

35. Based on device characterization (Not production tested).

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PSoC^®3: CY8C36 Family

Data Sheet

11.4.2 SIO

Table 11-11. SIO DC Specifications

Parameter

Vinmax

Description

Conditions

Min

Typ

Max

Units

Maximum input voltage

All allowed values of Vddio and

Vddd, see Section 11.2.1

–

5.5

V

Vinref

Input voltage reference (Differ-

ential input mode)

0.5

–

0.52 × V_DDIO

V

Output voltage reference (Regulated output mode)

V_DDIO> 3.7

Voutref

1

–

V_DDIO– 1

V_DDIO– 0.5

V

V_DDIO< 3.7

Input voltage high threshold

GPIO mode

Differential input mode^[36]

Input voltage low threshold

GPIO mode

Differential input mode^[36]

Output voltage high

Unregulated mode

Regulated mode^[36]

Output voltage low

V_IH

CMOS input

0.7 × V_DDIO

SIO_ref + 0.2

–

V

Hysteresis disabled

V_IL

CMOS input

–

0.3 × V_DDIO

SIO_ref – 0.2

V

Hysteresis disabled

I_OH= 4 mA, V_DDIO= 3.3 V

I_OH= 1 mA

I_OH= 0.1 mA

V_DDIO– 0.4

SIO_ref – 0.65

SIO_ref – 0.3

–

V

V_OH

SIO_ref + 0.2

V_OL

V

_DDIO= 3.30 V, I_OL= 25 mA

–

0.8

0.4

8.5

–

V

V_DDIO= 1.80 V, I_OL= 4 mA

Rpullup

Rpulldown

I_IL

Pull-up resistor

3.5

–

5.6

–

kΩ

–

Pull-down resistor

Input leakage current (absolute

value)^[37]

V_IH< Vddsio

V_IH> Vddsio

Input Capacitance^[37]

25 °C, Vddsio = 3.0 V, V_IH= 3.0 V

25 °C, Vddsio = 0 V, V_IH= 3.0 V

–

14

10

7

nA

µA

pF

C_IN

V_H

–

Input voltage hysteresis

(Schmitt-Trigger)^[37]

Single ended mode (GPIO mode)

Differential mode

40

35

–

mV

µA

–

Current through protection diode

to V_SSIO

100

Idiode

Notes

36. See Figure 6-9 on page 34 and Figure 6-12 on page 37 for more information on SIO reference.

37. Based on device characterization (Not production tested)

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PSoC^®3: CY8C36 Family

Data Sheet

Figure 11-17. SIO Output High Voltage and Current,

Unregulated Mode

Figure 11-18. SIO Output Low Voltage and Current,

Unregulated Mode

Figure 11-19. SIO Output High Voltage and Current, Regulat-

ed Mode

Table 11-12. SIO AC Specifications

Parameter

TriseF

Description

Conditions

Min

Typ

Max

Units

Rise time in Fast Strong Mode

(90/10%)^[37]

Cload = 25 pF, V_DDIO= 3.3 V

–

12

ns

TfallF

TriseS

TfallS

Fall time in Fast Strong Mode

(90/10%)^[37]

Cload = 25 pF, V_DDIO= 3.3 V

Cload = 25 pF, V_DDIO= 3.0 V

–

12

75

60

ns

Rise time in Slow Strong Mode

(90/10%)^[37]

Fall time in Slow Strong Mode

(90/10%)^[37]

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PSoC^®3: CY8C36 Family

Data Sheet

Table 11-12. SIO AC Specifications (continued)

Parameter

Description

Conditions

Min

Typ

Max

Units

SIO output operating frequency

2.7 V < V_DDIO< 5.5 V, Unregu-

lated output (GPIO) mode, fast

strong drive mode

90/10% V_DDIOinto 25 pF

–

33

MHz

1.71 V < V_DDIO< 2.7 V, Unregu- 90/10% V_DDIOinto 25 pF

lated output (GPIO) mode, fast

strong drive mode

–

16

5

MHz

3.3 V < V_DDIO< 5.5 V, Unregu-

lated output (GPIO) mode, slow

strong drive mode

90/10% V_DDIOinto 25 pF

1.71 V < V_DDIO< 3.3 V, Unregu- 90/10% V_DDIOinto 25 pF

lated output (GPIO) mode, slow

strong drive mode

4

Fsioout

2.7 V < V_DDIO< 5.5 V, Regulated Output continuously switching

20

10

2.5

output mode, fast strong drive

mode

into 25 pF

1.71 V < V_DDIO< 2.7 V, Regulated Output continuously switching

output mode, fast strong drive

mode

into 25 pF

1.71 V < V_DDIO< 5.5 V, Regulated Output continuously switching

output mode, slow strong drive

mode

into 25 pF

SIO input operating frequency

1.71 V < V_DDIO< 5.5 V

Fsioin

90/10% V_DDIO

–

66

MHz

Figure 11-20. SIO Output Rise and Fall Times, Fast Strong

Mode, V_DDIO= 3.3 V, 25 pF Load

Figure 11-21. SIO Output Rise and Fall Times, Slow Strong

Mode, V_DDIO= 3.3 V, 25 pF Load

11.4.3 USBIO

For operation in GPIO mode, the standard range for V_DDDapplies, see Device Level Specifications on page 65.

Table 11-13. USBIO DC Specifications

Parameter

Rusbi

Description

USB D+ pull-up resistance

Static output high

Conditions

With idle bus

Min

0.900

1.425

2.8

Typ

–

Max

1.575

3.090

3.6

Units

kΩ

Rusba

While receiving traffic

–

kΩ

Vohusb

15 kΩ ±5% to Vss, internal pull-up

enabled

–

V

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PSoC^®3: CY8C36 Family

Data Sheet

Table 11-13. USBIO DC Specifications

Parameter Description

Volusb Static output low

Conditions

Min

Typ

Max

Units

15 kΩ ±5% to Vss, internal pull-up

–

0.3

V

enabled

Vihgpio

Vilgpio

Vohgpio

Volgpio

Vdi

Input voltage high, GPIO mode

Input voltage low, GPIO mode

Output voltage high, GPIO mode

Output voltage low, GPIO mode

Differential input sensitivity

V

I

≥ 3 V

2

–

V

DDD

0.8

–

= 4 mA, V

≥ 3 V

2.4

–

OH

DDD

I

0.3

0.2

2.5

OL

DDD

|(D+)–(D–)|

–

Vcm

Differential input common mode

range

–

0.8

Vse

Single ended receiver threshold

PS/2 pull-up resistance

–

0.8

3

–

2

7

V

Rps2

In PS/2 mode, with PS/2 pull-up

enabled

kΩ

External USB series resistor

In series with each USB pin

21.78

(–1%)

22

22.22

(+1%)

Ω

Rext

Zo

USB driver output impedance

Including Rext

28

–

44

20

2

Ω

C

USB transceiver input capacitance

pF

nA

IN

I

Input leakage current (absolute value) 25 °C, V

= 3.0 V

–

IL

DDD

Figure 11-22. USBIO Output High Voltage and Current, GPIO

Mode

Figure 11-23. USBIO Output Low Voltage and Current, GPIO

Mode

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PSoC^®3: CY8C36 Family

Data Sheet

Table 11-14. USBIO AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Tdrate

Full-speed data rate average bit rate

12 – 0.25%

12

12 +

0.25%

MHz

Tjr1

Receiver data jitter tolerance to next transition

Receiver data jitter tolerance to pair transition

Driver differential jitter to next transition

Driver differential jitter to pair transition

–8

–5

–

8

5

ns

Tjr2

Tdj1

Tdj2

Tfdeop

–3.5

–4

3.5

4

Source jitter for differential transition to SE0

transition

–2

5

Tfeopt

Tfeopr

Tfst

Source SE0 interval of EOP

160

82

–

175

–

ns

Receiver SE0 interval of EOP

Width of SE0 interval during differential transition

14

20

6

ns

Fgpio_out GPIO mode output operating frequency

3 V ≤ V_DDD≤ 5.5 V

–

MHz

ns

V_DDD= 1.71 V

–

Tr_gpio

Tf_gpio

Rise time, GPIO mode, 10%/90% V_DDD

Fall time, GPIO mode, 90%/10% V_DDD

V_DDD> 3 V, 25 pF load

V_DDD= 1.71 V, 25 pF load

V_DDD> 3 V, 25 pF load

–

12

40

12

40

–

ns

–

ns

V_DDD= 1.71 V, 25 pF load

–

ns

Figure11-24. USBIOOutputRiseandFallTimes, GPIOMode,

_DDD= 3.3 V, 25 pF Load

V

Table 11-15. USB Driver AC Specifications

Parameter Description

Tr Transition rise time

Conditions

Min

–

Typ

Max

20

Units

ns

–

Tf

Transition fall time

–

20

ns

TR

Rise/fall time matching

V

_{USB_5}, V_{USB_3.3}, see USB DC

90%

111%

Specifications on page 99

Vcrs

Output signal crossover voltage

1.3

–

2

V

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PSoC^®3: CY8C36 Family

Data Sheet

11.4.4 XRES

Table 11-16. XRES DC Specifications

Parameter

V_IH

Description

Input voltage high threshold

Input voltage low threshold

Conditions

Min

0.7 × V_DDIO

–

Typ

–

Max

Units

–

V

V_IL

–

0.3 ×

V_DDIO

Rpullup

C_IN

Pull-up resistor

Input capacitance^[39]

3.5

–

5.6

3

8.5

–

kΩ

pF

V_H

Input voltage hysteresis

(Schmitt–Trigger)^[39]

–

100

–

mV

Idiode

Current through protection diode to

V_DDIOand V_SSIO

–

100

µA

Table 11-17. XRES AC Specifications

Parameter

Description

Reset pulse width

Conditions

Min

Typ

Max

Units

T_RESET

1

–

µs

38.

11.5 Analog Peripherals

Specifications are valid for –40 °C ≤ T_A≤ 85 °C and T_J≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

except where noted.

11.5.1 Opamp

Table 11-18. Opamp DC Specifications

Parameter

V_IOFF

Description

Input offset voltage

Conditions

Min

–

Typ

–

Max

2

Units

mV

Vos

–

2.5

2

mV

Operating temperature –40 °C to

70 °C

–

mV

TCVos

Ge1

Cin

Input offset voltage drift with temperature Power mode = high

–

±30

±0.1

18

µV / °C

Gain error, unity gain buffer mode

Input capacitance

Rload = 1 kΩ

%

pF

V

Routing from pin

Vo

Output voltage range

1 mA, source or sink, power mode = V

high

+ 0.05

V

–

SSA

DDA

0.05

Iout

Output current, source or sink

V

+ 500 mV ≤ Vout ≤ V

25

16

–

mA

SSA

DDA

–500 mV, V

> 2.7 V

DDA

V

+ 500 mV ≤ Vout ≤ V

–

SSA

DDA

–500 mV, 1.7 V = V

Power mode = min

Power mode = low

≤ 2.7 V

DDA

Idd

Quiescent current

–

200

250

330

1000

–

270

400

950

2500

–

uA

dB

Power mode = med

Power mode = high

–

CMRR

PSRR

Common mode rejection ratio

Power supply rejection ratio

80

85

70

Vdda ≥ 2.7 V

Vdda < 2.7 V

–

Note

39. Based on device characterization (Not production tested).

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PSoC^®3: CY8C36 Family

Data Sheet

Figure 11-25. Opamp Voffset Histogram, 3388 samples/847

parts, 25 °C, Vdda = 5 V

Figure 11-26. Opamp Voffset vs Temperature, Vdda = 5V

Figure 11-27. Opamp Voffset vs Vcommon and

Vdda, 25 °C

Figure 11-28. Opamp Output Voltage vs Load Current and

Temperature, High Power Mode, 25 °C, Vdda = 2.7 V

Figure 11-29. Opamp Operating Current vs Vdda and Power

Mode

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PSoC^®3: CY8C36 Family

Data Sheet

Table 11-19. Opamp AC Specifications

Parameter

GBW

Description

Gain-bandwidth product

Conditions

Min

1

2

1

3

1.1

0.9

3

Typ

–

45

Max

–

Units

MHz

V/µs

Power mode = minimum, 200 pF load

Power mode = low, 200 pF load

Power mode = medium, 200 pF load

Power mode = high, 200 pF load

Power mode = low, 200 pF load

Power mode = medium, 200 pF load

Power mode = high, 200 pF load

SR

e_n

Slew rate, 20% - 80%

Input noise density

Power mode = high, Vdda = 5 V,

at 100 kHz

–

nV/sqrtHz

Figure 11-30. Opamp Noise vs Frequency, Power Mode =

High, Vdda = 5V

Figure 11-31. Opamp Step Response, Rising

Figure 11-32. Opamp Step Response, Falling

Note

40. Based on device characterization (Not production tested).

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PSoC^®3: CY8C36 Family

Data Sheet

11.5.2 Delta-Sigma ADC

Unless otherwise specified, operating conditions are:

Operation in continuous sample mode

fclk = 6.144 MHz

Reference = 1.024 V internal reference bypassed on P3.2 or P0.3

Unless otherwise specified, all charts and graphs show typical values

Table 11-20. 12-bit Delta-sigma ADC DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Resolution

8

–

12

bits

No. of

GPIO

Number of channels, single ended

–

Differential pair is formed using a

pair of GPIOs.

Yes

Buffered, buffer gain = 1,

Range = ±1.024 V, 25 °C

No. of

GPIO/2

Number of channels, differential

Monotonic

–

Ge

Gain error

±0.2

%

Buffered, buffer gain = 1,

Range = ±1.024 V

Buffered, 16-bit mode, V_DDA= 2.7 V,

25 °C

Buffer gain = 1, 16-bit,

Range = ±1.024 V

Gd

Gain drift

–

50

ppm/°C

mV

Vos

TCVos

Input offset voltage

±0.1

Temperature coefficient, input offset

voltage

Input voltage range, single ended^[41]

Input voltage range, differential unbuf-

fered^[41]

–

55

µV/°C

V_SSA

V_DDA

V

Input voltage range, differential,

V_SSA

–

V_DDA– 1

V

buffered^[41]

INL12

DNL12

INL8

DNL8

Rin_Buff

Integral non linearity^[41]

Differential non linearity^[41]

Integral non linearity^[41]

Differential non linearity^[41]

ADC input resistance

Range = ±1.024 V, unbuffered

Input buffer used

–

10

–

±1

–

LSB

MΩ

Input buffer bypassed, 12 bit, Range

= ±1.024 V

Rin_ADC12 ADC input resistance

–

148^[42]

–

kΩ

ADC external reference input voltage, see

also internal reference in Voltage

Reference on page 85

Vextref

Pins P0[3], P3[2]

0.9

–

1.3

V

Current Consumption

I_{DD_12}

Current consumption, 12 bit^[41]

I_BUFF

Buffer current consumption^[41]

192 ksps, unbuffered

–

1.4

2.5

mA

Notes

41. Based on device characterization (not production tested).

42. By using switched capacitors at the ADC input an effective input resistance is created. Holding the gain and number of bits constant, the resistance is proportional to

the inverse of the clock frequency. This value is calculated, not measured. For more information see the Technical Reference Manual.

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PSoC^®3: CY8C36 Family

Data Sheet

Table 11-21. Delta-sigma ADC AC Specifications

Parameter

Description

Conditions

Min

–

Typ

–

Max

4

Units

Samples

%

Startup time

Total harmonic distortion^[43]

THD

Buffer gain = 1, 16 bit,

Range = ±1.024 V

–

0.0032

12-Bit Resolution Mode

SR12

BW12

Sample rate, continuous, high power^[43]

Input bandwidth at max sample rate^[43]

Range = ±1.024 V, unbuffered

4

–

44

–

192

–

ksps

kHz

dB

SINAD12int Signal to noise ratio, 12-bit, internal reference^[43]

Range = ±1.024 V, unbuffered 66

–

8-Bit Resolution Mode

SR8

Sample rate, continuous, high power^[43]

Input bandwidth at max sample rate^[43]

Range = ±1.024 V, unbuffered

8

–

88

–

384

–

ksps

kHz

dB

BW8

SINAD8int Signal to noise ratio, 8-bit, internal reference^[43]

Range = ±1.024 V, unbuffered 43

–

Table 11-22. Delta-sigma ADC Sample Rates, Range = ±1.024 V

Continuous

Multi-Sample

Resolution,

Bits

Min

Max

Min

1911

1543

1348

1154

978

Max

8

8000

6400

5566

4741

4000

384000

307200

267130

227555

192000

91701

74024

64673

55351

46900

9

10

11

12

Figure 11-33. Delta-sigma ADC IDD vs sps, Range = ±1.024 V,

Continuous Sample Mode, Input Buffer Bypassed

Note

43. Based on device characterization (Not production tested).

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PSoC^®3: CY8C36 Family

Data Sheet

11.5.3 Voltage Reference

Table 11-23. Voltage Reference Specifications

See also ADC external reference specifications in Section 11.5.2.

Parameter

Description

Conditions

Initial trimming

Min

Typ

Max

Units

V_REF

Precision reference voltage

1.023

1.024

1.025

V

(–0.1%)

(+0.1%)

Temperature drift^[44]

–

20

–

ppm/°C

ppm/Khr

ppm

Long term drift

Thermal cycling drift (stability)^[44]

100

–

11.5.4 Analog Globals

Table 11-24. Analog Globals Specifications

Parameter

Rppag

Description

Conditions

V_DDA= 3.0 V

Min

Typ

Max

Units

Resistance pin-to-pin through

analog global^[45]

–

939

1461

Ω

Rppmuxbus

Resistance pin-to-pin through

analog mux bus^[45]

V_DDA= 3.0 V

–

721

1135

Ω

Document Number: 001-53413 Rev. *L

Page 85 of 126

PSoC^®3: CY8C36 Family

Data Sheet

11.5.5 Comparator

Table 11-25. Comparator DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Input offset voltage in fast mode

Factory trim, Vdda > 2.7 V,

Vin ≥ 0.5 V

–

10

mV

V_OS

Input offset voltage in slow mode Factory trim, Vin ≥ 0.5 V

Input offset voltage in fast mode^[45]Custom trim

Input offset voltage in slow mode^[45]Custom trim

–

9

4

–

mV

–

V_OS

Input offset voltage in ultra

low-power mode

±12

V_HYST

V_ICM

Hysteresis

Hysteresis enable mode

High current / fast mode

Low current / slow mode

Ultra low power mode

–

V_SSA

–

10

–

32

V_DDA– 0.1

V_DDA

V_DDA– 0.9

–

mV

V

Input common mode voltage

–

V

–

V

CMRR

I_CMP

Common mode rejection ratio

High current mode/fast mode^[44]

Low current mode/slow mode^[44]

Ultra low-power mode^[44]

50

–

dB

µA

–

400

–

100

–

6

–

Table 11-26. Comparator AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Response time, high current

mode^[44]

50 mV overdrive, measured

pin-to-pin

–

75

110

ns

Response time, low current

mode^[44]

50 mV overdrive, measured

pin-to-pin

–

155

55

200

–

ns

µs

T_RESP

Response time, ultra low-power

mode^[44]

50 mV overdrive, measured

pin-to-pin

11.5.6 Current Digital-to-analog Converter (IDAC)

See the IDAC component data sheet in PSoC Creator for full electrical specifications and APIs.

Unless otherwise specified, all charts and graphs show typical values.

Table 11-27. IDAC DC Specifications

Parameter

Description

Conditions

Min

–

Typ

–

Max

8

Units

bits

Resolution

I_OUT

Output current at code = 255

Range = 2.048 mA, code = 255,

V_DDA≥ 2.7 V, Rload = 600 Ω

–

2.048

–

mA

Range = 2.048 mA, High mode,

code = 255, V_DDA≤ 2.7 V, Rload =

300 Ω

–

2.048

–

mA

Range=255µA, code=255, Rload

= 600 Ω

–

255

–

µA

Range = 31.875 µA, code = 255,

31.875

Rload = 600 Ω

Monotonicity

–

0

Yes

±1

Ezs

Zero scale error

LSB

Notes

44. Based on device characterization (Not production tested).

45. The resistance of the analog global and analog mux bus is high if V_DDA≤ 2.7 V, and the chip is in either sleep or hibernate mode. Use of analog global and analog

mux bus under these conditions is not recommended.

46. The recommended procedure for using a custom trim value for the on-chip comparators can be found in the TRM.

Document Number: 001-53413 Rev. *L

Page 86 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Table 11-27. IDAC DC Specifications (continued)

Parameter Description

Eg

Conditions

Range = 2.048 mA, 25 °C

Range = 255 µA, 25 ° C

Range = 31.875 µA, 25 ° C

Range = 2.048 mA

Min

–

Typ

–

Max

±2.5

±3.5

0.04

0.05

±1

Units

%

Gain error

–

%

–

%

TC_Eg

INL

Temperature coefficient of gain

error

–

% / °C

LSB

Range = 255 µA

–

Range = 31.875 µA

–

Integral nonlinearity

Sink mode, range = 255 µA, Codes

8 – 255, Rload = 2.4 kΩ, Cload =

15 pF

–

±0.9

Source mode, range = 255 µA,

Codes 8 – 255, Rload = 2.4 kΩ,

Cload = 15 pF

–

±1.2

±1.5

LSB

DNL

Differential nonlinearity

Sink mode, range = 255 µA, Rload

= 2.4 kΩ, Cload = 15 pF

–

1

±0.3

–

±1

–

LSB

V

Source mode, range = 255 µA,

Rload = 2.4 kΩ, Cload = 15 pF

Vcompliance

I_DD

Dropout voltage, source or sink

mode

Voltage headroom at max current,

Rload to Vdda or Rload to Vssa,

Vdiff from Vdda

Operating current, code = 0

Slow mode, source mode,

range = 31.875 µA

–

44

33

100

500

µA

Slow mode, source mode,

range = 255 µA,

Slow mode, source mode,

range = 2.04 mA

33

Slow mode, sink mode,

range = 31.875 µA

36

Slow mode, sink mode,

range = 255 µA

33

Slow mode, sink mode,

range = 2.04 mA

33

Fast mode, source mode,

range = 31.875 µA

310

305

310

300

Fast mode, source mode,

range = 255 µA

Fast mode, source mode,

range = 2.04 mA

Fast mode, sink mode,

range = 31.875 µA

Fast mode, sink mode,

range = 255 µA

Fast mode, sink mode,

range = 2.04 mA

Document Number: 001-53413 Rev. *L

Page 87 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Figure 11-34. IDAC INL vs Input Code, Range = 255 µA,

Source Mode

Figure 11-35. IDAC INL vs Input Code, Range = 255 µA, Sink

Mode

Figure 11-36. IDAC DNL vs Input Code, Range = 255 µA,

Source Mode

Figure 11-37. IDAC DNL vs Input Code, Range = 255 µA, Sink

Mode

Figure 11-38. IDAC INL vs Temperature, Range = 255 µA, Fast

Mode

Figure 11-39. IDAC DNL vs Temperature, Range = 255 µA,

Fast Mode

Document Number: 001-53413 Rev. *L

Page 88 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Figure 11-40. IDAC Full Scale Error vs Temperature, Range

= 255 µA, Source Mode

Figure 11-41. IDAC Full Scale Error vs Temperature, Range

= 255 µA, Sink Mode

Figure 11-42. IDAC Operating Current vs Temperature,

Range = 255 µA, Code = 0, Source Mode

Figure 11-43. IDAC Operating Current vs Temperature,

Range = 255 µA, Code = 0, Sink Mode

Document Number: 001-53413 Rev. *L

Page 89 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Table 11-28. IDAC AC Specifications

Parameter Description

F_DACUpdate rate

T_SETTLESettling time to 0.5 LSB

Conditions

Min

–

Typ

–

Max

8

Units

Msps

ns

Range = 31.875 µA or 255 µA, full

scale transition, fast mode, 600 Ω

15-pF load

–

125

Figure 11-44. IDAC Step Response, Codes 0x40 - 0xC0,

255 µA Mode, Source Mode, Fast Mode, Vdda = 5 V

Figure 11-45. IDAC Glitch Response, Codes 0x7F - 0x80,

255 µA Mode, Source Mode, Fast Mode, Vdda = 5 V

Figure 11-46. IDAC PSRR vs Frequency

Document Number: 001-53413 Rev. *L

Page 90 of 126

PSoC^®3: CY8C36 Family

Data Sheet

11.5.7 Voltage Digital to Analog Converter (VDAC)

See the VDAC component data sheet in PSoC Creator for full electrical specifications and APIs.

Unless otherwise specified, all charts and graphs show typical values.

Table 11-29. VDAC DC Specifications

Parameter

Description

Conditions

Min

–

Typ

8

Max

–

Units

Resolution

bits

INL1

Integral nonlinearity

Differential nonlinearity

Output resistance

1 V scale

4 V scale

–

±2.1

±0.3

4

±2.5

±1

LSB

DNL1

Rout

–

LSB

–

kΩ

–

16

1

–

kΩ

V_OUT

Output voltage range, code = 255 1 V scale

–

V

4 V scale, Vdda = 5 V

–

4

–

V

Monotonicity

Zero scale error

Gain error

–

Yes

±0.9

±2.5

0.03

100

500

–

V_OS

Eg

–

0

LSB

1 V scale

4 V scale

–

%

–

TC_Eg

I_DD

Temperature coefficient, gain error 1 V scale

4 V scale

–

%FSR / °C

µA

–

Operating current

Slow mode

Fast mode

–

µA

Figure 11-47. VDAC INL vs Input Code, 1 V Mode

Figure 11-48. VDAC DNL vs Input Code, 1 V Mode

Document Number: 001-53413 Rev. *L

Page 91 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Figure 11-49. VDAC INL vs Temperature, 1 V Mode

Figure 11-50. VDAC DNL vs Temperature, 1 V Mode

Figure 11-51. VDAC Full Scale Error vs Temperature, 1 V

Mode

Figure 11-52. VDAC Full Scale Error vs Temperature, 4 V

Mode

Figure 11-53. VDAC Operating Current vs Temperature, 1V

Mode, Slow Mode

Figure 11-54. VDAC Operating Current vs Temperature, 1 V

Mode, Fast Mode

Document Number: 001-53413 Rev. *L

Page 92 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Table 11-30. VDAC AC Specifications

Parameter Description

F_DACUpdate rate

Conditions

Min

–

Typ

–

Max

1000

250

1

Units

ksps

µs

1 V scale

4 V scale

–

TsettleP

TsettleN

Settling time to 0.1%, step 25% to 1 V scale, Cload = 15 pF

75%

–

0.45

4 V scale, Cload = 15 pF

–

0.8

3.2

1

µs

Settling time to 0.1%, step 75% to 1 V scale, Cload = 15 pF

25%

0.45

4 V scale, Cload = 15 pF

–

0.7

3

µs

Figure 11-55. VDAC Step Response, Codes 0x40 - 0xC0, 1 V

Mode, Fast Mode, Vdda = 5 V

Figure 11-56. VDAC Glitch Response, Codes 0x7F - 0x80, 1 V

Mode, Fast Mode, Vdda = 5 V

Figure 11-57. VDAC PSRR vs Frequency

Document Number: 001-53413 Rev. *L

Page 93 of 126

PSoC^®3: CY8C36 Family

Data Sheet

11.5.8 Mixer

The mixer is created using a SC/CT analog block; see the Mixer component data sheet in PSoC Creator for full electrical specifications

and APIs.

Table 11-31. Mixer DC Specifications

Parameter

V_OS

Description

Input offset voltage

Conditions

Min

–

Typ

–

Max

10

2

Units

mV

Quiescent current

Gain

–

0.9

0

mA

G

–

dB

Table 11-32. Mixer AC Specifications

Parameter

f_LO

Description

Local oscillator frequency

Input signal frequency

Local oscillator frequency

Input signal frequency

Slew rate

Conditions

Min

–

Typ

–

Max

4

Units

MHz

V/µs

Down mixer mode

f_in

f_LO

f_in

Down mixer mode

Up mixer mode

–

14

1

–

1

SR

3

–

11.5.9 Transimpedance Amplifier

The TIA is created using a SC/CT analog block; see the TIA component data sheet in PSoC Creator for full electrical specifications

and APIs.

Table 11-33. Transimpedance Amplifier (TIA) DC Specifications

Parameter

V_IOFF

Rconv

Description

Input offset voltage

Conversion resistance^[48]

Conditions

Min

–

Typ

–

Max

10

Units

mV

%

R = 20K; 40 pF load

–25

–

+35

2

R = 30K; 40 pF load

R = 40K; 40 pF load

R = 80K; 40 pF load

R = 120K; 40 pF load

R = 250K; 40 pF load

R= 500K; 40 pF load

R = 1M; 40 pF load

–

%

–

%

–

%

–

%

–

%

–

%

–

%

Quiescent current

1.1

mA

Table 11-34. Transimpedance Amplifier (TIA) AC Specifications

Parameter

BW

Description

Conditions

Min

Typ

Max

Units

Input bandwidth (–3 dB)

R = 20K; –40 pF load

1500

–

kHz

R = 120K; –40 pF load

R = 1M; –40 pF load

240

25

–

kHz

Notes

47. Based on device characterization (Not production tested).

48. Conversion resistance values are not calibrated. Calibrated values and details about calibration are provided in PSoC Creator component data sheets. External

precision resistors can also be used.

Document Number: 001-53413 Rev. *L

Page 94 of 126

PSoC^®3: CY8C36 Family

Data Sheet

11.5.10 Programmable Gain Amplifier

The PGA is created using a SC/CT analog block; see the PGA component data sheet in PSoC Creator for full electrical specifications

and APIs.

Unless otherwise specified, operating conditions are:

Operating temperature = 25 °C for typical values

Unless otherwise specified, all charts and graphs show typical values

Table 11-35. PGA DC Specifications

Parameter

Vin

Description

Input voltage range

Input offset voltage

Conditions

Min

Vssa

–

Typ

–

Max

Vdda

10

Units

V

Power mode = minimum

Vos

Power mode = high,

gain = 1

–

mV

TCVos

Input offset voltage drift

with temperature

Power mode = high,

gain = 1

–

±30

µV/°C

Ge1

Gain error, gain = 1

Gain error, gain = 16

Gain error, gain = 50

DC output nonlinearity

–

±0.15

±2.5

±5

%

Ge16

Ge50

Vonl

Gain = 1

±0.01

% of

FSR

Cin

Input capacitance

–

7

–

pF

V

Voh

Output voltage swing

Power mode = high,

gain = 1, Rload = 100 kΩ

to V_DDA/ 2

V

_DDA– 0.15

Vol

Output voltage swing

Power mode = high,

gain = 1, Rload = 100 kΩ

to V_DDA/ 2

–

V

_SSA+ 0.15

V

Vsrc

Output voltage under load

Operating current

Iload = 250 µA, Vdda ≥

2.7V, power mode = high

300

mV

Idd

Power mode = high

–

1.5

–

1.65

–

mA

dB

PSRR

Power supply rejection

ratio

48

Figure 11-58. PGA Voffset Histogram, 4096 samples/

1024 parts

Document Number: 001-53413 Rev. *L

Page 95 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Table 11-36. PGA AC Specifications

Parameter

Description

–3 dB bandwidth

Conditions

Min

Typ

Max

Units

BW1

Power mode = high,

gain = 1, input = 100 mV

peak-to-peak

6.7

8

–

MHz

SR1

e_n

Slew rate

Power mode = high,

gain = 1, 20% to 80%

3

–

V/µs

Input noise density

Power mode = high,

Vdda = 5 V, at 100 kHz

43

nV/sqrtHz

Figure 11-59. Bandwidth vs. Temperature, at Different Gain

Settings, Power Mode = High

Figure 11-60. Noise vs. Frequency, Vdda = 5 V,

Power Mode = High

11.5.11 Temperature Sensor

Table 11-37. Temperature Sensor Specifications

Parameter

Description

Temp sensor accuracy

Conditions

Min

Typ

Max

Units

Range: –40 °C to +85 °C

–

±5

–

°C

11.5.12 LCD Direct Drive

Table 11-38. LCD Direct Drive DC Specifications

Parameter

I_CC

Description

LCD system operating current

Conditions

Min

–

Typ

38

Max

–

Units

μA

Device sleep mode with wakeup at

400-Hz rate to refresh LCDs, bus

clock = 3 Mhz, Vddio = Vdda = 3 V,

4 commons, 16 segments, 1/4 duty

cycle, 50 Hz frame rate, no glass

connected

I_{CC_SEG}

V_BIAS

Current per segment driver

LCD bias range (V_BIASrefers to the main V_DDA≥ 3 V and V_DDA≥ V_BIAS

output voltage(V0) of LCD DAC)

Strong drive mode

–

2

260

–

5

µA

V

LCD bias step size

LCD capacitance per

V_DDA≥ 3 V and V_DDA≥ V_BIAS

Drivers may be combined

–

9.1 × V_DDA

500

–

mV

pF

5000

segment/common driver

Long term segment offset

Output drive current per segment driver) Vddio = 5.5V, strong drive mode

–

355

–

20

710

mV

µA

I_OUT

Table 11-39. LCD Direct Drive AC Specifications

Parameter

f_LCD

Description

LCD frame rate

Conditions

Min

10

Typ

50

Max

150

Units

Hz

Document Number: 001-53413 Rev. *L

Page 96 of 126

PSoC^®3: CY8C36 Family

Data Sheet

11.6 Digital Peripherals

Specifications are valid for –40 °C ≤ T_A≤ 85 °C and T_J≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

except where noted.

11.6.1 Timer

The following specifications apply to the Timer/Counter/PWM peripheral in timer mode. Timers can also be implemented in UDBs; for

more information, see the Timer component data sheet in PSoC Creator.

Table 11-40. Timer DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Block current consumption

16-bit timer, at listed input clock

frequency

–

µA

3 MHz

–

15

60

–

µA

12 MHz

48 MHz

67 MHz

260

350

Table 11-41. Timer AC Specifications

Parameter Description

Operating frequency

Conditions

Min

DC

15

30

15

30

15

30

Typ

–

Max

Units

MHz

ns

67.01

Capture pulse width (Internal)

Capture pulse width (external)

Timer resolution

–

ns

–

ns

Enable pulse width

–

ns

Enable pulse width (external)

Reset pulse width

–

ns

–

ns

Reset pulse width (external)

–

ns

11.6.2 Counter

The following specifications apply to the Timer/Counter/PWM peripheral, in counter mode. Counters can also be implemented in

UDBs; for more information, see the Counter component data sheet in PSoC Creator.

Table 11-42. Counter DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Block current consumption

16–bit counter, at listed input clock

frequency

–

µA

3 MHz

–

15

60

–

µA

12 MHz

48 MHz

67 MHz

260

350

Table 11-43. Counter AC Specifications

Parameter Description

Operating frequency

Conditions

Min

DC

15

30

15

30

15

30

Typ

–

Max

Units

MHz

ns

67.01

Capture pulse

–

Resolution

–

ns

Pulse width

–

ns

Pulse width (external)

Enable pulse width

Enable pulse width (external)

Reset pulse width

Reset pulse width (external)

–

ns

–

ns

–

ns

–

ns

–

ns

Document Number: 001-53413 Rev. *L

Page 97 of 126

PSoC^®3: CY8C36 Family

Data Sheet

11.6.3 Pulse Width Modulation

The following specifications apply to the Timer/Counter/PWM peripheral, in PWM mode. PWM components can also be implemented

in UDBs; for more information, see the PWM component data sheet in PSoC Creator.

Table 11-44. PWM DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Block current consumption

16-bit PWM, at listed input clock

frequency

–

µA

3 MHz

–

15

60

–

µA

12 MHz

48 MHz

67 MHz

260

350

Table 11-45. Pulse Width Modulation (PWM) AC Specifications

Parameter

Description

Operating frequency

Conditions

Min

DC

15

30

15

30

15

30

15

30

Typ

–

Max

Units

MHz

ns

67.01

Pulse width

–

Pulse width (external)

Kill pulse width

–

ns

–

ns

Kill pulse width (external)

Enable pulse width

–

ns

–

ns

Enable pulse width (external)

Reset pulse width

–

ns

–

ns

Reset pulse width (external)

–

ns

11.6.4 I²C

Table 11-46. Fixed I²C DC Specifications

Parameter

Description

Conditions

Min

–

Typ

–

Max

250

260

30

Units

µA

Block current consumption

Enabled, configured for 100 kbps

Enabled, configured for 400 kbps

Wake from sleep mode

–

µA

–

µA

Table 11-47. Fixed I²C AC Specifications

Parameter Description

Conditions

Min

Typ

Max

Units

Bit rate

Controller Area Network^[49]

Table 11-48. CAN DC Specifications

–

1

Mbps

Parameter

I_DD

Description

Min

Typ

Max

Units

Block current consumption

–

200

µA

Table 11-49. CAN AC Specifications

Parameter Description

Conditions

Min

Typ

Max

Units

Bit rate

Minimum 8 MHz clock

–

1

Mbit

Note

49. Refer to ISO 11898 specification for details.

Document Number: 001-53413 Rev. *L

Page 98 of 126

PSoC^®3: CY8C36 Family

Data Sheet

11.6.5 Digital Filter Block

Table 11-50. DFB DC Specifications

Parameter

Description

Conditions

64-tap FIR at F_DFB

Min

Typ

Max

Units

DFB operating current

100 kHz (1.3 ksps)

500 kHz (6.7 ksps)

1 MHz (13.4 ksps)

10 MHz (134 ksps)

48 MHz (644 ksps)

67 MHz (900 ksps)

–

0.03

0.16

0.33

3.3

0.05

0.27

0.53

5.3

mA

15.7

21.8

25.5

35.6

Table 11-51. DFB AC Specifications

Parameter

F_DFB

Description

Conditions

Min

Typ

Max

Units

DFB operating frequency

DC

–

67.01

MHz

11.6.6 USB

Table 11-52. USB DC Specifications

Parameter

V_{USB_5}

Description

Conditions

Min

Typ

Max

Units

Device supply for USB operation

USB configured, USB regulator

enabled

4.35

–

5.25

V

V_{USB_3.3}

V_{USB_3}

USB configured, USB regulator

bypassed

3.15

2.85

–

3.6

V

USB configured, USB regulator

bypassed^[50]

I_{USB_Configured}Device supply current in device

active mode, bus clock and IMO =

24 MHz

V_DDD= 5 V, F_CPU= 1.5 MHz

–

10

8

–

mA

V_DDD= 3.3 V, F_CPU= 1.5 MHz

I_{USB_Suspended}Device supply current in device

sleep mode

V_DDD= 5 V, connected to USB

host, PICU configured to wake on

USB resume signal

–

0.5

–

mA

V

_DDD= 5 V, disconnected from

–

0.3

0.5

–

mA

USB host

V_DDD= 3.3 V, connected to USB

host, PICU configured to wake on

USB resume signal

V_DDD= 3.3 V, disconnected from

USB host

–

0.3

–

mA

Note

50. Rise/fall time matching (TR) not guaranteed, see USB Driver AC Specifications on page 79.

Document Number: 001-53413 Rev. *L

Page 99 of 126

PSoC^®3: CY8C36 Family

Data Sheet

11.6.7 Universal Digital Blocks (UDBs)

PSoC Creator provides a library of prebuilt and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM,

AND, OR, and so on) that are mapped to the UDB array. See the component data sheets in PSoC Creator for full AC/DC specifications,

APIs, and example code.

Table 11-53. UDB AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Datapath Performance

F_{MAX_TIMER}

F_{MAX_ADDER}

F_{MAX_CRC}

Maximumfrequencyof16-bittimerin

a UDB pair

–

67.01

MHz

Maximum frequency of 16-bit adder

in a UDB pair

Maximum frequency of 16-bit

CRC/PRS in a UDB pair

PLD Performance

F_{MAX_PLD}Maximum frequency of a two-pass

PLD function in a UDB pair

Clock to Output Performance

–

67.01

MHz

t_{CLK_OUT}

Propagation delay for clock in to data 25 °C, Vddd ≥ 2.7 V

–

20

–

25

55

ns

out, see Figure 11-61.

t_{CLK_OUT}

Propagation delay for clock in to data Worst-case placement, routing,

out, see Figure 11-61.

and pin selection

Figure 11-61. Clock to Output Performance

Document Number: 001-53413 Rev. *L

Page 100 of 126

PSoC^®3: CY8C36 Family

Data Sheet

11.7 Memory

Specifications are valid for –40 °C ≤ T_A≤ 85 °C and T_J≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

except where noted.

11.7.1 Flash

Table 11-54. Flash DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Erase and program voltage

V_DDDpin

1.71

–

5.5

V

Table 11-55. Flash AC Specifications

Parameter

T_WRITE

Description

Row write time (erase + program)

Row erase time

Min

–

Typ

15

10

5

Max

20

13

7

Units

ms

T_ERASE

–

ms

Row program time

–

ms

T_BULK

Bulk erase time (16 KB to 64 KB)

Sector erase time (8 KB to 16 KB)

–

35

15

5

ms

–

ms

Total device program time, including

JTAG or SWD, and other overhead

–

seconds

Flash data retention time, retention

period measured from last erase cycle T_A≤ 55 °C, 100 K erase/program

Average ambient temp.

20

10

–

years

cycles

Average ambient temp.

T_A≤ 85 °C, 10 K erase/program

cycles

11.7.2 EEPROM

Table 11-56. EEPROM DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Erase and program voltage

1.71

–

5.5

V

Table 11-57. EEPROM AC Specifications

Parameter

Description

Min

–

Typ

2

Max

20

–

Units

ms

T_WRITE

Single row erase/write cycle time

EEPROM data retention time, retention Average ambient temp, T_A≤ 25 °C,

period measured from last erase cycle 1M erase/program cycles

20

–

years

Average ambient temp, T_A≤ 55 °C,

20

10

–

100 K erase/program cycles

Average ambient temp.

T_A≤ 85 °C, 10 K erase/program

cycles

Document Number: 001-53413 Rev. *L

Page 101 of 126

PSoC^®3: CY8C36 Family

Data Sheet

11.7.3 Nonvolatile Latches (NVL))

Table 11-58. NVL DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Erase and program voltage

V_DDDpin

1.71

–

5.5

V

Table 11-59. NVL AC Specifications

Parameter Description

NVL endurance

Min

Typ

Max

Units

Programmed at 25 °C

1K

–

program/

erase

cycles

Programmed at 0 °C to 70 °C

100

–

program/

erase

cycles

NVL data retention time

Programmed at 25 °C

20

–

years

Programmed at 0 °C to 70 °C

11.7.4 SRAM

Table 11-60. SRAM DC Specifications

Parameter

V_SRAM

Description

SRAM retention voltage

Conditions

Min

1.2

Typ

–

Max

–

Units

V

Table 11-61. SRAM AC Specifications

Parameter

Description

Min

Typ

Max

Units

F_SRAM

SRAM operating frequency

DC

–

67.01

MHz

Document Number: 001-53413 Rev. *L

Page 102 of 126

PSoC^®3: CY8C36 Family

Data Sheet

11.7.5 External Memory Interface

EM_CEn

Figure 11-62. Asynchronous Read Cycle Timing

Tcel

Taddrv

Taddrh

EM_Addr

Address

Toel

EM_OEn

EM_WEn

EM_Data

Tdoesu

Tdoeh

Data

Table 11-62. Asynchronous Read Cycle Specifications

Parameter Description

EMIF clock period^[51]

Conditions

Min

30.3

2T – 5

–

Typ

Max

Units

nS

T

Vdda ≥ 3.3 V

–

Tcel

EM_CEn low time

2T+ 5

nS

Taddrv

Taddrh

Toel

EM_CEn low to EM_Addr valid

Address hold time after EM_Wen high

EM_OEn low time

5

nS

T

–

nS

2T – 5

T + 15

3

2T + 5

nS

Tdoesu

Tdoeh

Data to EM_OEn high setup time

Data hold time after EM_OEn high

–

nS

Note

51. Limited by GPIO output frequency, see Table 11-10 on page 74.

Document Number: 001-53413 Rev. *L

Page 103 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Figure 11-63. Asynchronous Write Cycle Timing

Taddrv

Taddrh

EM_Addr

EM_CEn

Address

Tcel

Twel

EM_WEn

EM_OEn

Tdweh

Tdcev

EM_Data

Data

Table 11-63. Asynchronous Write Cycle Specifications

Parameter

T

Description

EMIF clock period^[52]

Conditions

Vdda ≥ 3.3 V

Min

Typ

–

Max

Units

nS

30.3

–

Tcel

EM_CEn low time

T – 5

–

T + 5

nS

Taddrv

Taddrh

Twel

EM_CEn low to EM_Addr valid

Address hold time after EM_WEn high

EM_WEn low time

–

T

–

5

–

nS

–

nS

T – 5

–

T + 5

7

nS

Tdcev

Tdweh

EM_CEn low to data valid

Data hold time after EM_WEn high

–

nS

T

–

nS

Note

52. Limited by GPIO output frequency, see Table 11-10 on page 74.

Document Number: 001-53413 Rev. *L

Page 104 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Figure 11-64. Synchronous Read Cycle Timing

Tcp/2

EM_Clock

EM_CEn

Tceld

Tcehd

Taddriv

Taddrv

EM_Addr

EM_OEn

Address

Toeld

Toehd

Tds

Data

EM_Data

Tadschd

Tadscld

EM_ ADSCn

Table 11-64. Synchronous Read Cycle Specifications

Parameter

T

Description

EMIF clock period^[53]

Conditions

Vdda ≥ 3.3 V

Min

30.3

T/2

Typ

–

Max

–

Units

nS

Tcp/2

EM_Clock pulse high

–

Tceld

EM_CEn low to EM_Clock high

EM_Clock high to EM_CEn high

EM_Addr valid to EM_Clock high

EM_Clock high to EM_Addr invalid

EM_OEn low to EM_Clock high

EM_Clock high to EM_OEn high

Data valid before EM_OEn high

EM_ADSCn low to EM_Clock high

EM_Clock high to EM_ADSCn high

5

–

Tcehd

Taddrv

Taddriv

Toeld

T/2 – 5

5

–

T/2 – 5

5

–

Toehd

Tds

T

–

T + 15

5

–

Tadscld

Tadschd

–

T/2 – 5

–

Note

53. Limited by GPIO output frequency, see Table 11-10 on page 74.

Document Number: 001-53413 Rev. *L

Page 105 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Figure 11-65. Synchronous Write Cycle Timing

Tcp/2

EM_Clock

EM_CEn

Tceld

Tcehd

Taddriv

Taddrv

EM_Addr

Address

Tweld

Twehd

EM_WEn

EM_Data

Tdh

Tds

Data

Tadschd

Tadscld

EM_ ADSCn

Table 11-65. Synchronous Write Cycle Specifications

Parameter

T

Description

EMIF clock Period^[54]

Conditions

Vdda ≥ 3.3 V

Min

Typ

–

Max

–

Units

nS

30.3

Tcp/2

EM_Clock pulse high

T/2

–

Tceld

EM_CEn low to EM_Clock high

EM_Clock high to EM_CEn high

EM_Addr valid to EM_Clock high

EM_Clock high to EM_Addr invalid

EM_WEn low to EM_Clock high

EM_Clock high to EM_WEn high

Data valid before EM_Clock high

Data invalid after EM_Clock high

EM_ADSCn low to EM_Clock high

EM_Clock high to EM_ADSCn high

5

–

Tcehd

Taddrv

Taddriv

Tweld

Twehd

Tds

T/2 – 5

–

5

–

T/2 – 5

–

5

–

T/2 – 5

–

5

–

Tdh

T

5

–

Tadscld

Tadschd

–

T/2 – 5

–

Note

54. Limited by GPIO output frequency, see Table 11-10 on page 74.

Document Number: 001-53413 Rev. *L

Page 106 of 126

PSoC^®3: CY8C36 Family

Data Sheet

11.8 PSoC System Resources

Specifications are valid for –40 °C ≤ T_A≤ 85 °C and T_J≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

except where noted.

11.8.1 POR with Brown Out

For brown out detect in regulated mode, V_DDDand V_DDAmust be ≥ 2.0 V. Brown out detect is not available in externally regulated

mode.

Table 11-66. Precise Power On Reset (PRES) with Brown Out DC Specifications

Parameter

Description

Precise POR (PPOR)

Conditions

Min

Typ

Max

Units

PRESR

PRESF

Rising trip voltage

Falling trip voltage

Factory trim

1.64

1.62

–

1.68

1.66

V

Table 11-67. Power On Reset (POR) with Brown Out AC Specifications

Parameter

Description

Conditions

Min

–

Typ

–

Max

0.5

–

Units

µs

PRES_TR Response time

V

_DDD/V_DDAdroop rate

Sleep mode

–

5

V/sec

11.8.2 Voltage Monitors

Table 11-68. Voltage Monitors DC Specifications

Parameter

Description

Conditions

Min

–

Typ

–

Max

–

Units

–

LVI

Trip voltage

LVI_A/D_SEL[3:0] = 0000b

LVI_A/D_SEL[3:0] = 0001b

LVI_A/D_SEL[3:0] = 0010b

LVI_A/D_SEL[3:0] = 0011b

LVI_A/D_SEL[3:0] = 0100b

LVI_A/D_SEL[3:0] = 0101b

LVI_A/D_SEL[3:0] = 0110b

LVI_A/D_SEL[3:0] = 0111b

LVI_A/D_SEL[3:0] = 1000b

LVI_A/D_SEL[3:0] = 1001b

LVI_A/D_SEL[3:0] = 1010b

LVI_A/D_SEL[3:0] = 1011b

LVI_A/D_SEL[3:0] = 1100b

LVI_A/D_SEL[3:0] = 1101b

LVI_A/D_SEL[3:0] = 1110b

LVI_A/D_SEL[3:0] = 1111b

Trip voltage

1.68

1.89

2.14

2.38

2.62

2.87

3.11

3.35

3.59

3.84

4.08

4.32

4.56

4.83

5.05

5.30

5.57

1.73

1.95

2.20

2.45

2.71

2.95

3.21

3.46

3.70

3.95

4.20

4.45

4.70

4.98

5.21

5.47

5.75

1.77

2.01

2.27

2.53

2.79

3.04

3.31

3.56

3.81

4.07

4.33

4.59

4.84

5.13

5.37

5.63

5.92

V

HVI

V

Table 11-69. Voltage Monitors AC Specifications

Parameter Description

Response time

Conditions

Min

Typ

Max

Units

–

1

µs

Document Number: 001-53413 Rev. *L

Page 107 of 126

PSoC^®3: CY8C36 Family

Data Sheet

11.8.3 Interrupt Controller

Table 11-70. Interrupt Controller AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Delay from interrupt signal input to ISR Includes worse case completion of

–

25

Tcy CPU

code execution from ISR code

longest instruction DIV with 6

cycles

11.8.4 JTAG Interface

Figure 11-66. JTAG Interface Timing

(1/f_TCK)

TCK

TDI

T_TDI_setup

T_TDI_hold

T_TDO_hold

T_TDO_valid

TDO

TMS

T_TMS_setup

T_TMS_hold

Table 11-71. JTAG Interface AC Specifications^[55]

Parameter Description

f_TCK TCK frequency

Conditions

3.3 V ≤ V_DDD≤ 5 V

Min

Typ

–

Max

14^[56]

7^[56]

–

Units

MHz

ns

–

1.71 V ≤ V_DDD< 3.3 V

–

(T/10) – 5

T/4

–

T_TDI_setup

TDI setup before TCK high

–

T_TMS_setup TMS setup before TCK high

–

T_TDI_hold

T_TDO_valid

T_TDO_hold

TDI, TMS hold after TCK high

TCK low to TDO valid

T = 1/f_TCK max

T/4

–

2T/5

–

TDO hold after TCK high

T/4

–

Notes

55. Based on device characterization (Not production tested).

56. f_TCK must also be no more than 1/3 CPU clock frequency.

Document Number: 001-53413 Rev. *L

Page 108 of 126

PSoC^®3: CY8C36 Family

Data Sheet

11.8.5 SWD Interface

Figure 11-67. SWD Interface Timing

(1/f_SWDCK)

SWDCK

SWDIO

T_SWDI_setup

T_SWDI_hold

(PSoC 3 reading on SWDIO)

T_SWDO_hold

T_SWDO_valid

SWDIO

(PSoC 3 writing to SWDIO)

Table 11-72. SWD Interface AC Specifications^[57]

Parameter

Description

SWDCLK frequency

Conditions

Min

–

Typ

–

Max

14^[58]

7^[58]

Units

MHz

f_SWDCK

3.3 V ≤ V_DDD≤ 5 V

1.71 V ≤ V_DDD< 3.3 V

–

1.71 V ≤ V_DDD< 3.3 V,

SWD over USBIO pins

–

5.5^[58]

T_SWDI_setup SWDIO input setup before SWDCK high T = 1/f_SWDCK max

T/4

–

T_SWDI_hold SWDIO input hold after SWDCK high

T_SWDO_valid SWDCK high to SWDIO output

T = 1/f_SWDCK max

2T/5

–

T_SWDO_hold SWDIO output hold after SWDCK low T = 1/f_SWDCK max

T/4

11.8.6 SWV Interface

[57]

Table 11-73. SWV Interface AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

SWV mode SWV bit rate

–

33

Mbit

Notes

57. Based on device characterization (Not production tested).

58. f_SWDCK must also be no more than 1/3 CPU clock frequency.

Document Number: 001-53413 Rev. *L

Page 109 of 126

PSoC^®3: CY8C36 Family

Data Sheet

11.9 Clocking

Specifications are valid for –40 °C ≤ T ≤ 85 °C and T ≤ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,

A

J

except where noted.

11.9.1 32 kHz External Crystal

[59]

Table 11-74. 32 kHz External Crystal DC Specifications

Parameter Description

Operating current

Conditions

Low-power mode

Min

–

Typ

0.25

6

Max

1.0

–

Units

µA

I

CC

CL

DL

External crystal capacitance

Drive level

–

pF

–

1

µW

Table 11-75. 32 kHz External Crystal AC Specifications

Parameter

Description

Conditions

Min

–

Typ

32.768

1

Max

–

Units

kHz

s

F

Frequency

T

Startup time

High power mode

–

ON

11.9.2 Internal Main Oscillator

Table 11-76. IMO DC Specifications

Parameter

Description

Supply current

Conditions

Min

Typ

Max

Units

62.6 MHz

–

600

500

300

200

180

150

µA

48 MHz

24 MHz – USB mode

24 MHz – non USB mode

12 MHz

With oscillator locking to USB bus

6 MHz

3 MHz

Note

59. Based on device characterization (Not production tested).

Document Number: 001-53413 Rev. *L

Page 110 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Figure 11-68. IMO Current vs. Frequency

Table 11-77. IMO AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

IMO frequency stability (with factory trim)

62.6 MHz

–7

–5

–

7

5

%

µs

48 MHz

24 MHz – Non USB mode

24 MHz – USB mode

12 MHz

–4

4

F

IMO

With oscillator locking to USB bus

–0.25

–3

0.25

3

6 MHz

–2

2

3 MHz

–1

1

[60]

Startup time

Fromenable(duringnormalsystem

operation) or wakeup from

low-power state

–

12

[60]

Jitter (peak to peak)

Jp–p

F = 24 MHz

F = 3 MHz

–

0.9

1.6

–

ns

[60]

Jitter (long term)

Jperiod

F = 24 MHz

F = 3 MHz

–

0.9

12

–

ns

Note

60. Based on device characterization (Not production tested).

Document Number: 001-53413 Rev. *L

Page 111 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Figure 11-69. IMO Frequency Variation vs. Temperature

Figure 11-70. IMO Frequency Variation vs. V_CC

11.9.3 Internal Low Speed Oscillator

Table 11-78. ILO DC Specifications

Parameter

Description

Operating current

Conditions

= 1 kHz

Min

–

Typ

0.3

1.0

2.0

Max

1.7

2.6

15

Units

µA

F

OUT

I

= 33 kHz

–

µA

CC

= 100 kHz

–

µA

Leakage current

Power down mode

–

nA

Table 11-79. ILO AC Specifications

Parameter

Description

Startup time, all frequencies

ILO frequencies (trimmed)

100 kHz

Conditions

Turbo mode

Min

Typ

Max

Units

–

2

ms

45

100

1

200

2

kHz

1 kHz

0.5

F

ILO

ILO frequencies (untrimmed)

100 kHz

30

100

1

300

3.5

kHz

1 kHz

0.3

Figure 11-71. ILO Frequency Variation vs. Temperature

Figure 11-72. ILO Frequency Variation vs. V_DD

Document Number: 001-53413 Rev. *L

Page 112 of 126

PSoC^®3: CY8C36 Family

Data Sheet

11.9.4 External Crystal Oscillator

Table 11-80. ECO AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

F

Crystal frequency range

4

–

25

MHz

11.9.5 External Clock Reference

[63]

Table 11-81. External Clock Reference AC Specifications

Parameter

Description

External frequency range

Input duty cycle range

Input edge rate

Min

Typ

Max

33

70

–

Units

MHz

%

0

–

50

–

Measured at V

/2

30

0.1

DDIO

V

to V

V/ns

IL

IH

11.9.6 Phase-Locked Loop

Table 11-82. PLL DC Specifications

Parameter

Description

PLL operating current

Conditions

Min

–

Typ

400

200

Max

–

Units

µA

I

In = 3 MHz, Out = 67 MHz

In = 3 MHz, Out = 24 MHz

DD

–

µA

Table 11-83. PLL AC Specifications

Parameter

Description

Conditions

Min

1

Typ

–

Max

48

Units

MHz

µs

[61]

Fpllin

PLL input frequency

[62]

PLL intermediate frequency

Output of prescaler

1

–

3

[61]

Fpllout

PLL output frequency

24

–

67

Lock time at startup

–

250

[63]

Jperiod-rms Jitter (rms)

–

ps

Notes

61. This specification is guaranteed by testing the PLL across the specified range using the IMO as the source for the PLL.

62. PLL input divider, Q, must be set so that the input frequency is divided down to the intermediate frequency range. Value for Q ranges from 1 to 16.

63. Based on device characterization (Not production tested).

Document Number: 001-53413 Rev. *L

Page 113 of 126

PSoC^®3: CY8C36 Family

Data Sheet

12. Ordering Information

In addition to the features listed in Table 12-1, every CY8C36 device includes: a precision on-chip voltage reference, precision

2

oscillators, flash, ECC, DMA, a fixed function I C, 4 KB trace RAM, JTAG/SWD programming and debug, external memory interface,

and more. In addition to these features, the flexible UDBs and analog subsection support a wide range of peripherals. To assist you

in selecting the ideal part, PSoC Creator makes a part recommendation after you choose the components required by your application.

All CY8C36 derivatives incorporate device and flash security in user-selectable security levels; see the TRM for details.

Table 12-1. CY8C36 Family with Single Cycle 8051

[66]

MCU Core

Analog

Digital

I/O

Part Number

Package

JTAG ID^[67]

32 KB Flash

CY8C3665AXI-010 67 32

CY8C3665PVI-008 67 32

CY8C3665AXI-016 67 32

4

1

✔

12-bit Del-Sig

4

2

4

2

✔

20

4

70 62

29 25

72 62

48 38

31 25

29 25

8

4

8

4

0

2

0

100-pin TQFP 0×1E00A069

48-pin SSOP 0×1E008069

100-pin TQFP 0×1E010069

–

✔

4

✔

CY8C3665LTI-044

CY8C3665LTI-006

67 32

68-pin QFN

48-pin QFN

48-pin SSOP

0×1E02C069

0×1E006069

0×1E007069

0×1E050069

CY8C3665PVI-007 67 32

CY8C3665PVI-080 67 32

64 KB Flash

–

CY8C3666AXI-052 67 64

CY8C3666AXI-036 67 64

8

2

12-bit Del-Sig

4

2

4

✔

24

4

70 62

72 62

48 38

31 25

70 62

8

4

8

0

2

0

100-pin TQFP 0×1E034069

100-pin TQFP 0×1E024069

✔

–

✔

CY8C3666LTI-027

CY8C3666LTI-050

67 64

68-pin QFN

48-pin QFN

0×1E01B069

0×1E032069

CY8C3666AXI-037 67 64

100-pin TQFP 0×1E025069

–

Notes

64. Analog blocks support a wide variety of functionality including TIA, PGA, and mixers. See the Example Peripherals on page 39 for more information on how analog

blocks can be used.

65. UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or

multiple UDBs. Multiple functions can share a single UDB. See the Example Peripherals on page 39 for more information on how UDBs can be used.

66. The I/O Count includes all types of digital I/O: GPIO, SIO, and the two USB I/O. See the I/O System and Routing on page 32 for details on the functionality of each of

these types of I/O.

67. The JTAG ID has three major fields. The most significant nibble (left digit) is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID.

Document Number: 001-53413 Rev. *L

Page 114 of 126

PSoC^®3: CY8C36 Family

Data Sheet

12.1 Part Numbering Conventions

PSoC 3 devices follow the part numbering convention described here. All fields are single character alphanumeric (0, 1, 2, …, 9, A,

B, …, Z) unless stated otherwise.

CY8Cabcdefg-xxx

a: Architecture

3: PSoC 3

5: PSoC 5

ef: Package code

Two character alphanumeric

AX: TQFP

LT: QFN

PV: SSOP

b: Family group within architecture

4: CY8C34 family

g: Temperature range

C: commercial

I: industrial

6: CY8C36 family

8: CY8C38 family

c: Speed grade

4: 48 MHz

A: automotive

xxx: Peripheral set

6: 67 MHz

Three character numeric

No meaning is associated with these three characters.

d: Flash capacity

4: 16 KB

5: 32 KB

6: 64 KB

CY8C

3

6

P

V

I

-

x x x

Example

Cypress Prefix

Architecture

3: PSoC 3

6: CY8C36 Family

6: 67 MHz

6: 64 KB

Family Group within Architecture

Speed Grade

Flash Capacity

PV: SSOP

Package Code

I: Industrial

Temperature Range

Peripheral Set

All devices in the PSoC 3 CY8C36 family comply to RoHS-6 specifications, demonstrating the commitment by Cypress to lead-free

products. Lead (Pb) is an alloying element in solders that has resulted in environmental concerns due to potential toxicity. Cypress

uses nickel-palladium-gold (NiPdAu) technology for the majority of leadframe-based packages.

A high level review of the Cypress Pb-free position is available on our website. Specific package information is also available. Package

Material Declaration data sheets (PMDDs) identify all substances contained within Cypress packages. PMDDs also confirm the

absence of many banned substances. The information in the PMDDs will help Cypress customers plan for recycling or other “end of

life” requirements.

Document Number: 001-53413 Rev. *L

Page 115 of 126

PSoC^®3: CY8C36 Family

Data Sheet

13. Packaging

Table 13-1. Package Characteristics

Parameter

Description

Conditions

Min

–40

–

Typ

25.00

–

Max

85

100

–

Units

°C

T

Operating ambient temperature

Operating junction temperature

A

T

°C

J

Package θ (48-pin SSOP)

49

°C/Watt

JA

JC

JA

Package θ (48-pin QFN)

–

14

–

JA

Package θ (68-pin QFN)

–

15

–

JA

Package θ (100-pin TQFP)

–

34

–

JA

Package θ (48-pin SSOP)

–

24

–

JC

Package θ (48-pin QFN)

–

15

–

JC

Package θ (68-pin QFN)

–

13

–

JC

Package θ (100-pin TQFP)

–

10

–

JC

Table 13-2. Solder Reflow Peak Temperature

Maximum Peak

Package

Maximum Time at Peak

Temperature

48-pin SSOP

48-pin QFN

68-pin QFN

100-pin TQFP

260 °C

30 seconds

Table 13-3. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2

Package

48-pin SSOP

48-pin QFN

68-pin QFN

100-pin TQFP

MSL

MSL 3

Document Number: 001-53413 Rev. *L

Page 116 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Figure 13-1. 48-pin (300 mil) SSOP Package Outline

.020

24

1

0.395

0.420

0.292

0.299

DIMENSIONS IN INCHES MIN.

MAX.

25

48

0.620

0.630

0.005

0.010

SEATING PLANE

.010

0.088

0.092

0.095

0.110

GAUGE PLANE

0.024

0.040

0.004

0.025

BSC

0°-8°

0.008

0.016

0.008

51-85061-*D

0.0135

Figure 13-2. 48-pin QFN Package Outline

SIDE VIEW

TOP VIEW

BOTTOM VIEW

1.00 MAX.

0.05 MAX.

7.00±0.10

5.6±0.10

PIN 1 ID

0.23±0.05

0.20 REF.

48

37

48

36

1

PIN 1 DOT

LASER MARK

SOLDERABLE

EXPOSED

PAD

7.00±0.10

5.55 REF

5.6±0.10

12

25

12

25

0.40±0.10

24

13

24

0.50±0.10

5.55 REF

0.08

C

NOTES:

1. HATCH AREA IS SOLDERABLE EXPOSED METAL.

2. REFERENCE JEDEC#: MO-220

3. PACKAGE WEIGHT: 0.13g

4. ALL DIMENSIONS ARE IN MM [MIN/MAX]

5. PACKAGE CODE

001- 45616 *B

PART #

LT48D

DESCRIPTION

LEAD FREE

Document Number: 001-53413 Rev. *L

Page 117 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Figure 13-3. 68-pin QFN 8×8 with 0.4 mm Pitch Package Outline (Sawn Version)

TOP VIEW

SIDE VIEW

BOTTOM VIEW

0.900±0.100

5.7±0.10

8.000±0.100

0.200 REF

PIN1 ID

R 0.20

0.400 PITCH

5

2

6

8

5

2

6

8

1

5

1

5

1

PIN 1 DOT

SOLDERABLE

EXPOSED

PAD

LASER MARK

5.7±0.10

0.20±0.05

1

7

3

5

1

7

3

_0.400±0.1005

3

4

1

8

0.05 MAX

3

4

1

8

6.40 REF

NOTES:

1. HATCH AREA IS SOLDERABLE EXPOSED METAL.

001-09618 *C

2. REFERENCE JEDEC#: MO-220

3. PACKAGE WEIGHT: 0.17g

4. ALL DIMENSIONS ARE IN MILLIMETERS

Figure 13-4. 100-pin TQFP (14 × 14 × 1.4 mm) Package Outline

51-85048 *E

Document Number: 001-53413 Rev. *L

Page 118 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Table 14-1. Acronyms Used in this Document (continued)

14. Acronyms

Acronym

FIR

Description

finite impulse response, see also IIR

flash patch and breakpoint

full-speed

Table 14-1. Acronyms Used in this Document

Acronym

abus

Description

FPB

FS

analog local bus

ADC

AG

analog-to-digital converter

analog global

GPIO

general-purpose input/output, applies to a PSoC

AHB

AMBA (advanced microcontroller bus archi-

tecture) high-performance bus, an ARM data

transfer bus

HVI

IC

high-voltage interrupt, see also LVI, LVD

integrated circuit

ALU

arithmetic logic unit

IDAC

IDE

current DAC, see also DAC, VDAC

integrated development environment

AMUXBUS analog multiplexer bus

2

API

application programming interface

I C, or IIC

Inter-Integrated Circuit, a communications

protocol

APSR

application program status register

advanced RISC machine, a CPU architecture

automatic thump mode

IIR

infinite impulse response, see also FIR

internal low-speed oscillator, see also IMO

internal main oscillator, see also ILO

integral nonlinearity, see also DNL

input/output, see also GPIO, DIO, SIO, USBIO

initial power-on reset

®

ARM

ILO

IMO

INL

ATM

BW

bandwidth

CAN

Controller Area Network, a communications

protocol

I/O

CMRR

CPU

common-mode rejection ratio

central processing unit

IPOR

IPSR

IRQ

ITM

LCD

LIN

interrupt program status register

interrupt request

CRC

cyclic redundancy check, an error-checking

protocol

instrumentation trace macrocell

liquid crystal display

DAC

DFB

DIO

digital-to-analog converter, see also IDAC, VDAC

digital filter block

Local Interconnect Network, a communications

protocol.

digital input/output, GPIO with only digital

capabilities, no analog. See GPIO.

LR

link register

DMA

DNL

direct memory access, see also TD

differential nonlinearity, see also INL

do not use

LUT

LVD

LVI

lookup table

low-voltage detect, see also LVI

low-voltage interrupt, see also HVI

low-voltage transistor-transistor logic

multiply-accumulate

DNU

DR

port write data registers

digital system interconnect

data watchpoint and trace

error correcting code

LVTTL

MAC

MCU

MISO

NC

DSI

DWT

ECC

ECO

EEPROM

microcontroller unit

master-in slave-out

external crystal oscillator

no connect

electrically erasable programmable read-only

memory

NMI

nonmaskable interrupt

non-return-to-zero

NRZ

NVIC

NVL

opamp

PAL

EMI

electromagnetic interference

external memory interface

end of conversion

nested vectored interrupt controller

nonvolatile latch, see also WOL

operational amplifier

EMIF

EOC

EOF

EPSR

ESD

ETM

end of frame

programmable array logic, see also PLD

program counter

execution program status register

electrostatic discharge

embedded trace macrocell

PC

PCB

PGA

printed circuit board

programmable gain amplifier

Document Number: 001-53413 Rev. *L

Page 119 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Table 14-1. Acronyms Used in this Document (continued)

Acronym Description

PHUB

Table 14-1. Acronyms Used in this Document (continued)

Acronym

SOF

Description

peripheral hub

physical layer

start of frame

PHY

PICU

PLA

SPI

Serial Peripheral Interface, a communications

protocol

port interrupt control unit

programmable logic array

programmable logic device, see also PAL

phase-locked loop

SR

slew rate

SRAM

SRES

SWD

SWV

TD

static random access memory

software reset

PLD

PLL

serial wire debug, a test protocol

single-wire viewer

PMDD

POR

PRES

PRS

PS

package material declaration data sheet

power-on reset

transaction descriptor, see also DMA

total harmonic distortion

transimpedance amplifier

technical reference manual

transistor-transistor logic

transmit

precise power-on reset

THD

TIA

pseudo random sequence

port read data register

TRM

TTL

®

PSoC

PSRR

PWM

RAM

RISC

RMS

RTC

RTL

Programmable System-on-Chip™

power supply rejection ratio

pulse-width modulator

TX

UART

Universal Asynchronous Transmitter Receiver, a

communications protocol

random-access memory

reduced-instruction-set computing

root-mean-square

UDB

universal digital block

Universal Serial Bus

USB

real-time clock

USBIO

USB input/output, PSoC pins used to connect to

a USB port

register transfer language

remote transmission request

receive

RTR

RX

VDAC

WDT

voltage DAC, see also DAC, IDAC

watchdog timer

SAR

SC/CT

SCL

successive approximation register

switched capacitor/continuous time

WOL

write once latch, see also NVL

watchdog timer reset

external reset I/O pin

crystal

WRES

XRES

XTAL

2

I C serial clock

2

SDA

S/H

I C serial data

sample and hold

15. Reference Documents

SINAD

SIO

signal to noise and distortion ratio

PSoC® 3, PSoC® 5 Architecture TRM

PSoC® 3 Registers TRM

special input/output, GPIO with advanced

features. See GPIO.

SOC

start of conversion

Document Number: 001-53413 Rev. *L

Page 120 of 126

PSoC^®3: CY8C36 Family

Data Sheet

16. Document Conventions

16.1 Units of Measure

Table 16-1. Units of Measure

Symbol

°C

Unit of Measure

degrees Celsius

decibels

dB

fF

femtofarads

hertz

Hz

KB

kbps

Khr

kHz

kΩ

1024 bytes

kilobits per second

kilohours

kilohertz

kilohms

ksps

LSB

Mbps

MHz

MΩ

Msps

µA

kilosamples per second

least significant bit

megabits per second

megahertz

megaohms

megasamples per second

microamperes

microfarads

microhenrys

microseconds

microvolts

µF

µH

µs

µV

µW

mA

ms

mV

nA

microwatts

milliamperes

milliseconds

millivolts

nanoamperes

nanoseconds

nanovolts

ns

nV

Ω

ohms

pF

picofarads

ppm

ps

parts per million

picoseconds

seconds

s

sps

sqrtHz

V

samples per second

square root of hertz

volts

Document Number: 001-53413 Rev. *L

Page 121 of 126

PSoC^®3: CY8C36 Family

Data Sheet

17. Revision History

Description Title: PSoC^®3: CY8C36 Family Data Sheet Programmable System-on-Chip (PSoC^®)

Document Number: 001-53413

Submission Orig. of

Rev.

ECN No.

Description of Change

Date

Change

**

2714854

2758970

06/04/09

09/02/09

PVKV

New data sheet

*A

MKEA

Updated Part Numbering Conventions

Added Section 11.7.5 (EMIF Figures and Tables)

Updated GPIO and SIO AC specifications

Updated XRES Pin Description and Xdata Address Map specifications

Updated DFB and Comparator specifications

Updated PHUB features section and RTC in sleep mode

Updated IDAC and VDAC DC and Analog Global specifications

Updated USBIO AC and Delta Sigma ADC specifications

Updated PPOR and Voltage Monitors DC specifications

Updated Drive Mode diagram

Added 48-QFN Information

Updated other electrical specifications

*B

2824546

12/09/09

MKEA

Updated I2C section to reflect 1 Mbps. Updated Table 11-6 and 11-7 (Boost AC

and DC specs); also added Shottky Diode specs. Changed current for

sleep/hibernate mode to include SIO; Added footnote to analog global specs.

Updated Figures 1-1, 6-2, 7-14, and 8-1. Updated Table 6-2 and Table 6-3

(Hibernate and Sleep rows) and Power Modes section. Updated GPIO and SIO

AC specifications. Updated Gain error in IDAC and VDAC specifications.

Updated description of V

spec in Table 11-1 and removed GPIO Clamp

DDA

Current parameter. Updated number of UDBs on page 1.

Moved FILO from ILO DC to AC table.

Added PCB Layout and PCB Schematic diagrams.

Updated Fgpioout spec (Table 11-9). Added duty cycle frequency in PLL AC spec

table. Added note for Sleep and Hibernate modes and Active Mode specs in Table

11-2. Linked URL in Section 10.3 to PSoC Creator site.

Updated Ja and Jc values in Table 13-1. Updated Single Sample Mode and Fast

FIR Mode sections. Updated Input Resistance specification in Del-Sig ADC table.

Added Tio_init parameter. Updated PGA and UGB AC Specs. Removed SPC

ADC. Updated Boost Converter section.

Added section 'SIO as Comparator'; updated Hysteresis spec (differential mode)

in Table 11-10.

Updated V

condition and deleted Vstart parameter in Table 11-6.

BAT

Added 'Bytes' column for Tables 4-1 to 4-5.

*C

2873322

02/04/10

MKEA

Changed maximum value of PPOR_TR to '1'. Updated V

specification.

BIAS

Updated PCB Schematic. Updated Figure 8-1 and Figure 6-3. Updated Interrupt

Vector table, Updated Sales links. Updated JTAG and SWD specifications.

Removed Jp-p and Jperiod from ECO AC Spec table. Added note on sleep timer

in Table 11-2. Updated ILO AC and DC specifications. Added Resolution

parameter in VDAC and IDAC tables. Updated I

typical and maximum values.

OUT

Changed Temperature Sensor range to –40 °C to +85 °C. Removed Latchup

specification from Table 11-1.

Document Number: 001-53413 Rev. *L

Page 122 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Description Title: PSoC^®3: CY8C36 Family Data Sheet Programmable System-on-Chip (PSoC^®)

Document Number: 001-53413

*D 2903576 04/01/10

MKEA

Updated Vb pin in PCB Schematic

Updated Tstartup parameter in AC Specifications table

Added Load regulation and Line regulation parameters to Inductive Boost

Regulator DC Specifications table

Updated I parameter in LCD Direct Drive DC Specs table

CC

Updated I

parameter in LCD Direct Drive DC Specs table

OUT

Updated Table 6-2 and Table 6-3

Added bullets on CapSense in page 1; added CapSense column in Section 12

Removed some references to footnote [1]

Changed INC_Rn cycles from 3 to 2 (Table 4-1)

Added footnote in PLL AC Specification table

Added PLL intermediate frequency row with footnote in PLL AC Specs table

Added UDBs subsection under 11.6 Digital Peripherals

Updated Figure 2-6 (PCB Layout)

Updated Pin Descriptions section and modified Figures 6-6, 6-8, 6-9

Updated LVD in Tables 6-2 and 6-3; modified Low-power modes bullet in page 1

Added note to Figures 2-5 and 6-2; Updated Figure 6-2 to add capacitors for V

DDA

and V

Changed V

pins.

DDD

from 0.9 to 0.1%

REF

Updated boost converter section (6.2.2)

Updated Tstartup values in Table 11-3.

Removed IPOR rows from Table 11-68. Updated 6.3.1.1, Power Voltage Level

Monitors.

Updated section 5.2 and Table 11-2 to correct suggestion of execution from flash.

Updated V

specs in Table 11-21.

REF

Updated IDAC uncompensated gain error in Table 11-25.

Updated Delay from Interrupt signal input to ISR code execution from ISR code

in Table11- 72. Removed other line in table.

Added sentence to last paragraph of section 6.1.1.3.

Updated T

, high and low-power modes, in Table 11-24.

RESP

Updated f_TCK values in Table 11-73 and f_SWDCK values in Table 11-74.

Updated SNR condition in Table 11-20.

Corrected unit of measurement in Table 11-21.

Updated sleep wakeup time in Table 6-3 and Tsleep in Table 11-3.

Added 1.71 V <= V

< 3.3 V, SWD over USBIO pins value to Table 11-74.

DDD

Removed mention of hibernate reset (HRES) from page 1 features, Table 6-3,

Section 6.2.1.4, Section 6.3, and Section 6.3.1.1. Change PPOR/PRES to TBDs

in Section 6.3.1.1, Section 6.4.1.6 (changed PPOR to reset), Table 11-3 (changed

PPOR to PRES), Table 11-68 (changed title, values TBD), and Table 11-69

(changed PPOR_TR to PRES_TR).

Added sentence saying that LVD

circuits can generate a reset to Section 6.3.1.1.

Changed I values on page 1, page 5, and Table 11-2.

DD

Changed resume time value in Section 6.2.1.3.

Changed ESD HBM value in Table 11-1.

Changed sample rate row in Table 11-20.

Removed V

= 1.65 V rows and changed BWag value in Table 11-22.

values and changed CMRR value in Table 11-23.

DDA

Changed V

IOFF

Changed INL max value in Table 11-27.

Added max value to the Quiescent current specs in Tables 11-29 and 11-31.

Changed occurrences of “Block” to “Row” and deleted the “ECC not included”

footnote in Table 11-57.

Changed max response time value in Tables 11-69 and 11-71.

Changed the Startup time in Table 11-79.

Added condition to intermediate frequency row in Table 11-85.

Added row to Table 11-69.

Added brown out note to Section 11.8.1.

Document Number: 001-53413 Rev. *L

Page 123 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Description Title: PSoC^®3: CY8C36 Family Data Sheet Programmable System-on-Chip (PSoC^®)

Document Number: 001-53413

*E

2938381

05/27/10

MKEA

Replaced V

with V

in USBIO diagram and specification tables, added

DDD

DDIO

text in USBIO section of Electrical Specifications.

Added Table 13-2 (Package MSL)

Modified Tstorag condition and changed max spec to 100

Added bullet (Pass) under ALU (section 7.2.2.2)

Added figures for kHzECO and MHzECO in the External Oscillator section

Updated Figure 6-1(Clocking Subsystem diagram)

Removed CPUCLK_DIV in table 5-2, Deleted Clock Divider SFR subsection

Updated PSoC Creator Framework image

Updated SIO DC Specifications (V and V parameters)

IH

IL

Updated bullets in Clocking System and Clocking Distribution sections

Updated Figure 8-2

Updated PCB Layout and Schematic, updated as per MTRB review comments

Updated Table 6-3 (power changed to current)

In 32kHZ EC DC Specifications table, changed I Max to 0.25

CC

In IMO DC Specifications table, updated Supply Current values

Updated GPIO DC Specs table

*F

2958674

2989685

06/22/10

08/04/10

SHEA

MKEA

Minor ECN to post data sheet to external website

*G

Added USBIO 22 ohm DP and DM resistors to Simplified Block Diagram

Added to Table 6-6 a footnote and references to same.

Added sentences to the resistive pull-up and pull-down description bullets.

Added sentence to Section 6.4.11, Adjustable Output Level.

Updated section 5.5 External Memory Interface

Updated Table 11-73 JTAG Interface AC Specifications

Updated Table 11-74 SWD Interface AC Specifications

Updated style changes as per the new template.

*H

*I

3078568

11/04/10

MKEA

Updated “Current Digital-to-analog Converter (IDAC)” on page 86

Updated “Voltage Digital to Analog Converter (VDAC)” on page 91

Updated “DC Specifications” on page 65

Updated “Voltage Reference Specifications” on page 85

3107314 12/10/2010

Updated delta-sigma tables and graphs.

Updated Flash AC specs

Formatted table 11.2.

Updated interrupt controller table

Updated transimpedance amplifier section

Updated SIO DC specs table

Updated Voltage Monitors DC Specifications table

Updated LCD Direct Drive DC specs table

Replaced the Discrete Time Mixer and Continuous Time Mixer tables with Mixer

DC and AC specs tables

Updated ESD

value.

HBM

Updated IDAC and VDAC sections

Removed ESO parts from ordering information

Changed USBIO pins from NC to DNU and removed redundant USBIO pin

description notes

Updated POR with brown out DC and AC specs

Updated PGA AC specs

Updated 32 kHz External Crystal DC Specifications

Updated opamp AC specs

Updated XRES IO specs

Updated Inductive boost regulator section

Delta sigma ADC spec updates

Updated comparator section

Removed buzz mode from Power Mode Transition diagram

Updated opamp DC and AC spec tables

Updated PGA DC table

*J

3179219

02/22/2011

MKEA

Updated conditions for flash data retention time.

Updated 100-pin TQFP package spec.

Updated EEPROM AC specifications.

Document Number: 001-53413 Rev. *L

Page 124 of 126

PSoC^®3: CY8C36 Family

Data Sheet

Description Title: PSoC^®3: CY8C36 Family Data Sheet Programmable System-on-Chip (PSoC^®)

Document Number: 001-53413

*K 3200146 03/28/2011

MKEA

Removed Preliminary status from the data sheet.

Updated JTAG ID

Deleted Cin_G1, ADC input capacitance from Delta-Sigma ADC DC spec table

Updated JTAG Interface AC Specifications and SWD Interface Specifications

tables

Updated USBIO DC specs

Added 0.01 to max speed

Updated Features on page 1

Added Section 5.5, Nonvolatile Latches

Updated Flash AC specs

Added CAN DC specs

Updated delta-sigma graphs, noise histogram figures and RMS Noise spec tables

Add reference to application note AN58304 in section 8.1

Updated 100-pin TQFP package spec

Added oscillator, I/O, VDAC, regulator graphs

Updated JTAG/SWD timing diagrams

Updated GPIO and SIO AC specs

Updated POR with Brown Out AC spec table

Updated IDAC graphs

Added DMA timing diagram, interrupt timing and interrupt vector, I2C timing

diagrams

Updated opamp graphs and PGA graphs

Added full chip performance graphs

Changed MHzECO range.

Added “Solder Reflow Peak Temperature” table.

*L

3259185

05/17/2011

MKEA

Added JTAG and SWD interface connection diagrams

Updated T and T values in Table 13-1

JA

JC

Changed typ and max values for the TCVos parameter in Opamp DC

specifications table.

Updated Clocking subsystem diagram.

Changed Vssd to Vssb in the PSoC Power System diagram

Updated Ordering information.

Document Number: 001-53413 Rev. *L

Page 125 of 126

PSoC^®3: CY8C36 Family

Data Sheet

18. Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturers’ representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

Products

PSoC Solutions

Automotive

cypress.com/go/automotive

cypress.com/go/clocks

cypress.com/go/interface

cypress.com/go/powerpsoc

cypress.com/go/plc

psoc.cypress.com/solutions

PSoC 1 | PSoC 3 | PSoC 5

Clocks & Buffers

Interface

Lighting & Power Control

Memory

cypress.com/go/memory

cypress.com/go/image

cypress.com/go/psoc

Optical & Image Sensing

PSoC

Touch Sensing

USB Controllers

Wireless/RF

cypress.com/go/touch

cypress.com/go/USB

cypress.com/go/wireless

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for

medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-53413 Rev. *L

Revised May 20, 2011

Page 126 of 126

CapSense^®, PSoC^®3, PSoC^®5, and PSoC^®Creator™ are trademarks and PSoC^®is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced

herein are property of the respective corporations.

Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided

that the system conforms to the I2C Standard Specification as defined by Philips.

ARM is a registered trademark, and Keil, and RealView are trademarks, of ARM Limited. All products and company names mentioned in this document may be the trademarks of their respective holders.


型号：	CY8C3666LTI-027T
厂家：	CYPRESS
描述：	Multifunction Peripheral, CMOS, QFN-68 多功能外围设备微控制器和处理器时钟
文件：	总126页 (文件大小：4339K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY8C3666LTI-027T [CYPRESS]

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