CY8C3666PVA-026_技术文档

PSoC^®3: CY8C36

Automotive Family Datasheet

Programmable System-on-Chip (PSoC^®)

General Description

With its unique array of configurable blocks, PSoC^®3 is a true system level solution providing microcontroller unit (MCU), memory,

analog, and digital peripheral functions in a single chip while being AEC-Q100 compliant. The CY8C36 family offers a modern method

of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans

the range from thermocouples (near DC voltages) to ultrasonic signals. The CY8C36 family can handle dozens of data acquisition

channels and analog inputs on every general-purpose input/output (GPIO) pin. The CY8C36 family is also a high-performance

configurable digital system with some part numbers including interfaces such as USB, multimaster inter-integrated circuit (I²C), and

controller area network (CAN). In addition to communication interfaces, the CY8C36 family has an easy to configure logic array, flexible

routing to all I/O pins, and a high-performance single cycle 8051 microprocessor core. You can easily create system-level designs

using a rich library of prebuilt components and boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool.

The CY8C36 family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating

last minute design changes through simple firmware updates.

 Library of standard peripherals

Features

• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs

 Single cycle 8051 CPU

• Serial peripheral interface (SPI), universal asynchronous

 DC to 67 MHz operation

 Multiply and divide instructions

 Flash program memory, up to 64 KB, 100,000 write cycles,

20 years retention, and multiple security features

 512-byte flash cache

 Up to 8-KB flash error correcting code (ECC) or configuration

transmitter receiver (UART), and I²C

• Many others available in catalog

 Library of advanced peripherals

• Cyclic redundancy check (CRC)

• Pseudo random sequence (PRS) generator

• Local interconnect network (LIN) bus 2.0

storage

 Up to 8 KB SRAM

• Quadrature decoder

 Analog peripherals (1.71 V  VDDA  5.5 V)

 1.024 V ± 0.1% internal voltage reference across –40 °C to

+85 °C

 Configurable delta-sigma ADC with 8- to 12-bit resolution

• Sample rates up to 192 ksps

• Programmable gain stage: ×0.25 to ×16

 Up to 2 KB electrically erasable programmable read-only

memory (EEPROM), 1 M cycles, and 20 years retention

 24-channel direct memory access (DMA) with multilayer

AHB^[1]bus access

• Programmable chained descriptors and priorities

• High bandwidth 32-bit transfer support

• 12-bit mode, 192 ksps, 66-dB signal to noise and distortion

ratio (SINAD), ±1-bit INL/DNL

 Low voltage, ultra low-power

 Wide operating voltage range: 1.71 V to 5.5 V

 0.8 mA at 3 MHz, 1.2 mA at 6 MHz, and 6.6 mA at 50 MHz

 Low-power modes including:

 Up to four 8-bit, 8-Msps IDACs or 1-Msps VDACs

 Four comparators with 95-ns response time

 Up to four uncommitted opamps with 25-mA drive capability

 Up to four configurable multifunction analog blocks. Example

configurations are programmable gain amplifier (PGA),

transimpedance amplifier (TIA), mixer, and sample and hold

 CapSense support

 Programming, debug, and trace

 JTAG (4-wire), serial wire debug (SWD) (2-wire), and single

wire viewer (SWV) interfaces

• 1-µA sleep mode with real time clock and low-voltage

detect (LVD) interrupt

• 200-nA hibernate mode with RAM retention

 Versatile I/O system

 29 to 72 I/O (62 GPIOs, eight special input/outputs (SIO),

two USBIOs^[2]

)

 Any GPIO to any digital or analog peripheral routability

 LCD direct drive from any GPIO, up to 46 × 16 segments^[2]

 CapSense^®support from any GPIO^[3]

 1.2-V to 5.5-V I/O interface voltages, up to four domains

 Maskable, independent IRQ on any pin or port

 Schmitt-trigger transistor-transistor logic (TTL) inputs

 All GPIO configurable as open drain high/low, pull-up/

pull-down, High Z, or strong output

 Configurable GPIO pin state at power-on reset (POR)

 25 mA sink on SIO

 Digital peripherals

 Eight address and one data breakpoint

 4-KB instruction trace buffer

 Bootloader programming supportable through I²C, SPI,

UART, USB, and other interfaces

 Precision, programmable clocking

 3- to 62-MHz internal oscillator over full temperature and

voltage range

 4- to 25-MHz crystal oscillator for crystal PPM accuracy

 Internal PLL clock generation up to 67 MHz

 32.768-kHz watch crystal oscillator

 Low-power internal oscillator at 1, 33, and 100 kHz

 Temperature and packaging

 –40 °C to +85 °C degrees automotive temperature

 –40 °C to +125 °C Extended temperature range

 48-pin SSOP, and 100-pin TQFP package options

 AEC-Q100 compliant.

 20 to 24 programmable logic device (PLD) based universal

digital blocks (UDB)

 Full CAN 2.0b 16 Rx, 8 Tx buffers^[2]

 USB 2.0 certified Full-Speed (FS) 12 Mbps peripheral

interface (TID#40770053) using internal oscillator^[2]

 Up to four 16-bit configurable timer, counter, and PWM blocks

 67 MHz, 24-bit fixed point digital filter block (DFB) to

implement FIR and IIR filters

Notes

1. AHB – AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus

2. This feature on select devices only. See Ordering Information on page 133 for details.

3. GPIOs with opamp outputs are not recommended for use with CapSense.

Cypress Semiconductor Corporation

Document Number: 001-57330 Rev. *G

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 14, 2014

PSoC^®3: CY8C36

Automotive Family Datasheet

Contents

1. Architectural Overview ..................................................3

2. Pinouts ............................................................................5

3. Pin Descriptions .............................................................9

8.6 LCD Direct Drive ...................................................57

8.7 CapSense ..............................................................58

8.8 Temp Sensor .........................................................58

8.9 DAC .......................................................................59

8.10 Up/Down Mixer ....................................................59

8.11 Sample and Hold .................................................59

4. CPU ................................................................................10

4.1 8051 CPU ..............................................................10

4.2 Addressing Modes .................................................10

4.3 Instruction Set .......................................................10

4.4 DMA and PHUB ....................................................15

4.5 Interrupt Controller ................................................17

9. Programming, Debug Interfaces, Resources .............60

9.1 JTAG Interface ......................................................60

9.2 Serial Wire Debug Interface ..................................62

9.3 Debug Features .....................................................63

9.4 Trace Features ......................................................63

9.5 Single Wire Viewer Interface .................................63

9.6 Programming Features ..........................................63

9.7 Device Security .....................................................63

5. Memory ..........................................................................21

5.1 Static RAM ............................................................21

5.2 Flash Program Memory .........................................21

5.3 Flash Security ........................................................21

5.4 EEPROM ...............................................................21

5.5 Nonvolatile Latches (NVLs) ...................................22

5.6 External Memory Interface ....................................23

5.7 Memory Map .........................................................24

10. Development Support ................................................64

10.1 Documentation ....................................................64

10.2 Online ..................................................................64

10.3 Tools ....................................................................64

6. System Integration .......................................................26

6.1 Clocking System ....................................................26

6.2 Power System .......................................................29

6.3 Reset .....................................................................31

6.4 I/O System and Routing ........................................33

11. Electrical Specifications ............................................65

11.1 Absolute Maximum Ratings .................................65

11.2 Device Level Specifications .................................66

11.3 Power Regulators ................................................72

11.4 Inputs and Outputs ..............................................74

11.5 Analog Peripherals ..............................................86

11.6 Digital Peripherals .............................................114

11.7 Memory .............................................................120

11.8 PSoC System Resources ..................................126

11.9 Clocking .............................................................129

7. Digital Subsystem ........................................................40

7.1 Example Peripherals .............................................40

7.2 Universal Digital Block ...........................................42

7.3 UDB Array Description ..........................................45

7.4 DSI Routing Interface Description .........................45

7.5 CAN .......................................................................47

7.6 USB .......................................................................49

7.7 Timers, Counters, and PWMs ...............................49

7.8 I²C .........................................................................50

7.9 Digital Filter Block ..................................................51

12. Ordering Information ................................................134

12.1 Part Numbering Conventions ............................135

13. Packaging ..................................................................136

14. Acronyms ..................................................................138

15. Reference Documents ..............................................139

8. Analog Subsystem .......................................................51

8.1 Analog Routing ......................................................52

8.2 Delta-sigma ADC ...................................................54

8.3 Comparators ..........................................................55

8.4 Opamps .................................................................56

8.5 Programmable SC/CT Blocks ...............................56

16. Document Conventions ...........................................140

16.1 Units of Measure ...............................................140

17. Revision History .......................................................141

18. Sales, Solutions, and Legal Information ................143

Document Number: 001-57330 Rev. *G

Page 2 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

1. Architectural Overview

Introducing the CY8C36 family of ultra low-power, flash Programmable System-on-Chip (PSoC^®) devices, part of a scalable 8-bit

PSoC 3 and 32-bit PSoC 5 platform. The CY8C36 family provides configurable blocks of analog, digital, and interconnect circuitry

around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables

a high level of integration in a wide variety of automotive consumer, industrial, and medical applications.

Figure 1-1. Simplified Block Diagram

Analog Interconnect

Digital Interconnect

Digital System

System Wide

Resources

I²

C

Universal Digital Block Array (24x UDB)

CAN

2.0

8-bit

Timer

Quadrature Decoder

16-bit PRS

Master/

Slave

16-bit

PWM

4to25MHz

(Optional)

UDB

22 

Xtal

Osc

USB

PHY

UDB

8-bit

Timer

FS USB

2.0

UDB

I²C Slave

UDB

4x

8-bit SPI

Logic

Timer

Counter

PWM

12-bit SPI

UDB

IMO

Logic

32.768 KHz

(Optional)

UDB

UART

12-bit PWM

RTC

Timer

System Bus

Program

Debug

&

Memory System

CPU System

WDT

and

Wake

8051

Interrupt

Controller

EEPROM

SRAM

Program

Debug

Trace

&

PHUB

DMA

FLASH

EMIF

Boundary

Scan

ILO

Clocking System

Analog System

ADC

Digital

Filter

Block

Power Management

System

LCD Direct

Drive

+

4 x

Opamp

POR and

LVD

3 per

Opamp

-

4 x SC/CT Blocks

(TIA, PGA, Mixer etc)

Sleep

Power

+

4 x

CMP

-

Del Sig

ADC

Temperature

Sensor

1.8V LDO

4 x DAC

CapSense

Figure 1-1 illustrates the major components of the CY8C36

family. They are:

PSoC’s digital subsystem provides half of its unique

configurability. It connects a digital signal from any peripheral to

any pin through the digital system interconnect (DSI). It also

provides functional flexibility through an array of small, fast,

low-power UDBs. PSoC Creator provides a library of prebuilt and

tested standard digital peripherals (UART, SPI, LIN, PRS, CRC,

timer, counter, PWM, AND, OR, and so on) that are mapped to

the UDB array. You can also easily create a digital circuit using

boolean primitives by means of graphical design entry. Each

UDB contains programmable array logic (PAL)/programmable

logic device (PLD) functionality, together with a small state

machine engine to support a wide variety of peripherals.

 8051 CPU subsystem

 Nonvolatile subsystem

 Programming, debug, and test subsystem

 Inputs and outputs

 Clocking

 Power

 Digital subsystem

 Analog subsystem

In addition to the flexibility of the UDB array, PSoC also provides

configurable digital blocks targeted at specific functions. For the

CY8C36 family these blocks can include four 16-bit timers,

counters, and PWM blocks; I²C slave, master, and multimaster;

FS USB; and Full CAN 2.0b.

Document Number: 001-57330 Rev. *G

Page 3 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

For more details on the peripherals see the “Example

Peripherals” section on page 40 of this data sheet. For

information on UDBs, DSI, and other digital blocks, see the

“Digital Subsystem” section on page 40 of this data sheet.

PSoC’s 8051 CPU subsystem is built around a single cycle

pipelined 8051 8-bit processor running at up to 67 MHz. The

CPU subsystem includes a programmable nested vector

interrupt controller, DMA controller, and RAM. PSoC’s nested

vector interrupt controller provides low latency by allowing the

CPU to vector directly to the first address of the interrupt service

routine, bypassing the jump instruction required by other

architectures. The DMA controller enables peripherals to

exchange data without CPU involvement. This allows the CPU

to run slower (saving power) or use those CPU cycles to improve

the performance of firmware algorithms. The single cycle 8051

CPU runs ten times faster than a standard 8051 processor. The

processor speed itself is configurable, allowing you to tune active

power consumption for specific applications.

PSoC’s analog subsystem is the second half of its unique

configurability. All analog performance is based on a highly

accurate absolute voltage reference with less than 0.1-percent

error over temperature and voltage. The configurable analog

subsystem includes:

 Analog muxes

 Comparators

 Voltage references

 Analog-to-digital converter (ADC)

 Digital-to-analog converters (DACs)

 Digital filter block (DFB)

PSoC’s nonvolatile subsystem consists of flash, byte-writeable

EEPROM, and nonvolatile configuration options. It provides up

to 64 KB of on-chip flash. The CPU can reprogram individual

blocks of flash, enabling bootloaders. You can enable an error

correcting code (ECC) for high reliability applications. A powerful

and flexible protection model secures the user's sensitive

information, allowing selective memory block locking for read

and write protection. Up to 2 KB of byte-writeable EEPROM is

available on-chip to store application data. Additionally, selected

configuration options such as boot speed and pin drive mode are

stored in nonvolatile memory. This allows settings to activate

immediately after POR.

All GPIO pins can route analog signals into and out of the device

using the internal analog bus. This allows the device to interface

up to 62 discrete analog signals. The heart of the analog

subsystem is a fast, accurate, configurable delta-sigma ADC

with these features ^[4]

:

 Less than 100 µV offset

 A gain error of 0.2 percent

 INL less than ±2 LSB

 DNL less than ±1 LSB

The three types of PSoC I/O are extremely flexible. All I/Os have

many drive modes that are set at POR. PSoC also provides up

to four I/O voltage domains through the VDDIO pins. Every GPIO

has analog I/O, LCD drive^[5], CapSense^[6], flexible interrupt

generation, slew rate control, and digital I/O capability. The SIOs

on PSoC allow V_OHto be set independently of Vddio when used

as outputs. When SIOs are in input mode they are high

impedance. This is true even when the device is not powered or

when the pin voltage goes above the supply voltage. This makes

the SIO ideally suited for use on an I²C bus where the PSoC may

not be powered when other devices on the bus are. The SIO pins

also have high current sink capability for applications such as

LED drives. The programmable input threshold feature of the

SIO can be used to make the SIO function as a general purpose

analog comparator. For devices with Full-Speed USB the USB

physical interface is also provided (USBIO). When not using

USB these pins may also be used for limited digital functionality

and device programming. All of the features of the PSoC I/Os are

covered in detail in the “I/O System and Routing” section on

page 33 of this data sheet.

 SINAD better than 84 dB in 16-bit mode

This converter addresses a wide variety of precision analog

applications, including some of the most demanding sensors.

The output of the ADC can optionally feed the programmable

DFB through the DMA without CPU intervention. You can

configure the DFB to perform IIR and FIR digital filters and

several user-defined custom functions. The DFB can implement

filters with up to 64 taps. It can perform a 48-bit

multiply-accumulate (MAC) operation in one clock cycle.

Four high-speed voltage or current DACs support 8-bit output

signals at an update rate of up to 8 Msps. They can be routed

out of any GPIO pin. You can create higher resolution voltage

PWM DAC outputs using the UDB array. This can be used to

create a pulse width modulated (PWM) DAC of up to 10 bits, at

up to 48 kHz. The digital DACs in each UDB support PWM, PRS,

or delta-sigma algorithms with programmable widths. In addition

to the ADC, DACs, and DFB, the analog subsystem provides

multiple:

 Uncommitted opamps

The PSoC device incorporates flexible internal clock generators,

designed for high stability and factory trimmed for high accuracy.

The internal main oscillator (IMO) is the clock base for the

system, and has 1-percent accuracy at 3 MHz. The IMO can be

configured to run from 3 MHz up to 62 MHz. Multiple clock

derivatives can be generated from the main clock frequency to

meet application needs. The device provides a PLL to generate

clock frequencies up to 67 MHz from the IMO, external crystal,

or external reference clock.

 Configurable switched capacitor/continuous time (SC/CT)

blocks. These support:

 Transimpedance amplifiers

 Programmable gain amplifiers

 Mixers

 Other similar analog components

See the “Analog Subsystem” section on page 51 of this data

sheet for more details.

Notes

4. Refer Electrical Specifications on page 65 for the detailed ADC specification across entire voltage range and temperature.

5. This feature on select devices only. See Ordering Information on page 133 for details.

6. GPIOs with opamp outputs are not recommended for use with CapSense.

Document Number: 001-57330 Rev. *G

Page 4 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

It also contains a separate, very low-power internal low-speed

oscillator (ILO) for the sleep and watchdog timers. A 32.768-kHz

external watch crystal is also supported for use in real-time

clock (RTC) applications. The clocks, together with

programmable clock dividers, provide the flexibility to integrate

most timing requirements.

2. Pinouts

Each VDDIO pin powers a specific set of I/O pins. (The USBIOs

are powered from VDDD.) Using the VDDIO pins, a single PSoC

can support multiple voltage levels, reducing the need for

off-chip level shifters. The black lines drawn on the pinout

diagrams in Figure 2-3 through Figure 2-4 show the pins that are

powered by each VDDIO.

The CY8C36 family supports a wide supply operating range from

1.71 V to 5.5 V. This allows operation from regulated supplies

such as 1.8 V ± 5%, 2.5 V ±10%, 3.3 V ± 10%, or 5.0 V ± 10%,

or directly from a wide range of battery types.

Each VDDIO may source up to 100 mA ^[7]total to its associated

I/O pins, as shown in Figure 2-1.

PSoC supports a wide range of low-power modes. These include

a 200-nA hibernate mode with RAM retention and a 1-µA sleep

mode with RTC. In the second mode, the optional 32.768-kHz

watch crystal runs continuously and maintains an accurate RTC.

Figure 2-1. VDDIO Current Limit

I_{DDIO X}= 100 mA

Power to all major functional blocks, including the programmable

digital and analog peripherals, can be controlled independently

by firmware. This allows low-power background processing

when some peripherals are not in use. This, in turn, provides a

total device current of only 1.2 mA when the CPU is running at

6 MHz, or 0.8 mA running at 3 MHz.

V_{DDIO X}

I/O Pins

PSoC

The details of the PSoC power modes are covered in the “Power

System” section on page 29 of this data sheet.

PSoC uses JTAG (4-wire) or SWD (2-wire) interfaces for

programming, debug, and test. The 1-wire SWV may also be

used for ‘printf’ style debugging. By combining SWD and SWV,

you can implement a full debugging interface with just three pins.

Using these standard interfaces you can debug or program the

PSoC with a variety of hardware solutions from Cypress or third

party vendors. PSoC supports on-chip break points and 4-KB

instruction and data race memory for debug. Details of the

programming, test, and debugging interfaces are discussed in

the “Programming, Debug Interfaces, Resources” section on

page 60 of this data sheet.

Conversely, for the 100-pin and 68-pin devices, the set of I/O

pins associated with any VDDIO may sink up to 100 mA ^[7]total,

as shown in Figure 2-2.

Figure 2-2. I/O Pins Current Limit

Ipins = 100 mA

V_{DDIO X}

I/O Pins

PSoC

V_SSD

For the 48-pin devices, the set of I/O pins associated with

VDDIO0 plus VDDIO2 may sink up to 100 mA ^[7]total. The set

of I/O pins associated with VDDIO1 plus VDDIO3 may sink up to

a total of 100 mA.

Note

7. The 100 mA source/ sink current per Vddio is valid only for temperature range of –40 °C to +85 °C. For extended temperature range of –40 °C to +125 °C, the maximum

source or sink current per Vddio is 40 mA.

Document Number: 001-57330 Rev. *G

Page 5 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

Figure 2-3. 48-pin SSOP Part Pinout

(SIO) P12[2]

(SIO) P12[3]

VDDA

VSSA

VCCA

1

2

48

47

46

Lines show

VDDIO to I/O

supply

(Opamp2OUT, GPIO) P0[0]

(Opamp0OUT, GPIO) P0[1]

(Opamp0+, GPIO) P0[2]

(Opamp0-/Extref0, GPIO) P0[3]

VDDIO0

3

4

45 P15[3] (GPIO, KHZ XTAL: XI)

44 P15[2] (GPIO, KHZ XTAL: XO)

43 P12[1] (SIO, I2C1: SDA)

42 P12[0] (SIO, I2C1: SCL)

41 VDDIO3

5

association

6

7

(Opamp2+, GPIO) P0[4]

(Opamp2-, GPIO) P0[5]

(IDAC0, GPIO) P0[6]

(IDAC2, GPIO) P0[7]

VCCD

8

9

40 P15[1] (GPIO, MHZ XTAL: XI)

P15[0] (GPIO, MHZ XTAL: XO)

10

11

12

13

39

38

37

36

VCCD

VSSD

VDDD

SSOP

VSSD

[8]

VDDD 14

(GPIO) P2[3]

35 P15[7] (USBIO, D-, SWDCK)

[8]

P15[6] (USBIO, D+, SWDIO)

P1[7] (GPIO)

15

16

17

18

19

20

21

22

23

34

33

32

31

30

29

28

27

26

(GPIO) P2[4]

VDDIO2

P1[6] (GPIO)

(GPIO) P2[5]

(GPIO) P2[6]

(GPIO) P2[7]

VSSD

VDDIO1

P1[5] (GPIO, nTRST)

P1[4] (GPIO, TDI)

P1[3] (GPIO, TDO, SWV)

NC

P1[2] (GPIO, Configurable XRES)

P1[1] (GPIO, TCK, SWDCK)

VSSD

VSSD 24

25 P1[0] (GPIO, TMS, SWDIO)

Note

8. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.

Document Number: 001-57330 Rev. *G

Page 6 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

Figure 2-4. 100-pin TQFP Part Pinout

(GPIO) P2[5]

(GPIO) P2[6]

(GPIO) P2[7]

VDDIO0

1

2

3

4

5

6

75

74

P0[3] (GPIO, Opamp0-/Extref0)

P0[2] (GPIO, Opamp0+)

P0[1] (GPIO, Opamp0OUT)

73

72

71

Lines show VDDIO

to I/O supply

association

(I2C0: SCL, SIO) P12[4]

(I2C0: SDA, SIO) P12[5]

(GPIO) P6[4]

P0[0] (GPIO, Opamp2OUT)

P4[1] (GPIO)

P4[0] (GPIO)

P12[3] (SIO)

P12[2] (SIO)

VSSD

70

69

(GPIO) P6[5]

(GPIO) P6[6]

(GPIO) P6[7]

7

8

9

68

67

66

10

VSSD

NC

VSSD

VDDA

VSSA

11

12

13

14

15

16

17

65

64

63

VCCA

NC

TQFP

VSSD

XRES

(GPIO) P5[0]

(GPIO) P5[1]

62

61

60

NC

59

58

57

56

55

(GPIO) P5[2]

(GPIO) P5[3]

(TMS, SWDIO, GPIO) P1[0]

18

19

20

21

22

NC

P15[3] (GPIO, KHZ XTAL: XI)

P15[2] (GPIO, KHZ XTAL: XO)

(TCK, SWDCK, GPIO) P1[1]

(Configurable XRES, GPIO) P1[2]

(TDO, SWV, GPIO) P1[3]

P12[1] (SIO, I2C1: SDA)

P12[0] (SIO, I2C1: SCL)

P3[7] (GPIO, Opamp3OUT)

54

53

52

51

23

(TDI, GPIO) P1[4]

(nTRST, GPIO) P1[5]

24

25

P3[6] (GPIO, Opamp1OUT)

Figure 2-5 and Figure 2-6 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal analog

performance on a two-layer board.

 The two pins labeled VDDD must be connected together.

 The two pins labeled VCCD must be connected together, with capacitance added, as shown in Figure 2-5 and Power System on

page 29. The trace between the two VCCD pins should be as short as possible.

 The two pins labeled Vssd must be connected together.

For information on circuit board layout issues for mixed signals, refer to the application note, AN57821 - Mixed Signal Circuit Board

Layout Considerations for PSoC® 3 and PSoC 5.

Note

9. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.

Document Number: 001-57330 Rev. *G

Page 7 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

Figure 2-5. Example Schematic for 100-pin TQFP Part with Power Connections

VDDD

C1

1uF

C2

0.1uF

VDDD

VCCD

C6

0.1uF

VSSD

VDDD

VDDA

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

P2[5]

P2[6]

P2[7]

P12[4], SIO

P12[5], SIO

P6[4]

P6[5]

P6[6]

P6[7]

VSSB

IND

VBOOST

VBAT

VSSD

XRES

P5[0]

P5[1]

VDDIO0

OA0-, REF0, P0[3]

OA0+, P0[2]

OA0OUT, P0[1]

OA2OUT, P0[0]

P4[1]

C8

0.1uF

C17

1uF

VSSD

P4[0]

VSSA

SIO, P12[3]

SIO, P12[2]

VSSD

VDDA

VSSA

VCCA

VDDA

VSSA

VCCA

NC

VSSD

C9

1uF

C10

0.1uF

P5[2]

P5[3]

NC

VSSA

P1[0], SWIO, TMS

P1[1], SWDIO, TCK

P1[2]

P1[3], SWV, TDO

P1[4], TDI

P1[5], NTRST

KHZXIN, P15[3]

KHZXOUT, P15[2]

SIO, P12[1]

SIO, P12[0]

OA3OUT, P3[7]

OA1OUT, P3[6]

VDDD

C11

0.1uF

C12

0.1uF

VSSD

C15

1uF

VSSD

C16

0.1uF

VSSD

Note The two Vccd pins must be connected together with as short a trace as possible. A trace under the device is recommended, as

shown in Figure 2-6 on page 9.

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Automotive Family Datasheet

Figure 2-6. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance

VSSA

VSSD

VDDD

VDDA

VSSA

Plane

VSSD

Plane

MHz XTAL: Xo, MHz XTAL: Xi

4- to 25-MHz crystal oscillator pin.

nTRST

3. Pin Descriptions

IDAC0, IDAC1, IDAC2, IDAC3

Low resistance output pin for high current DACs (IDAC).

Optional JTAG test reset programming and debug port

connection to reset the JTAG connection.

Opamp0OUT, Opamp1OUT, Opamp2OUT, Opamp3OUT

High current output of uncommitted opamp^[10]

.

SIO

Extref0, Extref1

Special I/O provides interfaces to the CPU, digital peripherals

and interrupts with a programmable high threshold voltage,

analog comparator, high sink current, and high impedance state

when the device is unpowered.

External reference input to the analog system.

Opamp0–, Opamp1–, Opamp2–, Opamp3–

Inverting input to uncommitted opamp.

Opamp0+, Opamp1+, Opamp2+, Opamp3+

Noninverting input to uncommitted opamp.

GPIO

SWDCK

Serial wire debug clock programming and debug port

connection.

SWDIO

Serial wire debug input and output programming and debug port

connection.

General purpose I/O pin provides interfaces to the CPU, digital

peripherals, analog peripherals, interrupts, LCD segment drive,

and CapSense^[10]

.

SWV

I2C0: SCL, I2C1: SCL

Single wire viewer debug output.

I²C SCL line providing wake from sleep on an address match.

Any I/O pin can be used for I²C SCL if wake from sleep is not

required.

TCK

JTAG test clock programming and debug port connection.

TDI

I2C0: SDA, I2C1: SDA

I²C SDA line providing wake from sleep on an address match.

Any I/O pin can be used for I²C SDA if wake from sleep is not

required.

JTAG test data in programming and debug port connection.

TDO

JTAG test data out programming and debug port connection.

TMS

kHz XTAL: Xo, kHz XTAL: Xi

32.768-kHz crystal oscillator pin.

JTAG test mode select programming and debug port connection.

Note

10. GPIOs with opamp outputs are not recommended for use with CapSense.

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Automotive Family Datasheet

USBIO, D+

4. CPU

Provides D+ connection directly to a USB 2.0 bus. May be used

as a digital I/O pin; it is powered from VDDD instead of from a

VDDIO. Pins are Do Not Use (DNU) on devices without USB.

4.1 8051 CPU

The CY8C36 devices use a single cycle 8051 CPU, which is fully

compatible with the original MCS-51 instruction set. The

CY8C36 family uses a pipelined RISC architecture, which

executes most instructions in 1 to 2 cycles to provide peak

performance of up to 33 MIPS with an average of 2 cycles per

instruction. The single cycle 8051 CPU runs ten times faster than

a standard 8051 processor.

USBIO, D–

Provides D– connection directly to a USB 2.0 bus. May be used

as a digital I/O pin; it is powered from VDDD instead of from a

VDDIO. Pins are Do Not Use (DNU) on devices without USB.

VCCA.

The 8051 CPU subsystem includes these features:

Output of the analog core regulator or the input to the

analog core. Requires a 1uF capacitor to VSSA. The regulator

output is not designed to drive external circuits. Note that if you

use the device with an external core regulator (externally

regulated mode), the voltage applied to this pin must not

exceed the allowable range of 1.71 V to 1.89 V. When using

the internal core regulator, (internally regulated mode, the

default), do not tie any power to this pin. For details see Power

System on page 29.

 Single cycle 8051 CPU

 Up to 64 KB of flash memory, up to 2 KB of EEPROM, and up

to 8 KB of SRAM

 512-byte instruction cache between CPU and flash

 Programmable nested vector interrupt controller

 DMA controller

 Peripheral HUB (PHUB)

VCCD.

 External memory interface (EMIF)

Output of the digital core regulator or the input to the digital

core. The two VCCD pins must be shorted together, with the

trace between them as short as possible, and a 1uF capacitor to

VSSD. The regulator output is not designed to drive external

circuits. Note that if you use the device with an external core

regulator (externally regulated mode), the voltage applied to

this pin must not exceed the allowable range of 1.71 V to

1.89 V. When using the internal core regulator (internally

regulated mode, the default), do not tie any power to this pin. For

details see Power System on page 29.

4.2 Addressing Modes

The following addressing modes are supported by the 8051:

 Direct Addressing: The operand is specified by a direct 8-bit

address field. Only the internal RAM and the SFRs can be

accessed using this mode.

 IndirectAddressing:Theinstructionspecifiestheregisterwhich

contains the address of the operand. The registers R0 or R1

are used to specify the 8-bit address, while the data pointer

(DPTR) register is used to specify the 16-bit address.

VDDA

Supply for all analog peripherals and analog core regulator.

VDDA must be the highest voltage present on the device. All

other supply pins must be less than or equal to VDDA.

 Register Addressing: Certain instructions access one of the

registers (R0 to R7) in the specified register bank. These

instructions are more efficient because there is no need for an

address field.

VDDD

Supply for all digital peripherals and digital core regulator. VDDD

must be less than or equal to VDDA.

 Register Specific Instructions: Some instructions are specific

to certain registers. For example, some instructions always act

on the accumulator. In this case, there is no need to specify the

operand.

VSSA

Ground for all analog peripherals.

VSSD

 Immediate Constants: Some instructions carry the value of the

constants directly instead of an address.

Ground for all digital logic and I/O pins.

VDDIO0, VDDIO1, VDDIO2, VDDIO3

 Indexed Addressing: This type of addressing can be used only

for a read of the program memory. This mode uses the Data

Pointer as the base and the accumulator value as an offset to

read a program memory.

Supply for I/O pins. Each VDDIO must be tied to a valid operating

voltage (1.71 V to 5.5 V), and must be less than or equal to

VDDA.

 Bit Addressing: In this mode, the operand is one of 256 bits.

XRES (and configurable XRES)

4.3 Instruction Set

External reset pin. Active low with internal pull-up. Pin P1[2] may

be configured to be a XRES pin; see “Nonvolatile Latches

(NVLs)” on page 22.

The 8051 instruction set is highly optimized for 8-bit handling and

Boolean operations. The types of instructions supported include:

 Arithmetic instructions

 Logical instructions

 Data transfer instructions

 Boolean instructions

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Automotive Family Datasheet

 Program branching instructions

4.3.1 Instruction Set Summary

4.3.1.1 Arithmetic Instructions

Arithmetic instructions support the direct, indirect, register, immediate constant, and register-specific instructions. Arithmetic modes

are used for addition, subtraction, multiplication, division, increment, and decrement operations. Table 4-1 lists the different arithmetic

instructions.

Table 4-1. Arithmetic Instructions

Mnemonic

ADD A,Rn

Description

Add register to accumulator

Bytes

Cycles

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

3

1

2

3

1

2

6

3

ADD A,Direct

ADD A,@Ri

ADD A,#data

ADDC A,Rn

Add direct byte to accumulator

Add indirect RAM to accumulator

Add immediate data to accumulator

Add register to accumulator with carry

Add direct byte to accumulator with carry

Add indirect RAM to accumulator with carry

Add immediate data to accumulator with carry

Subtract register from accumulator with borrow

Subtract direct byte from accumulator with borrow

Subtract indirect RAM from accumulator with borrow

Subtract immediate data from accumulator with borrow

Increment accumulator

ADDC A,Direct

ADDC A,@Ri

ADDC A,#data

SUBB A,Rn

SUBB A,Direct

SUBB A,@Ri

SUBB A,#data

INC

A

INC Rn

Increment register

INC Direct

INC @Ri

Increment direct byte

Increment indirect RAM

DEC

A

Decrement accumulator

DEC Rn

DEC Direct

DEC @Ri

INC DPTR

MUL

Decrement register

Decrement direct byte

Decrement indirect RAM

Increment data pointer

Multiply accumulator and B

DIV

Divide accumulator by B

DAA

Decimal adjust accumulator

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Automotive Family Datasheet

4.3.1.2 Logical Instructions

The logical instructions perform Boolean operations such as AND, OR, XOR on bytes, rotate of accumulator contents, and swap of

nibbles in an accumulator. The Boolean operations on the bytes are performed on the bit-by-bit basis. Table 4-2 shows the list of

logical instructions and their description.

Table 4-2. Logical Instructions

Mnemonic

ANL A,Rn

Description

AND register to accumulator

Bytes

Cycles

1

2

1

2

3

1

2

1

2

3

1

2

1

2

3

1

2

3

1

2

3

1

2

3

1

ANL A,Direct

ANL A,@Ri

AND direct byte to accumulator

AND indirect RAM to accumulator

AND immediate data to accumulator

AND accumulator to direct byte

AND immediate data to direct byte

OR register to accumulator

ANL A,#data

ANL Direct, A

ANL Direct, #data

ORL A,Rn

ORL A,Direct

ORL A,@Ri

OR direct byte to accumulator

OR indirect RAM to accumulator

OR immediate data to accumulator

OR accumulator to direct byte

OR immediate data to direct byte

XOR register to accumulator

XOR direct byte to accumulator

XOR indirect RAM to accumulator

XOR immediate data to accumulator

XOR accumulator to direct byte

XOR immediate data to direct byte

Clear accumulator

ORL A,#data

ORL Direct, A

ORL Direct, #data

XRL A,Rn

XRL A,Direct

XRL A,@Ri

XRL A,#data

XRL Direct, A

XRL Direct, #data

CLR

CPL

RL

A

Complement accumulator

Rotate accumulator left

RLC

RR

Rotate accumulator left through carry

Rotate accumulator right

RRC A

SWAP A

Rotate accumulator right though carry

Swap nibbles within accumulator

4.3.1.3 Data Transfer Instructions

addressing mode. Table 4-3 lists the various data transfer

instructions available.

The data transfer instructions are of three types: the core RAM,

xdata RAM, and the lookup tables. The core RAM transfer

includes transfer between any two core RAM locations or SFRs.

These instructions can use direct, indirect, register, and

immediate addressing. The xdata RAM transfer includes only the

transfer between the accumulator and the xdata RAM location.

It can use only indirect addressing. The lookup tables involve

nothing but the read of program memory using the Indexed

4.3.1.4 Boolean Instructions

The 8051 core has a separate bit-addressable memory location.

It has 128 bits of bit addressable RAM and a set of SFRs that are

bit addressable. The instruction set includes the whole menu of

bit operations such as move, set, clear, toggle, OR, and AND

instructions and the conditional jump instructions. Table 4-4 lists

the available Boolean instructions.

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Table 4-3. Data Transfer Instructions

Mnemonic

Description

Bytes

1

Cycles

MOV A,Rn

Move register to accumulator

Move direct byte to accumulator

1

2

1

3

2

3

2

3

2

3

5

4

3

5

4

3

2

3

MOV A,Direct

MOV A,@Ri

2

Move indirect RAM to accumulator

Move immediate data to accumulator

Move accumulator to register

1

MOV A,#data

2

MOV Rn,A

1

MOV Rn,Direct

MOV Rn, #data

MOV Direct, A

MOV Direct, Rn

MOV Direct, Direct

MOV Direct, @Ri

MOV Direct, #data

MOV @Ri, A

Move direct byte to register

2

Move immediate data to register

2

Move accumulator to direct byte

2

Move register to direct byte

2

Move direct byte to direct byte

3

Move indirect RAM to direct byte

2

Move immediate data to direct byte

Move accumulator to indirect RAM

Move direct byte to indirect RAM

3

1

MOV @Ri, Direct

MOV @Ri, #data

MOV DPTR, #data16

MOVC A, @A+DPTR

MOVC A, @A + PC

MOVX A,@Ri

2

Move immediate data to indirect RAM

Load data pointer with 16 bit constant

Move code byte relative to DPTR to accumulator

Move code byte relative to PC to accumulator

Move external RAM (8-bit) to accumulator

Move external RAM (16-bit) to accumulator

Move accumulator to external RAM (8-bit)

Move accumulator to external RAM (16-bit)

Push direct byte onto stack

2

3

1

MOVX A, @DPTR

MOVX @Ri, A

1

MOVX @DPTR, A

PUSH Direct

1

2

POP Direct

Pop direct byte from stack

2

XCH A, Rn

Exchange register with accumulator

Exchange direct byte with accumulator

Exchange indirect RAM with accumulator

Exchange low order indirect digit RAM with accumulator

1

XCH A, Direct

XCH A, @Ri

2

1

XCHD A, @Ri

1

Table 4-4. Boolean Instructions

Mnemonic

Description

Bytes

Cycles

CLR

C

Clear carry

1

2

1

2

1

2

1

3

1

3

1

3

2

CLR bit

SETB C

SETB bit

Clear direct bit

Set carry

Set direct bit

CPL

C

Complement carry

Complement direct bit

AND direct bit to carry

CPL bit

ANL C, bit

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Table 4-4. Boolean Instructions (continued)

Mnemonic

Description

Bytes

Cycles

ANL C, /bit

ORL C, bit

ORL C, /bit

MOV C, bit

MOV bit, C

AND complement of direct bit to carry

OR direct bit to carry

2

3

2

3

5

OR complement of direct bit to carry

Move direct bit to carry

Move carry to direct bit

JC

rel

Jump if carry is set

JNC rel

Jump if no carry is set

JB

bit, rel

Jump if direct bit is set

JNB bit, rel

JBC bit, rel

Jump if direct bit is not set

Jump if direct bit is set and clear bit

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4.3.1.5 Program Branching Instructions

The 8051 supports a set of conditional and unconditional jump instructions that help to modify the program execution flow. Table 4-5

shows the list of jump instructions.

Table 4-5. Jump Instructions

Mnemonic

ACALL addr11

Description

Bytes

Cycles

Absolute subroutine call

Long subroutine call

Return from subroutine

Return from interrupt

Absolute jump

2

3

1

2

3

2

1

2

3

2

3

1

4

3

4

3

5

4

5

4

5

4

5

1

LCALL addr16

RET

RETI

AJMP addr11

LJMP addr16

SJMP rel

Long jump

Short jump (relative address)

JMP @A + DPTR

JZ rel

Jump indirect relative to DPTR

Jump if accumulator is zero

JNZ rel

Jump if accumulator is nonzero

CJNE A,Direct, rel

CJNE A, #data, rel

CJNE Rn, #data, rel

CJNE @Ri, #data, rel

DJNZ Rn,rel

DJNZ Direct, rel

NOP

Compare direct byte to accumulator and jump if not equal

Compare immediate data to accumulator and jump if not equal

Compare immediate data to register and jump if not equal

Compare immediate data to indirect RAM and jump if not equal

Decrement register and jump if not zero

Decrement direct byte and jump if not zero

No operation

4.4.1 PHUB Features

4.4 DMA and PHUB

The PHUB and the DMA controller are responsible for data

transfer between the CPU and peripherals, and also data

transfers between peripherals. The PHUB and DMA also control

device configuration during boot. The PHUB consists of:

 CPU and DMA controller are both bus masters to the PHUB

 Eight multi-layer AHB bus parallel access paths (spokes) for

peripheral access

 Simultaneous CPU and DMA access to peripherals located on

different spokes

 A central hub that includes the DMA controller, arbiter, and

router

 Simultaneous DMA source and destination burst transactions

on different spokes

 Multiple spokes that radiate outward from the hub to most

peripherals

 Supports 8-, 16-, 24-, and 32-bit addressing and data

There are two PHUB masters: the CPU and the DMA controller.

Both masters may initiate transactions on the bus. The DMA

channels can handle peripheral communication without CPU

intervention. The arbiter in the central hub determines which

DMA channel is the highest priority if there are multiple requests.

Table 4-6. PHUB Spokes and Peripherals

PHUB Spokes

Peripherals

0

1

2

SRAM

IOs, PICU, EMIF

PHUB local configuration, Power manager,

Clocks, IC, SWV, EEPROM, Flash

programming interface

3

4

5

6

7

Analog interface and trim, Decimator

USB, CAN, I²C, Timers, Counters, and PWMs

DFB

UDBs group 1

UDBs group 2

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4.4.2 DMA Features

Priority levels 2 to 7 are guaranteed the minimum bus bandwidth

shown in Table 4-7 after the CPU and DMA priority levels 0 and

1 have satisfied their requirements.

 24 DMA channels

 Each channel has one or more transaction descriptors (TD) to

Table 4-7. Priority Levels

configure channel behavior. Up to 128 total TDs can be defined

Priority Level

% Bus Bandwidth

 TDs can be dynamically updated

 Eight levels of priority per channel

0

1

2

3

4

5

6

7

100.0

50.0

25.0

12.5

6.2

 Anydigitallyroutablesignal, theCPU, oranotherDMAchannel,

can trigger a transaction

 Each channel can generate up to two interrupts per transfer

 Transactions can be stalled or canceled

3.1

 Supports transaction size of infinite or 1 to 64 KB

 TDs may be nested and/or chained for complex transactions

1.5

4.4.3 Priority Levels

When the fairness algorithm is disabled, DMA access is granted

based solely on the priority level; no bus bandwidth guarantees

are made.

The CPU always has higher priority than the DMA controller

when their accesses require the same bus resources. Due to the

system architecture, the CPU can never starve the DMA. DMA

channels of higher priority (lower priority number) may interrupt

current DMA transfers. In the case of an interrupt, the current

transfer is allowed to complete its current transaction. To ensure

latency limits when multiple DMA accesses are requested

simultaneously, a fairness algorithm guarantees an interleaved

minimum percentage of bus bandwidth for priority levels 2

through 7. Priority levels 0 and 1 do not take part in the fairness

algorithm and may use 100 percent of the bus bandwidth. If a tie

occurs on two DMA requests of the same priority level, a simple

round robin method is used to evenly share the allocated

bandwidth. The round robin allocation can be disabled for each

DMA channel, allowing it to always be at the head of the line.

4.4.4 Transaction Modes Supported

The flexible configuration of each DMA channel and the ability to

chain multiple channels allow the creation of both simple and

complex use cases. General use cases include, but are not

limited to:

4.4.4.1 Simple DMA

In a simple DMA case, a single TD transfers data between a

source and sink (peripherals or memory location). The basic

timing diagrams of DMA read and write cycles are shown in

Figure 4-1. For more description on other transfer modes, refer

to the Technical Reference Manual.

Figure 4-1. DMA Timing Diagram

ADDRESS Phase

DATA Phase

ADDRESS Phase

DATA Phase

CLK

ADDR 16/32

WRITE

ADDR 16/32

A

B

A

B

WRITE

DATA

DATA (A)

DATA

READY

Basic DMA Read Transfer without wait states

Basic DMA Write Transfer without wait states

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4.4.4.2 Auto Repeat DMA

phase TD(s) finish, a status phase TD can be invoked that reads

some memory mapped status information from the peripheral

and copies it to a location in system memory specified by the

CPU for later inspection. Multiple sets of configuration, data, and

status phase ‘subchains’ can be strung together to create larger

chains that transmit multiple packets in this way. A similar

concept exists in the opposite direction to receive the packets.

Auto repeat DMA is typically used when a static pattern is

repetitively read from system memory and written to a peripheral.

This is done with a single TD that chains to itself.

4.4.4.3 Ping Pong DMA

A ping pong DMA case uses double buffering to allow one buffer

to be filled by one client while another client is consuming the

data previously received in the other buffer. In its simplest form,

this is done by chaining two TDs together so that each TD calls

the opposite TD when complete.

4.4.4.7 Nested DMA

One TD may modify another TD, as the TD configuration space

is memory mapped similar to any other peripheral. For example,

a first TD loads a second TD’s configuration and then calls the

second TD. The second TD moves data as required by the

application. When complete, the second TD calls the first TD,

which again updates the second TD’s configuration. This

process repeats as often as necessary.

4.4.4.4 Circular DMA

Circular DMA is similar to ping pong DMA except it contains more

than two buffers. In this case there are multiple TDs; after the last

TD is complete it chains back to the first TD.

4.5 Interrupt Controller

4.4.4.5 Scatter Gather DMA

The interrupt controller provides a mechanism for hardware

resources to change program execution to a new address,

independent of the current task being executed by the main

code. The interrupt controller provides enhanced features not

found on original 8051 interrupt controllers:

In the case of scatter gather DMA, there are multiple

noncontiguous sources or destinations that are required to

effectively carry out an overall DMA transaction. For example, a

packet may need to be transmitted off of the device and the

packet elements, including the header, payload, and trailer, exist

in various noncontiguous locations in memory. Scatter gather

DMA allows the segments to be concatenated together by using

multiple TDs in a chain. The chain gathers the data from the

multiple locations. A similar concept applies for the reception of

data onto the device. Certain parts of the received data may need

to be scattered to various locations in memory for software

processing convenience. Each TD in the chain specifies the

location for each discrete element in the chain.

 Thirty-two interrupt vectors

 Jumps directly to ISR anywhere in code space with dynamic

vector addresses

 Multiple sources for each vector

 Flexible interrupt to vector matching

 Each interrupt vector is independently enabled or disabled

4.4.4.6 Packet Queuing DMA

 Each interrupt can be dynamically assigned one of eight

priorities

Packet queuing DMA is similar to scatter gather DMA but

specifically refers to packet protocols. With these protocols,

there may be separate configuration, data, and status phases

associated with sending or receiving a packet.

 Eight level nestable interrupts

 Multiple I/O interrupt vectors

 Software can send interrupts

 Software can clear pending interrupts

For instance, to transmit a packet, a memory mapped

configuration register can be written inside a peripheral,

specifying the overall length of the ensuing data phase. The CPU

can set up this configuration information anywhere in system

memory and copy it with a simple TD to the peripheral. After the

configuration phase, a data phase TD (or a series of data phase

TDs) can begin (potentially using scatter gather). When the data

Figure 4-2 on page 18 represents typical flow of events when an

interrupt triggered. Figure 4-3 on page 19 shows the interrupt

structure and priority polling.

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Figure 4-2. Interrupt Processing Timing Diagram

1

2

3

4

5

6

7

8

9

10

11

S

Arrival of new Interrupt

S

Pend bit is set on next clock active edge

Interrupt is posted to ascertain the priority

POST and PEND bits cleared after IRQ is sleared

S

IRQ cleared after receiving IRA

Interrupt request sent to core for processing

S

The active interrupt

NA

0x0010

number is posted to core

S

The active interrupt ISR

address is posted to core

NA

S

Int. State

Clear

Interrupt generation and posting to CPU

CPU Response

Completing current instruction and branching to vector address

Complete ISR and return

Notes

 1: Interrupt triggered asynchronous to the clock

 2: The PEND bit is set on next active clock edge to indicate the interrupt arrival

 3: POST bit is set following the PEND bit

 4: Interrupt request and the interrupt number sent to CPU core after evaluation priority (Takes 3 clocks)

 5: ISR address is posted to CPU core for branching

 6: CPU acknowledges the interrupt request

 7: ISR address is read by CPU for branching

 8, 9: PEND and POST bits are cleared respectively after receiving the IRA from core

 10: IRA bit is cleared after completing the current instruction and starting the instruction execution from ISR location (Takes 7 cycles)

 11: IRC is set to indicate the completion of ISR, Active int. status is restored with previous status

The total interrupt latency (ISR execution)

= POST + PEND + IRQ + IRA + Completing current instruction and branching

= 1+1+1+2+7 cycles

= 12 cycles

Document Number: 001-57330 Rev. *G

Page 18 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

Table 4-8. Interrupt Vector Table

Fixed Function

#

DMA

UDB

udb_intr[0]

0

1

2

3

4

5

6

7

8

9

LVD

phub_termout0[0]

phub_termout0[1]

phub_termout0[2]

phub_termout0[3]

phub_termout0[4]

phub_termout0[5]

phub_termout0[6]

phub_termout0[7]

phub_termout0[8]

phub_termout0[9]

phub_termout0[10]

phub_termout0[11]

phub_termout0[12]

phub_termout0[13]

phub_termout0[14]

phub_termout0[15]

phub_termout1[0]

phub_termout1[1]

phub_termout1[2]

phub_termout1[3]

phub_termout1[4]

phub_termout1[5]

phub_termout1[6]

phub_termout1[7]

phub_termout1[8]

phub_termout1[9]

phub_termout1[10]

phub_termout1[11]

phub_termout1[12]

phub_termout1[13]

phub_termout1[14]

phub_termout1[15]

Cache/ECC

Reserved

udb_intr[1]

udb_intr[2]

udb_intr[3]

udb_intr[4]

udb_intr[5]

udb_intr[6]

udb_intr[7]

udb_intr[8]

udb_intr[9]

udb_intr[10]

udb_intr[11]

udb_intr[12]

udb_intr[13]

udb_intr[14]

udb_intr[15]

udb_intr[16]

udb_intr[17]

udb_intr[18]

udb_intr[19]

udb_intr[20]

udb_intr[21]

udb_intr[22]

udb_intr[23]

udb_intr[24]

udb_intr[25]

udb_intr[26]

udb_intr[27]

udb_intr[28]

udb_intr[29]

udb_intr[30]

udb_intr[31]

Sleep (Pwr Mgr)

PICU[0]

PICU[1]

PICU[2]

PICU[3]

PICU[4]

PICU[5]

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

PICU[6]

PICU[12]

PICU[15]

Comparators Combined

Switched Caps Combined

2

I C

CAN

Timer/Counter0

Timer/Counter1

Timer/Counter2

Timer/Counter3

USB SOF Int

USB Arb Int

USB Bus Int

USB Endpoint[0]

USB Endpoint Data

Reserved

LCD

DFB Int

Decimator Int

PHUB Error Int

EEPROM Fault Int

Document Number: 001-57330 Rev. *G

Page 20 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

protecting your application from external access (see the

“Device Security” section on page 63). For more information

about how to take full advantage of the security features in

PSoC, see the PSoC 3 TRM.

5. Memory

5.1 Static RAM

CY8C36 SRAM is used for temporary data storage. Up to 8 KB

of SRAM is provided and can be accessed by the 8051 or the

DMA controller. See Memory Map on page 24. Simultaneous

access of SRAM by the 8051 and the DMA controller is possible

if different 4-KB blocks are accessed.

Table 5-1. Flash Protection

Protection

Setting

Allowed

Not Allowed

Unprotected

External read and write

+ internal read and write

–

5.2 Flash Program Memory

Factory

Upgrade

External write + internal External read

read and write

Flash memory in PSoC devices provides nonvolatile storage for

user firmware, user configuration data, bulk data storage, and

optional ECC data. The main flash memory area contains up to

64 KB of user program space.

Field Upgrade Internal read and write External read and

write

Up to an additional 8 KB of flash space is available for ECC. If

ECC is not used this space can store device configuration data

and bulk user data. User code may not be run out of the ECC

flash memory section. ECC can correct one bit error and detect

two bit errors per 8 bytes of firmware memory; an interrupt can

be generated when an error is detected.

Full Protection Internal read

External read and

write + internal write

Disclaimer

Note the following details of the flash code protection features on

Cypress devices.

The CPU reads instructions located in flash through a cache

controller. This improves instruction execution rate and reduces

system power consumption by requiring less frequent flash

access. The cache has 8 lines at 64 bytes per line for a total of

512 bytes. It is fully associative, automatically controls flash

power, and can be enabled or disabled. If ECC is enabled, the

cache controller also performs error checking and correction,

and interrupt generation.

Cypress products meet the specifications contained in their

particular Cypress data sheets. Cypress believes that its family

of products is one of the most secure families of its kind on the

market today, regardless of how they are used. There may be

methods, unknown to Cypress, that can breach the code

protection features. Any of these methods, to our knowledge,

would be dishonest and possibly illegal. Neither Cypress nor any

other semiconductor manufacturer can guarantee the security of

their code. Code protection does not mean that we are

guaranteeing the product as ‘unbreakable’. Cypress is willing to

work with the customer who is concerned about the integrity of

their code. Code protection is constantly evolving. We at Cypress

are committed to continuously improving the code protection

features of our products.

Flash programming is performed through a special interface and

preempts code execution out of flash. The flash programming

interface performs flash erasing, programming and setting code

protection levels. Flash in-system serial programming (ISSP),

typically used for production programming, is possible through

both the SWD and JTAG interfaces. In-system programming,

typically used for bootloaders, is also possible using serial

interfaces such as I²C, USB, UART, and SPI, or any

communications protocol.

5.4 EEPROM

PSoC EEPROM memory is a byte-addressable nonvolatile

memory. The CY8C36 has up to 2 KB of EEPROM memory to

store user data. Reads from EEPROM are random access at the

byte level. Reads are done directly; writes are done by sending

write commands to an EEPROM programming interface. CPU

code execution can continue from flash during EEPROM writes.

EEPROM is erasable and writeable at the row level. The

EEPROM is divided into 128 rows of 16 bytes each. The CPU

can not execute out of EEPROM. There is no ECC hardware

associated with EEPROM. If ECC is required it must be handled

in firmware.

5.3 Flash Security

All PSoC devices include a flexible flash-protection model that

prevents access and visibility to on-chip flash memory. This

prevents duplication or reverse engineering of proprietary code.

Flash memory is organized in blocks, where each block contains

256 bytes of program or data and 32 bytes of ECC or

configuration data. A total of up to 256 blocks is provided on

64-KB flash devices.

The device offers the ability to assign one of four protection

levels to each row of flash. Table 5-1 lists the protection modes

available. Flash protection levels can only be changed by

performing a complete flash erase. The Full Protection and Field

Upgrade settings disable external access (through a debugging

tool such as PSoC Creator, for example). If your application

requires code update through a bootloader, then use the Field

Upgrade setting. Use the Unprotected setting only when no

security is needed in your application. The PSoC device also

offers an advanced security feature called Device Security which

permanently disables all test, programming, and debug ports,

It can take as much as 20 milliseconds to write to EEPROM or

flash. During this time the device should not be reset, or

unexpected changes may be made to portions of EEPROM or

flash. Reset sources (see Section 6.3.1) include XRES pin,

software reset, and watchdog; care should be taken to make

sure that these are not inadvertently activated. Also, the low

voltage detect circuits should be configured to generate an

interrupt instead of a reset.

Document Number: 001-57330 Rev. *G

Page 21 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

5.5 Nonvolatile Latches (NVLs)

PSoC has a 4-byte array of nonvolatile latches (NVLs) that are used to configure the device at reset. The NVL register map is shown

in Table 5-2.

Table 5-2. Device Configuration NVL Register Map

Register Address

7

6

5

4

3

2

1

0

0x00

0x01

0x02

0x03

PRT3RDM[1:0]

PRT12RDM[1:0]

PRT2RDM[1:0]

PRT6RDM[1:0]

PRT1RDM[1:0]

PRT5RDM[1:0]

PRT0RDM[1:0]

PRT4RDM[1:0]

PRT15RDM[1:0]

XRESMEN

DBGEN

DIG_PHS_DLY[3:0]

ECCEN

DPS[1:0]

CFGSPEED

The details for individual fields and their factory default settings are shown in Table 5-3:.

Table 5-3. Fields and Factory Default Settings

Field

Description

Settings

PRTxRDM[1:0]

Controls reset drive mode of the corresponding IO port. 00b (default) - high impedance analog

See “Reset Configuration” on page 39. All pins of the port 01b - high impedance digital

are set to the same mode.

10b - resistive pull up

11b - resistive pull down

XRESMEN

Controls whether pin P1[2] is used as a GPIO or as an

external reset. See “Pin Descriptions” on page 9, XRES 1 (default for 48-pin parts) - external reset

0 (default for 68-pin and 100-pin parts) - GPIO

description.

DBGEN

Debug Enable allows access to the debug system, for

third-party programmers.

0 - access disabled

1 (default) - access enabled

DPS{1:0]

Controls the usage of various P1 pins as a debug port. 00b - 5-wire JTAG

See “Programming, Debug Interfaces, Resources” on

page 60.

01b (default) - 4-wire JTAG

10b - SWD

11b - debug ports disabled

ECCEN

Controls whether ECC flash is used for ECC or for general 0 - ECC disabled

configuration and data storage. See “Flash Program

1 (default) - ECC enabled

See the TRM for details.

Memory” on page 21.

DIG_PHS_DLY[3:0]

Selects the digital clock phase delay.

Although PSoC Creator provides support for modifying the device configuration NVLs, the number of NVL erase / write cycles is limited

– see Nonvolatile Latches (NVL) on page 120.

Document Number: 001-57330 Rev. *G

Page 22 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

5.6 External Memory Interface

CY8C36 provides an EMIF for connecting to external memory

devices. The connection allows read and write accesses to

external memories. The EMIF operates in conjunction with

UDBs, I/O ports, and other hardware to generate external

memory address and control signals. At 33 MHz, each memory

access cycle takes four bus clock cycles. Figure 5-1 is the EMIF

block diagram. The EMIF supports synchronous and

asynchronous memories. The CY8C36 supports only one type

of external memory device at a time. External memory can be

accessed through the 8051 xdata space; up to 24 address bits

can be used. See “xdata Space” section on page 25. The

memory can be 8 or 16 bits wide.

Figure 5-1. EMIF Block Diagram

External_MEM_ ADDR[23:0]

IO

Address Signals

PORTs

Data,

Address,

and Control

Signals

External_MEM_ DATA[15:0]

IO

Data Signals

IO IF

PORTs

Control Signals

Control

IO

PORTs

PHUB

Data,

Address,

and Control

Signals

DSI Dynamic Output

Control

UDB

DSI to Port

Other

EM Control

Signals

Control

Signals

Data,

Address,

and Control

Signals

EMIF

Document Number: 001-57330 Rev. *G

Page 23 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

Figure 5-2. 8051 Internal Data Space

5.7 Memory Map

The CY8C36 8051 memory map is very similar to the MCS-51

memory map.

0x00

0x1F

0x20

0x2F

0x30

4 Banks, R0-R7 Each

Bit Addressable Area

5.7.1 Code Space

The CY8C36 8051 code space is 64 KB. Only main flash exists

in this space. See the Flash Program Memory on page 21.

Lower Core RAM Shared with Stack Space

(direct and indirect addressing)

5.7.2 Internal Data Space

0x7F

0x80

The CY8C36 8051 internal data space is 384 bytes, compressed

within a 256-byte space. This space consists of 256 bytes of

RAM (in addition to the SRAM mentioned in Static RAM on page

21) and a 128-byte space for special function registers (SFR).

See Figure 5-2. The lowest 32 bytes are used for 4 banks of

registers R0-R7. The next 16 bytes are bit-addressable.

SFR

Upper Core RAM Shared

with Stack Space

Special Function Registers

(direct addressing)

(indirect addressing)

0xFF

In addition to the register or bit address modes used with the

lower 48 bytes, the lower 128 bytes can be accessed with direct

or indirect addressing. With direct addressing mode, the upper

128 bytes map to the SFRs. With indirect addressing mode, the

upper 128 bytes map to RAM. Stack operations use indirect

addressing; the 8051 stack space is 256 bytes. See the

“Addressing Modes” section on page 10.

5.7.3 SFRs

The SFR space provides access to frequently accessed registers. The memory map for the SFR memory space is shown in Table 5-4.

Table 5-4. SFR Map

Address

0×F8 SFRPRT15DR

0×F0

0/8

1/9

SFRPRT15PS

–

2/A

SFRPRT15SEL

SFRPRT12SEL

MXAX

3/B

4/C

5/D

6/E

7/F

–

B

0×E8 SFRPRT12DR

0×E0 ACC

SFRPRT12PS

–

0×D8 SFRPRT6DR

0×D0 PSW

SFRPRT6PS

–

SFRPRT6SEL

–

0×C8 SFRPRT5DR

0×C0 SFRPRT4DR

0×B8

SFRPRT5PS

SFRPRT4PS

SFRPRT5SEL

SFRPRT4SEL

0×B0 SFRPRT3DR

0×A8 IE

SFRPRT3PS

SFRPRT3SEL

–

0×A0 P2AX

–

SFRPRT1SEL

SFRPRT2SEL

–

0×98 SFRPRT2DR

0×90 SFRPRT1DR

SFRPRT2PS

SFRPRT1PS

SFRPRT0PS

SP

DPX0

–

DPX1

–

0×88

–

SFRPRT0SEL

DPL0

0×80 SFRPRT0DR

DPH0

DPL1

DPH1

DPS

The CY8C36 family provides the standard set of registers found on industry standard 8051 devices. In addition, the CY8C36 devices

add SFRs to provide direct access to the I/O ports on the device. The following sections describe the SFRs added to the CY8C36

family.

Document Number: 001-57330 Rev. *G

Page 24 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

5.7.4 XData Space Access SFRs

5.7.5.1 xdata Space

The 8051 core features dual DPTR registers for faster data

transfer operations. The data pointer select SFR, DPS, selects

which data pointer register, DPTR0 or DPTR1, is used for the

following instructions:

The 8051 xdata space is 24-bit, or 16 MB in size. The majority of

this space is not ‘external’—it is used by on-chip components.

See Table 5-5. External, that is, off-chip, memory can be

accessed using the EMIF. See External Memory Interface on

page 23.

 MOVX @DPTR, A

 MOVX A, @DPTR

 MOVC A, @A+DPTR

 JMP @A+DPTR

 INC DPTR

Table 5-5. XDATA Data Address Map

Address Range

0×00 0000 – 0×00 1FFF

0×00 4000 – 0×00 42FF

0×00 4300 – 0×00 43FF

0×00 4400 – 0×00 44FF

0×00 4500 – 0×00 45FF

0×00 4700 – 0×00 47FF

0×00 4800 - 0×00 48FF

0×00 4900 – 0×00 49FF

0×00 4E00 – 0×00 4EFF

0×00 4F00 – 0×00 4FFF

0×00 5000 – 0×00 51FF

0×00 5400 – 0×00 54FF

0×00 5800 – 0×00 5FFF

0×00 6000 – 0×00 60FF

0×00 6400 – 0×00 6FFF

0×00 7000 – 0×00 7FFF

0×00 8000 – 0×00 8FFF

0×00 A000 – 0×00 A400

0×00 C000 – 0×00 C800

0×01 0000 – 0×01 FFFF

Purpose

SRAM

Clocking, PLLs, and oscillators

Power management

Interrupt controller

Ports interrupt control

Flash programming interface

Cache controller

 MOV DPTR, #data16

The extended data pointer SFRs, DPX0, DPX1, MXAX, and

P2AX, hold the most significant parts of memory addresses

during access to the xdata space. These SFRs are used only

with the MOVX instructions.

During a MOVX instruction using the DPTR0/DPTR1 register,

the most significant byte of the address is always equal to the

contents of DPX0/DPX1.

I²C controller

Decimator

Fixed timer/counter/PWMs

I/O ports control

During a MOVX instruction using the R0 or R1 register, the most

significant byte of the address is always equal to the contents of

MXAX, and the next most significant byte is always equal to the

contents of P2AX.

EMIF control registers

Analog subsystem interface

USB controller

5.7.5 I/O Port SFRs

The I/O ports provide digital input sensing, output drive, pin

interrupts, connectivity for analog inputs and outputs, LCD, and

access to peripherals through the DSI. Full information on I/O

ports is found in I/O System and Routing on page 33.

UDB Working Registers

PHUB configuration

EEPROM

I/O ports are linked to the CPU through the PHUB and are also

available in the SFRs. Using the SFRs allows faster access to a

limited set of I/O port registers, while using the PHUB allows boot

configuration and access to all I/O port registers.

CAN

DFB

Digital Interconnect

configuration

Each SFR supported I/O port provides three SFRs:

0×05 0220 – 0×05 02F0

0×08 0000 – 0×08 1FFF

0×80 0000 – 0×FF FFFF

Debug controller

 SFRPRTxDR sets the output data state of the port (where × is

port number and includes ports 0–6, 12 and 15).

Flash ECC bytes

External memory interface

 The SFRPRTxSEL selects whether the PHUB PRTxDR

register or the SFRPRTxDR controls each pin’s output buffer

within the port. If a SFRPRTxSEL[y] bit is high, the

corresponding SFRPRTxDR[y] bit sets the output state for that

pin. If a SFRPRTxSEL[y] bit is low, the corresponding

PRTxDR[y] bit sets the output state of the pin (where y varies

from 0 to 7).

 The SFRPRTxPS is a read only register that contains pin state

values of the port pins.

Document Number: 001-57330 Rev. *G

Page 25 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

Key features of the clocking system include:

6. System Integration

 Seven general purpose clock sources

 3- to 62-MHz IMO, ±1% at 3 MHz

 4- to 25-MHz external crystal oscillator (MHzECO)

 Clock doubler provides a doubled clock frequency output for

the USB block, see USB Clock Domain on page 28.

 DSI signal from an external I/O pin or other logic

 24- to 67-MHz fractional PLL sourced from IMO, MHzECO,

or DSI

6.1 Clocking System

The clocking system generates, divides, and distributes clocks

throughout the PSoC system. For the majority of systems, no

external crystal is required. The IMO and PLL together can

generate up to a 66 MHz clock, accurate to ±1 percent over

voltage and temperature. Additional internal and external clock

sources allow each design to optimize accuracy, power, and

cost. Any of the clock sources can be used to generate other

clock frequencies in the 16-bit clock dividers and UDBs for

anything the user wants, for example a UART baud rate

generator.

 1-kHz, 33-kHz, 100-kHz ILO for WDT and sleep timer

 32.768-kHz external crystal oscillator (kHzECO) for RTC

 IMO has a USB mode that auto locks to the USB bus clock

requiring no external crystal for USB (USB equipped parts only)

Clock generation and distribution is automatically configured

through the PSoC Creator IDE graphical interface. This is based

on the complete system’s requirements. It greatly speeds the

design process. PSoC Creator allows you to build clocking

systems with minimal input. You can specify desired clock

frequencies and accuracies, and the software locates or builds a

clock that meets the required specifications. This is possible

because of the programmability inherent in PSoC.

 Independently sourced clock in all clock dividers

 Eight 16-bit clock dividers for the digital system

 Four 16-bit clock dividers for the analog system

 Dedicated 16-bit divider for the bus clock

 Dedicated 4-bit divider for the CPU clock

 Automatic clock configuration in PSoC Creator

Table 6-1. Oscillator Summary

Source

Fmin

Tolerance at Fmin

Fmax Tolerance at Fmax

Startup Time

IMO

3 MHz ±1% over voltage and temperature 62 MHz ±7%

13 µs max

MHzECO 4 MHz Crystal dependent

25 MHz Crystal dependent

66 MHz Input dependent

67 MHz Input dependent

48 MHz Input dependent

100 kHz –55%, +100%

32 kHz Crystal dependent

5 ms typ, max is crystal dependent

Input dependent

DSI

PLL

0 MHz Input dependent

24 MHz Input dependent

48 MHz Input dependent

1 kHz –50%, +100%

250 µs max

Doubler

ILO

1 µs max

15 ms max in lowest power mode

500 ms typ, max is crystal dependent

kHzECO

32 kHz Crystal dependent

Document Number: 001-57330 Rev. *G

Page 26 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

Figure 6-1. Clocking Subsystem

External IO

or DSI

0-66 MHz

3-62 MHz

IMO

4-25 MHz

ECO

1,33,100 kHz

ILO

32 kHz ECO

CPU

Clock

CPU Clock Divider

4 bit

48 MHz

Doubler for

USB

24-67 MHz

PLL

Master

Mux

Bus

Clock

Bus Clock Divider

16 bit

s

k

e

w

Digital Clock

Divider 16 bit

Digital Clock

Divider 16 bit

Analog Clock

Divider 16 bit

s

k

e

w

Digital Clock

Divider 16 bit

Digital Clock

Divider 16 bit

Analog Clock

Divider 16 bit

7

s

k

e

w

7

Analog Clock

Divider 16 bit

Digital Clock

Divider 16 bit

Digital Clock

Divider 16 bit

s

k

e

w

Analog Clock

Divider 16 bit

Digital Clock

Divider 16 bit

Digital Clock

Divider 16 bit

6.1.1 Internal Oscillators

used until lock is complete and signaled with a lock bit. The lock

signal can be routed through the DSI to generate an interrupt.

Disable the PLL before entering low-power modes.

6.1.1.1 Internal Main Oscillator

In most designs the IMO is the only clock source required, due

to its ±1-percent accuracy. The IMO operates with no external

components and outputs a stable clock. A factory trim for each

frequency range is stored in the device. With the factory trim,

tolerance varies from ±1 percent at 3 MHz, up to ±7 percent at

62 MHz. The IMO, in conjunction with the PLL, allows generation

of other clocks up to the device's maximum frequency (see PLL).

The IMO provides clock outputs at 3, 6, 12, 24, 48, and 62 MHz.

6.1.1.4 Internal Low-Speed Oscillator

The ILO provides clock frequencies for low-power consumption,

including the watchdog timer, and sleep timer. The ILO

generates up to three different clocks: 1 kHz, 33 kHz, and

100 kHz. The 1-kHz clock (CLK1K) is typically used for a

background ‘heartbeat’ timer. This clock inherently lends itself to

low-power supervisory operations such as the watchdog timer

and long sleep intervals using the central timewheel (CTW).

6.1.1.2 Clock Doubler

The central timewheel is a 1-kHz, free running, 13-bit counter

clocked by the ILO. The central timewheel is always enabled,

except in hibernate mode and when the CPU is stopped during

debug on chip mode. It can be used to generate periodic

interrupts for timing purposes or to wake the system from a

low-power mode. Firmware can reset the central timewheel.

Systems that require accurate timing should use the RTC

capability instead of the central timewheel.

The clock doubler outputs a clock at twice the frequency of the

input clock. The doubler works at input frequency of 24 MHz,

providing 48 MHz for the USB. It can be configured to use a clock

from the IMO, MHzECO, or the DSI (external pin).

6.1.1.3 PLL

The PLL allows low-frequency, high-accuracy clocks to be

multiplied to higher frequencies. This is a trade off between

higher clock frequency and accuracy and, higher power

consumption and increased startup time.

The 100-kHz clock (CLK100K) can be used as a low power

master clock. It can also generate time intervals using the fast

timewheel.

The PLL block provides a mechanism for generating clock

frequencies based upon a variety of input sources. The PLL

outputs clock frequencies in the range of 24 to 67 MHz. Its input

and feedback dividers supply 4032 discrete ratios to create

almost any desired clock frequency. The accuracy of the PLL

output depends on the accuracy of the PLL input source. The

most common PLL use is to multiply the IMO clock at 3 MHz,

where it is most accurate, to generate the other clocks up to the

device’s maximum frequency.

The fast timewheel is a 5-bit counter, clocked by the 100-kHz

clock. It features programmable settings and automatically

resets when the terminal count is reached. An optional interrupt

can be generated each time the terminal count is reached. This

enables flexible, periodic interrupts of the CPU at a higher rate

than is allowed using the central timewheel.

The 33-kHz clock (CLK33K) comes from a divide-by-3 operation

on CLK100K. This output can be used as a reduced accuracy

version of the 32.768-kHz ECO clock with no need for a crystal.

The PLL achieves phase lock within 250 µs (verified by bit

setting). It can be configured to use a clock from the IMO,

MHzECO or DSI (external pin). The PLL clock source can be

Document Number: 001-57330 Rev. *G

Page 27 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

6.1.2 External Oscillators

capacitance, should equal the crystal CL value. For more

information, refer to application note AN54439: PSoC 3 and

PSoC 5 External Oscillators. See also pin capacitance

specifications in the “GPIO” section on page 74.

6.1.2.1 MHz External Crystal Oscillator

The MHzECO provides high frequency, high precision clocking

using an external crystal (see Figure 6-2). It supports a wide

variety of crystal types, in the range of 4 to 25 MHz. When used

in conjunction with the PLL, it can generate other clocks up to the

device's maximum frequency (see PLL). The GPIO pins

connecting to the external crystal and capacitors are fixed.

MHzECO accuracy depends on the crystal chosen.

6.1.2.3 Digital System Interconnect

The DSI provides routing for clocks taken from external clock

oscillators connected to I/O. The oscillators can also be

generated within the device in the digital system and UDBs.

While the primary DSI clock input provides access to all clocking

resources, up to eight other DSI clocks (internally or externally

generated) may be routed directly to the eight digital clock

dividers. This is only possible if there are multiple precision clock

sources.

Figure 6-2. MHzECO Block Diagram

XCLK_MHZ

4 - 25 MHz

Crystal Osc

6.1.3 Clock Distribution

All seven clock sources are inputs to the central clock distribution

system. The distribution system is designed to create multiple

high precision clocks. These clocks are customized for the

design’s requirements and eliminate the common problems

found with limited resolution prescalers attached to peripherals.

The clock distribution system generates several types of clock

trees.

Xo

Xi

(Pin P15[0])

(Pin P15[1])

4 –25 MHz

crystal

External

Components

 The master clock is used to select and supply the fastest clock

in the system for general clock requirements and clock

synchronization of the PSoC device.

Capacitors

 Bus clock 16-bit divider uses the master clock to generate the

bus clock used for data transfers. Bus clock is the source clock

for the CPU clock divider.

6.1.2.2 32.768-kHz ECO

The 32.768-kHz external crystal oscillator (32kHzECO) provides

precision timing with minimal power consumption using an

external 32.768-kHz watch crystal (see Figure 6-3). The

32kHzECO also connects directly to the sleep timer and provides

the source for the RTC. The RTC uses a 1-second interrupt to

implement the RTC functionality in firmware.

 Eight fully programmable 16-bit clock dividers generate digital

system clocks for general use in the digital system, as

configured by the design’s requirements. Digital system clocks

can generate custom clocks derived from any of the seven

clock sources for any purpose. Examples include baud rate

generators, accurate PWM periods, and timer clocks, and

many others. If more than eight digital clock dividers are

required, theUDBsandfixedfunctiontimer/counter/PWMscan

also generate clocks.

The oscillator works in two distinct power modes. This allows

users to trade off power consumption with noise immunity from

neighboring circuits. The GPIO pins connected to the external

crystal and capacitors are fixed.

 Four16-bitclockdividersgenerateclocksfortheanalogsystem

components that require clocking, such as ADC and mixers.

The analog clock dividers include skew control to ensure that

critical analog events do not occur simultaneously with digital

switching events. This is done to reduce analog system noise.

Figure 6-3. 32kHzECO Block Diagram

XCLK32K

32 kHz

Crystal Osc

Each clock divider consists of an 8-input multiplexer, a 16-bit

clock divider (divide by 2 and higher) that generates ~50 percent

duty cycle clocks, master clock resynchronization logic, and

deglitch logic. The outputs from each digital clock tree can be

routed into the digital system interconnect and then brought back

into the clock system as an input, allowing clock chaining of up

to 32 bits.

Xo

Xi

(Pin P15[2])

(Pin P15[3])

32 kHz

crystal

External

Components

6.1.4 USB Clock Domain

Capacitors

The USB clock domain is unique in that it operates largely

asynchronously from the main clock network. The USB logic

contains a synchronous bus interface to the chip, while running

on an asynchronous clock to process USB data. The USB logic

requires a 48 MHz frequency. This frequency can be generated

from different sources, including DSI clock at 48 MHz or doubled

value of 24 MHz from internal oscillator, DSI signal, or crystal

oscillator.

It is recommended that the external 32.768-kHz watch crystal

have a load capacitance (CL) of 6 pF or 12.5 pF. Check the

crystal manufacturer's datasheet. The two external capacitors,

CL1 and CL2, are typically of the same value, and their total

capacitance, CL1CL2 / (CL1 + CL2), including pin and trace

Document Number: 001-57330 Rev. *G

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PSoC^®3: CY8C36

Automotive Family Datasheet

6.2 Power System

The power system consists of separate analog, digital, and I/O supply pins, labeled VDDA, VDDD, and VDDIOX, respectively. It also

includes two internal 1.8-V regulators that provide the digital (VCCD) and analog (VCCA) supplies for the internal core logic. The

output pins of the regulators (VCCD and VCCA) and the VDDIO pins must have capacitors connected as shown in Figure 6-4. The

two VCCD pins must be shorted together, with as short a trace as possible, and connected to a 1-µF ±10-percent X5R capacitor. The

power system also contains a sleep regulator, an I²C regulator, and a hibernate regulator.

Figure 6-4. PSoC Power System

µF

VDDD

1

VDDIO2

VDDIO0

0.1 µF

I/O Supply

VDDIO0

0.1 µF

I2C

Regulator

Sleep

Regulator

Digital

VDDA

Domain

VDDA

VCCA

Analog

Regulator

0.1 µF

Digital

Regulators

VSSD

.

µF

1

VSSA

Analog

Domain

Hibernate

Regulator

I/O Supply

0.1µF

0.1 µF

VDDD

VDDIO1

VDDIO3

Note The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended,

as shown in Figure 2-6 on page 9.

You can power the device in internally regulated mode, where the voltage applied to the V_DDxpins is as high as 5.5 V, and the internal

regulators provide the core voltages. In this mode, do not apply power to the V_CCxpins, and do not tie the V_DDxpins to the V_CCx

pins.

You can also power the device in externally regulated mode, that is, by directly powering the V_CCDand V_CCApins. In this configuration,

the V_DDDpins should be shorted to the V_CCDpins and the V_DDApin should be shorted to the V_CCApin. The allowed supply range in

this configuration is 1.71 V to 1.89 V. After power up in this configuration, the internal regulators are on by default, and should be

disabled to reduce power consumption.

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Automotive Family Datasheet

6.2.1 Power Modes

Active is the main processing mode. Its functionality is

configurable. Each power controllable subsystem is enabled or

disabled by using separate power configuration template

registers. In alternate active mode, fewer subsystems are

enabled, reducing power. In sleep mode most resources are

disabled regardless of the template settings. Sleep mode is

optimized to provide timed sleep intervals and Real Time Clock

functionality. The lowest power mode is hibernate, which retains

register and SRAM state, but no clocks, and allows wakeup only

from I/O pins. Figure 6-5 on page 31 illustrates the allowable

transitions between power modes. Sleep and hibernate modes

should not be entered until all VDDIO supplies are at valid

voltage levels.

PSoC 3 devices have four different power modes, as shown in

Table 6-2 and Table 6-3. The power modes allow a design to

easily provide required functionality and processing power while

simultaneously minimizing power consumption and maximizing

battery life in low-power and portable devices.

PSoC 3 power modes, in order of decreasing power

consumption are:

 Active

 Alternate Active

 Sleep

 Hibernate

Table 6-2. Power Modes

Power Modes

Description

EntryCondition WakeupSource Active Clocks

Regulator

Active

Primary mode of operation, all Wakeup, reset, Any interrupt

Any

All regulators available.

peripherals available

(programmable)

manual register

entry

(programmable) Digital and analog

regulators can be disabled

if external regulation used.

Alternate

Active

Similar to Active mode, and is

typically configured to have

fewer peripherals active to

reduce power. One possible

configuration is to use the UDBs

for processing, with the CPU

turned off

Manual register Any interrupt

entry

Any

All regulators available.

(programmable) Digital and analog

regulators can be disabled

if external regulation used.

Sleep

All subsystems automatically

disabled

Manual register Comparator,

entry

ILO/kHzECO

Both digital and analog

regulators buzzed.

Digital and analog

PICU, I²C, RTC,

CTW, LVD

regulators can be disabled

if external regulation used.

Hibernate

All subsystems automatically

disabled

Manual register PICU

entry

Only hibernate regulator

active.

Lowest power consuming mode

with all peripherals and internal

regulators disabled, except

hibernate regulator is enabled

Configuration and memory

contents retained

Table 6-3. Power Modes Wakeup Time and Power Consumption

Sleep

Modes

Wakeup

Time

Current

(typ)

Code

Digital

Analog

ClockSources

Available

Reset

Sources

Wakeup Sources

Execution Resources Resources

–

1.2 mA^[11]

Yes

All

–

All

Active

Alternate

Active

–

User

defined

All

<15 µs

1 µA

No

I²C

Comparator ILO/kHzECO

Comparator,

PICU, I²C, RTC,

CTW, LVD

XRES, LVD,

WDR

Sleep

Hibernate <100 µs

200 nA

No

None

PICU

XRES

Note

11. Bus clock off. Execute from cache at 6 MHz. See Table 11-2 on page 66.

Document Number: 001-57330 Rev. *G

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PSoC^®3: CY8C36

Automotive Family Datasheet

Figure 6-5. Power Mode Transitions

6.2.1.5 Wakeup Events

Wakeup events are configurable and can come from an interrupt

or device reset. A wakeup event restores the system to active

mode. Firmware enabled interrupt sources include internally

generated interrupts, power supervisor, central timewheel, and

I/O interrupts. Internal interrupt sources can come from a variety

of peripherals, such as analog comparators and UDBs. The

central timewheel provides periodic interrupts to allow the

system to wake up, poll peripherals, or perform real-time

functions. Reset event sources include the external reset I/O pin

(XRES), WDT, and precision reset (PRES).

Active

Manual

Sleep

Hibernate

Buzz

6.3 Reset

Alternate

Active

CY8C36 has multiple internal and external reset sources

available. The reset sources are:

 Power source monitoring – The analog and digital power

voltages, VDDA, VDDD, VCCA, and VCCD are monitored in

several different modes during power up, active mode, and

sleep mode (buzzing). If any of the voltages goes outside

predetermined ranges then a reset is generated. The monitors

are programmable to generate an interrupt to the processor

under certain conditions before reaching the reset thresholds.

6.2.1.1 Active Mode

Active mode is the primary operating mode of the device. When

in active mode, the active configuration template bits control

which available resources are enabled or disabled. When a

resource is disabled, the digital clocks are gated, analog bias

currents are disabled, and leakage currents are reduced as

appropriate. User firmware can dynamically control subsystem

power by setting and clearing bits in the active configuration

template. The CPU can disable itself, in which case the CPU is

automatically reenabled at the next wakeup event.

 External – The device can be reset from an external source by

pulling the reset pin (XRES) low. The XRES pin includes an

internal pull-up to VDDIO1. VDDD, VDDA, and VDDIO1 must

all have voltage applied before the part comes out of reset.

When a wakeup event occurs, the global mode is always

returned to active, and the CPU is automatically enabled,

regardless of its template settings. Active mode is the default

global power mode upon boot.

 Watchdog timer – A watchdog timer monitors the execution of

instructions by the processor. If the watchdog timer is not reset

by firmware within a certain period of time, the watchdog timer

generates a reset.

6.2.1.2 Alternate Active Mode

 Software – The device can be reset under program control.

Alternate Active mode is very similar to Active mode. In alternate

active mode, fewer subsystems are enabled, to reduce power

consumption. One possible configuration is to turn off the CPU

and flash, and run peripherals at full speed.

Figure 6-6. Resets

Vddd Vdda

6.2.1.3 Sleep Mode

Power

Processor

Interrupt

Sleep mode reduces power consumption when a resume time of

15 µs is acceptable. The wake time is used to ensure that the

regulator outputs are stable enough to directly enter active

mode.

Voltage

Level

Monitors

Reset

6.2.1.4 Hibernate Mode

External

Reset

Controller

System

Reset

In hibernate mode nearly all of the internal functions are

disabled. Internal voltages are reduced to the minimal level to

keep vital systems alive. Configuration state is preserved in

hibernate mode and SRAM memory is retained. GPIOs

configured as digital outputs maintain their previous values and

external GPIO pin interrupt settings are preserved. The device

can only return from hibernate mode in response to an external

I/O interrupt. The resume time from hibernate mode is less than

100 µs.

Watchdog

Timer

Software

Reset

To achieve an extremely low current, the hibernate regulator has

limited capacity. This limits the frequency of any signal present

on the input pins - no GPIO should toggle at a rate greater than

10 kHz while in hibernate mode. If pins must be toggled at a high

rate while in a low power mode, use sleep mode instead.

Register

The term device reset indicates that the processor as well as

analog and digital peripherals and registers are reset.

A reset status register shows some of the resets or power voltage

monitoring interrupts. The program may examine this register to

Document Number: 001-57330 Rev. *G

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PSoC^®3: CY8C36

Automotive Family Datasheet

detect and report certain exception conditions. This register is

cleared after a power-on reset. For details see the Technical

Reference Manual.

Table 6-4. Analog/Digital Low Voltage Interrupt, Analog High

Voltage Interrupt

Normal Voltage

Interrupt Supply

Available Trip Settings

6.3.1 Reset Sources

Range

DLVI

ALVI

AHVI

VDDD 1.71 V–5.5 V

VDDA 1.71 V–5.5 V

1.70 V–5.45 V in 250 mV

increments

6.3.1.1 Power Voltage Level Monitors

 IPOR – Initial power-on reset

1.70 V–5.45 V in 250 mV

increments

At initial power on, IPOR monitors the power voltages V_DDD

,

V_DDA, V_CCDand V_CCA. The trip level is not precise. It is set to

5.75 V

approximately 1 volt, which is below the lowest specified

operating voltage but high enough for the internal circuits to be

reset and to hold their reset state. The monitor generates a

reset pulse that is at least 150 ns wide. It may be much wider

if one or more of the voltages ramps up slowly.

The monitors are disabled until after IPOR. During sleep mode

these circuits are periodically activated (buzzed). If an interrupt

occurs during buzzing then the system first enters its wakeup

sequence. The interrupt is then recognized and may be

serviced.

If after the IPOR triggers either V_DDXdrops back below the

trigger point, in a non-monotonic fashion, it must remain below

that point for at least 10 µs. The hysteresis of the IPOR trigger

point is typically 100 mV.

The buzz frequency is adjustable, and should be set to be less

than the minimum time that any voltage is expected to be out

of range. For details on how to adjust the buzz frequency, see

the TRM.

After boot, the IPOR circuit is disabled and voltage supervision

is handed off to the precise low-voltage reset (PRES) circuit.

6.3.1.2 Other Reset Sources

 XRES – External reset

 PRES – Precise low voltage reset

PSoC 3 has either a single GPIO pin that is configured as an

external reset or a dedicated XRES pin. Either the dedicated

XRES pin or the GPIO pin, if configured, holds the part in reset

while held active (low). The response to an XRES is the same

as to an IPOR reset.

This circuit monitors the outputs of the analog and digital

internal regulators after power up. The regulator outputs are

compared to a precise reference voltage. The response to a

PRES trip is identical to an IPOR reset.

After PRES has been deasserted, at least 10 µs must elapse

before it can be reasserted.

After XRES has been deasserted, at least 10 µs must elapse

before it can be reasserted.

In normal operating mode, the program cannot disable the

digital PRES circuit. The analog regulator can be disabled,

which also disables the analog portion of the PRES. The PRES

circuit is disabled automatically during sleep and hibernate

modes, with one exception: During sleep mode the regulators

are periodically activated (buzzed) to provide supervisory

services and to reduce wakeup time. At these times the PRES

circuit is also buzzed to allow periodic voltage monitoring.

The external reset is active low. It includes an internal pull-up

resistor. XRES is active during sleep and hibernate modes.

 SRES – Software reset

A reset can be commanded under program control by setting

a bit in the software reset register. This is done either directly

by the program or indirectly by DMA access. The response to

a SRES is the same as after an IPOR reset.

Another register bit exists to disable this function.

 ALVI, DLVI, AHVI – Analog/digital low voltage interrupt, analog

high voltage interrupt

 WRES – Watchdog timer reset

The watchdog reset detects when the software program is no

longer being executed correctly. To indicate to the watchdog

timer that it is running correctly, the program must periodically

reset the timer. If the timer is not reset before a user-specified

amount of time, then a reset is generated.

Note IPOR disables the watchdog function. The program must

enable the watchdog function at an appropriate point in the

code by setting a register bit. When this bit is set, it cannot be

cleared again except by an IPOR power on reset event.

Interrupt circuits are available to detect when VDDA and

VDDD go outside a voltage range. For AHVI, VDDA is

compared to a fixed trip level. For ALVI and DLVI, VDDA and

VDDD are compared to trip levels that are programmable, as

listed in Table 6-4. ALVI and DLVI can also be configured to

generate a device reset instead of an interrupt.

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PSoC^®3: CY8C36

Automotive Family Datasheet

 Slew rate controlled digital output drive mode

 Access port control and configuration registers on either port

basis or pin basis

 Separateportread(PS)andwrite(DR)dataregisterstoavoid

read modify write errors

6.4 I/O System and Routing

PSoC I/Os are extremely flexible. Every GPIO has analog and

digital I/O capability. All I/Os have a large number of drive modes,

which are set at POR. PSoC also provides up to four individual

I/O voltage domains through the VDDIO pins.

 Special functionality on a pin by pin basis

There are two types of I/O pins on every device; those with USB

provide a third type. Both GPIO and SIO provide similar digital

functionality. The primary differences are their analog capability

and drive strength. Devices that include USB also provide two

USBIO pins that support specific USB functionality as well as

limited GPIO capability.

All I/O pins are available for use as digital inputs and outputs for

both the CPU and digital peripherals. In addition, all I/O pins can

generate an interrupt. The flexible and advanced capabilities of

the PSoC I/O, combined with any signal to any pin routability,

greatly simplify circuit design and board layout. All GPIO pins can

be used for analog input, CapSense^[12], and LCD segment drive,

while SIO pins are used for voltages in excess of VDDA and for

programmable output voltages.

 Additional features only provided on the GPIO pins:

 LCD segment drive on LCD equipped devices

 CapSense^[12]

 Analog input and output capability

 Continuous 100 µA clamp current capability

 Standard drive strength down to 1.7 V

 Additional features only provided on SIO pins:

 Higher drive strength than GPIO

 Hot swap capability (5 V tolerance at any operating V_DD

 Programmable and regulated high input and output drive

levels down to 1.2 V

 No analog input, CapSense, or LCD capability

 Over voltage tolerance up to 5.5 V

 SIO can act as a general purpose analog comparator

 USBIO features:

 Full speed USB 2.0 compliant I/O

 Highest drive strength for general purpose use

 Input, output, or both for CPU and DMA

 Input, output, or both for digital peripherals

 Digital output (CMOS) drive mode

 Each pin can be an interrupt source configured as rising

edge, falling edge, or both edges

)

 Features supported by both GPIO and SIO:

 User programmable port reset state

 SeparateI/OsuppliesandvoltagesforuptofourgroupsofI/O

 Digital peripherals use DSI to connect the pins

 Input or output or both for CPU and DMA

 Eight drive modes

 Every pin can be an interrupt source configured as rising

edge, falling edge or both edges. If required, level sensitive

interrupts are supported through the DSI

 Dedicated port interrupt vector for each port

Note

12. GPIOs with opamp outputs are not recommended for use with CapSense.

Document Number: 001-57330 Rev. *G

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PSoC^®3: CY8C36

Automotive Family Datasheet

Figure 6-7. GPIO Block Diagram

Digital Input Path

Naming Convention

‘x’ = Port Number

‘y’ = Pin Number

PRT[x]CTL

PRT[x]DBL_SYNC_IN

PRT[x]PS

Digital System Input

PICU[x]INTTYPE[y]

PICU[x]INTSTAT

Pin Interrupt Signal

PICU[x]INTSTAT

Input Buffer Disable

Interrupt

Logic

Digital Output Path

PRT[x]SLW

PRT[x]SYNC_OUT

Vddio Vddio

Vddio

PRT[x]DR

0

1

In

Digital System Output

PRT[x]BYP

Drive

Logic

PRT[x]DM2

PRT[x]DM1

PRT[x]DM0

Slew

Cntl

Bidirectional Control

PRT[x]BIE

OE

Analog

1

0

1

0

1

Capsense Global Control

CAPS[x]CFG1

Switches

PRT[x]AG

Analog Global Enable

PRT[x]AMUX

Analog Mux Enable

LCD

Display

Data

Logic & MUX

PRT[x]LCD_COM_SEG

PRT[x]LCD_EN

LCD Bias Bus

5

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PSoC^®3: CY8C36

Automotive Family Datasheet

Figure 6-8. SIO Input/Output Block Diagram

Digital Input Path

Naming Convention

‘x’ = Port Number

‘y’ = Pin Number

PRT[x]SIO_HYST_EN

PRT[x]SIO_DIFF

Buffer

Thresholds

Reference Level

PRT[x]DBL_SYNC_IN

PRT[x]PS

Digital System Input

PICU[x]INTTYPE[y]

PICU[x]INTSTAT

Pin Interrupt Signal

PICU[x]INTSTAT

Input Buffer Disable

Interrupt

Logic

Digital Output Path

Reference Level

PRT[x]SIO_CFG

PRT[x]SLW

Driver

Vhigh

PRT[x]SYNC_OUT

PRT[x]DR

0

1

In

Digital System Output

PRT[x]BYP

Drive

Logic

PRT[x]DM2

PRT[x]DM1

PRT[x]DM0

Slew

Cntl

Bidirectional Control

PRT[x]BIE

OE

Figure 6-9. USBIO Block Diagram

Digital Input Path

Naming Convention

‘y’ = Pin Number

USB Receiver Circuitry

PRT[15]DBL_SYNC_IN

PRT[15]PS[6,7]

USBIO_CR1[0,1]

Digital System Input

PICU[15]INTTYPE[y]

PICU[15]INTSTAT

Pin Interrupt Signal

PICU[15]INTSTAT

Interrupt

Logic

Digital Output Path

PRT[15]SYNC_OUT

USBIO_CR1[5]

USB or I/O

D+ 1.5 k

D+ pin only

Vddd Vddd Vddd

USBIO_CR1[2]

Vddd

USB SIE Control for USB Mode

PRT[15]DR1[7,6]

0

1

In

Digital System Output

PRT[15]BYP

5 k

1.5 k

Drive

Logic

PRT[15]DM0[6]

PRT[15]DM0[7]

D+ Open

Drain

D- Open

Drain

PRT[15]DM1[6]

PRT[15]DM1[7]

D+ 5 k

D- 5 k

Document Number: 001-57330 Rev. *G

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PSoC^®3: CY8C36

Automotive Family Datasheet

6.4.1 Drive Modes

Each GPIO and SIO pin is individually configurable into one of the eight drive modes listed in Table 6-5. Three configuration bits are

used for each pin (DM[2:0]) and set in the PRTxDM[2:0] registers. Figure 6-10 depicts a simplified pin view based on each of the eight

drive modes. Table 6-5 shows the I/O pin’s drive state based on the port data register value or digital array signal if bypass mode is

selected. Note that the actual I/O pin voltage is determined by a combination of the selected drive mode and the load at the pin. For

example, if a GPIO pin is configured for resistive pull-up mode and driven high while the pin is floating, the voltage measured at the

pin is a high logic state. If the same GPIO pin is externally tied to ground then the voltage unmeasured at the pin is a low logic state.

Figure 6-10. Drive Mode

Vddio

DR

PS

DR

PS

DR

PS

DR

PS

0. High Impedance

Analog

1. High Impedance

Digital

2. Resistive

Pull Up

3. Resistive

Pull Down

Vddio

DR

PS

DR

PS

DR

PS

DR

PS

4. Open Drain,

Drives Low

5. Open Drain,

Drives High

6. Strong Drive

7. Resistive

Pull Up and Down

Table 6-5. Drive Modes

Diagram

Drive Mode

PRTxDM2

PRTxDM1

PRTxDM0

PRTxDR = 1

High Z

PRTxDR = 0

High Z

0

1

2

3

4

5

6

7

High impedance analog

High Impedance digital

Resistive pull-up^[13]

Resistive pull-down^[13]

Open drain, drives low

Open drain, drive high

Strong drive

0

1

0

1

0

1

0

1

0

1

0

1

0

1

High Z

Res High (5K)

Strong High

High Z

Strong Low

Res Low (5K)

Strong Low

High Z

Strong High

Res High (5K)

Strong Low

Res Low (5K)

Resistive pull-up and pull-down^[13]

Note

13. Resistive pull-up and pull-down are not available with SIO in regulated output mode.

Document Number: 001-57330 Rev. *G

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PSoC^®3: CY8C36

Automotive Family Datasheet

The USBIO pins (P15[7] and P15[6]), when enabled for I/O mode, have limited drive mode control. The drive mode is set using the

PRT15.DM0[7, 6] register. A resistive pull option is also available at the USBIO pins, which can be enabled using the PRT15.DM1[7,

6] register. When enabled for USB mode, the drive mode control has no impact on the configuration of the USB pins. Unlike the GPIO

and SIO configurations, the port wide configuration registers do not configure the USB drive mode bits. Table 6-6 shows the drive

mode configuration for the USBIO pins.

Table 6-6. USBIO Drive Modes (P15[7] and P15[6])

PRT15.DM1[7,6]

Pull up enable

PRT15.DM0[7,6]

Drive Mode enable

PRT15.DR[7,6] = 1

PRT15.DR[7,6] = 0

Description

0

1

0

1

0

1

High Z

Strong Low

Open Drain, Strong Low

Strong Outputs

Strong High

Res High (5k)

Strong High

Resistive Pull Up, Strong Low

Strong Outputs

 High impedance analog

6.4.2 Pin Registers

The default reset state with both the output driver and digital

input buffer turned off. This prevents any current from flowing

in the I/O’s digital input buffer due to a floating voltage. This

state is recommended for pins that are floating or that support

an analog voltage. High impedance analog pins do not provide

digital input functionality.

Registers to configure and interact with pins come in two forms

that may be used interchangeably.

All I/O registers are available in the standard port form, where

each bit of the register corresponds to one of the port pins. This

register form is efficient for quickly reconfiguring multiple port

pins at the same time.

To achieve the lowest chip current in sleep modes, all I/Os

must either be configured to the high impedance analog mode,

or have their pins driven to a power supply rail by the PSoC

device or by external circuitry.

I/O registers are also available in pin form, which combines the

eight most commonly used port register bits into a single register

for each pin. This enables very fast configuration changes to

individual pins with a single register write.

 High impedance digital

6.4.3 Bidirectional Mode

The input buffer is enabled for digital signal input. This is the

standard high impedance (High Z) state recommended for

digital inputs.

High speed bidirectional capability allows pins to provide both

the high impedance digital drive mode for input signals and a

second user selected drive mode such as strong drive (set using

PRT×DM[2:0] registers) for output signals on the same pin,

based on the state of an auxiliary control bus signal. The

bidirectional capability is useful for processor busses and

communications interfaces such as the SPI Slave MISO pin that

requires dynamic hardware control of the output buffer.

 Resistive pull-up or resistive pull-down

Resistive pull-up or pull-down, respectively, provides a series

resistance in one of the data states and strong drive in the

other. Pins can be used for digital input and output in these

modes. Interfacing to mechanical switches is a common

application for these modes. Resistive pullup and pull-down

are not available with SIO in regulated output mode.

The auxiliary control bus routes up to 16 UDB or digital peripheral

generated output enable signals to one or more pins.

 Open drain, drives high and open drain, drives low

6.4.4 Slew Rate Limited Mode

Open drain modes provide high impedance in one of the data

states and strong drive in the other. Pins can be used for digital

input and output in these modes. A common application for

these modes is driving the I²C bus signal lines.

GPIO and SIO pins have fast and slow output slew rate options

for strong and open drain drive modes, not resistive drive modes.

Because it results in reduced EMI, the slow edge rate option is

recommended for signals that are not speed critical, generally

less than 1 MHz. The fast slew rate is for signals between 1 MHz

and 33 MHz. The slew rate is individually configurable for each

pin, and is set by the PRT×SLW registers.

 Strong drive

Provides a strong CMOS output drive in either high or low

state. This is the standard output mode for pins. Strong Drive

mode pins must not be used as inputs under normal

circumstances. This mode is often used to drive digital output

signals or external FETs.

 Resistive pull-up and pull-down

Similar to the resistive pull-up and resistive pull-down modes

except the pin is always in series with a resistor. The high data

state is pull-up while the low data state is pull-down. This mode

is most often used when other signals that may cause shorts

can drive the bus. Resistive pullup and pull-down are not

available with SIO in regulated output mode.

Document Number: 001-57330 Rev. *G

Page 37 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

6.4.5 Pin Interrupts

6.4.9 CapSense

All GPIO and SIO pins are able to generate interrupts to the

system. All eight pins in each port interface to their own Port

Interrupt Control Unit (PICU) and associated interrupt vector.

Each pin of the port is independently configurable to detect rising

edge, falling edge, both edge interrupts, or to not generate an

interrupt.

This section applies only to GPIO pins. All GPIO pins may be

used to create CapSense buttons and sliders^[14]. See the

“CapSense” section on page 58 for more information.

6.4.10 LCD Segment Drive

This section applies only to GPIO pins. All GPIO pins may be

used to generate Segment and Common drive signals for direct

glass drive of LCD glass. See the “LCD Direct Drive” section on

page 57 for details.

Depending on the configured mode for each pin, each time an

interrupt event occurs on a pin, its corresponding status bit of the

interrupt status register is set to ‘1’ and an interrupt request is

sent to the interrupt controller. Each PICU has its own interrupt

vector in the interrupt controller and the pin status register

providing easy determination of the interrupt source down to the

pin level.

6.4.11 Adjustable Output Level

This section applies only to SIO pins. SIO port pins support the

ability to provide a regulated high output level for interface to

external signals that are lower in voltage than the SIO’s

respective VDDIO. SIO pins are individually configurable to

output either the standard VDDIO level or the regulated output,

which is based on an internally generated reference. Typically a

voltage DAC (VDAC) is used to generate the reference (see

Figure 6-11). The “DAC” section on page 59 has more details on

VDAC use and reference routing to the SIO pins. Resistive

pullup and pull-down drive modes are not available with SIO in

regulated output mode.

Port pin interrupts remain active in all sleep modes allowing the

PSoC device to wake from an externally generated interrupt.

While level sensitive interrupts are not directly supported; UDB

provide this functionality to the system when needed.

6.4.6 Input Buffer Mode

GPIO and SIO input buffers can be configured at the port level

for the default CMOS input thresholds or the optional LVTTL

input thresholds. All input buffers incorporate Schmitt triggers for

input hysteresis. Additionally, individual pin input buffers can be

disabled in any drive mode.

6.4.12 Adjustable Input Level

This section applies only to SIO pins. SIO pins by default support

the standard CMOS and LVTTL input levels but also support a

differential mode with programmable levels. SIO pins are

grouped into pairs. Each pair shares a reference generator block

which, is used to set the digital input buffer reference level for

interface to external signals that differ in voltage from VDDIO.

The reference sets the pins voltage threshold for a high logic

level (see Figure 6-11). Available input thresholds are:

6.4.7 I/O Power Supplies

Up to four I/O pin power supplies are provided depending on the

device and package. Each I/O supply must be less than or equal

to the voltage on the chip’s analog (VDDA) pin. This feature

allows users to provide different I/O voltage levels for different

pins on the device. Refer to the specific device package pinout

to determine VDDIO capability for a given port and pin. The SIO

port pins support an additional regulated high output capability,

as described in Adjustable Output Level.

 0.5 VDDIO

 0.4 VDDIO

 0.5 V_REF

 V_REF

6.4.8 Analog Connections

These connections apply only to GPIO pins. All GPIO pins may

be used as analog inputs or outputs. The analog voltage present

on the pin must not exceed the VDDIO supply voltage to which

the GPIO belongs. Each GPIO may connect to one of the analog

global busses or to one of the analog mux buses to connect any

pin to any internal analog resource such as ADC or comparators.

In addition, select pins provide direct connections to specific

analog features such as the high current DACs or uncommitted

opamps.

Typically a voltage DAC (VDAC) generates the V_REFreference.

“DAC” section on page 59 has more details on VDAC use and

reference routing to the SIO pins.

Note

14. GPIOs with opamp outputs are not recommended for use with CapSense.

Document Number: 001-57330 Rev. *G

Page 38 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

Figure 6-11. SIO Reference for Input and Output

 There are no current limitations for the SIO pins as they present a

high impedance load to the external circuit where VDDIO < V_IN

<

Input Path

5.5 V.

 TheGPIOpinsmustbelimitedto100µAusingacurrentlimiting

resistor. GPIO pins clamp the pin voltage to approximately one

diode above the VDDIO supply where VDDIO < V_IN< VDDA.

 In case of a GPIO pin configured for analog input/output, the

analog voltage on the pin must not exceed the VDDIO supply

voltage to which the GPIO belongs.

Digital

Input

Vinref

A common application for this feature is connection to a bus such

as I²C where different devices are running from different supply

voltages. In the I²C case, the PSoC chip is configured into the

Open Drain, Drives Low mode for the SIO pin. This allows an

external pull-up to pull the I²C bus voltage above the PSoC pin

supply. For example, the PSoC chip could operate at 1.8 V, and

an external device could run from 5 V. Note that the SIO pin’s V_IH

and V_ILlevels are determined by the associated VDDIO supply

pin. The SIO pin must be in one of the following modes: 0 (high

impedance analog), 1 (high impedance digital), or 4 (open drain

drives low). See Figure 6-10 for details. Absolute maximum

ratings for the device must be observed for all I/O pins.

Reference

Generator

SIO_Ref

Voutref

Output Path

Driver

Vhigh

6.4.16 Reset Configuration

Digital

Output

Drive

Logic

While reset is active all I/Os are reset to and held in the High

Impedance Analog state. After reset is released, the state can be

reprogrammed on a port-by-port basis to pull-down or pull-up. To

ensure correct reset operation, the port reset configuration data

is stored in special nonvolatile registers. The stored reset data is

automatically transferred to the port reset configuration registers

at reset release.

6.4.13 SIO as Comparator

6.4.17 Low-Power Functionality

This section applies only to SIO pins. The adjustable input level

feature of the SIOs as explained in the Adjustable Input Level

section can be used to construct a comparator. The threshold for

the comparator is provided by the SIO's reference generator. The

reference generator has the option to set the analog signal

routed through the analog global line as threshold for the

comparator. Note that a pair of SIO pins share the same

threshold. The digital input path in Figure 6-8 on page 35

illustrates this functionality. In the figure, ‘Reference level’ is the

analog signal routed through the analog global. The hysteresis

feature can also be enabled for the input buffer of the SIO, which

increases noise immunity for the comparator.

In all low-power modes the I/O pins retain their state until the part

is awakened and changed or reset. To awaken the part, use a

pin interrupt, because the port interrupt logic continues to

function in all low-power modes.

6.4.18 Special Pin Functionality

Some pins on the device include additional special functionality

in addition to their GPIO or SIO functionality. The specific special

function pins are listed in Pinouts on page 5. The special features

are:

 Digital

 4- to 25-MHz crystal oscillator

 32.768-kHz crystal oscillator

6.4.14 Hot Swap

 Wake from sleep on I²C address match. Any pin can be used

This section applies only to SIO pins. SIO pins support ‘hot swap’

capability to plug into an application without loading the signals

that are connected to the SIO pins even when no power is

applied to the PSoC device. This allows the unpowered PSoC to

maintain a high impedance load to the external device while also

preventing the PSoC from being powered through a SIO pin’s

protection diode.

for I²C if wake from sleep is not required.

 JTAG interface pins

 SWD interface pins

 SWV interface pins

 External reset

 Analog

Powering the device up or down while connected to an

operational I2C bus may cause transient states on the SIO pins.

The overall I2C bus design should take this into account.

 Opamp inputs and outputs

 High current IDAC outputs

 External reference inputs

6.4.15 Over Voltage Tolerance

6.4.19 JTAG Boundary Scan

All I/O pins provide an over voltage tolerance feature at any

The device supports standard JTAG boundary scan chains on all

I/O pins for board level test.

operating V_DD

.

Document Number: 001-57330 Rev. *G

Page 39 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

7.1 Example Peripherals

7. Digital Subsystem

The flexibility of the CY8C36 family’s UDBs and analog blocks

allow the user to create a wide range of components

(peripherals). The most common peripherals were built and

characterized by Cypress and are shown in the PSoC Creator

component catalog, however, users may also create their own

custom components using PSoC Creator. Using PSoC Creator,

users may also create their own components for reuse within

their organization, for example sensor interfaces, proprietary

algorithms, and display interfaces.

The digital programmable system creates application specific

combinations of both standard and advanced digital peripherals

and custom logic functions. These peripherals and logic are then

interconnected to each other and to any pin on the device,

providing a high level of design flexibility and IP security.

The features of the digital programmable system are outlined

here to provide an overview of capabilities and architecture. You

do not need to interact directly with the programmable digital

system at the hardware and register level. PSoC Creator

provides a high level schematic capture graphical interface to

automatically place and route resources similar to PLDs.

The number of components available through PSoC Creator is

too numerous to list in the data sheet, and the list is always

growing. An example of a component available for use in

CY8C36 family, but, not explicitly called out in this data sheet is

the UART component.

The main components of the digital programmable system are:

 UDB – These form the core functionality of the digital

programmable system. UDBs are a collection of uncommitted

logic (PLD) and structural logic (Datapath) optimized to create

all common embedded peripherals and customized

functionality that are application or design specific.

7.1.1 Example Digital Components

The following is a sample of the digital components available in

PSoC Creator for the CY8C36 family. The exact amount of

hardware resources (UDBs, routing, RAM, flash) used by a

component varies with the features selected in PSoC Creator for

the component.

 Universal digital block array – UDB blocks are arrayed within

a matrix of programmable interconnect. The UDB array

structure is homogeneous and allows for flexible mapping of

digital functions onto the array. The array supports extensive

and flexible routing interconnects between UDBs and the

Digital System Interconnect.

 Communications

 I²C

 UART

 SPI

 Digital system interconnect (DSI) – Digital signals from UDBs,

fixed function peripherals, I/O pins, interrupts, DMA, and other

system core signals are attached to the digital system

interconnecttoimplementfullfeatureddeviceconnectivity. The

DSI allows any digital function to any pin or other feature

routability when used with the universal digital block array.

 Functions

 EMIF

 PWMs

 Timers

 Counters

Figure 7-1. CY8C36 Digital Programmable Architecture

 Logic

 NOT

 OR

Digital Core System

and Fixed Function Peripherals

 XOR

 AND

DSI Routing Interface

7.1.2 Example Analog Components

UDB

The following is a sample of the analog components available in

PSoC Creator for the CY8C36 family. The exact amount of

hardware resources (SC/CT blocks, routing, RAM, flash) used

by a component varies with the features selected in PSoC

Creator for the component.

 Amplifiers

 TIA

 PGA

DSI Routing Interface

 opamp

 ADC

Digital Core System

 Delta-sigma

and Fixed Function Peripherals

 DACs

 Current

 Voltage

 PWM

 Comparators

 Mixers

Document Number: 001-57330 Rev. *G

Page 40 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

7.1.3 Example System Function Components

7.1.4.2 Component Catalog

The following is a sample of the system function components

available in PSoC Creator for the CY8C36 family. The exact

amount of hardware resources (UDBs, DFB taps, SC/CT blocks,

routing, RAM, flash) used by a component varies with the

features selected in PSoC Creator for the component.

The component catalog is a repository of reusable design

elements that select device functionality and customize your

PSoC device. It is populated with an impressive selection of

content; from simple primitives such as logic gates and device

registers, through the digital timers, counters and PWMs, plus

analog components such as ADC, DACs, and filters, and

communication protocols, such as I²C, USB, and CAN. See

Example Peripherals on page 40 for more details about available

peripherals. All content is fully characterized and carefully

documented in data sheets with code examples, AC/DC

specifications, and user code ready APIs.

 CapSense

 LCD drive

 LCD control

 Filters

7.1.4.3 Design Reuse

7.1.4 Designing with PSoC Creator

7.1.4.1 More Than a Typical IDE

The symbol editor gives you the ability to develop reusable

components that can significantly reduce future design time. Just

draw a symbol and associate that symbol with your proven

design. PSoC Creator allows for the placement of the new

symbol anywhere in the component catalog along with the

content provided by Cypress. You can then reuse your content

as many times as you want, and in any number of projects,

without ever having to revisit the details of the implementation.

A successful design tool allows for the rapid development and

deployment of both simple and complex designs. It reduces or

eliminates any learning curve. It makes the integration of a new

design into the production stream straightforward.

PSoC Creator is that design tool.

PSoC Creator is a full featured Integrated Development

Environment (IDE) for hardware and software design. It is

optimized specifically for PSoC devices and combines a modern,

powerful software development platform with a sophisticated

graphical design tool. This unique combination of tools makes

PSoC Creator the most flexible embedded design platform

available.

7.1.4.4 Software Development

Anchoring the tool is a modern, highly customizable user

interface. It includes project management and integrated editors

for C and assembler source code, as well the design entry tools.

Project build control leverages compiler technology from top

commercial vendors such as ARM^®Limited, Keil™, and

CodeSourcery (GNU). Free versions of Keil C51 and GNU C

Compiler (GCC) for ARM, with no restrictions on code size or end

product distribution, are included with the tool distribution.

Upgrading to more optimizing compilers is a snap with support

for the professional Keil C51 product and ARM RealView™

compiler.

Graphical design entry simplifies the task of configuring a

particular part. You can select the required functionality from an

extensive catalog of components and place it in your design. All

components are parameterized and have an editor dialog that

allows you to tailor functionality to your needs.

PSoC Creator automatically configures clocks and routes the I/O

to the selected pins and then generates APIs to give the

application complete control over the hardware. Changing the

PSoC device configuration is as simple as adding a new

component, setting its parameters, and rebuilding the project.

7.1.4.5 Nonintrusive Debugging

With JTAG (4-wire) and SWD (2-wire) debug connectivity

available on all devices, the PSoC Creator debugger offers full

control over the target device with minimum intrusion.

Breakpoints and code execution commands are all readily

available from toolbar buttons and an impressive lineup of

windows—register, locals, watch, call stack, memory and

peripherals—make for an unparalleled level of visibility into the

system.

At any stage of development you are free to change the

hardware configuration and even the target processor. To

retarget your application (hardware and software) to new

devices, even from 8- to 32-bit families, just select the new

device and rebuild.

You also have the ability to change the C compiler and evaluate

an alternative. Components are designed for portability and are

validated against all devices, from all families, and against all

supported tool chains. Switching compilers is as easy as editing

the from the project options and rebuilding the application with

no errors from the generated APIs or boot code.

PSoC Creator contains all the tools necessary to complete a

design, and then to maintain and extend that design for years to

come. All steps of the design flow are carefully integrated and

optimized for ease-of-use and to maximize productivity.

Document Number: 001-57330 Rev. *G

Page 41 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

 Status and control module – The primary role of this block is to

provide a way for CPU firmware to interact and synchronize

with UDB operation.

7.2 Universal Digital Block

The UDB represents an evolutionary step to the next generation

of PSoC embedded digital peripheral functionality. The

architecture in first generation PSoC digital blocks provides

coarse programmability in which a few fixed functions with a

small number of options are available. The new UDB

architecture is the optimal balance between configuration

granularity and efficient implementation. A cornerstone of this

approach is to provide the ability to customize the devices digital

operation to match application requirements.

 Clock and reset module – This block provides the UDB clocks

and reset selection and control.

7.2.1 PLD Module

The primary purpose of the PLD blocks is to implement logic

expressions, state machines, sequencers, lookup tables, and

decoders. In the simplest use model, consider the PLD blocks as

a standalone resource onto which general purpose RTL is

synthesized and mapped. The more common and efficient use

model is to create digital functions from a combination of PLD

and datapath blocks, where the PLD implements only the

random logic and state portion of the function while the datapath

(ALU) implements the more structured elements.

To achieve this, UDBs consist of a combination of uncommitted

logic (PLD), structured logic (Datapath), and a flexible routing

scheme to provide interconnect between these elements, I/O

connections, and other peripherals. UDB functionality ranges

from simple self contained functions that are implemented in one

UDB, or even a portion of a UDB (unused resources are

available for other functions), to more complex functions that

require multiple UDBs. Examples of basic functions are timers,

counters, CRC generators, PWMs, dead band generators, and

communications functions, such as UARTs, SPI, and I²C. Also,

the PLD blocks and connectivity provide full featured general

purpose programmable logic within the limits of the available

resources.

Figure 7-3. PLD 12C4 Structure

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

IN8

IN9

IN10

IN11

T C T C T C T C T C T C T C T C

Figure 7-2. UDB Block Diagram

AND

Array

PLD

Chaining

PLD

12C4

(8 PTs)

PLD

12C4

(8 PTs)

Clock

and Reset

Control

Carry In

Status and

Control

Datapath

T

MC0

MC1

MC2

MC3

OUT0

OUT1

OUT2

OUT3

Datapath

Chaining

Carry Out

OR

Array

Routing Channel

One 12C4 PLD block is shown in Figure 7-3. This PLD has 12

inputs, which feed across eight product terms. Each product term

(AND function) can be from 1 to 12 inputs wide, and in a given

product term, the true (T) or complement (C) of each input can

be selected. The product terms are summed (OR function) to

create the PLD outputs. A sum can be from 1 to 8 product terms

wide. The 'C' in 12C4 indicates that the width of the OR gate (in

this case 8) is constant across all outputs (rather than variable

as in a 22V10 device). This PLA like structure gives maximum

flexibility and insures that all inputs and outputs are permutable

for ease of allocation by the software tools. There are two 12C4

PLDs in each UDB.

The main component blocks of the UDB are:

 PLD blocks – There are two small PLDs per UDB. Theseblocks

take inputs from the routing array and form registered or

combinational sum-of-products logic. PLDs are used to

implement state machines, state bits, and combinational logic

equations. PLD configuration is automatically generated from

graphical primitives.

 Datapathmodule–This8-bitwidedatapathcontainsstructured

logic to implement a dynamically configurable ALU, a variety

ofcompare configurations andconditiongeneration. Thisblock

alsocontainsinput/outputFIFOs, whicharetheprimaryparallel

data interface between the CPU/DMA system and the UDB.

Document Number: 001-57330 Rev. *G

Page 42 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

7.2.2 Datapath Module

The datapath contains an 8-bit single cycle ALU, with associated compare and condition generation logic. This datapath block is

optimized to implement embedded functions, such as timers, counters, integrators, PWMs, PRS, CRC, shifters and dead band

generators and many others.

Figure 7-4. Datapath Top Level

PHUB System Bus

R/W Access to All

Registers

F1

FIFOs

Output

Muxes

Input

Muxes

F0

A0

A1

D0

D1

Input from

Programmable

Routing

Output to

Programmable

Routing

6

D1

Data Registers

D0

To/From

Chaining

A1

Accumulators

A0

PI

Parallel Input/Output

(to/from Programmable Routing)

PO

ALU

Shift

Mask

7.2.2.1 Working Registers

7.2.2.2 Dynamic Datapath Configuration RAM

The datapath contains six primary working registers, which are

accessed by CPU firmware or DMA during normal operation.

Dynamic configuration is the ability to change the datapath

function and internal configuration on a cycle-by-cycle basis,

under sequencer control. This is implemented using the 8-word

× 16-bit configuration RAM, which stores eight unique 16-bit

wide configurations. The address input to this RAM controls the

sequence, and can be routed from any block connected to the

UDB routing matrix, most typically PLD logic, I/O pins, or from

the outputs of this or other datapath blocks.

Table 7-1. Working Datapath Registers

Name

Function

Description

A0 and A1 Accumulators

These are sources and sinks for

the ALU and also sources for the

compares.

ALU

D0 and D1 Data Registers These are sources for the ALU

and sources for the compares.

The ALU performs eight general purpose functions. They are:

F0 and F1 FIFOs

These are the primary interface

to the system bus. They can be a

data source for the data registers

and accumulators or they can

capture data from the

 Increment

 Decrement

 Add

 Subtract

 Logical AND

 Logical OR

 Logical XOR

accumulatorsorALU. EachFIFO

is four bytes deep.

 Pass, used to pass a value through the ALU to the shift register,

mask, or another UDB register.

Document Number: 001-57330 Rev. *G

Page 43 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

Independent of the ALU operation, these functions are available:

7.2.2.7 Chaining

The datapath can be configured to chain conditions and signals

such as carries and shift data with neighboring datapaths to

create higher precision arithmetic, shift, CRC/PRS functions.

 Shift left

 Shift right

 Nibble swap

 Bitwise OR mask

7.2.2.8 Time Multiplexing

In applications that are over sampled, or do not need high clock

rates, the single ALU block in the datapath can be efficiently

shared with two sets of registers and condition generators. Carry

and shift out data from the ALU are registered and can be

selected as inputs in subsequent cycles. This provides support

for 16-bit functions in one (8-bit) datapath.

7.2.2.3 Conditionals

Each datapath has two compares, with bit masking options.

Compare operands include the two accumulators and the two

data registers in a variety of configurations. Other conditions

include zero detect, all ones detect, and overflow. These

conditions are the primary datapath outputs, a selection of which

can be driven out to the UDB routing matrix. Conditional

computation can use the built in chaining to neighboring UDBs

to operate on wider data widths without the need to use routing

resources.

7.2.2.9 Datapath I/O

There are six inputs and six outputs that connect the datapath to

the routing matrix. Inputs from the routing provide the

configuration for the datapath operation to perform in each cycle,

and the serial data inputs. Inputs can be routed from other UDB

blocks, other device peripherals, device I/O pins, and so on. The

outputs to the routing can be selected from the generated

conditions, and the serial data outputs. Outputs can be routed to

other UDB blocks, device peripherals, interrupt and DMA

controller, I/O pins, and so on.

7.2.2.4 Variable MSB

The most significant bit of an arithmetic and shift function can be

programmatically specified. This supports variable width CRC

and PRS functions, and in conjunction with ALU output masking,

can implement arbitrary width timers, counters and shift blocks.

7.2.3 Status and Control Module

7.2.2.5 Built in CRC/PRS

The primary purpose of this circuitry is to coordinate CPU

firmware interaction with internal UDB operation.

The datapath has built-in support for single cycle CRC

computation and PRS generation of arbitrary width and arbitrary

polynomial. CRC/PRS functions longer than 8 bits may be

implemented in conjunction with PLD logic, or built in chaining

may be use to extend the function into neighboring UDBs.

Figure 7-6. Status and Control Registers

System Bus

7.2.2.6 Input/Output FIFOs

8-bit Status Register

(Read Only)

8-bit Control Register

(Write/Read)

Each datapath contains two four-byte deep FIFOs, which can be

independently configured as an input buffer (system bus writes

to the FIFO, datapath internal reads the FIFO), or an output

buffer (datapath internal writes to the FIFO, the system bus reads

from the FIFO). The FIFOs generate status that are selectable

as datapath outputs and can therefore be driven to the routing,

to interact with sequencers, interrupts, or DMA.

Routing Channel

The bits of the control register, which may be written to by the

system bus, are used to drive into the routing matrix, and thus

provide firmware with the opportunity to control the state of UDB

processing. The status register is read-only and it allows internal

UDB state to be read out onto the system bus directly from

internal routing. This allows firmware to monitor the state of UDB

processing. Each bit of these registers has programmable

connections to the routing matrix and routing connections are

made depending on the requirements of the application.

Figure 7-5. Example FIFO Configurations

System Bus

F0

F1

D0/D1

D0

A0

D1

A1

A0/A1/ALU

F0

A0/A1/ALU

F1

7.2.3.1 Usage Examples

As an example of control input, a bit in the control register can

be allocated as a function enable bit. There are multiple ways to

enable a function. In one method the control bit output would be

routed to the clock control block in one or more UDBs and serve

as a clock enable for the selected UDB blocks. A status example

is a case where a PLD or datapath block generated a condition,

such as a “compare true” condition that is captured and latched

by the status register and then read (and cleared) by CPU

firmware.

F1

System Bus

Dual Capture

TX/RX

Dual Buffer

Document Number: 001-57330 Rev. *G

Page 44 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

7.2.3.2 Clock Generation

An example of this is the 8-bit timer in the upper left corner of the

array. This function only requires one datapath in the UDB, and

therefore the PLD resources may be allocated to another

function. A function such as a Quadrature Decoder may require

more PLD logic than one UDB can supply and in this case can

utilize the unused PLD blocks in the 8-bit Timer UDB.

Programmable resources in the UDB array are generally

homogeneous so functions can be mapped to arbitrary

boundaries in the array.

Each subcomponent block of a UDB including the two PLDs, the

datapath, and Status and Control, has a clock selection and

control block. This promotes a fine granularity with respect to

allocating clocking resources to UDB component blocks and

allows unused UDB resources to be used by other functions for

maximum system efficiency.

7.3 UDB Array Description

Figure 7-8. Function Mapping Example in a Bank of UDBs

Figure 7-7 shows an example of a 16 UDB array. In addition to

the array core, there are a DSI routing interfaces at the top and

bottom of the array. Other interfaces that are not explicitly shown

include the system interfaces for bus and clock distribution. The

UDB array includes multiple horizontal and vertical routing

channels each comprised of 96 wires. The wire connections to

UDBs, at horizontal/vertical intersection and at the DSI interface

are highly permutable providing efficient automatic routing in

PSoC Creator. Additionally the routing allows wire by wire

segmentation along the vertical and horizontal routing to further

increase routing flexibility and capability.

8-Bit

Timer

16-Bit

PWM

Quadrature Decoder

16-Bit PYRS

UDB

HV

A

HV

B

HV

A

HV

B

UDB

8-Bit

UDB

8-Bit SPI

UDB

Figure 7-7. Digital System Interface Structure

Timer

Logic

I2C Slave

UDB

12-Bit SPI

UDB

System Connections

UDB

HV

B

HV

A

HV

B

HV

A

HV

B

HV

A

HV

B

HV

A

UDB

Logic

HV

A

HV

B

HV

A

HV

B

UDB

UART

12-Bit PWM

UDB

7.4 DSI Routing Interface Description

The DSI routing interface is a continuation of the horizontal and

vertical routing channels at the top and bottom of the UDB array

core. It provides general purpose programmable routing

between device peripherals, including UDBs, I/Os, analog

peripherals, interrupts, DMA and fixed function peripherals.

HV

B

HV

A

HV

B

HV

A

UDB

Figure 7-9 illustrates the concept of the digital system

interconnect, which connects the UDB array routing matrix with

other device peripherals. Any digital core or fixed function

peripheral that needs programmable routing is connected to this

interface.

HV

A

HV

B

HV

A

HV

B

Signals in this category include:

System Connections

 Interrupt requests from all digital peripherals in the system.

 DMA requests from all digital peripherals in the system.

 Digital peripheral data signals that need flexible routing to I/Os.

 Digital peripheral data signals that need connections to UDBs.

 Connections to the interrupt and DMA controllers.

 Connection to I/O pins.

7.3.1 UDB Array Programmable Resources

Figure 7-8 shows an example of how functions are mapped into

a bank of 16 UDBs. The primary programmable resources of the

UDB are two PLDs, one datapath and one status/control register.

These resources are allocated independently, because they

have independently selectable clocks, and therefore unused

blocks are allocated to other unrelated functions.

 Connection to analog system digital signals.

Document Number: 001-57330 Rev. *G

Page 45 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

Figure 7-9. Digital System Interconnect

single synchronized (pipelined) and a data input signal has the

option to be double synchronized. The synchronization clock is

the master clock (see Figure 6-1). Normally all inputs from pins

are synchronized as this is required if the CPU interacts with the

signal or any signal derived from it. Asynchronous inputs have

rare uses. An example of this is a feed through of combinational

PLD logic from input pins to output pins.

Timer

Interrupt

DMA

IO Port

Pins

Global

Clocks

CAN

I2C

Counters

Controller

Figure 7-11. I/O Pin Synchronization Routing

Digital System Routing I/F

UDB ARRAY

DO

DI

Digital System Routing I/F

Figure 7-12. I/O Pin Output Connectivity

8 IO Data Output Connections from the

UDB Array Digital System Interface

Global

Clocks

IO Port

Pins

SC/CT

Blocks

EMIF

Del-Sig

DACs

Comparators

Interrupt and DMA routing is very flexible in the CY8C36

programmable architecture. In addition to the numerous fixed

function peripherals that can generate interrupt requests, any

data signal in the UDB array routing can also be used to generate

a request. A single peripheral may generate multiple

independent interrupt requests simplifying system and firmware

design. Figure 7-10 shows the structure of the IDMUX

(Interrupt/DMA Multiplexer).

DO

PIN 0

DO

PIN1

DO

PIN2

DO

PIN3

DO

PIN5

DO

PIN6

DO

PIN7

PIN4

Port i

Figure 7-10. Interrupt and DMA Processing in the IDMUX

Interrupt and DMA Processing in IDMUX

There are four more DSI connections to a given I/O port to

implement dynamic output enable control of pins. This

connectivity gives a range of options, from fully ganged 8-bits

controlled by one signal, to up to four individually controlled pins.

The output enable signal is useful for creating tri-state

bidirectional pins and buses.

Fixed Function IRQs

0

1

Interrupt

Controller

IRQs

2

UDB Array

Figure 7-13. I/O Pin Output Enable Connectivity

Edge

3

Detect

4 IO Control Signal Connections from

UDB Array Digital System Interface

DRQs

DMA termout (IRQs)

0

Fixed Function DRQs

DMA

Controller

1

Edge

2

Detect

7.4.1 I/O Port Routing

There are a total of 20 DSI routes to a typical 8-bit I/O port, 16

for data and four for drive strength control.

OE

PIN 0

OE

PIN1

OE

PIN2

OE

PIN3

OE

PIN4

OE

PIN5

OE

PIN6

OE

PIN7

When an I/O pin is connected to the routing, there are two

primary connections available, an input and an output. In

conjunction with drive strength control, this can implement a

bidirectional I/O pin. A data output signal has the option to be

Port i

Document Number: 001-57330 Rev. *G

Page 46 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

7.5 CAN

The CAN peripheral is a fully functional controller area network (CAN) supporting communication baud rates up to 1 Mbps. The CAN

controller implements the CAN2.0A and CAN2.0B specifications as defined in the Bosch specification and conforms to the

ISO-11898-1 standard. The CAN protocol was originally designed for automotive applications with a focus on a high level of fault

detection. This ensures high communication reliability at a low cost. Because of its success in automotive applications, CAN is used

as a standard communication protocol for motion oriented machine control networks (CANOpen) and factory automation applications

(DeviceNet). The CAN controller features allow the efficient implementation of higher level protocols without affecting the performance

of the microcontroller CPU. Full configuration support is provided in PSoC Creator.

Figure 7-14. CAN Bus System Implementation

CAN Node 1

PSoC

CAN Node 2

CAN Node n

CAN

Drivers

CAN Controller

En

Tx Rx

CAN Transceiver

CAN_H

CAN_L

CAN_H

CAN_L

CAN Bus

7.5.1 CAN Features

 Receive path

 16 receive buffers each with its own message filter

 Enhanced hardware message filter implementation that

covers the ID, IDE, and RTR

 DeviceNet addressing support

 Multiple receive buffers linkable to build a larger receive

message array

 CAN2.0A/B protocol implementation – ISO 11898 compliant

 Standard and extended frames with up to 8 bytes of data per

frame

 Message filter capabilities

 Remote Transmission Request (RTR) support

 Programmable bit rate up to 1 Mbps

 Automatic transmission request (RTR) response handler

 Lost received message notification

 Listen Only mode

 Transmit path

 SW readable error counter and indicator

 Eight transmit buffers

 Programmable transmit priority

 Round robin

 Fixed priority

 Message transmissions abort capability

 Sleep mode: Wake the device from sleep with activity on the

Rx pin

 Supports two or three wire interface to external transceiver (Tx,

Rx, and Enable). The three-wire interface is compatible with

the Philips PHY; the PHY is not included on-chip. The three

wires can be routed to any I/O

7.5.2 Software Tools Support

CAN Controller configuration integrated into PSoC Creator:

 Enhanced interrupt controller

 CAN receive and transmit buffers status

 CAN controller error status including BusOff

 CAN Configuration walkthrough with bit timing analyzer

 Receive filter setup

Document Number: 001-57330 Rev. *G

Page 47 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

Figure 7-15. CAN Controller Block Diagram

TxMessage0

TxReq

TxAbort

TxMessage1

TxReq

TxAbort

Tx Buffer

Status

TxReq

Bit Timing

Pending

Priority

Arbiter

Tx

TxMessage6

TxReq

TxAbort

Tx

CAN

Framer

CRC

Generator

TxInterrupt

Request

(if enabled)

TxMessage7

TxReq

TxAbort

Error Status



Error Active

Error Passive

Bus Off

RTR RxMessages

0-15

Tx Error Counter

Rx Error Counter

RxMessage0

RxMessage1

Acceptance Code 0

Acceptance Mask 0

Acceptance Mask 1

Rx Buffer

Status

RxMessage

Available

Acceptance Code 1

Rx

RxMessage

Handler

CAN

Framer

CRC Check

RxMessage14

RxMessage15

Acceptance Mask 14

Acceptance Mask 15

Acceptance Code 14

Acceptance Code 15

RxInterrupt

Request

(if enabled)

WakeUp

Request

Error Detection

CRC

Form

ACK

Bit Stuffing

Bit Error

Overload

Arbitration

ErrInterrupt

Request

(if enabled)

Document Number: 001-57330 Rev. *G

Page 48 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

7.6 USB

7.7 Timers, Counters, and PWMs

PSoC includes a dedicated Full-Speed (12 Mbps) USB 2.0

transceiver supporting all four USB transfer types: control,

interrupt, bulk, and isochronous. PSoC Creator provides full

configuration support. USB interfaces to hosts through two

dedicated USBIO pins, which are detailed in the “I/O System and

Routing” section on page 33.

The timer/counter/PWM peripheral is a 16-bit dedicated

peripheral providing three of the most common embedded

peripheral features. As almost all embedded systems use some

combination of timers, counters, and PWMs. Four of them have

been included on this PSoC device family. Additional and more

advanced functionality timers, counters, and PWMs can also be

instantiated in UDBs as required. PSoC Creator allows you to

choose the timer, counter, and PWM features that they require.

The tool set utilizes the most optimal resources available.

USB includes the following features:

 Eight unidirectional data endpoints

The timer/counter/PWM peripheral can select from multiple clock

sources, with input and output signals connected through the

DSI routing. DSI routing allows input and output connections to

any device pin and any internal digital signal accessible through

the DSI. Each of the four instances has a compare output,

terminal count output (optional complementary compare output),

and programmable interrupt request line. The

Timer/Counter/PWMs are configurable as free running, one shot,

or Enable input controlled. The peripheral has timer reset and

capture inputs, and a kill input for control of the comparator

outputs. The peripheral supports full 16-bit capture.

 One bidirectional control endpoint 0 (EP0)

 Shared 512-byte buffer for the eight data endpoints

 Dedicated 8-byte buffer for EP0

 Three memory modes

 Manual memory management with no DMA access

 Manual memory management with manual DMA access

 Automatic memory management with automatic DMA

access

 Internal 3.3-V regulator for transceiver

Timer/Counter/PWM features include:

 16-bit Timer/Counter/PWM (down count only)

 Selectable clock source

 Internal 48-MHz main oscillator mode that auto locks to USB

bus clock, requiring no external crystal for USB (USB equipped

parts only)

 PWM comparator (configurable for LT, LTE, EQ, GTE, GT)

 Period reload on start, reset, and terminal count

 Interrupt on terminal count, compare true, or capture

 Dynamic counter reads

 Interrupts on bus and each endpoint event, with device wakeup

 USB reset, suspend, and resume operations

 Bus-powered and self-powered modes

Figure 7-16. USB

 Timer capture mode

 Count while enable signal is asserted mode

 Free run mode

512 X 8

Arbiter

 One Shot mode (stop at end of period)

 Complementary PWM outputs with deadband

 PWM output kill

SRAM

External 22 

D+

Resistors

S I E

(Serial Interface

Engine)

USB

I/O

Figure 7-17. Timer/Counter/PWM

D–

Interrupts

Clock

IRQ

Reset

Timer / Counter /

PWM 16-bit

48 MHz

IMO

TC / Compare!

Compare

Enable

Capture

Kill

Document Number: 001-57330 Rev. *G

Page 49 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

functionality is required, I²C pin connections are limited to the

two special sets of SIO pins.

I²C features include:

2

7.8 I C

The I²C peripheral provides a synchronous two wire interface

designed to interface the PSoC device with a two wire I²C serial

communication bus. It is compatible^[15]with I²C Standard-mode,

Fast-mode, and Fast-mode Plus devices as defined in the NXP

I2C-bus specification and user manual (UM10204). The I2C bus

I/O may be implemented with GPIO or SIO in open-drain modes.

Additional I²C interfaces can be instantiated using Universal

Digital Blocks (UDBs) in PSoC Creator, as required.

 Slave and master, transmitter, and receiver operation

 Byte processing for low CPU overhead

 Interrupt or polling CPU interface

 Support for bus speeds up to 1 Mbps

 7 or 10-bit addressing (10-bit addressing requires firmware

To eliminate the need for excessive CPU intervention and

overhead, I²C specific support is provided for status detection

and generation of framing bits. I²C operates as a slave, a master,

or multimaster (Slave and Master)^.[16]. In slave mode, the unit

always listens for a start condition to begin sending or receiving

data. Master mode supplies the ability to generate the Start and

Stop conditions and initiate transactions. Multimaster mode

provides clock synchronization and arbitration to allow multiple

masters on the same bus. If Master mode is enabled and Slave

mode is not enabled, the block does not generate interrupts on

externally generated Start conditions. I²C interfaces through DSI

routing and allows direct connections to any GPIO or SIO pins.

support)

 SMBus operation (through firmware support - SMBus

supported in hardware in UDBs)

 7-bit hardware address compare

 Wake from low-power modes on address match

 Glitch filtering (active and alternate-active modes only)

Data transfers follow the format shown in Figure 7-18. After the

START condition (S), a slave address is sent. This address is 7

bits long followed by an eighth bit which is a data direction bit

(R/W) - a 'zero' indicates a transmission (WRITE), a 'one'

indicates a request for data (READ). A data transfer is always

terminated by a STOP condition (P) generated by the master.

I²C provides hardware address detect of a 7-bit address without

CPU intervention. Additionally the device can wake from

low-power modes on a 7-bit hardware address match. If wakeup

Figure 7-18. I²C Complete Transfer Timing

SDA

SCL

8

9

1 - 7

8

9

1 - 7

8

9

1 - 7

START

Condition

STOP

Condition

ADDRESS

R/W

ACK

DATA

ACK

DATA

ACK

Notes

15. The I²C peripheral is non-compliant with the NXP I²C specification in the following areas: analog glitch filter, I/O V_OL/I_OL, I/O hysteresis. The I²C Block has a digital

glitch filter (not available in sleep mode). The Fast-mode minimum fall-time specification can be met by setting the I/Os to slow speed mode. See the I/O Electrical

Specifications in “Inputs and Outputs” section on page 74 for details.

16. Fixed-block I²C does not support undefined bus conditions, nor does it support Repeated Start in Slave mode. These conditions should be avoided, or the UDB-based

I²C component should be used instead.

Document Number: 001-57330 Rev. *G

Page 50 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

The typical use model is for data to be supplied to the DFB over

the system bus from another on-chip system data source such

as an ADC. The data typically passes through main memory or

is directly transferred from another chip resource through DMA.

The DFB processes this data and passes the result to another

on chip resource such as a DAC or main memory through DMA

on the system bus.

7.9 Digital Filter Block

Some devices in the CY8C36 family of devices have a dedicated

HW accelerator block used for digital filtering. The DFB has a

dedicated multiplier and accumulator that calculates a 24-bit by

24-bit multiply accumulate in one bus clock cycle. This enables

the mapping of a direct form FIR filter that approaches a

computation rate of one FIR tap for each clock cycle. The MCU

can implement any of the functions performed by this block, but

at a slower rate that consumes MCU bandwidth.

Data movement in or out of the DFB is typically controlled by the

system DMA controller but can be moved directly by the MCU.

The heart of the DFB is a datapath (DP), which is the numerical

calculation unit of the DFB. The DP is a 24-bit fixed-point

numerical processor containing a 48-bit multiply and accumulate

function (MAC), a multi-function ALU, sample and coefficient

data RAMs as well as data routing, shifting, holding and rounding

functions.

8. Analog Subsystem

The analog programmable system creates application specific

combinations of both standard and advanced analog signal

processing blocks. These blocks are then interconnected to

each other and also to any pin on the device, providing a high

level of design flexibility and IP security. The features of the

analog subsystem are outlined here to provide an overview of

capabilities and architecture.

In the MAC, two 24-bit values can be multiplied and the result

added to the 48-bit accumulator in each bus clock cycle. The

MAC is the only portion of the DP that is wider than 24 bits. All

results from the MAC are passed on to the ALU as 24-bit values

representing the high-order 24 bits in the accumulator shifted by

one (bits 46:23). The MAC assumes an implied binary point after

the most significant bit.

 Flexible, configurable analog routing architecture provided by

analog globals, analog mux bus, and analog local buses.

 High resolution delta-sigma ADC.

The DP also contains an optimized ALU that supports add,

subtract, comparison, threshold, absolute value, squelch,

saturation, and other functions. The DP unit is controlled by

seven control fields totaling 18 bits coming from the DFB

Controller. For more information see the TRM.

 Up to four 8-bit DACs that provide either voltage or current

output.

 Fourcomparatorswithoptional connectiontoconfigurableLUT

outputs.

The PSoC Creator interface provides a wizard to implement FIR

and IIR digital filters with coefficients for LPF, BPF, HPF, Notch

and arbitrary shape filters. 64 pairs of data and coefficients are

stored. This enables a 64 tap FIR filter or up to 4 16 tap filters of

either FIR or IIR formulation.

 Up to four configurable switched capacitor/continuous time

(SC/CT) blocks for functions that include opamp, unity gain

buffer, programmablegainamplifier, transimpedanceamplifier,

and mixer.

 Up to four opamps for internal use and connection to GPIO that

can be used as high current output buffers.

Figure 7-19. DFB Application Diagram (pwr/gnd not shown)

 CapSense subsystem to enable capacitive touch sensing.

BUSCLK

read_data

write_data

 Precision reference for generating an accurate analog voltage

for internal analog blocks.

Data

Source

(PHUB)

System

Bus

addr

Digital

Routing

Digital Filter

Block

Data

Dest

(PHUB)

DMA

Request

DMA

CTRL

Document Number: 001-57330 Rev. *G

Page 51 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

Figure 8-1. Analog Subsystem Block Diagram

DAC

Precision

Reference

A

N

A

L

O

G

A

N

A

L

O

G

SC/CT Block

GPIO

Port

GPIO

Port

SC/CT Block

R

O

U

T

I

R

O

U

T

I

Comparators

CMP CMP

N

G

N

G

CMP

CapSense Subsystem

Config&

Status

Registers

Analog

Interface

AHB

PHUB

CPU

DSI

Array

Clock

Distribution

Decimator

The PSoC Creator software program provides a user friendly

interface to configure the analog connections between the GPIO

and various analog resources and connections from one analog

resource to another. PSoC Creator also provides component

libraries that allow you to configure the various analog blocks to

perform application specific functions (PGA, transimpedance

amplifier, voltage DAC, current DAC, and so on). The tool also

generates API interface libraries that allow you to write firmware

that allows the communication between the analog peripheral

and CPU/Memory.

8.1.1 Features

 Flexible, configurable analog routing architecture

 16 analog globals (AG) and two analog mux buses

(AMUXBUS) to connect GPIOs and the analog blocks

 Each GPIO is connected to one analog global and one analog

mux bus

 Eight analog local buses (abus) to route signals between the

different analog blocks

8.1 Analog Routing

 Multiplexers and switches for input and output selection of the

analog blocks

The CY8C36 family of devices has a flexible analog routing

architecture that provides the capability to connect GPIOs and

different analog blocks, and also route signals between different

analog blocks. One of the strong points of this flexible routing

architecture is that it allows dynamic routing of input and output

connections to the different analog blocks.

8.1.2 Functional Description

Analog globals (AGs) and analog mux buses (AMUXBUS)

provide analog connectivity between GPIOs and the various

analog blocks. There are 16 AGs in the CY8C36 family. The

analog routing architecture is divided into four quadrants as

shown in Figure 8-2. Each quadrant has four analog globals

(AGL[0..3], AGL[4..7], AGR[0..3], AGR[4..7]). Each GPIO is

connected to the corresponding AG through an analog switch.

The analog mux bus is a shared routing resource that connects

to every GPIO through an analog switch. There are two

AMUXBUS routes in CY8C36, one in the left half (AMUXBUSL)

and one in the right half (AMUXBUSR), as shown in Figure 8-2

on page 53.

For information on how to make pin selections for optimal analog

routing, refer to the application note, AN58304 - PSoC® 3 and

PSoC® 5 - Pin Selection for Analog Designs.

Document Number: 001-57330 Rev. *G

Page 52 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

Figure 8-2. CY8C36 Analog Interconnect

*

swinp

*

swinn

*

AMUXBUSR

AMUXBUSL

AGL[4]

AGR[4]

AGR[5]

AGR[6]

AGR[7]

AGL[5]

AGL[6]

AGL[7]

ExVrefL

ExVrefL1

ExVrefL2

swinp

swinn

GPIO

P3[5]

GPIO

P3[4]

GPIO

P3[3]

GPIO

P3[2]

GPIO

P3[1]

GPIO

P3[0]

GPXT

opamp3

swfol

opamp1

swfol

opamp0

swfol

opamp2

swfol

swinp

swinn

0123

3210

01234567

76543210

GPIO

P0[4]

GPIO

P0[5]

GPIO

P0[6]

GPIO

swinp

swinn

LPF

swout

in0

in1

abuf_vref_int

(1.024V)

abuf_vref_int

(1.024V)

i0

i2

*

ExVrefR

swin

out0

out1

comp0

comp1

*

+

-

+

-

P0[7]

i3

i1

COMPARATOR

cmp0_vref

(1.024V)

cmp0_vref

(1.024V)

+

-

+

-

GPIO

P4[2]

GPIO

P4[3]

GPIO

cmp_muxvn[1:0]

vref_cmp1

comp2

comp3

cmp1_vref

(0.256V)

*

bg_vda_res_en

P15[1]

GPXT

P15[0]

bg_vda_swabusl0

Vdda

Vdda/2

out

ref

in

out

ref

in

refbuf_vref1 (1.024V)

CAPSENSE

refbufl

refbuf_vref1 (1.024V)

refbuf_vref2 (1.2V)

*

refbuf_vref2 (1.2V)

refbufr

refsel[1:0]

P4[4]

GPIO

P4[5]

GPIO

P4[6]

GPIO

P4[7]

vssa

Vssa

sc0

Vin

Vref

out

sc1

Vin

Vref

sc1_bgref

(1.024V)

sc0_bgref

(1.024V)

*

out

sc2_bgref

(1.024V)

sc3_bgref

(1.024V)

Vccd

SC/CT

Vin

Vref

out

sc2

Vin

Vref

out

sc3

*

Vssd

*

Vccd

Vddd

*

Vssd

ABUSL0

ABUSL1

ABUSL2

ABUSL3

ABUSR0

ABUSR1

ABUSR2

ABUSR3

*

Vddd

GPIO

P6[0]

GPIO

P6[1]

GPIO

P6[2]

GPIO

P6[3]

GPIO

P15[4]

GPIO

v0

i0

v1

DAC1

i1

USB IO

DAC0

*

P15[7]

VIDAC

USB IO

v2

i2

v3

DAC3

i3

*

DAC2

P15[6]

GPIO

dac_vref (0.256V)

vcmsel[1:0]

vssd

P5[7]

GPIO

P5[6]

GPIO

P5[5]

GPIO

P5[4]

SIO

+

DSM0

DSM

refs

-

vssa

dsm0_vcm_vref1 (0.8V)

dsm0_vcm_vref2 (0.7V)

vcm

qtz_ref

vref_vss_ext

dsm0_qtz_vref2 (1.2V)

dsm0_qtz_vref1 (1.024V)

Vdda/3

Vdda/4

ExVrefL

ExVrefR

P15[5]

GPIO

P2[0]

GPIO

P2[1]

GPIO

P2[2]

GPIO

P12[7]

SIO

P12[6]

GPIO

AMUXBUSR

AMUXBUSL

76543210

0123

ANALOG

BUS

01234567

3210

ANALOG

ANALOG ANALOG

GLOBALS

BUS

GLOBALS

*

P1[7]

GPIO

P1[6]

*

P2[3]

GPIO

P2[4]

*

VBE

TS

ADC

*

:

Vss ref

Vddio2

LPF

AGL[3]

AGL[2]

AGR[3]

AGR[2]

AGR[1]

AGL[1]

AGL[0]

AGR[0]

AMUXBUSR

AMUXBUSL

*

Mux Group

*

Switch Group

Connection

*

Switch Resistance

Notes:

Small ( ~870 Ohms )

Large ( ~200 Ohms)

* Denotes pins on all packages

LCD signals are not shown.

Rev #60

10-Feb-2012

To preserve detail of this figure, this figure is best viewed with a PDF display program or printed on a 11" × 17" paper.

Document Number: 001-57330 Rev. *G

Page 53 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

Analog local buses (abus) are routing resources located within

the analog subsystem and are used to route signals between

different analog blocks. There are eight abus routes in CY8C36,

four in the left half (abusl [0:3]) and four in the right half (abusr

[0:3]) as shown in Figure 8-2. Using the abus saves the analog

globals and analog mux buses from being used for

interconnecting the analog blocks.

through the input buffer. The delta-sigma modulator performs the

actual analog to digital conversion. The modulator over-samples

the input and generates a serial data stream output. This high

speed data stream is not useful for most applications without

some type of post processing, and so is passed to the decimator

through the Analog Interface block. The decimator converts the

high speed serial data stream into parallel ADC results. The

modulator/decimator frequency response is [(sin x)/x]⁴.

Multiplexers and switches exist on the various buses to direct

signals into and out of the analog blocks. A multiplexer can have

only one connection on at a time, whereas a switch can have

multiple connections on simultaneously. In Figure 8-2,

multiplexers are indicated by grayed ovals and switches are

indicated by transparent ovals.

Figure 8-4. Delta-sigma ADC Block Diagram

Positive

Input Mux

Delta

Sigma

Modulator

Input

Buffer

12 to 20 Bit

Result

Decimator

(Analog Routing)

8.2 Delta-sigma ADC

Negative

EOC

Input Mux

The CY8C36 device contains one delta-sigma ADC. This ADC

offers differential input, high resolution and excellent linearity,

making it a good ADC choice for both audio signal processing

and measurement applications. The converter can be configured

to output 12-bit resolution at data rates of up to 192 ksps. At a

fixed clock rate, resolution can be traded for faster data rates as

shown in Table 8-1 and Figure 8-3.

SOC

Resolution and sample rate are controlled by the Decimator.

Data is pipelined in the decimator; the output is a function of the

last four samples. When the input multiplexer is switched, the

output data is not valid until after the fourth sample after the

switch.

Table 8-1. Delta-sigma ADC Performance

MaximumSampleRate

8.2.2 Operational Modes

Bits

SINAD (dB)

(sps)

192 k

384 k

The ADC can be configured by the user to operate in one of four

modes: Single Sample, Multi Sample, Continuous, or Multi

Sample (Turbo). All four modes are started by either a write to

the start bit in a control register or an assertion of the Start of

Conversion (SoC) signal. When the conversion is complete, a

status bit is set and the output signal End of Conversion (EoC)

asserts high and remains high until the value is read by either the

DMA controller or the CPU.

12

8

66

43

Figure8-3. Delta-sigmaADCSampleRates, Range=±1.024 V

1000000

8.2.2.1 Single Sample

100000

10000

1000

100

In Single Sample mode, the ADC performs one sample

conversion on a trigger. In this mode, the ADC stays in standby

state waiting for the SoC signal to be asserted. When SoC is

signaled the ADC performs four successive conversions. The

first three conversions prime the decimator. The ADC result is

valid and available after the fourth conversion, at which time the

EoC signal is generated. To detect the end of conversion, the

system may poll a control register for status or configure the

external EoC signal to generate an interrupt or invoke a DMA

request. When the transfer is done the ADC reenters the standby

state where it stays until another SoC event.

10

1

6

8

10

12

14

16

18

20

22

8.2.2.2 Continuous

Resolution, bits

Continuous

Multi-Sample

Multi-SampleTurbo

Continuous sample mode is used to take multiple successive

samples of a single input signal. Multiplexing multiple inputs

should not be done with this mode. There is a latency of three

conversion times before the first conversion result is available.

This is the time required to prime the decimator. After the first

result, successive conversions are available at the selected

sample rate.

8.2.1 Functional Description

The ADC connects and configures three basic components,

input buffer, delta-sigma modulator, and decimator. The basic

block diagram is shown in Figure 8-4. The signal from the input

muxes is delivered to the delta-sigma modulator either directly or

Document Number: 001-57330 Rev. *G

Page 54 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

8.2.2.3 Multi Sample

8.3 Comparators

Multi sample mode is similar to continuous mode except that the

ADC is reset between samples. This mode is useful when the

input is switched between multiple signals. The decimator is

re-primed between each sample so that previous samples do not

affect the current conversion. Upon completion of a sample, the

next sample is automatically initiated. The results can be

transferred using either firmware polling, interrupt, or DMA.

The CY8C36 family of devices contains four comparators in a

device. Comparators have these features:

 Input offset factory trimmed to less than 5 mV

 Rail-to-rail common mode input range (VSSA to VDDA)

 Speed and power can be traded off by using one of three

modes: fast, slow, or ultra low-power

 Comparator outputs can be routed to lookup tables to perform

simple logic functions and then can also be routed to digital

blocks

8.2.3 Start of Conversion Input

The SoC signal is used to start an ADC conversion. A digital

clock or UDB output can be used to drive this input. It can be

used when the sampling period must be longer than the ADC

conversion time or when the ADC must be synchronized to other

hardware. This signal is optional and does not need to be

connected if ADC is running in a continuous mode.

 The positive input ofthe comparators may be optionally passed

through a low pass filter. Two filters are provided

 Comparator inputs can be connections to GPIO, DAC outputs

and SC block outputs

8.2.4 End of Conversion Output

8.3.1 Input and Output Interface

The EoC signal goes high at the end of each ADC conversion.

This signal may be used to trigger either an interrupt or DMA

request.

The positive and negative inputs to the comparators come from

the analog global buses, the analog mux line, the analog local

bus and precision reference through multiplexers. The output

from each comparator could be routed to any of the two input

LUTs. The output of that LUT is routed to the UDB DSI.

Figure 8-5. Analog Comparator

ANAIF

From

Analog

Routing

+

comp0

_

+

_

From

Analog

Routing

comp1

From

Analog

Routing

+

comp3

_

+

From

Analog

Routing

comp2

_

4

LUT0

LUT1

LUT2

LUT3

UDBs

Document Number: 001-57330 Rev. *G

Page 55 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

8.3.2 LUT

Figure 8-7. Opamp Configurations

a) Voltage Follower

The CY8C36 family of devices contains four LUTs. The LUT is a

two input, one output lookup table that is driven by any one or

two of the comparators in the chip. The output of any LUT is

routed to the digital system interface of the UDB array. From the

digital system interface of the UDB array, these signals can be

connected to UDBs, DMA controller, I/O, or the interrupt

controller.

Vout to Pin

Opamp

Vin

The LUT control word written to a register sets the logic function

on the output. The available LUT functions and the associated

control word is shown in Table 8-2.

b) External Uncommitted

Opamp

Table 8-2. LUT Function vs. Program Word and Inputs

Vout to GPIO

Opamp

Control Word

0000b

0001b

0010b

0011b

0100b

0101b

0110b

0111b

Output (A and B are LUT inputs)

FALSE (‘0’)

A AND B

Vp to GPIO

Vn to GPIO

A AND (NOT B)

A

(NOT A) AND B

B

c) Internal Uncommitted

Opamp

A XOR B

Vn

A OR B

To Internal Signals

1000b

1001b

1010b

1011b

1100b

1101b

1110b

A NOR B

Vout to Pin

GPIO Pin

Opamp

A XNOR B

NOT B

Vp

A OR (NOT B)

NOT A

The opamp has three speed modes, slow, medium, and fast. The

slow mode consumes the least amount of quiescent power and

the fast mode consumes the most power. The inputs are able to

swing rail-to-rail. The output swing is capable of rail-to-rail

operation at low current output, within 50 mV of the rails. When

driving high current loads (about 25 mA) the output voltage may

only get within 500 mV of the rails.

(NOT A) OR B

A NAND B

TRUE (‘1’)

1111b

8.4 Opamps

The CY8C36 family of devices contain up to four general

purpose opamps in a device.

8.5 Programmable SC/CT Blocks

Figure 8-6. Opamp

The CY8C36 family of devices contains up to four switched

capacitor/continuous time (SC/CT) blocks in a device. Each

switched capacitor/continuous time block is built around a single

rail-to-rail high bandwidth opamp.

GPIO

Analog

Global Bus

Switched capacitor is a circuit design technique that uses

capacitors plus switches instead of resistors to create analog

functions. These circuits work by moving charge between

capacitors by opening and closing different switches.

Nonoverlapping in phase clock signals control the switches, so

that not all switches are ON simultaneously.

Opamp

Analog

Global Bus

GPIO

VREF

Analog

Internal Bus

=

Analog Switch

GPIO

The PSoC Creator tool offers a user friendly interface, which

allows you to easily program the SC/CT blocks. Switch control

and clock phase control configuration is done by PSoC Creator

so users only need to determine the application use parameters

such as gain, amplifier polarity, V_REFconnection, and so on.

The opamp is uncommitted and can be configured as a gain

stage or voltage follower, or output buffer on external or internal

signals.

See Figure 8-7. In any configuration, the input and output signals

can all be connected to the internal global signals and monitored

with an ADC, or comparator. The configurations are

The same opamps and block interfaces are also connectable to

an array of resistors which allows the construction of a variety of

continuous time functions.

implemented with switches between the signals and GPIO pins.

Document Number: 001-57330 Rev. *G

Page 56 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

The opamp and resistor array is programmable to perform

various analog functions including

The PGA is used in applications where the input signal may not

be large enough to achieve the desired resolution in the ADC, or

dynamic range of another SC/CT block such as a mixer. The gain

is adjustable at runtime, including changing the gain of the PGA

prior to each ADC sample.

 Naked operational amplifier – Continuous mode

 Unity-gain buffer – Continuous mode

 PGA – Continuous mode

8.5.4 TIA

 Transimpedance amplifier (TIA) – Continuous mode

 Up/down mixer – Continuous mode

The Transimpedance Amplifier (TIA) converts an internal or

external current to an output voltage. The TIA uses an internal

feedback resistor in a continuous time configuration to convert

input current to output voltage. For an input current I_in, the output

voltage is V_REF- I_inx R_fb, where V_REFis the value placed on the

non inverting input. The feedback resistor Rfb is programmable

between 20 K and 1 M through a configuration register.

Table 8-4 shows the possible values of Rfb and associated

configuration settings.

 Sample and hold mixer (NRZ S/H) – Switched cap mode

 First order analog to digital modulator – Switched cap mode

8.5.1 Naked Opamp

The Naked Opamp presents both inputs and the output for

connection to internal or external signals. The opamp has a unity

gain bandwidth greater than 6.0 MHz and output drive current up

to 650 µA. This is sufficient for buffering internal signals (such as

DAC outputs) and driving external loads greater than 7.5 kohms.

Table 8-4. Feedback Resistor Settings

Configuration Word

Nominal R_fb(K)

8.5.2 Unity Gain

000b

001b

010b

011b

100b

101b

110b

111b

20

30

The Unity Gain buffer is a Naked Opamp with the output directly

connected to the inverting input for a gain of 1.00. It has a –3 dB

bandwidth greater than 6.0 MHz.

40

60

8.5.3 PGA

120

250

500

1000

The PGA amplifies an external or internal signal. The PGA can

be configured to operate in inverting mode or noninverting mode.

The PGA function may be configured for both positive and

negative gains as high as 50 and 49 respectively. The gain is

adjusted by changing the values of R1 and R2 as illustrated in

Figure 8-8. The schematic in Figure 8-8 shows the configuration

and possible resistor settings for the PGA. The gain is switched

from inverting and non inverting by changing the shared select

value of the both the input muxes. The bandwidth for each gain

case is listed in Table 8-3.

Figure 8-9. Continuous Time TIA Schematic

R

fb

Table 8-3. Bandwidth

I

in

Gain

1

Bandwidth

5.5 MHz

340 kHz

220 kHz

215 kHz

V

out

V

ref

24

48

50

The TIA configuration is used for applications where an external

sensor's output is current as a function of some type of stimulus

such as temperature, light, magnetic flux etc. In a common

application, the voltage DAC output can be connected to the

Figure 8-8. PGA Resistor Settings

V

_REFTIA input to allow calibration of the external sensor bias

R1

R2

V_in

0

current by adjusting the voltage DAC output voltage.

1

V_ref

8.6 LCD Direct Drive

20k or 40k

20k to 980k

The PSoC LCD driver system is a highly configurable peripheral

designed to allow PSoC to directly drive a broad range of LCD

glass. All voltages are generated on chip, eliminating the need

for external components. With a high multiplex ratio of up to 1/16,

the CY8C36 family LCD driver system can drive a maximum of

736 segments. The PSoC LCD driver module was also designed

with the conservative power budget of portable devices in mind,

enabling different LCD drive modes and power down modes to

conserve power.

S

V_ref

V_in

0

1

Document Number: 001-57330 Rev. *G

Page 57 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

PSoC Creator provides an LCD segment drive component. The

component wizard provides easy and flexible configuration of

LCD resources. You can specify pins for segments and

commons along with other options. The software configures the

device to meet the required specifications. This is possible

because of the programmability inherent to PSoC devices.

8.6.1 LCD Segment Pin Driver

Each GPIO pin contains an LCD driver circuit. The LCD driver

buffers the appropriate output of the LCD DAC to directly drive

the glass of the LCD. A register setting determines whether the

pin is a common or segment. The pin’s LCD driver then selects

one of the six bias voltages to drive the I/O pin, as appropriate

for the display data.

Key features of the PSoC LCD segment system are:

 LCD panel direct driving

8.6.2 Display Data Flow

 Type A (standard) and Type B (low-power) waveform support

The LCD segment driver system reads display data and

generates the proper output voltages to the LCD glass to

produce the desired image. Display data resides in a memory

buffer in the system SRAM. Each time you need to change the

common and segment driver voltages, the next set of pixel data

moves from the memory buffer into the Port Data Registers

through the DMA.

 Wide operating voltage range support (2 V to 5 V) for LCD

panels

 Static, 1/2, 1/3, 1/4, 1/5 bias voltage levels

 Internal biasvoltage generationthrough internal resistorladder

 Up to 62 total common and segment outputs

8.6.3 UDB and LCD Segment Control

 Up to 1/16 multiplex for a maximum of 16 backplane/common

outputs

A UDB is configured to generate the global LCD control signals

and clocking. This set of signals is routed to each LCD pin driver

through a set of dedicated LCD global routing channels. In

addition to generating the global LCD control signals, the UDB

also produces a DMA request to initiate the transfer of the next

frame of LCD data.

 Up to 62 front plane/segment outputs for direct drive

 Drives upto 736 total segments (16 backplane× 46 front plane)

 Up to 64 levels of software controlled contrast

8.6.4 LCD DAC

 Ability to move display data from memory buffer to LCD driver

through DMA (without CPU intervention)

The LCD DAC generates the contrast control and bias voltage

for the LCD system. The LCD DAC produces up to five LCD drive

voltages plus ground, based on the selected bias ratio. The bias

voltages are driven out to GPIO pins on a dedicated LCD bias

bus, as required.

 Adjustable LCD refresh rate from 10 Hz to 150 Hz

 Ability to invert LCD display for negative image

 Three LCD driver drive modes, allowing power optimization

Figure 8-10. LCD System

8.7 CapSense

The CapSense system provides a versatile and efficient means

for measuring capacitance in applications such as touch sense

buttons, sliders, proximity detection, etc. The CapSense system

uses a configuration of system resources, including a few

hardware functions primarily targeted for CapSense. Specific

resource usage is detailed in the CapSense component in PSoC

Creator.

LCD

Global

DAC

Clock

UDB

A capacitive sensing method using a Delta-sigma Modulator

(CSD) is used. It provides capacitance sensing using a switched

capacitor technique with a delta-sigma modulator to convert the

sensing current to a digital code.

LCD Driver

Block

Display

DMA

RAM

8.8 Temp Sensor

Die temperature is used to establish programming parameters

for writing flash. Die temperature is measured using a dedicated

sensor based on a forward biased transistor. The temperature

sensor has its own auxiliary ADC.

PHUB

Document Number: 001-57330 Rev. *G

Page 58 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

 High and low speed / power modes

8.9 DAC

The CY8C36 parts contain up to four Digital to Analog

Convertors (DACs). Each DAC is 8-bit and can be configured for

either voltage or current output. The DACs support CapSense,

power supply regulation, and waveform generation. Each DAC

has the following features:

 8 Msps conversion rate for current output

 1 Msps conversion rate for voltage output

 Monotonic in nature

 Data and strobe inputs can be provided by the CPU or DMA,

or routed directly from the DSI

 Adjustable voltage or current output in 255 steps

 Programmable step size (range selection)

 Dedicated low-resistance output pin for high-current mode

 Eight bits of calibration to correct ± 25 percent of gain error

 Source and sink option for current output

Figure 8-11. DAC Block Diagram

I _sourceRange

1x,8x, 64x

Vout

Reference

Source

Scaler

Iout

R

3R

I _sinkRange

1x,8x, 64x

8.9.1 Current DAC

Continuous time up and down mixing works for applications with

input signals and local oscillator frequencies up to 1 MHz.

The current DAC (IDAC) can be configured for the ranges 0 to

31.875 µA, 0 to 255 µA, and 0 to 2.04 mA. The IDAC can be

configured to source or sink current.

Figure 8-12. Mixer Configuration

C2 = 1.7 pF

8.9.2 Voltage DAC

C1 = 850 fF

For the voltage DAC (VDAC), the current DAC output is routed

through resistors. The two ranges available for the VDAC are 0

to 1.02 V and 0 to 4.08 V. In voltage mode any load connected

to the output of a DAC should be purely capacitive (the output of

the VDAC is not buffered).

R

^mix0 20k or 40k

sc_clk

R^mix0 20k or 40k

Vin

8.10 Up/Down Mixer

Vout

0

1

In continuous time mode, the SC/CT block components are used

to build an up or down mixer. Any mixing application contains an

input signal frequency and a local oscillator frequency. The

polarity of the clock, Fclk, switches the amplifier between

inverting or noninverting gain. The output is the product of the

input and the switching function from the local oscillator, with

frequency components at the local oscillator plus and minus the

signal frequency (Fclk + Fin and Fclk – Fin) and reduced-level

frequency components at odd integer multiples of the local

oscillator frequency. The local oscillator frequency is provided by

the selected clock source for the mixer.

Vref

sc_clk

8.11 Sample and Hold

The main application for a sample and hold, is to hold a value

stable while an ADC is performing a conversion. Some

applications require multiple signals to be sampled

simultaneously, such as for power calculations (V and I).

Document Number: 001-57330 Rev. *G

Page 59 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

Figure 8-13. Sample and Hold Topology

(1 and 2 are opposite phases of a clock)

device. It does not require special interfaces, debugging pods,

simulators, or emulators. Only the standard programming

connections are required to fully support debug.

The PSoC Creator IDE software provides fully integrated

programming and debug support for PSoC devices. The low cost

MiniProg3 programmer and debugger is designed to provide full

programming and debug support of PSoC devices in conjunction

with the PSoC Creator IDE. PSoC JTAG, SWD, and SWV

interfaces are fully compatible with industry standard third party

tools.

₁

 ₂

₁

C₁

C₂

V ⁱ

V_ref

n

V_out

 ₁

₂

²

All DOC circuits are disabled by default and can only be enabled

in firmware. If not enabled, the only way to reenable them is to

erase the entire device, clear flash protection, and reprogram the

device with new firmware that enables DOC. Disabling DOC

features, robust flash protection, and hiding custom analog and

digital functionality inside the PSoC device provide a level of

security not possible with multichip application solutions.

Additionally, all device interfaces can be permanently disabled

(Device Security) for applications concerned about phishing

attacks due to a maliciously reprogrammed device. Permanently

disabling interfaces is not recommended in most applications

because you cannot access the device later. Because all

programming, debug, and test interfaces are disabled when

device security is enabled, PSoCs with Device Security enabled

may not be returned for failure analysis.

¹

₂

₁

₂

₁

²

V _ref

V

ref

C₃

C₄

8.11.1 Down Mixer

The SC/CT block can be used as a mixer to down convert an

input signal. This circuit is a high bandwidth passive sample

network that can sample input signals up to 14 MHz. This

sampled value is then held using the opamp with a maximum

clock rate of 4 MHz. The output frequency is at the difference

between the input frequency and the highest integer multiple of

the Local Oscillator that is less than the input.

Table 9-1. Debug Configurations

Debug and Trace Configuration

GPIO Pins Used

8.11.2 First Order Modulator – SC Mode

All debug and trace disabled

0

A first order modulator is constructed by placing the SC/CT block

in an integrator mode and using a comparator to provide a 1-bit

feedback to the input. Depending on this bit, a reference voltage

is either subtracted or added to the input signal. The block output

is the output of the comparator and not the integrator in the

modulator case. The signal is downshifted and buffered and then

processed by a decimator to make a delta-sigma converter or a

counter to make an incremental converter. The accuracy of the

sampled data from the first-order modulator is determined from

several factors.

JTAG

4 or 5

SWD

2

1

3

SWV

SWD + SWV

9.1 JTAG Interface

The IEEE 1149.1 compliant JTAG interface exists on four or five

pins (the nTRST pin is optional). The JTAG interface is used for

programming the flash memory, debugging, I/O scan chains, and

JTAG device chaining.

The main application for this modulator is for a low-frequency

ADC with high accuracy. Applications include strain gauges,

thermocouples, precision voltage, and current measurement.

PSoC 3 has certain timing requirements to be met for entering

programming mode through the JTAG interface. Due to these

timing requirements, not all standard JTAG programmers, or

standard JTAG file formats such as SVF or STAPL, can support

PSoC 3 programming. The list of programmers that support

PSoC 3 programming is available at

9. Programming, Debug Interfaces,

Resources

PSoC devices include extensive support for programming,

testing, debugging, and tracing both hardware and firmware.

Three interfaces are available: JTAG, SWD, and SWV. JTAG and

SWD support all programming and debug features of the device.

JTAG also supports standard JTAG scan chains for board level

test and chaining multiple JTAG devices to a single JTAG

connection.

http://www.cypress.com/go/programming.

The JTAG clock frequency can be up to 14 MHz, or 1/3 of the

CPU clock frequency for 8 and 16-bit transfers, or 1/5 of the CPU

clock frequency for 32-bit transfers. By default, the JTAG pins are

enabled on new devices but the JTAG interface can be disabled,

allowing these pins to be used as GPIO instead.

For more information on PSoC 3 Programming, refer to the

PSoC^®3 Device Programming Specifications.

Complete Debug on Chip (DoC) functionality enables full device

debugging in the final system using the standard production

Document Number: 001-57330 Rev. *G

Page 60 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

Figure 9-1. JTAG Interface Connections between PSoC 3 and Programmer

V_DD

Host Programmer

PSoC 3

1, 2, 3, 4

V_DD

V

_DDD, V_DDA, V_DDIO0, V_DDIO1, V_DDIO2, V_DDIO3

TCK (P1[1]

TCK

5

TMS

TMS (P1[0])

TDO

TDI

TDI (P1[4])

TDO (P1[3])

nTRST (P1[5]) ⁶

nTRST ⁶

XRES or P1[2] ^{4, 7}

V_SSD, V_SSA

XRES

GND

¹The voltage levels of Host Programmer and the PSoC 3 voltage domains involved in Programming should be same. The

Port 1 JTAG pins, XRES pin (XRES_N or P1[2]) are powered by V_DDIO1. So, V_DDIO1of PSoC 3 should be at same voltage

level as host V_DD. Rest of PSoC 3 voltage domains ( V_DDD, V_DDA, V_DDIO0, V_DDIO2, V_DDIO3) need not be at the same voltage level as

host Programmer.

2

Vdda must be greater than or equal to all other power supplies (Vddd, Vddio’s) in PSoC 3.

3

For Power cycle mode Programming, XRES pin is not required. But the Host programmer must have

the capability to toggle power (Vddd, Vdda, All Vddio’s) to PSoC 3. This may typically require external

interface circuitry to toggle power which will depend on the programming setup. The power supplies can

be brought up in any sequence, however, once stable, VDDA must be greater than or equal to all other

supplies.

4

For JTAG Programming, Device reset can also be done without connecting to the XRES pin or Power cycle mode by

using the TMS,TCK,TDI, TDO pins of PSoC 3, and writing to a specific register. But this requires that the DPS setting in

NVL is not equal to “Debug Ports Disabled”.

5

By default, PSoC 3 is configured for 4-wire JTAG mode unless user changes the DPS setting. So the TMS pin is

unidirectional. But if the DPS setting is changed to non-JTAG mode, the TMS pin in JTAG is bi-directional as the SWD

Protocol has to be used for acquiring the PSoC 3 device initially. After switching from SWD to JTAG mode, the TMS pin

will be uni-directional. In such a case, unidirectional buffer should not be used on TMS line.

6

nTRST JTAG pin (P1[5]) cannot be used to reset the JTAG TAP controlller during first time programming of PSoC 3 as

the default setting is 4-wire JTAG (nTRST disabled). Use the TMS, TCK pins to do a reset of JTAG TAP controller.

7

If XRES pin is used by host, P1[2] will be configured as XRES by default only for 48-pin devices (without dedicated XRES

pin). For devices with dedicated XRES pin, P1[2] is GPIO pin by default. So use P1[2] as Reset pin only for 48-pin

devices, but use dedicated XRES pin for rest of devices.

Document Number: 001-57330 Rev. *G

Page 61 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

SWD can be enabled on only one of the pin pairs at a time. This

only happens if, within 8 µs (key window) after reset, that pin pair

(JTAG or USB) receives a predetermined sequence of 1s and 0s.

SWD is used for debugging or for programming the flash

memory.

9.2 Serial Wire Debug Interface

The SWD interface is the preferred alternative to the JTAG

interface. It requires only two pins instead of the four or five

needed by JTAG. SWD provides all of the programming and

debugging features of JTAG at the same speed. SWD does not

provide access to scan chains or device chaining. The SWD

clock frequency can be up to 1/3 of the CPU clock frequency.

The SWD interface can be enabled from the JTAG interface or

disabled, allowing its pins to be used as GPIO. Unlike JTAG, the

SWD interface can always be reacquired on any device during

the key window. It can then be used to reenable the JTAG

interface, if desired. When using SWD or JTAG pins as standard

GPIO, make sure that the GPIO functionality and PCB circuits do

not interfere with SWD or JTAG use.

SWD uses two pins, either two of the JTAG pins (TMS and TCK)

or the USBIO D+ and D– pins. The USBIO pins are useful for in

system programming of USB solutions that would otherwise

require a separate programming connector. One pin is used for

the data clock and the other is used for data input and output.

Figure 9-2. SWD Interface Connections between PSoC 3 and Programmer

V_DD

Host Programmer

PSoC 3

1, 2, 3

V_DD

V_DDD, V_DDA, V_DDIO0, V_DDIO1, V_DDIO2, V_DDIO3

SWDCK

SWDCK (P1[1] or P15[7])

SWDIO (P1[0] or P15[6])

SWDIO

XRES

3, 4

XRES or P1[2]

GND

V_SSD, V_SSA

GND

1

The voltage levels of the Host Programmer and the PSoC 3 voltage domains involved in Programming

should be the same. XRES pin (XRES_N or P1[2]) is powered by V_DDIO1. The USB SWD pins are

powered by V_DDD. So for Programming using the USB SWD pins with XRES pin, the V_DDD, V_DDIO1of

PSoC 3 should be at the same voltage level as Host V_DD. Rest of PSoC 3 voltage domains ( V_DDA, V_DDIO0

V_DDIO2, V_DDIO3) need not be at the same voltage level as host Programmer. The Port 1 SWD pins are

powered by V_DDIO1. So V_DDIO1of PSoC 3 should be at same voltage level as host V_DDfor Port 1 SWD

,

programming. Rest of PSoC 3 voltage domains ( V_DDD, V_DDA, V_DDIO0, V_DDIO2, V_DDIO3) need not be at the same

voltage level as host Programmer.

2

Vdda must be greater than or equal to all other power supplies (Vddd, Vddio’s) in PSoC 3.

3

For Power cycle mode Programming, XRES pin is not required. But the Host programmer must have

the capability to toggle power (Vddd, Vdda, All Vddio’s) to PSoC 3. This may typically require external

interface circuitry to toggle power which will depend on the programming setup. The power supplies can

be brought up in any sequence, however, once stable, VDDA must be greater than or equal to all other

supplies.

4

P1[2] will be configured as XRES by default only for 48-pin devices (without dedicated XRES pin). For

devices with dedicated XRES pin, P1[2] is GPIO pin by default. So use P1[2] as Reset pin only for 48-

pin devices, but use dedicated XRES pin for rest of devices.

Document Number: 001-57330 Rev. *G

Page 62 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

erase. Individual flash blocks can be erased, programmed, and

verified, if block security settings permit.

9.3 Debug Features

Using the JTAG or SWD interface, the CY8C36 supports the

following debug features:

9.7 Device Security

 Halt and single-step the CPU

PSoC 3 offers an advanced security feature called device

security, which permanently disables all test, programming, and

debug ports, protecting your application from external access.

The device security is activated by programming a 32-bit key

(0×50536F43) to a Write Once Latch (WOL).

 View and change CPU and peripheral registers, and RAM

addresses

 Eight program address breakpoints

 One memory access breakpoint—break on reading or writing

The Write Once Latch is a type of nonvolatile latch (NVL). The

cell itself is an NVL with additional logic wrapped around it. Each

WOL device contains four bytes (32 bits) of data. The wrapper

outputs a ‘1’ if a super-majority (28 of 32) of its bits match a

pre-determined pattern (0×50536F43); it outputs a ‘0’ if this

majority is not reached. When the output is 1, the Write Once NV

latch locks the part out of Debug and Test modes; it also

permanently gates off the ability to erase or alter the contents of

the latch. Matching all bits is intentionally not required, so that

single (or few) bit failures do not deassert the WOL output. The

state of the NVL bits after wafer processing is truly random with

no tendency toward 1 or 0.

The WOL only locks the part after the correct 32-bit key

(0×50536F43) is loaded into the NVL's volatile memory,

programmed into the NVL's nonvolatile cells, and the part is

reset. The output of the WOL is only sampled on reset and used

to disable the access. This precaution prevents anyone from

reading, erasing, or altering the contents of the internal memory.

any memory address and data value

 Break on a sequence of breakpoints (non recursive)

 Debugging at the full speed of the CPU

 CompatiblewithPSoCCreatorandMiniProg3programmerand

debugger

 Standard JTAG programming and debugging interfaces make

CY8C36 compatible with other popular third-party tools (for

example, ARM / Keil)

9.4 Trace Features

The CY8C36 supports the following trace features when using

JTAG or SWD:

 Trace the 8051 program counter (PC), accumulator register

(ACC), and one SFR / 8051 core RAM register

 Trace depth up to 1000 instructions if all registers are traced,

or 2000 instructions if only the PC is traced (on devices that

include trace memory)

The user can write the key into the WOL to lock out external

access only if no flash protection is set (see “Flash Security” on

page 21). However, after setting the values in the WOL, a user

still has access to the part until it is reset. Therefore, a user can

write the key into the WOL, program the flash protection data,

and then reset the part to lock it.

 Program address trigger to start tracing

 Trace windowing, that is, only trace when the PC is within a

given range

 Two modes for handling trace buffer full: continuous (overwriting

the oldest trace data) or break when trace buffer is full

If the device is protected with a WOL setting, Cypress cannot

perform failure analysis and, therefore, cannot accept RMAs

from customers. The WOL can be read out through the SWD port

to electrically identify protected parts. The user can write the key

in WOL to lock out external access only if no flash protection is

set. For more information on how to take full advantage of the

security features in PSoC see the PSoC 3 TRM.

9.5 Single Wire Viewer Interface

The SWV interface is closely associated with SWD but can also

be used independently. SWV data is output on the JTAG

interface’s TDO pin. If using SWV, you must configure the device

for SWD, not JTAG. SWV is not supported with the JTAG

interface.

Disclaimer

SWV is ideal for application debug where it is helpful for the

firmware to output data similar to 'printf' debugging on PCs. The

SWV is ideal for data monitoring, because it requires only a

single pin and can output data in standard UART format or

Manchester encoded format. For example, it can be used to tune

a PID control loop in which the output and graphing of the three

error terms greatly simplifies coefficient tuning.

Note the following details of the flash code protection features on

Cypress devices.

Cypress products meet the specifications contained in their

particular Cypress data sheets. Cypress believes that its family

of products is one of the most secure families of its kind on the

market today, regardless of how they are used. There may be

methods, unknown to Cypress, that can breach the code

protection features. Any of these methods, to our knowledge,

would be dishonest and possibly illegal. Neither Cypress nor any

other semiconductor manufacturer can guarantee the security of

their code. Code protection does not mean that we are

guaranteeing the product as “unbreakable.”

Cypress is willing to work with the customer who is concerned

about the integrity of their code. Code protection is constantly

evolving. We at Cypress are committed to continuously

improving the code protection features of our products.

The following features are supported in SWV:

 32 virtual channels, each 32 bits long

 Simple, efficient packing and serializing protocol

 Supports standard UART format (N81)

9.6 Programming Features

The JTAG and SWD interfaces provide full programming

support. The entire device can be erased, programmed, and

verified. You can increase flash protection levels to protect

firmware IP. Flash protection can only be reset after a full device

Document Number: 001-57330 Rev. *G

Page 63 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

Application Notes: PSoC application notes discuss a particular

application of PSoC in depth; examples include brushless DC

motor control and on-chip filtering. Application notes often

include example projects in addition to the application note

document.

10. Development Support

The CY8C36 family has a rich set of documentation,

development tools, and online resources to assist you during

your development process. Visit

psoc.cypress.com/getting-started to find out more.

Technical Reference Manual: The Technical Reference Manual

(TRM) contains all the technical detail you need to use a PSoC

device, including a complete description of all PSoC registers.

10.1 Documentation

A suite of documentation, supports the CY8C36 family to ensure

that you can find answers to your questions quickly. This section

contains a list of some of the key documents.

10.2 Online

In addition to print documentation, the Cypress PSoC forums

connect you with fellow PSoC users and experts in PSoC from

around the world, 24 hours a day, 7 days a week.

Software User Guide: A step-by-step guide for using PSoC

Creator. The software user guide shows you how the PSoC

Creator build process works in detail, how to use source control

with PSoC Creator, and much more.

10.3 Tools

With industry standard cores, programming, and debugging

interfaces, the CY8C36 family is part of a development tool

ecosystem. Visit us at www.cypress.com/go/psoccreator for the

latest information on the revolutionary, easy to use PSoC Creator

IDE, supported third party compilers, programmers, debuggers,

and development kits.

Component data sheets: The flexibility of PSoC allows the

creation of new peripherals (components) long after the device

has gone into production. Component data sheets provide all of

the information needed to select and use a particular component,

including a functional description, API documentation, example

code, and AC/DC specifications.

Document Number: 001-57330 Rev. *G

Page 64 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

11. Electrical Specifications

Specifications are valid for -40°C  Ta  125°C and Tj  150°C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except

where noted. The unique flexibility of the PSoC UDBs and analog blocks enable many functions to be implemented in PSoC Creator

components, see the component data sheets for full AC/DC specifications of individual functions. See the Example Peripherals on

page 40 for further explanation of PSoC Creator components.

11.1 Absolute Maximum Ratings

Table 11-1. Absolute Maximum Ratings DC Specifications ^[17]

Parameter

Tstorag

Description

Storage temperature

Conditions

Min

Typ

Max

Units

Recommended storage

–55

25

125

°C

temperature is 0 °C–50 °C.

Exposure to storage temperatures

above 125 °C for extended periods

may affect device reliability

Vdda

Vddd

Analog supply voltage relative to

Vssd

–0.5

–

6

V

Digital supply voltage relative to

Vssd

Vddio

Vcca

Vccd

Vssa

I/O supply voltage relative to Vssd

Direct analog core voltage input

Direct digital core voltage input

Analog ground voltage

–0.5

–

6

V

1.95

–0.5

Vssd – 0.5

Vssd +

0.5

Vgpio^[18]

Vsio

DC input voltage on GPIO

DC input voltage on SIO

Includes signals sourced by Vdda Vssd – 0.5

and routed internal to the pin

–

Vddio +

0.5

V

Output disabled

Output enabled

–40 °C to +85 °C

–40 °C to +125 °C

Vssd – 0.5

–

7

6

V

Vssd – 0.5

–

Ivddio ^[19]

Current per Vddio supply pin

100

40

41

28

59

2

mA

–

I_GPIO

I_SIO

GPIO current

–30

–49

–56

–

mA

V

SIO current

I_USBIO

V_EXTREF

LU

USBIO current

ADC external reference inputs

Latch up current ^[20]

Pins P0[3], P3[2]

V_SSAtied to V_SSD

–140

2200

750

500

140

–

mA

V

Electrostatic discharge voltage,

Human body model

ESD_HBM

ESD_CDM

V_SSAnot tied to V_SSD

–

V

Electro-static discharge voltage

Charge Device Model

–

V

Note Usage above the absolute maximum conditions listed in Table 11-1 may cause permanent damage to the device. Exposure to

maximum conditions for extended periods of time may affect device reliability. When used below maximum conditions but above

normal operating conditions the device may not operate to specification.

Notes

17. Usage above the absolute maximum conditions listed in Table 11-1 may cause permanent damage to the device. Exposure to Absolute Maximum conditions for

extended periods of time may affect device reliability. The Maximum Storage Temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High

Temperature Storage Life. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification.

18. The Vddio supply voltage must be greater than the maximum analog voltage on the associated GPIO pins. Maximum analog voltage on GPIO pin Vddio  Vdda.

19. Maximum value 100 mA of Iddio applies only to –40 °C to +85 °C range and the limit of Iddio parameter for the –40 °C to +125 °C range is 40 mA.

20. Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch-up Test.

Document Number: 001-57330 Rev. *G

Page 65 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

11.2 Device Level Specifications

Specifications are valid for -40°C  Ta  125°C and Tj  150°C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except

where noted.

11.2.1 Device Level Specifications

Table 11-2. DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

V_DDA

Analog supply voltage and input to Analog core regulator enabled

analog core regulator

1.8

–

5.5

V

V_DDA

V_DDD

Analog supply voltage, analog

regulator bypassed

Analog core regulator disabled

Digital core regulator enabled

Digital core regulator disabled

1.71

1.8

–

1.89

V

Digital supply voltage relative to

V_SSD

V_D-

[21]

DA

Digital supply voltage, digital

regulator bypassed

1.71

1.8

1.89

[22]

[21]

V_DDIO

I/O supply voltage relative to V_SSIO

1.71

–

V_DDA

1.89

V

V_CCA

Direct analog core voltage input

(Analog regulator bypass)

Analog core regulator disabled

Digital core regulator disabled

1.8

V_CCD

Direct digital core voltage input

(Digital regulator bypass)

1.71

1.8

1.89

V

Notes

21. V_DDX= 3.3 V.

22. Based on device specifications (not production tested).

Document Number: 001-57330 Rev. *G

Page 66 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

Table 11-2. DC Specifications (continued)

Parameter Description

Conditions

Min

Typ

Max

Units

Idd^{[23, 24]}Active Mode, VDD = 1.71 V - 5.5 V

ExecutefromCPUinstructionbuffer,

see FlashProgramMemoryonpage

21

CPU at 3 MHz

CPU at 6 MHz

CPU at 12 MHz

CPU at 24 MHz

CPU at 48 MHz

CPU at 62 MHz

T = –40 °C

T = 25 °C

T = 85 °C

T = 125 °C

T = –40 °C

T = 25 °C

T = 85 °C

T = 125 °C

T = –40 °C

T = 25 °C

T = 85 °C

T = 125 °C

T = –40 °C

T = 25 °C

T = 85 °C

T = 125 °C

T = –40 °C

T = 25 °C

T = 85 °C

T = 125 °C

T = –40 °C

T = 25 °C

T = 85 °C

T = 125 °C

–

1.3

1.6

4.8

4.9

2.1

2.3

5.6

5.8

3.5

3.8

7.1

9.0

6.3

6.6

10

–

mA

15.8

11.5

12

15.5

21.7

16

19.5

27.8

Notes

23. The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective data sheets, available

in PSoC Creator, the integrated design environment. To compute total current, find CPU current at frequency of interest and add peripheral currents for your

particular system from the device data sheet and component data sheets.

24. Total current for all power domains: digital (I_DDD), analog (I_DDA), and I/Os (I_{DDIO0, 1, 2, 3}). All I/Os floating.

Document Number: 001-57330 Rev. *G

Page 67 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

Table 11-2. DC Specifications (continued)

Parameter

Description

Sleep Mode^[25]

Conditions

Min

Typ

Max

Units

V

_DD= V_DDIO= 4.5 V–5.5 V T = –40 °C

–

1.1

15

–

µA

CPU OFF

RTC = ON (= ECO32K ON, in low

power mode)

T = 25 °C

T = 85 °C

T = 125 °C

_DD= V_DDIO= 2.7 V–3.6 V T = –40 °C

T = 25 °C

20.3

1

Sleep timer = ON (= ILO ON at

1 kHz) ^[26]

WDT = OFF

I²C Wake = OFF

1

Comparator = OFF

POR = ON

SIO Pins in single ended input,

unregulated output mode

T = 85 °C

12

T = 125 °C

18.5

2.2

16.2

2.2

_CC= V_DDIO

=

T = 25 °C

1.71 V–1.95 V

T = 125 °C

Comparator = ON

CPU = OFF

V_DD= V_DDIO= 2.7 V–3.6 V T = 25 °C

RTC = OFF

Sleep timer = OFF

WDT = OFF

I²C Wake = OFF

POR = ON

SIO Pins in single ended input,

unregulated output mode

I²C Wake = ON

V_DD= V_DDIO= 2.7 V–3.6 V T = 25 °C

–

2.2

–

µA

CPU = OFF

RTC = OFF

Sleep timer = OFF

WDT = OFF

Comparator = OFF

POR = ON

SIO Pins in single ended input,

unregulated output mode

Notes

25. If Vccd and Vcca are externally regulated, the voltage difference between Vccd and Vcca must be less than 50 mV.

26. Sleep timer generates periodic interrupts to wake up the CPU. This specification applies only to those times that the CPU is off.

Document Number: 001-57330 Rev. *G

Page 68 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

Table 11-2. DC Specifications (continued)

Parameter

Description

Hibernate Mode^[27]

Conditions

Min

Typ

Max

Units

V

_DD= V_DDIO= 4.5 V–5.5 V T = –40 °C

–

0.2

0.5

4.1

17.7

0.2

3.2

15.3

0.2

3.3

12.4

0.3

1.4

1.1

0.7

10

–

nA

mA

pA

T = 25 °C

T = 85 °C

T = 125 °C

_DD= V_DDIO= 2.7 V–3.6 V T = –40 °C

T = 25 °C

Hibernate mode current

All regulators and oscillators off.

SRAM retention

GPIO interrupts are active

SIO Pins in single ended input,

unregulated output mode

T = 85 °C

T = 125 °C

_CC= V_DDIO

=

T = –40 °C

T = 25 °C

T = 85 °C

T = 125 °C

1.71 V–1.95 V

I_DDAR

I_DDDR

I_IB

Analog current consumption while V_DDA< 3.6 V

device is reset ^[28]

V_DDA> 3.6 V

Digital current consumption while

device is reset ^[28]

V_DDD< 3.6 V

V_DDD> 3.6 V

Input bias current ^[28]

T = 25 °C

Notes

27. If Vccd and Vcca are externally regulated, the voltage difference between Vccd and Vcca must be less than 50 mV.

28. Based on device characterization (not production tested). USBIO pins tied to ground (V_SSD).

Document Number: 001-57330 Rev. *G

Page 69 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

Figure 11-1. Active Mode Current vs F_CPU, V_DD= 3.3 V, Temperature = 25 °C

Document Number: 001-57330 Rev. *G

Page 70 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

Table 11-3. AC Specifications^[29]

Parameter Description

Conditions

Min

Typ

Max

Units

1.71 V  Vddd  5.5 V, -40°C  Ta

 85°C and Tj  100°C

DC

–

67

MHz

F_CPU

CPU frequency

1.71 V  Vddd  5.5 V, -40°C  Ta

 125°C and Tj  150°C

DC

–

50

67

50

MHz

1.71 V  Vddd  5.5 V, -40°C  Ta

 85°C and Tj  100°C

F_busclk

Bus frequency

Vdd ramp rate

1.71 V  Vddd  5.5 V, -40°C  Ta

 125°C and Tj  150°C

Svdd

–

0.066

10

V/µs

µs

Tio_init

Time from Vddd/Vdda/Vccd/Vcca 

IPOR to I/O ports set to their reset

states

Vcca/Vdda = regulated from

Vdda/Vddd, no PLL used, fast IMO

boot mode (48 MHz typ.)

–

33

66

µs

Time from Vddd/Vdda/Vccd/Vcca 

PRES to CPU executing code at

reset vector

Tstartup

Vcca/Vccd = regulated from

Vdda/Vddd, no PLL used, slow

IMO boot mode (12 MHz typ.)

Tsleep

Wakeup from sleep mode - Occur- 1.71 V  Vddd  5.5 V, Tj  100°C

rence of LVD interrupt to beginning

15

of execution of next CPU instruction

Thibernate

Wakeup from hibernate mode -

Application of external interrupt to

beginning of execution of next CPU

instruction

100

Figure 11-2. Fcpu vs. Vdd

5.5V

Valid Operating Region

3.3V

1.71V

0V

DC

1 MHz

10 MHz

50 MHz

CPU Frequency

Note

29. Based on device characterization (not production tested).

Document Number: 001-57330 Rev. *G

Page 71 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

11.3 Power Regulators

Specifications are valid for -40°C  Ta  125°C and Tj  150°C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except

where noted.

11.3.1 Digital Core Regulator

Table 11-4. Digital Core Regulator DC Specifications

Parameter

Vddd

Description

Input voltage

Conditions

Min

Typ

-

Max

Units

V

1.8

5.5

Vccd

Output voltage

-

1.80

1

-

V

Regulator output capacitance

Total capacitance on the two Vccd pins.

Each capacitor is ±10%, X5R ceramic or

better, see Power System on page 29

µF

Figure 11-3. Regulators V_CCvs V_DD

Figure 11-4. Digital Regulator PSRR vs Frequency and V_DD

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11.3.2 Analog Core Regulator

Table 11-5. Analog Core Regulator DC Specifications

Parameter

Vdda

Description

Input voltage

Conditions

Min

Typ

-

Max

Units

V

1.8

5.5

Vcca

Output voltage

-

1.80

1

-

V

Regulator output capacitor

±10%, X5R ceramic or better (X7R for Ta

> 85°C)

µF

Figure 11-5. Analog Regulator PSRR vs Frequency and V_DD

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11.4 Inputs and Outputs

Specifications are valid for -40°C  Ta  125°C and Tj  150°C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except

where noted.

11.4.1 GPIO

Table 11-6. GPIO DC Specifications

Parameter

Description

Input voltage high threshold

Input voltage low threshold

Input voltage high threshold

Conditions

Min

Typ

Max

Units

Vih

Vil

CMOS Input, PRT[x]CTL = 0

0.7  Vddio

-

V

-

0.3 Vddio

Vih

LVTTL Input, PRT[x]CTL = 1,Vddio 0.7 x Vddio

< 2.7 V

-

Vih

Vil

Input voltage high threshold

Input voltage low threshold

Output voltage high

LVTTLInput, PRT[x]CTL=1, Vddio

V

2.0

-

V

LVTTL Input, PRT[x]CTL = 1,Vddio

< 2.7 V

-

0.3 x Vddio

0.8

Vil

LVTTLInput, PRT[x]CTL=1, Vddio

V

Voh

Ioh = 4 mA at 3.3 Vddio

Ioh = 1 mA at 1.8 Vddio

Iol = 6 mA at 3.3 Vddio

Iol = 3 mA at 1.8 Vddio

Iol = 3 mA at 3.3 Vddio

Vddio - 0.6

-

V

Vddio - 0.5

-

Vol

Output voltage low

–

0.6

0.4

8.5

2

V

–

V

–

V

Rpullup

Pull up resistor

3.5

-

5.6

-

k

nA

Rpulldown Pull down resistor

Iil

Input leakage current (absolute

25°C, Vddio = 3.0 V

value)^[30]

C_IN

Input capacitance^[30]

GPIOs not shared with opamp

outputs, MHz ECO or kHzECO

–

4

5

7

pF

GPIOs shared with MHz ECO or

kHzECO^[31]

GPIOs shared with opamp outputs

–

-

–

18

-

pF

Vh

Input voltage hysteresis

(Schmitt-Trigger)^[30]

40

mV

Idiode

Current through protection diode to

Vddio and Vssio

-

100

µA

Rglobal

Rmux

Resistance pin to analog global bus

Resistance pin to analog mux bus

25°C, Vddio = 3.0 V

–

320

220

–



Notes

30. Based on device characterization (Not production tested).

31. For information on designing with PSoC 3 oscillators, refer to the application note, AN54439 - PSoC^®3 and PSoC 5 External Oscillator.

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Figure 11-6. GPIO Output High Voltage and Current

Figure 11-7. GPIO Output Low Voltage and Current

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Table 11-7. GPIO AC Specifications

Parameter

TriseF

Description

Conditions

3 V Vddio Cload = 25 pF

Min

–

Typ

–

Max

12

Units

ns

Rise time in Fast Strong Mode^[29]

Fall time in Fast Strong Mode^[29]

Rise time in Slow Strong Mode^[29]

Fall time in Slow Strong Mode^[29]

GPIO output operating frequency

TfallF

–

12

ns

TriseS

TfallS

–

60

ns

–

60

ns

3 V < Vddio < 5.5 V, fast strong drive

mode

90/10% Vddio into 25 pF, -40°C 

Ta  85°C and Tj  100°C

-

33

24

20

16

7

MHz

90/10% Vddio into 25 pF, -40°C 

Ta  125°C and Tj  150°C

1.71 V < Vddio < 3 V, fast strong drive 90/10% Vddio into 25 pF, -40°C 

mode

Ta  85°C and Tj  100°C

90/10% Vddio into 25 pF, -40°C 

Ta  125°C and Tj  150°C

Fgpioout

3 V < Vddio < 5.5 V, slow strong drive 90/10% Vddio into 25 pF, -40°C 

mode

Ta  85°C and Tj  100°C

90/10% Vddio into 25 pF, -40°C 

Ta  125°C and Tj  150°C

7

1.71 V < Vddio < 3 V, slow strong drive 90/10% Vddio into 25 pF, -40°C 

mode

3.5

Ta  85°C and Tj  100°C

90/10% Vddio into 25 pF, -40°C 

Ta  125°C and Tj  150°C

GPIO input operating frequency

90/10% better than 60/40 duty

cycle, -40°C  Ta  85°C and Tj 

100°C

-

66

50

MHz

Fgpioin

1.71 V < Vddio < 5.5 V

90/10% better than 60/40 duty

cycle, -40°C  Ta  125°C and Tj 

150°C

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Automotive Family Datasheet

11.4.2 SIO

Table 11-8. SIO DC Specifications

Parameter

Vinmax

Description

Conditions

Min

Typ

Max

Units

Maximum input voltage

All allowed values of Vddio and

Vddd

–

5.5

V

Vinref

Input voltage reference (Differ-

ential input mode)

0.5

-

0.52 Vddio

V

Output voltage reference (Regulated output mode)

Vddio > 3.7

Voutref

1

-

Vddio-1

V

Vddio < 3.7

Vddio - 0.5

Input voltage high threshold

GPIO mode

CMOS input

0.7  Vddio

-

V

Vih

Vil

Differential input mode

With hysteresis

SIO_ref +

0.2

–

Input voltage low threshold

GPIO mode

CMOS input

-

0.3 Vddio

V

Differential input mode

With hysteresis

–

SIO_ref –

0.2

Output voltage high

Unregulated mode

Regulated mode ^[32]

Ioh = 4 mA, Vddio = 3.3 V

Ioh = 1 mA

Vddio - 0.4

-

V

SIO_ref -

0.65

SIO_ref +

0.2

Voh

Vol

Regulated mode ^[32]

Output voltage low

Ioh = 0.1 mA

SIO_ref - 0.3

-

SIO_ref +

0.2

V

Vddio = 3.30 V, Iol = 25 mA

Vddio = 1.80 V, Iol = 4 mA

-

0.8

0.4

8.5

V

V_DDIO= 3.3 V, I_OL= 20 mA

–

V

Rpullup

Rpulldown

Iil

Pull up resistor

3.5

5.6

k

Pull down resistor

Input leakage current (absolute

value)^[33]

Vih < Vddsio

25°C, Vddsio = 3.0 V, Vih = 3.0 V

25°C, Vddsio = 0 V, Vih = 3.0 V

-

14

10

7

nA

µA

pF

Vih > Vddsio

Input Capacitance^[33]

Cin

Vh

-

Input voltage hysteresis

(Schmitt-Trigger)^[33]

Single ended mode (GPIO mode)

Differential mode

–

-

40

35

-

–

mV

µA

–

Current through protection diode

to Vssio

100

Idiode

Notes

32. See Figure 6-8 on page 35for more information on SIO reference.

33. Based on device characterization (not production tested).

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Figure 11-8. SIO Output High Voltage and Current, Unregulated Mode

Figure 11-9. SIO Output Low Voltage and Current, Unregulated Mode

Figure 11-10. SIO Output High Voltage and Current, Regulated Mode

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Table 11-9. SIO AC Specifications

Parameter Description

TriseF

Conditions

Min

Typ

Max

Units

Rise time in Fast Strong Mode

(90/10%)^[29]

Cload = 25 pF, Vddio = 3.3 V

–

12

ns

TfallF

TriseS

TfallS

Fall time in Fast Strong Mode

(90/10%)^[29]

Cload = 25 pF, Vddio = 3.3 V

Cload = 25 pF, Vddio = 3.0 V

–

12

80

70

ns

Rise time in Slow Strong Mode

(90/10%)^[29]

Fall time in Slow Strong Mode

(90/10%)^[29]

SIO output operating frequency

3.3 V < Vddio < 5.5 V, Unregulated 90/10% Vddio into 25 pF, -40°C 

-

33

24

16

MHz

output (GPIO) mode, fast strong

drive mode

Ta  85°C and Tj  100°C

90/10% Vddio into 25 pF, -40°C 

Ta  125°C and Tj  150°C

1.71 V<Vddio<3.3 V, Unregulated 90/10% Vddio into 25 pF

output (GPIO) mode, fast strong

drive mode

3.3 V < Vddio < 5.5 V, Unregulated 90/10% Vddio into 25 pF

output (GPIO) mode, slow strong

drive mode

-

5

4

MHz

Fsioout

1.71 V<Vddio<3.3 V, Unregulated 90/10% Vddio into 25 pF

output (GPIO) mode, slow strong

drive mode

3.3 V < Vddio < 5.5 V, Regulated Output continuously switching into

output mode, fast strong drive mode 25 pF

-

20

10

MHz

1.71 V < Vddio < 3.3 V, Regulated Output continuously switching into

output mode, fast strong drive mode 25 pF

1.71 V < Vddio < 5.5 V, Regulated Output continuously switching into

2.5

output mode, slow strong drive

mode

25 pF

SIO input operating frequency

90/10% better than 60/40 duty

cycle, -40°C  Ta  85°C and

Tj  100°C

-

66

50

MHz

Fsioin

1.71 V < Vddio < 5.5 V

90/10% better than 60/40 duty

cycle, -40°C  Ta  125°C and

Tj  150°C

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Figure 11-11. SIO Output Rise and Fall Times, Fast Strong Mode, V_DDIO= 3.3 V, 25 pF Load

Figure 11-12. SIO Output Rise and Fall Times, Slow Strong Mode, V_DDIO= 3.3 V, 25 pF Load

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11.4.3 USBIO

Table 11-10. USBIO DC Specifications

Parameter

Rusbi

Description

USB D+ pull up resistance

Static output high

Conditions

With idle bus

Min

0.900

1.425

2.8

Typ

Max

1.575

3.090

3.6

Units

k

-

Rusba

While receiving traffic

k

Vohusb

15 k ±5% to Vss, internal pull up

enabled

V

Volusb

Static output low

15 k ±5% to Vss, internal pull up

enabled

-

0.3

V

Vihgpio

Vilgpio

Vohgpio

Volgpio

Vdi

Input voltage high, GPIO mode

Input voltage low, GPIO mode

V_DDD3 V

2

–

-

–

V

0.8

-

Output voltage high, GPIO mode Ioh = 4 mA, Vddio  3 V

2.4

-

Output voltage low, GPIO mode

Differential input sensitivity

Iol = 4 mA, Vddio  3 V

-

0.3

0.2

2.5

|(D+)-(D-)|

-

Vcm

Differential input common mode

range

0.8

-

Vse

Single ended receiver threshold

PS/2 pull up resistance

0.8

3

-

2

7

V

Rps2

In PS/2 mode, with PS/2 pull up

enabled

k

External USB series resistor

USB driver output impedance

In series with each USB pin

21.78

(-1%)

22

-

22.22

(+1%)



Rext

Zo

Including Rext, -40°C  Ta  85°C

and Tj  100°C

28

44

Including Rext, -40°C  Ta  125°C

and Tj  150°C

28

-

46

Cin

USB transceiver input capacitance

-

20

2

pF

nA

Input leakage current (absolute

value)

25°C, Vddio = 3.0 V

Iil ^[34]

Note

34. Based on device characterization (not production tested).

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Figure 11-13. USBIO Output High Voltage and Current, GPIO Mode

Figure 11-14. USBIO Output Low Voltage and Current, GPIO Mode

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Table 11-11. USBIO AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Tdrate

Full-speed data rate average bit rate

12 - 0.25%

12

12 +

0.25%

MHz

Tdjr1

Tdjr2

Tudj1

Receiver data jitter tolerance to next

transition

-8

-5

-

8

5

ns

Receiver data jitter tolerance to pair

transition

Driver differential jitter to next

transition

-3.5

3.5

Tudj2

Driver differential jitter to pair transition

-4

-2

-

4

5

ns

Tfdeop

Source jitter fordifferentialtransitionto

SE0 transition

Tfeopt

Tfeopr

Tfst

Source SE0 interval of EOP

Receiver SE0 interval of EOP

160

82

-

175

-

ns

Width of SE0 interval during differ-

ential transition

14

Fgpio_out GPIO mode output operating

frequency

3 V  Vddd  5.5 V

-

20

6

MHz

ns

Vddd = 1.71 V

-

Tr_gpio

Rise time, GPIO mode, 10%/90%

Vddd

Vddd > 3 V, 25 pF load

Vddd = 1.71 V, 25 pF load

–

12

40

12

40

ns

Tf_gpio

Fall time, GPIO mode, 90%/10% Vddd Vddd > 3 V, 25 pF load

Vddd = 1.71 V, 25 pF load

ns

Figure 11-15. USBIO Output Rise and Fall Times, GPIO Mode, V_DDD= 3.3 V, 25 pF Load

Table 11-12. USB Driver AC Specifications

Parameter Description

Tr Transition rise time

Conditions

Min

–

Typ

Max

20

Units

ns

–

-

Tf

Transition fall time

–

20

ns

TR

Vcrs

Rise/fall time matching

Output signal crossover voltage

VUSB_5, VUSB_3.3, see

90%

1.3

111%

2

-

V

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11.4.4 XRES

Table 11-13. XRES DC Specifications

Parameter

Vih

Description

Input voltage high threshold

Input voltage low threshold

Pull up resistor

Conditions

Min

Typ

-

Max

Units

V

CMOS Input, PRT[x]CTL = 0

0.7  Vddio

-

Vil

-

3.5

-

0.3 Vddio

V

Rpullup

Cin

5.6

3

8.5

k

pF

Input capacitance^[29]

-

Vh

Input voltage hysteresis

(Schmitt-Trigger)^[29]

-

100

mV

Idiode

Current through protection diode to

Vddio and Vssio

-

100

µA

Table 11-14. XRES AC Specifications

Parameter

Description

Reset pulse width

Conditions

Min

Typ

Max

Units

Treset

1

-

µs

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11.5 Analog Peripherals

Specifications are valid for -40°C  Ta  125°C and Tj  150°C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except

where noted.

11.5.1 Opamp

Table 11-15. Opamp DC Specifications

Parameter

Description

Input offset voltage

Conditions

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

Power mode = high

Min

Typ

Max

±2.5

Units

mV

Vioff

-

±5.0

mV

–

-

±30

µV / °C

%

TCVos

Ge1

Vi

Input offset voltage drift with temperature

Gain error, unity gain buffer mode

Input voltage range

Rload = 1 k

-

Vssa

+0.1

-

Vdda

Vdda - 50

-

mV

Vo

Output voltage range

Output load = 1 mA

Vssa + 50

25

-

mV

Iout

Output current

Output voltage is between Vssa

+500 mV and Vdda -500 mV, and

Vdda > 2.7 V, -40°C  Ta  85°C

and Tj  100°C

-

mA

Output voltage is between Vssa

+500 mV and Vdda -500 mV, and

Vdda > 2.7 V, -40°C  Ta  125°C

and Tj  150°C

20

16

-

mA

Output current

Output voltage is between Vssa

+500 mV and Vdda -500 mV, and

Vdda > 1.7 V and Vdda < 2.7 V

Iout

I_DD

Quiescent current

Power mode = min

Power mode = low

Power mode = med

Power mode = high

–

250

330

1000

–

400

950

2500

–

µA

dB

–

CMRR

PSRR

Common mode rejection ratio^[29]

Power supply rejection ratio

80

85

70

Vdda  2.7 V

–

Vdda < 2.7 V

–

Figure 11-16. Opamp Voffset Histogram, 3388 samples/847 parts, 25 °C, Vdda = 5 V

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Figure 11-17. Opamp Voffset vs Temperature, Vdda = 5 V

Figure 11-18. Opamp Voffset vs Vcommon and Vdda, 25 °C

Figure 11-19. Opamp Output Voltage vs Load Current and Temperature, High Power Mode, 25 °C, Vdda = 2.7 V

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Figure 11-20. Opamp Operating Current vs Vdda and Power Mode

Table 11-16. Opamp AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

GBW

Gain-bandwidth product

Power mode = minimum, 15 pF

load

1

–

MHz

Power mode = low, 15 pF load

Power mode = medium, 200 pF

load

2

1

–

MHz

Power mode = high, 200 pF load

Power mode = low, 15 pF load

Power mode = medium, 200 pF

load

Power mode = high, 200 pF load

Power mode = high, Vdda = 5 V,

at 100 kHz

2.5

1.1

0.9

–

MHz

V/µs

SR

e_n

Slew rate, 20% - 80%

Input noise density

3

–

45

–

V/µs

nV/sqrtH

z

Figure 11-21. Opamp Noise vs Frequency, Power Mode = High, Vdda = 5 V

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Figure 11-22. Opamp Step Response, Rising

Figure 11-23. Opamp Step Response, Falling

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11.5.2 Delta-Sigma ADC

Unless otherwise specified, operating conditions are:

 Operation in continuous sample mode

 fclk = 6.144 MHz

 Reference = 1.024 V internal reference bypassed on P3.2 or P0.3

 Unless otherwise specified, all charts and graphs show typical values

Table 11-17. 12-bit Delta-sigma ADC DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Resolution

8

–

12

bits

No. of

GPIO

Number of channels, single ended

–

Differential pair is formed using a

pair of GPIOs.

No. of

GPIO/2

Number of channels, differential

Monotonic

–

Yes

–

Buffered, buffer gain = 1, Range =

±1.024 V, 12-bit mode, 25 °C

Ge

Gd

Gain error

±0.2

%

Buffered, buffer gain = 1, Range =

±1.024 V, 12-bit mode

Gain drift

–

50

ppm/°C

mV

Buffered, 16-bit mode, full voltage

range

±0.2

±0.1

Vos

Input offset voltage

Buffered, 16-bit mode,

V_DDA= 1.8 V + 5%

mV

Buffer gain = 1, 12-bit,

Range = ±1.024 V

TCVos

Temperature coefficient, input offset voltage

Input voltage range, single ended^[35]

–

1

µV/°C

V_SSA

V_DDA

V

Input voltage range, differential unbuf-

fered^[35]

Input voltage range, differential, buffered^[35]

Integral non linearity^[35]

Differential non linearity^[35]

Integral non linearity^[35]

V_SSA

–

V_DDA– 1

V

INL12

DNL12

INL8

Range = ±1.024 V, unbuffered

–

±1

LSB

DNL8

Differential non linearity^[35]

Note

35. Based on device characterization (not production tested).

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Table 11-17. 12-bit Delta-sigma ADC DC Specifications (continued)

Parameter

Description

ADC input resistance

Conditions

Input buffer used

Min

Typ

Max

Units

Rin_Buff

10

–

M

Input buffer bypassed, 12 bit,

Range = ±1.024 V

Rin_ADC12 ADC input resistance

–

148^[36]

–

k

Vextref

ADC external reference input voltage

Pins P0[3], P3[2]

0.9

1.3

V

Current Consumption

I_{DD_12}

I_BUFF

I_DDD+ I_DDACurrent consumption, 12 bit ^[37]192 ksps, unbuffered

Buffer current consumption^[37]

–

1.95

2.5

mA

Notes

36. By using switched capacitors at the ADC input an effective input resistance is created. Holding the gain and number of bits constant, the resistance is proportional

to the inverse of the clock frequency. This value is calculated, not measured. For more information see the Technical Reference Manual.

37. Based on device characterization (Not production tested).

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Table 11-18. Delta-sigma ADC AC Specifications

Parameter

Description

Conditions

Min

–

Typ

–

Max

4

Units

Samples

%

Startup time

Total harmonic distortion^[37]

THD

Buffer gain = 1, 16 bit,

Range = ±1.024 V

–

0.0040

12-Bit Resolution Mode

SR12

BW12

Sample rate, continuous, high power^[37]

Input bandwidth at max sample rate^[37]

Range = ±1.024 V, unbuffered

4

–

44

–

192

–

ksps

kHz

dB

SINAD12int Signal to noise ratio, 12-bit, internal

reference^[37]

66

–

8-Bit Resolution Mode

SR8

Sample rate, continuous, high power^[37]

Input bandwidth at max sample rate^[37]

Range = ±1.024 V, unbuffered

8

–

88

–

384

–

ksps

kHz

dB

BW8

SINAD8int

Signal to noise ratio, 8-bit, internal

reference^[37]

43

–

Table 11-19. Delta-sigma ADC Sample Rates, Range = ±1.024 V

Continuous

Multi-Sample

Multi-Sample Turbo

Resolution,

Bits

Min

Max

Min

Max

Min

1829

1489

1307

1123

956

Max

8

8000

6400

5566

4741

4000

384000

307200

267130

227555

192000

1911

1543

1348

1154

978

91701

74024

64673

55351

46900

87771

71441

62693

53894

45850

9

10

11

12

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Figure 11-24. Delta-sigma ADC IDD vs sps, Range = ±1.024 V, Continuous Sample Mode, Input Buffer Bypassed

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11.5.3 Voltage Reference

Table 11-20. Voltage Reference Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

-40°C  Ta  85°C and Tj  100°C 1.021

1.024

1.027

(+0.3%)

V

(-0.3%)

Vref ^[38]

Precision reference

-40°C  Ta  125°C and Tj  150°C 1.018

1.024

1.030

(+0.6%)

V

(–0.6%)

After typical PCB assembly, post reflow Typical (non-optimized) board

layout and 250 °C solder reflow.

Device may be calibrated after

assembly to improve performance.

–40 °C

25 °C

85 °C

±0.5

±0.2

–

%

Temperature drift^[39]

Box method

–

30

–

ppm/°C

ppm/khr

ppm

Long term drift

Thermal cycling drift (stability)^{[39, 40]}

100

–

Figure 11-25. Voltage Reference vs. Temperature and V_CCA

Figure 11-26. Voltage Reference Long-Term Drift

Notes

38. V_REFis measured after packaging, and thus accounts for substrate and die attach stresses.

39. Based on device characterization (Not production tested).

40. After eight full cycles between –40 °C and 100 °C.

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11.5.4 Analog Globals

Table 11-21. Analog Globals Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Rppag

Resistance pin-to-pin through P2[4], V_DDA= 3 V

AGL0, DSM INP, AGL1, P2[5]^[41]

–

1472

2200



Rppmuxbus Resistance pin-to-pin through P2[3], V_DDA= 3 V

amuxbusL, P2[4]^[41]

–

706

1100



11.5.5 Comparator

Table 11-22. Comparator DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Input offset voltage in fast mode

Factory trim, Vdda > 2.7 V,

Vin  0.5 V

–

10

mV

Input offset voltage in slow mode

Factory trim, Vin  0.5 V

–

9

4

–

mV

V_OS

Input offset voltage in fast mode^[42]Custom trim

Input offset voltage in slow mode^[42]Custom trim

–

Input offset voltage in ultra low-power V_DDA≤ 4.6 V

±12

mode

V_HYST

V_ICM

Hysteresis

Hysteresis enable mode

–

10

–

32

mV

V

Input common mode voltage

High current / fast mode

Low current / slow mode

Ultra low-power mode

V_SSA

V_DDA

–

V

–

V_DDA

1.15

–

V

V_DDA≤ 4.6 V

CMRR

Icmp

Common mode rejection ratio

High current mode/fast mode^[29]

–

-

50

-

–

dB

µA

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

VDDA < 4.6 V

400

600

100

150

-

Low current mode/slow mode^[29]

Ultra low power mode^[29]

-

6

Table 11-23. Comparator AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Response time, high current mode^[43]50 mV overdrive, measured

pin-to-pin

–

75

110

ns

Response time, low current mode^[43]50 mV overdrive, measured

pin-to-pin

–

155

55

200

–

ns

µs

T_RESP

Response time, ultra low-power

mode^[43]

50 mV overdrive, measured

pin-to-pin, V_DDA≤ 4.6 V

Note

41. The resistance of the analog global and analog mux bus is high if V_DDA 2.7 V, and the chip is in either sleep or hibernate mode. Use of analog global and analog

mux bus under these conditions is not recommended.

42. The recommended procedure for using a custom trim value for the on-chip comparators can be found in the TRM.

43. Based on device characterization (Not production tested).

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11.5.6 IDAC

All specifications are based on use of the low-resistance IDAC output pins (see Pin Descriptions on page 9 for details). See the IDAC

component data sheet in PSoC Creator for full electrical specifications and APIs.

Unless otherwise specified, all charts and graphs show typical values.

Table 11-24. IDAC (Current Digital-to-Analog Converter) DC Specifications

Parameter

Resolution

I_OUT

Description

Conditions

Min

Typ

8

Max

Units

-

Output current at code = 255

Range = 2.04 mA, code = 255,

V_DDA 2.7 V, Rload = 600 

–

2.04

–

mA

Range = 2.04 mA, high speed

mode, code = 255, V_DDA 2.7 V,

Rload = 300 

–

2.04

–

Range=255µA, code=255, Rload

= 600 

–

255

–

µA

Range = 31.875 µA, code = 255,

31.875

Rload = 600 

Monotonicity

–

Yes

±1

INL

Integral nonlinearity

Sink mode, range = 255 µA, Codes

8 – 255, Rload = 2.4 k, Cload =

15 pF

±0.9

LSB

Source mode, range = 255 µA,

Codes 8 – 255, Rload = 2.4 k,

Cload = 15 pF

–

±1.2

±1.5

DNL

Differential nonlinearity

Sink mode, range = 255 µA, Rload

= 2.4 k, Cload = 15 pF

–

±0.3

±1

LSB

Source mode, range = 255 µA,

Rload = 2.4 k, Cload = 15 pF

Ezs

Eg

Zero scale error

Gain error

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

Range = 2.04 mA, 25 °C

-

0

-

±1

±2

LSB

%

-

–

1

–

±2.5

±3.5

0.04

0.05

–

Range = 255 µA, 25 ° C

%

Range = 31.875 µA, 25 ° C

%

TC_Eg

Temperature coefficient of gain error Range = 2.04 mA

Range = 255 µA

% / °C

V

Range = 31.875 µA

Vcompliance Dropout voltage, source or sink mode Voltage headroom at max current,

Rload to Vdda or Rload to Vssa,

Vdiff from Vdda

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Table 11-24. IDAC (Current Digital-to-Analog Converter) DC Specifications (continued)

Parameter

I_DD

Description

Conditions

Min

Typ

Max

Units

Operating current, code = 0

Low speed mode, source mode,

range = 31.875 µA

–

44

100

µA

Low speed mode, source mode,

range = 255 µA,

–

33

100

500

µA

Low speed mode, source mode,

range = 2.04 mA

Low speed mode, sink mode,

range = 31.875 µA

36

Low speed mode, sink mode,

range = 255 µA

33

Low speed mode, sink mode,

range = 2.04 mA

33

High speed mode, source mode,

range = 31.875 µA

310

305

310

300

High speed mode, source mode,

range = 255 µA

High speed mode, source mode,

range = 2.04 mA

High speed mode, sink mode,

range = 31.875 µA

High speed mode, sink mode,

range = 255 µA

High speed mode, sink mode,

range = 2.04 mA

Figure 11-27. IDAC INL vs Input Code, Range = 255 µA, Source Mode

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Figure 11-28. IDAC INL vs Input Code, Range = 255 µA, Sink Mode

Figure 11-29. IDAC DNL vs Input Code, Range = 255 µA, Source Mode

Figure 11-30. IDAC DNL vs Input Code, Range = 255 µA, Sink Mode

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Figure 11-31. IDAC INL vs Temperature, Range = 255 µA, High speed mode

Figure 11-32. IDAC DNL vs Temperature, Range = 255 µA, High speed mode

Figure 11-33. IDAC Full Scale Error vs Temperature, Range = 255 µA, Source Mode

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Figure 11-34. IDAC Full Scale Error vs Temperature, Range = 255 µA, Sink Mode

Figure 11-35. IDAC Operating Current vs Temperature, Range = 255 µA, Code = 0, Source Mode

Figure 11-36. IDAC Operating Current vs Temperature, Range = 255 µA, Code = 0, Sink Mode

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Table 11-25. IDAC (Current Digital-to-Analog Converter) AC Specifications

Parameter

Fdac

Description

Conditions

Min

–

Typ

–

Max

8

Units

Msps

ns

Update rate

T_SETTLE

Settling time to 0.5 LSB

Range = 31.875 µA or 255 µA, full

scale transition, High speed mode,

600  15-pF load

–

125

Current noise

Range = 255 µA, source mode,

High speed mode, Vdda = 5 V,

10 kHz

–

340

–

pA/sqrtHz

Figure 11-37. IDAC Step Response, Codes 0x40 - 0xC0, 255 µA Mode, Source Mode, High speed mode, Vdda = 5 V

Figure 11-38. IDAC Glitch Response, Codes 0x7F - 0x80, 255 µA Mode, Source Mode, High speed mode, Vdda = 5 V

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Figure 11-39. IDAC PSRR vs Frequency

Figure 11-40. IDAC Current Noise, 255 µA Mode, Source Mode, High speed mode, Vdda = 5 V

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11.5.7 VDAC

Table 11-26. VDAC (Voltage Digital-to-Analog Converter) DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Resolution

-

8

-

Output resistance^[29]

Rout

Vout

High

Vout = 4 V

Vout = 1 V

1 V scale

-

16

4

-

k

Low

-

k

Output voltage range, code = 255

–

1.02

4.08

±2.1

±0.3

–

V

4 V scale, Vdda = 5 V

1 V scale

–

V

INL

Integral nonlinearity

Differential nonlinearity

Monotonicity

±2.5

±1

LSB

DNL

1 V scale

LSB

Yes

±2.5

0.03

100

500

±0.9

–

Eg

Gain error

1 V scale,

–

%

4 V scale

–

TC_Eg

Temperature coefficient, gain error

1 V scale,

–

%FSR / °C

µA

4 V scale

–

VDAC_ICC Operating current

V_OSZero scale error

Low speed mode

High speed mode

–

µA

0

LSB

Figure 11-41. VDAC INL vs Input Code, 1 V Mode

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Figure 11-42. VDAC DNL vs Input Code, 1 V Mode

Figure 11-43. VDAC INL vs Temperature, 1 V Mode

Figure 11-44. VDAC DNL vs Temperature, 1 V Mode

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Figure 11-45. VDAC Full Scale Error vs Temperature, 1 V Mode

Figure 11-46. VDAC Full Scale Error vs Temperature, 4 V Mode

Figure 11-47. VDAC Operating Current vs Temperature, 1V Mode, Low speed mode

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Figure 11-48. VDAC Operating Current vs Temperature, 1 V Mode, High speed mode

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Table 11-27. VDAC (Voltage Digital-to-Analog Converter) AC Specifications

Parameter

Fdac

Description

Update rate^[29]

Conditions

Min

Typ

Max

1

Units

Msps

Ksps

µs

1 V mode

4 V mode

-

250

1

TsettleP

Settling time to 0.1%, step 25% to

75%

1 V scale, Cload = 15 pF

4 V scale, Cload = 15 pF

1 V scale, Cload = 15 pF

4 V scale, Cload = 15 pF

–

0.45

0.8

3.2

1

µs

TsettleN

Settling time to 0.1%, step 75% to

25%

0.45

0.7

µs

3

µs

Voltage noise

Range = 1 V, High speed mode,

Vdda = 5 V, 10 kHz

750

–

nV/sqrtHz

Figure 11-49. VDAC Step Response, Codes 0x40 - 0xC0, 1 V Mode, High speed mode, Vdda = 5 V

Figure 11-50. VDAC Glitch Response, Codes 0x7F - 0x80, 1 V Mode, High speed mode, Vdda = 5 V

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Figure 11-51. VDAC PSRR vs Frequency

Figure 11-52. VDAC Voltage Noise, 1 V Mode, High speed mode, Vdda = 5 V

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11.5.8 Discrete and Continuous Time Mixer

The mixer is created using a SC/CT analog block; see the Mixer component data sheet in PSoC Creator for full electrical specifications

and APIs.

Table 11-28. Mixer DC Specifications

Parameter

V_OS

Description

Input offset voltage

Conditions

Min

–

Typ

–

Max

15

2

Units

mV

Quiescent current

Gain

–

0.9

0

mA

G

–

dB

Table 11-29. Mixer AC Specifications

Parameter

f_LO

Description

Local oscillator frequency

Input signal frequency

Local oscillator frequency

Input signal frequency

Slew rate

Conditions

Down mixer mode

Min

–

Typ

–

Max

4

Units

MHz

V/µs

f_in

f_LO

f_in

Down mixer mode

Up mixer mode

–

14

1

–

1

SR

3

–

Note

44. Bandwidth is guaranteed for input common mode between 0.3 V and Vdda-1.2 V and for output that is between 0.05 V and Vdda-0.05 V.

Document Number: 001-57330 Rev. *G

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11.5.9 Transimpedance Amplifier

The TIA is created using a SC/CT Analog Block, see the TIA component data sheet in PSoC Creator for full AC/DC specifications,

and APIs and example code.

Table 11-30. Transimpedance Amplifier (TIA) DC Specifications

Parameter

Vioff

Description

Input offset voltage

Conditions

Min

Typ

Max

Units

-

10

mV

Conversion resistance^[45]

R = 20K

40 pF load

-25

–

-

+35

2

%

R = 30K

-

R = 40K

-

%

Rconv

R = 80K

-

%

R = 120K

-

%

R = 250K

-

%

R= 500K

%

R = 1M

-

%

Quiescent current

1.1

mA

Table 11-31. Transimpedance Amplifier (TIA) AC Specifications

Parameter

BW

Description

Conditions

R = 20K; –40 pF load

R = 120K; –40 pF load

R = 1M; –40 pF load

Min

1000

220

25

Typ

–

Max

Units

kHz

Input bandwidth (–3 dB)

–

kHz

–

kHz

Note

45. Conversion resistance values are not calibrated. Calibrated values and details about calibration are provided in PSoC Creator component data sheets. External

precision resistors can also be used.

Document Number: 001-57330 Rev. *G

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11.5.10 Programmable Gain Amplifier

The PGA is created using a SC/CT Analog Block, see the PGA component data sheet in PSoC Creator for full AC/DC specifications,

and APIs and example code.

Unless otherwise specified, operating conditions are:

 Operating temperature = 25 °C for typical values

 Unless otherwise specified, all charts and graphs show typical values

Table 11-32. PGA DC Specifications

Parameter

Vin

Description

Input voltage range

Conditions

Min

Vssa

–

Typ

–

Max

Vdda

10

Units

V

Power mode = minimum

Vos

Input offset voltage

Power mode = high,

gain = 1

–

mV

Gain Error^[29]

Non inverting mode, reference = Vssa

Ge1

Gain = 1

Rin of 40K, -40°C  Ta  85°C and

Tj  100°C

–

±0.15

±2.5

±4

%

Rin of 40K, -40°C  Ta  125°C and

Tj  150°C

Ge16

Ge50

TCVos

Gain = 16

Gain = 50

Rin of 40K, -40°C  Ta  85°C and

Tj  100°C

%

Rin of 40K, -40°C  Ta  125°C and

Tj  150°C

%

Rin of 40K, -40°C  Ta  85°C and

Tj  100°C

±5

%

Rin of 40K, -40°C  Ta  125°C and

Tj  150°C

±6

%

Input offset voltage drift with

temperature

Power mode = high,

gain = 1

±30

µV/°C

Vonl

Cin

DC output nonlinearity

Input capacitance

Gain = 1

–

±0.01

% of FSR

7

–

pF

V

Voh

Output voltage swing

Power mode = high,

V_DDA–

gain = 1, Rload = 100 k to V_DDA/ 2 0.15

Vol

Output voltage swing

Power mode = high,

gain = 1, Rload = 100 k to V_DDA/ 2

–

V_SSA

0.15

+

V

Vsrc

Output voltage under load

Iload = 250 µA, Vdda  2.7V, power

mode = high

300

mV

Idd

Operating current

Power mode = high

–

1.5

–

1.65

–

mA

dB

PSRR

Power supply rejection ratio

48

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Figure 11-53. PGA Voffset Histogram, 4096 samples / 1024 parts

Table 11-33. PGA AC Specifications

Parameter Description

BW1 –3 dB bandwidth

Conditions

Power mode = high,

gain = 1, input = 100 mV

peak-to-peak, Cl = 40 pF

Min

Typ

Max

Units

5.5

8

–

MHz

SR1

e_n

Slew rate

Power mode = high,

gain = 1, 20% to 80%

3

–

V/µs

Input noise density

Power mode = high,

Vdda = 5 V, at 100 kHz

43

nV/sqrtHz

Figure 11-54. Noise vs. Frequency, Vdda = 5 V, Power Mode = High

11.5.11 Temperature Sensor

Table 11-34. Temperature Sensor Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Temp sensor accuracy

Range: –40 °C to +150 °C

-

±5

-

°C

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11.5.12 LCD Direct Drive

Table 11-35. LCD Direct Drive DC Specifications

Parameter

I_CC

Description

Conditions

Min

Typ

Max

Units

LCD system operating current

Device sleep mode with wakeup at

400-Hz rate to refresh LCDs, bus

clock = 3 Mhz, Vddio = Vdda = 3 V,

4 commons, 16 segments, 1/4 duty

cycle, 50 Hz frame rate, no glass

connected

–

38

–

A

I_{CC_SEG}

V_BIAS

Current per segment driver

Strong drive mode

–

2

260

–

5

µA

V

LCD bias range (V_BIASrefers to the V_DDA 3 V and V_DDA V_BIAS

main output voltage(V0) of LCD DAC)

LCD bias step size

V_DDA 3 V and V_DDA V_BIAS

–

9.1 ×

V_DDA

–

mV

pF

LCD capacitance per

Drivers may be combined

500

5000

segment/common driver

Long term segment offset

–

20

mV

µA

I_OUT

Output drive current per segment

driver)

Vddio = 5.5V, strong drive mode

355

710

Table 11-36. LCD Direct Drive AC Specifications

Parameter

Description

LCD frame rate

Conditions

Min

10

Typ

Max

Units

f_LCD

50

150

Hz

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11.6 Digital Peripherals

Specifications are valid for -40°C  Ta  125°C and Tj  150°C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except

where noted.

11.6.1 Timer

Table 11-37. Timer DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Block current consumption

16-bit timer, at listed input clock

frequency

–

µA

3 MHz

–

15

60

–

µA

12 MHz

50 MHz

67 MHz

260

350

Table 11-38. Timer AC Specifications

Parameter Description

Operating frequency

Conditions

Min

DC

15

21

30

42

15

21

15

21

30

42

15

21

30

42

Typ

Max

67 ^[46]

Units

MHz

ns

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

-

50

-

Capture pulse width (Internal)

Capture pulse width (external)

Timer resolution

-

ns

-

ns

-

ns

-

ns

-

ns

Enable pulse width

-

ns

-

ns

Enable pulse width (external)

Reset pulse width

-

ns

-

ns

-

ns

-

ns

Reset pulse width (external)

-

ns

-

ns

Note

46. Applicable at -40°C to 85°C; 50 MHz at -40°C to 125°C.

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11.6.2 Counter

Table 11-39. Counter DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Block current consumption

16-bit counter, at listed input clock

frequency

–

µA

3 MHz

–

15

60

–

µA

12 MHz

50 MHz

67 MHz

260

350

Table 11-40. Counter AC Specifications

Parameter Description

Operating frequency

Conditions

Min

DC

15

21

15

21

15

21

30

42

15

21

30

42

15

21

30

42

Typ

Max

67^[47]

Units

MHz

ns

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

-

50

-

Capture pulse

-

ns

Resolution

-

ns

-

ns

Pulse width

-

ns

-

ns

Pulse width (external)

Enable pulse width

Enable pulse width (external)

Reset pulse width

Reset pulse width (external)

-

ns

-

ns

-

ns

-

ns

-

ns

-

ns

-

ns

-

ns

-

ns

-

ns

Note

47. Applicable at -40°C to 85°C; 50 MHz at -40°C to 125°C.

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11.6.3 Pulse Width Modulation

Table 11-41. PWM DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Block current consumption

16-bit PWM, at listed input clock

frequency

–

µA

3 MHz

–

15

60

–

µA

12 MHz

50 MHz

67 MHz

260

350

Table 11-42. Pulse Width Modulation (PWM) AC Specifications

Parameter

Description

Operating frequency

Conditions

Min

DC

15

21

30

42

15

21

30

42

15

21

30

42

15

21

30

42

Typ

Max

67 ^[48]

Units

MHz

ns

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

-

50

-

Pulse width

-

ns

Pulse width (external)

Kill pulse width

-

ns

-

ns

-

ns

-

ns

Kill pulse width (external)

Enable pulse width

ns

-

ns

Enable pulse width (external)

Reset pulse width

ns

Reset pulse width (external)

ns

Note

48. Applicable at -40°C to 85°C; 50 MHz at -40°C to 125°C.

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11.6.4 I²C

Table 11-43. Fixed I²C DC Specifications

Parameter

Description

Conditions

Min

–

Typ

–

Max

250

260

30

Units

µA

Block current consumption

Enabled, configured for 100 kbps

Enabled, configured for 400 kbps

Wake from sleep mode

–

µA

–

µA

Table 11-44. Fixed I²C AC Specifications

Parameter Description

Conditions

Min

Typ

Max

Units

Bit rate

-

1

Mbps

11.6.5 Controller Area Network^[49]

Table 11-45. CAN DC Specifications

Parameter

Description

Conditions

500 kbps

Min

Typ

Max

285

330

Units

µA

Block current consumption

-

1 Mbps

µA

Table 11-46. CAN AC Specifications

Parameter Description

Conditions

Min

Typ

Max

Units

Bit rate

Minimum 8 MHz clock

-

1

Mbit

11.6.6 Digital Filter Block

Table 11-47. DFB DC Specifications

Parameter

Description

Conditions

64-tap FIR at Fdfb

500 kHz (6.7 ksps)

1 MHz (13.4 ksps)

10 MHz (134 ksps)

50 MHz (644 ksps)

67 MHz (900 ksps)^[50]

Min

Typ

Max

Units

DFB operating current

-

0.16

0.33

3.3

0.27

0.53

5.3

mA

15.7

21.8

25.5

35.6

Table 11-48. DFB AC Specifications

Parameter

Fdfb

Description

Conditions

Min

DC

Typ

Max

Units

MHz

DFB operating frequency

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

-

67 ^[50]

50 ^[50]

Note

49. Refer to ISO 11898 specification for details.

50. Applicable at -40°C to 85°C; 50 MHz at -40°C to 125°C.

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11.6.7 USB

Table 11-49. USB DC Specifications

Parameter

V_{USB_5}

Description

Conditions

Min

Typ

Max

Units

Device supply for USB operation

USB configured, USB regulator

enabled

4.35

–

5.25

V

V_{USB_3.3}

V_{USB_3}

USB configured, USB regulator

bypassed

3.15

2.85

–

3.6

V

USB configured, USB regulator

bypassed^[51]

I_{USB_Configured}Device supply current in device

active mode, bus clock and IMO =

24 MHz

V_DDD= 5 V, F_CPU= 1.5 MHz

–

10

8

–

mA

V_DDD= 3.3 V, F_CPU= 1.5 MHz

I_{USB_Suspended}Device supply current in device

sleep mode

V_DDD= 5 V, connected to USB

host, PICU configured to wake on

USB resume signal

–

0.5

–

mA

V

_DDD= 5 V, disconnected from

–

0.3

0.5

–

mA

USB host

V_DDD= 3.3 V, connected to USB

host, PICU configured to wake on

USB resume signal

V_DDD= 3.3 V, disconnected from

–

0.3

–

mA

USB host

11.6.8 Universal Digital Blocks (UDBs)

PSoC Creator provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM,

AND, OR, and so on) that are mapped to the UDB array. See the component data sheets in PSoC Creator for full AC/DC specifications,

APIs, and example code.

Table 11-50. UDB AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Datapath Performance

Fmax_timer Maximum frequency of 16-bit timer in a -40°C  Ta  85°C and Tj  100°C

-

67

50

67

50

67

50

MHz

UDB pair

-40°C  Ta  125°C and Tj  150°C

Fmax_adder Maximum frequency of 16-bit adder in a -40°C  Ta  85°C and Tj  100°C

UDB pair

-40°C  Ta  125°C and Tj  150°C

Fmax_CRC Maximum frequency of 16-bit CRC/PRS -40°C  Ta  85°C and Tj  100°C

in a UDB pair

-40°C  Ta  125°C and Tj  150°C

PLD Performance

Fmax_PLD Maximum frequency of a two-pass PLD -40°C  Ta  85°C and Tj  100°C

-

67

50

MHz

function in a UDB pair

-40°C  Ta  125°C and Tj  150°C

Clock to Output Performance

t_{clk_out}

Propogation delay for clock in to data out, 25 °C, Vddd  2.7 V

-

20

–

25

55

ns

see Figure 11-55.

t_{clk_out}

Propogation delay for clock in to data out, Worst-case placement, routing,

see Figure 11-55.

and pin selection

Note

51. Rise/fall time matching (TR) not guaranteed, see .

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Figure 11-55. Clock to Output Performance

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11.7 Memory

Specifications are valid for -40°C  Ta  125°C and Tj  150°C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except

where noted.

11.7.1 Flash

Table 11-51. Flash DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Erase and program voltage

Vddd pin

1.71

-

5.5

V

Table 11-52. Flash AC Specifications

Parameter

Description

Min

Typ

Max

15

10

5

Units

ms

Twrite

Block write time (erase + program)

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  140°C

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  140°C

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  140°C

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  140°C

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  140°C

No overhead ^[53]

-

ms

Terase

Tbulk

Block erase time

ms

Block program time

ms

5

ms

Bulk erase time (16 KB to 64 KB)^[52]

Sector erase time (8 KB to 16 KB)^[52]

35

TBD

15

5

ms

Total device program time

(including JTAG, etc.)

seconds

Flash data retention time,

retention period measured from last

erase cycle ^[54]

Average ambient temp.

T_A 55 °C, 100 K erase/program

cycles

20

10

–

years

Retention period measured from

last erase cycle after 100k

progra/erase cycles at

T_A 85 °C

Notes

52. ECC not included.

53. See PSoC^®3 Device Programming Specifications for a description of a low-overhead method of programming PSoC 3 flash. (Please take care of Foot note numbers)

54. Cypress provides a retention calculator to calculate the retention lifetime based on customers' individual temperature profiles for operation over the –40 °C to +125 °C

ambient temperature range. Contact customercare@cypress.com.

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11.7.2 EEPROM

Table 11-53. EEPROM DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Erase and program voltage

1.71

-

5.5

V

Table 11-54. EEPROM AC Specifications

Parameter

Description

Min

–

Typ

2

Max

20

–

Units

ms

T_WRITE

Single row erase/write cycle time

EEPROM data retention time, retention Average ambient temp, T_A 25 °C,

period measured from last erase cycle 1M erase/program cycles

20

–

years

Average ambient temp, T_A 55 °C,

20

10

–

100 K erase/program cycles

Average ambient temp. T_A85 °C,

10 K erase/program cycles

11.7.3 Nonvolatile Latches (NVL)

Table 11-55. NVL DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Erase and program voltage

Vddd pin

1.71

-

5.5

V

Table 11-56. NVL AC Specifications

Parameter Description

NVL endurance

Conditions

Min

Typ

Max

Units

Programmed at 25°C

Programmed at 0-70°C

1K

-

program/

erase

cycles

100

-

program/

erase

cycles

NVL data retention time

Programmed at 55°C

Programmed at 0-70°C

20

10

-

years

11.7.4 SRAM

Table 11-57. SRAM DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Vsram

SRAM retention voltage

1.2

-

V

Table 11-58. SRAM AC Specifications

Parameter

Description

Conditions

Min

DC

Typ

Max

67

Units

MHz

Fsram

SRAM operating frequency

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

-

50

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Automotive Family Datasheet

11.7.5 External Memory Interface

Figure 11-56. Asynchronous Read Cycle Timing

Tcel

EM_CEn

EM_Addr

Taddrv

Taddrh

Address

Toel

EM_OEn

EM_WEn

EM_Data

Tdoesu

Tdoeh

Data

Table 11-59. Asynchronous Read Cycle Specifications

Parameter

T

Description

EMIF clock period^[55]

Conditions

Vdda  3.3 V

Min

Typ

–

Max

Units

ns

30.3

2T – 5

–

Tcel

EM_CEn low time

–

2T+ 5

ns

Taddrv

Taddrh

Toel

EM_CEn low to EM_Addr valid

Address hold time after EM_Wen high

EM_OEn low time

–

5

ns

T

–

ns

2T – 5

T + 15

3

–

2T + 5

ns

Tdoesu

Tdoeh

Data to EM_OEn high setup time

Data hold time after EM_OEn high

–

ns

–

ns

Note

55. Limited by GPIO output frequency, see .

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Automotive Family Datasheet

Figure 11-57. Asynchronous Write Cycle Timing

Taddrv

Taddrh

EM_Addr

EM_CEn

Address

Tcel

Twel

EM_WEn

EM_OEn

Tdweh

Tdcev

EM_Data

Data

Table 11-60. Asynchronous Write Cycle Specifications

Parameter

T

Description

EMIF clock period^[55]

Conditions

Min

30.3

T – 5

–

Typ

–

Max

Units

ns

Vdda 3.3 V

–

Tcel

EM_CEn low time

–

T + 5

ns

Taddrv

Taddrh

Twel

EM_CEn low to EM_Addr valid

Address hold time after EM_WEn high

EM_WEn low time

–

5

–

ns

T

–

ns

T – 5

–

T + 5

7

ns

Tdcev

Tdweh

EM_CEn low to data valid

Data hold time after EM_WEn high

–

ns

T

–

ns

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Automotive Family Datasheet

Figure 11-58. Synchronous Read Cycle Timing

Tcp/2

EM_Clock

EM_CEn

Tceld

Taddrv

Toeld

Tcehd

Taddriv

EM_Addr

EM_OEn

Address

Toehd

Tds

Data

EM_Data

Tadschd

Tadscld

EM_ ADSCn

Table 11-61. Synchronous Read Cycle Specifications

Parameter

T

Description

EMIF clock period^[56]

Conditions

Vdda 3.3 V

Min

30.3

T/2

Typ

–

Max

–

Units

ns

Tcp/2

EM_Clock pulse high

–

ns

Tceld

EM_CEn low to EM_Clock high

EM_Clock high to EM_CEn high

EM_Addr valid to EM_Clock high

EM_Clock high to EM_Addr invalid

EM_OEn low to EM_Clock high

EM_Clock high to EM_OEn high

Data valid before EM_OEn high

EM_ADSCn low to EM_Clock high

EM_Clock high to EM_ADSCn high

5

–

ns

Tcehd

Taddrv

Taddriv

Toeld

T/2 – 5

5

–

ns

–

ns

T/2 – 5

5

–

ns

–

ns

Toehd

Tds

T

–

ns

T + 15

5

–

ns

Tadscld

Tadschd

–

ns

T/2 – 5

–

ns

Note

56. Limited by GPIO output frequency, see .

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Figure 11-59. Synchronous Write Cycle Timing

Tcp/2

EM_Clock

EM_CEn

Tceld

Taddrv

Tweld

Tds

Tcehd

Taddriv

EM_Addr

Address

Twehd

EM_WEn

EM_Data

Tdh

Data

Tadschd

Tadscld

EM_ ADSCn

Table 11-62. Synchronous Write Cycle Specifications

Parameter

T

Description

EMIF clock Period^[57]

Conditions

Vdda 3.3 V

Min

Typ

–

Max

–

Units

ns

30.3

Tcp/2

EM_Clock pulse high

T/2

–

ns

Tceld

EM_CEn low to EM_Clock high

EM_Clock high to EM_CEn high

EM_Addr valid to EM_Clock high

EM_Clock high to EM_Addr invalid

EM_WEn low to EM_Clock high

EM_Clock high to EM_WEn high

Data valid before EM_Clock high

Data invalid after EM_Clock high

EM_ADSCn low to EM_Clock high

EM_Clock high to EM_ADSCn high

5

–

ns

Tcehd

Taddrv

Taddriv

Tweld

Twehd

Tds

T/2 – 5

–

ns

5

–

ns

T/2 – 5

–

ns

5

–

ns

T/2 – 5

–

ns

5

–

ns

Tdh

T

5

–

ns

Tadscld

Tadschd

–

ns

T/2 – 5

–

ns

Note

57. Limited by GPIO output frequency, see .

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11.8 PSoC System Resources

Specifications are valid for -40°C  Ta  125°C and Tj  150°C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except

where noted.

11.8.1 POR with Brown Out

For brown out detect in regulated mode, Vddd and Vdda must be  2.0 V. Brown out detect is available in externally regulated mode.

Table 11-63. Precise Power On Reset (PRES) with Brown Out DC Specifications

Parameter

PRESR

Description

Rising trip voltage

Falling trip voltage

Conditions

Factory trim

Min

1.64

1.62

Typ

–

Max

1.68

1.66

Units

V

PRESF

–

Table 11-64. Precise Power On Reset (PRES) with Brown Out AC Specifications

Parameter

PRES_TR Response time

V_DDD/V_DDAdroop rate

Description

Conditions

Min

–

Typ

–

Max

0.5

–

Units

µs

Sleep mode

–

5

V/sec

11.8.2 Voltage Monitors

Table 11-65. Voltage Monitors DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

LVI

Trip voltage

LVI_A/D_SEL[3:0] = 0000b

LVI_A/D_SEL[3:0] = 0001b

LVI_A/D_SEL[3:0] = 0010b

LVI_A/D_SEL[3:0] = 0011b

LVI_A/D_SEL[3:0] = 0100b

LVI_A/D_SEL[3:0] = 0101b

LVI_A/D_SEL[3:0] = 0110b

LVI_A/D_SEL[3:0] = 0111b

LVI_A/D_SEL[3:0] = 1000b

LVI_A/D_SEL[3:0] = 1001b

LVI_A/D_SEL[3:0] = 1010b

LVI_A/D_SEL[3:0] = 1011b

LVI_A/D_SEL[3:0] = 1100b

LVI_A/D_SEL[3:0] = 1101b

LVI_A/D_SEL[3:0] = 1110b

LVI_A/D_SEL[3:0] = 1111b

Trip voltage

1.68

1.89

2.14

2.38

2.62

2.87

3.11

3.35

3.59

3.84

4.08

4.32

4.56

4.83

5.05

5.30

5.57

1.73

1.95

2.20

2.45

2.71

2.95

3.21

3.46

3.70

3.95

4.20

4.45

4.70

4.98

5.21

5.47

5.75

1.77

2.01

2.27

2.53

2.79

3.04

3.31

3.56

3.81

4.07

4.33

4.59

4.84

5.13

5.37

5.63

5.92

V

HVI

Table 11-66. Voltage Monitors AC Specifications

Parameter

Description

Response time^[58]

Conditions

Min

Typ

Max

Units

–

1

µs

Note

58. Based on device characterization (Not production tested).

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11.8.3 Interrupt Controller

Table 11-67. Interrupt Controller AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Delay from Interrupt signal input to ISR Includes worse case completion of

-

25

Tcy CPU

code execution from ISR code

longest instruction DIV with 6

cycles

11.8.4 JTAG Interface

Table 11-68. JTAG Interface AC Specifications^[29]

Parameter

f_TCK

Description

TCK frequency

Conditions

3.3 V  V_DDD 5 V

1.71 V  V_DDD< 3.3 V

Min

–

Typ

Max

Units

MHz

ns

–

14^[59]

7^[59]

–

T_TDI_setup

TDI setup before TCK high

(T/10) –

5

T_TMS_setup TMS setup before TCK high

T/4

–

T_TDI_hold

T_TDO_valid

T_TDO_hold

TDI, TMS hold after TCK high

TCK low to TDO valid

T = 1/f_TCK max

2T/5

–

TDO hold after TCK high

T/4

Figure 11-60. JTAG Interface Timing

(1/f_TCK)

TCK

T_TDI_setup

T_TDI_hold

TDI

T_TDO_hold

T_TDO_valid

TDO

T_TMS_setup

T_TMS_hold

TMS

Document Number: 001-57330 Rev. *G

Page 126 of 143

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Automotive Family Datasheet

11.8.5 SWD Interface

Table 11-69. SWD Interface AC Specifications^[29]

Parameter

Description

SWDCLK frequency

Conditions

3.3 V  V_DDD 5 V

1.71 V  V_DDD< 3.3 V

1.71 V  V_DDD< 3.3 V,

SWD over USBIO pins

Min

–

Typ

–

Max

14^[60]

7^[60]

Units

MHz

f_SWDCK

–

5.5^[60]

T_SWDI_setup SWDIO input setup before SWDCK high T = 1/f_SWDCK max

T/4

–

T_SWDI_hold SWDIO input hold after SWDCK high

T_SWDO_valid SWDCK high to SWDIO output

T = 1/f_SWDCK max

2T/5

Figure 11-61. SWD Interface Timing

(1/f_SWDCK)

SWDCK

T_SWDI_setup

T_SWDI_hold

SWDIO

(PSoC input)

T_SWDO_valid

T_SWDO_hold

SWDIO

(PSoC output)

11.8.6 SWV Interface

Table 11-70. SWV Interface AC Specifications

[29]

Parameter

Description

Conditions

Min

Typ

Max

33

Units

SWV mode SWV bit rate

-

Mbit

Notes

59. f_TCK must also be no more than 1/3 CPU clock frequency.

60. f_SWDCK must also be no more than 1/3 CPU clock frequency.

Document Number: 001-57330 Rev. *G

Page 127 of 143

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Automotive Family Datasheet

11.9 Clocking

Specifications are valid for -40°C  Ta  125°C and Tj  150°C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except

where noted.

11.9.1 Internal Main Oscillator

Table 11-71. IMO DC Specifications

Parameter

Description

Supply current

Conditions

Min

Typ

Max

Units

62.6 MHz

–

600

500

300

200

180

150

µA

48 MHz

24 MHz – USB mode

24 MHz – non USB mode

12 MHz

With oscillator locking to USB bus

6 MHz

3 MHz

Figure 11-62. IMO Current vs. Frequency

Document Number: 001-57330 Rev. *G

Page 128 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

Table 11-72. IMO AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

IMO frequency stability (with factory trim)

62.6 MHz

–7

–5

–

7

5

%

48 MHz

24 MHz – Non USB mode

24 MHz – USB mode

12 MHz

–4

–

4

[61]

F

IMO

With oscillator locking to USB bus

–0.25

–3

–

0.25

3

–

6 MHz

–2

–

2

3 MHz

–2

–

2

3 MHz frequency stability after typical Typical (non-optimized) board

-

±2

-

PCB assembly post-reflow.

layout and 250 °C solder reflow.

Device may be calibrated after

assembly to improve performance.

[62]

Startup time

Fromenable(duringnormalsystem

operation)

–

13

µs

[62]

Jitter (peak to peak)

Jp–p

F = 24 MHz

F = 3 MHz

–

0.9

1.6

–

ns

[62]

Jitter (long term)

Jperiod

F = 24 MHz

F = 3 MHz

–

0.9

12

–

ns

Notes

61. F_IMOis measured after packaging, and thus accounts for substrate and die attach stresses.

62. Based on device characterization (Not production tested).

Document Number: 001-57330 Rev. *G

Page 129 of 143

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Automotive Family Datasheet

Figure 11-63. IMO Frequency Variation vs. Temperature

Figure 11-64. IMO Frequency Variation vs. V_CC

Document Number: 001-57330 Rev. *G

Page 130 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

11.9.2 Internal Low Speed Oscillator

Table 11-73. ILO DC Specifications

Parameter

Description

Conditions

= 1 kHz

Min

Typ

–

Max

1.7

2.6

15

Units

µA

[63]

Operating current

F

–

-

OUT

I

= 33 kHz

–

µA

CC

= 100 kHz

–

µA

[63]

Leakage current

-40°C  Ta  85°C and Tj  100°C

Power down mode

2.0

nA

-40°C  Ta  125°C and Tj  150°C

Power down mode

-

200

nA

Table 11-74. ILO AC Specifications

Parameter

Description

Conditions

Turbo mode

Min

Typ

Max

Units

Startup time

-

2

ms

ILO frequencies (trimmed)

-40°C  Ta  85°C and Tj  100°C

100 kHz

45

100

1

200

2

kHz

1 kHz

0.5

Filo

ILO frequencies (untrimmed)

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

100 kHz

30

100

1

300

3.5

kHz

1 kHz

0.3

ILO frequencies (trimmed)

100 kHz

45

-

450

5

kHz

1 kHz

0.5

Filo

ILO frequencies (untrimmed)

100 kHz

1 kHz

150

0.3

-

500

6.5

kHz

Figure 11-65. ILO Frequency Variation vs. V_DD

Note

63. This value is calculated, not measured.

64. Based on device characterization (Not production tested).

Document Number: 001-57330 Rev. *G

Page 131 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

11.9.3 External Crystal Oscillator

[65]

Table 11-75. 32 kHz External Crystal DC Specifications

Parameter

Description

Operating current

Conditions

Min

Typ

Max

Units

Icc

Low power mode; C = 6 pF;

–

0.25

1.0

µA

L

-40°C  Ta  125°C and Tj  150°C

DL

Drive level

Low-power mode; C = 6 pF

–

1

µW

L

Table 11-76. 32 kHz External Crystal AC Specifications

Parameter

Description

Conditions

Min

–

Typ

32.768

1

Max

–

Units

kHz

s

F

Frequency

Ton

Startup time

High power mode

–

Table 11-77. MHz ECO AC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

F

Crystal frequency range

4

–

25

MHz

11.9.4 External Clock Reference

Table 11-78. External Clock Reference AC Specifications

Parameter

Description

External frequency range

Input duty cycle range

Input edge rate

Min

0

Typ

–

Max

33

70

–

Units

MHz

%

Measured at V

/2

30

50

–

DDIO

V

to V

0.51

V/ns

IL

IH

11.9.5 Phase-Locked Loop

Table 11-79. PLL DC Specifications

Parameter

Description

PLL operating current

Conditions

Min

–

Typ

400

200

Max

–

Units

µA

I

In = 3 MHz, Out = 67 MHz

In = 3 MHz, Out = 24 MHz

DD

–

µA

Table 11-80. PLL AC Specifications

Parameter

Description

Conditions

Min

1

Typ

Max

48

Units

MHz

µs

[66]

Fpllin

PLL input frequency

Output of Prescalar

-

[67]

PLL intermediate frequency

1

3

[66]

Fpllout

PLL output frequency

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

24

-

67

50

Lock time at startup

250

400

[29]

Jperiod-rms Jitter (rms)

-40°C  Ta  85°C and Tj  100°C

-40°C  Ta  125°C and Tj  150°C

-

ps

-

ps

Notes

65. Based on device characterization (not production tested).

66. This specification is guaranteed by testing the PLL across the specified range using the IMO as the source for the PLL.

67. PLL input divider, Q, must be set so that the input frequency is divided down to the intermediate frequency range. Value for Q ranges from 1 to 16.

Document Number: 001-57330 Rev. *G

Page 132 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

12. Ordering Information

In addition to the features listed in Table 12-1, every CY8C36 device includes: a precision on-chip voltage reference, precision

2

oscillators, Flash, ECC, DMA, a fixed function I C, 4 KB trace RAM, JTAG/SWD programming and debug, external memory interface,

and more. In addition to these features, the flexible UDBs and Analog Subsection support a wide range of peripherals. To assist you

in selecting the ideal part, PSoC Creator makes a part recommendation after you choose the components required by your application.

All CY8C36 derivatives incorporate device and Flash security in user-selectable security levels; see TRM for details.

Table 12-1. CY8C36 Family with Single Cycle 8051

[69]

MCU Core

Analog

Digital

I/O

Part Number

Package JTAG ID^[70]

32 KB Flash

CY8C3645AXE-169 50 32

CY8C3665AXA-010 67 32

CY8C3665AXA-016 67 32

CY8C3665PVA-007 67 32

CY8C3665PVA-008 67 32

CY8C3665PVA-080 67 32

64 KB Flash

4

1

-

12-bit Del-Sig

4

2

✔

20

4

✔

-

72 62

70 62

72 62

31 25

29 25

8

4

2

0

2

0

100-TQFP 0x1E0A9069

100-TQFP 0x1E00A069

100-TQFP 0x1E010069

48-SSOP 0x1E007069

48-SSOP 0x1E008069

48-SSOP 0x1E050069

-

✔

-

✔

-

✔

-

✔

CY8C3646AXE-170 50 64

CY8C3646AXE-178 50 64

CY8C3646PVE-171 50 64

CY8C3646PVE-179 50 64

CY8C3666AXA-036 67 64

CY8C3666AXA-037 67 64

CY8C3666AXA-052 67 64

CY8C3666PVA-022 67 64

CY8C3666PVA-026 67 64

CY8C3666PVA-180 67 64

8

2

-

12-bit Del-Sig

4

2

4

2

✔

24

4

-

✔

-

70 62

29 25

72 62

70 62

31 25

29 25

8

4

8

4

0

2

0

2

0

100-TQFP 0x1E0AA069

100-TQFP 0x1E0B2069

48-SSOP 0x1E0AB069

48-SSOP 0x1E0B3069

100-TQFP 0x1E024069

100-TQFP 0x1E025069

100-TQFP 0x1E034069

48-SSOP 0x1E016069

48-SSOP 0x1E01A069

48-SSOP 0x1E0B4069

-

✔

-

✔

-

✔

-

✔

-

✔

-

✔

-

✔

Notes

68. UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or

multiple UDBs. Multiple functions can share a single UDB. See the “Example Peripherals” section on page 40 for more information on how UDBs may be used.

69. The I/O Count includes all types of digital I/O: GPIO, SIO, and the two USB I/O. See the ““I/O System and Routing” section on page 33” for details on the functionality

of each of these types of I/O.

70. The JTAG ID has three major fields. The most significant nibble (left digit) is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID.

Document Number: 001-57330 Rev. *G

Page 133 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

12.1 Part Numbering Conventions

PSoC 3 devices follow the part numbering convention described below. All fields are single character alphanumeric (0, 1, 2, …, 9, A,

B, …, Z) unless stated otherwise.

CY8Cabcdefg-xxx

 a: Architecture

 3: PSoC 3

 5: PSoC 5

 ef: Package Code

 Two character alphanumeric

 AX: TQFP

 LT: QFN

 PV: SSOP

 b: Family Group within Architecture

 2: CY8C32 family

 g: Temperature Range

 4: CY8C34 family

 6: CY8C36 family

 8: CY8C38 family

 C: commercial 0°C to 70°C

 I: industrial -40°C to 85°C

 A: automotive -40°C to 85°C

 E: extended -40°C to 125°C

 c: Speed Grade

 4: 50 MHz

 xxx: Peripheral Set

 6: 67 MHz

 Three character numeric

 No meaning is associated with these three characters.

 d: Flash Capacity

 4: 16 KB

 5: 32 KB

 6: 64 KB

CY8C

3

6

P

V

A

-

x x x

Example

Cypress Prefix

Architecture

3: PSoC3

6: CY8C36 Family

6: 67 MHz

Family Group within Architecture

Speed Grade

6: 64 KB

Flash Capacity

PV: SSOP

Package Code

A: Automotive

Temperature Range

Peripheral Set

All devices in the PSoC 3 CY8C36 family comply to RoHS-6 specifications, demonstrating the commitment by Cypress to lead-free

products. Lead (Pb) is an alloying element in solders that has resulted in environmental concerns due to potential toxicity. Cypress

uses nickel-palladium-gold (NiPdAu) technology for the majority of leadframe-based packages.

A high level review of the Cypress Pb-free position is available on our website. Specific package information is also available. Package

Material Declaration Datasheets (PMDDs) identify all substances contained within Cypress packages. PMDDs also confirm the

absence of many banned substances. The information in the PMDDs will help Cypress customers plan for recycling or other "end of

life" requirements.

Document Number: 001-57330 Rev. *G

Page 134 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

13. Packaging

Table 13-1. Package Characteristics

Parameter

Description

Conditions

Min

–40

–

Typ

25.00

–

Max

125

150

–

Units

°C

T

Operating ambient temperature

Operating junction temperature

A

T

°C

J

Package  (48-pin SSOP)

49

°C/W

JA

JC

JA

Package  (100-pin TQFP)

–

34

–

JA

Package  (48-pin SSOP)

–

24

–

JC

Package  (100-pin TQFP)

–

10

–

JC

Table 13-2. Solder Reflow Peak Temperature

Maximum Peak

Package

Maximum Time at Peak

Temperature

48-pin SSOP

100-pin TQFP

260 °C

30 seconds

Table 13-3. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2

Package

MSL

48-pin SSOP

100-pin TQFP

MSL 3

Figure 13-1. 48-pin (300 mil) SSOP Package Outline

51-85061 *F

Document Number: 001-57330 Rev. *G

Page 135 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

Figure 13-2. 100-pin TQFP (14 × 14 × 1.4 mm) Package Outline

51-85048 *I

Document Number: 001-57330 Rev. *G

Page 136 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

Table 14-1. Acronyms Used in this Document (continued)

14. Acronyms

Acronym

FIR

Description

finite impulse response, see also IIR

flash patch and breakpoint

full-speed

Table 14-1. Acronyms Used in this Document

Acronym

abus

Description

FPB

FS

analog local bus

ADC

AG

analog-to-digital converter

analog global

GPIO

general-purpose input/output, applies to a PSoC

AHB

AMBA (advanced microcontroller bus archi-

tecture) high-performance bus, an ARM data

transfer bus

HVI

IC

high-voltage interrupt, see also LVI, LVD

integrated circuit

ALU

arithmetic logic unit

IDAC

IDE

current DAC, see also DAC, VDAC

integrated development environment

AMUXBUS analog multiplexer bus

2

API

application programming interface

I C, or IIC

Inter-Integrated Circuit, a communications

protocol

APSR

application program status register

advanced RISC machine, a CPU architecture

automatic thump mode

IIR

infinite impulse response, see also FIR

internal low-speed oscillator, see also IMO

internal main oscillator, see also ILO

integral nonlinearity, see also DNL

input/output, see also GPIO, DIO, SIO, USBIO

initial power-on reset

®

ARM

ILO

IMO

INL

ATM

BW

bandwidth

CAN

Controller Area Network, a communications

protocol

I/O

CMRR

CPU

common-mode rejection ratio

central processing unit

IPOR

IPSR

IRQ

ITM

LCD

LIN

interrupt program status register

interrupt request

CRC

cyclic redundancy check, an error-checking

protocol

instrumentation trace macrocell

liquid crystal display

DAC

DFB

DIO

digital-to-analog converter, see also IDAC, VDAC

digital filter block

Local Interconnect Network, a communications

protocol.

digital input/output, GPIO with only digital

capabilities, no analog. See GPIO.

LR

link register

DMA

DNL

direct memory access, see also TD

differential nonlinearity, see also INL

do not use

LUT

LVD

LVI

lookup table

low-voltage detect, see also LVI

low-voltage interrupt, see also HVI

low-voltage transistor-transistor logic

multiply-accumulate

DNU

DR

port write data registers

digital system interconnect

data watchpoint and trace

error correcting code

LVTTL

MAC

MCU

MISO

NC

DSI

DWT

ECC

ECO

EEPROM

microcontroller unit

master-in slave-out

external crystal oscillator

no connect

electrically erasable programmable read-only

memory

NMI

nonmaskable interrupt

non-return-to-zero

NRZ

NVIC

NVL

opamp

PAL

EMI

electromagnetic interference

external memory interface

end of conversion

nested vectored interrupt controller

nonvolatile latch, see also WOL

operational amplifier

EMIF

EOC

EOF

EPSR

ESD

ETM

end of frame

programmable array logic, see also PLD

program counter

execution program status register

electrostatic discharge

embedded trace macrocell

PC

PCB

PGA

printed circuit board

programmable gain amplifier

Document Number: 001-57330 Rev. *G

Page 137 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

Table 14-1. Acronyms Used in this Document (continued)

Acronym Description

PHUB

Table 14-1. Acronyms Used in this Document (continued)

Acronym

SOF

Description

peripheral hub

physical layer

start of frame

PHY

PICU

PLA

SPI

Serial Peripheral Interface, a communications

protocol

port interrupt control unit

programmable logic array

programmable logic device, see also PAL

phase-locked loop

SR

slew rate

SRAM

SRES

SWD

SWV

TD

static random access memory

software reset

PLD

PLL

serial wire debug, a test protocol

single-wire viewer

PMDD

POR

PRES

PRS

PS

package material declaration data sheet

power-on reset

transaction descriptor, see also DMA

total harmonic distortion

transimpedance amplifier

technical reference manual

transistor-transistor logic

transmit

precise low-voltage reset

pseudo random sequence

port read data register

THD

TIA

TRM

TTL

®

PSoC

PSRR

PWM

RAM

RISC

RMS

RTC

RTL

Programmable System-on-Chip™

power supply rejection ratio

pulse-width modulator

TX

UART

Universal Asynchronous Transmitter Receiver, a

communications protocol

random-access memory

reduced-instruction-set computing

root-mean-square

UDB

universal digital block

Universal Serial Bus

USB

real-time clock

USBIO

USB input/output, PSoC pins used to connect to

a USB port

register transfer language

remote transmission request

receive

RTR

RX

VDAC

WDT

voltage DAC, see also DAC, IDAC

watchdog timer

SAR

SC/CT

SCL

successive approximation register

switched capacitor/continuous time

WOL

write once latch, see also NVL

watchdog timer reset

external reset I/O pin

crystal

WRES

XRES

XTAL

2

I C serial clock

2

SDA

S/H

I C serial data

sample and hold

15. Reference Documents

SINAD

SIO

signal to noise and distortion ratio

PSoC® 3, PSoC® 5 Architecture TRM

PSoC® 3 Registers TRM

special input/output, GPIO with advanced

features. See GPIO.

SOC

start of conversion

Document Number: 001-57330 Rev. *G

Page 138 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

16. Document Conventions

16.1 Units of Measure

Table 16-1. Units of Measure

Symbol

°C

Unit of Measure

degrees Celsius

decibels

dB

fF

femtofarads

hertz

Hz

KB

kbps

Khr

kHz

k

1024 bytes

kilobits per second

kilohours

kilohertz

kilohms

ksps

LSB

Mbps

MHz

M

Msps

µA

kilosamples per second

least significant bit

megabits per second

megahertz

megaohms

megasamples per second

microamperes

microfarads

microhenrys

microseconds

microvolts

µF

µH

µs

µV

µW

mA

ms

mV

nA

microwatts

milliamperes

milliseconds

millivolts

nanoamperes

nanoseconds

nanovolts

ns

nV



ohms

pF

picofarads

ppm

ps

parts per million

picoseconds

seconds

s

sps

sqrtHz

V

samples per second

square root of hertz

volts

Document Number: 001-57330 Rev. *G

Page 139 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

17. Revision History

Description Title: PSoC^®3: CY8C36 Automotive Family Datasheet, Programmable System-on-Chip (PSoC^®)

Document Number: 001-57330

Submission

Date

Orig. of

Change

Revision

ECN

Description of Change

**

2800070

2921624

01/05/10

SECA

MKEA

New data sheet

*A

04/26/2010

Updated Active Mode Idd values in Table 11-2

Updated Boost AC and DC specifications

Updated solder paste reflow temperature (Table 11-3)

Moved Filo spec from ILO DC to ILO AC table

Updated Figure 7-14, Interrupt and DMA processing

Added Bytes column in Tables 4-1 and 4-5

Updated Figure 6-3, Power mode transitions

Updated JTAG and SWD specifications

Updated Interrupt Vector table

Updated Sales links

Updated PCB Schematic

Updated Vbias spec

Added UDBs subsection under 11.6 Digital Peripherals

Updated Iout parameter in LCD Direct Drive DC Specs table

Added footnote in PLL AC Specification table

Added Load regulation and Line regulation parameters to Inductive Boost

Regulator DC Specifications table

Updated Icc parameter in LCD Direct Drive DC Specs table

Updated Tstartup parameter in AC Specifications table

Updated LVD in Tables 6-2 and 6-3

In page 1, updated internal oscillator range under Precision programmable

clocking to start from 3 MHz

Updated Pin Descriptions section and modified Figures 6-6, 6-8, 6-9

Added PLL intermediate frequency row with footnote in PLL AC Specs table

Added bullets on CapSense in page 1; added CapSense column in Section

Updated Figure 2-6 (PCB Layout)

Updated Tstartup values in Table 11-3

Updated IMO frequency

Updated section 5.2 and Table 11-2 to correct suggestion of execution from

Flash

Updated Vref specs in Table 11-21.

Updated IDAC uncompensated gain error in Table 11-25.

Updated Tresp, high and low power modes, in Table 11-24.

Updated Delay from Interrupt signal input to ISR code execution from ISR code

in Table 72.

Updated sleep wakeup time in Table 6-3 and Tsleep in Table 11-3.

Updated SNR condition in Table 11-20

*B

*C

3490494

3994809

01/11/2012

05/08/2013

GIR

Updated Figure 6-7 on page 34

KPAT

Updated all tables in Electrical Specifications.

Updated Ordering Information (Updated part numbers, JTAG ID).

Removed all references of Vboost across the document.

*D

4047900

07/02/2013

RASB

Changed status from Preliminary to Final.

Updated Features.

Updated Architectural Overview.

Updated Memory.

Updated Analog Subsystem.

Updated Electrical Specifications.

Document Number: 001-57330 Rev. *G

Page 140 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

17. Revision History (continued)

Description Title: PSoC^®3: CY8C36 Automotive Family Datasheet, Programmable System-on-Chip (PSoC^®)

Document Number: 001-57330

Submission

Date

Orig. of

Change

Revision

ECN

Description of Change

*E

4109902

08/31/2013

NFB /

ANMD

Updated Features.

Updated Architectural Overview:

Added Note 4 and referred the same note in features in “The heart of the analog

subsystem is a fast, accurate, configurable delta-sigma ADC with these

features”.

Updated Pinouts:

Updated Figure 2-5.

Updated Memory:

Updated EEPROM:

Updated description.

Updated Nonvolatile Latches (NVLs):

Updated Table 5-2 and Table 5-3.

Updated Memory Map:

Updated I/O Port SFRs:

Updated xdata Space:

Updated Table 5-5.

Updated Digital Subsystem:

Updated Universal Digital Block:

Updated PLD Module:

Updated Figure 7-3.

2

Updated I C:

Updated description.

Updated Analog Subsystem:

Updated Programmable SC/CT Blocks:

Updated PGA:

Updated Table 8-3.

Updated Electrical Specifications:

Updated Device Level Specifications:

Updated Table 11-2.

Updated Inputs and Outputs:

Updated GPIO:

Removed figure “GPIO Output Rise and Fall Times, Fast Strong Mode,

V

= 3.3 V, 25 pF Load” and figure “GPIO Output Rise and Fall Times, Slow

DDIO

Strong Mode, V

= 3.3 V, 25 pF Load”.

DDIO

Updated Analog Peripherals:

Updated Delta-Sigma ADC:

Updated Table 11-17.

Updated Table 11-18.

Updated Voltage Reference:

Updated Table 11-20.

Updated Programmable Gain Amplifier:

Updated Table 11-33.

Updated Memory:

Updated Flash:

Updated Table 11-52.

Updated Packaging:

spec 51-85048 – Changed revision from *G to *H.

Updated in new template.

Document Number: 001-57330 Rev. *G

Page 141 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

17. Revision History (continued)

Description Title: PSoC^®3: CY8C36 Automotive Family Datasheet, Programmable System-on-Chip (PSoC^®)

Document Number: 001-57330

Submission

Date

Orig. of

Change

Revision

ECN

Description of Change

*F

4174914

10/26/2013

NFB /

ANMD

Updated Pinouts:

Added Note 7 and referred the same note in 100 mA in description.

Updated Electrical Specifications:

Updated Absolute Maximum Ratings:

Updated Table 11-1.

Added Note 17 and referred the same note in Table 11-1.

Added Note 19 and referred the same note in Ivddio parameter in Table 11-1.

Updated Analog Peripherals:

Updated Opamp:

Updated Table 11-15.

Updated Voltage Reference:

Updated Table 11-20.

Updated Packaging:

Updated Table 13-1.

*G

4281204

02/14/2014

ANMD

Updated Digital Subsystem:

Updated I C:

2

Updated Note 16.

Updated Electrical Specifications:

Updated Analog Peripherals:

Updated Delta-Sigma ADC:

Updated Table 11-17:

Updated Conditions of Vos parameter.

Updated Memory:

Updated Flash:

Updated Table 11-52:

Added Note 54 and referred the same note in “Flash data retention time,

retention period measured from last erase cycle” in description column.

Replaced “Tjavg” with “T ” in last row in conditions column.

A

Updated Packaging:

spec 51-85048 – Changed revision from *H to *I.

Completing Sunset Review.

Document Number: 001-57330 Rev. *G

Page 142 of 143

PSoC^®3: CY8C36

Automotive Family Datasheet

18. Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office

closest to you, visit us at Cypress Locations.

®

Products

PSoC Solutions

Automotive

cypress.com/go/automotive

cypress.com/go/clocks

cypress.com/go/interface

cypress.com/go/powerpsoc

cypress.com/go/plc

psoc.cypress.com/solutions

PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Clocks & Buffers

Interface

Cypress Developer Community

Lighting & Power Control

Community | Forums | Blogs | Video | Training

Technical Support

Memory

cypress.com/go/memory

cypress.com/go/psoc

cypress.com/go/support

PSoC

Touch Sensing

USB Controllers

Wireless/RF

cypress.com/go/touch

cypress.com/go/USB

cypress.com/go/wireless

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for

medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-57330 Rev. *G

Revised February 14, 2014

Page 143 of 143

CapSense^®, PSoC^®3, PSoC^®5, and PSoC^®Creator™ are trademarks and PSoC^®is a registered trademark of Cypress Semiconductor Corp. ARM is a registered trademark, and Keil, and RealView

are trademarks, of ARM Limited. All other trademarks or registered trademarks referenced herein are property of the respective corporations.


型号：	CY8C3666PVA-026
厂家：	CYPRESS
描述：	Multifunction Peripheral, CMOS, PDSO48, 0.300 INCH, ROHS COMPLIANT, SSOP-48 时钟光电二极管
文件：	总143页 (文件大小：3745K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY8C3666PVA-026 [CYPRESS]

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