CY7C68013A_0905_技术文档

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

EZ-USB FX2LP™ USB Microcontroller

High Speed USB Peripheral Controller

■ GPIF (General Programmable Interface)

❐ Enables direct connection to most parallel interfaces

❐ Programmable waveform descriptors and configuration

registers to define waveforms

❐ Supports multiple Ready (RDY) inputs and Control (CTL)

outputs

1. Features (CY7C68013A/14A/15A/16A)

■ USB 2.0 USB IF High Speed Certified (TID # 40460272)

■ Single Chip Integrated USB 2.0 Transceiver, Smart SIE, and

Enhanced 8051 Microprocessor

■ Fit, Form, and Function Compatible with the FX2

❐ Pin compatible

❐ Object-code-compatible

■ Integrated, Industry Standard Enhanced 8051

❐ 48 MHz, 24 MHz, or 12 MHz CPU operation

❐ Four clocks per instruction cycle

❐ Two USARTS

❐ Functionally Compatible (FX2LP is a superset)

■ Ultra Low Power: I_CCNo More than 85 mA in any Mode

❐ Ideal for bus and battery powered applications

❐ Three counter/timers

❐ Expanded interrupt system

❐ Two data pointers

■ Software: 8051 Code Runs from:

■ 3.3V Operation with 5V Tolerant Inputs

❐ Internal RAM, which is downloaded through USB

❐ Internal RAM, which is loaded from EEPROM

❐ External memory device (128 pin package)

■ Vectored USB Interrupts and GPIF/FIFO Interrupts

■ Separate Data Buffers for the Setup and Data Portions of a

CONTROL Transfer

■ 16 KBytes of On-Chip Code/Data RAM

■ Integrated I²C Controller, Runs at 100 or 400 kHz

■ Four Programmable BULK/INTERRUPT/ISOCHRONOUS

Endpoints

❐ Buffering options: double, triple, and quad

■ Four Integrated FIFOs

❐ Integrated glue logic and FIFOs lower system cost

❐ Automatic conversion to and from 16-bit buses

❐ Master or slave operation

❐ Uses external clock or asynchronous strobes

❐ Easy interface to ASIC and DSP ICs

■ Additional Programmable (BULK/INTERRUPT) 64 Byte

Endpoint

■ 8-bit or 16-bit External Data Interface

■ Smart Media Standard ECC Generation

■ Available in Commercial and Industrial Temperature Grade

(all packages except VFBGA)

Cypress Semiconductor Corporation

Document #: 38-08032 Rev. *M

•

198 Champion Court

•

San Jose, CA 95134-1709

•408-943-2600

Revised May 22, 2009

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Logic Block Diagram

High performance micro

using standard tools

with lower-power options

24 MHz

Ext. XTAL

FX2LP

I²C

/0.5

/1.0

/2.0

8051 Core

x20

PLL

Master

VCC

1.5k

12/24/48 MHz,

four clocks/cycle

Abundant I/O

including two USARTS

Additional I/Os (24)

connected for

full speed

General

ADDR (9)

programmable I/F

to ASIC/DSP or bus

standards such as

D+

D–

GPIF

USB

2.0

XCVR

CY

Smart

USB

16 KB

RAM

RDY (6)

CTL (6)

ATAPI, EPP, etc.

ECC

1.1/2.0

Engine

Integrated

full speed and

high speed

XCVR

Up to 96 MBytes/s

burst rate

4 kB

FIFO

8/16

Enhanced USB core

Simplifies 8051 code

“Soft Configuration”

Easy firmware changes

FIFO and endpoint memory

(master or slave operation)

Cypress has created a cost effective solution that provides

superior time-to-market advantages with low power to enable

bus powered applications.

1.1 Features (CY7C68013A/14A only)

■ CY7C68014A: Ideal for Battery Powered Applications

❐ Suspend current: 100 μA (typ)

The ingenious architecture of FX2LP results in data transfer

rates of over 53 Mbytes per second, the maximum allowable

USB 2.0 bandwidth, while still using a low cost 8051 microcon-

troller in a package as small as a 56 VFBGA (5 mm x 5 mm).

Because it incorporates the USB 2.0 transceiver, the FX2LP is

more economical, providing a smaller footprint solution than

USB 2.0 SIE or external transceiver implementations. With

EZ-USB FX2LP, the Cypress Smart SIE handles most of the

USB 1.1 and 2.0 protocol in hardware, freeing the embedded

microcontroller for application specific functions and decreasing

development time to ensure USB compatibility.

■ CY7C68013A: Ideal for Non-battery Powered Applications

❐ Suspend current: 300 μA (typ)

■ Available in Five Pb-free Packages with Up to 40 GPIOs

❐ 128-pinTQFP(40GPIOs),100-pinTQFP(40GPIOs),56-pin

QFN (24 GPIOs), 56-pin SSOP (24 GPIOs), and 56-pin VF-

BGA (24 GPIOs)

1.2 Features (CY7C68015A/16A only)

■ CY7C68016A: Ideal for Battery Powered Applications

❐ Suspend current: 100 μA (typ)

The General Programmable Interface (GPIF) and Master/Slave

Endpoint FIFO (8-bit or 16-bit data bus) provides an easy and

glueless interface to popular interfaces such as ATA, UTOPIA,

EPP, PCMCIA, and most DSP/processors.

■ CY7C68015A: Ideal for Non-battery Powered Applications

❐ Suspend current: 300 μA (typ)

■ Available in Pb-free 56-pin QFN Package (26 GPIOs)

❐ TwomoreGPIOsthanCY7C68013A/14Aenablingadditional

features in same footprint

The FX2LP draws less current than the FX2 (CY7C68013), has

double the on-chip code/data RAM, and is fit, form and function

compatible with the 56, 100, and 128 pin FX2.

Cypress’s EZ-USB FX2LP™ (CY7C68013A/14A) is a low power

version of the EZ-USB FX2™ (CY7C68013), which is a highly

integrated, low power USB 2.0 microcontroller. By integrating the

USB 2.0 transceiver, serial interface engine (SIE), enhanced

8051 microcontroller, and a programmable peripheral interface

in a single chip,

Five packages are defined for the family: 56VFBGA, 56 SSOP,

56 QFN, 100 TQFP, and 128 TQFP.

Document #: 38-08032 Rev. *M

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2. Applications

Figure 1. Crystal Configuration

■ Portable video recorder

■ MPEG/TV conversion

■ DSL modems

24 MHz

C1

C2

12 pf

■ ATA interface

20 × PLL

■ Memory card readers

■ Legacy conversion devices

■ Cameras

12-pF capacitor values assumes a trace capacitance

of 3 pF per side on a four-layer FR4 PCA

■ Scanners

The CLKOUT pin, which can be three-stated and inverted using

internal control bits, outputs the 50% duty cycle 8051 clock, at

the selected 8051 clock frequency: 48 MHz, 24 MHz, or 12 MHz.

■ Home PNA

■ Wireless LAN

3.2.2 USARTS

■ MP3 players

FX2LP contains two standard 8051 USARTs, addressed through

Special Function Register (SFR) bits. The USART interface pins

are available on separate I/O pins, and are not multiplexed with

port pins.

■ Networking

The “Reference Designs” section of the Cypress web site

provides additional tools for typical USB 2.0 applications. Each

reference design comes complete with firmware source and

object code, schematics, and documentation. Visit

www.cypress.com for more information.

UART0 and UART1 can operate using an internal clock at

230 KBaud with no more than 1% baud rate error. 230 KBaud

operation is achieved by an internally derived clock source that

generates overflow pulses at the appropriate time. The internal

clock adjusts for the 8051 clock rate (48 MHz, 24 MHz, and

12 MHz) such that it always presents the correct frequency for

230 KBaud operation.^[1]

3. Functional Overview

3.1 USB Signaling Speed

FX2LP operates at two of the three rates defined in the USB

Specification Revision 2.0, dated April 27, 2000:

3.2.3 Special Function Registers

Certain 8051 SFR addresses are populated to provide fast

access to critical FX2LP functions. These SFR additions are

shown in Table 1 on page 4. Bold type indicates non standard,

enhanced 8051 registers. The two SFR rows that end with “0”

and “8” contain bit addressable registers. The four I/O ports A to

D use the SFR addresses used in the standard 8051 for ports 0

to 3, which are not implemented in FX2LP. Because of the faster

and more efficient SFR addressing, the FX2LP I/O ports are not

addressable in external RAM space (using the MOVX

instruction).

■ Full speed, with a signaling bit rate of 12 Mbps

■ High speed, with a signaling bit rate of 480 Mbps.

FX2LP does not support the low speed signaling mode of

1.5 Mbps.

3.2 8051 Microprocessor

The 8051 microprocessor embedded in the FX2LP family has

256 bytes of register RAM, an expanded interrupt system, three

timer/counters, and two USARTs.

2

3.3 I C Bus

3.2.1 8051 Clock Frequency

FX2LP supports the I²C bus as a master only at 100/400 KHz.

SCL and SDA pins have open-drain outputs and hysteresis

inputs. These signals must be pulled up to 3.3V, even if no I²C

device is connected.

FX2LP has an on-chip oscillator circuit that uses an external

24 MHz (±100 ppm) crystal with the following characteristics:

■ Parallel resonant

■ Fundamental mode

3.4 Buses

■ 500 μW drive level

All packages, 8-bit or 16-bit “FIFO” bidirectional data bus, multi-

plexed on I/O ports B and D. 128-pin package: adds 16-bit

output-only 8051 address bus, 8-bit bidirectional data bus.

■ 12 pF (5% tolerance) load capacitors

An on-chip PLL multiplies the 24 MHz oscillator up to 480 MHz,

as required by the transceiver/PHY and internal counters divide

it down for use as the 8051 clock. The default 8051 clock

frequency is 12 MHz. The clock frequency of the 8051 can be

changed by the 8051 through the CPUCS register, dynamically.

Note

1. 115 KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a “1” for UART0, UART1, or both respectively.

Document #: 38-08032 Rev. *M

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Table 1. Special Function Registers

x

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

8x

IOA

9x

IOB

Ax

Bx

Cx

Dx

Ex

Fx

IOC

IOD

SCON1

SBUF1

PSW

ACC

B

SP

EXIF

INT2CLR

INT4CLR

IOE

DPL0

DPH0

DPL1

DPH1

DPS

MPAGE

OEA

OEB

OEC

OED

OEE

PCON

TCON

TMOD

TL0

SCON0

SBUF0

IE

IP

T2CON

EICON

EIE

EIP

AUTOPTRH1

AUTOPTRL1

reserved

EP2468STAT

EP24FIFOFLGS

EP68FIFOFLGS

EP01STAT

GPIFTRIG

RCAP2L

RCAP2H

TL2

TL1

TH0

TH1

AUTOPTRH2

AUTOPTRL2

reserved

GPIFSGLDATH

GPIFSGLDATLX

TH2

CKCON

AUTOPTRSET-UP GPIFSGLDATLNOX

Two control bits in the USBCS (USB Control and Status) register,

control the ReNumeration process: DISCON and RENUM. To

simulate a USB disconnect, the firmware sets DISCON to 1. To

reconnect, the firmware clears DISCON to 0.

3.5 USB Boot Methods

During the power up sequence, internal logic checks the I²C port

for the connection of an EEPROM whose first byte is either 0xC0

or 0xC2. If found, it uses the VID/PID/DID values in the EEPROM

in place of the internally stored values (0xC0), or it boot-loads the

EEPROM contents into internal RAM (0xC2). If no EEPROM is

detected, FX2LP enumerates using internally stored descriptors.

The default ID values for FX2LP are VID/PID/DID (0x04B4,

0x8613, 0xAxxx where xxx = Chip revision).^[2]

Before reconnecting, the firmware sets or clears the RENUM bit

to indicate whether the firmware or the Default USB Device

handles device requests over endpoint zero: if RENUM = 0, the

Default USB Device handles device requests; if RENUM = 1, the

firmware services the requests.

Table 2. Default ID Values for FX2LP

Default VID/PID/DID

3.7 Bus-Powered Applications

The FX2LP fully supports bus powered designs by enumerating

with less than 100 mA as required by the USB 2.0 specification.

Vendor ID

Product ID

0x04B4 Cypress Semiconductor

0x8613 EZ-USB FX2LP

3.8 Interrupt System

Device release 0xAnnn Depends on chip revision

(nnn = chip revision where first

silicon = 001)

3.8.1 INT2 Interrupt Request and Enable Registers

FX2LP implements an autovector feature for INT2 and INT4.

There are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF)

vectors. See EZ-USB Technical Reference Manual (TRM) for

more details.

3.6 ReNumeration

Because the FX2LP’s configuration is soft, one chip can take on

the identities of multiple distinct USB devices.

3.8.2 USB Interrupt Autovectors

When first plugged into USB, the FX2LP enumerates automati-

cally and downloads firmware and USB descriptor tables over

the USB cable. Next, the FX2LP enumerates again, this time as

a device defined by the downloaded information. This patented

two step process called ReNumeration™ happens instantly when

the device is plugged in, without a hint that the initial download

step has occurred.

The main USB interrupt is shared by 27 interrupt sources. To

save the code and processing time that is required to identify the

individual USB interrupt source, the FX2LP provides a second

level of interrupt vectoring, called Autovectoring. When a USB

interrupt is asserted, the FX2LP pushes the program counter to

its stack, and then jumps to the address 0x0043 where it expects

to find a “jump” instruction to the USB Interrupt service routine.

Note

2

2. The I C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly.

Document #: 38-08032 Rev. *M

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The FX2LP jump instruction is encoded as follows:

Table 3. INT2 USB Interrupts

USB INTERRUPT TABLE FOR INT2

Source

Priority

1

INT2VEC Value

Notes

00

04

08

0C

10

14

18

1C

20

24

28

2C

30

34

38

3C

40

44

48

4C

50

54

58

5C

60

64

68

6C

70

74

78

7C

SUDAV

Setup Data Available

2

SOF

Start of Frame (or microframe)

Setup Token Received

3

SUTOK

4

SUSPEND

USB RESET

HISPEED

EP0ACK

USB Suspend request

5

Bus reset

6

Entered high speed operation

FX2LP ACK’d the CONTROL Handshake

reserved

7

8

9

EP0-IN

EP0-OUT

EP1-IN

EP1-OUT

EP2

EP0-IN ready to be loaded with data

EP0-OUT has USB data

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

EP1-IN ready to be loaded with data

EP1-OUT has USB data

IN: buffer available. OUT: buffer has data

IN-Bulk-NAK (any IN endpoint)

reserved

EP4

EP6

EP8

IBN

EP0PING

EP1PING

EP2PING

EP4PING

EP6PING

EP8PING

ERRLIMIT

EP0 OUT was Pinged and it NAK’d

EP1 OUT was Pinged and it NAK’d

EP2 OUT was Pinged and it NAK’d

EP4 OUT was Pinged and it NAK’d

EP6 OUT was Pinged and it NAK’d

EP8 OUT was Pinged and it NAK’d

Bus errors exceeded the programmed limit

reserved

EP2ISOERR

EP4ISOERR

EP6ISOERR

EP8ISOERR

ISO EP2 OUT PID sequence error

ISO EP4 OUT PID sequence error

ISO EP6 OUT PID sequence error

ISO EP8 OUT PID sequence error

If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP register), the FX2LP substitutes its INT2VEC byte. Therefore, if the high

byte (“page”) of a jump table address is preloaded at the location 0x0044, the automatically inserted INT2VEC byte at 0x0045 directs

the jump to the correct address out of the 27 addresses within the page.

3.8.3 FIFO/GPIF Interrupt (INT4)

Just as the USB Interrupt is shared among 27 individual USB interrupt sources, the FIFO/GPIF interrupt is shared among 14 individual

FIFO/GPIF sources. The FIFO/GPIF Interrupt, like the USB Interrupt, can employ autovectoring. Table 4 on page 6 shows the priority

and INT4VEC values for the 14 FIFO/GPIF interrupt sources.

Document #: 38-08032 Rev. *M

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Table 4. Individual FIFO/GPIF Interrupt Sources

Priority

INT4VEC Value

Source

EP2PF

EP4PF

EP6PF

EP8PF

EP2EF

EP4EF

EP6EF

EP8EF

EP2FF

EP4FF

EP6FF

EP8FF

GPIFDONE

GPIFWF

Notes

1

2

80

84

88

8C

90

94

98

9C

A0

A4

A8

AC

B0

B4

Endpoint 2 Programmable Flag

Endpoint 4 Programmable Flag

Endpoint 6 Programmable Flag

Endpoint 8 Programmable Flag

Endpoint 2 Empty Flag

Endpoint 4 Empty Flag

Endpoint 6 Empty Flag

Endpoint 8 Empty Flag

Endpoint 2 Full Flag

3

4

5

6

7

8

9

10

11

12

13

14

Endpoint 4 Full Flag

Endpoint 6 Full Flag

Endpoint 8 Full Flag

GPIF Operation Complete

GPIF Waveform

If Autovectoring is enabled (AV4EN = 1 in the INTSET-UP

register), the FX 2LP substitutes its INT4VEC byte. Therefore, if

the high byte (“page”) of a jump-table address is preloaded at

location 0x0054, the automatically inserted INT4VEC byte at

0x0055 directs the jump to the correct address out of the 14

addresses within the page. When the ISR occurs, the FX2LP

pushes the program counter to its stack then jumps to address

0x0053, where it expects to find a “jump” instruction to the ISR

Interrupt service routine.

5 ms after VCC reaches 3.0V. If the crystal input pin is driven by

a clock signal the internal PLL stabilizes in 200 μs after VCC has

reached 3.0V.^[3]

Figure 2 on page 7 shows a power on reset condition and a reset

applied during operation. A power on reset is defined as the time

reset that is asserted while power is being applied to the circuit.

A powered reset is when the FX2LP powered on and operating

and the RESET# pin is asserted.

Cypress provides an application note which describes and

recommends power on reset implementation. For more infor-

mation about reset implementation for the FX2 family of products

visit http://www.cypress.com.

3.9 Reset and Wakeup

3.9.1 Reset Pin

The input pin, RESET#, resets the FX2LP when asserted. This

pin has hysteresis and is active LOW. When a crystal is used with

the CY7C680xxA the reset period must enable stabilization of

the crystal and the PLL. This reset period must be approximately

Note

3. If the external clock is powered at the same time as the CY7C680xxA and has a stabilization wait period, it must be added to the 200 μs.

Document #: 38-08032 Rev. *M

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Figure 2. Reset Timing Plots

RESET#

V_IL

3.3V

3.0V

3.3V

VCC

0V

T_RESET

Power on Reset

Powered Reset

Table 5. Reset Timing Values

3.10 Program/Data RAM

3.10.1 Size

Condition

T_RESET

Power on Reset with Crystal

5 ms

The FX2LP has 16 KBytes of internal program/data RAM, where

PSEN#/RD# signals are internally ORed to enable the 8051 to

access it as both program and data memory. No USB control

registers appear in this space.

Power on Reset with External

Clock

200 μs + Clock stability time

Powered Reset

200 μs

Two memory maps are shown in the following diagrams:

Figure 3 on page 8 shows the Internal Code Memory, EA = 0

Figure 4 on page 9 shows the External Code Memory, EA = 1.

3.9.2 Wakeup Pins

The 8051 puts itself and the rest of the chip into a power down

mode by setting PCON.0 = 1. This stops the oscillator and PLL.

When WAKEUP is asserted by external logic the oscillator

restarts after the PLL stabilizes, and the 8051 receives a wakeup

interrupt. This applies whether or not FX2LP is connected to the

USB.

3.10.2 Internal Code Memory, EA = 0

This mode implements the internal 16 KByte block of RAM

(starting at 0) as combined code and data memory. When

external RAM or ROM is added, the external read and write

strobes are suppressed for memory spaces that exist inside the

chip. This enables the user to connect a 64 KByte memory

without requiring address decodes to keep clear of internal

memory spaces.

The FX2LP exits the power down (USB suspend) state using one

of the following methods:

■ USB bus activity (if D+/D– lines are left floating, noise on these

lines may indicate activity to the FX2LP and initiate a wakeup)

Only the internal 16 KBytes and scratch pad 0.5 KBytes RAM

spaces have the following access:

■ External logic asserts the WAKEUP pin

■ External logic asserts the PA3/WU2 pin

■ USB download

■ USB upload

The second wakeup pin, WU2, can also be configured as a

general purpose I/O pin. This enables a simple external R-C

network to be used as a periodic wakeup source. WAKEUP is by

default active LOW.

■ Setup data pointer

■ I²C interface boot load.

3.10.3 External Code Memory, EA = 1

The bottom 16 KBytes of program memory is external and

therefore the bottom 16 KBytes of internal RAM is accessible

only as a data memory.

Document #: 38-08032 Rev. *M

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Figure 3. Internal Code Memory, EA = 0

Inside FX2LP

Outside FX2LP

FFFF

7.5 KBytes

USB regs and

4K FIFO buffers

(OK to populate

data memory

here—RD#/WR#

strobes are not

active)

(RD#,WR#)

E200

E1FF

0.5 KBytes RAM

Data (RD#,WR#)*

E000

48 KBytes

External

Code

Memory

(PSEN#)

40 KBytes

External

Data

Memory

(RD#,WR#)

3FFF

(Ok to populate

data memory

here—RD#/WR#

strobes are not

active)

(OK to populate

program

memory here—

PSEN# strobe

is not active)

16 KBytes RAM

Code and Data

(PSEN#,RD#,WR#)*

0000

Data

Code

*SUDPTR, USB upload/download, I²C interface boot access

Document #: 38-08032 Rev. *M

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Figure 4. External Code Memory, EA = 1

Inside FX2LP Outside FX2LP

FFFF

7.5 KBytes

(OK to populate

USB regs and

4K FIFO buffers

(RD#,WR#)

data memory

here—RD#/WR#

strobes are not

active)

E200

E1FF

0.5 KBytes RAM

Data (RD#,WR#)*

E000

40 KBytes

External

Data

Memory

(RD#,WR#)

64 KBytes

External

Code

Memory

(PSEN#)

3FFF

(Ok to populate

data memory

here—RD#/WR#

strobes are not

active)

16 KBytes

RAM

Data

(RD#,WR#)*

0000

Data

Code

*SUDPTR, USB upload/download, I²C interface boot access

3.11 Register Addresses

FFFF

4 KBytes EP2-EP8

buffers

(8 x 512)

F000

EFFF

2 KBytes RESERVED

E800

E7FF

64 Bytes EP1IN

E7C0

E7BF

E780

64 Bytes EP1OUT

E77F

E740

64 Bytes EP0 IN/OUT

E73F

64 Bytes RESERVED

E700

E6FF

8051 Addressable Registers

(512)

E500

E4FF

Reserved (128)

E480

E47F

128 bytes GPIF Waveforms

E400

E3FF

E200

Reserved (512)

E1FF

512 bytes

8051 xdata RAM

E000

Document #: 38-08032 Rev. *M

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3.12.3 Setup Data Buffer

3.12 Endpoint RAM

A separate 8 byte buffer at 0xE6B8-0xE6BF holds the setup data

from a CONTROL transfer.

3.12.1 Size

■ 3× 64 bytes

(Endpoints 0 and 1)

3.12.4 Endpoint Configurations (High Speed Mode)

■ 8 × 512 bytes (Endpoints 2, 4, 6, 8)

Endpoints 0 and 1 are the same for every configuration. Endpoint

0 is the only CONTROL endpoint, and endpoint 1 can be either

BULK or INTERRUPT.

3.12.2 Organization

■ EP0

The endpoint buffers can be configured in any 1 of the 12 config-

urations shown in the vertical columns. When operating in the full

speed BULK mode only the first 64 bytes of each buffer are used.

For example, in high speed, the max packet size is 512 bytes but

in full speed it is 64 bytes. Even though a buffer is configured to

a 512 byte buffer, in full speed only the first 64 bytes are used.

The unused endpoint buffer space is not available for other

operations. An example endpoint configuration is the EP2–1024

double buffered; EP6–512 quad buffered (column 8).

■ Bidirectional endpoint zero, 64 byte buffer

■ EP1IN, EP1OUT

■ 64 byte buffers, bulk or interrupt

■ EP2, 4, 6, 8

■ Eight 512 byte buffers, bulk, interrupt, or isochronous. EP4 and

EP8 can be double buffered; EP2 and 6 can be either double,

triple, or quad buffered. For high speed endpoint configuration

options, see Figure 5.

Figure 5. Endpoint Configuration

64

EP0 IN&OUT

EP1 IN

EP1 OUT

EP2

512

EP2

EP2 EP2

EP2

512

EP2

512

EP2

512

1024

512

1024

EP4

512

EP4 EP4

512

EP6

1024

512

EP6

512

EP6

512

EP6

512

EP6

512

EP6

EP6 EP6

512

1024

1024 1024

512

1024

512

EP8

512

EP8

512

EP8

512

EP8

512

EP8

512

1024

512

1024

512

10

11

12

9

4

5

8

1

2

3

6

7

Document #: 38-08032 Rev. *M

Page 10 of 62

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CY7C68015A, CY7C68016A

3.12.5 Default Full Speed Alternate Settings

Table 6. Default Full Speed Alternate Settings^{[4, 5]}

Alternate Setting

0

64

0

1

2

3

ep0

64

ep1out

ep1in

ep2

64 bulk

64 int

0

64 int

0

64 bulk out (2×)

64 bulk in (2×)

64 int out (2×)

64 bulk out (2×)

64 int in (2×)

64 iso out (2×)

64 bulk out (2×)

64 iso in (2×)

64 bulk in (2×)

ep4

0

ep6

0

ep8

0

64 bulk in (2×)

3.12.6 Default High Speed Alternate Settings

Table 7. Default High Speed Alternate Settings^{[4, 5]}

Alternate Setting

0

1

2

3

ep0

64

0

64

ep1out

ep1in

ep2

512 bulk^[6]

64 int

0

64 int

0

512 bulk out (2×)

512 bulk in (2×)

512 int out (2×)

512 bulk out (2×)

512 int in (2×)

512 bulk in (2×)

512 iso out (2×)

512 bulk out (2×)

512 iso in (2×)

512 bulk in (2×)

ep4

0

ep6

0

ep8

0

in the 8051-I/O domain. The blocks can be configured as single,

double, triple, or quad buffered as previously shown.

3.13 External FIFO Interface

3.13.1 Architecture

The I/O control unit implements either an internal master (M for

master) or external master (S for Slave) interface.

The FX2LP slave FIFO architecture has eight 512 byte blocks in

the endpoint RAM that directly serve as FIFO memories and are

controlled by FIFO control signals (such as IFCLK, SLCS#,

SLRD, SLWR, SLOE, PKTEND, and flags).

In Master (M) mode, the GPIF internally controls FIFOADR[1..0]

to select a FIFO. The RDY pins (two in the 56-pin package, six

in the 100-pin and 128-pin packages) can be used as flag inputs

from an external FIFO or other logic if desired. The GPIF can be

run from either an internally derived clock or externally supplied

clock (IFCLK), at a rate that transfers data up to 96 Megabytes/s

(48-MHz IFCLK with 16-bit interface).

In operation, some of the eight RAM blocks fill or empty from the

SIE, while the others are connected to the I/O transfer logic. The

transfer logic takes two forms, the GPIF for internally generated

control signals and the slave FIFO interface for externally

controlled transfers.

In Slave (S) mode, the FX2LP accepts either an internally

derived clock or externally supplied clock (IFCLK, max frequency

48 MHz) and SLCS#, SLRD, SLWR, SLOE, PKTEND signals

from external logic. When using an external IFCLK, the external

clock must be present before switching to the external clock with

the IFCLKSRC bit. Each endpoint can individually be selected

for byte or word operation by an internal configuration bit and a

Slave FIFO Output Enable signal SLOE enables data of the

selected width. External logic must ensure that the output enable

signal is inactive when writing data to a slave FIFO. The slave

interface can also operate asynchronously, where the SLRD and

SLWR signals act directly as strobes, rather than a clock qualifier

as in synchronous mode. The signals SLRD, SLWR, SLOE and

PKTEND are gated by the signal SLCS#.

3.13.2 Master/Slave Control Signals

The FX2LP endpoint FIFOS are implemented as eight physically

distinct 256x16 RAM blocks. The 8051/SIE can switch any of the

RAM blocks between two domains, the USB (SIE) domain and

the 8051-I/O Unit domain. This switching is done virtually instan-

taneously, giving essentially zero transfer time between “USB

FIFOS” and “Slave FIFOS.” Because they are physically the

same memory no bytes are actually transferred between buffers.

At any given time, some RAM blocks are filling/emptying with

USB data under SIE control, while other RAM blocks are

available to the 8051, the I/O control unit or both. The RAM

blocks operate as single port in the USB domain, and dual port

Notes

4. “0” means “not implemented.”

5. “2×” means “double buffered.”

6. Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer packets larger than 64 bytes to EP1.

Document #: 38-08032 Rev. *M

Page 11 of 62

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CY7C68015A, CY7C68016A

3.15 ECC Generation^[7]

3.13.3 GPIF and FIFO Clock Rates

An 8051 register bit selects one of two frequencies for the

internally supplied interface clock: 30 MHz and 48 MHz. Alterna-

tively, an externally supplied clock of 5 MHz–48 MHz feeding the

IFCLK pin can be used as the interface clock. IFCLK can be

configured to function as an output clock when the GPIF and

FIFOs are internally clocked. An output enable bit in the

IFCONFIG register turns this clock output off, if desired. Another

bit within the IFCONFIG register inverts the IFCLK signal

whether internally or externally sourced.

The EZ-USB can calculate ECCs (Error Correcting Codes) on

data that passes across its GPIF or Slave FIFO interfaces. There

are two ECC configurations: Two ECCs, each calculated over

256 bytes (SmartMedia Standard); and one ECC calculated over

512 bytes.

The ECC can correct any one-bit error or detect any two-bit error.

3.15.1 ECC Implementation

The two ECC configurations are selected by the ECCM bit:

ECCM = 0

3.14 GPIF

The GPIF is a flexible 8-bit or 16-bit parallel interface driven by

a user programmable finite state machine. It enables the

CY7C68013A/15A to perform local bus mastering and can

implement a wide variety of protocols such as ATA interface,

printer parallel port, and Utopia.

Two 3 byte ECCs, each calculated over a 256 byte block of data.

This configuration conforms to the SmartMedia Standard.

Write any value to ECCRESET, then pass data across the GPIF

or Slave FIFO interface. The ECC for the first 256 bytes of data

is calculated and stored in ECC1. The ECC for the next 256 bytes

is stored in ECC2. After the second ECC is calculated, the values

in the ECCx registers do not change until ECCRESET is written

again, even if more data is subsequently passed across the

interface.

The GPIF has six programmable control outputs (CTL), nine

address outputs (GPIFADRx), and six general-purpose ready

inputs (RDY). The data bus width can be 8 or 16 bits. Each GPIF

vector defines the state of the control outputs, and determines

what state a ready input (or multiple inputs) must be before

proceeding. The GPIF vector can be programmed to advance a

FIFO to the next data value, advance an address, etc. A

sequence of the GPIF vectors make up a single waveform that

is executed to perform the desired data move between the

FX2LP and the external device.

ECCM = 1

One 3 byte ECC calculated over a 512 byte block of data.

Write any value to ECCRESET then pass data across the GPIF

or Slave FIFO interface. The ECC for the first 512 bytes of data

is calculated and stored in ECC1; ECC2 is unused. After the

ECC is calculated, the values in ECC1 do not change even if

more data is subsequently passed across the interface, till

ECCRESET is written again.

3.14.1 Six Control OUT Signals

The 100-pin and 128-pin packages bring out all six Control

Output pins (CTL0-CTL5). The 8051 programs the GPIF unit to

define the CTL waveforms. The 56-pin package brings out three

of these signals, CTL0–CTL2. CTLx waveform edges can be

programmed to make transitions as fast as once per clock (20.8

ns using a 48-MHz clock).

3.16 USB Uploads and Downloads

The core has the ability to directly edit the data contents of the

internal 16 KByte RAM and of the internal 512 byte scratch pad

RAM via a vendor specific command. This capability is normally

used when soft downloading user code and is available only to

and from internal RAM, only when the 8051 is held in reset. The

available RAM spaces are 16 KBytes from 0x0000–0x3FFF

(code/data) and 512 bytes from 0xE000–0xE1FF (scratch pad

data RAM).^[8]

3.14.2 Six Ready IN Signals

The 100-pin and 128-pin packages bring out all six Ready inputs

(RDY0–RDY5). The 8051 programs the GPIF unit to test the

RDY pins for GPIF branching. The 56-pin package brings out two

of these signals, RDY0–1.

3.17 Autopointer Access

3.14.3 Nine GPIF Address OUT Signals

FX2LP provides two identical autopointers. They are similar to

the internal 8051 data pointers but with an additional feature:

they can optionally increment after every memory access. This

capability is available to and from both internal and external

RAM. The autopointers are available in external FX2LP registers

under control of a mode bit (AUTOPTRSET-UP.0). Using the

external FX2LP autopointer access (at 0xE67B – 0xE67C)

enables the autopointer to access all internal and external RAM

to the part.

Nine GPIF address lines are available in the 100-pin and 128-pin

packages, GPIFADR[8..0]. The GPIF address lines enable

indexing through up to a 512 byte block of RAM. If more address

lines are needed I/O port pins are used.

3.14.4 Long Transfer Mode

In the master mode, the 8051 appropriately sets GPIF trans-

action count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1, or

GPIFTCB0) for unattended transfers of up to 2³²transactions.

The GPIF automatically throttles data flow to prevent under or

overflow until the full number of requested transactions

complete. The GPIF decrements the value in these registers to

represent the current status of the transaction.

Also, the autopointers can point to any FX2LP register or

endpoint buffer space. When autopointer access to external

memory is enabled, location 0xE67B and 0xE67C in XDATA and

code space cannot be used.

Notes

7. To use the ECC logic, the GPIF or Slave FIFO interface must be configured for byte-wide operation.

8. After the data has been downloaded from the host, a “loader” can execute from internal RAM to transfer downloaded data to external memory.

Document #: 38-08032 Rev. *M

Page 12 of 62

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CY7C68015A, CY7C68016A

3.18.2 I²C Interface Boot Load Access

2

3.18 I C Controller

At power on reset the I²C interface boot loader loads the

VID/PID/DID configuration bytes and up to 16 KBytes of

program/data. The available RAM spaces are 16 KBytes from

0x0000–0x3FFF and 512 bytes from 0xE000–0xE1FF. The 8051

is in reset. I²C interface boot loads only occur after power on

reset.

FX2LP has one I²C port that is driven by two internal controllers,

one that automatically operates at boot time to load VID/PID/DID

and configuration information, and another that the 8051 uses

when running to control external I²C devices. The I²C port

operates in master mode only.

3.18.1 I²C Port Pins

3.18.3 I²C Interface General-Purpose Access

The 8051 can control peripherals connected to the I²C bus using

the I²CTL and I2DAT registers. FX2LP provides I²C master

control only, it is never an I²C slave.

The I²C pins SCL and SDA must have external 2.2 kΩ pull up

resistors even if no EEPROM is connected to the FX2LP.

External EEPROM device address pins must be configured

properly. See Table 8 for configuring the device address pins.

Table 8. Strap Boot EEPROM Address Lines to These Values

3.19 Compatible with Previous Generation

EZ-USB FX2

Bytes

16

Example EEPROM

24LC00^[9]

24LC01

A2

N/A

0

A1

N/A

0

A0

N/A

0

The EZ-USB FX2LP is form, fit and with minor exceptions

functionally compatible with its predecessor, the EZ-USB FX2.

This makes for an easy transition for designers wanting to

upgrade their systems from the FX2 to the FX2LP. The pinout

and package selection are identical and a vast majority of

firmware previously developed for the FX2 functions in the

FX2LP.

128

256

4K

24LC02

0

24LC32

0

1

8K

24LC64

0

1

16K

24LC128

0

1

For designers migrating from the FX2 to the FX2LP a change in

the bill of material and review of the memory allocation (due to

increased internal memory) is required. For more information

about migrating from EZ-USB FX2 to EZ-USB FX2LP, see the

application note titled Migrating from EZ-USB FX2 to EZ-USB

FX2LP available in the Cypress web site.

Table 9. Part Number Conversion Table

EZ-USB FX2

Part Number

EZ-USB FX2LP

Part Number

Package Description

CY7C68013-56PVC

CY7C68013-56PVCT

CY7C68013-56LFC

CY7C68013-100AC

CY7C68013-128AC

CY7C68013A-56PVXC or CY7C68014A-56PVXC 56-pin SSOP

CY7C68013A-56PVXCT or CY7C68014A-56PVXCT 56-pin SSOP – Tape and Reel

CY7C68013A-56LFXC or CY7C68014A-56LFXC 56-pin QFN

CY7C68013A-100AXC or CY7C68014A-100AXC 100-pin TQFP

CY7C68013A-128AXC or CY7C68014A-128AXC 128-pin TQFP

Note

9. This EEPROM does not have address pins.

Document #: 38-08032 Rev. *M

Page 13 of 62

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CY7C68015A, CY7C68016A

3.20 CY7C68013A/14A and CY7C68015A/16A

Differences

4. Pin Assignments

Figure 6 on page 15 identifies all signals for the five package

types. The following pages illustrate the individual pin diagrams,

plus a combination diagram showing which of the full set of

signals are available in the 128-pin, 100-pin, and 56-pin

packages.

CY7C68013A is identical to CY7C68014A in form, fit, and

functionality. CY7C68015A is identical to CY7C68016A in form,

fit, and functionality. CY7C68014A and CY7C68016A have a

lower suspend current than CY7C68013A and CY7C68015A

respectively and are ideal for power sensitive battery applica-

tions.

The signals on the left edge of the 56-pin package in Figure 6

on page 15 are common to all versions in the FX2LP family with

the noted differences between the CY7C68013A/14A and the

CY7C68015A/16A.

CY7C68015A and CY7C68016A are available in 56-pin QFN

package only. Two additional GPIO signals are available on the

CY7C68015A and CY7C68016A to provide more flexibility when

neither IFCLK or CLKOUT are needed in the 56-pin package.

Three modes are available in all package versions: Port, GPIF

master, and Slave FIFO. These modes define the signals on the

right edge of the diagram. The 8051 selects the interface mode

using the IFCONFIG[1:0] register bits. Port mode is the power on

default configuration.

USB developers wanting to convert their FX2 56-pin application

to a bus-powered system directly benefit from these additional

signals. The two GPIOs give developers the signals they need

for the power control circuitry of their bus-powered application

without pushing them to a high pincount version of FX2LP.

The 100-pin package adds functionality to the 56-pin package by

adding these pins:

The CY7C68015A is only available in the 56-pin QFN package

■ PORTC or alternate GPIFADR[7:0] address signals

Table 10. CY7C68013A/14A and CY7C68015A/16A Pin Dif-

ferences

■ PORTE or alternate GPIFADR[8] address signal and seven

additional 8051 signals

CY7C68013A/CY7C68014A CY7C68015A/CY7C68016A

■ Three GPIF Control signals

■ Four GPIF Ready signals

IFCLK

PE0

PE1

CLKOUT

■ Nine 8051 signals (two USARTs, three timer inputs, INT4,and

INT5#)

■ BKPT, RD#, WR#.

The 128-pin package adds the 8051 address and data buses

plus control signals. Note that two of the required signals, RD#

and WR#, are present in the 100-pin version.

In the 100-pin and 128-pin versions, an 8051 control bit can be

set to pulse the RD# and WR# pins when the 8051 reads

from/writes to PORTC. This feature is enabled by setting

PORTCSTB bit in CPUCS register.

Section 10.5 displays the timing diagram of the read and write

strobing function on accessing PORTC.

Document #: 38-08032 Rev. *M

Page 14 of 62

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CY7C68015A, CY7C68016A

Figure 6. Signal

GPIF Master

Port

Slave FIFO

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

FD[15]

FD[14]

FD[13]

FD[12]

FD[11]

FD[10]

FD[9]

FD[8]

FD[7]

FD[6]

FD[5]

FD[4]

FD[3]

FD[2]

FD[1]

FD[0]

FD[15]

FD[14]

FD[13]

FD[12]

FD[11]

FD[10]

FD[9]

FD[8]

FD[7]

FD[6]

FD[5]

FD[4]

FD[3]

FD[2]

FD[1]

FD[0]

XTALIN

XTALOUT

RESET#

WAKEUP#

SCL

SDA

56

SLRD

SLWR

RDY0

RDY1

**PE0 replaces IFCLK

& PE1 replaces CLKOUT

on CY7C68015A/16A

FLAGA

FLAGB

FLAGC

CTL0

CTL1

CTL2

**PE0

**PE1

INT0#/PA0

INT1#/PA1

PA2

WU2/PA3

PA4

INT0#/ PA0

INT1#/ PA1

SLOE

INT0#/PA0

INT1#/PA1

PA2

WU2/PA3

PA4

PA5

PA6

IFCLK

CLKOUT

WU2/PA3

FIFOADR0

FIFOADR1

PKTEND

DPLUS

DMINUS

PA5

PA6

PA7

PA7/FLAGD/SLCS#

PA7

CTL3

CTL4

CTL5

RDY2

RDY3

RDY4

RDY5

100

BKPT

PORTC7/GPIFADR7

PORTC6/GPIFADR6

PORTC5/GPIFADR5

PORTC4/GPIFADR4

PORTC3/GPIFADR3

PORTC2/GPIFADR2

PORTC1/GPIFADR1

PORTC0/GPIFADR0

RxD0

TxD0

RxD1

TxD1

INT4

INT5#

T2

PE7/GPIFADR8

PE6/T2EX

PE5/INT6

PE4/RxD1OUT

PE3/RxD0OUT

PE2/T2OUT

PE1/T1OUT

PE0/T0OUT

T1

T0

RD#

WR#

CS#

OE#

PSEN#

D7

D6

D5

D4

D3

D2

D1

D0

A15

A14

A13

A12

A11

A10

A9

128

A8

A7

A6

A5

A4

A3

EA

A2

A1

A0

Document #: 38-08032 Rev. *M

Page 15 of 62

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CY7C68015A, CY7C68016A

Figure 7. CY7C68013A/CY7C68014A 128-pin TQFP Pin Assignment

1

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

CLKOUT

VCC

GND

PD0/FD8

*WAKEUP

VCC

2

3

4

RDY0/*SLRD

RDY1/*SLWR

RDY2

RDY3

RDY4

RDY5

AVCC

XTALOUT

XTALIN

AGND

NC

RESET#

5

CTL5

6

A3

A2

A1

A0

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

GND

PA7/*FLAGD/SLCS#

PA6/*PKTEND

PA5/FIFOADR1

PA4/FIFOADR0

D7

NC

D6

D5

AVCC

DPLUS

DMINUS

AGND

A11

A12

A13

A14

A15

VCC

GND

INT4

T0

T1

T2

CY7C68013A/CY7C68014A

128-pin TQFP

PA3/*WU2

PA2/*SLOE

PA1/INT1#

PA0/INT0#

VCC

GND

PC7/GPIFADR7

PC6/GPIFADR6

PC5/GPIFADR5

PC4/GPIFADR4

PC3/GPIFADR3

PC2/GPIFADR2

PC1/GPIFADR1

PC0/GPIFADR0

CTL2/*FLAGC

CTL1/*FLAGB

CTL0/*FLAGA

VCC

*IFCLK

RESERVED

BKPT

EA

SCL

SDA

CTL4

CTL3

GND

OE#

* denotes programmable polarity

Document #: 38-08032 Rev. *M

Page 16 of 62

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CY7C68015A, CY7C68016A

Figure 8. CY7C68013A/CY7C68014A 100-pin TQFP Pin Assignment

1

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

VCC

GND

PD0/FD8

*WAKEUP

VCC

RESET#

2

3

RDY0/*SLRD

RDY1/*SLWR

RDY2

RDY3

RDY4

RDY5

AVCC

XTALOUT

XTALIN

AGND

NC

4

5

CTL5

GND

6

7

PA7/*FLAGD/SLCS#

PA6/*PKTEND

PA5/FIFOADR1

PA4/FIFOADR0

PA3/*WU2

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

PA2/*SLOE

PA1/INT1#

PA0/INT0#

NC

CY7C68013A/CY7C68014A

100-pin TQFP

VCC

GND

AVCC

DPLUS

DMINUS

AGND

VCC

GND

INT4

T0

T1

PC7/GPIFADR7

PC6/GPIFADR6

PC5/GPIFADR5

PC4/GPIFADR4

PC3/GPIFADR3

PC2/GPIFADR2

PC1/GPIFADR1

PC0/GPIFADR0

CTL2/*FLAGC

CTL1/*FLAGB

CTL0/*FLAGA

VCC

T2

*IFCLK

RESERVED

BKPT

SCL

CTL4

CTL3

SDA

* denotes programmable polarity

Document #: 38-08032 Rev. *M

Page 17 of 62

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CY7C68015A, CY7C68016A

Figure 9. CY7C68013A/CY7C68014A 56-pin SSOP Pin Assignment

CY7C68013A/CY7C68014A

56-pin SSOP

1

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

PD5/FD13

PD4/FD12

PD3/FD11

PD2/FD10

PD1/FD9

PD0/FD8

*WAKEUP

VCC

2

PD6/FD14

PD7/FD15

GND

CLKOUT

VCC

3

4

5

6

7

GND

8

RDY0/*SLRD

RDY1/*SLWR

AVCC

XTALOUT

XTALIN

AGND

RESET#

9

GND

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

PA7/*FLAGD/SLCS#

PA6/PKTEND

PA5/FIFOADR1

PA4/FIFOADR0

PA3/*WU2

PA2/*SLOE

PA1/INT1#

PA0/INT0#

VCC

AVCC

DPLUS

DMINUS

AGND

VCC

GND

*IFCLK

RESERVED

SCL

SDA

VCC

CTL2/*FLAGC

CTL1/*FLAGB

CTL0/*FLAGA

GND

VCC

GND

PB7/FD7

PB6/FD6

PB5/FD5

PB4/FD4

PB0/FD0

PB1/FD1

PB2/FD2

PB3/FD3

* denotes programmable polarity

Document #: 38-08032 Rev. *M

Page 18 of 62

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CY7C68015A, CY7C68016A

Figure 10. CY7C68013A/14A/15A/16A 56-pin QFN Pin Assignment

RESET#

RDY0/*SLRD

RDY1/*SLWR

AVCC

1

2

42

41

40

39

38

37

36

35

34

33

32

31

30

GND

PA7/*FLAGD/SLCS#

PA6/*PKTEND

PA5/FIFOADR1

PA4/FIFOADR0

PA3/*WU2

3

XTALOUT

XTALIN

4

CY7C68013A/CY7C68014A

5

&

AGND

6

CY7C68015A/CY7C68016A

AVCC

7

PA2/*SLOE

PA1/INT1#

DPLUS

8

56-pin QFN

DMINUS

AGND

9

PA0/INT0#

10

11

12

13

14

VCC

CTL2/*FLAGC

CTL1/*FLAGB

GND

*IFCLK/**PE0

RESERVED

29 CTL0/*FLAGA

* denotes programmable polarity

** denotes CY7C68015A/CY7C68016A pinout

Document #: 38-08032 Rev. *M

Page 19 of 62

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CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Figure 11. CY7C68013A 56-pin VFBGA Pin Assignment - Top View

1

2

3

4

5

6

7

8

1A

1B

1C

2A

2B

2C

3A

3B

3C

4A

4B

4C

5A

5B

5C

6A

6B

6C

7A

7B

7C

8A

8B

8C

A

B

C

D

1D

2D

7D

8D

1E

1F

1G

1H

2E

2F

2G

2H

7E

7F

7G

7H

8E

8F

8G

8H

E

3F

4F

5F

6F

F

G

H

3G

3H

4G

4H

5G

5H

6G

6H

Document #: 38-08032 Rev. *M

Page 20 of 62

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CY7C68015A, CY7C68016A

4.1 CY7C68013A/15A Pin Descriptions

The FX2LP Pin Descriptions follows.^[10]

Table 11. FX2LP Pin Descriptions

128 100

56

56 56 VF-

Name

AVCC

Type Default

Description

TQFP TQFP SSOP QFN BGA

10

17

9

10

14

3

7

2D

1D

Power

N/A Analog VCC. Connect this pin to 3.3V power source.

This signal provides power to the analog section of the

chip.

16

AVCC

Power

N/A Analog VCC. Connect this pin to 3.3V power source.

This signal provides power to the analog section of the

chip.

13

20

12

19

13

17

6

2F

1F

AGND

Ground

N/A AnalogGround. Connecttogroundwithasshortapath

as possible.

10

N/A AnalogGround. Connecttogroundwithasshortapath

as possible.

19

18

17

16

15

9

8

1E

2E

DMINUS

DPLUS

A0

I/O/Z

Z

L

Z

H

USB D– Signal. Connect to the USB D– signal.

USB D+ Signal. Connect to the USB D+ signal.

94

Output

I/O/Z

8051 Address Bus. This bus is driven at all times.

When the 8051 is addressing internal RAM it reflects

the internal address.

95

A1

96

A2

97

A3

117

118

119

120

126

127

128

21

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

D0

22

23

24

25

59

8051 Data Bus. This bidirectional bus is high

impedance when inactive, input for bus reads, and

output for bus writes. The data bus is used for external

8051 program and data memory. The data bus is active

only for external bus accesses, and is driven LOW in

suspend.

60

D1

I/O/Z

61

D2

I/O/Z

62

D3

I/O/Z

63

D4

I/O/Z

86

D5

I/O/Z

87

D6

I/O/Z

88

D7

I/O/Z

39

PSEN#

Output

Program Store Enable. This active-LOW signal

indicates an 8051 code fetch from external memory. It

is active for program memory fetches from

0x4000–0xFFFF when the EA pin is LOW, or from

0x0000–0xFFFF when the EA pin is HIGH.

Note

10. Unused inputs must not be left floating. Tie either HIGH or LOW as appropriate. Outputs should only be pulled up or down to ensure signals at power up and in

standby. Note also that no pins should be driven while the device is powered down.

Document #: 38-08032 Rev. *M

Page 21 of 62

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CY7C68015A, CY7C68016A

Table 11. FX2LP Pin Descriptions (continued)

128 100 56 56 56 VF-

Name

BKPT

Type Default

Description

TQFP TQFP SSOP QFN BGA

34

28

Output

L

Breakpoint. Thispingoesactive(HIGH)whenthe8051

address bus matches the BPADDRH/L registers and

breakpoints are enabled in the BREAKPT register

(BPEN = 1). If the BPPULSE bit in the BREAKPT

register is HIGH, this signal pulses HIGH for eight

12-/24-/48-MHz clocks. If the BPPULSE bit is LOW, the

signal remains HIGH until the 8051 clears the BREAK

bit (by writing 1 to it) in the BREAKPT register.

99

35

77

11

49

12

42

8B

1C

RESET#

EA

Input

N/A Active LOW Reset. Resets the entire chip. See section

3.9 ”Reset and Wakeup” on page 6 for more details.

N/A External Access. This pin determines where the 8051

fetches code between addresses 0x0000 and 0x3FFF.

If EA = 0 the 8051 fetches this code from its internal

RAM. IF EA = 1 the 8051 fetches this code from external

memory.

12

5

XTALIN

Input

N/A Crystal Input. Connect this signal to a 24-MHz

parallel-resonant, fundamental mode crystal and load

capacitor to GND.

It is also correct to drive XTALIN with an external

24-MHz square wave derived from another clock

source. When driving from an external source, the

driving signal should be a 3.3V square wave.

11

1

10

11

5

4

2C

2B

XTALOUT

Output

O/Z

N/A Crystal Output. Connect this signal to a 24-MHz

parallel-resonant, fundamental mode crystal and load

capacitor to GND.

If an external clock is used to drive XTALIN, leave this

pin open.

100

54

CLKOUT on

CY7C68013A

and

12 MHz CLKOUT: 12-, 24- or 48-MHz clock, phase locked to the

24-MHz input clock. The 8051 defaults to 12-MHz

operation. The 8051 may three-state this output by

setting CPUCS.1 = 1.

CY7C68014A

------------------ ----------- ---------- ------------------------------------------------------------------------

PE1 on

I/O/Z

I

PE1 is a bidirectional I/O port pin.

CY7C68015A

and

CY7C68016A

Port A

82

67

68

69

40

41

42

33

34

35

8G

6G

8F

PA0 or

INT0#

I/O/Z

I

Multiplexed pin whose function is selected by

(PA0) PORTACFG.0

PA0 is a bidirectional I/O port pin.

INT0# is the active-LOW 8051 INT0 interrupt input

signal, which is either edge triggered (IT0 = 1) or level

triggered (IT0 = 0).

83

84

PA1 or

INT1#

I/O/Z

I

Multiplexed pin whose function is selected by:

(PA1) PORTACFG.1

PA1 is a bidirectional I/O port pin.

INT1# is the active-LOW 8051 INT1 interrupt input

signal, which is either edge triggered (IT1 = 1) or level

triggered (IT1 = 0).

PA2 or

I

Multiplexed pin whose function is selected by two bits:

SLOE or

(PA2) IFCONFIG[1:0].

PA2 is a bidirectional I/O port pin.

SLOE is an input-only output enable with program-

mable polarity (FIFOPINPOLAR.4) for the slave FIFOs

connected to FD[7..0] or FD[15..0].

Document #: 38-08032 Rev. *M

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CY7C68015A, CY7C68016A

Table 11. FX2LP Pin Descriptions (continued)

128 100 56 56 56 VF-

Name

Type Default

Description

TQFP TQFP SSOP QFN BGA

85

70

43

36

7F

PA3 or

WU2

I/O/Z

I

Multiplexed pin whose function is selected by:

(PA3) WAKEUP.7 and OEA.3

PA3 is a bidirectional I/O port pin.

WU2 is an alternate source for USB Wakeup, enabled

by WU2EN bit (WAKEUP.1) and polarity set by

WU2POL (WAKEUP.4). If the 8051 is in suspend and

WU2EN = 1, a transition on this pin starts up the oscil-

lator and interrupts the 8051 to enable it to exit the

suspend mode. Asserting this pin inhibits the chip from

suspending, if WU2EN = 1.

89

90

91

71

72

73

44

45

46

37

38

39

6F

8C

7C

PA4 or

FIFOADR0

I/O/Z

I

Multiplexed pin whose function is selected by:

(PA4) IFCONFIG[1..0].

PA4 is a bidirectional I/O port pin.

FIFOADR0 is an input-only address select for the slave

FIFOs connected to FD[7..0] or FD[15..0].

PA5 or

FIFOADR1

I

Multiplexed pin whose function is selected by:

(PA5) IFCONFIG[1..0].

PA5 is a bidirectional I/O port pin.

FIFOADR1 is an input-only address select for the slave

FIFOs connected to FD[7..0] or FD[15..0].

PA6 or

PKTEND

I

Multiplexed pin whose function is selected by the

(PA6) IFCONFIG[1:0] bits.

PA6 is a bidirectional I/O port pin.

PKTEND is an input used to commit the FIFO packet

data to the endpoint and whose polarity is program-

mable via FIFOPINPOLAR.5.

92

74

47

40

6C

PA7 or

FLAGD or

I/O/Z

I

Multiplexed pin whose function is selected by the

(PA7) IFCONFIG[1:0] and PORTACFG.7 bits.

SLCS#

PA7 is a bidirectional I/O port pin.

FLAGD is a programmable slave-FIFO output status

flag signal.

SLCS# gates all other slave FIFO enable/strobes

Port B

44

34

35

36

37

44

25

26

27

28

29

18

19

20

21

22

3H

4F

4H

4G

5H

PB0 or

FD[0]

I/O/Z

I

Multiplexed pin whose function is selected by the

(PB0) following bits: IFCONFIG[1..0].

PB0 is a bidirectional I/O port pin.

FD[0] is the bidirectional FIFO/GPIF data bus.

45

46

47

54

PB1 or

FD[1]

I

Multiplexed pin whose function is selected by the

(PB1) following bits: IFCONFIG[1..0].

PB1 is a bidirectional I/O port pin.

FD[1] is the bidirectional FIFO/GPIF data bus.

PB2 or

FD[2]

I

Multiplexed pin whose function is selected by the

(PB2) following bits: IFCONFIG[1..0].

PB2 is a bidirectional I/O port pin.

FD[2] is the bidirectional FIFO/GPIF data bus.

PB3 or

FD[3]

I

Multiplexed pin whose function is selected by the

(PB3) following bits: IFCONFIG[1..0].

PB3 is a bidirectional I/O port pin.

FD[3] is the bidirectional FIFO/GPIF data bus.

PB4 or

FD[4]

I

Multiplexed pin whose function is selected by the

(PB4) following bits: IFCONFIG[1..0].

PB4 is a bidirectional I/O port pin.

FD[4] is the bidirectional FIFO/GPIF data bus.

Document #: 38-08032 Rev. *M

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CY7C68015A, CY7C68016A

Table 11. FX2LP Pin Descriptions (continued)

128 100 56 56 56 VF-

Name

Type Default

Description

TQFP TQFP SSOP QFN BGA

55

56

57

45

46

47

30

31

32

23

24

25

5G

5F

6H

PB5 or

FD[5]

I/O/Z

I

Multiplexed pin whose function is selected by the

(PB5) following bits: IFCONFIG[1..0].

PB5 is a bidirectional I/O port pin.

FD[5] is the bidirectional FIFO/GPIF data bus.

PB6 or

FD[6]

I

Multiplexed pin whose function is selected by the

(PB6) following bits: IFCONFIG[1..0].

PB6 is a bidirectional I/O port pin.

FD[6] is the bidirectional FIFO/GPIF data bus.

PB7 or

FD[7]

I

Multiplexed pin whose function is selected by the

(PB7) following bits: IFCONFIG[1..0].

PB7 is a bidirectional I/O port pin.

FD[7] is the bidirectional FIFO/GPIF data bus.

PORT C

57

72

73

74

75

76

77

78

79

PC0 or

GPIFADR0

I/O/Z

I

Multiplexed pin whose function is selected by

(PC0) PORTCCFG.0

PC0 is a bidirectional I/O port pin.

GPIFADR0 is a GPIF address output pin.

58

59

60

61

62

63

64

PC1 or

GPIFADR1

I

Multiplexed pin whose function is selected by

(PC1) PORTCCFG.1

PC1 is a bidirectional I/O port pin.

GPIFADR1 is a GPIF address output pin.

PC2 or

GPIFADR2

I

Multiplexed pin whose function is selected by

(PC2) PORTCCFG.2

PC2 is a bidirectional I/O port pin.

GPIFADR2 is a GPIF address output pin.

PC3 or

GPIFADR3

I

Multiplexed pin whose function is selected by

(PC3) PORTCCFG.3

PC3 is a bidirectional I/O port pin.

GPIFADR3 is a GPIF address output pin.

PC4 or

GPIFADR4

I

Multiplexed pin whose function is selected by

(PC4) PORTCCFG.4

PC4 is a bidirectional I/O port pin.

GPIFADR4 is a GPIF address output pin.

PC5 or

GPIFADR5

I

Multiplexed pin whose function is selected by

(PC5) PORTCCFG.5

PC5 is a bidirectional I/O port pin.

GPIFADR5 is a GPIF address output pin.

PC6 or

GPIFADR6

I

Multiplexed pin whose function is selected by

(PC6) PORTCCFG.6

PC6 is a bidirectional I/O port pin.

GPIFADR6 is a GPIF address output pin.

PC7 or

I

Multiplexed pin whose function is selected by

GPIFADR7

(PC7) PORTCCFG.7

PC7 is a bidirectional I/O port pin.

GPIFADR7 is a GPIF address output pin.

PORT D

102

80

52

53

45

46

8A

7A

PD0 or

FD[8]

I/O/Z

I

Multiplexed pin whose function is selected by the

(PD0) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.

FD[8] is the bidirectional FIFO/GPIF data bus.

103

81

PD1 or

FD[9]

I

Multiplexed pin whose function is selected by the

(PD1) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.

FD[9] is the bidirectional FIFO/GPIF data bus.

Document #: 38-08032 Rev. *M

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Table 11. FX2LP Pin Descriptions (continued)

128 100 56 56 56 VF-

Name

Type Default

Description

TQFP TQFP SSOP QFN BGA

104

105

121

122

123

124

82

83

95

96

97

98

54

55

56

1

47

48

49

50

51

52

6B

6A

3B

3A

3C

2A

PD2 or

FD[10]

I/O/Z

I

Multiplexed pin whose function is selected by the

(PD2) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.

FD[10] is the bidirectional FIFO/GPIF data bus.

PD3 or

FD[11]

I

Multiplexed pin whose function is selected by the

(PD3) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.

FD[11] is the bidirectional FIFO/GPIF data bus.

PD4 or

FD[12]

I

Multiplexed pin whose function is selected by the

(PD4) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.

FD[12] is the bidirectional FIFO/GPIF data bus.

PD5 or

FD[13]

I

Multiplexed pin whose function is selected by the

(PD5) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.

FD[13] is the bidirectional FIFO/GPIF data bus.

2

PD6 or

FD[14]

I

Multiplexed pin whose function is selected by the

(PD6) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.

FD[14] is the bidirectional FIFO/GPIF data bus.

3

PD7 or

FD[15]

I

Multiplexed pin whose function is selected by the

(PD7) IFCONFIG[1..0] and EPxFIFOCFG.0 (wordwide) bits.

FD[15] is the bidirectional FIFO/GPIF data bus.

Port E

108

86

PE0 or

T0OUT

I/O/Z

I

Multiplexed pin whose function is selected by the

(PE0) PORTECFG.0 bit.

PE0 is a bidirectional I/O port pin.

T0OUT is an active-HIGH signal from 8051

Timer-counter0. T0OUT outputs a high level for one

CLKOUT clock cycle when Timer0 overflows. If Timer0

is operated in Mode 3 (two separate timer/counters),

T0OUT is active when the low byte timer/counter

overflows.

109

87

PE1 or

T1OUT

I/O/Z

I

Multiplexed pin whose function is selected by the

(PE1) PORTECFG.1 bit.

PE1 is a bidirectional I/O port pin.

T1OUT is an active-HIGH signal from 8051

Timer-counter1. T1OUT outputs a high level for one

CLKOUT clock cycle when Timer1 overflows. If Timer1

is operated in Mode 3 (two separate timer/counters),

T1OUT is active when the low byte timer/counter

overflows.

110

111

88

89

PE2 or

T2OUT

I/O/Z

I

Multiplexed pin whose function is selected by the

(PE2) PORTECFG.2 bit.

PE2 is a bidirectional I/O port pin.

T2OUT is the active-HIGH output signal from 8051

Timer2. T2OUT is active (HIGH) for one clock cycle

when Timer/Counter 2 overflows.

PE3 or

RXD0OUT

I

Multiplexed pin whose function is selected by the

(PE3) PORTECFG.3 bit.

PE3 is a bidirectional I/O port pin.

RXD0OUT is an active-HIGH signal from 8051 UART0.

If RXD0OUT is selected and UART0 is in Mode 0, this

pin provides the output data for UART0 only when it is

in sync mode. Otherwise it is a 1.

Document #: 38-08032 Rev. *M

Page 25 of 62

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CY7C68015A, CY7C68016A

Table 11. FX2LP Pin Descriptions (continued)

128 100 56 56 56 VF-

Name

Type Default

Description

TQFP TQFP SSOP QFN BGA

112

90

PE4 or

RXD1OUT

I/O/Z

I

Multiplexed pin whose function is selected by the

(PE4) PORTECFG.4 bit.

PE4 is a bidirectional I/O port pin.

RXD1OUT is an active-HIGH output from 8051 UART1.

When RXD1OUT is selected and UART1 is in Mode 0,

this pin provides the output data for UART1 only when

it is in sync mode. In Modes 1, 2, and 3, this pin is HIGH.

113

114

91

92

PE5 or

INT6

I/O/Z

I

Multiplexed pin whose function is selected by the

(PE5) PORTECFG.5 bit.

PE5 is a bidirectional I/O port pin.

INT6is the 8051 INT6 interruptrequestinput signal. The

INT6 pin is edge-sensitive, active HIGH.

PE6 or

T2EX

I

Multiplexed pin whose function is selected by the

(PE6) PORTECFG.6 bit.

PE6 is a bidirectional I/O port pin.

T2EX is an active-HIGH input signal to the 8051 Timer2.

T2EX reloads timer 2 on its falling edge. T2EX is active

only if the EXEN2 bit is set in T2CON.

115

4

93

3

PE7 or

GPIFADR8

I/O/Z

Input

I

Multiplexed pin whose function is selected by the

(PE7) PORTECFG.7 bit.

PE7 is a bidirectional I/O port pin.

GPIFADR8 is a GPIF address output pin.

8

9

1

2

1A

1B

RDY0 or

SLRD

N/A Multiplexed pin whose function is selected by the

following bits:

IFCONFIG[1..0].

RDY0 is a GPIF input signal.

SLRD is the input-only read strobe with programmable

polarity (FIFOPINPOLAR.3) for the slave FIFOs

connected to FD[7..0] or FD[15..0].

5

4

RDY1 or

SLWR

Input

N/A Multiplexed pin whose function is selected by the

following bits:

IFCONFIG[1..0].

RDY1 is a GPIF input signal.

SLWR is the input-only write strobe with programmable

polarity (FIFOPINPOLAR.2) for the slave FIFOs

connected to FD[7..0] or FD[15..0].

6

7

5

6

RDY2

RDY3

RDY4

RDY5

Input

O/Z

N/A RDY2 is a GPIF input signal.

N/A RDY3 is a GPIF input signal.

N/A RDY4 is a GPIF input signal.

N/A RDY5 is a GPIF input signal.

8

7

9

8

69

54

36

29

7H

CTL0 or

FLAGA

H

Multiplexed pin whose function is selected by the

following bits:

IFCONFIG[1..0].

CTL0 is a GPIF control output.

FLAGA is a programmable slave-FIFO output status

flag signal.

Defaults to programmable for the FIFO selected by the

FIFOADR[1:0] pins.

Document #: 38-08032 Rev. *M

Page 26 of 62

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CY7C68015A, CY7C68016A

Table 11. FX2LP Pin Descriptions (continued)

128 100 56 56 56 VF-

Name

Type Default

Description

TQFP TQFP SSOP QFN BGA

70

55

37

30

7G

CTL1 or

FLAGB

O/Z

H

Multiplexed pin whose function is selected by the

following bits:

IFCONFIG[1..0].

CTL1 is a GPIF control output.

FLAGB is a programmable slave-FIFO output status

flag signal.

Defaults to FULL for the FIFO selected by the

FIFOADR[1:0] pins.

71

56

38

31

8H

CTL2 or

FLAGC

O/Z

H

Multiplexed pin whose function is selected by the

following bits:

IFCONFIG[1..0].

CTL2 is a GPIF control output.

FLAGC is a programmable slave-FIFO output status

flag signal.

Defaults to EMPTY for the FIFO selected by the

FIFOADR[1:0] pins.

66

67

98

32

51

52

76

26

CTL3

CTL4

CTL5

O/Z

H

Z

CTL3 is a GPIF control output.

CTL4 is a GPIF control output.

CTL5 is a GPIF control output.

Output

I/O/Z

20

13

2G

IFCLK on

CY7C68013A

and

Interface Clock, used for synchronously clocking data

into or out of the slave FIFOs. IFCLK also serves as a

timing reference for all slave FIFO control signals and

GPIF. When internal clocking is used (IFCONFIG.7 = 1)

the IFCLK pin can be configured to output 30/48 MHz

by bits IFCONFIG.5 and IFCONFIG.6. IFCLK may be

inverted, whether internally or externally sourced, by

setting the bit IFCONFIG.4 =1.

CY7C68014A

------------------ ----------- ---------- -----------------------------------------------------------------------

PE0 on

I/O/Z

I

PE0 is a bidirectional I/O port pin.

CY7C68015A

and

CY7C68016A

28

106

31

22

84

25

INT4

INT5#

T2

Input

N/A INT4is the 8051 INT4 interruptrequestinput signal. The

INT4 pin is edge-sensitive, active HIGH.

N/A INT5# is the 8051 INT5 interrupt request input signal.

The INT5 pin is edge-sensitive, active LOW.

N/A T2 is the active-HIGH T2 input signal to 8051 Timer2,

which provides the input to Timer2 when C/T2 = 1.

When C/T2 = 0, Timer2 does not use this pin.

30

29

24

23

T1

T0

Input

N/A T1 is the active-HIGH T1 signal for 8051 Timer1, which

provides the input to Timer1 when C/T1 is 1. When C/T1

is 0, Timer1 does not use this bit.

N/A T0 is the active-HIGH T0 signal for 8051 Timer0, which

provides the input to Timer0 when C/T0 is 1. When C/T0

is 0, Timer0 does not use this bit.

53

52

43

42

RXD1

TXD1

Input

N/A RXD1is an active-HIGH input signal for 8051 UART1,

which provides data to the UART in all modes.

Output

H

TXD1is an active-HIGH output pin from 8051 UART1,

which provides the output clock in sync mode, and the

output data in async mode.

51

41

RXD0

Input

N/A RXD0 is the active-HIGH RXD0 input to 8051 UART0,

which provides data to the UART in all modes.

Document #: 38-08032 Rev. *M

Page 27 of 62

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CY7C68015A, CY7C68016A

Table 11. FX2LP Pin Descriptions (continued)

128 100 56 56 56 VF-

Name

TXD0

Type Default

Description

TQFP TQFP SSOP QFN BGA

50

40

Output

H

TXD0 is the active-HIGH TXD0 output from 8051

UART0, which provides the output clock in sync mode,

and the output data in async mode.

42

41

CS#

Output

H

CS# is the active-LOW chip select for external memory.

32

31

WR#

WR# is the active-LOW write strobe output for external

memory.

40

38

RD#

OE#

Output

H

RD# is the active-LOW read strobe output for external

memory.

OE# is the active-LOW output enable for external

memory.

33

27

79

21

51

14

44

2H

7B

Reserved

WAKEUP

Input

N/A Reserved. Connect to ground.

101

N/A USB Wakeup. If the 8051 is in suspend, asserting this

pin starts up the oscillator and interrupts the 8051 to

enable it to exit the suspend mode. Holding WAKEUP

asserted inhibits the EZ-USB^®chip from suspending.

This pin has programmable polarity (WAKEUP.4).

36

37

29

30

22

23

15

16

3F

SCL

SDA

OD

Z

Clock for the I²C interface. Connect to VCC with a 2.2K

resistor, even if no I²C peripheral is attached.

3G

Z

Data for I²C-compatible interface. Connect to VCC

with a 2.2K resistor, even if no I²C-compatible

peripheral is attached.

2

1

6

55

11

17

5A

1G

7E

VCC

Power

N/A VCC. Connect to 3.3V power source.

26

20

33

38

49

53

66

78

85

18

24

43

48

64

34

27

8E

68

81

39

50

32

43

5C

5B

100

107

3

2

7

56

12

4B

1H

GND

Ground

N/A Ground.

27

21

39

48

50

65

75

94

99

19

49

58

33

35

26

28

7D

8D

65

80

93

48

4

41

53

4C

4A

116

125

14

15

16

13

14

15

NC

N/A

N/A No Connect. This pin must be left open.

Document #: 38-08032 Rev. *M

Page 28 of 62

[+] Feedback

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

5. Register Summary

FX2LP register bit definitions are described in the FX2LP TRM in greater detail.

Table 12. FX2LP Register Summary

Hex Size Name

Description

b7

b6

b5

b4

b3

b2

b1

b0

Default

Access

GPIF Waveform Memories

E400 128 WAVEDATA

GPIF Waveform

Descriptor 0, 1, 2, 3 data

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx RW

E480 128 reserved

GENERAL CONFIGURATION

E50D

GPCR2

General Purpose Configu-reserved

ration Register 2

reserved

0

reserved

FULL_SPEE reserved

D_ONLY

reserved

00000000 R

E600

E601

1

CPUCS

CPU Control & Status

0

PORTCSTB CLKSPD1 CLKSPD0 CLKINV

CLKOE

IFCFG1

8051RES

IFCFG0

00000010 rrbbbbbr

10000000 RW

IFCONFIG

Interface Configuration

(Ports, GPIF, slave FIFOs)

IFCLKSRC 3048MHZ

IFCLKOE

FLAGB1

FLAGD1

0

IFCLKPOL ASYNC

GSTATE

FLAGA2

FLAGC2

EP2

[11]

E602

E603

E604

1

PINFLAGSAB

Slave FIFO FLAGA and FLAGB3

FLAGB Pin Configuration

FLAGB2

FLAGD2

0

FLAGB0

FLAGD0

0

FLAGA3

FLAGC3

EP3

FLAGA1

FLAGC1

EP1

FLAGA0

FLAGC0

EP0

00000000 RW

PINFLAGSCD

Slave FIFO FLAGC and FLAGD3

FLAGD Pin Configuration

[11]

FIFORESET

Restore FIFOS to default NAKALL

state

xxxxxxxx W

E605

E606

E607

E608

1

BREAKPT

BPADDRH

BPADDRL

UART230

Breakpoint Control

0

BREAK

A11

A3

BPPULSE BPEN

0

00000000 rrrrbbbr

xxxxxxxx RW

Breakpoint Address H

Breakpoint Address L

A15

A7

0

A14

A6

0

A13

A5

0

A12

A4

0

A10

A2

0

A9

A1

A8

A0

230 Kbaud internally

generated ref. clock

0

230UART1 230UART0 00000000 rrrrrrbb

[11]

E609

1

FIFOPINPOLAR

Slave FIFO Interface pins 0

polarity

0

PKTEND

SLOE

rv4

SLRD

rv3

SLWR

rv2

EF

FF

00000000 rrbbbbbb

E60A 1

E60B 1

REVID

Chip Revision

rv7

rv6

0

rv5

0

rv1

rv0

RevA

00000001

R

[11]

REVCTL

Chip Revision Control

0

dyn_out

enh_pkt

00000000 rrrrrrbb

UDMA

E60C 1

3

GPIFHOLDAMOUNT MSTB Hold Time

(for UDMA)

0

HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb

reserved

ENDPOINT CONFIGURATION

E610

E611

1

EP1OUTCFG

Endpoint 1-OUT

Configuration

VALID

0

TYPE1

TYPE0

0

10100000 brbbrrrr

EP1INCFG

Endpoint 1-IN

Configuration

E612

E613

E614

E615

1

2

1

EP2CFG

EP4CFG

EP6CFG

EP8CFG

reserved

Endpoint 2 Configuration VALID

Endpoint 4 Configuration VALID

Endpoint 6 Configuration VALID

Endpoint 8 Configuration VALID

DIR

TYPE1

TYPE0

SIZE

0

BUF1

0

BUF0

0

10100010 bbbbbrbb

10100000 bbbbrrrr

11100010 bbbbbrbb

11100000 bbbbrrrr

SIZE

0

BUF1

0

BUF0

0

[11]

E618

E619

EP2FIFOCFG

Endpoint 2 / slave FIFO

configuration

0

INFM1

OEP1

AUTOOUT AUTOIN

ZEROLENIN 0

WORDWIDE 00000101 rbbbbbrb

1

EP4FIFOCFG

EP6FIFOCFG

EP8FIFOCFG

reserved

Endpoint 4 / slave FIFO

configuration

E61A 1

E61B 1

E61C 4

Endpoint 6 / slave FIFO

configuration

Endpoint 8 / slave FIFO

configuration

[11

E620

E621

E622

E623

E624

E625

E626

E627

1

EP2AUTOINLENH Endpoint 2 AUTOIN

0

PL10

PL2

0

PL9

PL8

PL0

PL8

PL0

PL8

PL0

PL8

PL0

00000010 rrrrrbbb

00000000 RW

Packet Length H

[11]

EP2AUTOINLENL

Endpoint 2 AUTOIN

Packet Length L

PL7

0

PL6

0

PL5

0

PL4

0

PL3

0

PL1

PL9

PL1

PL9

PL1

PL9

PL1

[11]

EP4AUTOINLENH Endpoint 4 AUTOIN

00000010 rrrrrrbb

00000000 RW

Packet Length H

[11]

EP4AUTOINLENL

Endpoint 4 AUTOIN

Packet Length L

PL7

0

PL6

0

PL5

0

PL4

0

PL3

0

PL2

PL10

PL2

0

[11]

EP6AUTOINLENH Endpoint 6 AUTOIN

00000010 rrrrrbbb

00000000 RW

Packet Length H

[11]

EP6AUTOINLENL

Endpoint 6 AUTOIN

Packet Length L

PL7

0

PL6

0

PL5

0

PL4

0

PL3

0

[11]

EP8AUTOINLENH Endpoint 8 AUTOIN

00000010 rrrrrrbb

00000000 RW

Packet Length H

[11]

EP8AUTOINLENL

Endpoint 8 AUTOIN

Packet Length L

PL7

PL6

PL5

PL4

PL3

PL2

E628

E629

1

ECCCFG

ECCRESET

ECC1B0

ECC Configuration

ECC Reset

0

ECCM

x

00000000 rrrrrrrb

00000000 W

x

E62A 1

ECC1 Byte 0 Address

LINE15

LINE14

LINE13

LINE12

LINE11

LINE10

LINE9

LINE8

00000000 R

Note

11. Read and writes to these registers may require synchronization delay, see Technical Reference Manual for “Synchronization Delay.”

Document #: 38-08032 Rev. *M

Page 29 of 62

[+] Feedback

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Table 12. FX2LP Register Summary (continued)

Hex Size Name

Description

b7

b6

b5

b4

b3

b2

b1

b0

Default

Access

E62B 1

E62C 1

E62D 1

E62E 1

E62F 1

ECC1B1

ECC1 Byte 1 Address

ECC1 Byte 2 Address

ECC2 Byte 0 Address

ECC2 Byte 1 Address

ECC2 Byte 2 Address

LINE7

COL5

LINE15

LINE7

COL5

LINE6

COL4

LINE14

LINE6

COL4

PKTSTAT

LINE5

COL3

LINE13

LINE5

COL3

LINE4

COL2

LINE12

LINE4

COL2

LINE3

COL1

LINE11

LINE3

COL1

LINE2

COL0

LINE10

LINE2

COL0

0

LINE1

LINE17

LINE9

LINE1

0

LINE0

LINE16

LINE8

LINE0

0

00000000 R

ECC1B2

00000000 R

ECC2B0

00000000 R

ECC2B1

00000000 R

ECC2B2

00000000 R

[11]

E630

H.S.

1

EP2FIFOPFH

Endpoint 2 / slave FIFO DECIS

Programmable Flag H

IN:PKTS[2] IN:PKTS[1] IN:PKTS[0]

OUT:PFC12 OUT:PFC11 OUT:PFC10

PFC9

PFC8

10001000 bbbbbrbb

E630

F.S.

EP2FIFOPFH

Endpoint 2 / slave FIFO DECIS

Programmable Flag H

PKTSTAT

PFC6

OUT:PFC12 OUT:PFC11 OUT:PFC10 0

PFC9

PFC1

0

IN:PKTS[2] 10001000 bbbbbrbb

OUT:PFC8

[11]

E631

H.S.

EP2FIFOPFL

Endpoint 2 / slave FIFO PFC7

Programmable Flag L

PFC5

PFC4

PFC3

PFC2

PFC0

PFC8

PFC0

PFC8

00000000 RW

E631

F.S

EP2FIFOPFL

Endpoint 2 / slave FIFO IN:PKTS[1] IN:PKTS[0] PFC5

Programmable Flag L OUT:PFC7 OUT:PFC6

00000000 RW

E632

H.S.

EP4FIFOPFH

Endpoint 4 / slave FIFO DECIS

Programmable Flag H

PKTSTAT

PFC6

0

IN: PKTS[1] IN: PKTS[0] 0

OUT:PFC10 OUT:PFC9

10001000 bbrbbrrb

00000000 RW

[11]

E632

F.S

EP4FIFOPFH

Endpoint 4 / slave FIFO DECIS

Programmable Flag H

0

OUT:PFC10 OUT:PFC9

0

[11]

E633

H.S.

EP4FIFOPFL

Endpoint 4 / slave FIFO PFC7

Programmable Flag L

PFC5

PFC4

PFC3

PFC2

0

PFC1

PFC9

PFC1

0

E633

F.S

EP4FIFOPFL

Endpoint 4 / slave FIFO IN: PKTS[1] IN: PKTS[0] PFC5

Programmable Flag L OUT:PFC7 OUT:PFC6

00000000 RW

E634

H.S.

EP6FIFOPFH

Endpoint 6 / slave FIFO DECIS

Programmable Flag H

PKTSTAT

PFC6

IN:PKTS[2] IN:PKTS[1] IN:PKTS[0]

OUT:PFC12 OUT:PFC11 OUT:PFC10

00001000 bbbbbrbb

[11]

E634

F.S

EP6FIFOPFH

Endpoint 6 / slave FIFO DECIS

Programmable Flag H

OUT:PFC12 OUT:PFC11 OUT:PFC10 0

IN:PKTS[2] 00001000 bbbbbrbb

OUT:PFC8

[11]

E635

H.S.

EP6FIFOPFL

Endpoint 6 / slave FIFO PFC7

Programmable Flag L

PFC5

PFC4

PFC3

PFC2

PFC0

PFC8

PFC0

00000000 RW

E635

F.S

EP6FIFOPFL

Endpoint 6 / slave FIFO IN:PKTS[1] IN:PKTS[0] PFC5

Programmable Flag L OUT:PFC7 OUT:PFC6

00000000 RW

E636

H.S.

EP8FIFOPFH

Endpoint 8 / slave FIFO DECIS

Programmable Flag H

PKTSTAT

PFC6

0

IN: PKTS[1] IN: PKTS[0] 0

OUT:PFC10 OUT:PFC9

00001000 bbrbbrrb

00000000 RW

[11]

E636

F.S

EP8FIFOPFH

Endpoint 8 / slave FIFO DECIS

Programmable Flag H

0

OUT:PFC10 OUT:PFC9

0

[11]

E637

H.S.

EP8FIFOPFL

reserved

Endpoint 8 / slave FIFO PFC7

Programmable Flag L

PFC5

PFC4

PFC3

PFC2

PFC1

[11]

E637

F.S

Endpoint 8 / slave FIFO IN: PKTS[1] IN: PKTS[0] PFC5

Programmable Flag L OUT:PFC7 OUT:PFC6

00000000 RW

8

1

E640

E641

E642

E643

EP2ISOINPKTS

EP4ISOINPKTS

EP6ISOINPKTS

EP8ISOINPKTS

reserved

EP2 (if ISO) IN Packets AADJ

per frame (1-3)

0

INPPF1

INPPF0

00000001 brrrrrbb

00000001 brrrrrrr

00000001 brrrrrbb

00000001 brrrrrrr

1

EP4 (if ISO) IN Packets AADJ

per frame (1-3)

EP6 (if ISO) IN Packets AADJ

per frame (1-3)

EP8 (if ISO) IN Packets AADJ

per frame (1-3)

E644

E648

E649

4

1

7

[11]

INPKTEND

Force IN Packet End

Skip

0

EP3

EP2

EP1

EP0

xxxxxxxx

W

[11]

OUTPKTEND

Force OUT Packet End Skip

INTERRUPTS

[11]

E650

E651

E652

E653

E654

E655

E656

E657

E658

E659

1

EP2FIFOIE

Endpoint 2 slave FIFO

Flag Interrupt Enable

0

EDGEPF

0

PF

EF

EP1

0

FF

00000000 RW

[11,12]

EP2FIFOIRQ

Endpoint 2 slave FIFO

Flag Interrupt Request

0

PF

FF

00000000 rrrrrbbb

00000000 RW

[11]

EP4FIFOIE

Endpoint 4 slave FIFO

Flag Interrupt Enable

0

EDGEPF

0

PF

FF

[11,12]

EP4FIFOIRQ

Endpoint 4 slave FIFO

Flag Interrupt Request

0

PF

FF

00000000 rrrrrbbb

00000000 RW

[11]

EP6FIFOIE

Endpoint 6 slave FIFO

Flag Interrupt Enable

0

EDGEPF

0

PF

FF

EP6FIFOIRQ

Endpoint 6 slave FIFO

Flag Interrupt Request

0

PF

FF

00000000 rrrrrbbb

00000000 RW

[11]

EP8FIFOIE

EP8FIFOIRQ

IBNIE

Endpoint 8 slave FIFO

Flag Interrupt Enable

0

EDGEPF

0

PF

FF

Endpoint 8 slave FIFO

Flag Interrupt Request

0

PF

FF

00000000 rrrrrbbb

00000000 RW

IN-BULK-NAK Interrupt

Enable

0

EP8

EP4

EP6

EP2

EP4

EP2

EP0

SUTOK

EP0

IBN

SUDAV

[12]

IBNIRQ

IN-BULK-NAK interrupt

Request

0

EP4

00xxxxxx rrbbbbbb

00000000 RW

E65A 1

E65B 1

E65C 1

NAKIE

Endpoint Ping-NAK / IBN EP8

Interrupt Enable

EP6

EP0ACK

EP1

[12]

NAKIRQ

Endpoint Ping-NAK / IBN EP8

Interrupt Request

EP1

0

xxxxxx0x bbbbbbrb

00000000 RW

USBIE

USB Int Enables

0

HSGRANT URES

SUSP

SOF

Note

12. The register can only be reset, it cannot be set.

Document #: 38-08032 Rev. *M

Page 30 of 62

[+] Feedback

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Table 12. FX2LP Register Summary (continued)

Hex Size Name

Description

b7

0

b6

b5

b4

b3

b2

b1

b0

Default

Access

[12]

E65D 1

E65E 1

USBIRQ

USB Interrupt Requests

EP0ACK

EP6

HSGRANT URES

SUSP

EP1OUT

SUTOK

EP1IN

SOF

SUDAV

EP0IN

0xxxxxxx rbbbbbbb

00000000 RW

EPIE

Endpoint Interrupt

Enables

EP8

EP4

EP2

EP0OUT

[12]

E65F 1

EPIRQ

Endpoint Interrupt

Requests

EP8

EP6

EP1OUT

EP1IN

EP0OUT

EP0IN

0

RW

[11]

E660

E661

E662

1

GPIFIE

GPIF Interrupt Enable

GPIF Interrupt Request

0

GPIFWF

0

GPIFDONE 00000000 RW

GPIFDONE 000000xx RW

GPIFIRQ

0

USBERRIE

USB Error Interrupt

Enables

ISOEP8

ISOEP6

ISOEP4

ISOEP2

ERRLIMIT

LIMIT0

00000000 RW

[12]

E663

E664

1

USBERRIRQ

USB Error Interrupt

Requests

ISOEP8

EC3

ISOEP6

EC2

ISOEP4

EC1

ISOEP2

EC0

0

0000000x bbbbrrrb

xxxx0100 rrrrbbbb

ERRCNTLIM

USB Error counter and

limit

LIMIT3

LIMIT2

LIMIT1

E665

E666

1

CLRERRCNT

INT2IVEC

Clear Error Counter EC3:0 x

x

xxxxxxxx W

Interrupt 2 (USB)

Autovector

0

1

0

I2V4

I2V3

I2V2

I2V1

I2V0

0

00000000 R

10000000 R

00000000 RW

E667

1

INT4IVEC

Interrupt 4 (slave FIFO &

GPIF) Autovector

0

I4V3

0

I4V2

0

I4V1

I4V0

0

E668

E669

1

7

INTSET-UP

reserved

Interrupt 2&4 setup

AV2EN

INT4SRC

AV4EN

INPUT / OUTPUT

PORTACFG

E670

E671

E672

1

I/O PORTA Alternate

Configuration

FLAGD

GPIFA7

GPIFA8

SLCS

GPIFA6

T2EX

0

INT1

INT0

00000000 RW

PORTCCFG

PORTECFG

I/O PORTC Alternate

Configuration

GPIFA5

INT6

GPIFA4

GPIFA3

GPIFA2

GPIFA1

T1OUT

GPIFA0

T0OUT

I/O PORTE Alternate

Configuration

RXD1OUT RXD0OUT T2OUT

E673

E677

E678

4

1

reserved

2

I CS

I²C Bus

START

STOP

d6

LASTRD

ID1

d4

0

ID0

d3

0

BERR

d2

ACK

d1

DONE

d0

000xx000 bbbrrrrr

xxxxxxxx RW

00000000 RW

xxxxxxxx RW

Control & Status

E679

1

I2DAT

I²C Bus

Data

d7

0

d5

0

2

E67A 1

E67B 1

E67C 1

I CTL

I²C Bus

Control

0

STOPIE

D1

400KHZ

D0

XAUTODAT1

XAUTODAT2

UDMA CRC

Autoptr1 MOVX access, D7

when APTREN=1

D6

D5

D4

D3

D2

Autoptr2 MOVX access, D7

when APTREN=1

D1

D0

[11]

E67D 1

E67E 1

E67F 1

UDMACRCH

UDMA CRC MSB

UDMA CRC LSB

UDMA CRC Qualifier

CRC15

CRC14

CRC6

0

CRC13

CRC5

0

CRC12

CRC4

0

CRC11

CRC3

CRC10

CRC2

CRC9

CRC1

CRC8

CRC0

01001010 RW

10111010 RW

[11]

UDMACRCL

CRC7

UDMACRC-

QUALIFIER

QENABLE

QSTATE

QSIGNAL2 QSIGNAL1 QSIGNAL0 00000000 brrrbbbb

USB CONTROL

USBCS

E680

E681

E682

E683

E684

E685

E686

E687

E688

1

2

USB Control & Status

Put chip into suspend

HSM

x

0

DISCON

NOSYNSOF RENUM

SIGRSUME x0000000 rrrrbbbb

SUSPEND

WAKEUPCS

TOGCTL

x

xxxxxxxx W

Wakeup Control & Status WU2

WU

S

WU2POL

WUPOL

I/O

0

DPEN

EP2

FC10

FC2

MF2

FA2

WU2EN

EP1

FC9

FC1

MF1

FA1

WUEN

EP0

FC8

FC0

MF0

FA0

xx000101 bbbbrbbb

x0000000 rrrbbbbb

00000xxx R

Toggle Control

Q

R

EP3

0

USBFRAMEH

USBFRAMEL

MICROFRAME

FNADDR

USB Frame count H

USB Frame count L

Microframe count, 0-7

USB Function address

0

FC7

0

FC6

0

FC5

0

FC4

0

FC3

0

xxxxxxxx

00000xxx R

0xxxxxxx R

R

0

FA6

FA5

FA4

FA3

reserved

ENDPOINTS

[11]

E68A 1

E68B 1

E68C 1

E68D 1

EP0BCH

Endpoint 0 Byte Count H (BC15)

Endpoint 0 Byte Count L (BC7)

(BC14)

BC6

(BC13)

BC5

(BC12)

BC4

(BC11)

BC3

(BC10)

BC2

(BC9)

BC1

(BC8)

BC0

xxxxxxxx RW

[11]

EP0BCL

reserved

EP1OUTBC

Endpoint 1 OUT Byte

Count

0

BC6

BC5

BC4

BC3

BC2

BC1

BC0

0xxxxxxx RW

E68E 1

E68F 1

reserved

EP1INBC

Endpoint 1 IN Byte Count 0

Endpoint 2 Byte Count H

Endpoint 2 Byte Count L BC7/SKIP

BC6

0

BC5

0

BC4

0

BC3

0

BC2

BC10

BC2

BC1

BC9

BC1

BC0

BC8

BC0

0xxxxxxx RW

00000xxx RW

xxxxxxxx RW

[11]

E690

E691

E692

E694

E695

E696

E698

E699

1

2

1

2

1

EP2BCH

0

[11]

EP2BCL

BC6

BC5

BC4

BC3

reserved

[11]

EP4BCH

Endpoint 4 Byte Count H

0

BC9

BC1

BC8

BC0

000000xx RW

xxxxxxxx RW

[11]

EP4BCL

Endpoint 4 Byte Count L BC7/SKIP

BC6

BC5

BC4

BC3

BC2

reserved

[11]

EP6BCH

Endpoint 6 Byte Count H

0

BC10

BC2

BC9

BC1

BC8

BC0

00000xxx RW

xxxxxxxx RW

[11]

EP6BCL

Endpoint 6 Byte Count L BC7/SKIP

BC6

BC5

BC4

BC3

E69A 2

E69C 1

reserved

[11]

EP8BCH

Endpoint 8 Byte Count H

0

BC9

BC8

000000xx RW

Document #: 38-08032 Rev. *M

Page 31 of 62

[+] Feedback

CY7C68013A, CY7C68014A

CY7C68015A, CY7C68016A

Table 12. FX2LP Register Summary (continued)

Hex Size Name

Description

b7

b6

b5

b4

b3

b2

b1

b0

Default

Access

[11]

E69D 1

E69E 2

E6A0 1

EP8BCL

Endpoint 8 Byte Count L BC7/SKIP

BC6

BC5

BC4

BC3

BC2

BC1

BC0

xxxxxxxx RW

reserved

EP0CS

Endpoint 0 Control and HSNAK

Status

0

BUSY

0

STALL

FF

10000000 bbbbbbrb

00000000 bbbbbbrb

00101000 rrrrrrrb

00000100 rrrrrrrb

00000010 R

E6A1 1

E6A2 1

E6A3 1

E6A4 1

E6A5 1

E6A6 1

E6A7 1

E6A8 1

E6A9 1

E6AA 1

E6AB 1

E6AC 1

E6AD 1

E6AE 1

E6AF 1

E6B0 1

E6B1 1

E6B2 1

E6B3 1

E6B4 1

E6B5 1

EP1OUTCS

EP1INCS

Endpoint 1 OUT Control

and Status

0

Endpoint 1 IN Control and 0

Status

0

EP2CS

Endpoint 2 Control and

Status

0

NPAK2

NPAK1

NPAK0

0

FULL

0

EMPTY

PF

EP4CS

Endpoint 4 Control and

Status

0

NPAK1

0

EP6CS

Endpoint 6 Control and

Status

0

NPAK2

NPAK1

0

EP8CS

Endpoint 8 Control and

Status

0

NPAK1

0

EP2FIFOFLGS

EP4FIFOFLGS

EP6FIFOFLGS

EP8FIFOFLGS

EP2FIFOBCH

EP2FIFOBCL

EP4FIFOBCH

EP4FIFOBCL

EP6FIFOBCH

EP6FIFOBCL

EP8FIFOBCH

EP8FIFOBCL

SUDPTRH

Endpoint 2 slave FIFO

Flags

0

EF

Endpoint 4 slave FIFO

Flags

0

PF

EF

FF

00000010 R

Endpoint 6 slave FIFO

Flags

0

PF

EF

FF

00000110 R

Endpoint 8 slave FIFO

Flags

0

PF

EF

FF

00000110 R

Endpoint 2 slave FIFO

total byte count H

0

BC12

BC4

0

BC11

BC3

0

BC10

BC2

BC10

BC2

BC10

BC2

BC10

BC2

A10

A2

BC9

BC1

BC9

BC1

BC9

BC1

BC9

BC1

A9

BC8

BC0

BC8

BC0

BC8

BC0

BC8

BC0

A8

00000000 R

Endpoint 2 slave FIFO

total byte count L

BC7

0

BC6

0

BC5

0

00000000 R

Endpoint 4 slave FIFO

total byte count H

00000000 R

Endpoint 4 slave FIFO

total byte count L

BC7

0

BC6

0

BC5

0

BC4

0

BC3

BC11

BC3

0

00000000 R

Endpoint 6 slave FIFO

total byte count H

00000000 R

Endpoint 6 slave FIFO

total byte count L

BC7

0

BC6

0

BC5

0

BC4

0

00000000 R

Endpoint 8 slave FIFO

total byte count H

00000000 R

Endpoint 8 slave FIFO

total byte count L

BC7

BC6

A14

A6

0

BC5

A13

A5

0

BC4

A12

A4

BC3

A11

A3

00000000 R

Setup Data Pointer high A15

address byte

xxxxxxxx RW

xxxxxxx0 bbbbbbbr

SUDPTRL

Setup Data Pointer low ad-A7

dress byte

A1

0

SUDPTRCTL

Setup Data Pointer Auto

Mode

0

SDPAUTO 00000001 RW

2

reserved

E6B8 8

SET-UPDAT

8 bytes of setup data

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx R

SET-UPDAT[0] =

bmRequestType

SET-UPDAT[1] =

bmRequest

SET-UPDAT[2:3] = wVal-

ue

SET-UPDAT[4:5] = wInd-

ex

SET-UPDAT[6:7] =

wLength

GPIF

E6C0 1

E6C1 1

GPIFWFSELECT

GPIFIDLECS

Waveform Selector

SINGLEWR1 SINGLEWR0 SINGLERD1 SINGLERD0 FIFOWR1 FIFOWR0

FIFORD1

0

FIFORD0

IDLEDRV

11100100 RW

10000000 RW

GPIF Done, GPIF IDLE DONE

drive mode

0

E6C2 1

E6C3 1

E6C4 1

E6C5 1

GPIFIDLECTL

GPIFCTLCFG

Inactive Bus, CTL states

CTL Drive Type

0

CTL5

0

CTL4

0

CTL3

0

CTL2

0

CTL1

0

CTL0

11111111 RW

00000000 RW

TRICTL

0

CTL0

[11]

GPIFADRH

GPIF Address H

0

GPIFA8

GPIFA0

[11]

GPIFADRL

GPIF Address L

GPIFA7

GPIFA6

GPIFA5

GPIFA4

GPIFA3

GPIFA2

GPIFA1

FLOWSTATE

E6C6 1

Flowstate Enable and

Selector

FSE

0

FS2

FS1

FS0

00000000 brrrrbbb

E6C7 1

E6C8 1

FLOWLOGIC

Flowstate Logic

LFUNC1

CTL0E3

LFUNC0

CTL0E2

TERMA2

TERMA1

TERMA0

CTL3

TERMB2

CTL2

TERMB1

CTL1

TERMB0

CTL0

00000000 RW

FLOWEQ0CTL

CTL-Pin States in

Flowstate

(when Logic = 0)

CTL0E1/

CTL5

CTL0E0/

CTL4

E6C9 1

E6CA 1

FLOWEQ1CTL

CTL-Pin States in Flow- CTL0E3

state (when Logic = 1)

CTL0E2

CTL0E1/

CTL5

CTL0E0/

CTL4

CTL3

CTL2

CTL1

CTL0

00000000 RW

00010010 RW

FLOWHOLDOFF

Holdoff Configuration

HOPERIOD3 HOPERIOD2 HOPERIOD1 HOPERIOD HOSTATE HOCTL2

0

HOCTL1

HOCTL0

Document #: 38-08032 Rev. *M

Page 32 of 62

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Table 12. FX2LP Register Summary (continued)

Hex Size Name

Description

b7

b6

b5

b4

b3

0

b2

b1

b0

Default

Access

E6CB 1

FLOWSTB

Flowstate Strobe

Configuration

SLAVE

RDYASYNC CTLTOGL

SUSTAIN

MSTB2

MSTB1

MSTB0

00100000 RW

E6CC 1

FLOWSTBEDGE

Flowstate Rising/Falling

Edge Configuration

0

FALLING

RISING

00000001 rrrrrrbb

E6CD 1

E6CE 1

FLOWSTBPERIOD Master-Strobe Half-Period D7

[11]

D6

D5

D4

D3

D2

D1

D0

00000010 RW

00000000 RW

GPIFTCB3

GPIFTCB2

GPIFTCB1

GPIFTCB0

GPIF Transaction Count TC31

Byte 3

TC30

TC29

TC28

TC27

TC26

TC25

TC24

[11]

E6CF 1

E6D0 1

E6D1 1

2

GPIF Transaction Count TC23

Byte 2

TC22

TC14

TC6

TC21

TC13

TC5

TC20

TC12

TC4

TC19

TC11

TC3

TC18

TC10

TC2

TC17

TC9

TC1

TC16

TC8

TC0

00000000 RW

00000001 RW

00000000 RW

GPIF Transaction Count TC15

Byte 1

GPIF Transaction Count TC7

Byte 0

reserved

[11]

E6D2 1

E6D3 1

EP2GPIFFLGSEL

Endpoint 2 GPIF Flag

select

0

x

0

x

0

x

0

x

0

x

0

x

FS1

0

FS0

00000000 RW

EP2GPIFPFSTOP

Endpoint 2 GPIF stop

transaction on prog. flag

FIFO2FLAG 00000000 RW

[11]

E6D4 1

3

EP2GPIFTRIG

Endpoint 2 GPIF Trigger

x

xxxxxxxx W

reserved

[11]

E6DA 1

E6DB 1

EP4GPIFFLGSEL

Endpoint 4 GPIF Flag

select

0

x

0

x

0

x

0

x

0

x

0

x

FS1

0

FS0

00000000 RW

EP4GPIFPFSTOP

Endpoint 4 GPIF stop

transaction on GPIF Flag

FIFO4FLAG 00000000 RW

[11]

E6DC 1

3

EP4GPIFTRIG

Endpoint 4 GPIF Trigger

x

xxxxxxxx W

reserved

[11]

E6E2 1

E6E3 1

EP6GPIFFLGSEL

Endpoint 6 GPIF Flag

select

0

x

0

x

0

x

0

x

0

x

0

x

FS1

0

FS0

00000000 RW

EP6GPIFPFSTOP

Endpoint 6 GPIF stop

transaction on prog. flag

FIFO6FLAG 00000000 RW

[11]

E6E4 1

3

EP6GPIFTRIG

Endpoint 6 GPIF Trigger

x

xxxxxxxx W

reserved

[11]

E6EA 1

E6EB 1

EP8GPIFFLGSEL

Endpoint 8 GPIF Flag

select

0

x

0

x

0

x

0

x

0

x

0

x

FS1

0

FS0

00000000 RW

EP8GPIFPFSTOP

Endpoint 8 GPIF stop

transaction on prog. flag

FIFO8FLAG 00000000 RW

[11]

E6EC 1

3

EP8GPIFTRIG

Endpoint 8 GPIF Trigger

x

xxxxxxxx W

reserved

E6F0 1

XGPIFSGLDATH

GPIF Data H

D15

D14

D6

D13

D12

D4

0

D11

D3

0

D10

D2

0

D9

D1

0

D8

D0

0

xxxxxxxx RW

(16-bit mode only)

E6F1 1

E6F2 1

E6F3 1

XGPIFSGLDATLX

Read/Write GPIF Data L & D7

trigger transaction

D5

XGPIFSGLDATL-

NOX

Read GPIF Data L, no

transaction trigger

D7

D6

D5

xxxxxxxx

R

GPIFREADYCFG

InternalRDY,Sync/Async, INTRDY

RDY pin states

SAS

TCXRDY5

00000000 bbbrrrrr

E6F4 1

E6F5 1

E6F6 2

GPIFREADYSTAT

GPIFABORT

GPIF Ready Status

0

x

0

x

RDY5

x

RDY4

x

RDY3

x

RDY2

x

RDY1

x

RDY0

x

00xxxxxx

xxxxxxxx

R

Abort GPIF Waveforms

W

reserved

ENDPOINT BUFFERS

E740 64 EP0BUF

EP0-IN/-OUT buffer

EP1-OUT buffer

EP1-IN buffer

D7

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx RW

RW

E780 64 EP10UTBUF

E7C0 64 EP1INBUF

E800 2048 reserved

F000 1024 EP2FIFOBUF

512/1024byteEP2/slave D7

FIFO buffer (IN or OUT)

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx RW

F400 512 EP4FIFOBUF

512 byte EP 4 / slave FIFO D7

buffer (IN or OUT)

xxxxxxxx RW

F600 512 reserved

F800 1024 EP6FIFOBUF

512/1024byteEP6/slave D7

FIFO buffer (IN or OUT)

D6

D5

D4

D3

D2

D1

D0

xxxxxxxx RW

FC00 512 EP8FIFOBUF

FE00 512 reserved

512 byte EP 8 / slave FIFO D7

buffer (IN or OUT)

Document #: 38-08032 Rev. *M

Page 33 of 62

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Table 12. FX2LP Register Summary (continued)

Hex Size Name

Description

b7

0

b6

b5

0

b4

0

b3

0

b2

0

b1

0

b0

Default

Access

xxxx

I²C Configuration Byte

DISCON

400KHZ

xxxxxxxx n/a

[14]

Special Function Registers (SFRs)

[13]

80

81

82

83

84

85

86

87

88

1

IOA

Port A (bit addressable) D7

D6

A6

A14

A6

A14

0

D5

A5

A13

A5

A13

0

D4

A4

A12

A4

A12

0

D3

A3

A11

A3

A11

0

D2

A2

A10

A2

A10

0

D1

A1

A9

A1

A9

0

D0

xxxxxxxx RW

00000111 RW

00000000 RW

00110000 RW

00000000 RW

SP

Stack Pointer

D7

D0

DPL0

DPH0

Data Pointer 0 L

Data Pointer 0 H

Data Pointer 1 L

Data Pointer 1 H

Data Pointer 0/1 select

Power Control

A7

A0

A15

A7

A8

[13]

DPL1

DPH1

A0

[13]

A15

0

A8

[13]

DPS

SEL

IDLE

IT0

PCON

TCON

SMOD0

TF1

x

1

x

Timer/Counter Control

(bit addressable)

TR1

TF0

TR0

IE1

IT1

IE0

89

1

TMOD

Timer/Counter Mode

Control

GATE

CT

M1

M0

GATE

CT

M1

M0

00000000 RW

8A

8B

8C

8D

8E

8F

90

91

92

1

TL0

Timer 0 reload L

Timer 1 reload L

Timer 0 reload H

Timer 1 reload H

Clock Control

D7

D15

x

D6

D14

x

D5

D4

D3

D2

D1

D0

00000000 RW

00000001 RW

TL1

D5

D4

D3

D2

D1

D0

TH0

D13

T2M

D12

T1M

D11

T0M

D10

MD2

D9

D8

TH1

D9

D8

[13]

CKCON

MD1

MD0

reserved

[13]

IOB

Port B (bit addressable) D7

External Interrupt Flag(s) IE5

D6

D5

D4

D3

1

D2

0

D1

0

D0

0

xxxxxxxx RW

00001000 RW

00000000 RW

[13]

EXIF

IE4

A14

I²CINT

A13

USBNT

A12

[13]

MPAGE

Upper Addr Byte of MOVX A15

using @R0 / @R1

A11

A10

A9

A8

93

98

5

1

reserved

SCON0

Serial Port 0 Control

(bit addressable)

SM0_0

SM1_0

SM2_0

REN_0

TB8_0

RB8_0

TI_0

RI_0

00000000 RW

99

9A

9B

9C

9D

9E

9F

A0

A1

A2

A3

A8

1

5

1

SBUF0

Serial Port 0 Data Buffer D7

Autopointer 1 Address H A15

Autopointer 1 Address L A7

D6

D5

D4

D3

A11

A3

D2

D1

A9

A1

D0

A8

A0

00000000 RW

[13]

AUTOPTRH1

A14

A6

A13

A5

A12

A4

A10

A2

[13]

AUTOPTRL1

reserved

[13]

AUTOPTRH2

Autopointer 2 Address H A15

Autopointer 2 Address L A7

A14

A6

A13

A5

A12

A4

A11

A3

A10

A2

A9

A1

A8

A0

00000000 RW

[13]

AUTOPTRL2

reserved

[13]

IOC

Port C (bit addressable) D7

D6

x

D5

x

D4

x

D3

x

D2

x

D1

x

D0

x

xxxxxxxx RW

[13]

INT2CLR

Interrupt 2 clear

Interrupt 4 clear

x

xxxxxxxx

W

[13]

INT4CLR

x

reserved

IE

Interrupt Enable

(bit addressable)

EA

ES1

ET2

ES0

ET1

EX1

ET0

EX0

00000000 RW

A9

AA

1

reserved

[13]

EP2468STAT

Endpoint 2,4,6,8 status

flags

EP8F

EP8E

EP6F

EP6E

EP4F

EP4E

EP2F

EP2E

01011010 R

00100010 R

01100110 R

AB

AC

1

EP24FIFOFLGS

[13]

Endpoint 2,4 slave FIFO

status flags

0

EP4PF

EP8PF

EP4EF

EP8EF

EP4FF

EP8FF

0

EP2PF

EP6PF

EP2EF

EP6EF

EP2FF

EP6FF

EP68FIFOFLGS

[13]

Endpoint 6,8 slave FIFO

status flags

AD

AF

B0

B1

2

1

reserved

[13]

AUTOPTRSETUP

Autopointer 1&2 setup

0

APTR2INC APTR1INC APTREN

00000110 RW

xxxxxxxx RW

[13]

IOD

Port D (bit addressable) D7

D6

D5

D4

D3

D2

D1

D0

[13]

IOE

Port E

(NOT bit addressable)

D7

[13]

B2

B3

B4

B5

B6

B7

B8

1

OEA

Port A Output Enable

Port B Output Enable

Port C Output Enable

Port D Output Enable

Port E Output Enable

D7

D6

D5

D4

D3

D2

D1

D0

00000000 RW

[13]

OEB

[13]

OEC

[13]

OED

[13]

OEE

reserved

IP

Interrupt Priority (bit ad-

dressable)

1

PS1

PT2

PS0

PT1

PX1

PT0

PX0

10000000 RW

B9

BA

1

reserved

[13]

EP01STAT

Endpoint 0&1 Status

0

EP1INBSY EP1OUTBS EP0BSY

Y

00000000 R

[13, 11]

BB

1

GPIFTRIG

Endpoint 2,4,6,8 GPIF

slave FIFO Trigger

DONE

RW

EP1

EP0

10000xxx brrrrbbb

BC

BD

1

reserved

[13]

GPIFSGLDATH

GPIF Data H (16-bit mode D15

only)

D14

D13

D12

D11

D10

D9

D8

xxxxxxxx RW

Note

13. SFRs not part of the standard 8051 architecture.

14. If no EEPROM is detected by the SIE then the default is 00000000.

Document #: 38-08032 Rev. *M

Page 34 of 62

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Table 12. FX2LP Register Summary (continued)

Hex Size Name

Description

b7

b6

b5

b4

b3

b2

b1

b0

Default

xxxxxxxx RW

xxxxxxxx

Access

[13]

BE

BF

1

GPIFSGLDATLX

GPIFSGLDATL-

GPIF Data L w/ Trigger D7

GPIF Data L w/ No Trigger D7

D6

D5

D4

D3

D2

D1

D0

R

[13]

NOX

[13]

C0

1

SCON1

Serial Port 1 Control (bit SM0_1

addressable)

SM1_1

D6

SM2_1

D5

REN_1

D4

TB8_1

D3

RB8_1

D2

TI_1

D1

RI_1

D0

00000000 RW

[13]

C1

C2

C8

1

6

1

SBUF1

Serial Port 1 Data Buffer D7

reserved

T2CON

Timer/Counter 2 Control TF2

(bit addressable)

EXF2

RCLK

TCLK

EXEN2

TR2

CT2

CPRL2

00000000 RW

C9

CA

1

reserved

RCAP2L

Capture for Timer 2, au- D7

to-reload, up-counter

D6

D5

D4

D3

D2

D1

D0

00000000 RW

CB

1

RCAP2H

Capture for Timer 2, au- D7

to-reload, up-counter

CC

CD

CE

D0

1

2

1

TL2

Timer 2 reload L

Timer 2 reload H

D7

D6

D5

D4

D3

D2

D1

D9

D0

D8

00000000 RW

TH2

D15

D14

D13

D12

D11

D10

reserved

PSW

Program Status Word (bit CY

addressable)

AC

F0

RS1

RS0

OV

F1

P

00000000 RW

D1

D8

D9

E0

7

1

7

1

reserved

[13]

EICON

External Interrupt Control SMOD1

1

ERESI

D5

RESI

D4

INT6

D3

0

01000000 RW

00000000 RW

reserved

ACC

Accumulator (bit address- D7

able)

D6

D2

D1

D0

E1

E8

7

1

reserved

[13]

EIE

External Interrupt En-

able(s)

1

EX6

EX5

EX4

EI²C

EUSB

11100000 RW

E9

F0

F1

F8

7

1

7

1

reserved

B

B (bit addressable)

D7

1

D6

1

D5

1

D4

D3

D2

D1

D0

00000000 RW

11100000 RW

reserved

[13]

EIP

External Interrupt Priority

Control

PX6

PX5

PX4

PI²C

PUSB

F9

7

reserved

R = all bits read-only

W = all bits write-only

r = read-only bit

w = write-only bit

b = both read/write bit

Document #: 38-08032 Rev. *M

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6. Absolute Maximum Ratings

Exceeding maximum ratings may impair the useful life of the

device. These user guidelines are not tested.

Max Output Current, per I/O port......................................10 mA

Max Output Current, all five I/O ports

Storage Temperature ......................................–65°C to +150°C

(128- and 100-pin packages)............................................50 mA

Ambient Temperature with

Power Supplied (Commercial)...............................0°C to +70°C

7. Operating Conditions

Ambient Temperature with

Power Supplied (Industrial) ............................–40°C to + 105°C

T_A(Ambient Temperature Under Bias)

Commercial ...........................................................0°C to +70°C

Supply Voltage to Ground Potential.................... –0.5V to +4.0V

DC Input Voltage to Any Input Pin^[15]................................5.25V

T_A(Ambient Temperature Under Bias)

Industrial–40°C to +105°C

Supply Voltage................................................+3.00V to +3.60V

Ground Voltage.......................................................................0V

DC Voltage Applied to Outputs

in High Z State.......................................... –0.5V to VCC + 0.5V

Power Dissipation..........................................................300 mW

Static Discharge Voltage................. ...............................>2000V

F

_OSC(Oscillator or Crystal Frequency)............24 MHz ± 10 ppm,

Parallel Resonant

8. Thermal Characteristics

The following table displays the thermal characteristics of various packages:

Table 13. Thermal Characteristics

θJc

θCa

θJa

θa

Junction to Case Case to Ambient

^{Junction to}θ^AJ^mc^b+^ieθⁿC^ta^Temperature

Ambient Temperature

Package

Temperature

(°C)

(°C/W)

24.4

11.9

(°C/W)

23.3

34.0

27.7

14.6

27.7

(°C/W)

47.7

45.9

43.2

25.2

58.6

56 SSOP

100 TQFP

128 TQFP

56 QFN

70

15.5

10.6

30.9

56 VFBGA

^{The Junction Temperature}θj, can be calculated using the following equation: θj = P*θJa + θa

where,

P = Power

θJa = Junction to Ambient Temperature (θJc + θCa)

θa = Ambient Temperature (70 C)

^{The Case Temperature}θc, can be calculated using the following equation: θc = P*θCa + θa

where,

P = Power

θCa = Case to Ambient Temperature

θa = Ambient Temperature (70 C)

Note

15. Do not power I/O with chip power off.

Document #: 38-08032 Rev. *M

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9. DC Characteristics

Table 14. DC Characteristics

Parameter

VCC

VCC Ramp Up 0 to 3.3V

Description

Conditions

Min

3.00

200

2

Typ

Max

Unit

V

Supply Voltage

3.3

3.60

μs

V

V_IH

V_IL

Input HIGH Voltage

5.25

0.8

Input LOW Voltage

–0.5

2

V

V_{IH_X}

V_{IL_X}

I_I

Crystal Input HIGH Voltage

Crystal Input LOW Voltage

Input Leakage Current

Output Voltage HIGH

Output LOW Voltage

Output Current HIGH

Output Current LOW

Input Pin Capacitance

5.25

0.8

V

–0.5

V

0< V_IN< VCC

±10

μA

V

V_OH

V_OL

I_OH

I_OL

I_OUT= 4 mA

2.4

I_OUT= –4 mA

0.4

4

V

mA

pF

μA

mA

mS

μS

4

C_IN

Except D+/D–

10

D+/D–

15

I_SUSP

Suspend Current

Connected

300

100

0.5

0.3

50

380^[16]

150^[16]

1.2^[16]

1.0^[16]

85

CY7C68014/CY7C68016

Suspend Current

Disconnected

Connected

CY7C68013/CY7C68015

Supply Current

Disconnected

I_CC

8051 running, connected to USB HS

8051 running, connected to USB FS

VCC min = 3.0V

35

65

T_RESET

Reset Time after Valid Power

Pin Reset after powered on

5.0

200

9.1 USB Transceiver

USB 2.0 compliant in full speed and high speed modes.

10. AC Electrical Characteristics

10.1 USB Transceiver

USB 2.0 compliant in full speed and high speed modes.

Note

16. Measured at Max VCC, 25°C.

Document #: 38-08032 Rev. *M

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10.2 Program Memory Read

Figure 12. Program Memory Read Timing Diagram

t

CL

CLKOUT^[17]

t

AV

A[15..0]

t

STBH

STBL

PSEN#

D[7..0]

[18]

ACC1

t

DH

t

data in

t

SOEL

OE#

CS#

t

SCSL

Table 15. Program Memory Read Parameters

Parameter Description

1/CLKOUT Frequency

Min

Typ

Max

Unit

ns

Notes

48 MHz

24 MHz

12 MHz

t_CL

20.83

41.66

83.2

t_AV

Delay from Clock to Valid Address

Clock to PSEN Low

Clock to PSEN High

Clock to OE Low

0

10.7

8

t_STBL

t_STBH

t_SOEL

t_SCSL

t_DSU

t_DH

8

11.1

13

Clock to CS Low

Data Setup to Clock

Data Hold Time

9.6

0

Notes

17. CLKOUT is shown with positive polarity.

18. t

is computed from the above parameters as follows:

ACC1

t

(24 MHz) = 3*t – t – t

= 106 ns

= 43 ns.

CL

AV

DSU

(48 MHz) = 3*t – t – t

CL

AV

Document #: 38-08032 Rev. *M

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10.3 Data Memory Read

Figure 13. Data Memory Read Timing Diagram

t

CL

Stretch = 0

CLKOUT^[17]

t

AV

A[15..0]

t

STBH

STBL

RD#

t

SCSL

CS#

OE#

t

SOEL

t

DSU

[19]

t

DH

t

ACC1

D[7..0]

data in

Stretch = 1

t

CL

CLKOUT^[17]

t

AV

A[15..0]

RD#

CS#

t

DSU

t

[19]

DH

t

ACC1

D[7..0]

data in

Table 16. Data Memory Read Parameters

Parameter Description

1/CLKOUT Frequency

Min

Typ

20.83

41.66

83.2

Max

Unit

ns

Notes

48 MHz

24 MHz

12 MHz

t_CL

t_AV

Delay from Clock to Valid Address

Clock to RD LOW

10.7

11

t_STBL

t_STBH

t_SCSL

t_SOEL

t_DSU

t_DH

Clock to RD HIGH

11

Clock to CS LOW

13

Clock to OE LOW

11.1

Data Setup to Clock

Data Hold Time

9.6

0

When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is only active while either

RD# or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the above address valid time for

which is based on the stretch value

Note

19. t

and t

are computed from the above parameters as follows:

ACC2

ACC3

t

(24 MHz) = 3*t – t –t

= 106 ns

(48 MHz) = 3*t – t – t = 43 ns

DSU

CL

AV DSU

CL

AV

(24 MHz) = 5*t – t –t = 190 ns

(48 MHz) = 5*t – t – t = 86 ns.

DSU

CL

AV DSU

CL

AV

Document #: 38-08032 Rev. *M

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10.4 Data Memory Write

Figure 14. Data Memory Write Timing Diagram

t

CL

CLKOUT

A[15..0]

t

AV

t

STBL

STBH

AV

WR#

CS#

t

SCSL

t

ON1

t

OFF1

data out

D[7..0]

Stretch = 1

t

CL

CLKOUT

A[15..0]

t

AV

WR#

CS#

t

ON1

t

OFF1

data out

D[7..0]

Table 17. Data Memory Write Parameters

Parameter Description

Delay from Clock to Valid Address

Min

0

Max

10.7

11.2

13.0

13.1

Unit

ns

Notes

t_AV

t_STBL

t_STBH

t_SCSL

t_ON1

Clock to WR Pulse LOW

Clock to WR Pulse HIGH

Clock to CS Pulse LOW

Clock to Data Turn-on

Clock to Data Hold Time

0

ns

0

ns

0

ns

t_OFF1

ns

When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is only active while either RD#

or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the above address valid time for which is

based on the stretch value.

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10.5 PORTC Strobe Feature Timings

The RD# and WR# are present in the 100-pin version and the

128-pin package. In these 100-pin and 128-pin versions, an

8051 control bit can be set to pulse the RD# and WR# pins when

the 8051 reads from or writes to PORTC. This feature is enabled

by setting PORTCSTB bit in CPUCS register.

The RD# signal prompts the external logic to prepare the next

data byte. Nothing gets sampled internally on assertion of the

RD# signal itself, it is just a prefetch type signal to get the next

data byte prepared. So, using it with that in mind easily meets the

setup time to the next read.

The RD# and WR# strobes are asserted for two CLKOUT cycles

when PORTC is accessed.

The purpose of this pulsing of RD# is to allow the external

peripheral to know that the 8051 is done reading PORTC and the

data was latched into PORTC three CLKOUT cycles before

asserting the RD# signal. After the RD# is pulsed, the external

logic can update the data on PORTC.

The WR# strobe is asserted two clock cycles after PORTC is

updated and is active for two clock cycles after that, as shown in

Figure 15.

Following is the timing diagram of the read and write strobing

function on accessing PORTC. Refer to Section 10.3 and

Section 10.4 for details on propagation delay of RD# and WR#

signals.

As for read, the value of PORTC three clock cycles before the

assertion of RD# is the value that the 8051 reads in. The RD# is

pulsed for 2 clock cycles after 3 clock cycles from the point when

the 8051 has performed a read function on PORTC.

Figure 15. WR# Strobe Function when PORTC is Accessed by 8051

t

CLKOUT

PORTC IS UPDATED

WR#

t

STBL

STBH

Figure 16. RD# Strobe Function when PORTC is Accessed by 8051

t

CLKOUT

8051 READS PORTC

RD#

DATA CAN BE UPDATED BY EXTERNAL LOGIC

DATA MUST BE HELD FOR 3 CLK CYLCES

t

STBL

STBH

Document #: 38-08032 Rev. *M

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10.6 GPIF Synchronous Signals

Figure 17. GPIF Synchronous Signals Timing Diagram^[20]

t

IFCLK

t

SGA

GPIFADR[8:0]

RDY

X

t

SRY

t

RYH

DATA(input)

valid

t

SGD

t

DAH

CTL_X

t

XCTL

DATA(output)

N

N+1

t

XGD

Table 18. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK^{[20, 21]}

Parameter

t_IFCLK

Description

Min

20.83

8.9

0

Max

Unit

ns

IFCLK Period

t_SRY

t_RYH

t_SGD

t_DAH

t_SGA

t_XGD

t_XCTL

RDY_Xto Clock Setup Time

Clock to RDY_X

GPIF Data to Clock Setup Time

GPIF Data Hold Time

9.2

0

Clock to GPIF Address Propagation Delay

Clock to GPIF Data Output Propagation Delay

Clock to CTL_XOutput Propagation Delay

7.5

11

6.7

Table 19. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK^[21]

Parameter

t_IFCLK

Description

Min.

20.83

2.9

Max.

Unit

ns

IFCLK Period^[22]

200

t_SRY

t_RYH

t_SGD

t_DAH

t_SGA

t_XGD

t_XCTL

RDY_Xto Clock Setup Time

Clock to RDY_X

3.7

GPIF Data to Clock Setup Time

GPIF Data Hold Time

3.2

4.5

Clock to GPIF Address Propagation Delay

Clock to GPIF Data Output Propagation Delay

Clock to CTL_XOutput Propagation Delay

11.5

15

10.7

Notes

20. Dashed lines denote signals with programmable polarity.

21. GPIF asynchronous RDY signals have a minimum Setup time of 50 ns when using internal 48-MHz IFCLK.

x

22. IFCLK must not exceed 48 MHz.

Document #: 38-08032 Rev. *M

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10.7 Slave FIFO Synchronous Read

Figure 18. Slave FIFO Synchronous Read Timing Diagram^[20]

t

IFCLK

SLRD

t

RDH

t

SRD

t

XFLG

FLAGS

DATA

N+1

N

t

XFD

OEon

t

OEoff

SLOE

Table 20. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK^[21]

Parameter

t_IFCLK

Description

Min

20.83

18.7

0

Max

Unit

ns

IFCLK Period

t_SRD

t_RDH

t_OEon

t_OEoff

t_XFLG

t_XFD

SLRD to Clock Setup Time

ns

Clock to SLRD Hold Time

ns

SLOE Turn-on to FIFO Data Valid

SLOE Turn-off to FIFO Data Hold

Clock to FLAGS Output Propagation Delay

Clock to FIFO Data Output Propagation Delay

10.5

9.5

ns

11

ns

Table 21. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK^[21]

Parameter

t_IFCLK

Description

Min

20.83

12.7

3.7

Max

Unit

ns

IFCLK Period

200

t_SRD

t_RDH

t_OEon

t_OEoff

t_XFLG

t_XFD

SLRD to Clock Setup Time

ns

Clock to SLRD Hold Time

ns

SLOE Turn-on to FIFO Data Valid

SLOE Turn-off to FIFO Data Hold

Clock to FLAGS Output Propagation Delay

Clock to FIFO Data Output Propagation Delay

10.5

13.5

15

ns

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10.8 Slave FIFO Asynchronous Read

Figure 19. Slave FIFO Asynchronous Read Timing Diagram^[20]

t

RDpwh

SLRD

t

RDpwl

t

XFLG

t

FLAGS

XFD

DATA

SLOE

N+1

N

t

OEoff

OEon

Table 22. Slave FIFO Asynchronous Read Parameters^[23]

Parameter Description

t_RDpwlSLRD Pulse Width LOW

SLRD Pulse Width HIGH

Min

Max

Unit

ns

50

t_RDpwh

t_XFLG

t_XFD

ns

SLRD to FLAGS Output Propagation Delay

SLRD to FIFO Data Output Propagation Delay

SLOE Turn-on to FIFO Data Valid

70

15

ns

t_OEon

t_OEoff

10.5

ns

SLOE Turn-off to FIFO Data Hold

ns

Note

23. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.

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10.9 Slave FIFO Synchronous Write

Figure 20. Slave FIFO Synchronous Write Timing Diagram^[20]

t

IFCLK

SLWR

t

WRH

t

SWR

DATA

N

Z

t

FDH

SFD

FLAGS

t

XFLG

Table 23. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK^[21]

Parameter

t_IFCLK

Description

Min

20.83

10.4

0

Max

Unit

ns

IFCLK Period

t_SWR

t_WRH

t_SFD

SLWR to Clock Setup Time

ns

Clock to SLWR Hold Time

ns

FIFO Data to Clock Setup Time

Clock to FIFO Data Hold Time

Clock to FLAGS Output Propagation Time

9.2

0

ns

t_FDH

t_XFLG

ns

9.5

ns

Table 24. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK^[21]

Parameter

t_IFCLK

Description

Min

20.83

12.1

3.6

Max

Unit

ns

IFCLK Period

200

t_SWR

t_WRH

t_SFD

SLWR to Clock Setup Time

ns

Clock to SLWR Hold Time

ns

FIFO Data to Clock Setup Time

Clock to FIFO Data Hold Time

Clock to FLAGS Output Propagation Time

3.2

ns

t_FDH

t_XFLG

4.5

ns

13.5

ns

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10.10 Slave FIFO Asynchronous Write

Figure 21. Slave FIFO Asynchronous Write Timing Diagram^[20]

t

WRpwh

SLWR

SLWR/SLCS#

t

WRpwl

t

FDH

SFD

DATA

t

XFD

FLAGS

Table 25. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK ^[23]

Parameter

t_WRpwl

t_WRpwh

t_SFD

Description

Min

50

Max

Unit

ns

SLWR Pulse LOW

SLWR Pulse HIGH

70

ns

SLWR to FIFO DATA Setup Time

FIFO DATA to SLWR Hold Time

10

ns

t_FDH

10

ns

t_XFD

SLWR to FLAGS Output Propagation Delay

70

ns

10.11 Slave FIFO Synchronous Packet End Strobe

Figure 22. Slave FIFO Synchronous Packet End Strobe Timing Diagram^[20]

IFCLK

t

PEH

PKTEND

FLAGS

t

SPE

t

XFLG

Table 26. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK^[21]

Parameter

t_IFCLK

Description

Min

20.83

14.6

0

Max

Unit

ns

IFCLK Period

t_SPE

t_PEH

t_XFLG

PKTEND to Clock Setup Time

ns

Clock to PKTEND Hold Time

ns

Clock to FLAGS Output Propagation Delay

9.5

ns

Table 27. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK^[21]

Parameter

t_IFCLK

Description

Min

20.83

8.6

Max

Unit

ns

IFCLK Period

200

t_SPE

t_PEH

t_XFLG

PKTEND to Clock Setup Time

ns

Clock to PKTEND Hold Time

2.5

ns

Clock to FLAGS Output Propagation Delay

13.5

ns

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There is no specific timing requirement that should be met for

asserting PKTEND pin to asserting SLWR. PKTEND can be

asserted with the last data value clocked into the FIFOs or there-

after. The setup time t_SPEand the hold time t_PEHmust be met.

caused the last byte or word to be clocked into the previous auto

committed packet. Figure 23 shows this scenario. X is the value

the AUTOINLEN register is set to when the IN endpoint is

configured to be in auto mode.

Although there are no specific timing requirements for the

PKTEND assertion, there is a specific corner case condition that

needs attention while using the PKTEND to commit a one byte

or word packet. There is an additional timing requirement that

needs to be met when the FIFO is configured to operate in auto

mode and it is required to send two packets back to back: a full

packet (full defined as the number of bytes in the FIFO meeting

the level set in AUTOINLEN register) committed automatically

followed by a short one byte or word packet committed manually

using the PKTEND pin. In this scenario, the user must ensure to

assert PKTEND at least one clock cycle after the rising edge that

Figure 23 shows a scenario where two packets are committed.

The first packet gets committed automatically when the number

of bytes in the FIFO reaches X (value set in AUTOINLEN

register) and the second one byte/word short packet being

committed manually using PKTEND.

Note that there is at least one IFCLK cycle timing between the

assertion of PKTEND and clocking of the last byte of the previous

packet (causing the packet to be committed automatically).

Failing to adhere to this timing results in the FX2 failing to send

the one byte or word short packet.

Figure 23. Slave FIFO Synchronous Write Sequence and Timing Diagram^[20]

t

IFCLK

t

SFA

FAH

FIFOADR

>= t

WRH

>= t

SWR

SLWR

DATA

t

FDH

t

FDH

t

SFD

t

SFD

FDH

SFD

t

SFD

t

FDH

SFD

FDH

X-4

X-2

X-1

1

X-3

X

At least one IFCLK cycle

t

SPE

t

PEH

PKTEND

10.12 Slave FIFO Asynchronous Packet End Strobe

Figure 24. Slave FIFO Asynchronous Packet End Strobe Timing Diagram^[20]

t

PEpwh

PKTEND

FLAGS

t

PEpwl

t

XFLG

Table 28. Slave FIFO Asynchronous Packet End Strobe Parameters^[23]

Parameter Description

t_PEpwlPKTEND Pulse Width LOW

t_PWpwh

t_XFLG

Min

50

Max

Unit

ns

PKTEND Pulse Width HIGH

50

PKTEND to FLAGS Output Propagation Delay

115

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10.13 Slave FIFO Output Enable

Figure 25. Slave FIFO Output Enable Timing Diagram^[20]

SLOE

t

OEoff

t

OEon

DATA

Table 29. Slave FIFO Output Enable Parameters

Parameter

t_OEon

t_OEoff

Description

Min

Max

10.5

Unit

ns

SLOE Assert to FIFO DATA Output

SLOE Deassert to FIFO DATA Hold

ns

10.14 Slave FIFO Address to Flags/Data

Figure 26. Slave FIFO Address to Flags/Data Timing Diagram^[20]

FIFOADR [1.0]

t

XFLG

FLAGS

DATA

t

XFD

N

N+1

Table 30. Slave FIFO Address to Flags/Data Parameters

Parameter

t_XFLG

t_XFD

Description

FIFOADR[1:0] to FLAGS Output Propagation Delay

FIFOADR[1:0] to FIFODATA Output Propagation Delay

Min

Max

10.7

14.3

Unit

ns

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10.15 Slave FIFO Synchronous Address

Figure 27. Slave FIFO Synchronous Address Timing Diagram^[20]

IFCLK

SLCS/FIFOADR [1:0]

t

FAH

SFA

Table 31. Slave FIFO Synchronous Address Parameters ^[21]

Parameter

t_IFCLK

t_SFA

t_FAH

Description

Interface Clock Period

Min

20.83

25

Max

Unit

ns

200

FIFOADR[1:0] to Clock Setup Time

Clock to FIFOADR[1:0] Hold Time

ns

10

ns

10.16 Slave FIFO Asynchronous Address

Figure 28. Slave FIFO Asynchronous Address Timing Diagram^[20]

SLCS/FIFOADR [1:0]

t

FAH

t

SFA

SLRD/SLWR/PKTEND

Table 32. Slave FIFO Asynchronous Address Parameters^[23]

Parameter

Description

Min

10

Max

Unit

ns

t_SFA

t_FAH

FIFOADR[1:0] to SLRD/SLWR/PKTEND Setup Time

RD/WR/PKTEND to FIFOADR[1:0] Hold Time

10

ns

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10.17 Sequence Diagram

10.17.1 Single and Burst Synchronous Read Example

Figure 29. Slave FIFO Synchronous Read Sequence and Timing Diagram^[20]

t

IFCLK

t

SFA

t

FAH

FIFOADR

t=0

T=0

t

>= t

SRD

>= t

RDH

SRD

SLRD

SLCS

t=3

t=2

T=3

T=2

t

XFLG

FLAGS

DATA

SLOE

t

XFD

t

XFD

N+4

Data Driven: N

N+2

N+3

N+1

t

OEoff

OEon

t

OEoff

OEon

t=4

T=4

T=1

t=1

Figure 30. Slave FIFO Synchronous Sequence of Events Diagram

IFCLK

N

IFCLK

N+1

IFCLK

N+1

IFCLK

N+1

IFCLK

N+2

IFCLK

N+3

IFCLK

N+4

IFCLK

N+4

IFCLK

N+4

N

FIFO POINTER

SLOE

SLRD

SLOE

SLRD

SLOE

SLRD

SLOE

FIFO DATA BUS Not Driven

Driven: N

N+1

Not Driven

N+1

N+2

N+3

N+4

Not Driven

Figure 29 shows the timing relationship of the SLAVE FIFO

signals during a synchronous FIFO read using IFCLK as the

synchronizing clock. The diagram illustrates a single read

followed by a burst read.

If the SLCS signal is used, it must be asserted before SLRD is

asserted (The SLCS and SLRD signals must both be asserted

to start a valid read condition).

■ The FIFO pointer is updated on the rising edge of the IFCLK,

while SLRD is asserted. This starts the propagation of data

from the newly addressed location to the data bus. After a

propagation delay of t_XFD(measured from the rising edge of

IFCLK) the new data value is present. N is the first data value

read from the FIFO. To have data on the FIFO data bus, SLOE

MUST also be asserted.

■ At t = 0 the FIFO address is stable and the signal SLCS is

asserted (SLCS may be tied low in some applications). Note

that t_SFAhas a minimum of 25 ns. This means when IFCLK is

running at 48 MHz, the FIFO address setup time is more than

one IFCLK cycle.

■ At t = 1, SLOE is asserted. SLOE is an output enable only,

whose sole function is to drive the data bus. The data that is

driven on the bus is the data that the internal FIFO pointer is

currently pointing to. In this example it is the first data value in

the FIFO. Note: the data is pre-fetched and is driven on the bus

when SLOE is asserted.

The same sequence of events are shown for a burst read and

are marked with the time indicators of T = 0 through 5.

Note For the burst mode, the SLRD and SLOE are left asserted

during the entire duration of the read. In the burst read mode,

when SLOE is asserted, data indexed by the FIFO pointer is on

the data bus. During the first read cycle, on the rising edge of the

clock the FIFO pointer is updated and increments to point to

address N+1. For each subsequent rising edge of IFCLK, while

the SLRD is asserted, the FIFO pointer is incremented and the

next data value is placed on the data bus.

■ At t = 2, SLRD is asserted. SLRD must meet the setup time of

t_SRD(time from asserting the SLRD signal to the rising edge of

the IFCLK) and maintain a minimum hold time of t_RDH(time

from the IFCLK edge to the deassertion of the SLRD signal).

Document #: 38-08032 Rev. *M

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10.17.2 Single and Burst Synchronous Write

Figure 31. Slave FIFO Synchronous Write Sequence and Timing Diagram^[20]

t

IFCLK

t

SFA

t

SFA

t

FAH

FIFOADR

>= t

WRH

t=0

t

>= t

T=0

SWR

WRH

SWR

SLWR

SLCS

T=2

T=5

t=2

t=3

t

XFLG

t

XFLG

FLAGS

DATA

t

FDH

t

SFD

FDH

SFD

FDH

SFD

FDH

N+1

N+3

N

N+2

T=4

T=3

t=1

T=1

t

SPE

t

PEH

PKTEND

The Figure 31 shows the timing relationship of the SLAVE FIFO

signals during a synchronous write using IFCLK as the synchro-

nizing clock. The diagram illustrates a single write followed by

burst write of 3 bytes and committing all 4 bytes as a short packet

using the PKTEND pin.

FIFO data bus is written to the FIFO on every rising edge of

IFCLK. The FIFO pointer is updated on each rising edge of

IFCLK. In Figure 31, after the four bytes are written to the FIFO,

SLWR is deasserted. The short 4 byte packet can be committed

to the host by asserting the PKTEND signal.

There is no specific timing requirement that should be met for

asserting PKTEND signal with regards to asserting the SLWR

signal. PKTEND can be asserted with the last data value or

thereafter. The only requirement is that the setup time t_SPEand

the hold time t_PEHmust be met. In the scenario of Figure 31, the

number of data values committed includes the last value written

to the FIFO. In this example, both the data value and the

PKTEND signal are clocked on the same rising edge of IFCLK.

PKTEND can also be asserted in subsequent clock cycles. The

FIFOADDR lines should be held constant during the PKTEND

assertion.

■ At t = 0 the FIFO address is stable and the signal SLCS is

asserted. (SLCS may be tied low in some applications) Note

that t_SFAhas a minimum of 25 ns. This means when IFCLK is

running at 48 MHz, the FIFO address setup time is more than

one IFCLK cycle.

■ At t = 1, the external master/peripheral must outputs the data

value onto the data bus with a minimum set up time of t_SFD

before the rising edge of IFCLK.

■ At t = 2, SLWR is asserted. The SLWR must meet the setup

time of t_SWR(time from asserting the SLWR signal to the rising

edgeofIFCLK)andmaintainaminimumholdtimeoft_WRH(time

from the IFCLK edge to the deassertion of the SLWR signal).

If the SLCS signal is used, it must be asserted with SLWR or

before SLWR is asserted (The SLCS and SLWR signals must

both be asserted to start a valid write condition).

Although there are no specific timing requirement for the

PKTEND assertion, there is a specific corner case condition that

needs attention while using the PKTEND to commit a one

byte/word packet. Additional timing requirements exists when

the FIFO is configured to operate in auto mode and it is desired

to send two packets: a full packet (full defined as the number of

bytes in the FIFO meeting the level set in AUTOINLEN register)

committed automatically followed by a short one byte or word

packet committed manually using the PKTEND pin.

■ While the SLWR is asserted, data is written to the FIFO and on

the rising edge of the IFCLK, the FIFO pointer is incremented.

The FIFO flag is also updated after a delay of t_XFLGfrom the

rising edge of the clock.

In this case, the external master must ensure to assert the

PKTEND pin at least one clock cycle after the rising edge that

caused the last byte or word that needs to be clocked into the

previous auto committed packet (the packet with the number of

bytes equal to what is set in the AUTOINLEN register). Refer to

Figure 23 for further details on this timing.

The same sequence of events are also shown for a burst write

and are marked with the time indicators of T = 0 through 5.

Note For the burst mode, SLWR and SLCS are left asserted for

the entire duration of writing all the required data values. In this

burst write mode, after the SLWR is asserted, the data on the

Document #: 38-08032 Rev. *M

Page 51 of 62

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10.17.3 Sequence Diagram of a Single and Burst Asynchronous Read

Figure 32. Slave FIFO Asynchronous Read Sequence and Timing Diagram^[20]

t

FAH

SFA

FAH

FIFOADR

t=0

t

RDpwh

t

RDpwl

t

T=0

RDpwl

RDpwh

SLRD

SLCS

t=3

t=2

T=2

T=3

T=5

T=4

T=6

t

XFLG

t

XFLG

FLAGS

DATA

SLOE

t

XFD

t

XFD

t

XFD

Data (X)

Driven

N+3

N

N+1

N+2

N

t

OEon

t

OEoff

OEon

t=4

T=1

T=7

t=1

Figure 33. Slave FIFO Asynchronous Read Sequence of Events Diagram

SLOE

SLRD

SLOE

SLRD

N+1

SLRD

N+1

SLRD

N+2

SLRD

N+2

SLOE

FIFO POINTER

N

N+1

N

N+1

N+3

N+2

N+3

FIFO DATA BUS Not Driven

Driven: X

Not Driven

N

N+1

N+2

Not Driven

Figure 32 shows the timing relationship of the SLAVE FIFO

signals during an asynchronous FIFO read. It shows a single

read followed by a burst read.

■ The data that is driven, after asserting SLRD, is the updated

data from the FIFO. This data is valid after a propagation delay

of t_XFDfrom the activating edge of SLRD. In Figure 32, data N

is the first valid data read from the FIFO. For data to appear on

the data bus during the read cycle (SLRD is asserted), SLOE

must be in an asserted state. SLRD and SLOE can also be tied

together.

■ At t = 0 the FIFO address is stable and the SLCS signal is

asserted.

■ At t = 1, SLOE is asserted. This results in the data bus being

driven. The data that is driven on to the bus is previous data,

it data that was in the FIFO from a prior read cycle.

The same sequence of events is also shown for a burst read

marked with T = 0 through 5.

■ At t = 2, SLRD is asserted. The SLRD must meet the minimum

active pulse of t_RDpwland minimum de-active pulse width of

Note In burst read mode, during SLOE is assertion, the data bus

is in a driven state and outputs the previous data. After SLRD is

asserted, the data from the FIFO is driven on the data bus (SLOE

must also be asserted) and then the FIFO pointer is incre-

mented.

t

_RDpwh. If SLCS is used then, SLCS must be asserted before

SLRD is asserted (The SLCS and SLRD signals must both be

asserted to start a valid read condition.)

Document #: 38-08032 Rev. *M

Page 52 of 62

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10.17.4 Sequence Diagram of a Single and Burst Asynchronous Write

Figure 34. Slave FIFO Asynchronous Write Sequence and Timing Diagram^[20]

t

FAH

t

SFA

FAH

FIFOADR

t=0

T=0

t

WRpwh

WRpwl

WRpwh

WRpwl

WRpwh

WRpwl

SLWR

SLCS

t =1

t=3

T=1

T=4

T=3

T=7

T=6

T=9

t

XFLG

t

XFLG

FLAGS

DATA

t

SFD

t

SFD FDH

FDH

N

N+1

N+2

N+3

t=2

T=8

T=2

T=5

t

PEpwl

PEpwh

PKTEND

Figure 34 shows the timing relationship of the SLAVE FIFO write

in an asynchronous mode. The diagram shows a single write

followed by a burst write of 3 bytes and committing the 4 byte

short packet using PKTEND.

The FIFO flag is also updated after t_XFLGfrom the deasserting

edge of SLWR.

The same sequence of events are shown for a burst write and is

indicated by the timing marks of T = 0 through 5.

■ At t = 0 the FIFO address is applied, insuring that it meets the

setup time of t_SFA. If SLCS is used, it must also be asserted

(SLCS may be tied low in some applications).

Note In the burst write mode, after SLWR is deasserted, the data

is written to the FIFO and then the FIFO pointer is incremented

to the next byte in the FIFO. The FIFO pointer is post incre-

mented.

■ At t = 1 SLWR is asserted. SLWR must meet the minimum

active pulse of t_WRpwland minimum de-active pulse width of

In Figure 34 after the four bytes are written to the FIFO and

SLWR is deasserted, the short 4 byte packet can be committed

to the host using the PKTEND. The external device should be

designed to not assert SLWR and the PKTEND signal at the

same time. It should be designed to assert the PKTEND after

SLWR is deasserted and met the minimum deasserted pulse

width. The FIFOADDR lines have to held constant during the

PKTEND assertion.

t

_WRpwh. If the SLCS is used, it must be asserted with SLWR or

before SLWR is asserted.

■ At t = 2, data must be present on the bus t_SFDbefore the

deasserting edge of SLWR.

■ At t = 3, deasserting SLWR causes the data to be written from

the data bus to the FIFO and then increments the FIFO pointer.

Document #: 38-08032 Rev. *M

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11. Ordering Information

Table 33. Ordering Information

8051 Address

/Data Busses

Ordering Code

Package Type

RAM Size

# Prog I/Os

Ideal for battery powered applications

CY7C68014A-128AXC

128 TQFP – Pb-Free

100 TQFP – Pb-Free

56 SSOP – Pb-Free

56 QFN – Pb-Free

56 VFBGA – Pb-Free

56 QFN – Pb-Free

16K

40

24

26

16/8 bit

CY7C68014A-100AXC

–

CY7C68014A-56PVXC

CY7C68014A-56LFXC

CY7C68014A-56BAXC

CY7C68016A-56LFXC

Ideal for non-battery powered applications

CY7C68013A-128AXC

CY7C68013A-128AXI

CY7C68013A-100AXC

CY7C68013A-100AXI

CY7C68013A-56PVXC

CY7C68013A-56PVXI

CY7C68013A-56LFXC

CY7C68013A-56LFXI

CY7C68015A-56LFXC

CY7C68013A-56BAXC

CY7C68013A-56LTXC

CY7C68013A-56LTXCT

CY7C68013A-56LTXI

128 TQFP – Pb-Free

128 TQFP – Pb-Free (Industrial)

100 TQFP – Pb-Free

100 TQFP – Pb-Free (Industrial)

56 SSOP – Pb-Free

56 SSOP – Pb-Free (Industrial)

56 QFN – Pb-Free

56 QFN – Pb-Free (Industrial)

56 QFN – Pb-Free

56 VFBGA – Pb-Free

56 QFN

16K

40

24

26

24

16/8 bit

–

56 QFN

CY7C68014A-56LTXC

CY7C68015A-56LTXC

CY7C68016A-56LTXC

CY7C68016A-56LTXCT

56 QFN

Development Tool Kit

CY3684

EZ-USB FX2LP Development Kit

Reference Design Kit

CY4611B

USB 2.0 to ATA/ATAPI Reference Design using EZ-USB FX2LP

Document #: 38-08032 Rev. *M

Page 54 of 62

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12. Package Diagrams

The FX2LP is available in five packages:

■ 56-pin SSOP

■ 56-pin QFN

■ 100-pin TQFP

■ 128-pin TQFP

■ 56-ball VFBGA

Package Diagrams

Figure 35. 56-Pin Shrunk Small Outline Package O56 (51-85062)

51-85062-*C

Document #: 38-08032 Rev. *M

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Package Diagrams (continued)

Figure 36. 56-Pin QFN 8 x 8 mm LF56A (51-85144)

SIDE VIEW

BOTTOM VIEW

TOP VIEW

0.08[0.003]

C

7.90[0.311]

A

1.00[0.039] MAX.

0.80[0.031] MAX.

8.10[0.319]

6.1

0.05[0.002] MAX.

0.20[0.008] REF.

0.18[0.007]

0.28[0.011]

7.70[0.303]

7.80[0.307]

PIN1 ID

0.20[0.008] R.

N

1

2

1

2

0.45[0.018]

0.80[0.031]

DIA.

SOLDERABLE

EXPOSED

PAD

6.1

0.24[0.009]

0.60[0.024]

(4X)

0°-12°

0.30[0.012]

0.50[0.020]

C

SEATING PLANE

6.45[0.254]

6.55[0.258]

51-85144-*D

NOTES:

1.

HATCH AREA IS SOLDERABLE EXPOSED METAL.

2. REFERENCE JEDEC#: MO-220

3. PACKAGE WEIGHT: 0.162g

4. ALL DIMENSIONS ARE IN MM [MIN/MAX]

5. PACKAGE CODE

PART #

DESCRIPTION

LF56

LY56

STANDARD

PB-FREE

(SUBCON PUNCH TYPE PKG with 6.1 x 6.1 EPAD)

51-85144-*G

Figure 37. 56-Pin QFN 8 x 8 mm (Sawn Version)

51-85187 *C

Document #: 38-08032 Rev. *M

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Package Diagrams (continued)

Figure 38. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A100RA (51-85050)

16.00 0.20

14.00 0.10

1.40 0.05

100

81

80

1

0.30 0.08

0.65

TYP.

12° 1°

(8X)

SEE DETAIL

A

30

51

31

50

0.20 MAX.

1.60 MAX.

R 0.08 MIN.

0.20 MAX.

0° MIN.

SEATING PLANE

STAND-OFF

0.05 MIN.

0.15 MAX.

NOTE:

1. JEDEC STD REF MS-026

0.25

GAUGE PLANE

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

R 0.08 MIN.

0.20 MAX.

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

3. DIMENSIONS IN MILLIMETERS

0°-7°

0.60 0.15

1.00 REF.

51-85050-*B

0.20 MIN.

DETAIL

A

Document #: 38-08032 Rev. *M

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Package Diagrams (continued)

Figure 39. 128-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A128 (51-85101)

16.00 0.20

14.00 0.10

1.40 0.05

128

1

0.22 0.05

12° 1°

(8X)

SEE DETAIL

A

0.50

TYP.

0.20 MAX.

1.60 MAX.

R 0.08 MIN.

0.20 MAX.

0° MIN.

SEATING PLANE

STAND-OFF

NOTE:

1. JEDEC STD REF MS-026

0.05 MIN.

0.15 MAX.

0.25

GAUGE PLANE

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

R 0.08 MIN.

0.20 MAX.

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

51-85101-*C

0°-7°

3. DIMENSIONS IN MILLIMETERS

0.60 0.15

1.00 REF.

0.20 MIN.

DETAIL

A

Document #: 38-08032 Rev. *M

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Package Diagrams (continued)

Figure 40. 56 VFBGA (5 x 5 x 1.0 mm) 0.50 Pitch, 0.30 Ball BZ56 (001-03901)

TOP VIEW

BOTTOM VIEW

Ø0.05 M C

Ø0.15 M C A B

A1 CORNER

PIN A1 CORNER

Ø0.30 0.05(56X)

1

2

3

4

5

6

8

7

6

5

4

3

2

1

A

B

C

D

E

A

B

C

D

E

F

G

H

G

H

0.50

3.50

-B-

-A-

5.00 0.10

SIDE VIEW

5.00 0.10

0.10(4X)

REFERENCE JEDEC: MO-195C

PACKAGE WEIGHT: 0.02 grams

-C-

SEATING PLANE

001-03901-*B

13. PCB Layout Recommendations

Follow these recommendations to ensure reliable high perfor-

mance operation:^[24]

■ Bypass and flyback caps on VBus, near connector, are recom-

mended.

■ Four layer impedance controlled boards are required to

maintain signal quality.

■ DPLUS and DMINUS trace lengths should be kept to within 2

mm of each other in length, with preferred length of 20 to

30 mm.

■ Specify impedance targets (ask your board vendor what they

can achieve).

■ Maintain a solid ground plane under the DPLUS and DMINUS

traces. Do not allow the plane to split under these traces.

■ To control impedance, maintain trace widths and trace spacing.

■ Minimize stubs to minimize reflected signals.

■ Do not place vias on the DPLUS or DMINUS trace routing.

■ Isolate the DPLUS and DMINUS traces from all other signal

traces by no less than 10 mm.

■ Connections between the USB connector shell and signal

ground must be near the USB connector.

Note

24. Source for recommendations: EZ-USB FX2™PCB Design Recommendations, http://www.cypress.com/cfuploads/support/app_notes/FX2_PCB.pdf and High

Speed USB Platform Design Guidelines, http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf.

Document #: 38-08032 Rev. *M

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14. Quad Flat Package No Leads (QFN) Package Design Notes

Electrical contact of the part to the Printed Circuit Board (PCB)

is made by soldering the leads on the bottom surface of the

package to the PCB. Hence, special attention is required to the

heat transfer area below the package to provide a good thermal

bond to the circuit board. Design a Copper (Cu) fill in the PCB as

a thermal pad under the package. Heat is transferred from the

FX2LP through the device’s metal paddle on the bottom side of

the package. Heat from here is conducted to the PCB at the

thermal pad. It is then conducted from the thermal pad to the

PCB inner ground plane by a 5 x 5 array of via. A via is a plated

through hole in the PCB with a finished diameter of 13 mil. The

QFN’s metal die paddle must be soldered to the PCB’s thermal

pad. Solder mask is placed on the board top side over each via

to resist solder flow into the via. The mask on the top side also

minimizes outgassing during the solder reflow process.

For further information on this package design refer to Appli-

cation Notes for Surface Mount Assembly of Amkor's MicroLead-

Frame (MLF) Packages. You can find this on Amkor's website

http://www.amkor.com.

The application note provides detailed information about board

mounting guidelines, soldering flow, rework process, etc.

Figure 41 shows

a cross-sectional area underneath the

package. The cross section is of only one via. The solder paste

template should be designed to allow at least 50% solder

coverage. The thickness of the solder paste template should be

5 mil. Use the No Clean type 3 solder paste for mounting the part.

Nitrogen purge is recommended during reflow.

Figure 42 is a plot of the solder mask pattern and Figure 43

displays an X-Ray image of the assembly (darker areas indicate

solder).

Figure 41. Cross-section of the Area Underneath the QFN Package

0.017” dia

Solder Mask

Cu Fill

0.013” dia

PCB Material

Via hole for thermally connecting the

This figure only shows the top three layers of the

circuit board: Top Solder, PCB Dielectric, and

the Ground Plane

QFN to the circuit board ground plane.

Figure 42. Plot of the Solder Mask (White Area)

Figure 43. X-ray Image of the Assembly

Document #: 38-08032 Rev. *M

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Document History Page

Document Title: CY7C68013A, CY7C68014A, CY7C68015A, CY7C68016A, EZ-USB FX2LP™ USB Microcontroller High

Speed USB Peripheral Controller

Document Number: 38-08032

Submission Orig. of

REV. ECN NO.

Description of Change

Date

Change

** 124316

03/17/03

09/02/03

VCS New data sheet

*A 128461

VCS Added PN CY7C68015A throughout data sheet

Modified Figure 1 to add ECC block and fix errors

Removed word “compatible” where associated with I²C

Corrected grammar and formatting in various locations

Updated Sections 3.2.1, 3.9, 3.11, Table 9, Section 5.0

Added Sections 3.15, 3.18.4, 3.20

Modified Figure 5 for clarity

Updated Figure 36 to match current spec revision

*B 130335

*C 131673

10/09/03

02/12/04

KKV Restored PRELIMINARY to header (had been removed in error from rev. *A)

KKU Section 8.1 changed “certified” to “compliant”

Table 14 added parameter V_{IH_X}and V_{IL_X}

Added Sequence diagrams Section 9.16

Updated Ordering information with lead-free parts

Updated Registry Summary

Section 3.12.4:example changed to column 8 from column 9

Updated Figure 14 memory write timing Diagram

Updated section 3.9 (reset)

Updated section 3.15 ECC Generation

*D 230713

*E 242398

See ECN

KKU Changed Lead free Marketing part numbers in Table 33 as per spec change in 28-00054.

TMD Minor Change: data sheet posted to the web,

*F

271169

MON Added USB-IF Test ID number

Added USB 2.0 logo

Added values for Isusp, Icc, Power Dissipation, Vih_x, Vil_x

Changed VCC from + 10% to + 5%

Changed E-Pad size to 4.3 mm x 5.0 mm

Changed PKTEND to FLAGS output propagation delay (asynchronous interface) in

Table 28 from a max value of 70 ns to 115 ns

*G

*H

316313

338901

See ECN

MON Removed CY7C68013A-56PVXCT part availability

Added parts ideal for battery powered applications: CY7C68014A, CY7C68016A

Provided additional timing restrictions and requirement about the use of PKETEND pin to

commit a short one byte/word packet subsequent to committing a packet automatically

(when in auto mode).

Added Min Vcc Ramp Up time (0 to 3.3v)

MON Added information about the AUTOPTR1/AUTOPTR2 address timing with regards to data

memory read/write timing diagram.

Removed TBD for Min value of Clock to FIFO Data Output Propagation Delay (t_XFD) for

Slave FIFO Synchronous Read

Changed Table 33 to include part CY7C68016A-56LFXC in the part listed for battery

powered applications

Added register GPCR2 in register summary

*I

371097

397239

See ECN

MON Added timing for strobing RD#/WR# signals when using PortC strobe feature (Section 10.5)

*J

MON Removed XTALINSRC register from register summary.

Changed Vcc margins to +10%

Added 56-pin VFBGA Pin Package Diagram

Added 56-pin VFBGA definition in pin listing

Added RDK part number to the Ordering Information table

Document #: 38-08032 Rev. *M

Page 61 of 62

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Document Title: CY7C68013A, CY7C68014A, CY7C68015A, CY7C68016A, EZ-USB FX2LP™ USB Microcontroller High

Speed USB Peripheral Controller

Document Number: 38-08032

Submission Orig. of

REV. ECN NO.

Description of Change

Date

Change

*K 420505

See ECN

MON Remove SLCS from figure in Section 10.10.

Removed indications that SLRD can be asserted simultaneously with SLCS in Section

10.17.2 and Section 10.17.3

Added Absolute Maximum Temperature Rating for industrial packages in Section 6.

Changed number of packages stated in the description in Section 4. to five.

Added Table 13 on Thermal Coefficients for various packages

*L 2064406 See ECN

*M 2710327 05/22/2009

CMCC/ Changed TID number

PYRS Removed T0OUT and T1OUT from CY7C68015A/16A

Updated t_SWRMin value in Figure 20

Updated 56-lead QFN package diagram

DPT Added 56-Pin QFN (8 X 8 mm) package diagram

Updated ordering information for CY7C68013A-56LTXC, CY7C68013A-56LTXI,

CY7C68014A-56LTXC, CY7C68015A-56LTXC, and CY7C68016A-56LTXC parts.

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medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

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Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document #: 38-08032 Rev. *M

Revised May 22, 2009

Page 62 of 62

Purchase of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided

that the system conforms to the I2C Standard Specification as defined by Philips. EZ-USB FX2LP and EZ-USB FX2 are trademarks, and EZ-USB is a registered trademark, of Cypress Semiconductor

Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.

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型号：	CY7C68013A_0905
厂家：	CYPRESS
描述：	EZ-USB FX2LP? USB Microcontroller High Speed USB Peripheral Controller EZ- USB FX2LP ™ USB微控制器，高速USB外设控制器微控制器
文件：	总62页 (文件大小：1809K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY7C68013A_0905 [CYPRESS]

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