CY7C64013C_11 [CYPRESS]
Full-Speed USB (12-Mbps) Function; 全速USB （ 12 Mbps）的功能
| 型号： | CY7C64013C_11 |
| 厂家： | 
CYPRESS |
| 描述： | Full-Speed USB (12-Mbps) Function |
| 文件： | 总53页 (文件大小：1270K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C64013C
CY7C64113C
Full-Speed USB (12-Mbps) Function
Full-Speed USB (12-Mbps) Function
Features
Functional Overview
■ Full-speed USB Microcontroller
The CY7C64013C and CY7C64113C are 8-bit One Time
Programmable microcontrollers that are designed for full-speed
USB applications. The instruction set has been optimized
specifically for USB operations, although the microcontrollers
can be used for a variety of non-USB embedded applications.
■ 8-bit USB Optimized Microcontroller
❐ Harvard architecture
❐ 6-MHz external clock source
❐ 12-MHz internal CPU clock
❐ 48-MHz internal clock
GPIO
The CY7C64013C features 19 GPIO pins to support USB and
other applications. The I/O pins are grouped into three ports
(P0[7:0], P1[2:0], P2[6:2], P3[2:0]) where each port can be
configured as inputs with internal pull-ups, open drain outputs, or
traditional CMOS outputs. There are 16 GPIO pins (Ports 0 and
■ Internal memory
❐ 256 bytes of RAM
❐ 8 KB of PROM (CY7C64013C, CY7C64113C)
■ Integrated Master/Slave I2C-compatible Controller (100 kHz)
1) which are rated at 7 mA typical sink current. Port 3 pins are
rated at 12 mA typical sink current, a current sufficient to drive
LEDs. Multiple GPIO pins can be connected together to drive a
single output for more drive current capacity. Additionally, each
GPIO can be used to generate a GPIO interrupt to the
microcontroller. All of the GPIO interrupts share the same “GPIO”
interrupt vector.
enabled through General-Purpose I/O (GPIO) pins
■ Hardware Assisted Parallel Interface (HAPI) for data transfer
to external devices
■ I/O ports
❐ Three GPIO ports (Port 0 to 2) capable of sinking 7 mA per
pin (typical)
The CY7C64113C has 32 GPIO pins (P0[7:0], P1[7:0], P2[7:0],
P3[7:0]).
❐ An additional GPIO port (Port 3) capable of sinking 12 mA
per pin (typical) for high current requirements: LEDs
❐ Higher current drive achievable by connecting multiple GPIO
pins together to drive a common output
DAC
❐ Each GPIO port can be configured as inputs with internal
The CY7C64113C has four programmable sink current I/O pins
(DAC) pins (P4[7,2:0]). Every DAC pin includes an integrated
14-k pull-up resistor. When a ‘1’ is written to a DAC I/O pin, the
output current sink is disabled and the output pin is driven HIGH
by the internal pull-up resistor. When a ‘0’ is written to a DAC I/O
pin, the internal pull-up resistor is disabled and the output pin
provides the programmed amount of sink current. A DAC I/O pin
can be used as an input with an internal pull-up by writing a ‘1’
to the pin.
pull-ups or open drain outputs or traditional CMOS outputs
❐ A Digital to Analog Conversion (DAC) port with
programmable current sink outputs is available on the
CY7C64113C devices
❐ Maskable interrupts on all I/O pins
■ 12-bit free-running timer with one microsecond clock ticks
■ Watchdog Timer (WDT)
■ Internal Power-On Reset (POR)
The sink current for each DAC I/O pin can be individually
programmed to one of 16 values using dedicated Isink registers.
DAC bits P4[1:0] can be used as high-current outputs with a
programmable sink current range of 3.2 to 16 mA (typical). DAC
bits P4[7,2] have a programmable current sink range of 0.2 to
1.0 mA (typical). Multiple DAC pins can be connected together
to drive a single output that requires more sink current capacity.
Each I/O pin can be used to generate a DAC interrupt to the
microcontroller. Also, the interrupt polarity for each DAC I/O pin
is individually programmable.
■ USB Specification Compliance
❐ Conforms to USB Specification, Version 1.1
❐ Conforms to USB HID Specification, Version 1.1
❐ Supports up to five user configured endpoints
• Up to four 8-byte data endpoints
• Up to two 32-byte data endpoints
❐ Integrated USB transceivers
■ Improved output drivers to reduce EMI
Clock
■ Operating voltage from 4.0 V to 5.5 V DC
■ Operating temperature from 0 to 70 degrees Celsius
The microcontroller uses an external 6-MHz crystal and an
internal oscillator to provide a reference to an internal PLL-based
clock generator. This technology allows the customer application
to use an inexpensive 6-MHz fundamental crystal that reduces
the clock-related noise emissions (EMI). A PLL clock generator
provides the 6-, 12-, and 48-MHz clock signals for distribution
within the microcontroller.
❐ CY7C64013C available in 28-pin SOIC and 28-pin PDIP
packages
❐ CY7C64113C available in 48-pin SSOP packages
■ Industry-standard programmer support
Cypress Semiconductor Corporation
Document Number: 38-08001 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 8, 2011
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CY7C64013C
CY7C64113C
duration of the event in microseconds. The upper four bits of the
timer are latched into an internal register when the firmware
reads the lower eight bits. A read from the upper four bits actually
reads data from the internal register, instead of the timer. This
feature eliminates the need for firmware to try to compensate if
the upper four bits increment immediately after the lower eight
bits are read.
Memory
The CY7C64013C and CY7C64113C have 8 KB of PROM.
Power on Reset, Watchdog and Free running Time
These parts include power-on reset logic, a Watchdog timer, and
a 12-bit free-running timer. The power-on reset (POR) logic
detects when power is applied to the device, resets the logic to
a known state, and begins executing instructions at PROM
address 0x0000. The Watchdog timer is used to ensure the
microcontroller recovers after a period of inactivity. The firmware
may become inactive for a variety of reasons, including errors in
the code or a hardware failure such as waiting for an interrupt
that never occurs.
Interrupts
The microcontroller supports 11 maskable interrupts in the
vectored interrupt controller. Interrupt sources include the USB
Bus Reset interrupt, the 128-µs (bit 6) and 1.024-ms (bit 9)
outputs from the free-running timer, five USB endpoints, the DAC
port, the GPIO ports, and the I2C-compatible master mode
interface. The timer bits cause an interrupt (if enabled) when the
bit toggles from LOW ‘0’ to HIGH ‘1.’ The USB endpoints interrupt
after the USB host has written data to the endpoint FIFO or after
the USB controller sends a packet to the USB host. The DAC
ports have an additional level of masking that allows the user to
select which DAC inputs can cause a DAC interrupt. The GPIO
ports also have a level of masking to select which GPIO inputs
can cause a GPIO interrupt. For additional flexibility, the input
transition polarity that causes an interrupt is programmable for
each pin of the DAC port. Input transition polarity can be
programmed for each GPIO port as part of the port configuration.
The interrupt polarity can be rising edge (‘0’ to ‘1’) or falling edge
(‘1’ to ‘0’).
2
I C and HAPI Interface
The microcontroller can communicate with external electronics
through the GPIO pins. An I2C-compatible interface
accommodates a 100-kHz serial link with an external device.
There is also a Hardware Assisted Parallel Interface (HAPI)
which can be used to transfer data to an external device.
Timer
The free-running 12-bit timer clocked at 1 MHz provides two
interrupt sources, 128-µs and 1.024-ms. The timer can be used
to measure the duration of an event under firmware control by
reading the timer at the start of the event and after the event is
complete. The difference between the two readings indicates the
Document Number: 38-08001 Rev. *D
Page 2 of 53
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CY7C64013C
CY7C64113C
Logic Block Diagram
6-MHz crystal
PLL
48 MHz
Clock
12-MHz
8-bit
CPU
Divider
USB
Transceiver
D+[0]
D–[0]
USB
SIE
Upstream
USB Port
12 MHz
Interrupt
Controller
PROM
8 KB
RAM
256 byte
GPIO
PORT 0
P0[7:0]
P1[2:0]
P1[7:3]
6 MHz
GPIO
PORT 1
12-bit
Timer
CY7C64113C only
P2[0,1,7]
GPIO/
HAPI
Watchdog
Timer
P2[2]; Latch_Empty
P2[3]; Data_Ready
P2[4]; STB
PORT 2
P2[5]; OE
P2[6]; CS
Power-On
Reset
High Current
P3[2:0]
Outputs
GPIO
Additional
High Current
Outputs
PORT 3
P3[7:3]
DAC[0]
DAC
PORT
DAC[2]
DAC[7]
CY7C64113C only
I2C
Interface
SCLK
SDATA
2
*I C-compatible interface enabled by firmware through
P2[1:0] or P1[1:0]
Document Number: 38-08001 Rev. *D
Page 3 of 53
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CY7C64013C
CY7C64113C
Contents
Pin Configurations ...........................................................5
Product Summary Tables ................................................6
Pin Assignments .........................................................6
I/O Register Summary .................................................6
Instruction Set Summary .............................................9
Programming Model .......................................................10
14-Bit Program Counter (PC) ....................................10
8-Bit Accumulator (A) ................................................12
8-Bit Temporary Register (X) ....................................12
8-Bit Program Stack Pointer (PSP) ...........................12
8-Bit Data Stack Pointer (DSP) .................................13
Address Modes .........................................................13
Clocking ..........................................................................13
Reset ................................................................................14
Power-On Reset (POR) .............................................14
Watchdog Reset (WDR) ............................................14
Suspend Mode ................................................................14
General-Purpose I/O (GPIO) Ports ................................15
GPIO Configuration Port ...........................................16
GPIO Interrupt Enable Ports .....................................17
DAC Port ..........................................................................18
DAC Isink Registers ..................................................19
DAC Port Interrupts ...................................................20
12-Bit Free-Running Timer ............................................20
I2C and HAPI Configuration Register ...........................21
I2C-compatible Controller ..............................................22
Hardware Assisted Parallel Interface (HAPI) ...............24
Processor Status and Control Register .......................25
Interrupts .........................................................................26
Interrupt Vectors ........................................................27
Interrupt Latency .......................................................29
USB Bus Reset Interrupt ...........................................29
Timer Interrupt ...........................................................29
USB Endpoint Interrupts ............................................29
DAC Interrupt ............................................................29
GPIO/HAPI Interrupt ..................................................29
I2C Interrupt ...............................................................30
USB Overview .................................................................30
USB Serial Interface Engine (SIE) ............................31
USB Enumeration ......................................................31
USB Upstream Port Status and Control ....................31
USB Serial Interface Engine Operation ........................32
USB Device Address .................................................32
USB Device Endpoints ..............................................32
USB Control Endpoint Mode Register .......................32
USB Non-Control Endpoint Mode Registers .............33
USB Endpoint Counter Registers ..............................34
Endpoint Mode/Count Registers Update and
Locking Mechanism ..........................................................34
USB Mode Tables ...........................................................36
Register Summary ..........................................................41
Sample Schematic ..........................................................44
Absolute Maximum Ratings ..........................................45
Electrical Characteristics ...............................................45
Switching Characteristics ..............................................46
Ordering Information ......................................................48
Ordering Code Definitions .........................................48
Package Diagrams ..........................................................49
Acronyms ........................................................................51
Document Conventions .................................................51
Units of Measure .......................................................51
Document History Page .................................................52
Sales, Solutions, and Legal Information ......................53
Worldwide Sales and Design Support .......................53
Products ....................................................................53
PSoC Solutions .........................................................53
Document Number: 38-08001 Rev. *D
Page 4 of 53
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CY7C64013C
CY7C64113C
Pin Configurations
TOP VIEW
CY7C64013C
28-pin SOIC
CY7C64013C
28-pin PDIP
CY7C64113C
48-pin SSOP
XTALOUT
XTALIN
1
2
3
4
28
27
26
XTALOUT
XTALIN
1
2
3
4
48
47
46
V
V
XTALOUT
XTALIN
1
2
3
4
28
27
26
V
CC
CC
CC
P1[1]
P1[0]
P1[2]
P3[0]
P3[2]
GND
P2[2]
P1[1]
P1[0]
P1[2]
P1[4]
P1[6]
P3[0]
P3[2]
P1[0]
P1[2]
P3[0]
P3[2]
P2[2]
GND
P2[4]
V
V
V
REF
REF
REF
GND
P3[1]
D+[0]
D–[0]
P2[3]
P2[5]
P0[7]
P0[5]
P0[3]
P0[1]
P0[6]
25
24
23
22
21
20
19
18
17
16
15
P1[3]
P1[5]
P1[7]
P3[1]
D+[0]
D–[0]
P3[3]
GND
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
P1[1]
GND
P3[1]
D+[0]
D–[0]
P2[3]
P2[5]
P0[7]
P0[5]
P0[3]
P0[1]
25
24
23
22
21
20
19
18
17
16
15
5
5
5
6
6
6
7
7
7
8
8
8
9
P2[4]
P2[6]
9
GND
P3[4]
NC
9
P2[6]
10
11
12
13
14
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
10
11
12
13
14
V
PP
V
P0[0]
P0[2]
P0[4]
P0[6]
PP
P0[0]
P0[2]
P0[4]
P3[5]
P3[7]
P2[1]
P2[3]
GND
P3[6]
P2[0]
P2[2]
GND
P2[4]
P2[6]
DAC[0]
P2[5]
P2[7]
DAC[7]
P0[7]
P0[5]
P0[3]
P0[1]
DAC[1]
V
PP
P0[0]
P0[2]
P0[4]
P0[6]
DAC[2]
Document Number: 38-08001 Rev. *D
Page 5 of 53
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CY7C64113C
Product Summary Tables
Pin Assignments
Table 1. Pin Assignments
Name
D+[0], D–[0]
P0
I/O
I/O
I/O
28-pin SOIC
6, 7
28-pin PDIP
7, 8
48-pin SSOP
7, 8
Description
Upstream port, USB differential data.
P0[7:0]
P0[7:0]
P0[7:0]
GPIO Port 0 capable of sinking 7 mA (typical).
GPIO Port 1 capable of sinking 7 mA (typical).
GPIO Port 2 capable of sinking 7 mA (typical). HAPI
10, 14, 11, 15, 11, 15, 12, 16, 20, 26, 21, 27,
12, 16, 13, 17 13, 17, 14, 18 22, 28, 23, 29
P1
I/O
I/O
I/O
I/O
P1[2:0]
25, 27, 26
P1[2:0]
26, 4, 27
P1[7:0]
6, 43, 5, 44,
4, 45, 47, 46
P2
P2[6:2]
19, 9, 20, 8,
21
P2[6:2]
20, 10, 21,
9, 23
P2[7:0]
18, 32, 17, 33, is also supported through P2[6:2].
15, 35, 14, 36
P3
P3[2:0]
23, 5, 24
P3[2:0]
24, 6, 25
P3[7:0]
13, 37, 12, 39,
10, 41, 7, 42
GPIO Port 3, capable of sinking 12 mA (typical).
DAC
DAC[7,2:0]
DAC Port with programmable current sink outputs.
19, 25, 24, 31 DAC[1:0] offer a programmable range of 3.2 to 16 mA
typical. DAC[7,2] have a programmable sink current
range of 0.2 to 1.0 mA typical.
XTALIN
XTALOUT
VPP
IN
OUT
IN
2
1
2
1
2
1
6-MHz crystal or external clock input.
6-MHz crystal out.
18
19
30
Programming voltage supply, tie to ground during
normal operation.
VCC
IN
IN
IN
28
4, 22
3
28
5, 22
3
48
Voltage supply.
GND
VREF
11, 16, 34, 40 Ground.
3
External 3.3 V supply voltage for the differential data
output buffers and the D+ pull-up.
NC
38
No Connect.
the specified port. Specifying address 0 (e.g., IOWX 0h) means
the I/O register is selected solely by the contents of X.
I/O Register Summary
I/O registers are accessed via the I/O Read (IORD) and I/O Write
(IOWR, IOWX) instructions. IORD reads data from the selected
port into the accumulator. IOWR performs the reverse; it writes
data from the accumulator to the selected port. Indexed I/O Write
(IOWX) adds the contents of X to the address in the instruction
to form the port address and writes data from the accumulator to
All undefined registers are reserved. It is important not to write
to reserved registers as this may cause an undefined operation
or increased current consumption during operation. When
writing to registers with reserved bits, the reserved bits must be
written with ‘0.’
Document Number: 38-08001 Rev. *D
Page 6 of 53
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CY7C64113C
Table 2. I/O Register Summary
Register Name
Port 0 Data
I/O Address Read/Write
Function
Page
15
16
16
16
17
17
18
18
16
21
32
32
32
32
32
32
32
31
26
27
20
21
14
22
22
19
20
20
19
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x1F
0x20
0x21
0x24
0x25
0x26
0x28
0x29
0x30
0x31
0x32
0x38-0x3F
0x40
0x41
0x42
0x43
0x44
0x48
0x49
0x4A
0x4B
0x4C
R/W
R/W
R/W
R/W
W
GPIO Port 0 Data
GPIO Port 1 Data
GPIO Port 2 Data
GPIO Port 3 Data
Port 1 Data
Port 2 Data
Port 3 Data
Port 0 Interrupt Enable
Port 1 Interrupt Enable
Port 2 Interrupt Enable
Port 3 Interrupt Enable
GPIO Configuration
HAPI and I2C Configuration
USB Device Address A
EP A0 Counter Register
EP A0 Mode Register
EP A1 Counter Register
EP A1 Mode Register
EP A2 Counter Register
EP A2 Mode Register
USB Status & Control
Global Interrupt Enable
Endpoint Interrupt Enable
Timer (LSB)
Interrupt Enable for Pins in Port 0
Interrupt Enable for Pins in Port 1
Interrupt Enable for Pins in Port 2
Interrupt Enable for Pins in Port 3
GPIO Port Configurations
W
W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
HAPI Width and I2C Position Configuration
USB Device Address A
USB Address A, Endpoint 0 Counter
USB Address A, Endpoint 0 Configuration
USB Address A, Endpoint 1 Counter
USB Address A, Endpoint 1 Configuration
USB Address A, Endpoint 2 Counter
USB Address A, Endpoint 2 Configuration
USB Upstream Port Traffic Status and Control
Global Interrupt Enable
USB Endpoint Interrupt Enables
Lower 8 Bits of Free-running Timer (1 MHz)
Upper 4 Bits of Free-running Timer
Watchdog Timer Clear
Timer (MSB)
R
WDT Clear
W
I2C Control & Status
I2C Data
R/W
R/W
R/W
W
I2C Status and Control
I2C Data
DAC Data
DAC Data
DAC Interrupt Enable
DAC Interrupt Polarity
DAC Isink
Interrupt Enable for each DAC Pin
Interrupt Polarity for each DAC Pin
Input Sink Current Control for each DAC Pin
Reserved
W
W
Reserved
EP A3 Counter Register
EP A3 Mode Register
EP A4 Counter Register
EP A4 Mode Register
Reserved
R/W
R/W
R/W
R/W
USB Address A, Endpoint 3 Counter
USB Address A, Endpoint 3 Configuration
USB Address A, Endpoint 4 Counter
USB Address A, Endpoint 4 Configuration
Reserved
32
32
32
32
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Document Number: 38-08001 Rev. *D
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CY7C64113C
Table 2. I/O Register Summary (continued)
Register Name I/O Address Read/Write
Reserved
Function
Page
0x4D
0x4E
0x4F
0x50
0x51
0xFF
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Processor Status & Control
R/W
Microprocessor Status and Control Register
23
Document Number: 38-08001 Rev. *D
Page 8 of 53
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CY7C64113C
Instruction Set Summary
Refer to the CYASM Assembler User’s Guide for more details.
Table 3. Instruction Set Summary
MNEMONIC
HALT
operand opcode cycles
MNEMONIC
NOP
operand opcode cycles
20
21
00
01
7
4
6
7
4
6
7
4
6
7
4
6
7
4
6
7
4
6
7
4
6
7
5
7
8
4
5
6
4
5
4
ADD A,expr
ADD A,[expr]
ADD A,[X+expr]
ADC A,expr
ADC A,[expr]
ADC A,[X+expr]
SUB A,expr
SUB A,[expr]
SUB A,[X+expr]
SBB A,expr
SBB A,[expr]
SBB A,[X+expr]
OR A,expr
data
INC A
acc
4
direct
index
data
02
INC X
x
22
23
4
7
8
4
4
7
8
5
5
4
4
5
5
5
5
5
6
7
8
7
8
7
8
6
4
4
4
4
4
8
4
4
8
5
5
7
14
03
INC [expr]
INC [X+expr]
DEC A
direct
index
acc
04
24
direct
index
data
05
25
06
DEC X
x
26
07
DEC [expr]
DEC [X+expr]
IORD expr
IOWR expr
POP A
direct
index
address
address
27
direct
index
data
08
28
09
29
0A
2A
direct
index
data
0B
2B
0C
0D
0E
POP X
2C
2D
2E
PUSH A
PUSH X
SWAP A,X
SWAP A,DSP
MOV [expr],A
MOV [X+expr],A
OR [expr],A
OR [X+expr],A
AND [expr],A
AND [X+expr],A
XOR [expr],A
XOR [X+expr],A
IOWX [X+expr]
CPL
OR A,[expr]
OR A,[X+expr]
AND A,expr
AND A,[expr]
AND A,[X+expr]
XOR A,expr
XOR A,[expr]
XOR A,[X+expr]
CMP A,expr
CMP A,[expr]
CMP A,[X+expr]
MOV A,expr
MOV A,[expr]
MOV A,[X+expr]
MOV X,expr
MOV X,[expr]
reserved
direct
index
data
0F
2F
10
30
direct
index
data
11
direct
index
direct
index
direct
index
direct
index
index
31
12
32
13
33
direct
index
data
14
34
15
35
16
36
direct
index
data
17
37
18
38
19
39
direct
index
data
1A
3A
1B
ASL
3B
1C
1D
1E
ASR
3C
3D
3E
direct
RLC
RRC
XPAGE
1F
4
4
RET
3F
MOV A,X
40
DI
70
MOV X,A
41
4
EI
72
MOV PSP,A
CALL
60
4
RETI
73
addr
addr
addr
addr
addr
50 - 5F
80-8F
90-9F
A0-AF
B0-BF
10
5
JC
addr
addr
addr
addr
C0-CF
D0-DF
E0-EF
F0-FF
JMP
JNC
CALL
10
5
JACC
JZ
INDEX
JNZ
5
Document Number: 38-08001 Rev. *D
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CY7C64013C
CY7C64113C
instruction. The assembler directive “XPAGEON” causes the
assembler to insert XPAGE instructions automatically. Because
instructions can be either one or two bytes long, the assembler
may occasionally need to insert a NOP followed by an XPAGE
to execute correctly.
Programming Model
14-Bit Program Counter (PC)
The 14-bit program counter (PC) allows access to up to 8 KB of
PROM available with the CY7C64x13C architecture. The top
32 bytes of the ROM in the 8 Kb part are reserved for testing
purposes. The program counter is cleared during reset, such that
the first instruction executed after a reset is at address 0x0000h.
Typically, this is a jump instruction to a reset handler that
initializes the application (see Interrupt Vectors on page 27).
The address of the next instruction to be executed, the carry flag,
and the zero flag are saved as two bytes on the program stack
during an interrupt acknowledge or a CALL instruction. The
program counter, carry flag, and zero flag are restored from the
program stack during a RETI instruction. Only the program
counter is restored during a RET instruction.
The lower eight bits of the program counter are incremented as
instructions are loaded and executed. The upper six bits of the
program counter are incremented by executing an XPAGE
instruction. As a result, the last instruction executed within a
256-byte “page” of sequential code should be an XPAGE
The program counter cannot be accessed directly by the
firmware. The program stack can be examined by reading SRAM
from location 0x00 and up.
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Program Memory Organization
after reset
14-bit PC
Address
0x0000
Program execution begins here after a reset
USB Bus Reset interrupt vector
128-µs timer interrupt vector
0x0002
0x0004
0x0006
0x0008
0x000A
0x000C
0x000E
0x0010
0x0012
0x0014
0x0016
0x0018
0x001A
1.024-ms timer interrupt vector
USB address A endpoint 0 interrupt vector
USB address A endpoint 1 interrupt vector
USB address A endpoint 2 interrupt vector
USB address A endpoint 3 interrupt vector
USB address A endpoint 4 interrupt vector
Reserved
DAC interrupt vector
GPIO interrupt vector
I2C interrupt vector
Program Memory begins here
0x1FDF
8 KB (-32) PROM ends here (CY7C64013C, CY7C64113C)
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counter and flags on the program “stack” and increment the PSP
by two.
8-Bit Accumulator (A)
The accumulator is the general-purpose register for the
microcontroller.
The Return from Interrupt (RETI) instruction decrements the
PSP, then restores the second byte from memory addressed by
the PSP. The PSP is decremented again and the first byte is
restored from memory addressed by the PSP. After the program
counter and flags have been restored from stack, the interrupts
are enabled. The overall effect is to restore the program counter
and flags from the program stack, decrement the PSP by two,
and reenable interrupts.
8-Bit Temporary Register (X)
The “X” register is available to the firmware for temporary storage
of intermediate results. The microcontroller can perform indexed
operations based on the value in X. Refer to Indexed on page 13
for additional information.
8-Bit Program Stack Pointer (PSP)
The Call Subroutine (CALL) instruction stores the program
counter and flags on the program stack and increments the PSP
by two.
During a reset, the program stack pointer (PSP) is set to 0x00
and “grows” upward from this address. The PSP may be set by
firmware, using the MOV PSP,A instruction. The PSP supports
interrupt service under hardware control and CALL, RET, and
RETI instructions under firmware control. The PSP is not
readable by the firmware.
The Return from Subroutine (RET) instruction restores the
program counter but not the flags from the program stack and
decrements the PSP by two.
Data Memory Organization
During an interrupt acknowledge, interrupts are disabled and the
14-bit program counter, carry flag, and zero flag are written as
two bytes of data memory. The first byte is stored in the memory
addressed by the PSP, then the PSP is incremented. The second
byte is stored in memory addressed by the PSP, and the PSP is
incremented again. The overall effect is to store the program
The CY7C64x13C microcontrollers provide 256 bytes of data
RAM. Normally, the SRAM is partitioned into four areas: program
stack, user variables, data stack, and USB endpoint FIFOs. The
following is one example of where the program stack, data stack,
and user variables areas could be located.
After reset
8-bit DSP 8-bit PSP
Address
0x00
Program Stack Growth
(Move DSP[1]
)
user selected
Data Stack Growth
8-bit DSP
User variables
USB FIFO space for five endpoints[2]
0xFF
Notes
1. Refer to 8-Bit Data Stack Pointer (DSP) on page 13 for a description of DSP.
2. Endpoint sizes are fixed by the Endpoint Size Bit (I/O register 0x1F, Bit 7), see Table 34 on page 32.
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“0xD8.” A constant may be referred to by name if a prior “EQU”
statement assigns the constant value to the name. For example,
the following code is equivalent to the example shown above:
8-Bit Data Stack Pointer (DSP)
The data stack pointer (DSP) supports PUSH and POP
instructions that use the data stack for temporary storage. A
PUSH instruction pre-decrements the DSP, then writes data to
the memory location addressed by the DSP. A POP instruction
reads data from the memory location addressed by the DSP,
then post-increments the DSP.
■ DSPINIT: EQU 0D8h
■ MOV A,DSPINIT
Direct
During a reset, the DSP is reset to 0x00. A PUSH instruction
when DSP equals 0x00 writes data at the top of the data RAM
(address 0xFF). This writes data to the memory area reserved
for USB endpoint FIFOs. Therefore, the DSP should be indexed
at an appropriate memory location that does not compromise the
Program Stack, user-defined memory (variables), or the USB
endpoint FIFOs.
“Direct” address mode is used when the data operand is a
variable stored in SRAM. In that case, the one byte address of
the variable is encoded in the instruction. As an example,
consider an instruction that loads A with the contents of memory
address location 0x10:
■ MOV A,[10h]
For USB applications, the firmware should set the DSP to an
appropriate location to avoid a memory conflict with RAM
dedicated to USB FIFOs. The memory requirements for the USB
endpoints are described in USB Device Endpoints on page 32.
Example assembly instructions to do this with two device
addresses (FIFOs begin at 0xD8) are shown below:
Normally, variable names are assigned to variable addresses
using “EQU” statements to improve the readability of the
assembler source code. As an example, the following code is
equivalent to the example shown above:
■ buttons: EQU 10h
■ MOV A,[buttons]
MOV A,20h
or less)
; Move 20 hex into Accumulator (must be D8h
Indexed
SWAP A,DSP ; swap accumulator value into DSP register
“Indexed” address mode allows the firmware to manipulate
arrays of data stored in SRAM. The address of the data operand
is the sum of a constant encoded in the instruction and the
contents of the “X” register. Normally, the constant is the “base”
address of an array of data and the X register contains an index
that indicates which element of the array is actually addressed:
Address Modes
The CY7C64013C and CY7C64113C microcontrollers support
three addressing modes for instructions that require data
operands: data, direct, and indexed.
Data (Immediate)
■ array: EQU 10h
■ MOV X,3
“Data” address mode refers to a data operand that is actually a
constant encoded in the instruction. As an example, consider the
instruction that loads A with the constant 0xD8:
■ MOV A,[X+array]
This would have the effect of loading A with the fourth element
of the SRAM “array” that begins at address 0x10. The fourth
element would be at address 0x13.
■ MOV A,0D8h
This instruction requires two bytes of code where the first byte
identifies the “MOV A” instruction with a data operand as the
second byte. The second byte of the instruction is the constant
Clocking
Figure 1. Clock Oscillator On-Chip Circuit
XTALOUT
(pin 1)
XTALIN
(pin 2)
To Internal PLL
30 pF
30 pF
The XTALIN and XTALOUT are the clock pins to the
microcontroller. The user can connect an external oscillator or a
crystal to these pins. When using an external crystal, keep PCB
traces between the chip leads and crystal as short as possible
(less than 2 cm). A 6-MHz fundamental frequency parallel
resonant crystal can be connected to these pins to provide a
reference frequency for the internal PLL. The two internal 30-pF
load caps appear in series to the external crystal and would be
equivalent to a 15-pF load. Therefore, the crystal must have a
required load capacitance of about 15–18 pF. A ceramic
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resonator does not allow the microcontroller to meet the timing
specifications of full speed USB and therefore a ceramic
resonator is not recommended with these parts.
“semi-suspend” state. During the semi-suspend state, which is
different from the suspend state defined in the USB specification,
the oscillator and all other blocks of the part are functional,
except for the CPU. This semi-suspend time ensures that both a
valid VCC level is reached and that the internal PLL has time to
stabilize before full operation begins. When the VCC has risen
above approximately 2.5 V, and the oscillator is stable, the POR
is deasserted and the on-chip timer starts counting. The first
1 ms of suspend time is not interruptible, and the semi-suspend
state continues for an additional 95 ms unless the count is
bypassed by a USB Bus Reset on the upstream port. The 95 ms
provides time for VCC to stabilize at a valid operating voltage
before the chip executes code.
An external 6-MHz clock can be applied to the XTALIN pin if the
XTALOUT pin is left open. Grounding the XTALOUT pin when
driving XTALIN with an oscillator does not work because the
internal clock is effectively shorted to ground.
Reset
The CY7C64x13C supports two resets: Power-On Reset (POR)
and a Watchdog Reset (WDR). Each of these resets causes:
■ all registers to be restored to their default states,
■ the USB Device Address to be set to 0,
■ all interrupts to be disabled,
If a USB Bus Reset occurs on the upstream port during the
95-ms semi-suspend time, the semi-suspend state is aborted
and program execution begins immediately from address
0x0000. In this case, the Bus Reset interrupt is pending but not
serviced until firmware sets the USB Bus Reset Interrupt Enable
bit (bit 0 of register 0x20) and enables interrupts with the EI
command.
■ the PSP and Data Stack Pointer (DSP) to be set to memory
address 0x00.
The occurrence of a reset is recorded in the Processor Status
and Control Register, as described in Processor Status and
Control Register on page 25. Bits 4 and 6 are used to record the
occurrence of POR and WDR, respectively. Firmware can
interrogate these bits to determine the cause of a reset.
The POR signal is asserted whenever VCC drops below
approximately 2.5 V, and remains asserted until VCC rises above
this level again. Behavior is the same as described above.
Watchdog Reset (WDR)
Program execution starts at ROM address 0x0000 after a reset.
Although this looks like interrupt vector 0, there is an important
difference. Reset processing does NOT push the program
counter, carry flag, and zero flag onto program stack. The
firmware reset handler should configure the hardware before the
“main” loop of code. Attempting to execute a RET or RETI in the
firmware reset handler causes unpredictable execution results.
The Watchdog Timer Reset (WDR) occurs when the internal
Watchdog timer rolls over. Writing any value to the write-only
Watchdog Restart Register at address 0x26 clears the timer. The
timer rolls over and WDR occurs if it is not cleared within tWATCH
(8 ms minimum) of the last clear. Bit 6 of the Processor Status
and Control Register is set to record this event (the register
contents are set to 010X0001 by the WDR). A Watchdog Timer
Reset lasts for 2 ms, after which the microcontroller begins
execution at ROM address 0x0000.
Power-On Reset (POR)
When VCC is first applied to the chip, the Power-On Reset (POR)
signal is asserted and the CY7C64x13C enters
a
Figure 2. Watchdog Reset (WDR)
2 ms
tWATCH
Last write to
Watchdog Timer
Register
No write to WDT
register, so WDR
goes HIGH
Execution begins at
Reset Vector 0x0000
The USB transmitter is disabled by a Watchdog Reset because
the USB Device Address Register is cleared. Otherwise, the
USB Controller would respond to all address 0 transactions.
Suspend Mode
The CY7C64x13C can be placed into a low-power state by
setting the Suspend bit of the Processor Status and Control
register. All logic blocks in the device are turned off except the
GPIO interrupt logic and the USB receiver. The clock oscillator
and PLL, as well as the free-running and Watchdog timers, are
shut down. Only the occurrence of an enabled GPIO interrupt or
non-idle bus activity at a USB upstream or downstream port
It is possible for the WDR bit of the Processor Status and Control
Register (0xFF) to be set following a POR event. The WDR bit
should be ignored If the firmware interrogates the Processor
Status and Control Register for a Set condition on the WDR bit
and if the POR (bit 3 of register 0xFF) bit is set.
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wakes the part out of suspend. The Run bit in the Processor
Status and Control Register must be set to resume a part out of
suspend.
The GPIO interrupt allows the controller to wake-up periodically
and poll system components while maintaining a very low
average power consumption. To achieve the lowest possible
current during suspend mode, all I/O should be held at VCC or
Gnd. This also applies to internal port pins that may not be
bonded in a particular package.
The clock oscillator restarts immediately after exiting suspend
mode. The microcontroller returns to a fully functional state 1 ms
after the oscillator is stable. The microcontroller executes the
instruction following the I/O write that placed the device into
suspend mode before servicing any interrupt requests.
Typical code for entering suspend is shown below:
...
...
; All GPIO set to low-power state (no floating pins)
; Enable GPIO interrupts if desired for wake-up
; Set suspend and run bits
; Write to Status and Control Register - Enter suspend, wait for USB activity (or GPIO Interrupt)
; This executes before any ISR
mov a, 09h
iowr FFh
nop
...
; Remaining code for exiting suspend routine
General-Purpose I/O (GPIO) Ports
Figure 3. Block Diagram of a GPIO Pin
VCC
GPIO
CFG
mode
2-bits
OE
Q2
Q1
Data
Out
Latch
Internal
Data Bus
14 k
GPIO
PIN
Port Write
Port Read
Q3*
Data
In
Latch
Reg_Bit
STRB
(Latch is Transparent
except in HAPI mode)
Data
Interrupt
Latch
Interrupt
Enable
*Port 0,1,2: Low Isink
Port 3: High Isink
Interrupt
Controller
There are up to 32 GPIO pins (P0[7:0], P1[7:0], P2[7:0], and
P3[7:0]) for the hardware interface. The number of GPIO pins
changes based on the package type of the chip. Each port can
be configured as inputs with internal pull-ups, open drain outputs,
or traditional CMOS outputs. Port 3 offers a higher current drive,
with typical current sink capability of 12 mA. The data for each
GPIO port is accessible through the data registers. Port data
registers are shown in Table 4 through Table 7, and are set to 1
on reset.
Table 4. Port 0 Data
Port 0 Data
ADDRESS 0x00
Bit #
7
6
5
4
3
2
1
0
Bit Name
Read/Write
Reset
P0.7
R/W
1
P0.6
R/W
1
P0.5
R/W
1
P0.4
R/W
1
P0.3
R/W
1
P0.2
R/W
1
P0.1
R/W
1
P0.0
R/W
1
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Table 5. Port 1 Data
Port 1 Data
ADDRESS 0x01
Bit #
7
6
5
4
3
2
1
0
Bit Name
Read/Write
Reset
P1.7
R/W
1
P1.6
R/W
1
P1.5
R/W
1
P1.4
R/W
1
P1.3
R/W
1
P1.2
R/W
1
P1.1
R/W
1
P1.0
R/W
1
Table 6. Port 2 Data
Port 2 Data
ADDRESS 0x02
Bit #
7
6
5
4
3
2
1
0
Bit Name
Read/Write
Reset
P2.7
R/W
1
P2.6
R/W
1
P2.5
R/W
1
P2.4
R/W
1
P2.3
R/W
1
P2.2
R/W
1
P2.1
R/W
1
P2.0
R/W
1
Table 7. Port 3 Data
Port 3 Data
ADDRESS 0x03
Bit #
7
6
5
4
3
2
1
0
Bit Name
Read/Write
Reset
P3.7
R/W
1
P3.6
R/W
1
P3.5
R/W
1
P3.4
R/W
1
P3.3
R/W
1
P32
R/W
1
P3.1
R/W
1
P3.0
R/W
1
Special care should be taken with any unused GPIO data bits.
An unused GPIO data bit, either a pin on the chip or a port bit
that is not bonded on a particular package, must not be left
floating when the device enters the suspend state. If a GPIO data
bit is left floating, the leakage current caused by the floating bit
may violate the suspend current limitation specified by the USB
Specifications. If a ‘1’ is written to the unused data bit and the
port is configured with open drain outputs, the unused data bit
remains in an indeterminate state. Therefore, if an unused port
bit is programmed in open-drain mode, it must be written with a
‘0.’ Notice that the CY7C64013C part always requires that the
data bits P1[7:3], P2[7,1,0], and P3[7:3] be written with a ‘0.’
a port, reads of that port return latched data as controlled by the
HAPI signals (see Hardware Assisted Parallel Interface (HAPI)
on page 24). During reset, all of the GPIO pins are set to a
high-impedance input state (‘1’ in open drain mode). Writing a ‘0’
to a GPIO pin drives the pin LOW. In this state, a ‘0’ is always
read on that GPIO pin unless an external source overdrives the
internal pull-down device.
GPIO Configuration Port
Every GPIO port can be programmed as inputs with internal
pull-ups, outputs LOW or HIGH, or Hi-Z (floating, the pin is not
driven internally). In addition, the interrupt polarity for each port
can be programmed. The Port Configuration bits (Table 8) and
the Interrupt Enable bit (Table 10 on page 17 through Table 13
on page 18) determine the interrupt polarity of the port pins.
In normal non-HAPI mode, reads from a GPIO port always return
the present state of the voltage at the pin, independent of the
settings in the Port Data Registers. If HAPI mode is activated for
Table 8. GPIO Configuration Register
GPIO
Configuration
ADDRESS 0x08
Bit #
7
6
5
4
3
2
1
0
Bit Name
Port 3
Config Bit 1
Port 3
Config Bit 0
Port 2
Config Bit 1
Port 2
Config Bit 0
Port 1
Config Bit 1
Port 1
Config Bit 0
Port 0
Config Bit 1
Port 0
Config Bit 0
Read/Write
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
As shown in Table 9 on page 17 below, a positive polarity on an
input pin represents a rising edge interrupt (LOW to HIGH), and
a negative polarity on an input pin represents a falling edge
interrupt (HIGH to LOW).
Interrupt Enable Register is enabled, the GPIO Interrupt Enable
bit of the Global Interrupt Enable Register (Table 28 on page 26)
is enabled, the Interrupt Enable Sense (bit 2,
Table 27 on page 25) is set, and the GPIO pin of the port sees
an event matching the interrupt polarity.
The GPIO interrupt is generated when all of the following
conditions are met: the Interrupt Enable bit of the associated Port
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The driving state of each GPIO pin is determined by the value
written to the pin’s Data Register (Table 4 on page 15 through
Table 7 on page 16) and by its associated Port Configuration bits
as shown in the GPIO Configuration Register
(Table 8 on page 16). These ports are configured on a per-port
basis, so all pins in a given port are configured together. The
possible port configurations are detailed in Table 9. As shown in
this table below, when a GPIO port is configured with CMOS
outputs, interrupts from that port are disabled.
During reset, all of the bits in the GPIO Configuration Register
are written with ‘0’ to select Hi-Z mode for all GPIO ports as the
default configuration.
Table 9. GPIO Port Output Control Truth Table and Interrupt Polarity
Port Config Bit 1 Port Config Bit 0 Data Register Output Drive Strength Interrupt Enable Bit
Interrupt Polarity
Disabled
1
1
0
0
1
0
1
0
0
1
0
1
0
1
0
1
Output LOW
Resistive
0
1
0
1
0
1
0
1
– (Falling Edge)
Disabled
Output LOW
Output HIGH
Output LOW
Hi-Z
Disabled
Disabled
– (Falling Edge)
Disabled
Output LOW
Hi-Z
+ (Rising Edge)
Q1, Q2, and Q3 discussed below are the transistors referenced
in Figure 3 on page 15. The available GPIO drive strength are:
■ Hi-Z Mode: The pin’s Data Register is set to1 and Port
Configuration Bits[1:0] is set either ‘00’ or ‘01’
Q1, Q2, and Q3 are all OFF. The GPIO pin is not driven
internally. In this mode, the pin may serve as an input.
Reading the Port Data Register returns the actual logic value
on the port pins.
■ Output LOW Mode: The pin’s Data Register is set to ‘0’
Writing ‘0’ to the pin’s Data Register puts the pin in output
LOW mode, regardless of the contents of the Port
Configuration Bits[1:0]. In this mode, Q1 and Q2 are OFF. Q3
is ON. The GPIO pin is driven LOW through Q3.
GPIO Interrupt Enable Ports
■ Output HIGH Mode: The pin’s Data Register is set to 1 and the
Port Configuration Bits[1:0] is set to ‘10’
Each GPIO pin can be individually enabled or disabled as an
interrupt source. The Port 0–3 Interrupt Enable registers provide
this feature with an interrupt enable bit for each GPIO pin. When
HAPI mode (discussed in Hardware Assisted Parallel Interface
(HAPI) on page 24) is enabled the GPIO interrupts are blocked,
including ports not used by HAPI, so GPIO pins cannot be used
as interrupt sources.
In this mode, Q1 and Q3 are OFF. Q2 is ON. The GPIO is
pulled up through Q2. The GPIO pin is capable of sourcing of
current.
■ Resistive Mode: The pin’s Data Register is set to 1 and the Port
Configuration Bits[1:0] is set to ‘11’
During a reset, GPIO interrupts are disabled by clearing all of the
GPIO interrupt enable ports. Writing a ‘1’ to a GPIO Interrupt
Enable bit enables GPIO interrupts from the corresponding input
pin. All GPIO pins share a common interrupt, as discussed in
GPIO/HAPI Interrupt on page 29.
Q2 and Q3 are OFF. Q1 is ON. The GPIO pin is pulled up with
an internal 14 kresistor. In resistive mode, the pin may serve
as an input. Reading the pin’s Data Register returns a logic
HIGH if the pin is not driven LOW by an external source.
Table 10. Port 0 Interrupt Enable
Port 0 Interrupt
Enable
ADDRESS 0x04
Bit #
7
6
5
4
3
2
1
0
Bit Name
Read/Write
Reset
P0.7 Intr Enable P0.6 Intr Enable P0.5 Intr Enable P0.4 Intr Enable P0.3 Intr Enable P0.2 Intr Enable P0.1 Intr Enable P0.0 Intr Enable
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Table 11. Port 1 Interrupt Enable
Port 1 Interrupt
Enable
ADDRESS 0x05
Bit #
7
6
5
4
3
2
1
0
Bit Name
Read/Write
Reset
P1.7 Intr Enable P1.6 Intr Enable P1.5 Intr Enable P1.4 Intr Enable P1.3 Intr Enabl P1.2 Intr Enable P1.1 Intr Enable P1.0 Intr Enable
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
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Table 12. Port 2 Interrupt Enable
Port 2 Interrupt
Enable
ADDRESS 0x06
Bit #
7
6
5
4
3
2
1
0
Bit Name
Read/Write
Reset
P2.7 Intr Enable P2.6 Intr Enable P2.5 Intr Enable P2.4 Intr Enable P2.3 Intr Enable P2.2 Intr Enable P2.1 Intr Enable P2.0 Intr Enable
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Table 13. Port 3 Interrupt Enable
Port 3 Interrupt
Enable
ADDRESS 0x07
Bit #
7
6
5
4
3
2
1
0
Bit Name
Reserved
(Set to 0)
P3.6 Intr Enable P3.5 Intr Enable P3.4 Intr Enable P3.3 Intr Enable P3.2 Intr Enable P3.1 Intr Enable P3.0 Intr Enable
Read/Write
Reset
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
the I/O pin HIGH through an integrated 14-k resistor. When a
‘0’ is written to a DAC I/O pin, the Isink DAC is enabled and the
pull-up resistor is disabled. This causes the Isink DAC to sink
current to drive the output LOW. Figure 4 shows a block diagram
of the DAC port pin.
DAC Port
The CY7C64113C features a programmable current sink 4 bit
port which is also known as a DAC port. Each of these port I/O
pins have a programmable current sink. Writing a ‘1’ to a DAC
I/O pin disables the output current sink (Isink DAC) and drives
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Figure 4. Block Diagram of a DAC Pin
VCC
Q1
Data
Out
Latch
Internal
Data Bus
Suspend
(Bit 3 of Register 0xFF)
14 k
DAC Write
DAC
I/O Pin
4 bits
Isink
Register
Isink
DAC
Internal
Buffer
DAC Read
Interrupt
Enable
to Interrupt
Controller
Interrupt
Polarity
The amount of sink current for the DAC I/O pin is programmable
over 16 values based on the contents of the DAC Isink Register
for that output pin. DAC[1:0] are high-current outputs that are
programmable from 3.2 mA to 16 mA (typical). DAC[7:2] are
low-current outputs, programmable from 0.2 mA to 1.0 mA
(typical).
circuitry is disabled. Special care should be taken when the
CY7C64x13C device is placed in the suspend mode. The DAC
Port Data Register (see Table 14) should normally be loaded
with all ‘1’s (0xFF) before setting the suspend bit. If any of the
DAC bits are set to ‘0’ when the device is suspended, that DAC
input will float. The floating pin could result in excessive current
consumption by the device, unless an external load places the
pin in a deterministic state.
When the suspend bit in Processor Status and Control Register
(see Table 27 on page 25) is set, the Isink DAC block of the DAC
Table 14. DAC Port Data
DAC Port Data
ADDRESS 0x30
Bit #
7
DAC[7]
R/W
1
6
Reserved
R/W
5
Reserved
R/W
4
Reserved
R/W
3
Reserved
R/W
2
DAC[2]
R/W
1
1
DAC[1]
R/W
1
0
DAC[0]
R/W
1
Bit Name
Read/Write
Reset
1
1
1
1
Bit [1..0]: High Current Output 3.2 mA to 16 mA typical
DAC Isink Registers
1= I/O pin is an output pulled HGH through the 14-k resistor.
0 = I/O pin is an input with an internal 14-k pull-up resistor
Bit [3..2]: Low Current Output 0.2 mA to 1 mA typical
1= I/O pin is an output pulled HGH through the 14-k resistor.
0 = I/O pin is an input with an internal 14-k pull-up resistor
Each DAC I/O pin has an associated DAC Isink register to
program the output sink current when the output is driven LOW.
The first Isink register (0x38) controls the current for DAC[0], the
second (0x39) for DAC[1], and so on until the Isink register at
0x3F controls the current to DAC[7].
Table 15. DAC Sink Register
DAC Sink
Register
ADDRESS 0x38 -0x3F
Bit #
7
6
5
4
3
Isink[3]
W
2
Isink[2]
W
1
Isink[1]
W
0
Isink[0]
W
Bit Name
Read/Write
Reset
Reserved
Reserved
Reserved
Reserved
-
-
-
-
0
0
0
0
Document Number: 38-08001 Rev. *D
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CY7C64113C
Bit [4..0]: Isink [x] (x= 0..4)
DAC Port Interrupts
Writing all ‘0’s to the Isink register causes 1/5 of the max current
to flow through the DAC I/O pin. Writing all ‘1’s to the Isink
register provides the maximum current flow through the pin. The
other 14 states of the DAC sink current are evenly spaced
between these two values.
A DAC port interrupt can be enabled/disabled for each pin
individually. The DAC Port Interrupt Enable register provides this
feature with an interrupt enable bit for each DAC I/O pin.All of the
DAC Port Interrupt Enable register bits are cleared to ‘0’ during
a reset. All DAC pins share a common interrupt, as explained in
DAC Interrupt on page 29.
Bit [7..5]: Reserved
Table 16. DAC Port Interrupt Enable
DAC Port
Interrupt
ADDRESS 0x31
Bit #
7
6
5
4
3
2
1
0
Bit Name
Read/Write
Reset
Enable Bit 7
Reserved
Reserved
Reserved
Reserved
Enable Bit 2
Enable Bit 1
Enable Bit 0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Bit [7..0]: Enable bit x (x= 0..2, 7)
causes an interrupt (if enabled) if a falling edge transition occurs
on the corresponding input pin. Writing a ‘1’ to a bit in this register
selects positive polarity (rising edge) that causes an interrupt (if
enabled) if a rising edge transition occurs on the corresponding
input pin. All of the DAC Port Interrupt Polarity register bits are
cleared during a reset.
1= Enables interrupts from the corresponding bit position;
0= Disables interrupts from the corresponding bit position
As an additional benefit, the interrupt polarity for each DAC pin
is programmable with the DAC Port Interrupt Polarity register.
Writing a ‘0’ to a bit selects negative polarity (falling edge) that
Table 17. DAC Port Interrupt Polarity
DAC Port
Interrupt
Polarity
ADDRESS 0x32
Bit #
7
6
5
4
3
2
1
0
Bit Name
Read/Write
Reset
Enable Bit 7
Reserved
Reserved
Reserved
Reserved
Enable Bit 2
Enable Bit 1
Enable Bit 0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
Bit [7..0]: Enable bit x (x= 0..2, 7)
in duration. The lower 8 bits of the timer can be read directly by
the firmware. Reading the lower 8 bits latches the upper 4 bits
into a temporary register. When the firmware reads the upper
4 bits of the timer, it is accessing the count stored in the
temporary register. The effect of this logic is to ensure a stable
12-bit timer value can be read, even when the two reads are
separated in time.
1= Selects positive polarity (rising edge) that causes an interrupt
(if enabled);
0= Selects negative polarity (falling edge) that causes an
interrupt (if enabled)
12-Bit Free-Running Timer
The 12-bit timer provides two interrupts (128-µs and 1.024-ms)
and allows the firmware to directly time events that are up to 4 ms
Table 18. Timer LSB Register
Timer LSB
ADDRESS 0x24
Bit #
7
6
5
4
3
2
1
0
Bit Name
Read/Write
Reset
Timer Bit 7
Timer Bit 6
Timer Bit 5
Timer Bit 4
Timer Bit 3
Timer Bit 2
Timer Bit 1
Timer Bit 0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Document Number: 38-08001 Rev. *D
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CY7C64113C
Bit [7:0]: Timer lower 8 bits
Table 19. Timer MSB Register
Timer MSB
ADDRESS 0x25
Bit #
7
6
5
4
3
2
1
0
Bit Name
Read/Write
Reset
Reserved
Reserved
Reserved
Reserved
Timer Bit 11
Timer Bit 10
Timer Bit 9
Timer Bit 8
-
-
-
-
R
0
R
0
R
0
R
0
0
0
0
0
Bit [3:0]: Timer higher nibble
Bit [7:4]: Reserved
Figure 5. Timer Block Diagram
1.024-ms Interrupt
128- µs Interrupt
1-MHz Clock
11 10 9
8
7
6
5
4
3
2
1
0
L3 L2 L1 L0
D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
To Timer Register
8
a HAPI for 1, 2, or 3 byte transfers. The I2C-compatible interface
and HAPI functions, discussed in detail in I2C-compatible
Controller on page 22 and Hardware Assisted Parallel Interface
(HAPI) on page 24, share a common configuration register (see
Table 21). All bits of this register are cleared on reset.
2
I C and HAPI Configuration Register
Internal hardware supports communication with external devices
through two interfaces: a two-wire I2C-compatible interface, and
Table 20. HAPI/I2C Configuration Register
I2C
ADDRESS 0x09
Configuration
Bit #
7
6
5
4
3
2
1
0
2
Bit Name
I C Position
Reserved
LEMPTY
Polarity
DRDY
Latch
Data
HAPIPortWidth HAPIPortWidth
Polarity
Empty
Ready
Bit 1
R/W
0
Bit 0
R/W
0
Read/Write
Reset
R/W
0
-
R/W
0
R/W
0
R
0
R
0
0
Note: I2C-compatible function must be separately enabled as
described in I2C-compatible Controller on page 22.
options. These I2C-compatible options exist due to pin limitations
in certain packages, and to allow simultaneous HAPI and
I2C-compatible operation.
Bits [7,1:0] of the HAPI/I2C Configuration Register control the pin
out configuration of the HAPI and I2C-compatible interfaces. Bits
[5:2] are used in HAPI mode only, and are described in
Hardware Assisted Parallel Interface (HAPI) on page 24.
Table 21 on page 22 shows the HAPI port configurations, and
Table 22 on page 22 shows I2C pin location configuration
HAPI operation is enabled whenever either HAPI Port Width Bit
(Bit 1 or 0) is non-zero. This affects GPIO operation as described
in Hardware Assisted Parallel Interface (HAPI) on page 24.
I2C-compatible blocks must be separately enabled as described
in I2C-compatible Controller on page 22.
Document Number: 38-08001 Rev. *D
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CY7C64113C
I2C-compatible Controller
Table 21. HAPI Port Configuration
Port Width (Bits[1:0])
HAPI Port Width
11
10
01
00
24 Bits: P3[7:0], P1[7:0], P0[7:0]
16 Bits: P1[7:0], P0[7:0]
8 Bits: P0[7:0]
No HAPI Interface
Table 22. I2C Port Configuration
I2C Position (Bit[7])
Port Width (Bit[1])
I2C Position
X
0
1
1
0
0
I2C on P2[1:0], 0:SCL, 1:SDA
I2C on P1[1:0], 0:SCL, 1:SDA
I2C on P2[1:0], 0:SCL, 1:SDA
and write registers. Generally, the I2C Status and Control
Register should only be monitored after the I2C interrupt, as all
bits are valid at that time. Polling this register at other times could
read misleading bit status if a transaction is underway.
2
I C-compatible Controller
The I2C-compatible block provides
a versatile two-wire
communication with external devices, supporting master, slave,
and multi-master modes of operation. The I2C-compatible block
functions by handling the low-level signaling in hardware, and
issuing interrupts as needed to allow firmware to take
appropriate action during transactions. While waiting for
firmware response, the hardware keeps the I2C-compatible bus
idle if necessary.
The I2C-compatible block generates an interrupt to the
microcontroller at the end of each received or transmitted byte,
when a stop bit is detected by the slave when in receive mode,
or when arbitration is lost. Details of the interrupt responses are
given in I2C Interrupt on page 30.
The I2C SCL clock is connected to bit 0 of GPIO port 1 or GPIO
port 2, and the I2C SDA data is connected to bit 1 of GPIO port
1 or GPIO port 2. Refer to I2C and HAPI Configuration Register
on page 21 for the bit definitions and functionality of the HAPI/I2C
Configuration Register, which is used to set the locations of the
configurable I2C-compatible pins. Once the I2C-compatible
functionality is enabled by setting bit 0 of the I2C Status & Control
Register, the two LSB bits ([1:0]) of the corresponding GPIO port
are placed in Open Drain mode, regardless of the settings of the
GPIO Configuration Register.The electrical characteristics of the
I2C-compatible interface is the same as that of GPIO ports 1 and
2. Note that the IOL (max) is 2 mA @ VOL = 2.0 V for ports 1 and 2.
The I2C-compatible interface consists of two registers, an I2C
Data Register (Table 23) and an I2C Status and Control Register
(Table 24). The Data Register is implemented as separate read
All control of the I2C clock and data lines is performed by the
I2C-compatible block.
Table 23. I2C Data Register
2
I C Data
ADDRESS 0x29
Bit #
7
6
5
4
3
2
1
0
2
2
2
2
2
2
2
2
Bit Name
Read/Write
Reset
I C Data 7
I C Data 6
I C Data 5
I C Data 4
I C Data 3
I C Data 2
I C Data 1
I C Data 0
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Bits [7..0] : I2C Data
Contains the 8 bit data on the I2C Bus
Table 24. I2C Status and Control Register
2
I C Status and
Control
Bit #
7
6
5
4
3
2
1
0
2
Bit Name
MSTR Mode
Continue/Busy
Xmit Mode
ACK
Addr
ARB
Lost/Restart
Received Stop
I C Enable
Read/Write
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
The I2C Status and Control register bits are defined in Table 26 on page 24, with a more detailed description following.
Document Number: 38-08001 Rev. *D
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Table 25. I2C Status and Control Register Bit Definitions
Bit
Name
I2C Enable
Description
0
When set to ‘1’, the I2C-compatible function is enabled. When cleared, I2C GPIO pins
operate normally.
1
2
3
4
Received Stop
ARB Lost/Restart
Addr
Reads 1 only in slave receive mode, when I2C Stop bit detected (unless firmware did not
ACK the last transaction).
Reads 1 to indicate master has lost arbitration. Reads 0 otherwise.
Write to 1 in master mode to perform a restart sequence (also set Continue bit).
Reads 1 during first byte after start/restart in slave mode, or if master loses arbitration.
Reads 0 otherwise. This bit should always be written as 0.
ACK
In receive mode, write 1 to generate ACK, 0 for no ACK.
In transmit mode, reads 1 if ACK was received, 0 if no ACK received.
5
6
Xmit Mode
Write to 1 for transmit mode, 0 for receive mode.
Continue/Busy
Write 1 to indicate ready for next transaction.
Reads 1 when I2C-compatible block is busy with a transaction, 0 when transaction is
complete.
7
MSTR Mode
Write to 1 for master mode, 0 for slave mode. This bit is cleared if master loses arbitration.
Clearing from 1 to 0 generates Stop bit.
Bit 7 : MSTR Mode
Setting this bit to 1 causes the I2C-compatible block to
initiate a master mode transaction by sending a start bit
Bit 5 : Xmit Mode
This bit is set by firmware to enter transmit mode and
perform a data transmit in master or slave mode. Clearing
this bit sets the part in receive mode. Firmware generally
determines the value of this bit from the R/W bit associated
with the I2C address packet. The Xmit Mode bit state is
ignored when initially writing the MSTR Mode or the
Restart bits, as these cases always cause transmit mode
for the first byte.
and transmitting the first data byte from the data register
(this typically holds the target address and R/W bit).
Subsequent bytes are initiated by setting the Continue bit,
as described below.
Clearing this bit (set to 0) causes the GPIO pins to operate
normally
Bit 4 : ACK
In master mode, the I2C-compatible block generates the
clock (SCK), and drives the data line as required
depending on transmit or receive state. The
I2C-compatible block performs any required arbitration
and clock synchronization. IN the event of a loss of
arbitration, this MSTR bit is cleared, the ARB Lost bit is set,
and an interrupt is generated by the microcontroller. If the
chip is the target of an external master that wins arbitration,
then the interrupt is held off until the transaction from the
external master is completed.
This bit is set or cleared by firmware during receive
operation to indicate if the hardware should generate an
ACK signal on the I2C-compatible bus. Writing a 1 to this
bit generates an ACK (SDA LOW) on the I2C-compatible
bus at the ACK bit time. During transmits (Xmit Mode = 1),
this bit should be cleared.
Bit 3 : Addr
This bit is set by the I2C-compatible block during the first
byte of a slave receive transaction, after an I2C start or
restart. The Addr bit is cleared when the firmware sets the
Continue bit. This bit allows the firmware to recognize
when the master has lost arbitration, and in slave mode it
allows the firmware to recognize that a start or restart has
occurred.
When MSTR Mode is cleared from 1 to 0 by a firmware
write, an I2C Stop bit is generated.
Bit 6 : Continue / Busy
This bit is written by the firmware to indicate that the
firmware is ready for the next byte transaction to begin. In
other words, the bit has responded to an interrupt request
and has completed the required update or read of the data
register. During a read this bit indicates if the hardware is
busy and is locking out additional writes to the I2C Status
and Control register. This locking allows the hardware to
complete certain operations that may require an extended
period of time. Following an I2C interrupt, the
I2C-compatible block does not return to the Busy state until
firmware sets the Continue bit. This allows the firmware to
make one control register write without the need to check
the Busy bit.
Bit 2 : ARB Lost/Restart
This bit is valid as a status bit (ARB Lost) after master
mode transactions. In master mode, set this bit (along with
the Continue and MSTR Mode bits) to perform an I2C
restart sequence. The I2C target address for the restart
must be written to the data register before setting the
Continue bit. To prevent false ARB Lost signals, the
Restart bit is cleared by hardware during the restart
sequence.
Document Number: 38-08001 Rev. *D
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Bit 1 : Receive Stop
This bit is set when the slave is in receive mode and
Hardware Assisted Parallel Interface (HAPI)
The CY7C64x13C processor provides a hardware assisted
parallel interface for bus widths of 8, 16, or 24 bits, to
accommodate data transfer with an external microcontroller or
similar device. Control bits for selecting the byte width are in the
HAPI/I2C Configuration Register (Table 20 on page 21), bits 1
and 0.
detects a stop bit on the bus. The Receive Stop bit is not
set if the firmware terminates the I2C transaction by not
acknowledging the previous byte transmitted on the
I2C-compatible bus, e.g. in receive mode if firmware sets
the Continue bit and clears the ACK bit.
Bit 0 : I2C Enable
Signals are provided on Port 2 to control the HAPI interface.
Table 26 describes these signals and the HAPI control bits in the
HAPI/I2C Configuration Register. Enabling HAPI causes the
GPIO setting in the GPIO Configuration Register (0x08) to be
overridden. The Port 2 output pins are in CMOS output mode and
Port 2 input pins are in input mode (open drain mode with Q3
OFF in Figure 3 on page 15).
Set this bit to override GPIO definition with I2C-compatible
function on the two I2C-compatible pins. When this bit is
cleared, these pins are free to function as GPIOs. In
I2C-compatible mode, the two pins operate in open drain
mode, independent of the GPIO configuration setting.
Table 26. Port 2 Pin and HAPI Configuration Bit Definitions
Pin
P2[2]
Name
LatEmptyPin
DReadyPin
STB
Direction
Out
Description (Port 2 Pin)
Ready for more input data from external interface.
P2[3]
P2[4]
P2[5]
P2[6]
Out
In
Output data ready for external interface.
Strobe signal for latching incoming data.
Output Enable, causes chip to output data.
Chip Select (Gates STB and OE).
OE
In
CS
In
Bit
2
Name
R/W
R
Description (HAPI/I2C Configuration Register)
Data Ready
Latch Empty
DRDY Polarity
Asserted after firmware writes data to Port 0, until OE driven LOW.
Asserted after firmware reads data from Port 0, until STB driven LOW.
3
R
4
R/W
Determines polarity of Data Ready bit and DReadyPin:
If 0, Data Ready is active LOW, DReadyPin is active HIGH.
If 1, Data Ready is active HIGH, DReadyPin is active LOW.
5
LEMPTY Polarity
R/W
Determines polarity of Latch Empty bit and LatEmptyPin:
If 0, Latch Empty is active LOW, LatEmptyPin is active HIGH.
If 1, Latch Empty is active HIGH, LatEmptyPin is active LOW.
HAPI Read by External Device from CY7C64x13C:
HAPI Write by External Device to CY7C64x13C:
In this case (see Figure 12), firmware writes data to the GPIO
ports. If 16-bit or 24-bit transfers are being made, Port 0 should
be written last, since writes to Port 0 asserts the Data Ready bit
and the DReady Pin to signal the external device that data is
available.
In this case (see Figure 13 on page 48), the external device
drives the STB and CS pins active (LOW) when it drives new
data onto the port pins. When this happens, the internal latches
become full, which causes the Latch Empty bit to be deasserted.
When STB is returned HIGH (inactive), the HAPI/GPIO interrupt
is generated. Firmware then reads the parallel ports to empty the
HAPI latches. If 16-bit or 24-bit transfers are being made, Port 0
should be read last because reads from Port 0 assert the Latch
Empty bit and the LatEmptyPin to signal the external device for
more data.
The external device then drives the OE and CS pins active
(LOW), which causes the HAPI data to be output on the port pins.
When OE is returned HIGH (inactive), the HAPI/GPIO interrupt
is generated. At that point, firmware can reload the HAPI latches
for the next output, again writing Port 0 last.
The Latch Empty bit reads the opposite state from the external
LatEmptyPin on pin P2[2]. If the LEMPTY Polarity bit is 0,
LatEmptyPin is active HIGH, and the Latch Empty bit is active
LOW.
The Data Ready bit reads the opposite state from the external
DReadyPin on pin P2[3]. If the DRDY Polarity bit is 0, DReadyPin
is active HIGH, and the Data Ready bit is active LOW.
Document Number: 38-08001 Rev. *D
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CY7C64113C
Processor Status and Control Register
Table 27. Processor Status and Control Register
Processor
Status and
Control
ADDRESS 0xFF
Bit #
7
6
5
4
3
2
1
0
Bit Name
IRQ
Pending
Watchdog
Reset
USB Bus Reset
Interrupt
Power-On
Reset
Suspend
Interrupt
Enable Sense
Reserved
Run
Read/Write
Reset
R
0
R/W
0
R/W
0
R/W
1
R/W
0
R
0
R/W
0
R/W
1
Bit 0: Run
Bit 5: USB Bus Reset Interrupt
This bit is manipulated by the HALT instruction. When Halt
is executed, all the bits of the Processor Status and Control
Register are cleared to 0. Since the run bit is cleared, the
processor stops at the end of the current instruction. The
processor remains halted until an appropriate reset occurs
(power-on or Watchdog). This bit should normally be
written as a ‘1.’
The USB Bus Reset Interrupt bit is set when the USB Bus
Reset is detected on receiving a USB Bus Reset signal on
the upstream port. The USB Bus Reset signal is a
single-ended zero (SE0) that lasts from 12 to 16 µs. An
SE0 is defined as the condition in which both the D+ line
and the D– line are LOW at the same time.
Bit 6: Watchdog Reset
Bit 1: Reserved
The Watchdog Reset is set during a reset initiated by the
Watchdog Timer. This indicates the Watchdog Timer went
for more than tWATCH (8 ms minimum) between Watchdog
clears. This can occur with a POR event, as noted below.
Bit 1 is reserved and must be written as a zero.
Bit 2: Interrupt Enable Sense
This bit indicates whether interrupts are enabled or
disabled. Firmware has no direct control over this bit as
writing a zero or one to this bit position has no effect on
interrupts. A ‘0’ indicates that interrupts are masked off and
a ‘1’ indicates that the interrupts are enabled. This bit is
further gated with the bit settings of the Global Interrupt
Enable Register (Table 28 on page 26) and USB End Point
Interrupt Enable Register (Table 29 on page 27).
Instructions DI, EI, and RETI manipulate the state of this
bit.
Bit 7: IRQ Pending
The IRQ pending, when set, indicates that one or more of
the interrupts has been recognized as active. An interrupt
remains pending until its interrupt enable bit is set (Table
28 on page 26, Table 29 on page 27) and interrupts are
globally enabled. At that point, the internal interrupt
handling sequence clears this bit until another interrupt is
detected as pending.
During power-up, the Processor Status and Control
Register is set to 00010001, which indicates a POR (bit 4
set) has occurred and no interrupts are pending (bit 7
clear). During the 96 ms suspend at start-up (explained in
Power-On Reset (POR) on page 14), a Watchdog Reset
also occurs unless this suspend is aborted by an upstream
SE0 before 8 ms. If a WDR occurs during the power-up
suspend interval, firmware reads 01010001 from the
Status and Control Register after power-up. Normally, the
POR bit should be cleared so a subsequent WDR can be
clearly identified. If an upstream bus reset is received
before firmware examines this register, the Bus Reset bit
may also be set.
Bit 3: Suspend
Writing a ‘1’ to the Suspend bit halts the processor and
cause the microcontroller to enter the suspend mode that
significantly reduces power consumption. A pending,
enabled interrupt or USB bus activity causes the device to
come out of suspend. After coming out of suspend, the
device resumes firmware execution at the instruction
following the IOWR which put the part into suspend. An
IOWR attempting to put the part into suspend is ignored if
USB bus activity is present. See Suspend Mode on page
14 for more details on suspend mode operation.
Bit 4: Power-On Reset
During a Watchdog Reset, the Processor Status and
Control Register(Table 27 on page 25) is set to
01XX0001b, which indicates a Watchdog Reset (bit 6 set)
has occurred and no interrupts are pending (bit 7 clear).
The Watchdog Reset does not effect the state of the POR
and the Bus Reset Interrupt bits.
The Power-On Reset is set to ‘1’ during a power-on reset.
The firmware can check bits 4 and 6 in the reset handler
to determine whether a reset was caused by a power-on
condition or a Watchdog timeout. A POR event may be
followed by a Watchdog reset before firmware begins
executing, as explained below.
Document Number: 38-08001 Rev. *D
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Interrupts
Interrupts are generated by the GPIO/DAC pins, the internal
timers, I2C-compatible interface or HAPI operation, or on various
USB traffic conditions. All interrupts are maskable by the Global
Interrupt Enable Register and the USB End Point Interrupt
Enable Register. Writing a ‘1’ to a bit position enables the
interrupt associated with that bit position.
Table 28. Global Interrupt Enable Register
Global
ADDRESS 0X20
Interrupt
Enable
Register
Bit #
7
6
5
4
3
2
1
0
2
Bit Name
Reserved
I C Interrupt
Enable
GPIO Interrupt
Enable
DAC Interrupt
enable
Reserved
1.024-ms
128-sInterrupt USB Bus RST
Interrupt Enable
Enable
R/W
0
Interrupt Enable
Read/Write
Reset
-
-
R/W
0
R/W
0
-
R/W
0
R/W
0
R/W
0
X
Bit 0 : USB Bus RST Interrupt Enable
Bit 4 : DAC Interrupt Enable
1= Enable Interrupt on a USB Bus Reset; 0 = Disable
interrupt on a USB Bus Reset (Refer to USB Bus Reset
Interrupt on page 29)
1 = Enable DAC Interrupt; 0 = Disable DAC interrupt
Bit 5 : GPIO Interrupt Enable
1 = Enable Interrupt on falling/rising edge on any GPIO;
0 = Disable Interrupt on falling/rising edge on any GPIO
(Refer to GPIO Configuration Port on page 16 and GPIO
Interrupt Enable Ports on page 17.)
Bit 1 :128-µs Interrupt Enable
1 = Enable Timer interrupt every 128 µs; 0 = Disable Timer
Interrupt for every 128 µs.
Bit 6 : I2C Interrupt Enable
Bit 2 : 1.024-ms Interrupt Enable
1= Enable Interrupt on I2C related activity; 0 = Disable I2C
related activity interrupt.
1= Enable Timer interrupt every 1.024 ms; 0 = Disable
Timer Interrupt every 1.024 ms.
(Refer to I2C Interrupt on page 30).
Bit 3 : Reserved
Bit 7 : Reserved
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Table 29. USB Endpoint Interrupt Enable Register
USB Endpoint
Interrupt
Enable
ADDRESS 0X21
Bit #
7
6
5
4
3
2
1
0
Bit Name
Reserved
Reserved
Reserved
EPB1 Interrupt
Enable
EPB0 Interrupt EPA2 Interrupt
EPA1 Interrupt EPA0 Interrupt
Enable
R/W
0
Enable
R/W
0
Enable
R/W
0
Enable
R/W
0
Read/Write
Reset
-
-
-
-
-
-
R/W
0
Figure 6. USB Endpoint Interrupt Enable Register
Bit 0: EPA0 Interrupt Enable
3. Generates an automatic CALL instruction to the ROM ad-
dress associated with the interrupt being serviced (i.e., the
Interrupt Vector, see Interrupt Vectors).
1= Enable Interrupt on data activity through endpoint A0;
0= Disable Interrupt on data activity through endpoint A0
The instruction in the interrupt table is typically a JMP instruction
to the address of the Interrupt Service Routine (ISR). The user
can re-enable interrupts in the interrupt service routine by
executing an EI instruction. Interrupts can be nested to a level
limited only by the available stack space.
Bit 1: EPA1 Interrupt Enable
1= Enable Interrupt on data activity through endpoint A1;
0= Disable Interrupt on data activity through endpoint A1
Bit 2: EPA2 Interrupt Enable
The Program Counter value as well as the Carry and Zero flags
(CF, ZF) are stored onto the Program Stack by the automatic
CALL instruction generated as part of the interrupt acknowledge
process. The user firmware is responsible for ensuring that the
processor state is preserved and restored during an interrupt.
The PUSH A instruction should typically be used as the first
command in the ISR to save the accumulator value and the POP
A instruction should be used to restore the accumulator value
just before the RETI instruction. The program counter CF and ZF
are restored and interrupts are enabled when the RETI
instruction is executed.
1= Enable Interrupt on data activity through endpoint A2;
0= Disable Interrupt on data activity through endpoint A2.
Bit 3: EPB0 Interrupt Enable
1= Enable Interrupt on data activity through endpoint B0;
0= Disable Interrupt on data activity through endpoint B0
Bit 4: EPB1 Interrupt Enable
1= Enable Interrupt on data activity through endpoint B1;
0= Disable Interrupt on data activity through endpoint B1
Bit [7..5] : Reserved
The DI and EI instructions can be used to disable and enable
interrupts, respectively. These instructions affect only the Global
Interrupt Enable bit of the CPU. If desired, EI can be used to
re-enable interrupts while inside an ISR, instead of waiting for the
RETI that exists the ISR. While the global interrupt enable bit is
cleared, the presence of a pending interrupt can be detected by
examining the IRQ Sense bit (Bit 7 in the Processor Status and
Control Register).
During a reset, the contents the Global Interrupt Enable Register
and USB End Point Interrupt Enable Register are cleared,
effectively, disabling all interrupts
The interrupt controller contains a separate flip-flop for each
interrupt. See Figure 7 on page 28 for the logic block diagram of
the interrupt controller. When an interrupt is generated, it is first
registered as a pending interrupt. It stays pending until it is
serviced or a reset occurs. A pending interrupt only generates an
interrupt request if it is enabled by the corresponding bit in the
interrupt enable registers. The highest priority interrupt request
is serviced following the completion of the currently executing
instruction.
Interrupt Vectors
The Interrupt Vectors supported by the USB Controller are listed
in Table 30 on page 29. The lowest-numbered interrupt (USB
Bus Reset interrupt) has the highest priority, and the
highest-numbered interrupt (I2C interrupt) has the lowest priority.
When servicing an interrupt, the hardware does the following
1. Disables all interrupts by clearing the Global Interrupt Enable
bit in the CPU (the state of this bit can be read at Bit 2 of the
Processor Status and Control Register, Table 27 on page 25).
2. Clears the flip-flop of the current interrupt.
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Figure 7. Interrupt Controller Function Diagram
USB Reset Clear
Interrupt
Vector
To CPU
CLR
USB Reset IRQ
128-s CLR
128-s IRQ
1-ms CLR
1-ms IRQ
1
D
Q
Enable [0]
(Reg 0x20)
CPU
USB Reset Int
IRQ Sense
IRQ
CLK
IRQout
AddrA EP0 CLR
AddrA EP0 IRQ
AddrA EP1 CLR
AddrA EP1 IRQ
AddrA EP2 CLR
AddrA EP2 IRQ
CLR
Q
1
D
Global
Interrupt
Enable
Bit
Int Enable
Sense
Enable [2]
(Reg 0x21)
AddrB EP0 CLR
AddrB EP0 IRQ
AddrA ENP2 Int
CLK
AddrB EP1 CLR
AddrB EP1 IRQ
Controlled by DI, EI, and
RETI Instructions
CLR
Hub CLR
Hub IRQ
Interrupt
Acknowledge
DAC CLR
DAC IRQ
GPIO CLR
GPIO IRQ
I2C CLR
CLR
I2C IRQ
Q
1
Enable [6]
(Reg 0x20)
D
Interrupt Priority Encoder
I2C Int
CLK
Although Reset is not an interrupt, the first instruction executed
after a reset is at PROM address 0x0000h—which corresponds
to the first entry in the Interrupt Vector Table. Because the JMP
instruction is two bytes long, the interrupt vectors occupy two
bytes.
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Table 30. Interrupt Vector Assignments
Interrupt Vector Number
ROM Address
0x0000
0x0002
0x0004
0x0006
0x0008
0x000A
0x000C
0x000E
0x0010
0x0012
0x0014
0x0016
0x0018
Function
Not Applicable
Execution after Reset begins here
USB Bus Reset interrupt
128- µs timer interrupt
1
2
3
1.024-ms timer interrupt
USB Address A Endpoint 0 interrupt
USB Address A Endpoint 1 interrupt
USB Address A Endpoint 2 interrupt
USB Address A Endpoint 3 interrupt
USB Address A Endpoint 4 interrupt
Reserved
4
5
6
7
8
9
10
11
12
DAC interrupt
GPIO interrupt
I2C interrupt
USB endpoint FIFO or after the USB controller sends a packet
to the USB host. The interrupt is generated on the last packet of
the transaction (e.g., on the host’s ACK during an IN, or on the
device ACK during on OUT). If no ACK is received during an IN
transaction, no interrupt is generated.
Interrupt Latency
Interrupt latency can be calculated from the following equation:
Interrupt latency = (Number of clock cycles remaining in the
current instruction) + (10 clock cycles for the CALL instruction) +
(5 clock cycles for the JMP instruction)
DAC Interrupt
For example, if a 5 clock cycle instruction such as JC is being
executed when an interrupt occurs, the first instruction of the
Interrupt Service Routine executes a minimum of 16 clocks
(1+10+5) or a maximum of 20 clocks (5+10+5) after the interrupt
is issued. For a 12-MHz internal clock (6-MHz crystal), 20 clock
periods is 20 / 12 MHz = 1.667 µs.
Each DAC I/O pin can generate an interrupt, if enabled. The
interrupt polarity for each DAC I/O pin is programmable. A
positive polarity is a rising edge input while a negative polarity is
a falling edge input. All of the DAC pins share a single interrupt
vector, which means the firmware needs to read the DAC port to
determine which pin or pins caused an interrupt.
USB Bus Reset Interrupt
If one DAC pin has triggered an interrupt, no other DAC pins can
cause a DAC interrupt until that pin has returned to its inactive
(non-trigger) state or the corresponding interrupt enable bit is
cleared. The USB Controller does not assign interrupt priority to
different DAC pins and the DAC Interrupt Enable Register is not
cleared during the interrupt acknowledge process.
The USB Controller recognizes a USB Reset when a Single
Ended Zero (SE0) condition persists on the upstream USB port
for 12–16 µs (the Reset may be recognized for an SE0 as short
as 12 µs, but is always recognized for an SE0 longer than 16 µs).
SE0 is defined as the condition in which both the D+ line and the
D– line are LOW. Bit 5 of the Status and Control Register is set
to record this event. The interrupt is asserted at the end of the
Bus Reset. If the USB reset occurs during the start-up delay
following a POR, the delay is aborted as described in Power-On
Reset (POR) on page 14. The USB Bus Reset Interrupt is
generated when the SE0 state is deasserted.
GPIO/HAPI Interrupt
Each of the GPIO pins can generate an interrupt, if enabled. The
interrupt polarity can be programmed for each GPIO port as part
of the GPIO configuration. All of the GPIO pins share a single
interrupt vector, which means the firmware needs to read the
GPIO ports with enabled interrupts to determine which pin or pins
caused an interrupt. A block diagram of the GPIO interrupt logic
is shown in Figure 8 on page 30. Refer to GPIO Configuration
Port on page 16 and GPIO Interrupt Enable Ports on page 17 for
more information of setting GPIO interrupt polarity and enabling
individual GPIO interrupts.
A USB Bus Reset clears the following registers:
SIE Section:USB Device Address Registers (0x10, 0x40)
Timer Interrupt
There are two periodic timer interrupts: the 128- µs interrupt and
the 1.024-ms interrupt. The user should disable both timer inter-
rupts before going into the suspend mode to avoid possible
conflicts between servicing the timer interrupts first or the
suspend request first.
If one port pin has triggered an interrupt, no other port pins can
cause a GPIO interrupt until that port pin has returned to its
inactive (non-trigger) state or its corresponding port interrupt
enable bit is cleared. The USB Controller does not assign
interrupt priority to different port pins and the Port Interrupt
Enable Registers are not cleared during the interrupt
acknowledge process.
USB Endpoint Interrupts
There are five USB endpoint interrupts, one per endpoint. A USB
endpoint interrupt is generated after the USB host writes to a
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Figure 8. GPIO Interrupt Structure
Port
Configuration
GPIO Interrupt
Flip Flop
Register
OR Gate
(1 input per
GPIO pin)
IRQout
Interrupt
Priority
1
D
Q
M
U
X
Interrupt
Vector
Encoder
GPIO
Pin
CLR
Port Interrupt
Enable Register
1 = Enable
0 = Disable
IRA
Global
GPIO Interrupt
Enable
1 = Enable
0 = Disable
(Bit 5, Register 0x20)
When HAPI is enabled, the HAPI logic takes over the interrupt
vector and blocks any interrupt from the GPIO bits, including
ports/bits not being used by HAPI. Operation of the HAPI
interrupt is independent of the GPIO specific bit interrupt
enables, and is enabled or disabled only by bit 5 of the Global
Interrupt Enable Register (Table 28 on page 26) when HAPI is
enabled. The settings of the GPIO bit interrupt enables on
ports/bits not used by HAPI still effect the CMOS mode operation
of those ports/bits. The effect of modifying the interrupt bits while
the Port Config bits are set to “10” is shown in Table 9. The
events that generate HAPI interrupts are described in Hardware
Assisted Parallel Interface (HAPI) on page 24.
3. In slave transmit mode, after the slave transmits a byte of
data: The ACK bit indicates if the master that requested the
byte acknowledged the byte. If more bytes are to be sent,
firmware writes the next byte into the Data Register and then
sets the Xmit MODE and Continue/Busy bits as required.
4. In master transmit mode, after the master sends a byte of
data. Firmware should load the Data Register if necessary,
and set the Xmit MODE, MSTR MODE, and Continue/Busy
bits appropriately. Clearing the MSTR MODE bit issues a stop
signal to the I2C-compatible bus and return to the idle state.
5. In master receive mode, after the master receives a byte of
data: Firmware should read the data and set the ACK and
Continue/Busy bits appropriately for the next byte. Clearing
the MSTR MODE bit at the same time causes the master state
machine to issue a stop signal to the I2C-compatible bus and
leave the I2C-compatible hardware in the idle state.
2
I C Interrupt
The I2C interrupt occurs after various events on the
I2C-compatible bus to signal the need for firmware interaction.
This generally involves reading the I2C Status and Control
Register (Table 24 on page 22) to determine the cause of the
interrupt, loading/reading the I2C Data Register as appropriate,
and finally writing the Status and Control Register to initiate the
subsequent transaction. The interrupt indicates that status bits
are stable and it is safe to read and write the I2C registers. Refer
to I2C-compatible Controller on page 22 for details on the I2C
registers.
6. When the master loses arbitration: This condition clears the
MSTR MODE bit and sets the ARB Lost/Restart bit
immediately and then waits for a stop signal on the
I2C-compatible bus to generate the interrupt.
The Continue/Busy bit is cleared by hardware prior to interrupt
conditions 1 to 4. Once the Data Register has been read or
written, firmware should configure the other control bits and set
the Continue/Busy bit for subsequent transactions. Following an
interrupt from master mode, firmware should perform only one
write to the Status and Control Register that sets the
Continue/Busy bit, without checking the value of the
Continue/Busy bit. The Busy bit may otherwise be active and I2C
register contents may be changed by the hardware during the
transaction, until the I2C interrupt occurs.
When enabled, the I2C-compatible state machines generate
interrupts on completion of the following conditions. The refer-
enced bits are in the I2C Status and Control Register.
1. In slave receive mode, after the slave receives a byte of data:
The Addr bit is set, if this is the first byte since a start or restart
signal was sent by the external master. Firmware must read
or write the data register as necessary, then set the ACK, Xmit
MODE, and Continue/Busy bits appropriately for the next
byte.
USB Overview
The USB hardware consists of the logic for a full-speed USB
Port. The full-speed serial interface engine (SIE) interfaces the
2. In slave receive mode, after a stop bit is detected: The
Received Stop bit is set, if the stop bit follows a slave receive
transaction where the ACK bit was cleared to 0, no stop bit
detection occurs.
microcontroller to the USB bus. An external series resistor (Rext
)
must be placed in series with the D+ and D– lines, as close to
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the corresponding pins as possible, to meet the USB driver
requirements of the USB specifications.
In this description, ‘Firmware’ refers to embedded firmware in the
CY7C64x13C controller.
1. The host computer sends a SETUP packet followed by a
DATA packet to USB address 0 requesting the Device
descriptor.
USB Serial Interface Engine (SIE)
The SIE allows the CY7C64x13C microcontroller to commu-
nicate with the USB host. The SIE simplifies the interface
between the microcontroller and USB by incorporating hardware
that handles the following USB bus activity independently of the
microcontroller:
2. Firmware decodes the request and retrieves its Device
descriptor from the program memory tables.
3. The host computer performs a control read sequence and
Firmware responds by sending the Device descriptor over the
USB bus, via the on-chip FIFOs.
■ Bit stuffing/unstuffing
4. After receiving the descriptor, the host sends a SETUP packet
followed by a DATA packet to address 0 assigning a new USB
address to the device.
■ Checksum generation/checking
■ ACK/NAK/STALL
5. Firmware stores the new address in its USB Device Address
Register after the no-data control sequence completes.
■ Token type identification
■ Address checking
6. The host sends a request for the Device descriptor using the
new USB address.
Firmware is required to handle the following USB interface tasks:
7. Firmware decodes the request and retrieves the Device
descriptor from program memory tables.
■ Coordinate enumeration by responding to SETUP packets
■ Fill and empty the FIFOs
8. The host performs a control read sequence and Firmware
responds by sending its Device descriptor over the USB bus.
■ Suspend/Resume coordination
9. The host generates control reads from the device to request
the Configuration and Report descriptors.
■ Verify and select DATA toggle values
USB Enumeration
10.Once the device receives a Set Configuration request, its
functions may now be used.
The USB device is enumerated under firmware control. The
following is a brief summary of the typical enumeration process
of the CY7C64x13C by the USB host. For a detailed description
of the enumeration process, refer to the USB specification.
USB Upstream Port Status and Control
USB status and control is regulated by the USB Status and
Control Register, as shown in Table 31. All bits in the register are
cleared during reset.
Table 31. USB Status and Control Register
USB Status
and Control
ADDRESS 0x1F
Bit #
7
6
5
4
3
2
1
0
Bit Name
Endpoint Size
Endpoint Mode
D+ Upstream
D– Upstream
Bus Activity
Control Action
Bit 2
Control Action
Bit 1
Control Action
Bit 0
Read/Write
Reset
R/W
0
R/W
0
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits[2..0] : Control Action
cleared. Table 32 shows how the control bits affect the up-
stream port.
Set to control action as per Table 32.The three control bits
allow the upstream port to be driven manually by firmware.
For normal USB operation, all of these bits must be
Table 32. Control Bit Definition for Upstream Port
Control Bits
000
Control Action
Not Forcing (SIE Controls Driver)
Force D+[0] HIGH, D–[0] LOW
Force D+[0] LOW, D–[0] HIGH
Force SE0; D+[0] LOW, D–[0] LOW
Force D+[0] LOW, D–[0] LOW
Force D+[0] HiZ, D–[0] LOW
Force D+[0] LOW, D–[0] HiZ
Force D+[0] HiZ, D–[0] HiZ
001
010
011
100
101
110
111
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Bit 3 : Bus Activity
This is a “sticky” bit that indicates if any non-idle USB event
This bit used to configure the number of USB endpoints.
See USB Device Endpoints on page 32 for a detailed
description.
has occurred on the upstream USB port. Firmware should
check and clear this bit periodically to detect any loss of
bus activity. Writing a ‘0’ to the Bus Activity bit clears it,
while writing a ‘1’ preserves the current value. In other
words, the firmware can clear the Bus Activity bit, but only
the SIE can set it.
USB Serial Interface Engine Operation
USB Device Address A includes up to five endpoints: EPA0,
EPA1, EPA2, EPA3, and EPA4. Endpoint (EPA0) allows the USB
host to recognize, set-up, and control the device. In particular,
EPA0 is used to receive and transmit control (including set-up)
packets.
Bits 4 and 5 : D– Upstream and D+ Upstream
These bits give the state of each upstream port pin individ-
ually: 1 = HIGH, 0 = LOW.
USB Device Address
Bit 6 : Endpoint Mode
The USB Controller provides one USB Device Address with five
endpoints. The USB Device Address Register contents are
cleared during a reset, setting the USB device address to zero
and marking this address as disabled. Table 33 shows the format
of the USB Address Registers.
This bit used to configure the number of USB endpoints.
See USB Device Endpoints on page 32 for a detailed
description.
Bit 7 : Endpoint Size
Table 33. USB Device Address Registers
USB Device
Address
ADDRESSES 0x10
Bit #
7
6
5
4
3
2
1
0
Bit Name
Device Address Device Address Device Address Device Address Device Address Device Address Device Address Device Address
Enable
R/W
0
Bit 6
R/W
0
Bit 5
R/W
0
Bit 4
R/W
0
Bit 3
R/W
0
Bit 2
R/W
0
Bit 1
R/W
0
Bit 0
R/W
0
Read/Write
Reset
Bits[6..0] :Device Address
enumeration process to the non-zero address assigned by
the USB host.
Firmware writes this bits during the USB enumeration pro-
cess to the non-zero address assigned by the USB host.
USB Device Endpoints
Bit 7
:Device Address Enable
The CY7C64x13C controller supports one USB device address
and five endpoints for communication with the host. The
configuration of these endpoints, and associated FIFOs, is
controlled by bits [7,6] of the USB Status and Control Register
(0x1F). Bit 7 controls the size of the endpoints and bit 6 controls
the number of endpoints. These configuration options are
detailed in Table 34. The “unused” FIFO areas in the following
table can be used by the firmware as additional user RAM space.
Must be set by firmware before the SIE can respond to
USB traffic to the Device Address.
Bit 7 (Device Address Enable) in the USB Device Address
Register must be set by firmware before the SIE can
respond to USB traffic to this address. The Device
Addresses in bits [6:0] are set by firmware during the USB
Table 34. Memory Allocation for Endpoints
USB Status And Control Register (0x1F) Bits [7, 6]
[0,0]
[1,0]
[0,1]
[1,1]
Start
Start
Start
Start
Label
unused
unused
EPA2
Address
Size
Label
unused
unused
EPA0
Address
Size
8
Label
EPA4
EPA3
EPA2
EPA1
EPA0
Address
Size
Label
EPA4
EPA3
EPA0
EPA1
EPA2
Address
Size
8
0xD8
0xE0
0xE8
0xF0
0xF8
8
8
8
8
8
0xA8
0xB0
0xB8
0xC0
0xE0
0xD8
0xE0
0xE8
0xF0
0xF8
8
8
8
8
8
0xB0
0xA8
0xB8
0xC0
0xE0
8
8
8
8
EPA1
EPA1
32
32
32
32
EPA0
EPA2
When the SIE writes data to a FIFO, the internal data bus is
driven by the SIE; not the CPU. This causes a short delay in the
CPU operation. The delay is three clock cycles per byte. For
example, an 8-byte data write by the SIE to the FIFO generates
a delay of 2 µs (3 cycles/byte * 83.33 ns/cycle * 8 bytes).
USB Control Endpoint Mode Register
All USB devices are required to have a Control Endpoint 0
(EPA0) that is used to initialize and control each USB address.
Endpoint 0 provides access to the device configuration
information and allows generic USB status and control accesses.
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Endpoint 0 is bidirectional to both receive and transmit data. The
other endpoints are unidirectional, but selectable by the user as
IN or OUT endpoints.
The endpoint mode register is cleared during reset. The endpoint
zero EPA0 mode register uses the format shown in Table 35.
Table 35. USB Device Endpoint Zero Mode Registers
USB Device
Endpoint Zero
Mode
ADDRESSES 0x12
Bit #
7
6
5
4
3
2
1
0
Bit Name
Endpoint0SETUP
Received
Endpoint 0 IN Endpoint 0 OUT
ACK
Mode Bit 3
Mode Bit 2
Mode Bit 1
Mode Bit 0
Received
Received
Read/Write
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits[3..0] : Mode
the SIE. The CPU should not clear this bit during this
interval, and subsequently, until the CPU first does an
IORD to this endpoint 0 mode register. The bit must be
cleared by firmware as part of the USB processing.
These sets the mode which control how the control end-
point responds to traffic.
Bit 4 : ACK
Bits[6:0] of the endpoint 0 mode register are locked from CPU
write operations whenever the SIE has updated one of these bits,
which the SIE does only at the end of the token phase of a
transaction (SETUP... Data... ACK, OUT... Data... ACK, or IN...
Data... ACK). The CPU can unlock these bits by doing a
subsequent read of this register. Only endpoint 0 mode registers
are locked when updated. The locking mechanism does not
apply to the mode registers of other endpoints.
This bit is set whenever the SIE engages in a transaction
to the register’s endpoint that completes with an ACK
packet.
Bit 5: Endpoint 0 OUT Received
1 = Token received is an OUT token. 0 = Token received
is not an OUT token. This bit is set by the SIE to report the
type of token received by the corresponding device
address is an OUT token. The bit must be cleared by
firmware as part of the USB processing.
Because of these hardware locking features, firmware must
perform an IORD after an IOWR to an endpoint 0 register. This
verifies that the contents have changed as desired, and that the
SIE has not updated these values.
Bit 6: Endpoint 0 IN Received
1= Token received is an IN token. 0= Token received is not
an IN token. This bit is set by the SIE to report the type of
token received by the corresponding device address is an
IN token. The bit must be cleared by firmware as part of
the USB processing.
While the SETUP bit is set, the CPU cannot write to the endpoint
zero FIFOs. This prevents firmware from overwriting an incoming
SETUP transaction before firmware has a chance to read the
SETUP data. Refer to Table 34 for the appropriate endpoint zero
memory locations.
Bit 7: Endpoint 0 SETUP Received
The Mode bits (bits [3:0]) control how the endpoint responds to
USB bus traffic. The mode bit encoding is shown inTable 38.
Additional information on the mode bits can be found inTable 39.
1= Token received is a SETUP token. 0= Token received
is not a SETUP token. This bit is set ONLY by the SIE to
report the type of token received by the corresponding
device address is a SETUP token. Any write to this bit by
the CPU will clear it (set it to 0). The bit is forced HIGH from
the start of the data packet phase of the SETUP
transaction until the start of the ACK packet returned by
USB Non-Control Endpoint Mode Registers
The format of the non-control endpoint mode register is shown
in Table 36.
Table 36. USB Non-Control Device Endpoint Mode Registers
USB
ADDRESSES 0x14, 0x16, 0x42, 0x44
Non-Control
Device
Endpoint
Mode
Bit #
7
STALL
R/W
0
6
Reserved
R/W
5
Reserved
R/W
4
3
Mode Bit 3
R/W
2
Mode Bit 2
R/W
1
Mode Bit 1
R/W
0
Mode Bit 0
R/W
Bit Name
Read/Write
Reset
ACK
R/W
0
0
0
0
0
0
0
Bits[3..0] : Mode
These sets the mode which control how the control end-
point responds to traffic. The mode bit encoding is shown
in Table 38
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Bit 4 : ACK
This bit is set whenever the SIE engages in a transaction
the mode bits are set to ACK-OUT. For all other modes, the
STALL bit must be a LOW.
to the register’s endpoint that completes with an ACK
packet.
USB Endpoint Counter Registers
There are five Endpoint Counter registers, with identical formats
for both control and non-control endpoints. These registers
contain byte count information for USB transactions, as well as
bits for data packet status. The format of these registers is shown
in Table 37:
Bits[6..5] : Reserved
Must be written zero during register writes.
Bit 7 : STALL
If this STALL is set, the SIE stalls an OUT packet if the
mode bits are set to ACK-IN, and the SIE stalls an IN packet if
Table 37. USB Endpoint Counter Registers
USB Endpoint
Counter
ADDRESSES 0x11, 0x13, 0x15, 0x41, 0x43
Bit #
7
6
Data Valid
R/W
5
4
3
2
1
0
Bit Name
Read/Write
Reset
Data 0/1 Toggle
Byte Count Bit 5 Byte Count Bit 4 Byte Count Bit 3 Byte Count Bit 2 Byte Count Bit 1 Byte Count Bit 0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
Bits[5..0] : Byte Count
Endpoint Mode/Count Registers Update and Locking
Mechanism
These counter bits indicate the number of data bytes in a
transaction. For IN transactions, firmware loads the count
with the number of bytes to be transmitted to the host from
the endpoint FIFO. Valid values are 0 to 32, inclusive. For
OUT or SETUP transactions, the count is updated by
hardware to the number of data bytes received, plus 2 for
the CRC bytes. Valid values are 2 to 34, inclusive.
The contents of the endpoint mode and counter registers are
updated, based on the packet flow diagram in Figure 9. Two time
points, UPDATE and SETUP, are shown in the same figure. The
following activities occur at each time point:
SETUP:
The SETUP bit of the endpoint 0 mode register is forced HIGH
at this time. This bit is forced HIGH by the SIE until the end of the
data phase of a control write transfer. The SETUP bit can not be
cleared by firmware during this time.
Bit 6 : Data Valid
This bit is set on receiving a proper CRC when the
endpoint FIFO buffer is loaded with data during
transactions. This bit is used OUT and SETUP tokens only.
If the CRC is not correct, the endpoint interrupt occurs, but
Data Valid is cleared to a zero.
The affected mode and counter registers of endpoint 0 are
locked from any CPU writes once they are updated. These
registers can be unlocked by a CPU read, only if the read
operation occurs after the UPDATE. The firmware needs to
perform a register read as a part of the endpoint ISR processing
to unlock the effected registers. The locking mechanism on
mode and counter registers ensures that the firmware
recognizes the changes that the SIE might have made since the
previous IO read of that register.
Bit 7 : Data 0/1 Toggle
This bit selects the DATA packet’s toggle state: 0 for
DATA0, 1 for DATA1. For IN transactions, firmware must
set this bit to the desired state. For OUT or SETUP
transactions, the hardware sets this bit to the state of the
received Data Toggle bit.
UPDATE:
Whenever the count updates from a SETUP or OUT transaction
on endpoint 0, the counter register locks and cannot be written
by the CPU. Reading the register unlocks it. This prevents
firmware from overwriting a status update on incoming SETUP
or OUT transactions before firmware has a chance to read the
data. Only endpoint 0 counter register is locked when updated.
The locking mechanism does not apply to the count registers of
other endpoints.
1. Endpoint Mode Register – All the bits are updated (except the
SETUP bit of the endpoint 0 mode register).
2. Counter Registers – All bits are updated.
3. Interrupt – If an interrupt is to be generated as a result of the
transaction, the interrupt flag for the corresponding endpoint
is set at this time. For details on what conditions are required
to generate an endpoint interrupt, refer to Table 39.
4. The contents of the updated endpoint 0 mode and counter
registers are locked, except the SETUP bit of the endpoint 0
mode register which was locked earlier.
Document Number: 38-08001 Rev. *D
Page 34 of 53
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Figure 9. Token/Data Packet Flow Diagram
1. IN Token
Host To Device
Device To Host
Host To Device
D
A
T
A
S
Y
N
C
A
D
D
R
E
N
D
P
C
R
C
5
S
Y
N
C
C
R
C
S
A
Y
C
N
K
C
IN
Data
16
1/0
Hand
Shake
Packet
Token Packet
Data Packet
UPDATE
Host To Device
Device To Host
S
Y
N
C
A
D
D
R
E
N
D
P
C
R
C
5
S
Y
N
C
IN
NAK/STALL
D
Token Packet
Data Packet
H
O
S
T
E
V
I
C
E
UPDATE
2. OUT or SETUP Token without CRC error
Device To Host
Host To Device
Host To Device
O
D
A
S
Y
N
C
U
T
/
Set
up
A
D
D
R
E
N
D
P
C
R
C
5
S
Y
N
C
C
R
C
S
ACK,
Y
T
A
Data
NAK,
N
STAL
C
16
1/0
Hand
Shake
Packet
Token Packet
Data Packet
UPDATE
SETUP
3. OUT or SETUP Token with CRC error
Host To Device
Host To Device
O
U
T
D
A
T
A
1/0
S
Y
N
C
A
D
D
R
E
N
D
P
C
R
C
5
S
Y
N
C
C
R
C
Data
/
Set
up
16
Token Packet
Data Packet
UPDATE only if FIFO is
written
Document Number: 38-08001 Rev. *D
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USB Mode Tables
Table 38. USB Register Mode Encoding
Mode
Disable
Mode Bits SETUP
IN
OUT
Comments
0000
0001
0010
0011
0100
0101
0110
0111
1000
ignore
accept
accept
accept
accept
ignore
ignore
NAK
stall
ignore Ignore all USB traffic to this endpoint
Nak In/Out
NAK Forced from Setup on Control endpoint, from modes other than 0000
check For Control endpoints
Status Out Only
Stall In/Out
stall
stall For Control endpoints
Ignore In/Out
Isochronous Out
Status In Only
Isochronous In
Nak Out
ignore
ignore
ignore For Control endpoints
always For Isochronous endpoints
stall For Control Endpoints
accept TX 0 BYte
ignore TX Count ignore For Isochronous endpoints
ignore
ignore
NAK Is set by SIE on an ACK from mode 1001 (Ack Out)
Ack
1001
1001
ignore
ignore
ignore
ignore
ACK On issuance of an ACK this mode is changed by SIE to 1000 (NAK
stall Out)
Out(STALL[3]=0)
Ack
Out(STALL[3]=1)
Nak Out - Status In
Ack Out - Status In
1010
1011
accept TX 0 BYte NAK Is set by SIE on an ACK from mode 1011 (Ack Out- Status In)
accept TX 0 BYte ACK On issuance of an ACK this mode is changed by SIE to 1010 (NAK
Out - Status In)
Nak In
1100
ignore
NAK
ignore Is set by SIE on an ACK from mode 1101 (Ack In)
Ack
1101
1101
ignore TX Count ignore On issuance of an ACK this mode is changed by SIE to 1100 (NAK
IN(STALL[3]=0)
Ack
ignore
accept
stall
ignore In)
IN(STALL[3]=1)
Nak In - Status Out
Ack In - Status Out
1110
1111
NAK
check Is set by SIE on an ACK from mode 1111 (Ack In - Status Out)
accept TX Count check On issuance of an ACK this mode is changed by SIE to 1110 (NAK
In - Status Out)
Mode
A “Check” on the OUT token column, implies that on receiving
an OUT token the SIE checks to see whether the OUT packet is
of zero length and has a Data Toggle (DTOG) set to ‘1.’ If the
DTOG bit is set and the received OUT Packet has zero length,
the OUT is ACKed to complete the transaction. If either of this
condition is not met the SIE will respond with a STALLL or just
ignore the transaction.
This lists the mnemonic given to the different modes that can be
set in the Endpoint Mode Register by writing to the lower nibble
(bits 0..3). The bit settings for different modes are covered in the
column marked “Mode Bits”. The Status IN and Status OUT
represent the Status stage in the IN or OUT transfer involving the
control endpoint.
A “TX Count” entry in the IN column implies that the SIE transmit
the number of bytes specified in the Byte Count (bits 3..0 of the
Endpoint Count Register) to the host in response to the IN token
received.
Mode Bits
These column lists the encoding for different modes by setting
Bits[3..0] of the Endpoint Mode register. This modes represents
how the SIE responds to different tokens sent by the host to an
endpoint. For instance, if the mode bits are set to “0001” (NAK
IN/OUT), the SIE will respond with an
A “TX0 Byte” entry in the IN column implies that the SIE transmit
a zero length byte packet in response to the IN token received
from the host.
■ ACK on receiving a SETUP token from the host
■ NAK on receiving an OUT token from the host
■ NAK on receiving an IN token from the host
An “Ignore” in any of the columns means that the device will not
send any handshake tokens (no ACK) to the host.
An “Accept” in any of the columns means that the device will
respond with an ACK to a valid SETUP transaction tot he host.
Refer to I2C-compatible Controller on page 22 for more
information on the SIE functioning
Comments
Some Mode Bits are automatically changed by the SIE in
response to certain USB transactions. For example, if the Mode
Bits [3:0] are set to '1111' which is ACK IN-Status OUT mode, the
SIE will change the endpoint Mode Bits [3:0] to NAK IN-Status
OUT mode (1110) after ACK’ing a valid status stage OUT token.
SETUP, IN and OUT
These columns shows the SIE’s response to the host on
receiving a SETUP, IN and OUT token depending on the mode
set in the Endpoint Mode Register.
Document Number: 38-08001 Rev. *D
Page 36 of 53
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The firmware needs to update the mode for the SIE to respond
appropriately. See Table 34 on page 32 for more details on what
modes will be changed by the SIE. A disabled endpoint will
remain disabled until changed by firmware, and all endpoints
reset to the disabled mode (0000). Firmware normally enables
the endpoint mode after a SetConfiguration request.
be placed in the correct mode to function as such. Non-Control
endpoints should not be placed into modes that accept SETUPs.
Note that most modes that control transactions involving an
ending ACK, are changed by the SIE to a corresponding mode
which NAKs subsequent packets following the ACK. Exceptions
are modes 1010 and 1110.
Any SETUP packet to an enabled endpoint with mode set to
accept SETUPs will be changed by the SIE to 0001 (NAKing INs
and OUTs). Any mode set to accept a SETUP will send an ACK
handshake to a valid SETUP token.
Note: The SIE offers an “Ack out–Status in” mode and not an
“Ack out–Nak in” mode. Therefore, if following the status stage
of a Control Write transfer a USB host were to immediately start
the next transfer, the new Setup packet could override the data
payload of the data stage of the previous Control Write.
The control endpoint has three status bits for identifying the
token type received (SETUP, IN, or OUT), but the endpoint must
Properties of
Incoming Packets
Changes to the Internal Register made by the SIE on receiving an incoming packet
from the host
Interrupt
3
2
1
0
Token
count
buffer
dval
DTOG
DVAL
COUNT
Setup
In
Out
ACK
3
2
1
0
Response Int
Byte Count (bits 0..5, Figure 17-4)
Data Valid (bit 6, Figure 17-4)
Endpoint Mode
encoding
SIE’sResponse
to the Host
Received Token
(SETUP/IN/OUT)
Data0/1 (bit7 Figure 17-4)
PID Status Bits
(Bit[7..5], Figure 17-2)
Endpoint Mode bits
Changed by the SIE
The validity of the received data
The quality status of the DMA buffer
The number of received bytes
Acknowledge phase completed
Legend:
TX : transmit
RX : receive
UC : unchanged
TX0 :Transmit 0 length packet
available for Control endpoint only
x: don’t care
The response of the SIE can be summarized as follows:
endpoint in which an ACK is transferred. These registers are
only unlocked by a CPU read of the register, which should be
done by the firmware only after the transaction is complete.
This represents about a 1- µs window in which the CPU is
locked from register writes to these USB registers. Normally
the firmware should perform a register read at the beginning
of the Endpoint ISRs to unlock and get the mode register
information. The interlock on the Mode and Count registers
ensures that the firmware recognizes the changes that the
SIE might have made during the previous transaction. Note
that the setup bit of the mode register is NOT locked. This
means that before writing to the mode register, firmware must
first read the register to make sure that the setup bit is not set
(which indicates a setup was received, while processing the
current USB request). This read will of course unlock the
register. So care must be taken not to overwrite the register
elsewhere.
1. The SIE will only respond to valid transactions, and will ignore
non-valid ones.
2. The SIE will generate an interrupt when a valid transaction is
completed or when the FIFO is corrupted. FIFO corruption
occurs during an OUT or SETUP transaction to a valid internal
address, that ends with a non-valid CRC.
3. An incoming Data packet is valid if the count is < Endpoint
Size + 2 (includes CRC) and passes all error checking;
4. An IN will be ignored by an OUT configured endpoint and visa
versa.
5. The IN and OUT PID status is updated at the end of a
transaction.
6. The SETUP PID status is updated at the beginning of the Data
packet phase.
7. The entire Endpoint 0 mode register and the Count register
are locked to CPU writes at the end of any transaction to that
Document Number: 38-08001 Rev. *D
Page 37 of 53
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Table 39. Details of Modes for Differing Traffic Conditions (see Table 38 for the decode legend)
SETUP (if accepting SETUPs)
Properties of Incoming Packet
Changes made by SIE to Internal Registers and Mode Bits
Mode Bits
token
Setup
Setup
Setup
count
<= 10
> 10
x
buffer
data
junk
dval
valid
x
DTOG
DVAL
COUNT Setup
In
Out
UC
UC
UC
ACK
1
Mode Bits Response
ACK
Intr
yes
yes
yes
See Table 38
See Table 38
See Table 38
updates
1
updates
1
1
1
UC
UC
UC
0
0
0
1
updates updates updates
updates updates
UC
UC
NoChange ignore
NoChange ignore
junk
invalid
0
Properties of Incoming Packet
Changes made by SIE to Internal Registers and Mode Bits
Mode Bits
token
count
buffer
dval
DTOG
DVAL
COUNT Setup
In
Out
ACK
Mode Bits Response
Intr
DISABLED
0
0
0
0
x
x
UC
x
UC
UC
UC
UC
UC
UC
UC
NoChange ignore
no
Nak In/Out
0
0
0
0
0
0
1
1
Out
In
x
x
UC
UC
x
x
UC
UC
UC
UC
UC
UC
UC
UC
UC
1
1
UC
UC
NoChange NAK
NoChange NAK
yes
yes
UC
Ignore In/Out
0
0
1
1
0
0
0
0
Out
In
x
x
UC
UC
x
x
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
NoChange ignore
NoChange ignore
no
no
Stall In/Out
0
0
0
0
1
1
1
1
Out
In
x
x
UC
UC
x
x
UC
UC
UC
UC
UC
UC
UC
UC
UC
1
1
UC
UC
NoChange Stall
NoChange Stall
yes
yes
UC
CONTROL WRITE
Properties of Incoming Packet
Mode Bits token count
Normal Out/premature status In
Changes made by SIE to Internal Registers and Mode Bits
buffer
dval
DTOG
DVAL
COUNT Setup
In
Out
ACK
Mode Bits Response
Intr
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
Out
Out
Out
In
<= 10
data
junk
junk
UC
valid
updates
1
updates UC
UC
UC
UC
1
1
1
1
0
1
0
ACK
yes
yes
yes
yes
> 10
x
updates updates updates UC
1
UC
UC
1
NoChange ignore
NoChange ignore
NoChange TX 0
x
x
invalid
x
updates
UC
0
updates UC
1
UC
UC
UC
UC
NAK Out/premature status In
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
Out
Out
Out
In
<= 10
UC
UC
UC
UC
valid
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
1
1
UC
UC
UC
1
NoChange NAK
NoChange ignore
NoChange ignore
NoChange TX 0
yes
no
> 10
x
UC
UC
UC
x
x
invalid
x
no
yes
Document Number: 38-08001 Rev. *D
Page 38 of 53
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Table 39. Details of Modes for Differing Traffic Conditions (see Table 38 for the decode legend) (continued)
Status In/extra Out
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
Out
Out
Out
In
<= 10
UC
UC
UC
UC
valid
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
1
1
UC
UC
UC
1
0
0
1
1
Stall
yes
no
> 10
x
UC
UC
UC
NoChange ignore
NoChange ignore
NoChange TX 0
x
x
invalid
x
no
yes
CONTROL READ
Properties of Incoming Packet
Mode Bits token count
Normal In/premature status Out
Changes made by SIE to Internal Registers and Mode Bits
buffer
dval
DTOG
DVAL
COUNT Setup
In
Out
ACK
Mode Bits Response
Intr
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Out
Out
Out
Out
Out
In
2
UC
UC
UC
UC
UC
UC
valid
valid
valid
x
1
1
updates UC
updates UC
updates UC
UC
UC
UC
UC
UC
1
1
1
NoChange ACK
yes
yes
yes
no
2
0
1
1
UC
UC
UC
UC
1
0
0
0
0
1
1
1
1
Stall
Stall
!=2
> 10
x
updates
UC
1
1
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
NoChange ignore
NoChange ignore
invalid
x
UC
no
x
UC
1
1
1
0
ACK (back)
yes
Nak In/premature status Out
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
Out
Out
Out
Out
Out
In
2
UC
UC
UC
UC
UC
UC
valid
valid
valid
x
1
1
updates UC
updates UC
updates UC
UC
UC
UC
UC
UC
1
1
1
NoChange ACK
yes
yes
yes
no
2
0
1
1
UC
UC
UC
UC
UC
0
0
0
0
1
1
1
1
Stall
Stall
!=2
> 10
x
updates
UC
1
1
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
NoChange ignore
NoChange ignore
NoChange NAK
invalid
x
UC
no
x
UC
yes
Status Out/extra In
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
Out
Out
Out
Out
Out
In
2
UC
UC
UC
UC
UC
UC
valid
valid
valid
x
1
1
updates UC
updates UC
updates UC
UC
UC
UC
UC
1
1
1
NoChange ACK
yes
yes
yes
no
2
0
1
1
UC
UC
UC
UC
UC
0
0
0
0
1
1
1
1
Stall
Stall
!=2
> 10
x
updates
UC
1
1
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
NoChange ignore
NoChange ignore
invalid
x
UC
no
x
UC
1
0
0
1
1
Stall
yes
OUT ENDPOINT
Properties of Incoming Packet
Mode Bits token count
Changes made by SIE to Internal Registers and Mode Bits
DTOG DVAL COUNT Setup In Out ACK
buffer
dval
Mode Bits Response
Intr
Document Number: 38-08001 Rev. *D
Page 39 of 53
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Table 39. Details of Modes for Differing Traffic Conditions (see Table 38 for the decode legend) (continued)
Normal Out/erroneous In
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
Out
Out
Out
In
<= 10
data
junk
junk
UC
valid
updates
1
updates UC
UC
UC
UC
UC
UC
UC
UC
UC
1
1
0
0
0
ACK
yes
yes
yes
no
> 10
x
updates updates updates UC
UC
UC
UC
NoChange ignore
NoChange ignore
NoChange ignore
x
x
invalid
x
updates
UC
0
updates UC
UC
UC
UC
(STALL[3] = 0)
NoChange Stall
(STALL[3] = 1)
1
0
0
1
In
x
UC
x
UC
UC
UC
UC
UC
UC
UC
no
NAK Out/erroneous In
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
Out
Out
Out
In
<= 10
UC
UC
UC
UC
valid
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
1
UC
UC
UC
UC
NoChange NAK
NoChange ignore
NoChange ignore
NoChange ignore
yes
no
> 10
x
UC
UC
UC
x
x
invalid
x
no
no
Isochronous endpoint (Out)
0
0
1
1
0
0
1
1
Out
In
x
x
updates updates updates updates updates UC
UC
UC
1
1
NoChange RX
yes
no
UC
x
UC
UC
UC
UC
UC
UC
NoChange ignore
IN ENDPOINT
Properties of Incoming Packet
Changes made by SIE to Internal Registers and Mode Bits
Mode Bits
token
count
buffer
UC
dval
DTOG
DVAL
COUNT Setup
In
Out
UC
UC
UC
ACK
UC
UC
1
Mode Bits Response
Intr
no
Normal In/erroneous Out
1
1
1
1
1
1
0
0
0
1
1
1
Out
Out
In
x
x
x
x
x
x
UC
UC
UC
UC
UC
UC
UC
UC
UC
UC
1
NoChange ignore
(STALL[3] = 0)
UC
UC
UC
NoChange stall
(STALL[3] = 1)
no
UC
UC
UC
1
1
0
0
ACK (back)
yes
NAK In/erroneous Out
1
1
1
1
0
0
0
0
Out
In
x
x
UC
UC
x
x
UC
UC
UC
UC
UC
UC
UC
UC
UC
1
UC
UC
UC
UC
NoChange ignore
NoChange NAK
no
yes
Isochronous endpoint (In)
0
1
1
1
1
1
1
Out
In
x
x
UC
UC
x
x
UC
UC
UC
UC
UC
UC
UC
UC
UC
1
UC
UC
UC
UC
NoChange ignore
NoChange TX
no
0
yes
Note:
3. STALL bit is bit 7 of the USB Non-Control Device Endpoint Mode registers. For more information, refer to Sec.
Document Number: 38-08001 Rev. *D
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Register Summary
Address
0x00
Register Name
Bit 7
P0.7
P1.7
P2.7
P3.7
Bit 6
P0.6
P1.6
P2.6
P3.6
Bit 5
P0.5
P1.5
P2.5
P3.5
Bit 4
P0.4
P1.4
P2.4
P3.4
Bit 3
P0.3
P1.3
P2.3
P3.3
Bit 2
P0.2
P1.2
P2.2
P3.2
Bit 1
P0.1
P1.1
P2.1
P3.1
Bit 0
P0.0
P1.0
P2.0
P3.0
Read/Write/Both/- Default/Reset
Port 0 Data
Port 1 Data
Port 2 Data
Port 3 Data
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
wwwwwwww
11111111
11111111
11111111
11111111
00000000
0x01
0x02
0x03
0x04
Port 0 Interrupt Enable P0.7 Intr P0.6 Intr P0.5 Intr P0.4 Intr P0.3 Intr P0.2 Intr P0.1 Intr P0.0 Intr
Enable Enable Enable Enable Enable Enable Enable Enable
0x05
0x06
0x07
0x08
Port 1 Interrupt Enable P1.7 Intr P1.6 Intr P1.5 Intr P1.4 Intr Reserved P1.2 Intr P1.1 Intr P1.0 Intr
Enable Enable Enable Enable Enable Enable Enable
wwwwwwww
wwwwwwww
wwwwwwww
bbbbbbbb
00000000
00000000
00000000
00000000
Port 2 Interrupt Enable P2.7 Intr P2.6 Intr P2.5 Intr P2.4 Intr P2.3 Intr Reserved Reserved Reserved
Enable Enable Enable Enable Enable
Port 3 Interrupt Enable Reserved Reserved Reserved Reserved Reserved Reserved P3.1 Intr P3.0 Intr
Enable
Enable
GPIO Configuration
Port 3
Port 3
Port 2
Port 2
Port 1
Port 1
Port 0
Port 0
Config Bit Config Bit Config Bit Config Bit Config Bit Config Bit Config Bit Config Bit
1
0
1
0
1
0
1
0
0x09
HAPI/I2C Configuration
I2C
Position
Reserved Reserved Reserved Reserved Reserved I2C Port Reserved
Width
bbbbbbbb
00000000
0x10
0x11
0x12
0x13
USB Device Address A Device
Device
Device
Device
Device
Device
Device
Device
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
00000000
00000000
00000000
00000000
Address A Address A Address A Address A Address A Address A Address A Address A
Enable
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EP A0 Counter
Register
Data 0/1 Data Valid
Toggle
Byte
Count
Bit 5
Byte
Count
Bit 4
Byte
Count
Bit 3
Byte
Count
Bit 2
Byte
Count
Bit 1
Byte
Count
Bit 0
EP A0 Mode Register Endpoint0 Endpoint0 Endpoint0
SETUP IN OUT
Received Received Received
ACK
Mode Bit 3 Mode Bit 2 Mode Bit 1 Mode Bit 0
EP A1 Counter
Register
Data 0/1 Data Valid
Toggle
Byte
Count
Bit 5
Byte
Count
Bit 4
Byte
Count
Bit 3
Byte
Count
Bit 2
Byte
Count
Bit 1
Byte
Count
Bit 0
0x14
0x15
EP A1 Mode Register
STALL
-
-
ACK
Mode Bit 3 Mode Bit 2 Mode Bit 1 Mode Bit 0
bbbbbbbb
bbbbbbbb
00000000
00000000
EP A2 Counter
Register
Data 0/1 Data Valid
Toggle
Byte
Count
Bit 5
Byte
Count
Bit 4
Byte
Count
Bit 3
Byte
Count
Bit 2
Byte
Count
Bit 1
Byte
Count
Bit 0
0x16
EP A2 Mode Register
STALL
-
-
ACK
Mode Bit 3 Mode Bit 2 Mode Bit 1 Mode Bit 0
bbbbbbbb
00000000
Document Number: 38-08001 Rev. *D
Page 41 of 53
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CY7C64013C
CY7C64113C
Register Summary (continued)
Address
Register Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read/Write/Both/- Default/Reset
0x1F
USB Status and Control Endpoint Endpoint
D+
D–
Bus
Control
Bit 2
Control
Bit 1
Control
Bit 0
bbrrbbbb
-0xx0000
Size
Mode
Upstream Upstream Activity
0x20
0x21
Global Interrupt Enable Reserved
I2C
GPIO
Reserved USB Hub 1.024-ms
128-s USB Bus
-bbbbbbb
-0000000
Interrupt Interrupt
Enable Enable
Interrupt Interrupt Interrupt RESET
Enable
EPB0
Enable
EPA2
Enable
Interrupt
Enable
Endpoint Interrupt
Enable
Reserved Reserved Reserved
EPB1
EPA1
EPA0
---bbbbb
---00000
Interrupt Interrupt Interrupt Interrupt Interrupt
Enable Enable Enable Enable Enable
0x24
0x25
Timer (LSB)
Timer (MSB)
Timer Bit 7 Timer Bit 6 Timer Bit 5 Timer Bit 4 Timer Bit 3 Timer Bit 2 Timer Bit 1 Timer Bit 0
rrrrrrrr
----rrrr
00000000
----0000
Reserved Reserved Reserved Reserved Timer Bit Timer Bit Time Bit 9 Timer Bit 8
11
10
x2
0x26
0x28
WDT Clear
I2C Control and Status
x
x6
MSTR Continue/
Mode Busy
x
x
x 3
x
x
I2C
Enable
wwwwwwww
bbbbbbbb
xxxxxxxx
Xmit
Mode
ACK
Addr
ARB Lost/ Received
Restart Stop
00000000
0x29
0x30
0x31
I2C Data
I2C Data 7 I2C Data 6 I2C Data 5 I2C Data 4 I2C Data 3 I2C Data 2 I2C Data 1 I2C Data 0
bbbbbbbb
rrrrrrrr
xxxxxxxx
00000000
----0000
DAC Data
Timer Bit 7 Timer Bit 6 Timer Bit 5 Timer Bit 4 Timer Bit 3 Timer Bit 2 Timer Bit 1 Timer Bit 0
DAC Interrupt Enable) Reserved Reserved Reserved Reserved Timer Bit Timer Bit Time Bit 9 Timer Bit 8
----rrrr
11
10
0x32
DAC Interrupt Polarity
DAS Isink
0x38-
0x3F
x
x6
x
x
x 3
x2
x
x
wwwwwwww
0x40
0x41
Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
bbbbbbbb
bbbbbbbb
00000000
00000000
EP A3 Counter Register Data 0/1 Data Valid
Toggle
Byte
Byte
Byte
Byte
Byte
Byte
Count Bit 5 Count Bit 4 Count Bit 3 Count Bit 2 Count Bit 1 Count Bit 0
0x42
0x43
0x44
EP A3 Mode Register Endpoint 0 Endpoint 0 Endpoint 0
SETUP IN OUT
Received Received Received
ACK
Mode Bit 3 Mode Bit 2 Mode Bit 1 Mode Bit 0
bbbbbbbb
bbbbbbbb
bbbbbbbb
00000000
00000000
00000000
EP A4 Counter Register Data 0/1 Data Valid
Byte
Count
Bit 5
Byte
Count
Bit 4
Byte
Count
Bit 3
Byte
Count
Bit 2
Byte
Count
Bit 1
Byte
Count
Bit 0
Toggle
EP A4 Mode Register
STALL
-
-
ACK
Mode Bit 3 Mode Bit 2 Mode Bit 1 Mode Bit 0
Document Number: 38-08001 Rev. *D
Page 42 of 53
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CY7C64013C
CY7C64113C
Register Summary (continued)
Address
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0xFF
Register Name
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read/Write/Both/- Default/Reset
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
rbbbbrbb
00000000
00000000
00000000
00000000
--000000
Reserved
Reserved
Reserved
Reserved
Reserved
00000000
00000000
00000000
00000000
00000000
00000000
00010001
Reserved
Reserved
Reserved
Reserved
Reserved
Process Status & Control
IRQ
Pending
Watchdog USB Bus Power-On Suspend Interrupt Reserved
Reset
Run
Reset
Interrupt
Reset
Enable
Sense
Note:
W: Write
R: Read
B: Read and Write
Document Number: 38-08001 Rev. *D
Page 43 of 53
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CY7C64013C
CY7C64113C
Sample Schematic
3.3V Regulator
Vref
OUT
IN
2.2 F
2.2 F
Vref
0V
1.5K
(R
)
UUP
USB-B
Vbus
D–
D+
GND
.01 F
.01 F
Vbus
22x2(R
)
ext
0V
0V
SHELL
D0–
D0+
4.7 nF
Optional
250VAC
XTALO
XTALI
10M
6.000 MHz
GND
GND
Vpp
0V
0V
Document Number: 38-08001 Rev. *D
Page 44 of 53
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CY7C64013C
CY7C64113C
Power Dissipation..................................................... 500 mW
Static discharge voltage (MIL-STD-883, M 3015)... > 2000 V
Latch up current..................................................... > 200 mA
Absolute Maximum Ratings
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with power applied ....... 0 °C to +70 °C
Supply voltage on VCC relative to VSS..........–0.5 V to +7.0 V
DC input voltage..................................–0.5 V to VCC + 0.5 V
Max Output Sink Current into Port 0, 1, 2, 3, and
DAC[1:0] Pins ............................................................ 60 mA
Max Output Sink Current into DAC[7:2] Pins ............. 10 mA
DC Voltage Applied to Outputs in
High Z State.........................................–0.5 V to VCC + 0.5 V
Electrical Characteristics
fOSC = 6 MHz; Operating Temperature = 0 °C to 70 °C, VCC = 4.0 V to 5.25 V
Parameter
Description
General
Conditions
Min
Max
Unit
VREF
Vpp
ICC
Reference Voltage
3.3 V ±5%
3.15
–0.4
–
3.45
0.4
50
50
30
1
V
Programming Voltage (disabled)
VCC Operating Current
V
No GPIO source current
mA
µA
mA
µA
ISB1
Iref
Supply Current—Suspend Mode
VREF Operating Current
–
Note 5
–
Iil
Input Leakage Current
Any pin
–
USB Interface
Vdi
Differential Input Sensitivity
Differential Input Common Mode Range
Single Ended Receiver Threshold
Transceiver Capacitance
| (D+)–(D–) |
0.2
0.8
0.8
–
–
V
V
Vcm
Vse
Cin
2.5
2.0
20
10
21
V
pF
µA
Ilo
Hi-Z State Data Line Leakage
External USB Series Resistor
0 V < Vin < 3.3 V
–10
19
Rext
RUUP
In series with each USB pin
External Upstream USB Pull-up Resistor 1.5 k ±5%, D+ to VREG
1.425 1.575
k
Power On Reset
[4]
tvccs
VCC Ramp Rate
USB Upstream
Linear ramp 0V to VCC
0
100
ms
VUOH
VUOL
ZO
Static Output High
15 k ±5% to Gnd
1.5 k ±5% to VREF
Including Rext Resistor
2.8
–
3.6
0.3
44
V
V
Static Output Low
USB Driver Output Impedance
General Purpose I/O (GPIO)
Pull-up Resistance (typical 14 k
Input Threshold Voltage
28
Rup
VITH
VH
8.0
20%
2%
–
24.0
40%
8%
k
All ports, LOW to HIGH edge
All ports, HIGH to LOW edge
IOL = 3 mA
VCC
VCC
Input Hysteresis Voltage
Port 0,1,2,3 Output Low Voltage
VOL
0.4
2.0
V
V
IOL = 8 mA
VOH
Output High Voltage
IOH = 1.9 mA (all ports 0,1,2,3)
2.4
–
V
Notes
4. Power-on Reset occurs whenever the voltage on V is below approximately 2.5 V.
CC
5. This is based on transitions every 2 full-speed bit times on average.
Document Number: 38-08001 Rev. *D
Page 45 of 53
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CY7C64013C
CY7C64113C
Electrical Characteristics (continued)
fOSC = 6 MHz; Operating Temperature = 0 °C to 70 °C, VCC = 4.0 V to 5.25 V
Parameter
Description
DAC Interface
Conditions
Min
Max
Unit
Rup
DAC Pull-up Resistance (typical 14 k
DAC[7:2] Sink current (0)
DAC[7:2] Sink current (F)
DAC[1:0] Sink current (0)
DAC[1:0] Sink current (F)
Programmed Isink Ratio: max/min
Tracking Ratio DAC[1:0] to DAC[7:2]
DAC Sink Current
8.0
0.1
0.5
1.6
8
24.0
0.3
1.5
4.8
24
k
mA
mA
mA
mA
Isink0(0)
Isink0(F)
Isink1(0)
Isink1(F)
Irange
Vout = 2.0 V DC
Vout = 2.0 V DC
Vout = 2.0 V DC
Vout = 2.0 V DC
Vout = 2.0 V DC[6]
Vout = 2.0 V[7]
Vout = 2.0 V DC
DAC Port[8]
4
6
Tratio
14
1.6
–
22
IsinkDAC
Ilin
4.8
0.6
mA
Differential Nonlinearity
LSB
Switching Characteristics
(fOSC = 6.0 MHz)
Parameter
Description
Min
Max
Unit
Clock Source
fOSC
tcyc
tCH
tCL
Clock Rate
6 ±0.25%
166.25
–
MHz
ns
Clock Period
167.08
Clock HIGH time
0.45 tCYC
0.45 tCYC
–
–
ns
Clock LOW time
ns
USB Full Speed Signaling[9]
trfs
Transition Rise Time
4
20
20
111
–
ns
ns
tffs
Transition Fall Time
4
90
trfmfs
tdratefs
Rise / Fall Time Matching; (tr/tf)
Full Speed Date Rate
%
12 ±0.25%
Mb/s
DAC Interface
Current Sink Response Time
HAPI Read Cycle Timing
tsink
–
0.8
µs
tRD
Read Pulse Width
15
–
–
ns
ns
ns
ns
tOED
tOEZ
tOEDR
OE LOW to Data Valid[10, 11]
OE HIGH to Data High Z[11]
OE LOW to Data_Ready Deasserted[10, 11]
40
20
60
–
0
HAPI Write Cycle Timing
tWR
Write Strobe Width
15
5
–
–
ns
ns
ns
ns
tDSTB
tSTBZ
tSTBLE
Data Valid to STB HIGH (Data Set-up Time)[11]
STB HIGH to Data High Z (Data Hold Time)[11]
STB LOW to Latch_Empty Deasserted[10, 11]
Timer Signals
15
0
–
50
twatch
Watchdog Timer Period
8.192
14.336
ms
Notes:
6. Irange: I
(15)/ I
(0) for the same pin.
sinkn
sinkn
7.
8.
T
= I
[1:0](n)/I
[7:2](n) for the same n, programmed.
ratio
sink1
sink0
I
measured as largest step size vs. nominal according to measured full scale and zero programmed values.
lin
9. Per Table 7-6 of revision 1.1 of USB specification.
10. For 25-pF load.
11. Assumes chip select CS is asserted (LOW).
Document Number: 38-08001 Rev. *D
Page 46 of 53
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CY7C64013C
CY7C64113C
Figure 10. Clock Timing
tCYC
tCH
CLOCK
tCL
Figure 11. USB Data Signal Timing
tr
tr
D
D
90%
90%
10%
10%
Figure 12. HAPI Read by External Interface from USB Microcontroller
Interrupt Generated
Int
CS (P2.6, input)
OE (P2.5, input)
DATA (output)
tRD
D[23:0]
tOED
tOEZ
STB (P2.4, input)
tOEDR
(Ready)
DReadyPin (P2.3, output)
(Shown for DRDY Polarity=0)
Internal Write
Internal Addr
Port0
Document Number: 38-08001 Rev. *D
Page 47 of 53
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CY7C64013C
CY7C64113C
Figure 13. HAPI Write by External Device to USB Microcontroller
Interrupt Generated
Int
CS (P2.6, input)
STB (P2.4, input)
tWR
tSTBZ
DATA (input)
D[23:0]
tDSTB
OE (P2.5, input)
tSTBLE
LEmptyPin (P2.2, output)
(Shown for LEMPTY Polarity=0)
(not empty)
Internal Read
Internal Addr
Port0
Ordering Information
Operating
Range
Ordering Code
CY7C64013C-SXC
CY7C64013C-SXCT
PROM Size
Package Type
28-pin (300-Mil) SOIC (Pb-free)
8 KB
8 KB
Commercial
Commercial
28-pin (300-Mil) SOIC - Tape Reel (Pb-free)
Ordering Code Definitions
CY 7C64013C -
S
X
C
X
X = blank or T (blank = Bulk; T = Tape and Reel)
Temperature Grade: C = Commercial
X = Pb-free
Package Type: S = 28-pin (300-Mil) SOIC
7C64013C = Part Identifier
Company ID: CY = Cypress
Document Number: 38-08001 Rev. *D
Page 48 of 53
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CY7C64013C
CY7C64113C
Package Diagrams
Figure 14. 48-pin SSOP
51-85061 *D
Figure 15. 28-pin (300 MIL) PDIP
51-85014 *E
Document Number: 38-08001 Rev. *D
Page 49 of 53
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CY7C64013C
CY7C64113C
Figure 16. 28-pin SOIC (.713 × .300 × .0932 INCHES)
51-85026 *F
Document Number: 38-08001 Rev. *D
Page 50 of 53
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CY7C64013C
CY7C64113C
Acronyms
Document Conventions
Units of Measure
Acronym
ADC
CMOS
CPU
DAC
EMI
Description
analog-to-digital converter
Symbol
ns
Unit of Measure
complementary metal oxide semiconductor
central processing unit
digital-to-analog converter
electromagnetic interference
general-purpose input/output
Hardware Assisted Parallel Interface
light-emitting diode
nano seconds
milli seconds
micro seconds
kilo ohms
ms
µs
k
GPIO
HAPI
LED
ohms
V
Volts
µA
mA
cm
mm
kHz
MHz
pF
micro Amperes
milli Amperes
centi meter
milli meter
kilo Hertz
LSB
least significant bit
MSB
I/O
most significant bit
input/output
OE
output enable
PCB
printed circuit board
Mega Hertz
pico Farad
degree Celcius
percent
PDIP
PLL
plastic dual in-line package
phase-locked loop
°C
POR
PROM
RAM
SIE
Power-On Reset
%
programmable read-only memory
random access memory
serial interface engine
small-outline integrated circuit
shrink small-outline package
fine-pitch ball grid array
Universal Serial Bus
mW
W
milli Watts
Watts
SOIC
SSOP
FBGA
USB
WDT
Watchdog Timer
Document Number: 38-08001 Rev. *D
Page 51 of 53
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CY7C64013C
CY7C64113C
Document History Page
Document Title: CY7C64013C, CY7C64113C Full-Speed USB (12-Mbps) Function
Document Number: 38-08001
Orig. of
REV.
**
ECN NO. Issue Date
Change
Description of Change
109962
129715
12/16/01
02/05/04
SZV
Change from Spec number: 38-00626 to 38-08001
*A
MON
Added register bit definitions
Added default bit state of each register
Corrected the Schematic (location of the Pull up on D+)
Added register summary
Modified tables 19-1 and 19-2
Provided more explanation regarding locking/unlocking mechanism of the
mode register.
*B
*C
429099
See ECN
03/22/10
TYJ
Changed part numbers to the ‘C’ types. Included ‘Cypress Perform’ logo.
Updated part numbers in the Ordering section.
2897159
XUT
Removed inactive parts CY7C64013C-PXC and CY7C64113C-PVXC from
the Ordering information table.
Updated package diagrams.
*D
3190495
03/08/2011
NXZ
Added Ordering Code Definitions.
Updated Package Diagrams.
Added Acronyms and Units of Measure.
Updated in new template.
Document Number: 38-08001 Rev. *D
Page 52 of 53
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CY7C64013C
CY7C64113C
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
PSoC Solutions
Clocks & Buffers
Interface
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 5
Lighting & Power Control
Memory
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2001-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-08001 Rev. *D
Revised March 8, 2011
Page 53 of 53
All products and company names mentioned in this document may be the trademarks of their respective holders.
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