CY7C343-30JIT [CYPRESS]
OT PLD, 30ns, CMOS, PQCC44, PLASTIC, LCC-44;
| 型号： | CY7C343-30JIT |
| 厂家： | 
CYPRESS |
| 描述： | OT PLD, 30ns, CMOS, PQCC44, PLASTIC, LCC-44 时钟 输入元件 可编程逻辑 |
| 文件： | 总19页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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CY7C343
64-Macrocell MAX® EPLD
Features
Functional Description
• 64 MAX® macrocells in four LABs
• Eightdedicated inputs, 24 bidirectional I/O pins
• Programmable interconnect array
The CY7C343 is a high-performance, high-density erasable
programmable logic device, available in 44-pin PLCC and
HLCC packages.
The CY7C343 contains 64 highly flexible macrocells and 128
expander product terms. These resources are divided into four
Logic Array Blocks (LABs) connected through the Program-
mable Inter-connect Array (PIA). There are eight input pins,
one that doubles as a clock pin when needed. The CY7C343
also has 28 I/O pins, each connected to a macrocell (six for
LABs A and C, and eight for LABs B and D). The remaining 36
macrocells are used for embedded logic.
• 0.8-micron double-metal CMOS EPROM technology
• Available in 44-pin HLCC, PLCC
• Lowest power MAX device
The CY7C343 is excellent for a wide range of both
synchronous and asynchronous applications.
Logic Block Diagram 9 INPUT
INPUT 35
11 INPUT
12 INPUT
13 INPUT
INPUT/CLK34
INPUT 33
INPUT 31
DEDICATED INPUTS
SYSTEM CLOCK
LAB A
LAB D
MACROCELL56
2
4
5
6
7
8
MACROCELL1
MACROCELL2
MACROCELL3
MACROCELL4
MACROCELL5
MACROCELL6
1
MACROCELL55
MACROCELL54
MACROCELL53
MACROCELL52
MACROCELL51
MACROCELL50
MACROCELL49
44
42
41
40
39
38
37
I/O PINS
I/O PINS
MACROCELLS 7–16
MACROCELLS 57–64
P
I
A
LAB B
LAB C
MACROCELL38
MACROCELL37
MACROCELL36
MACROCELL35
MACROCELL34
MACROCELL33
MACROCELL17
MACROCELL18
MACROCELL19
MACROCELL20
MACROCELL21
MACROCELL22
MACROCELL23
MACROCELL24
30
29
28
27
26
24
15
16
17
18
19
20
22
23
I/O PINS
I/O PINS
MACROCELLS 39–48
MACROCELLS 25–32
(3, 14, 25, 36)
(10, 21, 32, 43)
V
CC
GND
Selection Guide
7C343-20
7C343-25
7C343-30
30
7C343-35
35
Unit
Maximum Access Time
20
25
ns
Maximum Operating Current
Commercial
135
225
225
125
200
200
135
225
225
125
200
200
135
135
mA
Military
225
225
Industrial
225
225
Maximum Standby Current
Commercial
Military
125
125
mA
200
200
Industrial
200
200
Cypress Semiconductor Corporation
Document #: 38-03015 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised April 22, 2004
USE ULTRA37000™ FOR
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CY7C343
Pin Configuration
HLCC, PLCC
Top View
6
5
4
3
2
1
44 43 42 41 40
I/O
I/O
I/O
V
I/O
I/O
7
39
38
37
8
INPUT
GND
9
CC
10
11
12
13
14
15
16
17
36
35
INPUT
INPUT
INPUT
INPUT
INPUT/CLK
34
33
INPUT
GND
V
CC
32
31
7C343
INPUT
I/O
I/O
I/O
I/O
30
29
I/O
18 19 20 21 22 23 24 25 26 27 28
Document #: 38-03015 Rev. *B
Page 2 of 19
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CY7C343
Programmable Interconnect Array
Timing Considerations
The Programmable Interconnect Array (PIA) solves inter-
connect limitations by routing only the signals needed by each
logic array block. The inputs to the PIA are the outputs of every
macrocell within the device and the I/O pin feedback of every
pin on the device.
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum
expander delay tEXP to the overall delay. Similarly, there is an
additional tPIA delay for an input from an I/O pin when
compared to a signal from a straight input pin.
Unlike masked or programmable gate arrays, which induce
variable delay dependent on routing, the PIA has a fixed delay.
This eliminates undesired skews among logic signals, which
may cause glitches in internal or external logic. The fixed
delay, regardless of programmable interconnect array config-
uration, simplifies design by ensuring that internal signal
skews or races are avoided. The result is simpler design imple-
mentation, often in a single pass, without the multiple internal
logic placement and routing iterations required for a program-
mable gate array to achieve design timing objectives.
When calculating synchronous frequencies, use tS1 if all inputs
are on the input pins. tS2 should be used if data is applied at
an I/O pin. If tS2 is greater than tCO1, 1/tS2 becomes the limiting
frequency in the data path mode unless 1/(tWH + tWL) is less
than 1/tS2
.
When expander logic is used in the data path, add the appro-
priate maximum expander delay, tEXP to tS1. Determine which
of 1/(tWH + tWL), 1/tCO1, or 1/(tEXP + tS1) is the lowest
frequency. The lowest of these frequencies is the maximum
data path frequency for the synchronous configuration.
When calculating external asynchronous frequencies, use
tAS1 if all inputs are on dedicated input pins. If any data is
applied to an I/O pin, tAS2 must be used as the required set-up
Timing Delays
Timing delays within the CY7C343 may be easily determined
using Warp®, Warp Professional™, or Warp Enterprise™
software. The CY7C343 has fixed internal delays, allowing the
user to determine the worst case timing delays for any design.
time. If (tAS2 + tAH) is greater than tACO1, 1/(tAS2 + tAH
)
becomes the limiting frequency in the data path mode unless
1/(tAWH + tAH) is less than 1/(tAS2 + tAH).
When expander logic is used in the data path, add the appro-
priate maximum expander delay, tEXP to tAS1. Determine
which of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is the
lowest frequency. The lowest of these frequencies is the
maximum data path frequency for the asynchronous configu-
ration.
Design Recommendations
Operation of the devices described herein with conditions
above those listed under “Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this data sheet is not implied. Exposure to absolute maximum
ratings conditions for extended periods of time may affect
device reliability. The CY7C343 contains circuitry to protect
device pins from high static voltages or electric fields;
however, normal precautions should be taken to avoid
applying any voltage higher than maximum rated voltages.
The parameter tOH indicates the system compatibility of this
device when driving other synchronous logic with positive
input hold times, which is controlled by the same synchronous
clock. If tOH is greater than the minimum required input hold
time of the subsequent synchronous logic, then the devices
are guaranteed to function properly with
a common
synchronous clock under worst-case environmental and
supply voltage conditions.
For proper operation, input and output pins must be
constrained to the range GND < (VIN or VOUT) < VCC. Unused
inputs must always be tied to an appropriate logic level (either
VCC or GND). Each set of VCC and GND pins must be
connected together directly at the device. Power supply
decoupling capacitors of at least 0.2 µF must be connected
between VCC and GND. For the most effective decoupling,
each VCC pin should be separately decoupled to GND, directly
at the device. Decoupling capacitors should have good
frequency response, such as monolithic ceramic types.
The parameter tAOH indicates the system compatibility of this
device when driving subsequent registered logic with a
positive hold time and using the same clock as the CY7C343.
In general, if tAOH is greater than the minimum required input
hold time of the subsequent logic (synchronous or
asynchronous), then the devices are guaranteed to function
properly under worst-case environmental and supply voltage
conditions, provided the clock signal source is the same. This
also applies if expander logic is used in the clock signal path
of the driving device, but not for the driven device. This is due
to the expander logic in the second device’s clock signal path
adding an additional delay (tEXP), causing the output data from
the preceding device to change prior to the arrival of the clock
signal at the following device’s register.
Document #: 38-03015 Rev. *B
Page 3 of 19
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CY7C343
EXPANDER
DELAY
t
EXP
REGISTER
LOGIC ARRAY
OUTPUT
DELAY
t
t
CONTROLDELAY
CLR
INPUT
t
INPUT/
OUTPUT
LAC
PRE
t
OD
XZ
ZX
INPUT
DELAY
t
LOGIC ARRAY
DELAY
t
t
RD
t
RSU
t
t
COMB
LATCH
t
t
IN
RH
t
LAD
SYSTEM CLOCK DELAY t
ICS
PIA
CLOCK
DELAY
DELAY
t
t
PIA
IC
FEEDBACK
DELAY
t
FD
I/O DELAY
t
IO
Figure 1. CY7C343 Internal Timing Model
Document #: 38-03015 Rev. *B
Page 4 of 19
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CY7C343
DC Output Current, per Pin ......................–25 mA to +25 mA
DC Input Voltage[1] .........................................–3.0V to +7.0V
DC Program Voltage..................................................... 13.0V
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage........................................... > 1100V
(per MIL–STD–883, method 3015)
Storage Temperature ................................ –65°C to +150°C
Ambient Temperature with
Power Applied.................................................. 0°C to +70°C
Maximum Junction Temperature
(Under Bias).................................................................150°C
Supply Voltage to Ground Potential...............–2.0V to +7.0V
Operating Range[2]
Range
Commercial
Industrial
Military
Ambient Temperature
0°C to +70°C
–40°C to +85°C
VCC
5V ±5%
5V ±10%
5V ±10%
Maximum Power Dissipation...................................2500 mW
–55°C to +125°C (Case)
DC VCC or GND Current............................................500 mA
Electrical Characteristics Over the Operating Range[3]
Parameter
VOH
Description
Output HIGH Voltage
Test Conditions
VCC = Min., IOH = –4.0 mA
Min.
Max.
Unit
2.4
V
V
VOL
VIH
VIL
IIX
Output LOW Voltage
Input HIGH Level
VCC = Min., IOL = 8 mA
0.45
VCC + 0.3
0.8
2.2
–0.3
–10
–40
–30
V
Input LOW Level
V
Input Current
GND < VIN < VCC
+10
µA
µA
mA
mA
mA
mA
mA
ns
IOZ
IOS
ICC1
Output Leakage Current
Output Short Circuit Current
Power Supply Current (Standby)
VO = VCC or GND
VCC = Max., VOUT = 0.5V[4, 5]
+40
–90
VI = VCC or GND
(No Load)
Commercial
125
Military/Industrial
Commercial
200
ICC2
Power Supply Current[6]
VI = VCC or GND (No
Load) f = 1.0 MHz[5, 6]
135
Military/Industrial
225
tR
tF
Recommended Input Rise Time
Recommended Input Fall Time
100
100
ns
Capacitance[7]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
VIN = 2V, f = 1.0 MHz
VOUT = 2.0V, f = 1.0 MHz
Max.
10
Unit
pF
CIN
COUT
10
pF
AC Test Loads and Waveforms[7]
R1 464Ω
R1 464Ω
5V
5V
ALL INPUT PULSES
90%
OUTPUT
OUTPUT
3.0V
GND
90%
10%
10%
R2
250Ω
R2
250Ω
50 pF
5 pF
< 6 ns
< 6 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT (commercial/military)
163 Ω
OUTPUT
1.75V
Notes:
1. Minimum DC input is –0.3V. During transitions, the inputs may undershoot to –2.0V for periods less than 20 ns.
2. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
3. Typical values are for T = 25°C and V = 5V.
A
CC
4. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. V
test problems caused by tester ground degradation.
= 0.5V has been chosen to avoid
OUT
5. Guaranteed but not 100% tested.
6. Measured with device programmed as a 16-bit counter in each LAB. This parameter is tested periodically by sampling production material.
7. Part (a) in AC Test Load and Waveforms is used for all parameters except t and t , which is used for part (b) in AC Test Load and Waveforms. All external
ER
XZ
timing parameters are measured referenced to external pins of the device.
Document #: 38-03015 Rev. *B
Page 5 of 19
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CY7C343
External Synchronous Switching Characteristics Over Operating Range [7]
7C343-20
7C343-25
Parameter
tPD1
Description
Dedicated Input to Combinatorial Output Delay[8]
Min. Max. Min. Max. Unit
Com’l/Ind
Mil
20
20
32
32
30
30
42
42
20
20
20
20
12
12
25
25
25
39
39
37
37
51
51
25
25
25
25
14
14
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPD2
tPD3
tPD4
tEA
I/O Input to Combinatorial Output Delay[9]
Com’l/Ind
Mil
Dedicated Input to Combinatorial Output Delay with Expander Com’l/Ind
Delay[10]
Mil
I/O Input to Combinatorial Output Delay with Expander Delay[5, Com’l/Ind
11]
Input to Output Enable Delay[5, 8]
Input to Output Disable Delay[5, 8]
Synchronous Clock Input to Output Delay
Com’l/Ind
Mil
tER
Com’l/Ind
Mil
tCO1
tCO2
tS1
Com’l/Ind
Mil
Synchronous Clock to Local Feedback to Combinatorial
Output[5, 12]
Com’l/Ind
Mil
Dedicated Input or Feedback Set-Up Time to Synchronous
Clock Input[8]
Com’l/Ind
Mil
12
15
15
30
30
0
tS2
I/O Input Set-Up Time to Synchronous Clock Input[8, 13]
Input Hold Time from Synchronous Clock Input[8]
Synchronous Clock Input HIGH Time
Com’l/Ind
Mil
24
24
0
tH
Com’l/Ind
Mil
0
0
tWH
tWL
tRW
tRR
Com’l/Ind
Mil
6
8
6
8
Synchronous Clock Input LOW Time
Com’l/Ind
Mil
6
8
6
8
Asynchronous Clear Width[5, 8]
Com’l/Ind
Mil
20
20
20
20
25
25
25
25
Asynchronous Clear Recovery Time[5, 8]
Asynchronous Clear to Registered Output Delay[8]
Com’l/Ind
Mil
tRO
Com’l/Ind
Mil
20
20
25
25
Notes:
8. This specification is a measure of the delay from input signal applied to a dedicated input (44-pin PLCC input pin 9, 11, 12, 13, 31, 33, 34, or 35) to combinatorial
output on any output pin. This delay assumes no expander terms are used to form the logic function. When this note is applied to any parameter specification it
indicates that the signal (data, asynchronous clock, asynchronous clear, and/or asynchronous preset) is applied to a dedicated input only and no signal path
(either clock or data) employs expander logic. If an input signal is applied to an I/O pin, an additional delay equal to t should be added to the comparable delay
PIA
for a dedicated input. If expanders are used, add the maximum expander delay t
to the overall delay for the comparable delay without expanders.
EXP
9. This specification is a measure of the delay from input signal applied to an I/O macrocell pin to any output. This delay assumes no expander terms are used to
form the logic function.
10. This specification is a measure of the delay from an input signal applied to a dedicated input (44-pin PLCC input pin 9, 11, 12, 13, 31, 33, 34, or 35) to combinatorial
output on any output pin. This delay assumes expander terms are used to form the logic function and includes the worst-case expander logic delay for one pass
through the expander logic. This parameter is tested periodically by sampling production material.
11. This specification is a measure of the delay from an input signal applied to an I/O macrocell pin to any output. This delay assumes expander terms are used to
form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by sampling
production material.
12. This specification is a measure of the delay from synchronous register clock to internal feedback of the register output signal to the input of the LAB logic array
and then to a combinatorial output. This delay assumes no expanders are used, register is synchronously clocked and all feedback is within the same LAB. This
parameter is tested periodically by sampling production material.
13. If data is applied to an I/O input for capture by a macrocell register, the I/O pin set-up time minimums should be observed. These parameters are t forsynchronous
S2
operation and t
for asynchronous operation..
AS2
Document #: 38-03015 Rev. *B
Page 6 of 19
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CY7C343
External Synchronous Switching Characteristics Over Operating Range (continued)[7]
7C343-20
7C343-25
Parameter
tPR
Description
Asynchronous Preset Recovery Time[5, 8]
Min. Max. Min. Max. Unit
Com’l/Ind
Mil
20
20
25
25
ns
tPO
Asynchronous Preset to Registered Output Delay[8]
Com’l/Ind
Mil
20
20
3
25
25
3
ns
tCF
Synchronous Clock to Local Feedback Input[5, 14]
Com’l/Ind
Mil
ns
3
3
[5]
tP
External Synchronous Clock Period (1/fMAX3
)
Com’l/Ind
Mil
12
12
16
16
ns
fMAX1
fMAX2
fMAX3
fMAX4
tOH
External Maximum Frequency (1/(tCO1 + tS1))[5, 15]
Com’l/Ind 41.6
Mil 41.6
Internal Local Feedback Maximum Frequency, lesser of (1/(tS1 Com’l/Ind 66.6
34
MHz
MHz
MHz
MHz
ns
34
55
[5, 16]
+ tCF)) or (1/tCO1
)
Mil
66.6
55
Data Path Maximum Frequency, least of 1/(tWL +tWH), 1/(tS1 +tH), Com’l/Ind 83.3
62.5
62.5
62.5
62.5
3
[5, 17]
or (1/tCO1
)
Mil
83.3
Maximum Register Toggle Frequency (1/(tWL+tWH))[5, 18]
Com’l/Ind 83.3
Mil
83.3
3
Output Data Stable Time from Synchronous Clock Input[5, 19] Com’l/Ind
Mil
3
3
tPW
Asynchronous Preset Width[5, 8]
Com’l/Ind
Mil
20
20
25
ns
25
Notes:
14. This specification is a measure of the delay associated with the internal register feedback path. This is the delay from synchronous clock to LAB logic array input.
This delay plus the register set-up time, t , is the minimum internal period for an internal synchronous state machine configuration. This delay is for feedback within the same
S1
LAB. This parameter is tested periodically by sampling production material.
15. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which a state machine configuration with externalfeedback can operate.
It is assumed that all data inputs and feedback signals are applied to dedicated inputs.
16. This specification indicates the guaranteed maximum frequency at which a state machine, with internal-only feedback, can operate. If register output states must
also control external points, this frequency can still be observed as long as this frequency is less than 1/t
the same LAB..
. All feedback is assumed to be local, originating within
CO1
17. This frequency indicates the maximum frequency at which the device may operate in data path mode. This delay assumes data input signals are applied to
dedicated inputs and no expander logic is used.
18. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which an individual output or buried register can be cycled.
19. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin.
Document #: 38-03015 Rev. *B
Page 7 of 19
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CY7C343
External Synchronous Switching CharacteristicsOver Operating Range (continued)[7]
7C343-30
7C343-35
Parameter
tPD1
Description
Dedicated Input to Combinatorial Output Delay[8]
Min. Max. Min. Max. Unit
Com’l/Ind
Mil
30
30
44
44
44
44
58
58
30
30
30
30
16
16
35
35
35
35
53
53
55
55
73
73
35
35
35
35
20
20
42
42
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
tPD2
tPD3
tPD4
tEA
I/O Input to Combinatorial Output Delay[9]
Com’l/Ind
Mil
Dedicated Input to Combinatorial Output Delay with Expander
Delay[10]
Com’l/Ind
Mil
I/O Input to Combinatorial Output Delay with Expander Delay[5, 11] Com’l/Ind
Mil
Input to Output Enable Delay[5, 8]
Input to Output Disable Delay[5, 8]
Synchronous Clock Input to Output Delay
Com’l/Ind
Mil
tER
tCO1
tCO2
tS1
Com’l/Ind
Mil
Com’l/Ind
Mil
Synchronous Clock to Local Feedback to Combinatorial Output[5, 12] Com’l/Ind
Mil
Dedicated Input or Feedback Set-Up Time to Synchronous Clock Com’l/Ind
20
20
35
35
0
25
25
Input[8]
Mil
tS2
I/O Input Set-Up Time to Synchronous Clock Input[8, 13]
Input Hold Time from Synchronous Clock Input[8]
Synchronous Clock Input HIGH Time
Com’l/Ind
Mil
42
42
tH
Com’l/Ind
Mil
0
0
0
tWH
tWL
tRW
tRR
tRO
tPR
tPO
tCF
Com’l/Ind
Mil
10
10
10
10
30
30
30
30
12.5
12.5
12.5
12.5
35
Synchronous Clock Input LOW Time
Com’l/Ind
Mil
Asynchronous Clear Width[5, 8]
Com’l/Ind
Mil
35
Asynchronous Clear Recovery Time[5, 8]
Asynchronous Clear to Registered Output Delay[8]
Asynchronous Preset Recovery Time[5, 8]
Asynchronous Preset to Registered Output Delay[8]
Com’l/Ind
Mil
35
35
Com’l/Ind
Mil
30
30
35
35
Com’l/Ind
Mil
30
30
35
35
Com’l/Ind
Mil
30
30
3
35
35
5
Synchronous Clock to Local Feedback Input[5, 14]
Com’l/Ind
Mil
3
5
[5]
tP
External Synchronous Clock Period (1/fMAX3
)
Com’l/Ind
Mil
20
20
27
27
25
25
fMAX1
External Maximum Frequency (1/(tCO1 + tS1))[5, 15]
Com’l/Ind
Mil
22.2
22.2
Document #: 38-03015 Rev. *B
Page 8 of 19
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CY7C343
External Synchronous Switching CharacteristicsOver Operating Range (continued)[7]
7C343-30
7C343-35
Parameter
fMAX2
Description
Min. Max. Min. Max. Unit
Internal Local Feedback Maximum Frequency, lesser of (1/(tS1 + Com’l/Ind
43
43
50
50
50
50
3
33
33
40
40
40
40
3
MHz
MHz
MHz
ns
[5, 16]
t
CF)) or (1/tCO1)
Mil
fMAX3
fMAX4
tOH
Data Path Maximum Frequency, least of 1/(tWL + tWH), 1/(tS1 + tH), Com’l/Ind
[5, 17]
or (1/tCO1
)
Mil
Maximum Register Toggle Frequency (1/(tWL+tWH))[5, 18]
Output Data Stable Time from Synchronous Clock Input[5, 19]
Asynchronous Preset Width[5, 8]
Com’l/Ind
Mil
Com’l/Ind
Mil
3
3
tPW
Com’l/Ind
Mil
30
30
35
35
ns
External Asynchronous Switching Characteristics Over Operating Range [7]
7C343-20
7C343-25
Parameter
tACO1
Description
Asynchronous Clock Input to Output Delay[8]
Min. Max. Min. Max. Unit
Com’l/Ind
Mil
20
20
32
32
12
ns
tACO2
tAS1
tAS2
tAH
Asynchronous Clock Input to Local Feedback to Combinatorial Com’l/Ind
25
25
40
40
ns
Output[20]
Mil
Dedicated Input or Feedback Set-Up Time to Asynchronous Com’l/Ind
4
4
ns
Clock Input[8]
Mil
I/O Input Set-Up Time to Asynchronous Clock Input[8]
Input Hold Time from Asynchronous Clock Input[8]
Asynchronous Clock Input HIGH Time[8]
Com’l/Ind
Mil
15
15
5
5
5
ns
Com’l/Ind
Mil
20
20
6
ns
5
tAWH
tAWL
tACF
tAP
Com’l/Ind
Mil
9
ns
9
6
Asynchronous Clock Input LOW Time[8, 21]
Com’l/Ind
Mil
7
11
11
9
ns
7
Asynchronous Clock to Local Feedback Input[5, 22]
Com’l/Ind
Mil
13
13
ns
9
[5]
External Asynchronous Clock Period (1/fMAXA4
)
Com’l/Ind
Mil
16
16
15
15
ns
fMAXA1
External Maximum Frequency in Asynchronous Mode 1/(tACO1 Com’l/Ind 41.6
20
20
MHz
[5, 23]
+ tAS1
)
Mil
41.6
Notes:
20. This specification is a measure of the delay from an asynchronous register clock input to internal feedback of the register output signal to the input of the LAB
logic array and then to a combinatorial output. This delay assumes no expanders are used in the logic of combinatorial output or the asynchronous clock input.
The clock signal is applied to a dedicated input pin and all feedback is within a single LAB. This parameter is tested periodically by sampling production material.
21. This parameter is measured with a positive-edge triggered clock at the register. For negative edge triggering, the t
and t
parameters must be swapped. If a
AWH
.
AWL
given input is used to clock multiple registers with both positive and negative polarity, t
should be used for both t
and t
AWH
AWH
AWL
22. This specification is a measure of the delay associated with the internal register feedback path for an asynchronous clock to LAB logic array input. This delay
plus the asynchronous register set-up time, t , is the minimum internal period for an internal asynchronously clocked state machine configuration. This delay is for feedback
AS1
within the same LAB, assumes no expander logic in the clock path, and assumes that the clock input signal is applied to a dedicated input pin. This parameter is tested periodically
by sampling production material.
23. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine configuration with external feedback can
operate. It is assumed that all data inputs, clock inputs, and feedback signals are applied to dedicated inputs, and that no expander logic is employed in the clock
signal path or data path.
Document #: 38-03015 Rev. *B
Page 9 of 19
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CY7C343
External Asynchronous Switching Characteristics Over Operating Range (continued)[7]
7C343-20
7C343-25
Parameter
fMAXA2
Description
Maximum Internal Asynchronous Frequency[5, 24]
Min. Max. Min. Max. Unit
Com’l/Ind 58.8
33
50
50
MHz
MHz
MHz
ns
Mil
58.8
50
fMAXA3
fMAXA4
tAOH
Data Path Maximum Frequency in Asynchronous Mode[5, 25] Com’l/Ind
Mil
50
Maximum Asynchronous Register Toggle Frequency 1/(tAWH + Com’l/Ind 62.5
40
40
15
15
[5, 26]
tAWL
)
Mil
62.5
12
Output Data Stable Time from Asynchronous Clock Input[5, 27] Com’l/Ind
Mil
12
External Asynchronous Switching Characteristics Over Operating Range [7]
7C343-30
7C343-35
Parameter
tACO1
Description
Asynchronous Clock Input to Output Delay[8]
Min. Max. Min. Max. Unit
Com’l/Ind
Mil
30
30
46
46
35
35
55
55
ns
ns
tACO2
tAS1
Asynchronous Clock Input to Local Feedback to Combinatorial Com’l/Ind
Output[20]
Mil
Dedicated Input or Feedback Set-Up Time to Asynchronous
Clock Input[8]
Com’l/Ind
Mil
6
6
8
ns
8
tAS2
I/O Input Set-Up Time to Asynchronous Clock Input[8]
Input Hold Time from Asynchronous Clock Input[8]
Asynchronous Clock Input HIGH Time[8]
Com’l/Ind
Mil
25
25
8
30
30
10
10
16
16
14
14
ns
tAH
Com’l/Ind
Mil
ns
8
tAWH
tAWL
tACF
Com’l/Ind
Mil
14
14
11
11
ns
Asynchronous Clock Input LOW Time[8, 21]
Com’l/Ind
Mil
ns
Asynchronous Clock to Local Feedback Input[5, 22]
Com’l/Ind
Mil
18
18
22
22
ns
[5]
tAP
External Asynchronous Clock Period (1/fMAXA4
)
Com’l/Ind
Mil
25
25
27
27
40
40
33
33
40
40
30
30
23
23
33
33
28
28
33
33
ns
fMAXA1
fMAXA2
fMAXA3
External Maximum Frequency in Asynchronous Mode 1/(tACO1 Com’l/Ind
MHz
MHz
MHz
MHz
[5, 23]
+ tAS1
)
Mil
Maximum Internal Asynchronous Frequency[5, 24]
Com’l/Ind
Mil
Data Path Maximum Frequency in Asynchronous Mode[5, 25]
Com’l/Ind
Mil
fMAXA4
Maximum Asynchronous Register Toggle Frequency 1/(tAWH + Com’l/Ind
[5, 26]
tAWL
)
Mil
Notes:
24. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with internal-only feedback can operate.
This parameter is determined by the lesser of (1/t + t )) or (1/(t +t )). If register output states must also control external points, this frequency can still be observed
ACF AS1
AWH AWL
as long as this frequency is less than 1/t
.
ACO1
25. This frequency is the maximum frequency at which the device may operate in the asynchronously clocked data path mode. This specification is determined by
the least of 1/(t + t ), 1/(t + t ) or 1/t . It assumes data and clock input signals are applied to dedicated input pins and no expander logic is used.
AWH
AWL
AS1
AH
ACO1
26. This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked mode
by a clock signal applied to an external dedicated input pin.
27. This parameter indicates the minimum time that the previous register output data is maintained on the output after an asynchronous register clock input.
Document #: 38-03015 Rev. *B
Page 10 of 19
USE ULTRA37000™ FOR
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CY7C343
External Asynchronous Switching Characteristics Over Operating Range (continued)[7]
7C343-30
7C343-35
Parameter
tAOH
Description
Min. Max. Min. Max. Unit
Output Data Stable Time from Asynchronous Clock Input[5, 27] Com’l/Ind
15
15
15
15
ns
Mil
Internal Switching Characteristics Over Operating Range [7]
7C343-20
7C343-25
Parameter
tIN
Description
Min.
Max.
Min.
Max.
Unit
Dedicated Input Pad and Buffer Delay
Com’l/Ind
Mil
4
4
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tIO
I/O Input Pad and Buffer Delay
Expander Array Delay
Com’l/Ind
Mil
4
5
4
5
tEXP
tLAD
tLAC
tOD
Com’l/Ind
Mil
10
10
10
10
8
12
12
12
12
10
10
5
Logic Array Data Delay
Com’l/Ind
Mil
Logic Array Control Delay
Output Buffer and Pad Delay
Output Buffer Enable Delay[28]
Output Buffer Disable Delay
Com’l/Ind
Mil
8
Com’l/Ind
Mil
4
4
5
tZX
Com’l/Ind
Mil
8
10
10
10
10
8
tXZ
Com’l/Ind
Mil
8
8
tRSU
tRH
tLATCH
tRD
tCOMB
tCH
Register Set-Up Time Relative to Clock Signal Com’l/Ind
4
4
4
4
6
6
6
6
at Register
Mil
Register Hold Time Relative to Clock Signal at Com’l/Ind
Register
Mil
Flow-Through Latch Delay
Register Delay
Com’l/Ind
Mil
2
2
1
1
2
2
3
3
1
1
3
3
Com’l/ Ind
Mil
Transparent Mode Delay[29]
Clock HIGH Time
Com’l/Ind
Mil
Com’l/Ind
Mil
6
6
6
6
8
8
8
8
tCL
Clock LOW Time
Com’l/Ind
Mil
tIC
Asynchronous Clock Logic Delay
Synchronous Clock Delay
Com’l/Ind
Mil
12
12
2
14
14
2
tICS
Com’l/Ind
Mil
2
2
Notes:
28. Sample tested only for an output change of 500 mV.
29. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combinatorial
operation.
Document #: 38-03015 Rev. *B
Page 11 of 19
USE ULTRA37000™ FOR
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CY7C343
Internal Switching Characteristics Over Operating Range (continued)[7]
7C343-20
7C343-25
Parameter
tFD
Description
Min.
Max.
Min.
Max.
Unit
Feedback Delay
Com’l/Ind
Mil
1
1
4
4
4
4
1
1
5
5
5
5
ns
tPRE
tCLR
tPCW
tPCR
tPIA
Asynchronous Register Preset Time
Asynchronous Register Clear Time
Com’l/Ind
Mil
ns
ns
ns
ns
ns
Com’l/Ind
Mil
Asynchronous Preset and Clear Pulse Width Com’l /Ind
Mil
4
4
4
4
5
5
5
5
Asynchronous Preset and Clear Recovery
Time
Com’l/Ind
Mil
Programmable Interconnect Array Delay Time Com’l/Ind
Mil
12
12
14
14
Internal Switching Characteristics Over Operating Range [7]
7C343-30
7C343-35
Parameter
tIN
Description
Min.
Max.
7
Min.
Max.
9
Unit
Dedicated Input Pad and Buffer Delay
Com’l/Ind
Mil
ns
7
9
tIO
I/O Input Pad and Buffer Delay
Expander Array Delay
Com’l/Ind
Mil
5
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
7
tEXP
tLAD
tLAC
tOD
Com’l/Ind
Mil
14
14
14
14
12
12
5
20
20
16
16
13
13
6
Logic Array Data Delay
Com’l/Ind
Mil
Logic Array Control Delay
Output Buffer and Pad Delay
Output Buffer Enable Delay[28]
Output Buffer Disable Delay
Com’l/Ind
Mil
Com’l/Ind
Mil
5
6
tZX
Com’l/Ind
Mil
11
11
11
11
13
13
13
13
tXZ
Com’l/Ind
Mil
tRSU
tRH
tLATCH
tRD
Register Set-Up Time Relative to Clock Signal Com’l/Ind
at Register
8
8
8
8
10
10
12
12
Mil
Register Hold Time Relative to Clock Signal at Com’l/Ind
Register
Mil
Flow-Through Latch Delay
Register Delay
Com’l/Ind
Mil
4
4
2
2
4
4
4
4
2
2
4
4
Com’l/Ind
Mil
tCOMB
Transparent Mode Delay[29]
Com’l/Ind
Mil
Document #: 38-03015 Rev. *B
Page 12 of 19
USE ULTRA37000™ FOR
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CY7C343
Internal Switching Characteristics Over Operating Range (continued)[7]
7C343-30
7C343-35
Parameter
tCH
Description
Min.
Max.
Min.
Max.
Unit
Clock HIGH Time
Clock LOW Time
Com’l/Ind
Mil
10
10
10
10
12.5
12.5
12.5
12.5
ns
tCL
Com’l/Ind
Mil
ns
ns
ns
ns
ns
ns
ns
ns
ns
tIC
Asynchronous Clock Logic Delay
Synchronous Clock Delay
Com’l/Ind
Mil
16
16
2
18
18
3
tICS
tFD
Com’l/Ind
Mil
2
3
Feedback Delay
Com’l/Ind
Mil
1
2
1
2
tPRE
tCLR
tPCW
tPCR
tPIA
Asynchronous Register Preset Time
Asynchronous Register Clear Time
Com’l/Ind
Mil
6
7
6
7
Com’l/Ind
Mil
6
7
6
7
Asynchronous Preset and Clear Pulse Width Com’l/Ind
Mil
6
6
6
6
7
7
7
7
Asynchronous Preset and Clear Recovery
Time
Com’l/Ind
Mil
Programmable Interconnect Array Delay Time Com’l/Ind
Mil
16
16
20
20
Switching Waveforms
External Combinatorial
DEDICATED INPUT/
I/O INPUT
t
/t
PD1 PD2
COMBINATORIAL
OUTPUT
t
ER
COMBINATORIAL OR
REGISTERED OUTPUT
HIGH-IMPEDANCE
THREE–STATE
t
ER
HIGH-IMPEDANCE
THREE-STATE
VALID OUTPUT
Document #: 38-03015 Rev. *B
Page 13 of 19
USE ULTRA37000™ FOR
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CY7C343
Switching Waveforms (continued)
External Synchronous
DEDICATED INPUTS OR
[8]
REGISTERED FEEDBACK
t
S1
t
H
t
t
WL
WH
SYNCHRONOUS
CLOCK
t
t
/t
t /t
RR PR
CO1
RW PW
ASYNCHRONOUS
CLEAR/PRESET
t
OH
[8]
t
/t
RO PO
REGISTERED
OUTPUTS
t
CO2
COMBINATORIAL OUTPUT FROM
[12]
REGISTERED FEEDBACK
External Asynchronous
DEDICATEDINPUTSOR
REGISTERED
[8 ]
FEEDBACK
t
t
t
AWL
t
AH
AWH
AS1
ASYNCHRONOUS
CLOCK INPUT
t
ACO1
t
/t
t
/t
RW PW
RR PR
ASYNCHRONOUS
CLEAR/PRESET
t
AOH
[8 ]
t
/t
RO PO
ASYNCHRONOUS REGISTERED
OUTPUTS
t
ACO2
COMBINATORIAL OUTPUT FROM
ASYNCH. REGISTERED FEEDBACK
Internal Combinatorial
t
IN
INPUT PIN
t
PIA
t
IO
I/O PIN
t
EXP
EXPANDER
ARRAY DELAY
t
, t
LAC LAD
LOGIC ARRAY
INPUT
LOGIC ARRAY
OUTPUT
Document #: 38-03015 Rev. *B
Page 14 of 19
USE ULTRA37000™ FOR
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CY7C343
Switching Waveforms (continued)
Internal Asynchronous
t
t
AWL
AWH
t
R
t
F
CLOCK PIN
t
IN
CLOCK INTO
LOGIC ARRAY
t
IC
CLOCK FROM
LOGIC ARRAY
t
t
RH
RSU
DATA FROM
LOGIC ARRAY
t
,t
t
FD
t
,t
t
FD
RD LATCH
CLR PRE
REGISTER OUTPUT
TO LOCAL LAB
InternalSynchronous
t
t
CL
CH
SYSTEM CLOCK PIN
t
IN
t
ICS
SYSTEM CLOCK
AT REGISTER
t
t
RH
RSU
DATA FROM
LOGIC ARRAY
Output Mode
CLOCK FROM
LOGIC ARRAY
t
t
OD
RD
DATA FROM
LOGIC ARRAY
t
XZ
t
ZX
HIGH IMPEDANCE
STATE
OUTPUT PIN
Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C343-20JC/JI
CY7C343-25HC/HI
CY7C343-25JC/JI
CY7C343-30HC/HI
CY7C343-30JC/JI
CY7C343-30HMB
CY7C343-35HC/HI
CY7C343-35JC
Package Type
20
J67
H67
J67
H67
J67
H67
H67
J67
H67
44-Lead Plastic Leaded Chip Carrier
44-Pin Windowed Leaded Chip Carrier
44-Lead Plastic Leaded Chip Carrier
44-Pin Windowed Leaded Chip Carrier
44-Lead Plastic Leaded Chip Carrier
44-Pin Windowed Leaded Chip Carrier
44-Pin Windowed Leaded Chip Carrier
44-Lead Plastic Leaded Chip Carrier
44-Pin Windowed Leaded Chip Carrier
Commercial/Industrial
Commercial/Industrial
25
30
35
Commercial/Industrial
Military
Commercial/Industrial
CY7C343-35HMB
Military
Document #: 38-03015 Rev. *B
Page 15 of 19
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CY7C343
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Switching Characteristics
Parameters
Subgroups
7, 8, 9, 10, 11
tPD1
tPD2
tPD3
tCO1
tS
DC Characteristics
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
Parameters
Subgroups
VOH
VOL
VIH
VIL
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
tH
tACO1
tACO2
tAS
IIX
IOZ
ICC1
tAH
Document #: 38-03015 Rev. *B
Page 16 of 19
USE ULTRA37000™ FOR
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CY7C343
Package Diagrams
44-Pin Windowed Leaded Chip Carrier H67
51-80079-**
Document #: 38-03015 Rev. *B
Page 17 of 19
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C343
Package Diagrams (continued)
44-Lead Plastic Leaded Chip Carrier J67
51-85003-*A
Warp is a registered trademark, and Ultra37000, Warp Professional and Warp Enterprise are trademarks, of Cypress Semicon-
ductor Corporation.
Document #: 38-03015 Rev. *B
Page 18 of 19
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C343
Document History Page
Document Title: CY7C343 64-Macrocell MAX® EPLD
Document Number: 38-03015
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
Change from Spec number: to 38-03015
106315
122226
213375
04/24/01
12/28/02
See ECN
SZV
RBI
*A
Power up requirements added to Operating Range Information
Added note to title page: “Use Ultra37000 For All New Designs”
*B
FSG
Document #: 38-03015 Rev. *B
Page 19 of 19
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