CY7C343B [CYPRESS]
64-Macrocell MAX EPLD; 64宏单元MAX EPLD
| 型号： | CY7C343B |
| 厂家： | 
CYPRESS |
| 描述： | 64-Macrocell MAX EPLD |
| 文件： | 总12页 (文件大小：173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
43B
CY7C343B
64-Macrocell MAX® EPLD
The CY7C343B contains 64 highly flexible macrocells and 128
expander product terms. These resources are divided into four
Logic Array Blocks (LABs) connected through the Program-
mable Inter-connect Array (PIA). There are 8 input pins, one
that doubles as a clock pin when needed. The CY7C343B also
has 28 I/O pins, each connected to a macrocell (6 for LABs A
and C, and 8 for LABs B and D). The remaining 36 macrocells
are used for embedded logic.
Features
• 64 MAX macrocells in 4 LABs
• 8 dedicated inputs, 24 bidirectional I/O pins
• Programmable interconnect array
• Advanced 0.65-micron CMOS technology to increase
performance
• Available in 44-pin HLCC, PLCC
• Lowest power MAX device
The CY7C343B is excellent for a wide range of both synchro-
nous and asynchronous applications.
Functional Description
The CY7C343B is a high-performance, high-density erasable
programmable logic device, available in 44-pin PLCC and
HLCC packages.
Logic Block Diagram
9 INPUT
11 INPUT
12 INPUT
13 INPUT
INPUT 35
INPUT/CLK34
INPUT 33
INPUT 31
DEDICATED INPUTS
SYSTEM CLOCK
LAB A
MACROCELL1
MACROCELL2
MACROCELL3
MACROCELL4
MACROCELL5
MACROCELL6
LAB D
MACROCELL56
2
4
5
6
7
8
1
MACROCELL55
MACROCELL54
MACROCELL53
MACROCELL52
MACROCELL51
MACROCELL50
MACROCELL49
44
42
41
40
39
38
37
I/O PINS
I/O PINS
MACROCELLS 7 - 16
MACROCELLS57 - 64
P
I
A
LAB B
LAB C
MACROCELL38
MACROCELL37
MACROCELL36
MACROCELL35
MACROCELL34
MACROCELL33
MACROCELL17
MACROCELL18
MACROCELL19
MACROCELL20
MACROCELL21
MACROCELL22
MACROCELL23
MACROCELL24
30
29
28
27
26
24
15
16
17
18
19
20
22
23
I/O PINS
I/O PINS
MACROCELLS39 - 48
MACROCELLS 25 - 32
(3, 14, 25, 36)
(10, 21, 32, 43)
V
CC
GND
C343B-1
MAX is a registered trademark of Altera Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-03038 Rev. **
Revised December 8, 1999
CY7C343B
Pin Configuration
HLCC, PLCC
Top View
6
5
4
3
2
1
44 43 42 41 40
I/O
I/O
I/O
V
I/O
I/O
7
39
38
37
8
INPUT
GND
9
CC
10
11
12
13
14
15
16
17
36
35
INPUT
INPUT
INPUT
INPUT
INPUT/CLK
34
33
INPUT
GND
V
CC
32
31
7C343
INPUT
I/O
I/O
I/O
I/O
30
29
I/O
18 19 20 21 22 23 24 25 26 27 28
C343B-2
Selection Guide
7C343B-25
7C343B-30
7C343B-35
Maximum Access Time (ns)
25
30
35
DC Output Current, per Pin[1]...................–25 mA to +25 mA
DC Input Voltage[1] .........................................–2.0V to +7.0V
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Operating Range
Storage Temperature ..................................–65°C to+135°C
Ambient
Ambient Temperature with
Power Applied..............................................–65°C to+135°C
Range
Commercial
Industrial
Military
Temperature
VCC
0°C to +70°C
5V ±5%
5V ±10%
5V ±10%
Maximum Junction Temperature
(Under Bias)................................................................. 150°C
Supply Voltage to Ground Potential[1].............–2.0V to+7.0V
–40°C to +85°C
–55°C to +125°C (Case)
Note:
1. Minimum DC input is –0.3V. During transactions, the inputs may undershoot to –2.0V or overshoot to 7.0V for input currents less then 100 mA and periods
shorter than 20 ns.
Document #: 38-03038 Rev. **
Page 2 of 12
CY7C343B
Electrical Characteristics Over the Operating Range
Parameter
VCC
Description
Supply Voltage
Test Conditions
Min.
Max.
Unit
V
Maximum VCC rise time is 10 ms 4.75(4.5)
5.25(5.5)
VOH
VOL
VIH
VIL
IIX
Output HIGH Voltage
Output LOW Voltage
Input HIGH Level
IOH = –4.0 mA DC[2]
IOL = 8 mA DC[2]
2.4
V
0.45
VCC+0.3
0.8
V
2.0
–0.3
–10
–40
V
Input LOW Level
V
Input Current
VI = VCC or ground
VO = VCC or ground
+10
µA
µA
ns
ns
IOZ
tR
Output Leakage Current
Recommended Input Rise Time
Recommended Input Fall Time
+40
100
tF
100
Capacitance
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Max.
Unit
CIN
VIN = 0V, f = 1.0 MHz
VOUT = 0V, f = 1.0 MHz
10
20
pF
pF
COUT
Note:
2. The IOH parameter refers to high-level TTL output current; the IOL parameter refers to low-level TTL output current.
AC Test Loads and Waveforms
R1 464Ω
R1 464Ω
5V
5V
ALL INPUT PULSES
90%
OUTPUT
OUTPUT
3.0V
GND
90%
10%
10%
<6 ns
R2
250Ω
R2
250Ω
50 pF
5 pF
<6 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
C343B-4
C343B-5
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT (commercial/military)
163 Ω
OUTPUT
1.75V
Document #: 38-03038 Rev. **
Page 3 of 12
CY7C343B
Programmable Interconnect Array
Typical I vs. f
CC
MAX
The Programmable Interconnect Array (PIA) solves intercon-
nect limitations by routing only the signals needed by each
logic array block. The inputs to the PIA are the outputs of every
macrocell within the device and the I/O pin feedback of every
pin on the device.
200
150
Unlike masked or programmable gate arrays, which induce
variable delay dependent on routing, the PIA has a fixed delay.
This eliminates undesired skews among logic signals, which
may cause glitches in internal or external logic. The fixed de-
lay, regardless of programmable interconnect array configura-
tion, simplifies design by ensuring that internal signal skews or
races are avoided. The result is simpler design implementa-
tion, often in a single pass, without the multiple internal logic
placement and routing iterations required for a programmable
gate array to achieve design timing objectives.
V
= 5.0V
CC
Room Temp.
100
50
0
100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 50 MHz
Design Recommendations
MAXIMUM FREQUENCY
C343B–7
Operation of the devices described herein with conditions
above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any
other conditions above those indicated in the operational sec-
tions of this data sheet is not implied. Exposure to absolute
maximum ratings conditions for extended periods of time may
affect device reliability. The CY7C343B contains circuitry to
protect device pins from high static voltages or electric fields;
however, normal precautions should be taken to avoid apply-
ing any voltage higher than maximum rated voltages.
Output Drive Current
250
200
150
I
OL
V
CC
= 5.0V
For proper operation, input and output pins must be con-
strained to the range GND < (VIN or VOUT) < VCC. Unused
inputs must always be tied to an appropriate logic level (either
VCC or GND). Each set of VCC and GND pins must be con-
nected together directly at the device. Power supply decou-
pling capacitors of at least 0.2 µF must be connected between
VCC and GND. For the most effective decoupling, each VCC
pin should be separately decoupled to GND, directly at the
device. Decoupling capacitors should have good frequency
response, such as monolithic ceramic types.
Room Temp.
100
50
I
OH
0
1
2
3
4
5
V
O
OUTPUTVOLTAGE (V)
C343B–8
Timing Considerations
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum ex-
pander delay tEXP to the overall delay. Similarly, there is an
additional tPIA delay for an input from an I/O pin when com-
pared to a signal from a straight input pin.
When calculating external asynchronous frequencies, use
tAS1 if all inputs are on dedicated input pins.
When expander logic is used in the data path, add the appro-
priate maximum expander delay, tEXP to tAS1. Determine
which of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is the low-
est frequency. The lowest of these frequencies is the maxi-
mum data path frequency for the asynchronous configuration.
When calculating synchronous frequencies, use tS1 if all inputs
are on the input pins. When expander logic is used in the data
path, add the appropriate maximum expander delay, tEXP to
tS1. Determine which of 1/(tWH + tWL), 1/tCO1, or 1/(tEXP + tS1
)
The parameter tOH indicates the system compatibility of this
device when driving other synchronous logic with positive in-
put hold times, which is controlled by the same synchronous
clock. If tOH is greater than the minimum required input hold
time of the subsequent synchronous logic, then the devices
are guaranteed to function properly with a common synchro-
nous clock under worst-case environmental and supply volt-
age conditions.
is the lowest frequency. The lowest of these frequencies is the
maximum data path frequency for the synchronous configura-
tion.
Document #: 38-03038 Rev. **
Page 4 of 12
CY7C343B
EXPANDER
DELAY
t
EXP
REGISTER
LOGIC ARRAY
OUTPUT
DELAY
t
t
CONTROLDELAY
CLR
INPUT
t
INPUT/
OUTPUT
LAC
PRE
t
OD
XZ
ZX
INPUT
DELAY
t
LOGIC ARRAY
DELAY
t
t
RD
t
RSU
t
t
COMB
LATCH
t
t
IN
RH
t
LAD
SYSTEM CLOCK DELAY t
ICS
PIA
CLOCK
DELAY
DELAY
t
t
PIA
IC
FEEDBACK
DELAY
t
FD
I/O DELAY
t
IO
C343B-9
Figure 1. CY7C343B Internal Timing Model
External Synchronous Switching CharacteristicsOver Operating Range
7C343B-25
7C343B-30
7C343B-35
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max. Unit
tPD1
Dedicated Input to Combinatorial Output
Delay[3]
Com’l/Ind
25
30
35
ns
tPD2
tSU
I/O Input to Combinatorial Output Delay[3] Com’l/Ind
40
14
45
16
55
ns
ns
ns
Global clock setup time
Com’l/ Ind
Com’l/Ind
15
0
20
0
25
0
tCO1
Synchronous Clock Input to Output
Delay[3]
20
tH
Input Hold Time from Synchronous Clock Com’l/Ind
ns
Input
tWH
tWL
Synchronous Clock Input HIGH Time
Synchronous Clock Input LOW Time
Maximum Register Toggle Frequency[4]
Com’l/Ind
Com’l/Ind
Com’l/Ind
8
8
10
10
50
12.5
12.5
40
ns
ns
fMAX
62.5
MH
z
tCNT
tODH
fCNT
Minimum Global Clock Period
Com’l/Ind
Com’l/Ind
Com’l/Ind
20
25
30
ns
ns
Output Data Hold Time After Clock
2
2
2
Maximum Internal Global Clock
Frequency[5]
50
40
33.3
MH
z
Notes:
3. C1 = 35 pF.
4. The fMAX values represent the highest frequency for pipeline data.
5. This parameter is measured with a 16-bit counter programmed into each LAB.
Document #: 38-03038 Rev. **
Page 5 of 12
CY7C343B
External Asynchronous Switching Characteristics Over Operating Range
7C343B-25
7C343B-30
7C343B-35
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tACO1
Asynchronous Clock Input to Output Com’l/Ind
25
30
35
ns
Delay[3]
tAS1
Dedicated Input or Feedback Set-Up Com’l/Ind
Time to Asynchronous Clock Input
5
6
6
8
8
ns
ns
tAH
Input Hold Time from Asynchronous
Clock Input
Com’l/Ind
Com’l/Ind
Com’l/Ind
Com’l/Ind
Com’l/Ind
10
16
14
tAWH
tAWL
tACNT
fACNT
Asynchronous Clock Input HIGH
Time[6]
11
9
14
11
ns
Asynchronous Clock Input LOW
Time[6]
ns
Minimum Internal Array Clock
Frequency
20
25
30
ns
Maximum Internal Array Clock
Frequency[5]
50
40
33.3
MHz
Internal Switching Characteristics Over Operating Range
7C343B-25
7C343B-30
7C343B-35
Parameter
tIN
Description
Min.
Max.
5
Min.
Max.
7
Min.
Max.
11
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Dedicated Input Pad and Buffer Delay Com’l/Ind
tIO
I/O Input Pad and Buffer Delay
Expander Array Delay
Com’l/Ind
Com’l/Ind
Com’l/Ind
Com’l/Ind
Com’l/Ind
Com’l/Ind
Com’l/Ind
Com’l/Ind
6
6
11
tEXP
tLAD
tLAC
tOD
12
12
10
5
14
14
12
5
20
14
13
6
Logic Array Data Delay
Logic Array Control Delay
Output Buffer and Pad Delay[3]
Output Buffer Enable Delay[3]
Output Buffer Disable Delay[7]
tZX
10
10
11
11
13
13
tXZ
tRSU
Register Set-Up Time Relative to
Clock Signal at Register
6
4
8
6
12
8
tRH
Register Hold Time Relative to Clock Com’l/Ind
ns
Signal at Register
tLATCH
tRD
tCOMB
tIC
Flow-Through Latch Delay
Register Delay
Com’l/Ind
Com’l/Ind
Com’l/Ind
Com’l/Ind
Com’l/Ind
Com’l/Ind
Com’l/Ind
Com’l/Ind
Com’l/Ind
3
1
4
2
4
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
Transparent Mode Delay
Asynchronous Clock Logic Delay
Synchronous Clock Delay
Feedback Delay
3
4
4
14
3
16
2
18
1
tICS
tFD
1
1
2
tPRE
tCLR
tPIA
Asynchronous Register Preset Time
Asynchronous Register Clear Time
5
6
7
5
6
7
Programmable Interconnect Array
Delay Time
14
16
20
Notes:
6. This parameter is measured with a positive-edge-triggered clock at the register. For negative-edge clocking, the tACH and tACL parameter must be swapped.
7. C1 = 5 pF.
Document #: 38-03038 Rev. **
Page 6 of 12
CY7C343B
Switching Waveforms
Internal Synchronous
CLOCK FROM
LOGIC ARRAY
t
OD
t
RD
DATA FROM
LOGIC ARRAY
t
XZ
t
ZX
HIGH IMPEDANCE
STATE
OUTPUT PIN
C343B-10
Internal Asynchronous
t
t
AWL
AWH
t
R
t
F
CLOCK PIN
t
IN
CLOCK INTO
LOGIC ARRAY
t
IC
CLOCK FROM
LOGIC ARRAY
t
t
RH
SU
DATA FROM
LOGIC ARRAY
t
,t
t
FD
t
,t
t
FD
RD LATCH
CLR PRE
REGISTER OUTPUT
TO LOCAL LAB
LOGIC ARRAY
t
PIA
REGISTER OUTPUT
TO ANOTHER LAB
C343B-11
Internal Synchronous
SYSTEM CLOCK PIN
t
t
ICS
IN
SYSTEM CLOCK
AT REGISTER
t
t
RH
RSU
DATA FROM
LOGIC ARRAY
C343B-12
Document #: 38-03038 Rev. **
Page 7 of 12
CY7C343B
Switching Waveforms (continued)
Internal Combinatorial
t
IN
INPUT PIN
I/O PIN
t
IO
t
EXP
EXPANDER
ARRAY DELAY
t
, t
LAC LAD
LOGIC ARRAY
INPUT
LOGIC ARRAY
OUTPUT
tCOMB
tOD
OUTPUT
PIN
C343B-13
External Combinatorial
DEDICATED INPUT/
I/O INPUT
t
/t
PD1 PD2
COMBINATORIAL
OUTPUT
C343B-14
External Synchronous
tWH
tWL
SYNCHRONOUS
CLOCK PIN
SYNCHRONOUS
CLOCK AT REGISTER
tH
tSU
DATA FROM
LOGIC ARRAY
tCO1
REGISTERED
OUTPUTS
C343B-15
Document #: 38-03038 Rev. **
Page 8 of 12
CY7C343B
Switching Waveforms (continued)
External Asynchronous
DEDICATED INPUTS OR
REGISTERED FEEDBACK
t
t
t
AWL
t
AH
AWH
AS1
ASYNCHRONOUS
CLOCK INPUT
C343B-16
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C343B-25HC/HI
CY7C343B-25JC/JI
CY7C343B-30JC/JI
CY7C343B-35HC/HI
CY7C343B-35JC/JI
Package Type
25
H67
J67
J67
H67
J67
44-Pin Windowed Leaded Chip Carrier
44-Lead Plastic Leaded Chip Carrier
44-Lead Plastic Leaded Chip Carrier
44-Pin Windowed Leaded Chip Carrier
44-Lead Plastic Leaded Chip Carrier
Commercial/Industrial
30
35
Commercial/Industrial
Commercial/Industrial
Document #: 38-03038 Rev. **
Page 9 of 12
CY7C343B
Package Diagrams
44-Pin Windowed Leaded Chip Carrier H67
51-80079
Document #: 38-03038 Rev. **
Page 10 of 12
CY7C343B
Package Diagrams (continued)
44-Lead Plastic Leaded Chip Carrier J67
51-85003-A
Document #: 38-03038 Rev. **
Page 11 of 12
© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C343B
Document Title: CY7C343B 64-Macrocell Max ® EPLD
Document Number: 38-03038
Issue
ECN NO. Date
Orig. of
Change
REV.
Description of Change
**
106461
07/11/01
SZV
Change from Spec Number: 38-00862 to 38-03038
Document #: 38-03038 Rev. **
Page 12 of 12
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