CY7C1386BV25-167BGI [CYPRESS]
Cache SRAM, 512KX36, 3.4ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119;型号: | CY7C1386BV25-167BGI |
厂家: | CYPRESS |
描述: | Cache SRAM, 512KX36, 3.4ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119 时钟 静态存储器 内存集成电路 |
文件: | 总28页 (文件大小:807K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CY7C1387BV25
CY7C1386BV25
512K x 36 / 1M x 18 Pipelined DCD SRAM
registers controlled by a positive-edge-triggered clock input
(CLK). The synchronous inputs include all addresses, all data
Features
• Fast clock speed: 200,167, 150, 133 MHz
• Provide high-performance 3-1-1-1 access rate
• Fast OE access times: 3.0, 3.4, 3.8, 4.2 ns
• Optimal for depth expansion
• 2.5V ± 5% power supply
• Common data inputs and data outputs
• Double-cycle Deselect
• Byte Write Enable and Global Write control
• Chip enable for address pipeline
• Address, data, and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst
sequence)
inputs, address-pipelining Chip Enable (CE), burst control
inputs (ADSC, ADSP, and ADV), Write Enables (BWa, BWb,
BWc, BWd and BWE), and global write (GW).
Asynchronous inputs include the output enable (OE) and burst
mode control (MODE). The data (DQa,b,c,d) and the data parity
(DPa,b,c,d) outputs, enabled by OE, are also asynchronous.
DQa,b,c,d and DPa,b,c,d apply to CY7C1386BV25 and DQa,b
and DPa,b apply to CY7C1387BV25. a, b, c, d each are of eight
bits wide in the case of DQ and one bit wide in the case of DP.
Addresses and chip enables are registered with either address
status processor (ADSP) or address status controller (ADSC)
input pins. Subsequent burst addresses can be internally
generated as controlled by the burst advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQa and DPa. BWb controls DQb and DPb. BWc
controls DQc and DPd. BWd controls DQd-DQd and DPd.
BWa, BWb BWc, and BWd can be active only with BWE being
LOW. GW being LOW causes all bytes to be written. Write
pass-through capability allows written data available at the
output for the immediately next Read cycle. This device also
incorporates pipelined enable circuit for easy depth expansion
without penalizing system performance.
• Automatic power-down available using ZZ mode or CE
deselect
• High-density, high-speed packages
• JTAG boundary scan for BGA packaging version
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced
single-layer polysilicon, triple-layer metal technology. Each
memory cell consists of six transistors.
The CY7C1386BV25 and CY7C1387BV25 SRAMs integrate
1,048,576 × 18 and 524,288 × 36 SRAM cells with advanced
synchronous peripheral circuitry and a two-bit counter for
internal burst operation. All synchronous inputs are gated by
The CY7C1386BV25/CY7C1387BV25 are both double-cycle
deselect parts. All inputs and outputs of the CY7C1386BV25
and the CY7C1387BV25 are JEDEC-standard JESD8-5-
compatible.
Selection Guide
200 MHz
167 MHz
3.4
150 MHz
3.8
133 MHz
4.2
Unit
ns
Maximum Access Time
3.0
280
30
Maximum Operating Current
Maximum CMOS Standby Current
Commercial
230
190
160
mA
mA
30
30
30
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05253 Rev. *A
Revised January 18, 2003
CY7C1387BV25
CY7C1386BV25
Logic Block Diagram
MODE
512K × 36
2
(A[1;0]
)
Q
Q
CLK
ADV
0
BURST
COUNTER
CE
CLR
ADSC
1
ADSP
Q
17
19
ADDRESS
REGISTER
CE
D
512K × 36
Memory
Array
A[18:0]
19
17
GW
DQd, DPd
BYTEWRITE
REGISTERS
D
Q
BWE
BW
d
DQc, DPc
BYTEWRITE
REGISTERS
D
D
D
Q
Q
Q
BW
c
DQb, DPb
BYTEWRITE
REGISTERS
BW
b
DQa, DPa
BYTEWRITE
REGISTERS
BW
a
36
36
CE
2
1
CE
D
D
Q
ENABLE CE
REGISTER
CE
3
Q
OUTPUT
REGISTERS
INPUT
REGISTERS
CLK
ENABLE DELAY
REGISTER
CLK
OE
ZZ
SLEEP
CONTROL
DQa,b,c,d
DPa,b,c,d
Logic Block Diagram
MODE
(A[1;0])
2
1M × 18
Q
Q
CLK
ADV
0
BURST
COUNTER
CE
CLR
ADSC
1
ADSP
Q
17
19
ADDRESS
REGISTER
CE
D
1M × 18
A[19:0]
19
17
Memory
Array
GW
DQb, DPb
BYTEWRITE
REGISTERS
D
Q
BWE
BW
b
DQa, DPa
BYTEWRITE
REGISTERS
D
Q
BW
a
18
18
CE
2
1
CE
D
CE
Q
ENABLE CE
REGISTER
CE
3
D
Q
OUTPUT
INPUT
REGISTERS
CLK
ENABLE DELAY
REGISTER
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQa,b
DPa,b
Document #: 38-05253 Rev. *A
Page 2 of 28
CY7C1387BV25
CY7C1386BV25
Pin Configurations
100-pin TQFP
Packages
NC
NC
NC
VDDQ
VSSQ
NC,DQPc
1
A
NC
NC,DQPb
DQb
DQb
VDDQ
VSSQ
1
2
3
4
5
6
7
8
80
79
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQc
2
DQc
VDDQ
VSSQ
DQc
NC
78
3
4
5
VDDQ
VSSQ
NC
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
DQb
DQb
6
DQc
7
DPa
DQa
DQa
VSSQ
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSSQ
DQa
DQa
NC
DQb
DQb
DQc
8
DQb
VSSQ
VDDQ
DQc
DQb
VSSQ
VDDQ
DQb
9
9
10
11
VSSQ
VDDQ
DQc
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DQb
DQb
DQb
12
DQc
13
NC
VDD
NC
VSS
NC
14
CY7C1387BV25
VSS
NC
VDD
ZZ
CY7C1386BV25
(512K × 36)
VDD
15
(1M × 18)
NC
16
VSS
17
DQb
DQd
18
DQa
DQb
DQa
DQd
19
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
20
21
DQb
DQa
DQd
22
DQb
DQa
DQd
23
DPb
NC
DQd
24
DQa
DQa
VSSQ
VDDQ
DQa
DQd
25
NC
VSSQ
VDDQ
NC
NC
NC
VSSQ
26
VSSQ
VDDQ
NC
NC
NC
VDDQ
27
28
DQd
DQd
29
DQa
NC,DQPa
NC,DQPd
30
Document #: 38-05253 Rev. *A
Page 3 of 28
CY7C1387BV25
CY7C1386BV25
Pin Configurations (continued)
119-ball BGA
CY7C1386BV25 (512K × 36)
1
3
2
4
5
6
7
A
A
A
VDDQ
NC
A
A
VDDQ
A
A
ADSP
ADSC
VDD
A
A
B
C
D
E
F
NC
NC
NC
A
A
A
A
DQPb
DQb
DQb
VSS
VSS
VSS
VSS
DQPc
DQc
NC
DQb
DQb
DQc
DQc
CE1
OE
VSS
VDDQ
DQc
VDDQ
DQb
DQb
VDDQ
DQa
VSS
BWb
VSS
NC
DQb
ADV
GW
VDD
G
H
J
DQc
DQc
VDD
DQd
DQd
BWc
VSS
NC
DQc
DQc
DQb
VDD
VDDQ
DQd
DQd
VDDQ
DQd
DQd
NC
K
L
VSS
VSS
DQa
DQa
DQa
DQa
DQPa
A
CLK
NC
BWd
VSS
VSS
BWa
VSS
VSS
VSS
DQa
VDDQ
DQa
M
DQd
DQd
BWE
A1
N
P
R
T
DQPd
DQa
VSS
MODE
A
A0
VDD
A
NC
A
A
NC
ZZ
64M
32M
NC
NC
U
VDDQ
TMS
TDI
TCK
TDO
VDDQ
CY7C1387BV25
(1M × 18)
1
2
3
4
5
6
7
A
B
C
D
E
F
A
A
VDDQ
NC
A
A
A
A
VDDQ
NC
A
A
ADSP
ADSC
VDD
NC
NC
A
A
A
A
VSS
VSS
VSS
VSS
DQb
NC
NC
NC
DQPa
NC
NC
DQa
VDDQ
DQa
NC
DQb
CE1
OE
VSS
DQa
VDDQ
NC
VSS
VSS
VSS
NC
NC
ADV
GW
VDD
G
H
J
NC
DQb
DQb
NC
BWb
VSS
NC
DQa
VDD
VDDQ
DQa
VDDQ
NC
VDD
DQb
NC
K
L
VSS
NC
DQa
NC
DQa
NC
A
VSS
VSS
CLK
NC
DQb
VDDQ
DQb
NC
BWa
VSS
VSS
NC
VDDQ
NC
M
DQb
NC
BWE
A1
VSS
VSS
N
P
R
T
DQPb
DQa
VSS
MODE
A
A0
VSS
NC
A
NC
VDD
32M
TCK
A
A
NC
ZZ
A
64M
VDDQ
U
TMS
TDI
TDO
NC
VDDQ
Document #: 38-05253 Rev. *A
Page 4 of 28
CY7C1387BV25
CY7C1386BV25
Pin Configurations (continued)
165-ball Bump FBGA
CY7C1386BV25 (512K × 36)–11 × 15 FBGA
1
2
3
4
5
6
7
8
9
10
11
NC
A
CE
BWc
BWb
CE
BWE
A
ADSC
ADV
A
NC
1
2
3
NC
DPc
DQc
A
CE
BWd
BWa
CLK
GW
B
C
D
OE
ADSP
A
128M
DPb
NC
V
V
V
V
V
V
V
V
V
V
V
NC
DDQ
DDQ
SS
SS
SS
SS
SS
DDQ
DQc
DQc
DQc
DQc
V
V
V
V
V
V
DQb
DQb
DD
SS
SS
SS
DD
DDQ
DQc
DQc
DQc
NC
V
V
V
V
E
F
V
V
DQb
DQb
DQb
NC
DQb
DQb
DQb
ZZ
DDQ
DDQ
DDQ
DD
SS
SS
SS
DD
DDQ
V
V
V
V
V
V
DD
SS
SS
SS
DD
DDQ
V
V
V
V
G
H
J
V
V
DD
SS
SS
SS
DD
DDQ
V
NC
V
V
V
V
V
NC
SS
DD
SS
SS
SS
DD
DQd
DQd
DQd
DQd
DPd
NC
DQd
DQd
DQd
DQd
NC
V
V
V
V
V
V
V
DQa
DQa
DQa
DQa
NC
DQa
DQa
DQa
DQa
DPa
A
DDQ
DDQ
DDQ
DD
SS
SS
SS
DD
DDQ
V
V
V
V
V
V
V
V
K
L
V
V
DD
SS
SS
SS
DD
DDQ
V
V
V
V
V
V
DD
SS
SS
SS
DD
DDQ
V
V
V
V
M
N
P
V
V
DDQ
DD
SS
SS
SS
DD
DDQ
V
NC
TDI
A
NC
V
V
DDQ
SS
SS
DDQ
64M
A
A
A
A1
A0
TDO
TCK
A
A
A
A
A
MODE
32M
A
TMS
R
A
A
CY7C1387BV25 (1M × 18)–11 × 15 FBGA
1
2
3
4
5
6
7
8
9
10
11
NC
A
CE
BWb
NC
CE
BWE
A
ADSC
ADV
A
A
1
2
3
NC
NC
NC
A
CE
NC
BWa
CLK
GW
B
C
D
E
F
OE
ADSP
A
128M
DPa
NC
V
V
V
V
V
V
V
V
V
V
V
NC
NC
DDQ
DDQ
SS
SS
SS
SS
SS
DDQ
DQb
V
V
V
V
V
V
DQa
DD
SS
SS
SS
DD
DDQ
NC
NC
DQb
DQb
DQb
V
V
V
V
V
V
NC
NC
DQa
DQa
DQa
ZZ
DDQ
DDQ
DDQ
DD
SS
SS
SS
DD
DDQ
V
V
V
V
V
V
DD
SS
SS
SS
DD
DDQ
NC
V
V
V
V
G
H
J
V
V
NC
DD
SS
SS
SS
DD
DDQ
NC
V
NC
V
V
V
V
V
NC
NC
SS
DD
SS
SS
SS
DD
DQb
DQb
DQb
DQb
DPb
NC
NC
NC
NC
NC
NC
64M
V
V
V
V
V
V
V
DQa
DQa
DQa
DQa
NC
NC
NC
NC
NC
NC
A
DDQ
DDQ
DDQ
DDQ
DD
SS
SS
SS
DD
DDQ
V
V
V
V
V
V
V
V
K
L
V
V
DD
SS
SS
SS
DD
DDQ
V
V
V
V
V
V
DD
SS
SS
SS
DD
DDQ
V
V
V
V
M
N
P
V
V
DD
SS
SS
SS
DD
DDQ
V
NC
TDI
A
NC
V
V
DDQ
SS
SS
DDQ
A
A
A
A1
A0
TDO
TCK
A
A
A
A
A
MODE
32M
A
TMS
R
A
A
Document #: 38-05253 Rev. *A
Page 5 of 28
CY7C1387BV25
CY7C1386BV25
Pin Definitions
Pin
Name
I/O
Input-
Pin Description
Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK
A0
A1
A
Synchronous if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the two-bit
counter.
BWa
BWb
BWc
BWd
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Synchronous Sampled on the rising edge of CLK.
GW
BWE
CLK
CE1
CE2
CE3
OE
Input-
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
Synchronous write is conducted (ALL bytes are written, regardless of the values on BWa,b,c,d and BWE).
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
Synchronous asserted LOW to conduct a byte write.
Input-Clock
Input-
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH.
Input- Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE3 to select/deselect the device (TQFP only).
Input- Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE2 to select/deselect the device (TQFP only).
Input- Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
Asynchronous LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act
as input data pins. OE is masked during the first clock of a read cycle when emerging from a
deselected state.
ADV
Input-
Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically incre-
Synchronous ments the address in a burst cycle.
ADSP
Input-
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A is
Synchronous captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
MODE
ZZ
Input-
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A[x:0] is
Synchronous captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
Input-
Pin
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDDQ or left
floatingselects interleavedburst sequence. Thisis astrappin andshouldremainstaticduringdevice
operation.
Input-
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
Asynchronous with data integrity preserved.
DQa,
DPa
DQb,
DPb
DQc,
DPc
I/O-
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by
Synchronous the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by A[X] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE.
When OE is asserted LOW, the pins behave as outputs. When HIGH, DQx and DPx are placed in
a three-state condition.DQ a,b,c and d are eight bits wide. DP a,b,c and d are one bit wide.
DQd,
DPd
TDO
TDI
JTAG serial
output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only).
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK(BGA only).
This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK (BGA only).
JTAG serial
input
Synchronous
TMS
Test Mode
Select
Synchronous
Document #: 38-05253 Rev. *A
Page 6 of 28
CY7C1387BV25
CY7C1386BV25
Pin Definitions
Pin
Name
I/O
Pin Description
Serial clock to the JTAG circuit (BGA only).
TCK
JTAG serial
clock
VDD
Power Supply Power supply inputs to the core of the device. Should be connected to 2.5V +5% power supply.
VSS
Ground
Ground for the core of the device. Should be connected to ground of the system.
Power supply for the I/O circuitry. Should be connected to a 2.5V +5% power supply.
VDDQ
I/O Power
Supply
VSSQ
NC
I/O Ground
Ground for the I/O circuitry. Should be connected to ground of the system.
No Connects. Pins are not internally connected.
–
–
32M
64M
128M
No Connects. Reserved for address expansion.
Introduction
Functional Overview
the data bus within 4.2 ns (133-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single read cycles are supported.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (tCO) is 4.2 ns
(133-MHz device).
The CY7C1386BV25/CY7C1387BV25 are double-cycle
deselect parts. Once the SRAM is deselected at clock rise by
the chip select and either ADSP or ADSC signals, its output
will three-state immediately after the next clock rise.
The CY7C1386BV25/CY7C1387BV25 supports secondary
cache in systems utilizing either a linear or interleaved burst
sequence. The interleaved burst order supports Pentium and
i486 processors. The linear burst sequence is suited for
processors that utilize a linear burst sequence. The burst order
is user selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC). Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
chip select is asserted active. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
Write signals (GW, BWE, and BWx) and ADV inputs are
ignored during this first cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the corre-
sponding address location in the RAM core. If GW is HIGH,
then the write operation is controlled by BWE and BWx
signals. The CY7C1386BV25/CY7C1387BV25 provides byte
write capability that is described in the write cycle description
table. Asserting the Byte Write Enable input (BWE) with the
selected Byte Write (BWa,b,c,d for CY7C1386BV25 & BWa,b for
CY7C1387BV25) input will selectively write to only the desired
bytes. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWa,b,c,d for CY7C1386
/CY7C1386BV25 and BWa,b for CY7C1387BV25) inputs. A
Global Write Enable (GW) overrides all byte write inputs and
writes data to all four bytes. All writes are simplified with
on-chip synchronous self-timed write circuitry.
Synchronous Chip Selects (CE1, CE2, CE3 for TQFP / CE1 for
BGA) and an asynchronous Output Enable (OE) provide for
easy bank selection and output three-state control. ADSP is
ignored if CE1 is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
chip selects are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The corre-
sponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
Because the CY7C1386BV25/CY7C1387BV25 is a common
I/O device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQ inputs. Doing so will
three-state the output drivers. As a safety precaution, DQ are
automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
Document #: 38-05253 Rev. *A
Page 7 of 28
CY7C1387BV25
CY7C1386BV25
deasserted HIGH, (3) chip select is asserted active, and (4)
the appropriate combination of the write inputs (GW, BWE,
and BWx) are asserted active to conduct a write to the desired
byte(s). ADSC triggered write accesses require a single clock
cycle to complete. The address presented to A[17:0] is loaded
into the address register and the address advancement logic
while being delivered to the RAM core. The ADV input is
ignored during this cycle. If a global write is conducted, the
data presented to the DQ[x:0] is written into the corresponding
address location in the RAM core. If a byte write is conducted,
only the selected bytes are written. Bytes not selected during
a byte write operation will remain unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
write operations.
Interleaved Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
Because the CY7C1386BV25/CY7C1387BV25 is a common
I/O device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQ[x:0] inputs. Doing so will
three-state the output drivers. As a safety precaution, DQ[x:0]
are automatically three-stated whenever a write cycle is
detected, regardless of the state of OE.
A[1:0]
A[1:0]
A[1:0]
10
A[1:0]
11
00
01
10
11
01
10
11
00
11
00
00
01
Burst Sequences
01
10
The CY7C1386BV25/CY7C1387BV25 provides a two-bit
wraparound counter, fed by A[1:0], that implements either an
interleaved or linear burst sequence. The interleaved burst
sequence is designed specifically to support Intel® Pentium®
applications. The linear burst sequence is designed to support
processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Test Conditions
Min.
Max.
20
Unit
mA
ns
Sleep mode standby current ZZ > VDD − 0.2V
tZZS
Device operation to ZZ
ZZ recovery time
ZZ > VDD − 0.2V
ZZ < 0.2V
2tCYC
tZZREC
2tCYC
ns
[1, 2, 3, 4]
Cycle Descriptions
Next Cycle
Unselected
Add. Used
ZZ
O
O
O
O
O
O
O
O
O
O
CE3
CE2
X
CE1
H
L
ADSP
ADSC
ADV
X
OE
X
DQ
Hi-Z
Write
None
None
None
None
None
External
External
Next
X
H
X
H
X
L
X
L
L
X
X
L
X
Unselected
Unselected
Unselected
Unselected
Begin Read
Begin Read
Continue Read
Continue Read
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQ
X
L
L
L
X
X
X
X
L
H
H
L
X
X
X
L
L
L
X
X
X
H
H
X
L
X
L
X
X
X
L
L
H
H
H
X
X
X
Read
Read
Read
Read
X
X
X
X
X
H
H
H
H
L
H
L
Next
X
L
Continue Read
Next
X
L
H
Hi-Z
Note:
1. X = “Don't Care,” H = HIGH, L = LOW.
2. Write is defined by BWE, BWx, and GW. See Write Cycle Descriptions table.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4. CE1, CE2 and CE3 are available only in the TQFP package. BGA package has a single chip select CE1.
Document #: 38-05253 Rev. *A
Page 8 of 28
CY7C1387BV25
CY7C1386BV25
Cycle Descriptions (continued)[1, 2, 3, 4]
Next Cycle
Continue Read
Suspend Read
Suspend Read
Suspend Read
Suspend Read
Begin Write
Add. Used
Next
ZZ
O
O
O
O
O
O
O
O
O
O
O
O
1
CE3
X
CE2
X
CE1
H
X
ADSP
X
ADSC
H
ADV
L
OE
L
DQ
DQ
Write
Read
Read
Read
Read
Read
Write
Write
Write
Write
Write
Write
Write
X
Current
Current
Current
Current
Current
Current
External
Next
X
X
H
H
H
H
H
H
H
H
X
H
L
Hi-Z
DQ
X
X
X
H
H
X
X
H
H
X
X
H
H
L
Hi-Z
DQ
X
X
X
H
X
X
H
H
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Begin Write
X
X
H
L
X
H
Begin Write
L
H
X
H
L
Continue Write
Continue Write
Suspend Write
Suspend Write
ZZ “sleep”
X
X
H
H
L
Next
X
X
H
X
X
H
L
Current
Current
None
X
X
H
H
H
H
X
X
X
H
X
X
H
X
X
X
X
Write Cycle Descriptions[5, 6, 7]
Function (CY7C1386BV25)
Read
GW
BWE
BWd
BWc
X
1
BWb
BWa
X
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
X
X
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
X
Read
Write Byte 0 – DQa
Write Byte 1 – DQb
Write Bytes 1, 0
Write Byte 2 – DQc
Write Bytes 2, 0
Write Bytes 2, 1
Write Bytes 2, 1, 0
Write Byte 3 – DQd
Write Bytes 3, 0
Write Bytes 3, 1
Write Bytes 3, 1, 0
Write Bytes 3, 2
Write Bytes 3, 2, 0
Write Bytes 3, 2, 1
Write All Bytes
1
0
1
1
1
0
0
1
0
0
0
1
0
0
1
1
1
0
1
1
1
0
0
1
0
0
0
1
0
0
Write All Bytes
X
X
Function (CY7C1387BV25)
Read
GW
1
BWE
BWb
BWa
1
0
0
0
0
X
X
1
1
0
0
X
X
1
0
1
0
X
Read
1
Write Byte 0 – DQ[7:0] and DP0
Write Byte 1 – DQ[15:8] and DP1
Write All Bytes
1
1
1
Write All Bytes
0
Notes:
5. All Voltage referenced to Ground.
6. Overshoot: VIH(AC) < VDD + 1.5V for t < tTCYC/2; undershoot:VIL(AC) < 0.5V for t < tTCYC/2; power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms.
7.
tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
Document #: 38-05253 Rev. *A
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CY7C1387BV25
CY7C1386BV25
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1386BV25/CY7C1387BV25 incorporates a serial
boundary scan Test Access Port (TAP) in the BGA package
only. The TQFP package does not offer this functionality. This
port operates in accordance with IEEE Standard 1149.1-1900,
but does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC standard 2.5V I/O logic levels.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in the TAP Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the CaptureIR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board level serial test path.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain states. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Test Access Port–Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Boundary Scan Register
The boundary scan register is connected to all the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a xx-bit-long
register, and the x18 configuration has a yy-bit-long register.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-
tions can be used to capture the contents of the Input and
Output ring.
Test Data-In–(TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the Most Significant Bit (MSB) on any register.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
Test Data Out (TDO)
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
The TDO output pin is used to serially clock data-out from the
registers. The e output is active depending upon the current
state of the TAP state machine (see TAP Controller State
Diagram). The output changes on the falling edge of TCK.
TDO is connected to the Least Significant Bit (LSB) of any
register.
Performing a TAP Reset
TAP Instruction Set
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a high-Z state.
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller
cannot be used to load address, data or control signals into the
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
Document #: 38-05253 Rev. *A
Page 10 of 28
CY7C1387BV25
CY7C1386BV25
SRAM and cannot preload the Input or Output buffers. The
SRAM does not implement the 1149.1 commands EXTEST or
INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather it performs a capture of the Inputs and Output ring when
these instructions are executed.
When the SAMPLE/PRELOAD instructions loaded into the
instruction register and the TAP controller in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in the TAP controller, and
therefore this device is not compliant to the 1149.1 standard.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK captured in the
boundary scan register.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between the two
instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High-Z state.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the
Update-DR state while performing a SAMPLE/PRELOAD
instruction will have the same effect as the Pause-DR
command.
Bypass
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
SAMPLE/PRELOAD
Reserved
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully 1149.1-compliant.
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document #: 38-05253 Rev. *A
Page 11 of 28
CY7C1387BV25
CY7C1386BV25
TAP Controller State Diagram
TEST-LOGIC
1[8]
RESET
1
1
1
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-DR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Note:
8. The “0”/”1” next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05253 Rev. *A
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CY7C1387BV25
CY7C1386BV25
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
Selection
Circuitry
2
1
0
TDO
TDI
Instruction Register
29
Identification Register
31 30
.
.
2
1
1
0
0
.
x
.
.
.
2
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range[5, 6]
Parameter
VOH1
Description
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Test Conditions
IOH = −4.0 mA
Min.
2.0
Max.
Unit
V
V
VOH2
VOL1
VOL2
VIH
IOH = −100 µA
IOL = 8.0 mA
IOL = 100 µA
VDD – 0.2
0.4
0.2
V
V
1.7
−0.3
−5
V
DD+ 0.3
V
VIL
0.7
V
IX
GND ≤ VI ≤ VDDQ
5
µA
Document #: 38-05253 Rev. *A
Page 13 of 28
CY7C1387BV25
CY7C1386BV25
TAP AC Switching Characteristics Over the Operating Range[7, 9]
Parameters
tTCYC
Description
Min.
Max
Unit
ns
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
100
tTF
10
MHz
ns
tTH
40
40
tTL
TCK Clock LOW
ns
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
10
10
10
ns
ns
ns
tTDIS
tCS
Hold Times
tTMSH
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
10
10
10
ns
ns
ns
tTDIH
tCH
Capture Hold after Clock Rise
Output Times
tTDOV
TCK Clock LOW to TDO Valid
TCK Clock HIGH to TDO Invalid
20
ns
ns
tTDOX
0
Notes:
9. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Document #: 38-05253 Rev. *A
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CY7C1387BV25
CY7C1386BV25
TAP Timing and Test Conditions
1.25V
50Ω
ALL INPUT PULSES
TDO
2.5V
Z = 50Ω
0
1.25V
C = 20 pF
L
0V
GND
tTL
tTH
(a)
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOV
tTDOX
Identification Register Definitions
Instruction Field
Revision Number (31:28)
Device Depth (27:23)
512K x 36
1M x 18
xxxx
Description
xxxx
00111
Reserved for version number.
01000
00011
xxxxx
Defines depth of SRAM. 512K or 1M
Defines with of the SRAM. x36 or x18
Reserved for future use.
Device Width (22:18)
00100
Cypress Device ID (17:12)
Cypress JEDEC ID (11:1)
ID Register Presence (0)
xxxxx
00011100100
1
00011100100
1
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
Scan Register Sizes
Register Name
Instruction
Bypass
Bit Size (x18)
Bit Size (x36)
3
1
3
1
ID
32
51
32
70
Boundary Scan
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CY7C1387BV25
CY7C1386BV25
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures the Input/Output ring contents. Places the boundary scan
register between the TDI and TDO. Forces all SRAM outputs to High-Z state.
This instruction is not 1149.1 compliant.
IDCODE
001
010
Loads the ID register with the vendor ID code and places the register between
TDI and TDO. This operation does not affect SRAM operation.
SAMPLE Z
Captures the Input/Output contents. Places the boundary scan register
between TDI and TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
011
100
Do not use. This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the Input/Output ring contents. Places the boundary scan
register between TDI and TDO. Does not affect the SRAM operation. This
instruction does not implement 1149.1 preload function and is therefore not
1149.1 compliant.
RESERVED
RESERVED
BYPASS
101
110
111
Do not use. This instruction is reserved for future use.
Do not use. This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operation.
Document #: 38-05253 Rev. *A
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CY7C1387BV25
CY7C1386BV25
Boundary Scan Order (512K X 36)
Boundary Scan Order (1M X 18)
Signal
Name
Bump
ID
Signal
Name
Bump
ID
Signal
Name
Bump
ID
Signal
Name
Bump
ID
Bit #
Bit #
36
Bit #
Bit #
36
1
A
2R
A
6B
1
A
2R
DQb
2E
2
A
3T
4T
5T
6R
3B
5B
6P
7N
6M
7L
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
BWa
BWb
BWc
BWd
A
5L
2
A
2T
3T
5T
6R
3B
5B
7P
6N
6L
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
DQb
DQb
NC
2G
1H
5R
2K
1L
3
A
5G
3G
3L
3
A
4
A
4
A
5
A
5
A
DQb
DQb
DQb
DQb
DQb
MODE
A
6
A
2B
4E
3A
2A
2D
1E
2F
1G
1D
1D
2E
2G
1H
5R
2K
1L
6
A
7
A
CE
7
A
2M
1N
2P
3R
2C
3C
5C
6C
4N
4P
8
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
ZZ
A
8
DQa
DQa
DQa
DQa
ZZ
9
A
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
7K
7T
6H
7G
6F
7E
6D
6T
6A
5A
4G
4A
4B
4F
4M
4H
4K
6B
5L
6K
7P
6N
6L
A
DQa
DQa
DQa
DQa
DQa
A
A
A
A1
7K
7T
6H
7G
6F
7E
6D
7H
6G
6E
7D
6A
5A
4G
4A
4B
4F
4M
4H
4K
A0
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
A
A
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
MODE
A
A
ADV
ADSP
ADSC
OE
BWE
GW
CLK
A
2M
1N
2P
1K
2L
2N
1P
3R
2C
3C
5C
6C
4N
4P
A
ADV
ADSP
ADSC
OE
BWa
BWb
A
3G
2B
4E
3A
2A
1D
A
A
CE
A
BWE
GW
CLK
A
A1
A
A0
DQb
Document #: 38-05253 Rev. *A
Page 17 of 28
CY7C1387BV25
CY7C1386BV25
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage ......................................... > 1500V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–55°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Range
Commercial
Industrial
Ambient Temperature[11] VDD/VDDQ
[13]
Supply Voltage on VDD Relative to GND ....... –0.3V to +3.6V
0°C to +70°C
2.5V ± 5%
DC Voltage Applied to Outputs
–40°C to + 85°C
in High-Z State[10] ............................... –0.5V to VDDQ + 0.5V
DC Input Voltage[10] ............................ –0.5V to VDDQ + 0.5V
Electrical Characteristics Over the Operating Range
Parameter
VDD/VDDQ
VOH
Description
Power Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[10]
Input Load Current
Test Conditions
Min.
Max. Unit
2.5V range
2.375 2.625
V
V
VDD = Min., IOH = −1.0 mA
2.0
0.4
1.7
VOL
VDD = Min., IOL = 1.0 mA
VIH
VIL
–0.3
−5
0.7
5
IX
GND ≤ VI ≤ VDDQ
µA
µA
Input Current of MODE
Input Current of ZZ
−30
−30
30
Input = VSS
30
µA
IOZ
IDD
Output Leakage Current
VDD Operating Supply
GND ≤ VI ≤ VDDQ, Output Disabled
5
µA
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
6.7-ns cycle, 150 MHz
7.5-ns cycle, 133 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 167 MHz
6.7-ns cycle, 150 MHz
7.5-ns cycle, 133 MHz
All speed grades
280
230
190
160
100
80
mA
mA
mA
mA
mA
mA
mA
mA
mA
ISB1
AutomaticCEPower-down Max. VDD, Device Deselected,
Current—TTL Inputs IN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
V
65
60
ISB2
AutomaticCEPower-down Max. VDD, Device Deselected,
Current—CMOS Inputs IN ≤ 0.3V or VIN > VDDQ – 0.3V,
f = 0
30
V
ISB3
AutomaticCEPower-down Max. VDD, Device Deselected, or 5.0-ns cycle, 200 MHz
90
70
60
55
50
mA
mA
mA
mA
mA
Current—CMOS Inputs
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
f = fMAX = 1/tCYC
6.0-ns cycle, 167 MHz
6.7-ns cycle, 150 MHz
7.5-ns cycle, 133 MHz
All Speeds
ISB4
AutomaticCEPower-down Max. VDD, Device Deselected,
Current—TTL Inputs IN ≥ VIH or VIN ≤ VIL, f = 0
V
Capacitance[12]
Parameter
Description
Input Capacitance
Test Conditions
Max.
Unit
CIN
TA = 25°C, f = 1 MHz,
DD = 3.3V,
DDQ = 2.5V
3
3
3
pF
pF
pF
V
V
CCLK
Clock Input Capacitance
Input/Output Capacitance
CI/O
Notes:
10. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.
11. A is the temperature.
T
12. Tested initially and after any design or process changes that may affect these parameters.
13. Power Supply ramp up should be monotonic.
Document #: 38-05253 Rev. *A
Page 18 of 28
CY7C1387BV25
CY7C1386BV25
AC Test Loads and Waveforms[14]
R = 1667Ω
V
DDQ
[11]
OUTPUT
ALL INPUT PULSES
90%
OUTPUT
2.5V
GND
90%
10%
Z = 50Ω
0
10%
R = 50Ω
L
5 pF
R = 1538Ω
≤ 2.5 ns
≤ 2.5 ns
= 1.25V
VTH
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Thermal Resistance[12]
ΘJA
ΘJC
Description
Test Conditions
Unit
°C/W
°C/W
°C/W
(Junction to Ambient)
(Junction to Case)
119-ball BGA
165-ball FBGA
100 pin TQFP
Still Air, soldered on a 114.3 × 101.6 × 1.57 mm3,
41.54
44.51
25
6.33
2.38
9
2-layer board
Still Air, soldered on a 4.25 × 1.125 inch, 4-layer
printed circuit board
Switching Characteristics Over the Operating Range[15, 16, 17]
-200
-167
-150
-133
Parameter
tCYC
tCH
Description
Clock Cycle Time
Min. Max. Min. Max. Min. Max. Min. Max. Unit
5.0
1.8
1.8
1.4
0.4
6.0
2.1
2.1
1.5
0.5
6.7
2.3
2.3
1.5
0.5
7.5
2.5
2.5
1.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock HIGH
tCL
Clock LOW
tAS
Address Set-up Before CLK Rise
Address Hold After CLK Rise
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
ADSP, ADSC Set-up Before CLK Rise
ADSP, ADSC Hold After CLK Rise
tAH
tCO
3.0
3.4
3.8
4.2
tDOH
tADS
tADH
tWES
tWEH
tADVS
tADVH
tDS
1.3
1.4
0.4
1.3
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.3
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.3
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
BWE, GW, BWx Set-up Before CLK Rise 1.4
BWE, GW, BWx Hold After CLK Rise
ADV Set-up Before CLK Rise
ADV Hold After CLK Rise
0.4
1.4
0.4
1.4
0.4
1.4
0.4
Data Input Set-up Before CLK Rise
Data Input Hold After CLK Rise
Chip enable Set-up
tDH
tCES
tCEH
tCHZ
tCLZ
Chip enable Hold After CLK Rise
Clock to High-Z[16]
Clock to Low-Z[16]
OE HIGH to Output High-Z[16, 17]
OE LOW to Output Low-Z[16, 17]
OE LOW to Output Valid[16]
3.0
4.0
3.0
3.0
4.0
3.4
3.0
4.0
3.8
3.0
4.0
4.2
1.3
0
1.3
0
1.3
0
1.3
0
tEOHZ
tEOLZ
tEOV
Notes:
14. Input waveform should have a slew rate of 1 V/ns.
15. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and
output loading of the specified IOL/IOH and load capacitance. Shown in (a), (b) and (c) of AC test loads.
16.
tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from
steady-state voltage.
17. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ
.
Document #: 38-05253 Rev. *A
Page 19 of 28
CY7C1387BV25
CY7C1386BV25
Switching Waveforms
Write Cycle Timing[4, 18, 19]
Single Write
tCYC
tADH
Burst Write
Pipelined Write
tCH
Unselected
CLK
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
ADSC
ADV
tADH
tADS
ADSC initiated write
tADVH
tADVS
tAS
ADV Must Be Inactive for ADSP Write
WD3
ADD
GW
WE
CE1
WD1
WD2
tAH
tWH
tWH
tWS
tWS
tCES
tCEH
CE1 masks ADSP
tCEH
tCES
Unselected with CE2
CE2
CE3
OE
tCES
tCEH
tDH
tDS
High-Z
High-Z
Data
In
3a
2a
1a
2b
2c
2d
= DON’T CARE
= UNDEFINED
Notes:
18. WE is the combination of BWE, BWx and GW to define a write cycle (see Write Cycle Descriptions table).
19. WDx stands for Write Data to Address X.
Document #: 38-05253 Rev. *A
Page 20 of 28
CY7C1387BV25
CY7C1386BV25
Switching Waveforms (continued)
Read Cycle Timing[4, 18, 20]
Burst Read
Single Read
tCYC
Unselected
tCH
Pipelined Read
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADS
ADSC initiated read
ADSC
ADV
tADVS
tADH
Suspend Burst
tADVH
tAS
ADD
GW
RD1
RD3
RD2
tAH
tWS
tWS
tWH
WE
tCES
tCEH
tWH
CE1 masks ADSP
CE1
Unselected with CE2
CE2
tCES
tCEH
CE3
OE
tCES
tEOV
tCEH
tOEHZ
tDOH
Double-Cycle
Deselect
tCO
Data Out
2c
1a
2d
3a
2a
2b
tCLZ
tCHZ
= DON’T CARE
= UNDEFINED
Note:
20. RDx stands for Read Data from Address X.
Document #: 38-05253 Rev. *A
Page 21 of 28
CY7C1387BV25
CY7C1386BV25
Switching Waveforms (continued)
Read/Write Cycle Timing[4, 18, 19, 20]
Single Read
tCYC
Single Write
tCH
Unselected
Burst Read
Pipelined Read
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
ADSC
ADV
tADS
tADVS
tADH
tAS
tADVH
WD2
ADD
GW
RD1
RD3
tAH
tWS
tWS
tWH
WE
tCES
tCEH
tWH
CE1 masks ADSP
CE1
CE2
tCES
tCEH
CE3
OE
tCES
tEOV
tCEH
tEOHZ
tDS
tDH
Double-Cycle
Deselect
tDOH
tEOLZ
tCO
2a
Out
3b
Out
3c
Out
3a
Out
3d
Out
Data In/Out
1a
2a
In
Out
tCHZ
= UNDEFINED
= DON’T CARE
Document #: 38-05253 Rev. *A
Page 22 of 28
CY7C1387BV25
CY7C1386BV25
Switching Waveforms (continued)
OE Switching Waveforms
OE
tEOV
tEOHZ
Three-state
tEOLZ
I/Os
ZZ Mode Timing [4, 21, 22]
CLK
ADSP
HIGH
ADSC
CE1
LOW
HIGH
CE2
CE3
ZZ
tZZS
IDD
IDD(active)
tZZREC
IDDZZ
I/Os
Three-state
Notes:
21. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device.
22. I/Os are in three-state when exiting ZZ sleep mode.
Document #: 38-05253 Rev. *A
Page 23 of 28
CY7C1387BV25
CY7C1386BV25
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
200
167
150
133
200
167
150
133
200
167
150
133
200
167
150
133
200
167
150
133
200
167
150
133
167
150
133
167
150
133
167
150
133
167
150
133
167
150
133
167
150
133
Ordering Code
Package Type
CY7C1386BV25-200AC
CY7C1386BV25-167AC
CY7C1386BV25-150AC
CY7C1386BV25-133AC
CY7C1387BV25-200AC
CY7C1387BV25-167AC
CY7C1387BV25-150AC
CY7C1387BV25-133AC
CY7C1386BV25-200BGC
CY7C1386BV25-167BGC
CY7C1386BV25-150BGC
CY7C1386BV25-133BGC
CY7C1387BV25-200BGC
CY7C1387BV25-167 BGC
CY7C1387BV25-150BGC
CY7C1387BV25-133BGC
CY7C1386B-200BZC
A101
BG119
BB165A
100-lead Thin Quad Flat Pack
Commercial
Commercial
Commercial
119-ball BGA
165-ball FBGA
CY7C1386BV25-167BZC
CY7C1386BV25-150BZC
CY7C1386BV25-133BZC
CY7C1387B-200BZC
CY7C1387BV25-167BZC
CY7C1387BV25-150BZC
CY7C1387BV25-133BZC
CY7C1386BV25-167AI
CY7C1386BV25-150AI
CY7C1386BV25-133AI
CY7C1387BV25-167AI
CY7C1387BV25-150AI
CY7C1387BV25-133AI
CY7C1386BV25-167BGI
CY7C1386BV25-150BGI
CY7C1386BV25-133BGI
CY7C1387BV25-167BGI
CY7C1387BV25-150BGI
CY7C1387BV25-133BGI
CY7C1386BV25-167BZI
CY7C1386BV25-150BZI
CY7C1386BV25-133BZI
CY7C1387BV25-167BZI
CY7C1387BV25-150BZI
CY7C1387BV25-133BZI
A101
BG119
BB165A
100-lead Thin Quad Flat Pack
Industrial
Industrial
Industrial
119-ball BGA
165-ball FBGA
Shaded areas contain advance information.
Document #: 38-05253 Rev. *A
Page 24 of 28
CY7C1387BV25
CY7C1386BV25
Package Diagrams
100-pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A101
51-85050-A
Document #: 38-05253 Rev. *A
Page 25 of 28
CY7C1387BV25
CY7C1386BV25
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*A
Document #: 38-05253 Rev. *A
Page 26 of 28
CY7C1387BV25
CY7C1386BV25
Package Diagrams (continued)
165-Ball FBGA (13 x 15 x 1.2 mm) BB165A
51-85122-*B
Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document
are the trademarks of their respective holders.
Document #: 38-05253 Rev. *A
Page 27 of 28
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1387BV25
CY7C1386BV25
Document Title: CY7C1386BV25/CY7C1387BV25 512K x 36 / 1M x 18 Pipelined DCD SRAM
Document Number: 38-05253
Orig. of
Change
REV.
ECN No.
Issue Date
Description of Change
**
113655
05/03/02
CJM
Changed Spec number from: 38-01119 to 38-05253
Added ZZ mode function in “Features”
Changed tDOH to 1.3 ns for all speeds
Added I-temp offering
Changed ISB values to reflect new char. values
Added 165-ball fBGA packaging
Added Thermal Resistance values
Changed VOH and VOL values to reflect char. values
Changed tEOHZ to 4.0 ns for 200 and 167 Mhz
Changes tEOV to char. values
Changed ESD voltage to 1500V
Changed tCLZ from 0 to 1.3 ns for all speeds
*A
123133
01/18/03
RBI
Add power up requirements to operating range information
Document #: 38-05253 Rev. *A
Page 28 of 28
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