CY7C1386C-167BGC [CYPRESS]
18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM; 18 -MB （ 512K ×36 / 1M ×18 ）流水线DCD同步SRAM
| 型号： | CY7C1386C-167BGC |
| 厂家： | 
CYPRESS |
| 描述： | 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM |
| 文件： | 总34页 (文件大小：553K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1386C
CY7C1387C
18-Mb (512K x 36/1M x 18) Pipelined DCD
Sync SRAM
Features
Functional Description[1]
• Supports bus operation up to 250 MHz
The CY7C1386C/CY7C1387C SRAM integrates 524,288 x 36
and 1048,576 x 18 SRAM cells with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. All synchronous inputs are gated by registers
controlled by a positive-edge-triggered Clock Input (CLK). The
synchronous inputs include all addresses, all data inputs,
• Available speed grades are 250, 225, 200 and 167 MHz
• Registered inputs and outputs for pipelined operation
• Optimal for performance (Double-Cycle deselect)
• Depth expansion without wait state
• 3.3V –5% and +10% core power supply (VDD
• 2.5V / 3.3V I/O operation
address-pipelining Chip Enable (
), depth-expansion Chip
CE1
[2]
)
Enables (CE and
), Burst Control inputs (
,
,
CE3
2
ADSC ADSP
), Write Enables (
, and
BWX
), and Global Write
and
ADV
BWE
(
). Asynchronous inputs include the Output Enable (
)
OE
GW
• Fast clock-to-output times
and the ZZ pin.
— 2.6 ns (for 250-MHz device)
— 2.8 ns (for 225-MHz device)
— 3.0 ns (for 200-MHz device)
— 3.4 ns (for 167-MHz device)
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor ( ) or
ADSP
) are active. Subsequent
Address Strobe Controller (
ADSC
burst addresses can be internally generated as controlled by
the Advance pin ( ).
ADV
• Provide high-performance 3-1-1-1 access rate
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
• User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
controlled by the byte write control inputs.
active
GW
LOW
This device incorporates an
causes all bytes to be written.
additional pipelined enable register which delays turning off
the output buffers an additional cycle when a deselect is
executed.This feature allows depth expansion without penal-
izing system performance.
• Asynchronous output enable
• Offered in JEDEC-standard 100-pin TQFP, 119-ball BGA
and 165-Ball fBGA packages
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• “ZZ” Sleep Mode Option
The CY7C1386C/CY7C1387C operates from a +3.3V core
power supply while all outputs operate with a +3.3V or a +2.5V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
Selection Guide
250 MHz
225 MHz
2.8
200 MHz
3.0
167 MHz
3.4
Unit
ns
mA
mA
Maximum Access Time
Maximum Operating Current
2.6
350
70
325
70
300
70
275
70
Maximum CMOS Standby Current
Shaded areas contain advance information.
Please contact your local Cypress sales representative for availability of these parts.
Notes:
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
2. CE and CE are for TQFP and 165 fBGA package only. 119 BGA is offered only in Single Chip Enable.
3
2
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05239 Rev. *B
Revised February 26, 2004
CY7C1386C
CY7C1387C
1
Logic Block Diagram – CY7C1386C (512K x 36)
ADDRESS
A0,A1,A
REGISTER
2
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQD,DQP
D
DQD,DQP
D
BYTE
BYTE
BW
D
WRITE REGISTER
WRITE DRIVER
DQ
BYTE
WRITE DRIVER
c,DQPC
DQ
BYTE
WRITE REGISTER
c,DQPC
MEMORY
ARRAY
BW
C
OUTPUT
BUFFERS
OUTPUT
REGISTERS
SENSE
AMPS
DQs
DQP
DQP
DQP
A
DQ
BYTE
WRITE DRIVER
B,DQPB
E
DQ
BYTE
WRITE REGISTER
B,DQPB
B
C
BW
BW
B
A
DQP
D
DQA,DQP
A
DQA,DQP
A
BYTE
WRITE DRIVER
BYTE
WRITE REGISTER
BWE
INPUT
REGISTERS
GW
ENABLE
REGISTER
PIPELINED
ENABLE
CE
CE
CE
1
2
3
OE
SLEEP
ZZ
CONTROL
2
Logic Block Diagram – CY7C1387C (1M x 18)
ADDRESS
REGISTER
A0, A1, A
2
A[1:0]
MODE
Q1
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQB , DQP
BYTE
WRITE DRIVER
B
DQB, DQP
BYTE
WRITE REGISTER
B
OUTPUT
BUFFERS
BW
B
A
OUTPUT
REGISTERS
DQs,
DQP
DQP
SENSE
AMPS
MEMORY
ARRAY
A
DQA, DQP
BYTE
WRITE DRIVER
A
B
E
DQA , DQP
BYTE
WRITE REGISTER
A
BW
BWE
GW
INPUT
REGISTERS
ENABLE
REGISTER
CE
CE
CE
1
PIPELINED
ENABLE
2
3
OE
SLEEP
ZZ
CONTROL
Document #: 38-05239 Rev. *B
Page 2 of 34
CY7C1386C
CY7C1387C
Pin Configurations
100-pin TQFP Pinout (3 Chip Enables)
DQPC
1
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
A
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQC
2
NC
2
DQC
3
NC
NC
3
VDDQ
4
5
VDDQ
VSSQ
NC
VDDQ
VSSQ
NC
4
VSSQ
5
DQC
6
6
DQC
7
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
7
DQC
8
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
8
DQC
9
9
VSSQ
10
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VDDQ
11
DQC
12
DQC
13
NC
14
VDD
15
NC
VDD
NC
CY7C1387C
(1M x 18)
CY7C1386C
(512K X 36)
NC
16
VDD
ZZ
VDD
ZZ
VSS
17
VSS
DQD
18
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
DQD
19
VDDQ
20
VSSQ
21
DQD
22
DQD
23
DQD
24
DQD
25
NC
VSSQ
26
VSSQ
VDDQ
NC
VSSQ
VDDQ
NC
VDDQ
27
DQD
28
DQD
29
NC
NC
DQPD
30
NC
NC
Document #: 38-05239 Rev. *B
Page 3 of 34
CY7C1386C
CY7C1387C
Pin Configurations (continued)
119-ball BGA (1 Chip Enable with JTAG)
CY7C1386C (512K x 36)
1
2
3
4
5
6
7
VDDQ
A
A
A
A
A
A
VDDQ
A
B
C
ADSP
ADSC
VDD
NC
NC
A
A
A
A
A
A
NC
NC
DQC
DQC
VDDQ
DQPC
DQC
DQC
VSS
VSS
VSS
NC
CE1
VSS
VSS
VSS
DQPB
DQB
DQB
DQB
DQB
VDDQ
D
E
F
OE
DQC
DQC
VDDQ
DQD
DQD
VDDQ
DQD
DQC
DQC
VDD
BWC
VSS
NC
BWB
VSS
NC
DQB
DQB
VDD
DQA
DQA
DQA
DQA
DQB
DQB
VDDQ
DQA
DQA
VDDQ
DQA
G
H
J
ADV
GW
VDD
CLK
NC
BWE
A1
DQD
VSS
VSS
K
L
M
N
DQD
DQD
DQD
BWD
VSS
VSS
BWA
VSS
VSS
P
R
DQD
NC
DQPD
A
VSS
MODE
A0
VDD
VSS
NC
DQPA
A
DQA
NC
T
U
NC
VDDQ
NC
TMS
A
TDI
A
TCK
A
TDO
NC
NC
ZZ
VDDQ
CY7C1387C (1M x 18)
2
A
A
1
3
A
A
4
5
A
A
6
A
A
7
A
B
C
D
E
F
VDDQ
NC
NC
VDDQ
NC
NC
ADSP
ADSC
VDD
A
A
A
A
DQB
NC
VDDQ
NC
DQB
NC
VSS
VSS
VSS
NC
CE1
OE
VSS
VSS
VSS
DQPA
NC
DQA
NC
DQA
VDDQ
G
H
J
NC
DQB
VDDQ
DQB
NC
VDD
VSS
VSS
NC
NC
DQA
VDD
DQA
NC
VDDQ
BWB
VSS
NC
ADV
GW
VDD
NC
DQB
VSS
CLK
NC
BWE
A1
VSS
NC
DQA
NC
DQA
NC
DQA
K
L
M
N
P
DQB
VDDQ
DQB
NC
NC
DQB
NC
VSS
VSS
VSS
VSS
NC
VDDQ
NC
BWA
VSS
VSS
VSS
DQPB
A0
DQA
R
T
NC
NC
A
A
MODE
A
VDD
NC
NC
A
A
A
NC
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Document #: 38-05239 Rev. *B
Page 4 of 34
CY7C1386C
CY7C1387C
Pin Configurations (continued)
165-ball fBGA (3 Chip Enable)
CY7C1386C (512K x 36)
1
NC / 288M
NC
DQPC
DQC
2
A
A
NC
DQC
DQC
DQC
DQC
VSS
3
4
5
6
7
8
9
10
11
NC
NC / 144M
DQPB
DQB
A
A
B
C
D
E
F
G
H
J
K
L
CE1
BWC
BWD
VSS
VDD
BWB
BWA
VSS
VSS
CE3
CLK
VSS
VSS
ADSC
BWE
GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
ADV
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
A
NC
DQB
DQB
DQB
DQB
NC
DQA
DQA
DQA
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
DQC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DQB
DQC
DQC
NC
DQD
DQD
DQD
DQB
DQB
ZZ
DQA
DQA
DQA
DQD
DQD
DQD
VDDQ
VDDQ
VDDQ
DQD
DQPD
NC
DQD
NC
NC / 72M
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
TDI
VSS
A
A1
VSS
NC
TDO
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
DQA
DQPA
A
M
N
P
A0
MODE NC / 36M
A
A
TMS
TCK
A
A
A
A
R
CY7C1387C (1M x 18)
1
NC / 288M
NC
2
3
CE1
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
4
BWB
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
5
6
7
8
9
10
11
A
A
NC
A
A
CE
BWE
GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
ADSC
OE
VSS
ADV
ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
3
A
NC
DQB
DQB
DQB
DQB
VSS
NC
NC
NC
BWA
VSS
VSS
VSS
VSS
VSS
VSS
‘VSS
VSS
VSS
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A
NC
NC
NC
NC
NC
NC / 144M
DQPA
DQA
B
C
D
E
F
G
H
J
K
L
NC
NC
NC
NC
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
DQA
DQA
DQA
ZZ
NC
NC
NC
NC
DQB
DQB
DQB
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQA
DQA
DQA
NC
DQB
DQPB
NC
NC
NC
NC / 72M
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
TDI
VSS
A
A1
A0
VSS
NC
TDO
VDD
VSS
A
VDDQ
VDDQ
A
DQA
NC
A
NC
NC
A
M
N
P
MODE NC / 36M
A
A
TMS
TCK
A
A
A
A
R
Document #: 38-05239 Rev. *B
Page 5 of 34
CY7C1386C
CY7C1387C
CY7C1386C–Pin Definitions
BGA
(1 Chip
Name
TQFP
Enable)
fBGA
I/O
Description
Address Inputs used to select one of the 512K
A0, A1 , A 37,36,32,33, P4,N4,A2,
R6,P6,A2,
Input-
34,35,42,43, B2,C2,R2, A10,B2,B10, Synchronous address locations. Sampled at the rising edge of the
44,45,46,47, 3A,B3,C3, N6,P3,P4,P8,
48,49,50,81, T3,T4,A5, P9,P10,P11,
82,99,100 B5,C5,T5, R3,R4,R8,R9,
CLK if
or
is active LOW, and CE , CE ,
ADSP ADSC
2
and CE3 [2]are sampled active. A1: A0 are fed1to the
two-bit counter.
.
A6,B6,C6,
R6
R10,R11
93,94,95,96 L5,G5,G3, B5,A5,A4,B4
L3
Input-
Byte Write Select Inputs, active LOW. Qualified with
BWE to conduct byte writes to the SRAM. Sampled on
the rising edge of CLK.
BWA,BWB
BWC,BWD
Synchronous
H4
B7
Input-
Global Write Enable Input, active LOW. When
88
GW
Synchronous asserted LOW on the rising edge of CLK, a global write
is conducted (ALL bytes are written, regardless of the
values on BWX and BWE).
87
89
98
M4
K4
E4
A7
B6
A3
Input-
Byte Write Enable Input, active LOW. Sampled on the
BWE
CLK
Synchronous rising edge of CLK. This signal must be asserted LOW
to conduct a byte write.
Input-
Clock
Clock Input. Used to capture all synchronous inputs to
the device. Also used to increment the burst counter
when ADV is asserted LOW, during a burst operation.
Input-
Chip Enable 1 Input, active LOW. Sampled on the
CE1
Synchronous rising edge of CLK. Used in conjunction with CE2 and
CE3[2] to select/deselect the device. ADSP is ignored if
CE1 is HIGH.
[2]
CE2
97
92
-
-
B3
A6
Input-
Chip Enable 2 Input, active HIGH. Sampled on the
Synchronous rising edge of CLK. Used in conjunction with CE1 and
CE3[2] to select/deselect the device.
Input-
Chip Enable 3 Input, active LOW. Sampled on the
[2]
CE3
Synchronous rising edge of CLK. Used in conjunction with CE1 and
CE to select/deselect the device.
Not connected for
BG2A. Where referenced, CE3[2] is assumed active
throughout this document for BGA.
86
F4
B8
Input-
Output Enable, asynchronous input, active LOW.
OE
Asynchronous Controls the direction of the I/O pins. When LOW, the
I/O pins behave as outputs. When deasserted HIGH,
DQ pins are tri-stated, and act as input data pins. OE is
masked during the first clock of a read cycle when
emerging from a deselected state.
83
84
G4
A4
A9
B9
Input-
Advance Input signal, sampled on the rising edge of
ADV
Synchronous CLK, active LOW. When asserted, it automatically
increments the address in a burst cycle.
Input-
Address Strobe from Processor, sampled on the
ADSP
Synchronous rising edge of CLK, active LOW. When asserted LOW,
addresses presented to the device are captured in the
address registers. A1: A0 are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only
ADSP is recognized. ASDP is ignored when CE1 is
deasserted HIGH.
Document #: 38-05239 Rev. *B
Page 6 of 34
CY7C1386C
CY7C1387C
CY7C1386C–Pin Definitions (continued)
BGA
(1 Chip
Name
ADSC
TQFP
Enable)
fBGA
I/O
Description
Address Strobe from Controller, sampled on the
B4
A8
Input-
85
Synchronous rising edge of CLK, active LOW. When asserted LOW,
addresses presented to the device are captured in the
address registers. A1: A0 are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only
ADSP is recognized.
ZZ
64
T7
H11
Input-
ZZ “sleep” Input, active HIGH. When asserted HIGH
Asynchronous places the device in a non-time-critical “sleep” condition
with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal
pull-down.
52,53,56,57, K6,L6,M6, M11,L11,K11,
I/O-
Bidirectional Data I/O lines. As inputs, they feed into
DQs, DQPs
58,59,62,63, N6,K7,L7, J11,J10,K10, Synchronous an on-chip data register that is triggered by the rising
68,69,72,73, N7,P7,E6, L10,M10,D10
74,75,78,79, F6,G6,H6, ,E10,F10,G10
2,3,6,7,8,9, D7,E7,G7, ,D11,E11,F11,
12,13,18,19, H7,D1,E1, G11,D1,E1,
22,23,24,25, G1,H1,E2, F1,G1,D2,E2,
28,29,51,80, F2,G2,H2, F2,G2,J1,K1,
edge of CLK. As outputs, they deliver the data contained
in the memory location specified by the addresses
presented during the previous
clock rise of the read
cycle. The direction of the pins is controlled by OE.
When OE is asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQPX are placed in a tri-state
condition.
1,30
K1,L1,N1, L1,M1,J2,K2,
P1,K2,L2, L2,M2,N11,
M2,N2,P6, C11,C1,N1
D6,D2,P2
VDD
15,41,65,91 J2,C4,J4, D4,D8,E4,E8, Power Supply Power supply inputs to the core of the device.
R4,J6
F4,F8,G4,G8,
H4,H8,J4,J8,
K4,K8,L4,L8,
M4,M8
VSS
17,40,67,90 D3,E3,F3, C4,C5,C6,C7,
H3,K3,M3, C8,D5,D6,D7,
N3,P3,D5, E5,E6,E7,F5,
Ground
Ground for the core of the device.
E5,F5,H5, F6,F7,G5,G6,
K5,M5,N5, G7,H2,H5,H6
P5
,H7,J5,J6,J7,
K5,K6,K7,L5,
L6,L7,M5,M6,
M7,N4,N8
VSSQ
VDDQ
5,10,21,26,
55,60,71,76
-
-
I/O Ground Ground for the I/O circuitry.
4,11,20,27, A1,F1,J1, C3,C9,D3,D9, I/O Power Sup- Power supply for the I/O circuitry.
54,61,70,77 M1,U1,A7, E3,E9,F3,F9,
F7,J7,M7, G3,G9,J3,J9,
ply
U7
K3,K9,L3,L9,
M3,M9,N3,N9
MODE
TDO
31
-
R3
R1
P7
Input-
Static
Selects Burst Order. When tied to GND selects linear
burst sequence. When tied to VDD or left floating selects
interleaved burst sequence. This is a strap pin and
should remain static during device operation. Mode Pin
has an internal pull-up.
U5
JTAG serial Serial data-out to the JTAG circuit. Delivers data on
output
the negative edge of TCK. If the JTAG feature is not
being utilized, this pin should be disconnected. This pin
is not available on TQFP packages.
Synchronous
Document #: 38-05239 Rev. *B
Page 7 of 34
CY7C1386C
CY7C1387C
CY7C1386C–Pin Definitions (continued)
BGA
(1 Chip
Name
TDI
TQFP
Enable)
fBGA
I/O
Description
-
U3
P5
JTAG serial Serial data-In to the JTAG circuit. Sampled on the
input rising edge of TCK. If the JTAG feature is not being
Synchronous utilized, this pin can be disconnected or connected to
DD. This pin is not available on TQFP packages.
V
TMS
-
-
U2
U4
R5
R7
JTAG serial Serial data-In to the JTAG circuit. Sampled on the
input rising edge of TCK. If the JTAG feature is not being
Synchronous utilized, this pin can be disconnected or connected to
DD. This pin is not available on TQFP packages.
V
TCK
NC
JTAG-Clock Clock input to the JTAG circuitry. If the JTAG feature
is not being utilized, this pin must be connected to VSS
.
This pin is not available on TQFP packages.
14,16,66,39, B1,C1,R1, A11,B1,C2,
-
No Connects. Not internally connected to the die
38
T1,T2,J3, C10,H1,H3,
D4,L4,5J, H9,H10,N2,
5R,6T,6U, N5,N7,N10,
B7,C7,R7 P1,A1,B11,
P2,R2
CY7C1387C:Pin Definitions
BGA
(2-Chip
Name
TQFP
Enable)
fBGA
I/O
Description
A0, A1 , A 37,36,32,33, P4,N4,A2, R6,P6,A2,
Input-
Address Inputs used to select one of the 1M address
34,35,42,43, B2,C2,R2, A10,A11,B2, Synchronous locations. Sampled at the rising edge of the CLK if
44,45,46,47, T2,A3,B3, B10,N6,P3,
48,49,50,80, C3,T3,A5, P4,P8,P9,
81,82,99, B5,C5,T5, P10,P11,R3,
or
is active LOW, and CE , CE , and
ADSP ADSC
1
CE3[2] are sampled active. A1: A0 are fed to t2he two-bit
counter.
100
A6,B6,C6, R4,R8,R9,
R6,T6
G3,L5
R10,R11
B5,A4
93,94
Input-
Byte Write Select Inputs, active LOW. Qualified with
BWA,BWB
GW
Synchronous
BWE to conduct byte writes to the SRAM. Sampled on
.
the rising edge of CLK
H4
B7
Input-
Global Write Enable Input, active LOW. When
88
Synchronous asserted LOW on the rising edge of CLK, a global write
is conducted (ALL bytes are written, regardless of the
values on BWX and BWE).
87
89
98
M4
K4
E4
A7
B6
A3
Input-
Byte Write Enable Input, active LOW. Sampled on the
BWE
CLK
Synchronous rising edge of CLK. This signal must be asserted LOW
to conduct a byte write.
Input-
Clock
Clock Input. Used to capture all synchronous inputs to
the device. Also used to increment the burst counter
when ADV is asserted LOW, during a burst operation.
Input-
Chip Enable 1 Input, active LOW. Sampled on the
CE1
Synchronous rising edge of CLK. Used in conjunction with CE2 and
CE3[2] to select/deselect the device. ADSP is ignored if
CE1 is HIGH.
[2]
CE2
97
-
B3
Input-
Chip Enable 2 Input, active HIGH. Sampled on the
Synchronous rising edge of CLK. Used in conjunction with CE1 and
CE3[2] to select/deselect the device.
Document #: 38-05239 Rev. *B
Page 8 of 34
CY7C1386C
CY7C1387C
CY7C1387C:Pin Definitions (continued)
BGA
(2-Chip
Name
TQFP
Enable)
fBGA
I/O
Description
Chip Enable 3 Input, active LOW. Sampled on the
92
-
A6
Input-
[2]
CE3
Synchronous rising edge of CLK. Used in conjunction with CE1 and
CE to select/deselect the device.
Not connected for
BG2A. Where referenced, CE3[2] is assumed active
throughout this document for BGA.
86
F4
B8
Input-
Output Enable, asynchronous input, active LOW.
OE
Asynchronous Controls the direction of the I/O pins. When LOW, the
I/O pins behave as outputs. When deasserted HIGH,
DQ pins are tri-stated, and act as input data pins. OE is
masked during the first clock of a read cycle when
emerging from a deselected state.
83
84
G4
A4
A9
B9
Input-
Advance Input signal, sampled on the rising edge of
ADV
Synchronous CLK, active LOW. When asserted, it automatically
increments the address in a burst cycle.
Input-
Address Strobe from Processor, sampled on the
ADSP
Synchronous rising edge of CLK, active LOW. When asserted LOW,
addresses presented to the device are captured in the
address registers. A1: A0 are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only
ADSP is recognized. ASDP is ignored when CE1 is
deasserted HIGH.
P4
T7
A8
Input-
Address Strobe from Controller, sampled on the
85
64
ADSC
Synchronous rising edge of CLK, active LOW. When asserted LOW,
addresses presented to the device are captured in the
address registers. A1: A0 are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only
ADSP is recognized.
ZZ
H11
Input-
ZZ “sleep” Input, active HIGH. When asserted HIGH
Asynchronous places the device in a non-time-critical “sleep” condition
with data integrity preserved. For normal operation, this
pin has to be LOW or left floating. ZZ pin has an internal
pull-down.
58,59,62,63, P7,K7,G7, J10,K10,L10,
I/O-
Bidirectional Data I/O lines. As inputs, they feed into
DQs, DQPs
68,69,72,73, E7,F6,H6,
M10,D11,
Synchronous an on-chip data register that is triggered by the rising
edge of CLK. As outputs, they deliver the data contained
in the memory location specified by the addresses
8,9,12,13,18 L6,N6,D1, E11,F11,G11
,19,22,23,74 H1,L1,N1, ,J1,K1,L1,M1
,24
E2,G2,K2, ,D2,E2,F2,
M2,D6,P2 G2,C11,N1
presented during the previous
clock rise of the read
cycle. The direction of the pins is controlled by OE.
When OE is asserted LOW, the pins behave as outputs.
When HIGH, DQs and DQPX are placed in a tri-state
condition.
VDD
15,41,65,91 C4,J2,J4, D4,D8,E4,E8 Power Supply Power supply inputs to the core of the device.
J6,R4
,F4,F8,G4,
G8,H4,H8,J4
,J8,K4,K8,L4
,L8,M4,M8
Document #: 38-05239 Rev. *B
Page 9 of 34
CY7C1386C
CY7C1387C
CY7C1387C:Pin Definitions (continued)
BGA
(2-Chip
Name
VSS
TQFP
Enable)
fBGA
I/O
Description
Ground for the core of the device.
17,40,67,90 D3,D5,E5, H2,C4,C5,C6
E3,F3,F5, ,C7,C8,D5,
G5,H3,H5, D6,D7,E5,E6
K3,K5,L3, ,E7,F5,F6,F7
M3,M5,N3, ,G5,G6,G7,
N5,P3,P5 H5,H6,H7,J5
,J6,J7,K5,K6,
Ground
K7,L5,L6,L7,
M5,M6,M7,
N4,N8
VSSQ
VDDQ
5,10,21,26,
55,60,71,76
-
-
I/O Ground
Ground for the I/O circuitry.
4,11,20,27, A1,A7,F1, C3,C9,D3,D9 I/O Power Sup- Power supply for the I/O circuitry.
54,61,70,77 F7,J1,J7, ,E3,E9,F3,F9
M1,M7,U1, ,G3,G9,J3,J9
ply
U7
,K3,K9,L3,L9
,M3,M9,N3,
N9
MODE
31
R3
R1
Input-
Static
Selects Burst Order. When tied to GND selects linear
burst sequence. When tied to VDD or left floating selects
interleaved burst sequence. This is a strap pin and
should remain static during device operation. Mode Pin
has an internal pull-up.
TDO
TDI
-
-
U5
U3
P7
P5
JTAG serial out- Serial data-out to the JTAG circuit. Delivers data on
put
the negative edge of TCK. If the JTAG feature is not
being utilized, this pin should be left unconnected. This
pin is not available on TQFP packages.
Synchronous
JTAG serial Serial data-In to the JTAG circuit. Sampled on the
input
rising edge of TCK. If the JTAG feature is not being uti-
Synchronous lized, this pin can be left floating or connected to VDD
through a pull up resistor. This pin is not available on
TQFP packages.
TMS
-
-
U2
U4
R5
R7
JTAG serial Serial data-In to the JTAG circuit. Sampled on the
input
rising edge of TCK. If the JTAG feature is not being uti-
Synchronous lized, this pin can be disconnected or connected to VDD
.
This pin is not available on TQFP packages.
TCK
NC
JTAG-Clock Clock input to the JTAG circuitry. If the JTAG feature
is not being utilized, this pin must be connected to VSS
.
This pin is not available on TQFP packages.
1,2,3,6,7,14, B1,B7,C1, A5,B1,B4,C1
16,25,28,29, C7,D2,D4, ,C2,C10,D1,
30,38,39,51, D7,E1,E6, D10,E1,E10,
52,53,56,57, H2,F2,G1, F1,F10,G1,
66,75,78,79, G6,H7,J3, G10,H1,H3,
-
No Connects. Not internally connected to the die.
95,96
J5,K1,K6, H9,H10,J2,
L4,L2,L7, J11,K2,K11,
M6,N2,L7, L2,L1,M2,
P1,P6,R1, M11,N2,N10,
R5,R7,T1, N5,N7,N11,
T4,U6
P1,A1,B11,
P2,R2
Document #: 38-05239 Rev. *B
Page 10 of 34
CY7C1386C
CY7C1387C
The write signals (GW, BWE, and
ignored during this first cycle.
) and ADV inputs are
BWX
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
The CY7C1386C/CY7C1387C supports secondary cache in
systems utilizing either a linear or interleaved burst sequence.
The interleaved burst order supports Pentium and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the corre-
sponding address location in the memory core. If GW is HIGH,
then the write operation is controlled by BWE and
BWX
signals. The CY7C1386C/CY7C1387C provides byte write
capability that is described in the Write Cycle Description table.
Asserting the Byte Write Enable input (BWE) with the selected
Byte Write input will selectively write to only the desired bytes.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Accesses can
Strobe (ADSP)
be initiated with either the Processor Address
or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Because the CY7C1386C/CY7C1387C is a common I/O
device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQ inputs. Doing so will tri-state
the output drivers. As a safety precaution, DQ are automati-
cally tri-stated whenever a write cycle is detected, regardless
of the state of OE.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
Single Write Accesses Initiated by ADSC
self-timed write circuitry.
synchronous
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) chip select is asserted active, and (4)
the appropriate combination of the write inputs (GW, BWE,
[2]
Synchronous Chip Selects CE1, CE2, CE3
and an
asynchronous Output Enable (OE) provide for easy bank
output tri-state control.
is ignored if
CE1
selection and
is HIGH.
ADSP
and
) are asserted active to conduct a write to the desired
BWX
byte(s). ADSC triggered write accesses require a single clock
cycle to complete. The address presented is loaded into the
address register and the address advancement logic while
being delivered to the memory core. The ADV input is ignored
during this cycle. If a global write is conducted, the data
presented to the DQX is written into the corresponding address
location in the memory core. If a byte write is conducted, only
the selected bytes are written. Bytes not selected during a byte
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
chip selects are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The corre-
sponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within tco if OE is active LOW. The only exception
occurs when the SRAM is emerging from a deselected state
to a selected state, its outputs are always tri-stated during the
first cycle of the access. After the first cycle of the access, the
outputs are controlled by the OE signal. Consecutive single
read cycles are supported.
write operation will remain unaltered.
A synchronous
self-timed write mechanism has been provided to simplify the
write operations.
Because the CY7C1386C/CY7C1387C is a common I/O
device, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQX inputs. Doing so will tri-state
the output drivers. As a safety precaution, DQX are automati-
cally tri-stated whenever a write cycle is detected, regardless
of the state of OE.
Burst Sequences
The CY7C1386C/CY7C1387C is a double-cycle deselect part.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will tri-state
immediately after the next clock rise.
The CY7C1386C/CY7C1387CCY7C1387C provides a two-bit
wraparound counter, fed by A[1:0], that implements either an
interleaved or linear burst sequence. The interleaved burst
sequence is designed specifically to support Intel® Pentium
applications. The linear burst sequence is designed to support
processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input. Both
read and write burst operations are supported.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
chip select is asserted active. The address presented is
loaded into the address register and the address
advancement logic while being delivered to the memory core.
Document #: 38-05239 Rev. *B
Page 11 of 34
CY7C1386C
CY7C1387C
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
Interleaved Burst Address Table
(MODE = Floating or VDD
)
First
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
Address
A1: A0
LOW
.
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table
(MODE = GND)
First
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
.
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
Description
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to snooze current
ZZ Inactive to exit snooze current
Test Conditions
ZZ > VDD – 0.2V
ZZ > VDD – 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
Max.
60
2tCYC
Unit
mA
ns
ns
ns
2tCYC
0
2tCYC
tRZZI
ns
Truth Table[ 3, 4, 5, 6, 7, 8]
Operation
Add. Used
None
CE2
X
L
X
L
CE3
WRITE
CLK
DQ
CE1
H
L
L
L
L
X
L
L
L
L
L
X
X
H
ZZ ADSP ADSC ADV
OE
X
X
X
X
X
X
L
H
X
L
H
L
Deselect Cycle,Power Down
Deselect Cycle,Power Down
Deselect Cycle,Power Down
Deselect Cycle,Power Down
Deselect Cycle,Power Down
Snooze Mode,Power Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
X
X
H
X
H
X
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
X
L
L
H
H
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
H
H
H
H
H
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
L-H Tri-State
X
L-H
L-H Tri-State
L-H
L-H
None
None
None
None
X
X
L
None
X
X
X
L
L
L
H
H
H
Tri-State
Q
External
External
External
External
External
Next
H
H
H
H
H
X
L
H
H
H
H
H
X
D
Q
L-H Tri-State
L-H
L-H Tri-State
L-H
X
X
X
Q
Next
Next
X
X
L
L
H
L
Q
Document #: 38-05239 Rev. *B
Page 12 of 34
CY7C1386C
CY7C1387C
Truth Table[ 3, 4, 5, 6, 7, 8]
Operation
Add. Used
Next
CE2
X
X
X
X
X
X
X
X
CE3
X
X
X
X
X
X
X
X
WRITE
CLK
L-H Tri-State
DQ
CE1
H
ZZ ADSP ADSC ADV
OE
H
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle,Suspend Burst
L
L
L
L
L
L
L
L
L
X
H
X
H
H
X
X
H
X
H
H
H
H
H
H
H
H
H
L
L
L
H
H
H
H
H
H
H
L
L
H
H
H
H
L
Next
Next
X
H
X
X
H
H
X
H
X
X
L
H
L
H
X
X
L-H
L-H
L-H
L-H Tri-State
L-H
L-H Tri-State
D
D
Q
Current
Current
Current
Current
Current
Current
Q
L-H
L-H
D
D
WRITE Cycle,Suspend Burst
X
X
L
Notes:
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW= L. WRITE = H when all Byte write enable signals , BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the signal. is asynchronous and is not sampled with the clock.
OE
OE
7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW . Writes may occur only on subsequent clocks
6. CE , CE , and CE are available only in the TQFP package. BGA package has only 2 chip selects CE and CE .
1
2
3
1
2
X
after the
or with the assertion of
. As a result,
ADSC
must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state.
is a
OE
OE
ADSP
don't care for the remainder of the write cycle
8.
is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are Tri-State when
is
OE
OE
.
is active (LOW)
inactive or when the device is deselected, and all data bits behave as output when
OE
9. Table only lists a partial listing of the byte write combinations. Any Combination of BW is valid Appropriate write will be done based on which byte write is active.
X
Partial Truth Table for Read/Write[5, 9]
Function (CY7C1386C)
BWD
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
X
BWC
X
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
BWB
X
H
H
L
BWA
X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
GW
BWE
Read
Read
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
Write Byte A – ( DQA and DQPA )
Write Byte B – ( DQB and DQPB )
Write Bytes B, A
Write Byte C – ( DQC and DQPC )
Write Bytes C, A
Write Bytes C, B
Write Bytes C, B, A
Write Byte D – ( DQD and DQPD )
Write Bytes D, A
Write Bytes D, B
Write Bytes D, B, A
Write Bytes D, C
L
H
H
L
L
H
H
L
L
H
H
L
L
X
Write Bytes D, C, A
Write Bytes D, C, B
Write All Bytes
L
X
Write All Bytes
X
Truth Table for Read/Write[5]
Function (CY7C1387C)
BWB
X
H
H
L
L
X
BWA
GW
BWE
Read
Read
H
H
L
L
L
L
X
X
H
L
H
L
H
H
H
H
L
Write Byte A – ( DQA and DQPA )
Write Byte B – ( DQB and DQPB )
Write All Bytes
Write All Bytes
X
Document #: 38-05239 Rev. *B
Page 13 of 34
CY7C1386C
CY7C1387C
Test MODE SELECT (TMS)
IEEE 1149.1 Serial Boundary Scan (JTAG)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
The CY7C1386C/CY7C1387C incorporates a serial boundary
scan test access port (TAP). This port operates in accordance
with IEEE Standard 1149.1-1990 but does not have the set of
functions required for full 1149.1 compliance. These functions
from the IEEE specification are excluded because their
inclusion places an added delay in the critical speed path of
the SRAM. Note that the TAP controller functions in a manner
that does not conflict with the operation of other devices using
1149.1 fully compliant TAPs. The TAP operates using
JEDEC-standard 3.3V or 2.5V I/O logic levels.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see Figure . TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most signif-
icant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
The CY7C1386C/CY7C1387C contains a TAP controller,
instruction register, boundary scan register, bypass register,
and ID register.
Disabling the JTAG Feature
Test Data-Out (TDO)
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may alter-
nately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller Block Diagram
TAP Controller State Diagram
0
Bypass Register
TEST-LOGIC
1
RESET
0
2
1
0
0
0
1
1
1
Selection
Circuitry
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
Instruction Register
31 30 29
Identification Register
0
Selection
TDI
TDO
Circuitr
y
0
0
.
.
. 2 1
1
1
CAPTURE-DR
CAPTURE-IR
0
0
x
.
.
.
.
. 2 1
SHIFT-DR
0
SHIFT-IR
0
Boundary Scan Register
1
1
1
1
EXIT1-DR
EXIT1-IR
TCK
TMS
0
0
TAP CONTROLLER
PAUSE-DR
0
PAUSE-IR
0
1
1
0
0
EXIT2-DR
1
EXIT2-IR
1
Performing a TAP Reset
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
UPDATE-DR
UPDATE-IR
1
0
1
0
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
TAP Registers
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Document #: 38-05239 Rev. *B
Page 14 of 34
CY7C1386C
CY7C1387C
Instruction Register
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in this SRAM TAP controller,
and therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High-Z
state.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
IDCODE
Boundary Scan Register
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The x36 configuration has a
xx-bit-long register, and the x18 configuration has a yy-bit-long
register.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
SAMPLE/PRELOAD
Identification (ID) Register
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the device TAP controller is not fully 1149.1 compliant.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls
is captured in the boundary scan register.
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus
hold time (tCS plus tCH).
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; rather, it performs a capture of the I/O
ring when these instructions are executed.
The SRAM clock input might not be captured correctly if there
is no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
Document #: 38-05239 Rev. *B
Page 15 of 34
CY7C1386C
CY7C1387C
possible to capture all other signals and simply ignore the
value of the CLK captured in the boundary scan register.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO balls.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state while
performing a SAMPLE/PRELOAD instruction will have the
same effect as the Pause-DR command.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the operating Range[10, 11]
Parameter
Symbol
Min
Max
Units
Clock
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
Output Times
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
Setup Times
tTCYC
tTF
tTH
100
ns
MHz
ns
10
20
40
40
tTL
ns
tTDOV
tTDOX
ns
ns
0
TMS Set-Up to TCK Clock Rise
TDI Set-Up to TCK Clock Rise
Capture Set-Up to TCK Rise
Hold Times
tTMSS
tTDIS
tCS
10
10
10
ns
ns
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
tTMSH
tTDIH
tCH
10
10
10
ns
ns
ns
Notes:
t
t
10. CS and CH refer to the setup and hold time requirements of latching data from the boundary scan register.
11. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1ns.
R
F
Document #: 38-05239 Rev. *B
Page 16 of 34
CY7C1386C
CY7C1387C
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input pulse levels ........ ........................................VSS to 3.3V
Input rise and fall times...................... ..............................1ns
Input timing reference levels...........................................1.5V
Output reference levels...................................................1.5V
Test load termination supply voltage...............................1.5V
Input pulse levels...............................................VSS to 2.5V
Input rise and fall time ......................................................1ns
Input timing reference levels................... ......................1.25V
Output reference levels .................. ..............................1.25V
Test load termination supply voltage .................... ........1.25V
3.3V TAP AC Output Load Equivalent
2.5V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
50Ω
TDO
TDO
ZO= 50Ω
20pF
ZO= 50Ω
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; Vdd = 3.3V ±0.165V unless otherwise noted)[12]
Parameter
VOH1
Description
Output HIGH Voltage
Test Conditions
IOH = -4.0 mA, VDDQ = 3.3V
Min
2.4
2.0
2.9
2.1
Max
Units
V
V
V
V
V
V
V
V
I
I
OH = -1.0 mA, VDDQ = 2.5V
OH = -100 µA VDDQ = 3.3V
VDDQ = 2.5V
IOL = 8.0 mA, VDDQ = 3.3V
OL = 8.0 mA, VDDQ = 2.5V
IOL = 100 µA VDDQ = 3.3V
DDQ = 2.5V
VOH2
VOL1
VOL2
VIH
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
0.4
0.4
0.2
0.2
I
V
V
DDQ = 3.3V
2.0
1.7
VDD + 0.3
V
VDDQ = 2.5V
VDD + 0.3
V
V
V
DDQ = 3.3V
DDQ = 2.5V
-0.5
-0.3
-5
0.7
0.7
5
V
V
µA
VIL
Input LOW Voltage
Input Load Current
IX
GND < VIN < VDDQ
Note:
12. All voltages referenced to VSS (GND).
Document #: 38-05239 Rev. *B
Page 17 of 34
CY7C1386C
CY7C1387C
Identification Register Definitions
Instruction Field
Revision Number (31:29)
Device Depth (28:24)
CY7C1386C
CY7C1387C
010
Description
010
01010
Describes the version number.
01010
Reserved for Internal Use
Device Width (23:18)
000110
100101
00000110100
1
000110
010101
00000110100
1
Defines memory type and architecture
Defines width and density
Cypress Device ID (17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size (x18)
Bit Size(X36)
Instruction
3
1
3
1
Bypass
ID
32
72
32
72
Boundary Scan Order
Identification Codes
Instruction
EXTEST
Code
Description
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.
001
010
IDCODE
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
SAMPLE Z
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
011
100
RESERVED
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1 compliant.
101
110
111
RESERVED
RESERVED
BYPASS
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect
SRAM operations.
Document #: 38-05239 Rev. *B
Page 18 of 34
CY7C1386C
CY7C1387C
119-Ball BGA Boundary Scan Order
CY7C1386C (512K x 36)
BIT# BALL
ID
BIT
#
BALL ID
1
2
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
B2
K4
H4
M4
F4
B4
A4
G4
C6
A6
D6
D7
E6
G6
H7
E7
F6
G7
H6
P4
3
N4
4
R6
5
T5
6
T3
7
R2
8
R3
9
P2
10
11
12
13
14
15
16
17
18
P1
N2
L2
K1
N1
M2
L1
K2
Not Bonded (Preset to 1)
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
T7
K7
L6
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
71
H1
G2
E2
N6
P7
K6
L7
D1
H2
G1
F2
M6
N7
P6
B5
B3
C5
C3
C2
A2
T4
B6
E1
D2
A5
A3
E4
Internal
L3
G3
G5
L5
Internal
Document #: 38-05239 Rev. *B
Page 19 of 34
CY7C1386C
CY7C1387C
119-Ball BGA Boundary Scan Order
CY7C1387C (1M x 18)
BIT# BALL
ID
BIT
#
BALL ID
1
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
B2
K4
H4
M4
F4
2
P4
3
N4
4
R6
5
B4
A4
G4
C6
A6
T6
T5
6
T3
7
R2
8
R3
9
Not Bonded (Preset to 0)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Not Bonded (Preset to 0)
Not
Not
Not
D6
E7
F6
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
P2
N1
M2
L1
G7
H6
T7
K2
Not Bonded (Preset to 1)
H1
K7
L6
G2
E2
N6
P7
Not
Not
Not
Not
Not
B5
B3
C5
C3
C2
A2
T2
D1
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
A5
A3
E4
Internal
Not Bonded (Preset to 0)
Internal
G3
L5
B6
Internal
Document #: 38-05239 Rev. *B
Page 20 of 34
CY7C1386C
CY7C1387C
165-Ball fBGA Boundary Scan Order
CY7C1386C (512K x 36)
BIT#
BALL
ID
BIT#
BALL
ID
1
B6
B7
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
N6
R6
P6
R4
R3
P4
P3
R1
N1
L2
2
3
A7
4
B8
5
A8
6
B9
7
A9
8
B10
A10
C11
E10
F10
G10
D10
D11
E11
F11
G11
H11
J10
K10
L10
M10
J11
K11
L11
M11
N11
R11
R10
R9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
K2
J2
M2
M1
L1
K1
J1
Internal
G2
F2
E2
D2
G1
F1
E1
D1
C1
A2
B2
A3
B3
B4
A4
A5
B5
A6
R8
P10
P9
P8
P11
Document #: 38-05239 Rev. *B
Page 21 of 34
CY7C1386C
CY7C1387C
165-Ball fBGA Boundary Scan Order
CY7C1387C (1M x 18)
BIT#
BALL
ID
BIT#
BALL
ID
0
B6
B7
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
N6
R6
1
2
A7
P6
3
B8
R4
4
A8
R3
5
B9
P4
6
A9
P3
7
B10
A10
A11
Not
Not
Not
C11
D11
E11
F11
G11
H11
J10
K10
L10
M10
Not
Not
Not
Not
Not
R11
R10
R9
R1
8
Not
Not
Not
Not
N1
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
M1
L1
K1
J1
Internal
G2
F2
E2
D2
Not
Not
Not
Not
Not
A2
B2
A3
B3
R8
Not
Not
A4
P10
P9
P8
B5
P11
A6
Document #: 38-05239 Rev. *B
Page 22 of 34
CY7C1386C
CY7C1387C
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage........................................... >2001V
(Above which the useful life may be impaired. For user guide-
(per MIL-STD-883, Method 3015)
lines, not tested.)
Latch-up Current..................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V
Ambient
Range
Temperature
VDD
VDDQ
DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to VDDQ + 0.5V
Commercial 0°C to +70°C 3.3V – 5%/+10% 2.5V – 5%
to VDD
DC Input Voltage....................................–0.5V to VDD + 0.5V
Industrial
-40°C to +85°C
Electrical Characteristics Over the Operating Range[13, 14]
Parameter
VDD
VDDQ
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
3.135
3.135
2.375
2.4
Max.
3.6
VDD
Unit
V
V
V
V
V
V
V
V
V
V
V
µA
VDDQ = 3.3V
VDDQ = 2.5V
2.625
VOH
VOL
VIH
VIL
IX
Output HIGH Voltage
Output LOW Voltage
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
DDQ = 2.5V, VDD = Min., IOH = –1.0 mA
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA
V
2.0
0.4
0.4
VDD + 0.3V
VDD + 0.3V
0.8
Input HIGH Voltage[13] VDDQ = 3.3V
DDQ = 2.5V
VDDQ = 3.3V
DDQ = 2.5V
2.0
1.7
–0.3
–0.3
–5
V
Input LOW Voltage[13]
V
0.7
5
Input Load Current ex- GND ≤ VI ≤ VDDQ
cept ZZ and MODE
Input Current of MODE Input = VSS
Input = VDD
–30
–5
µA
µA
µA
µA
µA
5
Input Current of ZZ
Input = VSS
Input = VDD
30
5
IOZ
IDD
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
–5
VDD Operating Supply VDD = Max., IOUT = 0 mA,
4.0-ns cycle, 250 MHz
4.4-ns cycle, 225 MHz
5-ns cycle, 200MHz
6-ns cycle, 167 MHz
4.0-ns cycle, 250 MHz
4.4-ns cycle, 225 MHz
5.0-ns cycle, 200MHz
6.0-ns cycle, 167 MHz
All speeds
350
325
300
275
120
110
100
90
mA
mA
mA
mA
mA
mA
mA
mA
mA
Current
f = fMAX = 1/tCYC
ISB1
Automatic CE
VDD = Max, Device Deselected,
Power-down
VIN ≥ VIH or VIN ≤ VIL
Current—TTL Inputs
f = fMAX = 1/tCYC
ISB2
Automatic CE
Power-down
VDD = Max, Device Deselected,
70
V
IN ≤ 0.3V or VIN > VDDQ – 0.3V,
Current—CMOS Inputs f = 0
ISB3
Automatic CE
VDD = Max, Device Deselected, or 4.0-ns cycle, 250 MHz
105
100
95
mA
mA
mA
mA
Power-down
V
IN ≤ 0.3V or VIN > VDDQ – 0.3V
4.4-ns cycle, 225 MHz
5.0-ns cycle, 200MHz
6.0-ns cycle, 167 MHz
Current—CMOS Inputs f = fMAX = 1/tCYC
85
Document #: 38-05239 Rev. *B
Page 23 of 34
CY7C1386C
CY7C1387C
Electrical Characteristics Over the Operating Range[13, 14] (continued)
Parameter
ISB4
Description
Test Conditions
VDD = Max, Device Deselected, All Speeds
VIN ≥ VIH or VIN ≤ VIL, f = 0
Min.
Max.
80
Unit
mA
Automatic CE
Power-down
Current—TTL Inputs
Shaded areas contain advance information.
Notes:
13. Overshoot: V (AC) < V +1.5V (Pulse width less than t
/2), undershoot: V (AC) > -2V (Pulse width less than t
/2).
IH
DD
CYC
IL
CYC
< V
DD\
14. TPower-up: Assumes a linear ramp from 0v to V (min.) within 200ms. During this time V < V and V
DDQ
DD
IH
DD
Thermal Resistance[15]
TQFP
BGA
fBGA
Parameter
Description
Test Conditions
Package
Package
Package
Unit
ΘJA
Thermal Resistance
Test conditions follow standard
test methods and procedures
for measuring thermal
31
45
46
°C/W
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
6
7
3
°C/W
impedence, per EIA / JESD51.
Capacitance[15]
TQFP
BGA
fBGA
Parameter
Description
Input Capacitance
Test Conditions
Package
Package
Package
Unit
pF
CIN
TA = 25°C, f = 1 MHz,
5
5
5
8
8
8
9
9
9
V
DD = 3.3V.
CCLK
Clock Input Capacitance
Input/Output Capacitance
pF
VDDQ = 2.5V
CI/O
pF
Notes:
15. Tested initially and after any design or process change that may affect these parameters
AC Test Loads and Waveforms
3.3V I/O Test Load
R = 317Ω
3.3V
OUTPUT
ALL INPUT PULSES
90%
VDD
OUTPUT
90%
10%
Z = 50Ω
0
R = 50Ω
10%
L
GND
5 pF
R = 351Ω
≤ 1ns
≤ 1ns
V = 1.5V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
R = 50Ω
OUTPUT
ALL INPUT PULSES
90%
VDD
90%
10%
Z = 50Ω
0
10%
L
GND
≤ 1ns
5 pF
R =1538Ω
≤ 1ns
V = 1.25V
L
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Document #: 38-05239 Rev. *B
Page 24 of 34
CY7C1386C
CY7C1387C
Switching Characteristics Over the Operating Range[20, 21]
250 MHz
225 MHz
200 MHz
167 MHz
Parameter
tPOWER
Clock
tCYC
tCH
tCL
Description
Min. Max Min. Max Min. Max Min. Max Unit
VDD(Typical) to the first Access[16]
1
1
1
1
ms
Clock Cycle Time
Clock HIGH
4.0
1.7
1.7
4.4
2.0
2.0
5.0
2.0
2.0
6.0
2.2
2.2
ns
ns
ns
Clock LOW
Output Times
tCO
tDOH
tCLZ
tCHZ
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z[17, 18, 19]
2.6
2.8
3.0
3.4
ns
ns
ns
ns
ns
ns
ns
1.0
1.0
1.0
1.0
1.3
1.3
1.3
1.3
Clock to High-Z[17, 18, 19]
2.6
2.6
2.8
2.8
3.0
3.0
3.4
3.4
tOEV
OE LOW to Output Valid
LOW to Output Low-Z[17, 18, 19]
OE
tOELZ
tOEHZ
Setup Times
tAS
tADS
tADVS
tWES
0
0
0
0
OE HIGH to Output High-Z[17, 18, 19]
2.6
2.8
3.0
3.4
Address Set-up Before CLK Rise
1.2
1.2
1.2
1.2
1.2
1.2
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
,
ADSC ADSP Set-up Before CLK Rise
ADV Set-up Before CLK Rise
Set-up Before CLK Rise
GW, BWE, BWX
tDS
tCES
Data Input Set-up Before CLK Rise
Chip Enable Set-Up Before CLK Rise
Hold Times
tAH
tADH
tADVH
tWEH
tDH
Address Hold After CLK Rise
0.3
0.3
0.3
0.3
0.3
0.3
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
,
Hold After CLK Rise
ADSP ADSC
ADV Hold After CLK Rise
,
,
GW BWE BWX Hold After CLK Rise
Data Input Hold After CLK Rise
tCEH
Chip Enable Hold After CLK Rise
Shaded areas contain advance information.
Notes:
16. This part has a voltage regulator internally; t
can be initiated.
is the time that the power needs to be supplied above V ( minimum) initially before a read or write operation
DD
POWER
17. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
18. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
OEHZ
OELZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions
19. This parameter is sampled and not 100% tested.
20. Timing reference level is 1.5V when V
= 3.3V and is 1.25V when V
= 2.5V.
DDQ
DDQ
21. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05239 Rev. *B
Page 25 of 34
CY7C1386C
CY7C1387C
Switching Waveforms
Read Cycle Timing[22]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
ADDRESS
Burst continued with
new base address
t
t
WEH
WES
GW, BWE,BWX
Deselect
cycle
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
OEV
CO
t
t
CHZ
t
t
t
OELZ
OEHZ
DOH
CLZ
t
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A3)
Q(A1)
Data Out (DQ)
High-Z
CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Notes:
22. On this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
23.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW.
X
Document #: 38-05239 Rev. *B
Page 26 of 34
CY7C1386C
CY7C1387C
Switching Waveforms (continued)
Write Cycle Timing[22, 23]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
ADDRESS
BWE,
Byte write signals are ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BW
X
t
t
WEH
WES
GW
CE
t
t
CEH
CES
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
DH
DS
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A1)
High-Z
Data in (D)
t
OEHZ
Data Out (Q)
BURST READ
BURST WRITE
DON’T CARE
Single WRITE
Extended BURST WRITE
UNDEFINED
Document #: 38-05239 Rev. *B
Page 27 of 34
CY7C1386C
CY7C1387C
Switching Waveforms (continued)
Read/Write Cycle Timing[22, 24, 25]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE, BW
X
t
t
CEH
CES
CE
ADV
OE
t
t
DH
t
CO
DS
t
OELZ
Data In (D)
High-Z
High-Z
D(A3)
D(A5)
D(A6)
t
t
OEHZ
CLZ
Data Out (Q)
Q(A1)
Back-to-Back READs
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
BURST READ
Back-to-Back
Single WRITE
DON’T CARE
WRITEs
UNDEFINED
Note:
24.
.
The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by
ADSP or ADSC
25. GW is HIGH.
Document #: 38-05239 Rev. *B
Page 28 of 34
CY7C1386C
CY7C1387C
Switching Waveforms (continued)
ZZ Mode Timing [26, 27]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
26. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
27. DQs are in high-Z when exiting ZZ sleep mode
Document #: 38-05239 Rev. *B
Page 29 of 34
CY7C1386C
CY7C1387C
Ordering Information
Speed
Package
Name
Operating
Range
(MHz)
Ordering Code
Part and Package Type
250
CY7C1386C-250AC
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
Commercial
CY7C1387C-250AC
3 Chip Enables
CY7C1386C-250BGC
CY7C1387C-250BGC
BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with
JTAG
CY7C1386C-250BZC
BB165A 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm)
CY7C1387C-250BZC
3 Chip Enables with JTAG
225
200
167
CY7C1386C-225AC
CY7C1387C-225AC
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Commercial
Industrial
CY7C1386C-225AI
CY7C1387C-225AI
CY7C1386C-225BGC
CY7C1387C-225BGC
CY7C1386C-225BGI
CY7C1387C-225BGI
CY7C1386C-225BZC
CY7C1387C-225BZC
CY7C1386C-225BZI
CY7C1387C-225BZI
CY7C1386C-200AC
CY7C1387C-200AC
BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with Commercial
JTAG
Industrial
BB165A 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm) Commercial
3 Chip Enables with JTAG
Industrial
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Commercial
Industrial
CY7C1386C-200AI
CY7C1387C-200AI
CY7C1386C-200BGC
CY7C1387C-200BGC
CY7C1386C-200BGI
CY7C1387C-200BGI
CY7C1386C-200BZC
CY7C1387C-200BZC
CY7C1386C-200BZI
CY7C1387C-200BZI
BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with Commercial
JTAG
Industrial
BB165A 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm) Commercial
3 Chip Enables with JTAG
Industrial
CY7C1386C-167AC
A101
100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm)
3 Chip Enables
Commercial
Industrial
CY7C1387C-167AC
CY7C1386C-167AI
CY7C1387C-167AI
CY7C1386C-167BGC
CY7C1387C-167BGC
CY7C1386C-167BG
ICY7C1387C-167BGI
CY7C1386C-167BZC
CY7C1387C-167BGC
CY7C1386C-167BZI
CY7C1387C-167BGI
BG119 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with Commercial
JTAG
Industrial
BB165A 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.2mm) Commercial
3 Chip Enables with JTAG
Industrial
Shaded areas contain advance information.
Please contact your local sales representative for availability of these parts.
Document #: 38-05239 Rev. *B
Page 30 of 34
CY7C1386C
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
DIMENSIONS ARE IN MILLIMETERS.
ꢁ6.00 0.20
ꢁ4.00 0.ꢁ0
ꢁ.40 0.05
ꢁ00
ꢀꢁ
ꢀ0
ꢁ
0.30 0.0ꢀ
0.65
TYP.
ꢁ2° ꢁ°
(ꢀX)
SEE DETAIL
A
30
5ꢁ
3ꢁ
50
0.20 MAX.
ꢁ.60 MAX.
R 0.0ꢀ MIN.
0.20 MAX.
0° MIN.
STAND-OFF
0.05 MIN.
0.ꢁ5 MAX.
SEATING PLANE
0.25
GAUGE PLANE
R 0.0ꢀ MIN.
0.20 MAX.
0°-7°
0.60 0.ꢁ5
0.20 MIN.
ꢁ.00 REF.
51-85050-*A
DETAIL
A
Document #: 38-05239 Rev. *B
Page 31 of 34
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1386C
CY7C1387C
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Document #: 38-05239 Rev. *B
Page 32 of 34
CY7C1386C
CY7C1387C
Package Diagrams (continued)
165-Ball FBGA (13 x 15 x 1.2 mm) BB165A
51-85122-*C
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM
Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05239 Rev. *B
Page 33 of 34
CY7C1386C
CY7C1387C
Document History Page
Document Title: CY7C1386C/CY7C1387C 18-Mb (512K x 36/1M x 18) Pipelined DCD Sync SRAM
Document Number: 38-05239
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
116279
08/29/02
SKX
New Data Sheet
*A
121542
11/21/02
DSG
Updated package drawings 51-85115 (BG 119) to *B and 51-85122
(BB165A) to *C.
*B
206081
See ECN
RKF
Final Datasheet
Document #: 38-05239 Rev. *B
Page 34 of 34
相关型号：
CY7C1386C-167BGI
Cache SRAM, 512KX36, 3.4ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CYPRESS
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