CY7C1366B-250BZC [CYPRESS]
Cache SRAM, 256KX36, 2.6ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165;型号: | CY7C1366B-250BZC |
厂家: | CYPRESS |
描述: | Cache SRAM, 256KX36, 2.6ns, CMOS, PBGA165, 13 X 15 MM, 1.20 MM HEIGHT, FBGA-165 时钟 静态存储器 内存集成电路 |
文件: | 总27页 (文件大小:637K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CY7C1366B
CY7C1367B
PRELIMINARY
256K x 36/512K x 18 Pipelined
Double-cycle Deselect SRAM
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise is 2.6 ns (250 MHz
device).
Features
• Supports bus operation up to 250 MHz
— Available speed grades are 250, 200, and 166 MHz
• Fully registered inputs and outputs for pipelined
operation
• Single 3.3V power supply
• Supports 3.3V and 2.5V I/Os
• Fast clock-to-output times
— 2.6ns (for 250 MHz device)
The CY7C1366B and CY7C1367B support either the inter-
leaved burst sequence used by the Intel Pentium processor or
a linear burst sequence used by processors such as the
PowerPC™. The burst sequence is selected through the
MODE pin (Pin 31 and ball R3 for the TQFP and BGA
packages, respectively.) Accesses can be initiated by
asserting either the Processor Address Strobe (ADSP) or the
Controller Address Strobe (ADSC) at clock rise. Address
advancement through the burst sequence is controlled by the
ADV input. A 2-bit on-chip wraparound burst counter captures
the first address in a burst sequence and automatically incre-
ments the address for the rest of the burst access.
— 3.0ns (for 200 MHz device)
— 3.5 ns (for 166 MHz device)
• User-selectable burst counter supporting Intel
Pentium® interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Two Cycle Chip Deselect
• Available as a 100-pin TQFP, 119-Ball BGA, 165-Ball
FBGA
Byte write operations are qualified with the Byte Write Select
(BWa,b,c,d for 1366B and BWa,b for 1367B) inputs. A Global
Write Enable (GW) overrides all byte write inputs and writes
data to all four bytes. All writes are conducted with on-chip
synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to provide
proper data during depth expansion, OE is masked during the
first clock of a read cycle when emerging from a deselected
state.
• TQFP and FBGA has 3 Chip Enables
• 119 BGA has 2-Chip Enables
• IEEE 1149.1 JTAG-compatible Boundary Scan for 119
BGA and 165 FBGA Packages
• “ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1366B and CY7C1367B are 3.3V, 256K x 36 and
512K x 18 synchronous-pipelined cache SRAM, respectively.
Logic Block Diagram
D
CLK
Data-In REG.
CE
Q
ADV
1366B
1367B
A
x
A
A
A
[17:0]
[18:0]
X
GW
CE
CE
CE
CONTROL
and WRITE
LOGIC
256Kx36/
512Kx18
DQ
DQ
a,b
a,b,c,d
DQ
1
2
X
DQP
BW
DQP
DQP
DQ
DQP
a,b,c,d
a,b
X
x
x
MEMORY
ARRAY
3
BW
BW
a,b,c,d
a,b
BWE
X
BW
x
MODE
ADSP
ADSC
ZZ
OE
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05096 Rev. *A
Revised November 12, 2002
CY7C1366B
CY7C1367B
PRELIMINARY
Selection Table
CY7C1366B-250
CY7C1367B-250
CY7C1366B-200
CY7C1366B-166
CY7C1367B-200
CY7C1367B-166
Unit
ns
Maximum Access Time
2.6
250
30
3.0
220
30
3.5
180
30
Maximum Operating Current
Comm’l
mA
mA
Maximum CMOS Standby Current Comm’l
Pin Configurations
100-pin TQFP Pinout (3 Chip Enables)
DQPc
1
DQPb
DQb
DQb
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
A
NC
NC
V
V
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQc
2
DQc
3
4
5
6
7
8
9
V
DDQ
V
V
V
DDQ
DDQ
DDQ
V
SSQ
V
SSQ
SSQ
NC
NC
DQb
DQb
SSQ
DQc
DQc
DQc
DQc
DQb
DQb
DQb
DQb
NC
DQPa
DQa
DQa
V
V
DQa
DQa
V
NC
V
9
V
SSQ
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
V
SSQ
SSQ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SSQ
V
DDQ
V
DDQ
DDQ
DDQ
DQc
DQc
NC
DQb
DQb
DQb
DQb
NC
V
SS
SS
V
DD
NC
NC
V
DD
CY7C1367B
(512K x 18)
CY7C1366B
(256K X 36)
V
NC
DD
DD
V
SS
ZZ
DQa
DQa
V
SS
ZZ
DQa
DQa
V
DQd
DQd
DQb
DQb
V
V
DDQ
V
V
DDQ
DDQ
DDQ
V
DQd
DQd
DQd
DQd
SSQ
V
SSQ
SSQ
DQb
DQb
DQPb
NC
V
SSQ
DQa
DQa
DQa
DQa
DQa
DQa
NC
NC
V
V
SSQ
V
V
V
SSQ
SSQ
SSQ
V
DDQ
V
DDQ
DDQ
V
DDQ
DQd
DQd
DQPd
DQa
DQa
DQPa
NC
NC
NC
NC
NC
NC
Document #: 38-05096 Rev. *A
Page 2 of 27
CY7C1366B
CY7C1367B
PRELIMINARY
Pin Configurations (continued)
119-ball BGA Pinout (2 Chip Enables with JTAG)
CY7C1366B (256K x 36)
1
2
3
4
5
6
7
A
VDDQ
A
A
ADSP
A
A
VDDQ
B
C
NC
NC
CE2
A
A
A
ADSC
VDD
A
A
A
A
NC
NC
D
E
F
DQc
DQc
DQPc
DQc
VSS
VSS
VSS
NC
CE1
OE
VSS
VSS
VSS
DQPb
DQb
DQb
DQb
VDDQ
DQc
DQb
VDDQ
G
H
J
DQc
DQc
DQc
DQc
VDD
DQd
BWc
VSS
NC
ADV
GW
VDD
CLK
BWb
VSS
NC
DQb
DQb
VDD
DQa
DQb
DQb
VDDQ
DQa
VDDQ
DQd
K
VSS
VSS
L
M
N
DQd
VDDQ
DQd
DQd
DQd
DQd
BWd
VSS
VSS
NC
BWE
A1
BWa
VSS
VSS
DQa
DQa
DQa
DQa
VDDQ
DQa
P
R
DQd
NC
DQPd
A
VSS
A0
VSS
NC
DQPa
A
DQa
NC
MODE
VDD
T
NC
NC
A
A
A
NC
NC
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
VDDQ
CY7C1367B (512K x 18)
2
A
1
3
A
4
5
A
6
A
7
A
B
C
D
E
F
VDDQ
NC
ADSP
ADSC
VDD
NC
VDDQ
NC
CE2
A
A
A
A
NC
A
A
A
NC
DQb
NC
NC
DQb
NC
VSS
VSS
VSS
VSS
VSS
VSS
DQPa
NC
DQa
NC
CE1
OE
DQa
VDDQ
VDDQ
G
H
J
NC
DQb
VDDQ
DQb
NC
VDD
BWb
VSS
NC
ADV
GW
VDD
VSS
VSS
NC
NC
DQd
VDD
DQa
NC
VDDQ
K
L
NC
DQb
VDDQ
DQb
NC
DQb
NC
VSS
VSS
VSS
VSS
VSS
CLK
NC
VSS
BWa
VSS
VSS
VSS
NC
DQa
NC
DQa
NC
M
N
P
DQb
NC
BWE
A1
VDDQ
NC
DQa
NC
DQPb
A0
DQa
NC
NC
A
A
MODE
A
Vdd
NC
NC
A
A
A
NC
ZZ
R
T
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
Document #: 38-05096 Rev. *A
Page 3 of 27
CY7C1366B
CY7C1367B
PRELIMINARY
Pin Configurations (continued)
165-ball TQFP fBGA (3 Chip Enable with JTAG)
CY7C1366B (256K x 36)
1
2
A
3
CE1
4
BWc
5
BWb
6
CE3
7
8
9
ADV
10
A
11
NC
E(288)
BWE
GW
VSS
VSS
ADSC
A
B
C
D
NC
A
CE2
VDDQ
VDDQ
BWd
VSS
VDD
BWa
VSS
VSS
CLK
VSS
VSS
OE
VSS
VDD
ADSP
VDDQ
VDDQ
A
E(144)
DQPb
DQb
DQPc
DQc
NC
DQc
NC
DQb
DQc
DQc
DQc
DQc
VSS
DQd
DQd
DQd
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
NC
DQb
DQb
DQb
NC
DQb
E
F
DQc
DQc
NC
VSS
VSS
VSS
VSS
VSS
VSS
DQb
DQb
ZZ
G
H
J
DQd
DQd
DQd
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DQa
DQa
DQa
DQa
DQa
DQa
K
L
DQd
DQPd
NC
DQd
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
E(18)
A1
VSS
VSS
VDD
VSS
A
VDDQ
VDDQ
A
DQa
NC
A
DQa
DQPa
A
M
N
P
E(72)
TDI
TDO
A0
MODE
E(36)
A
A
TMS
TCK
A
A
A
A
R
CY7C1367B (512K x 18)
1
E(288)
NC
2
A
3
CE1
4
BWb
5
NC
6
CE3
7
8
9
ADV
10
A
11
A
BWE
GW
VSS
VSS
ADSC
A
B
C
D
A
CE2
VDDQ
VDDQ
NC
VSS
VDD
BWa
VSS
VSS
CLK
VSS
VSS
OE
VSS
VDD
ADSP
VDDQ
VDDQ
A
E(144)
DQPa
DQa
NC
NC
DQb
NC
NC
NC
NC
DQb
VDDQ
VDDQ
VDDQ
NC
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
VDDQ
NC
NC
DQa
E
F
NC
NC
DQb
DQb
VSS
NC
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
NC
NC
DQa
DQa
ZZ
G
H
J
NC
NC
DQb
DQb
DQb
VDDQ
VDDQ
DQa
DQa
DQa
NC
NC
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
A
VSS
VSS
VSS
NC
VDDQ
VDDQ
VDDQ
VDDQ
A
K
L
NC
DQb
DQPb
NC
NC
NC
VDD
VSS
A
VSS
E(18)
A1
VSS
VSS
VDD
VSS
A
DQa
NC
A
NC
NC
A
M
N
P
E(72)
TDI
TDO
MODE
E(36)
A
A
TMS
A0
TCK
A
A
A
A
R
Document #: 38-05096 Rev. *A
Page 4 of 27
CY7C1366B
CY7C1367B
PRELIMINARY
Pin Definitions
Pin Name
I/O
Pin Description
A0
A1
A
Input-
Synchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge of
the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed
the two-bit counter.
BWa
BWb
BWc
BWd
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
GW
BWE
CLK
CE1
CE2
CE3
OE
Input-
Synchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a
global write is conducted (ALL bytes are written, regardless of the values on BWa,b,c,d and BWE).
Input-
Synchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW, during a burst operation.
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH.
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE1 and CE3 to select/deselect the device.
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select/deselect the device. This pin is not available on the 2CE TQFP package.
Input-
Asynchronous
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and
act as input data pins. OE is masked during the first clock of a read cycle when emerging from
a deselected state.
ADV
Input-
Advance Input signal, active LOW, sampled on the rising edge of CLK. When asserted, it
Synchronous
automatically increments the address in a burst cycle.
ADSP
Input-
Synchronous
Address Strobe from Processor, active LOW, sampled on the rising edge of CLK. When
asserted LOW, A is captured in the address registers. A[1:0] are also loaded into the burst counter.
When ADSP and ADSC are both asserted, only ADSP is recognized. ADSP is ignored when CE1
is deasserted HIGH.
ADSC
MODE
Input-
Synchronous
Address Strobe from Controller, active LOW, sampled on the rising edge of CLK. When
asserted LOW, A[x:0] is captured in the address registers. A[1:0] are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
Input-
Static
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left
floating selects interleaved burst sequence. This is a strap pin and should remain static during
device operation.
DQa, DQPa
DQb, DQPb
DQc, DQPc
DQd, DQPd
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by A during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQx and
DQPx are placed in a three-state condition.
ZZ
Input-
Asynchronous
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved. During normal operation, this pin can be connected to Vss or left
floating.
VDD
Power Supply
Ground
Power supply inputs to the core of the device. Should be connected to 3.3V power supply.
Ground for the core of the device. Should be connected to ground of the system.
VSS
VDDQ
VSSQ
TDO
I/O Power Supply Power supply for the I/O circuitry. Should be connected to a 3.3 or 2.5V power supply.
I/O Ground Ground for the I/O circuitry. Should be connected to ground of the system.
JTAG Serial Output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG
Synchronous
feature is not being utilized, this pin should be disconnected. This pin is not available on TQFP
packages.
TDI
JTAG Serial Input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is
Synchronous
not being utilized, this pin can be disconnected or connected to VCC. This pin is not available on
TQFP packages.
Document #: 38-05096 Rev. *A
Page 5 of 27
CY7C1366B
CY7C1367B
PRELIMINARY
Pin Definitions (continued)
Pin Name
I/O
Pin Description
TMS
Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
Synchronous
If JTAG the feature is not being utilized, this pin can be disconnected or connected to VSS. This
pin is not available on TQFP packages.
TCK
JTAG-
Clock
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin can be
disconnected, connected to VSS or connected to VDD. This pin is not available on TQFP
packages.
NC
–
–
No Connects.
E(18,36,72,
144, 288)
These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M
and 288M densities.
OE signal. Consecutive single read cycles are supported.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Introduction
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (tCO) is 2.6 ns (250
MHz device).
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) CE1, CE2, CE3 are all asserted active. The address
presented is loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
write signals (GW, BWE, and BWx) and ADV inputs are
ignored during this first cycle.
The CY7C1366B and CY7C1367B support secondary cache
in systems utilizing either a linear or interleaved burst
sequence. The interleaved burst order supports Pentium and
i486 processors. The linear burst sequence is suited for
processors that utilize a linear burst sequence. The burst order
is user selectable, and is determined by sampling the MODE
input. Accesses can be initiated with either the Processor
Address Strobe (ADSP) or the Controller Address Strobe
(ADSC). Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the corre-
sponding address location in the RAM core. If GW is HIGH,
then the write operation is controlled by BWE and BWx
signals. The CY7C1366B and 1367B provide byte write
capability that is described in the Write Cycle Description table.
Asserting the Byte Write Enable input (BWE) with the selected
Byte Write (BWa,b,c,d for CY7C1366B and BWa,b for
CY7C1367B input will selectively write to only the desired
bytes. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWa,b,c,d for CY7C1366B and
BWa,b for CY7C1367B) inputs. A Global Write Enable (GW)
overrides all byte write inputs and writes data to all four bytes.
All writes are simplified with on-chip synchronous self-timed
write circuitry.
Because the CY7C1366B and CY7C1367B are common I/O
devices, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQ inputs. Doing so will
three-state the output drivers. As a safety precaution, DQ are
automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. ADSP is ignored if
CE1 is HIGH.
Single Read Accesses
Single Write Accesses Initiated by ADSC
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE2, CE3 are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
is HIGH. The address presented to the address inputs is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The corre-
sponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 2.6 ns (250-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state; its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active,
and (4) the appropriate combination of the write inputs (GW,
BWE, and BWx) are asserted active to conduct a write to the
desired byte(s). ADSC triggered write accesses require a
single clock cycle to complete. The address presented to
A[17:0] is loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
ADV input is ignored during this cycle. If a global write is
conducted, the data presented to the DQ[x:0] is written into the
corresponding address location in the RAM core. If a byte write
is conducted, only the selected bytes are written. Bytes not
selected during a byte write operation will remain unaltered. A
Document #: 38-05096 Rev. *A
Page 6 of 27
CY7C1366B
CY7C1367B
PRELIMINARY
synchronous self-timed write mechanism has been provided
to simplify the write operations.
Linear Burst Sequence
First
Address
Second
Address
Third
Fourth
Because the CY7C1366B and CY7C1367B are common I/O
devices, the Output Enable (OE) must be deasserted HIGH
before presenting data to the DQ[x:0] inputs. Doing so will
three-state the output drivers. As a safety precaution, DQ[x:0]
are automatically three-stated whenever a write cycle is
detected, regardless of the state of OE.
Address
A[1:0]
10
Address
A[1:0]
00
A[1:0]
01
A[1:0]
11
01
10
11
00
10
11
00
01
Burst Sequences
The CY7C1366B and CY7C1367B provide
11
00
01
10
a two-bit
wraparound counter, fed by A[1:0], that implements either an
interleaved or linear burst sequence. The interleaved burst
sequence is designed specifically to support Intel Pentium
applications. The linear burst sequence is designed to support
processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Interleaved Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]]
00
A[1:0]
01
A[1:0]
10
A[1:0]
11
01
00
11
10
10
11
00
01
11
10
01
00
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
ZZ > VDD − 0.2V
Min. Max. Unit.
35 mA
IDDZZ
tZZS
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ > VDD − 0.2V
ZZ < 0.2V
2tCYC ns
2tCYC ns
tZZREC
[1, 2, 3]
Cycle Description
Next Cycle
Unselected
Add. Used
None
ZZ
L
L
L
L
L
L
L
L
L
L
L
L
CE3
X
1
CE2
X
X
0
CE1
ADSP
ADSC
ADV
X
OE
X
X
X
X
X
X
X
1
DQ
Hi-Z
Write
X
1
0
0
0
0
0
0
X
X
1
1
X
X
0
0
1
1
0
1
1
1
X
X
1
0
X
X
0
0
X
0
1
1
1
1
1
Unselected
None
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQ
X
Unselected
None
X
1
X
X
Unselected
None
X
0
X
X
Unselected
None
X
0
X
X
Begin Read
Begin Read
Continue Read
Continue Read
Continue Read
Continue Read
External
External
Next
1
X
X
0
1
X
Read
Read
Read
Read
Read
Read
X
X
X
X
X
X
X
X
X
X
0
Next
0
0
Next
0
1
Hi-Z
DQ
Next
0
0
Suspend Read
Current
1
1
Hi-Z
Notes:
1. X = ”don't care,” 1 = HIGH, 0 = LOW.
2. Write is defined by BWE, BWx, and GW. See Write Cycle Description table.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
Document #: 38-05096 Rev. *A
Page 7 of 27
CY7C1366B
CY7C1367B
PRELIMINARY
Cycle Description (continued)[1, 2, 3]
Next Cycle
Suspend Read
Suspend Read
Suspend Read
Begin Write
Add. Used
Current
Current
Current
Current
Current
External
Next
ZZ
L
CE3
X
CE2
X
CE1
X
1
ADSP
ADSC
ADV
1
OE
0
DQ
DQ
Write
Read
Read
Read
Write
Write
Write
Write
Write
Write
Write
X
1
X
X
1
1
1
1
1
1
0
1
1
1
1
X
L
X
X
1
1
Hi-Z
DQ
L
X
X
1
1
0
L
X
X
X
1
1
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Begin Write
L
X
X
X
1
1
Begin Write
L
0
1
0
X
0
Continue Write
Continue Write
Suspend Write
Suspend Write
ZZ “sleep”
L
X
X
X
1
1
Next
L
X
X
X
1
0
Current
Current
None
L
X
X
X
1
1
L
X
X
X
X
1
H
X
X
X
X
Write Cycle Description[1, 2]
Function (1366)
Read
GW
BWE
BWd
BWc
X
1
BWb
BWa
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
X
X
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
X
X
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
Read
Write Byte 0 – DQa
Write Byte 1 – DQb
Write Bytes 1, 0
Write Byte 2 – DQc
Write Bytes 2, 0
Write Bytes 2, 1
Write Bytes 2, 1, 0
Write Byte 3 – DQd
Write Bytes 3, 0
Write Bytes 3, 1
Write Bytes 3, 1, 0
Write Bytes 3, 2
Write Bytes 3, 2, 0
Write Bytes 3, 2, 1
Write All Bytes
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
Write All Bytes
X
Function (1367)
Read
GW
1
BWE
BWb
BWa
1
0
0
0
0
X
X
1
1
0
0
X
X
1
0
1
0
X
Read
1
Write Byte 0 – DQ[7:0] and DQP0
Write Byte 1 – DQ[15:8] and DQP1
Write All Bytes
1
1
1
Write All Bytes
0
Document #: 38-05096 Rev. *A
Page 8 of 27
CY7C1366B
CY7C1367B
PRELIMINARY
circuitry. Only one register can be selected at a time through
the instruction registers. Data is serially loaded into the TDI pin
on the rising edge of TCK. Data is output on the TDO pin on
the falling edge of TCK.
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1366B and CY7C1367B incorporate a serial
boundary scan Test Access Port (TAP) in the FBGA package
only. This port operates in accordance with IEEE Standard
1149.1-1900, but does not have the set of functions required
for full 1149.1 compliance. These functions from the IEEE
specification are excluded because their inclusion places an
added delay in the critical speed path of the SRAM. Note that
the TAP controller functions in a manner that does not conflict
with the operation of other devices using 1149.1 fully compliant
TAPs. The TAP operates using JEDEC standard for 3.3V and
2.5V I/O logic levels.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO pins as shown in the TAP Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
When the TAP controller is in the CaptureIR state, the two least
significant bits are loaded with a binary "01" pattern to allow for
fault isolation of the board level serial test path.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are inter-
nally pulled up and may be unconnected. They may alternately
be connected to VDD through a pull-up resistor. TDO should
be left unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the operation of the
device.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain states. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
Test Access Port (TAP) - Test Clock
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Boundary Scan Register
The boundary scan register is connected to all the input and
output pins on the SRAM. Several no connect (NC) pins are
also included in the scan register to reserve pins for higher
density devices. The x36 configuration has a xx-bit-long
register, and the x18 configuration has a yy-bit-long register.
Test Mode Select
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this pin unconnected if the TAP is not used. The pin is
pulled up internally, resulting in a logic HIGH level.
The boundary scan register is loaded with the contents of the
RAM Input and Output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and
TDO pins when the controller is moved to the Shift-DR state.
The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instruc-
tions can be used to capture the contents of the Input and
Output ring.
Test Data-In (TDI)
The TDI pin is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see the TAP
Controller State Diagram. TDI is internally pulled up and can
be unconnected if the TAP is unused in an application. TDI is
connected to the Most Significant Bit (MSB) on any register.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
Test Data Out (TDO)
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
The TDO output pin is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine (see TAP Controller State
Diagram). The output changes on the falling edge of TCK.
TDO is connected to the Least Significant Bit (LSB) of any
register.
Performing a TAP Reset
TAP Instruction Set
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of
the SRAM and may be performed while the SRAM is
operating. At power-up, the TAP is reset internally to ensure
that TDO comes up in a high-Z state.
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in the
Instruction Code table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented. The TAP controller
cannot be used to load address, data or control signals into the
TAP Registers
Registers are connected between the TDI and TDO pins and
allow data to be scanned into and out of the SRAM test
Document #: 38-05096 Rev. *A
Page 9 of 27
CY7C1366B
CY7C1367B
PRELIMINARY
SRAM and cannot preload the Input or Output buffers. The
SRAM does not implement the 1149.1 commands EXTEST or
INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather it performs a capture of the Inputs and Output ring when
these instructions are executed.
When the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 10 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO pins.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all
0s. EXTEST is not implemented in the TAP controller, and
therefore this device is not compliant to the 1149.1 standard.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK# captured in the
boundary scan register.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the SRAM responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between the two
instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a High-Z state.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO pins and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state. The IDCODE instruction
is loaded into the instruction register upon power-up or
whenever the TAP controller is given a test logic reset state.
Note that since the PRELOAD part of the command is not
implemented, putting the TAP into the Update to the
Update-DR state while performing a SAMPLE/PRELOAD
instruction will have the same effect as the Pause-DR
command.
Bypass
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High-Z state.
SAMPLE/PRELOAD
Reserved
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the TAP controller is not fully 1149.1 compliant.
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document #: 38-05096 Rev. *A
Page 10 of 27
CY7C1366B
CY7C1367B
PRELIMINARY
TAP Controller State Diagram[4]
TEST-LOGIC
1
RESET
1
1
1
TEST-LOGIC/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-DR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
Note:
4. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05096 Rev. *A
Page 11 of 27
CY7C1366B
CY7C1367B
PRELIMINARY
TAP Controller Block Diagram
0
Bypass Register
Selection
Circuitry
Selection
Circuitry
2
1
0
TDO
Instruction Register
29
Identification Register
31 30
.
.
2
1
1
0
0
TDI
.
x
.
.
.
2
Boundary Scan Register
TCK
TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range[5, 6]
Parameter
Description
Output HIGH Voltage
Test Conditions
IOH = –2.0 mA, VDDQ = 3.3V
IOH = –2.0 mA, VDDQ = 2.5V
IOH = –100 µA, VDDQ = 3.3V
IOH = –100 µA, VDDQ = 2.5V
IOL = 2.0 mA
Min.
Max.
Unit
V
VOH1
2.0
1.7
2.0
2.0
V
VOH2
Output HIGH Voltage
V
V
VOL1
VOL2
VIH
Output LOW Voltage
Output LOW Voltage
Input HIGH Voltage
0.7
0.2
V
IOL = 100 µA
V
VDDQ = 3.3V
2.0 VDD + 0.3
1.7
V
VDDQ = 3.3V
V
VIL
IX
Input LOW Voltage
Input Load Current
–0.3
–30
–30
0.7
30
30
V
GND ≤ VI ≤ VDDQ
µA
µA
IX
Input Load Current TMS,TCK, and TDI GND ≤ VI ≤ VDDQ
TAP AC Switching Characteristics Over the Operating Range[7, 8]
Parameters
tTCYC
Description
Min.
Max.
10
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH
100
ns
MHz
ns
tTF
tTH
40
40
tTL
TCK Clock LOW
ns
Set-up Times
tTMSS
TMS Set-up to TCK Clock Rise
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
10
10
10
ns
ns
ns
tTDIS
tCS
Notes:
5. All voltage referenced to ground.
6. Overshoot: VIH(AC) < VDD + 1.5V for t < tTCYC/2; undershoot: VIL(AC) < 0.5V for t < tTCYC/2; power-up: VIH < 3.3V and VDD < 3.3V and VDDQ < 1.7V for t < 200 ms.
7. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
8. Test conditions are specified using the load in TAP AC test conditions. tR/tF= 1 ns.
Document #: 38-05096 Rev. *A
Page 12 of 27
CY7C1366B
CY7C1367B
PRELIMINARY
TAP AC Switching Characteristics Over the Operating Range[7, 8]
Parameters
Hold Times
tTMSH
Description
Min.
Max.
Unit
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
10
10
10
ns
ns
ns
tTDIH
tCH
Capture Hold after Clock Rise
Output Times
tTDOV
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
20
ns
ns
tTDOX
0
TAP Timing and Test Conditions
1.5V for 3.3V V
1.25V for 2.5V V
DDQ
DDQ
ALL INPUT PULSES
V
= 3.0V or 2.5V
0V
DDQ
50Ω
1.5V for 3.0V V
1.25V for 2.5V V
DDQ
DDQ
TDO
Z =50Ω
0
C =20 pF
L
(a)
tTL
GND
tTH
Test Clock
TCK
tTCYC
tTMSS
tTMSH
Test Mode Select
TMS
tTDIS
tTDIH
Test Data-In
TDI
Test Data-Out
TDO
tTDOV
tTDOX
Identification Register Definitions
Instruction Field
Revision Number (31:29)
Device Depth (28:12)
CY7C1366B
CY7C1367B
Description
0000
01010000000100110
00000110100
1
000
Reserved for version number.
01010000000010110 Defines the type of SRAM.
Cypress JEDEC ID (11:1)
ID Register Presence (0)
00000110100
1
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
Document #: 38-05096 Rev. *A
Page 13 of 27
CY7C1366B
CY7C1367B
PRELIMINARY
Scan Register Sizes
Register Name
Bit Size (x36)
Bit Size (x18)
Instruction
Bypass
3
1
3
1
ID
32
70
32
51
Boundary Scan
Identification Codes
Instruction
EXTEST
Code
Description
000
Captures the Input/Output ring contents. Places the boundary scan register between the TDI and
TDO. Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.
IDCODE
001
010
011
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100
Captures the Input/Output ring contents. Places the boundary scan register between TDI and
TDO. Does not affect the SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1-compliant.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Boundary Scan Exit Order (x36)
Boundary Scan Exit Order (x36) (continued)
Bit #
1
Signal Name
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
119-Ball ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
165-Ball ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Bit #
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Signal Name
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
119-Ball ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
165-Ball ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Document #: 38-05096 Rev. *A
Page 14 of 27
CY7C1366B
CY7C1367B
PRELIMINARY
Boundary Scan Exit Order (x36) (continued)
Boundary Scan Exit Order (x18) (continued)
Bit #
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
Signal Name
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
119-Ball ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
165-Ball ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Bit #
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Signal Name
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
119- Ball ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
165- Ball ID
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Boundary Scan Exit Order (x18)
Bit #
1
Signal Name
TBD
119- Ball ID
TBD
165- Ball ID
TBD
2
TBD
TBD
TBD
3
TBD
TBD
TBD
4
TBD
TBD
TBD
5
TBD
TBD
TBD
6
TBD
TBD
TBD
7
TBD
TBD
TBD
8
TBD
TBD
TBD
9
TBD
TBD
TBD
10
11
12
13
14
15
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Document #: 38-05096 Rev. *A
Page 15 of 27
CY7C1366B
CY7C1367B
PRELIMINARY
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Latch-up Current.................................................... > 200 mA
Operating Range
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Ambient
Supply Voltage on VDD Relative to GND........ –0.3V to +3.6V
Range Temperature[10]
VDD/VDDQ
DC Voltage Applied to Outputs
in High-Z State[9] ................................. –0.5V to VDDQ + 0.5V
Com’l
0°C to +70°C
3.135 – 3.6V /
3.135 – 3.6V or 2.375 – 2.9V
DC Input Voltage[9].............................. –0.5V to VDDQ + 0.5V
Electrical Characteristics Over the Operating Range
Parameter
VDD
Description
Power Supply Voltage
I/O Supply Voltage
Test Conditions
Min.
3.135
3.135
2.375
2.4
Max.
3.6
Unit
V
VDDQ
VDDQ = 3.3V
VDDQ = 2.5V
VDD
2.9
V
V
VOH
VOL
VIH
VIL
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage[9]
VDD = Min., IOH = −4.0 mA, VDDQ = 3.3V
VDD = Min., IOH = −1.0 mA, VDDQ = 2.5V
VDD = Min., IOH = 8.0 mA, VDDQ = 3.3V
VDD = Min., IOH = 1.0 mA, VDDQ = 2.5V
VDDQ = 3.3V
V
2.0
V
0.4
0.4
V
V
2.0 VDDQ + 0.3V
1.7
V
VDDQ = 2.5V
V
VDDQ = 3.3V
–0.3
–0.3
–5
0.8
0.7
5
V
VDDQ = 2.5V
v
IX
Input Load Current
GND ≤ VI ≤ VDDQ
µA
except ZZ and MODE
IOZ
IZZ
IDD
Output Leakage
Current
GND ≤ VI ≤ VDDQ, Output Disabled
–5
5
µA
µA
Input Current of MODE
and ZZ pins
–30
30
VDD Operating Supply VDD = Max., IOUT = 0 mA,
Current
4.0-ns cycle,250 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 166 MHz
4.0-ns cycle,250 MHz
5.0-ns cycle, 200 MHz
6.0-ns cycle, 166 MHz
250
220
180
250
220
180
30
mA
mA
mA
mA
mA
mA
mA
f = fMAX = 1/tCYC
ISB1
Automatic CS
Power-down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
ISB2
Automatic CS
Power-down
Max. VDD, Device Deselected,
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
Current—CMOS Inputs f = 0
ISB3
Automatic CS
Power-down
Current—CMOS Inputs f = fMAX = 1/tCYC
Max. VDD, Device Deselected, or 4.0-ns cycle,250 MHz
250
220
180
40
mA
mA
mA
mA
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
5.0-ns cycle, 200 MHz
6.0-ns cycle, 166 MHz
ISB4
Automatic CS
Power-down
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0
Current—TTL Inputs
Note:
9. Minimum voltage equals –2.0V for < 1 ns or -0.5V for pulse durations of less than 20 ns.
10. A is the temperature.
T
Document #: 38-05096 Rev. *A
Page 16 of 27
CY7C1366B
CY7C1367B
PRELIMINARY
Capacitance[11]
Parameter
Description
Input Capacitance
Test Conditions
Max.
Unit
pF
CIN
TA = 25°C, f = 1 MHz,
DD = 3.3V,
DDQ = 3.3V
4
4
4
V
V
CCLK
CI/O
Clock Input Capacitance
Input/Output Capacitance
pF
pF
AC Test Loads and Waveforms[12]
R = 1667/317Ω
2.5/3.3V
2.5/3.3V
OUTPUT
[11,13]
90%
OUTPUT
ALL INPUT PULSES
90%
10%
Z = 50Ω
0
1.5/1.25V
R = 50Ω
10%
L
5 pF
INCLUDING
GND
R = 1538/351Ω
≤ 1.0ns
≤ 1.0ns
V = 1.25/1.5V
L
JIG AND
SCOPE
(a)
(b)
(c)
Thermal Characteristics[13]
Parameter
Description
Test Conditions
BGA Typ. fBGA Typ. TQFP Typ.
Unit
Notes
QJA
Thermal Resistance
(Junction to Ambient) 1.125 inch, 4-layer printed
Still Air, soldered on a 4.25 x
25
27
25
°C/W
15
circuit board
QJC
Thermal Resistance
6
6
9
°C/W
15
(Junction to Case)
[14, 15, 16, 17]
Switching Characteristics Over the Operating Range
-250
-200
Max.
-166
Parameter
Clock
Description
Min.
Max.
Min.
Min.
Max.
Unit
tCYC
Clock Cycle Time
4.0
5
6
ns
MHz
ns
FMAX
tCH
Maximum Operating Frequency
Clock HIGH
250
200
166
1.7
1.7
2.0
2.0
2.4
2.4
tCL
Clock LOW
ns
Output Times
tCO
Data Output Valid After CLK Rise
OE LOW to Output Valid[14]
Data Output Hold After CLK Rise
Clock to High-Z[14]
Clock to Low-Z[14]
OE HIGH to Output High-Z[14, 15]
OE LOW to Output Low-Z[14, 15]
2.6
2.6
3.0
3.0
3.5
3.5
ns
ns
ns
ns
ns
ns
ns
tEOV
tDOH
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
1.25
tCHZ
2.6
2.6
3.0
3.0
3.5
3.5
tCLZ
tEOHZ
tEOLZ
Set-up Times
tAS
0
0
0
Address Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
ADSP, ADSC Set-up Before CLK Rise
WE, BWSx Set-up Before CLK Rise
1.2
1.2
1.2
1.2
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
tDS
tADS
tWES
Notes:
11. Tested initially and after any design or process changes that may affect these parameters.
12. Input waveform should have a slew rate > 1V/ns.
13. Tested initially and after any design or process change that may affect these parameters.
14. Unless otherwise noted, test conditions assume signal transition time of 1 ns or less, timing reference levels of 1.5V OR 1.25v, input pulse levels of 0 to 3.0V
OR 2.5V, and output loading of the specified IOL/IOH and load capacitance. Shown in (a), (b) and (c) of AC Test Loads.
15. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
16. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ
.
17. AC parameters may exceed minimums and maximums during the first 20 microseconds of operation.
Document #: 38-05096 Rev. *A
Page 17 of 27
CY7C1366B
CY7C1367B
PRELIMINARY
Switching Characteristics Over the Operating Range (continued)[14, 15, 16, 17]
-250
-200
Max.
-166
Parameter
tADVS
Description
ADV Set-up Before CLK Rise
Chip Select Set-up
Min.
1.2
Max.
Min.
1.5
Min.
1.5
Max.
Unit
ns
tCES
1.2
1.5
1.5
ns
Hold Times
tAH
Address Hold After CLK Rise
Data Input Hold After CLK Rise
ADSP, ADSC Hold After CLK Rise
WE, BWx Hold After CLK Rise
ADV Hold after CLK Rise
0.3
0.3
0.3
0.3
0.3
0.3
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tDH
tADH
tWEH
tADVH
tCEH
Chip Select Hold After CLK Rise
Document #: 38-05096 Rev. *A
Page 18 of 27
CY7C1366B
CY7C1367B
PRELIMINARY
Switching Waveforms
Write Cycle Timing[18, 19]
Single Write
tCYC
tADH
Burst Write
Pipelined Write
tCH
Unselected
CLK
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
ADSC
ADV
tADH
tADS
ADSC initiated write
tADVH
tADVS
tAS
ADV Must Be Inactive for ADSP Write
WD3
ADD
GW
WE
CE1
WD1
WD2
tAH
tWH
tWH
tWS
tWS
tCES
tCEH
CE1 masks ADSP
tCEH
tCES
Unselected with CE2
CE2
CE3
OE
tCES
tCEH
tDH
tDS
High-Z
High-Z
Data In
3a
2a
2d
= DON’T CARE
1a
2b
2c
= UNDEFINED
Notes:
18. WE is the combination of BWE, BWx, and GW to define a write cycle (see Write Cycle Description table).
19. WDx stands for Write Data to Address X.
Document #: 38-05096 Rev. *A
Page 19 of 27
CY7C1366B
CY7C1367B
PRELIMINARY
Switching Waveforms (continued)
Read Cycle Timing[18, 20]
Burst Read
Single Read
tCYC
Unselected
tCH
Pipelined Read
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADS
ADSC initiated read
ADSC
ADV
tADVS
tADH
Suspend Burst
tADVH
tAS
ADD
GW
RD1
RD3
RD2
tAH
tWS
tWS
tWH
WE
tCES
tCEH
tWH
CE1 masks ADSP
CE1
Unselected with CE2
CE2
tCES
tCEH
CE3
OE
tCES
tEOV
tCEH
tOEHZ
tDOH
Double-Cycle
Deselect
tCO
Data Out
2c
1a
2d
3a
2a
2b
tCLZ
tCHZ
= DON’T CARE
= UNDEFINED
Note:
20. RDx stands for Read Data from Address X.
Document #: 38-05096 Rev. *A
Page 20 of 27
CY7C1366B
CY7C1367B
PRELIMINARY
Switching Waveforms (continued)
Read/Write Cycle Timing[21, 22]
Single Write
Single Read
tCYC
Single Write
tCH
Burst Read
Pipelined Read
CLK
tADS
tADH
tCL
ADSP
ADSC
ADV
tADVS
tAS
tADVH
WD2
ADD
RD1
RD4
WD3
RD5
tAH
GW
WE
tWS
tWS
tWH
tCES
tWH
tCEH
Deselect cycle
CE1
CE2
CE3
tCES
tCEH
tEOV
tCES
tCEH
OE
tEOHZ
tDS
tDH
tDOH
tEOLZ
tCO
4b
Out
4c
4a
Out
4d
5a
Data In/Out
1a
2a
In
3a
In
Out
Out
Out
Out
tCHZ
= UNDEFINED
= DON’T CARE
Notes:
21. Device originally deselected.
22. CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device.
Document #: 38-05096 Rev. *A
Page 21 of 27
CY7C1366B
CY7C1367B
PRELIMINARY
Switching Waveforms (continued)
OE Switching Waveforms
OE
tEOV
tEOHZ
Three-state
I/Os
tEOLZ
ZZ Mode Timing [23, 24]
CLK
ADSP
HIGH
ADSC
CE1
LOW
CE2
HIGH
CE3
ZZ
tZZS
IDD
IDD(active)
Three-state
tZZREC
IDDZZ
I/O’s
Notes:
23. Device must be deselected when entering ZZ mode. See Cycle Description Table for all possible signal conditions to deselect the device.
24. I/Os are in three-state when exiting ZZ sleep mode.
Document #: 38-05096 Rev. *A
Page 22 of 27
CY7C1366B
CY7C1367B
PRELIMINARY
Ordering Information
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Part & Package Type
250
CY7C1366B-250AC
CY7C1367B-250AC
CY7C1366B-250BGC
CY7C1367B-250BGC
CY7C1366B-250BZC
CY7C1367B-250BZC
CY7C1366B-200AC
CY7C1367B-200AC
CY7C1366B-200BGC
CY7C136B2-200BGC
CY7C1366B-200BZC
CY7C1367B-200BZC
CY7C1366B-166AC
CY7C1367B-166AC
CY7C1366B-166BGC
CY7C1367B-166BGC
CY7C1366B-166BZC
CY7C1367B-166BZC
A101
100-lead Thin Quad Flat Pack
3 Chip Enables
Commercial
BG119
BB165A
A101
119-ball (14 x 22 x 2.4 mm) BGA
2 Chip Enables and JTAG
165-ball Fine-Pitch Ball Grid Array
3 Chip Enables and JTAG
200
166
100-lead Thin Quad Flat Pack
3 Chip Enables
BG119
BB165A
A101
119-ball (14 x 22 x 2.4 mm) BGA
2 Chip Enables and JTAG
165-ball Fine-Pitch Ball Grid Array
3 Chip Enables and JTAG
100-lead Thin Quad Flat Pack
3 Chip Enables
BG119
BB165A
119-ball (14 x 22 x 2.4 mm) BGA
2 Chip Enables and JTAG
165-ball Fine-Pitch Ball Grid Array
3 Chip Enables and JTAG
Document #: 38-05096 Rev. *A
Page 23 of 27
CY7C1366B
CY7C1367B
PRELIMINARY
Package Diagrams
100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A
Document #: 38-05096 Rev. *A
Page 24 of 27
CY7C1366B
CY7C1367B
PRELIMINARY
Package Diagrams (continued)
119-Lead PBGA (14 x 22 x 2.4 mm) BG119
51-85115-*B
Document #: 38-05096 Rev. *A
Page 25 of 27
CY7C1366B
CY7C1367B
PRELIMINARY
Package Diagrams (continued)
165-Ball FBGA (13 x 15 x 1.2 mm) BB165A
51-85122-*C
Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and
company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05096 Rev. *A
Page 26 of 27
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1366B
CY7C1367B
PRELIMINARY
Document Title: CY7C1366B/CY7C1367B 256K x 36/512K x 18 Pipelined Double-cycle Deselect SRAM (Preliminary)
Document Number: 38-05096
ISSUE
DATE
ORIG. OF
CHANGE
REV.
**
ECN NO.
117903
121066
DESCRIPTION OF CHANGE
8/28/02
RCS
DSG
New Data Sheet
*A
11/13/02
Updated package drawings 51-85115 (BG119) to *B and 51-85122
(BB165A) to *C
Document #: 38-05096 Rev. *A
Page 27 of 27
相关型号:
CY7C1366C-166AXIT
Cache SRAM, 256KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100
CYPRESS
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