CY7C1366C-166AXCT [CYPRESS]
SRAM,;
CYPRESS 
CY7C1366C
CY7C1367C
9-Mbit (256K × 36/512K × 18)
Pipelined DCD Sync SRAM
9-Mbit (256K
× 36/512K × 18) Pipelined DCD Sync SRAM
circuitry and a two-bit counter for internal burst operation. All
synchronous inputs are gated by registers controlled by a
positive-edge-triggered clock input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelining
chip enable (CE1), depth-expansion chip enables (CE2 and
Features
■ Supports bus operation up to 166 MHz
■ Available speed grade is 166 MHz
CE3[1]), burst control inputs (ADSC, ADSP,
ADV), write
and
■ Registered inputs and outputs for pipelined operation
❐ Optimal for performance (double-cycle deselect)
• Depth expansion without wait state
enables (BWX, and BWE), and global write (GW). Asynchronous
inputs include the output enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
❐ 3.3 V – 5% and + 10% core power supply (VDD
)
■ 2.5 V/3.3 V I/O power supply (VDDQ
)
■ Fast clock-to-output times
❐ 3.5 ns (for 166 MHz device)
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed write cycle.This part supports byte write
operations (see Pin Definitions on page 6 and Partial Truth Table
for Read/Write on page 9 for further details). Write cycles can be
one to four bytes wide as controlled by the byte write control
■ Provide high performance 3-1-1-1 access rate
■ User-selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed writes
inputs. GW
This
active
causes all bytes to be written.
LOW
device incorporates an additional pipelined enable register which
delays turning off the output buffers an additional cycle when a
deselect is executed. This feature enables depth expansion
without penalizing system performance.
■ Asynchronous output enable
■ Available in Pb-free 100-pin TQFP and non Pb-free 119-ball
BGA package
The CY7C1366C/CY7C1367C operates from a +3.3 V core
power supply while all outputs operate with a +3.3 V or a +2.5 V
supply. All inputs and outputs are JEDEC-standard
JESD8-5-compatible.
■ IEEE 1149.1 JTAG-compatible boundary scan
■ “ZZ” sleep mode option
For a complete list of related documentation, click here.
Functional Description
The CY7C1366C/CY7C1367C SRAM integrates 256K × 36 and
512K × 18 SRAM cells with advanced synchronous peripheral
Selection Guide
Description
Maximum access time
166 MHz Unit
3.5
180
40
ns
Maximum operating current
mA
mA
Maximum CMOS standby current
Note
1. CE is for 100-pin TQFP. 119-ball BGA is offered only in 2 Chip Enable.
3
Cypress Semiconductor Corporation
Document Number: 38-05542 Rev. *N
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 12, 2018
CY7C1366C
CY7C1367C
Logic Block Diagram – CY7C1366C
ADDRESS
REGISTER
A0,A1,A
MODE
2
A[1:0]
Q1
ADV
CLK
BURST
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQ D, DQP
BYTE
WRITE REGISTER
D
DQ D, DQP
BYTE
WRITE DRIVER
D
BW
BW
D
DQ ,DQP
c
C
DQ
BYTE
WRITE REGISTER
c,DQP C
MEMORY
ARRAY
BYTE
WRITE DRIVER
C
OUTPUT
BUFFERS
OUTPUT
REGISTERS
SENSE
AMPS
DQs
DQP
DQP
DQP
DQP
A
DQ
BYTE
WRITE DRIVER
B,DQP B
E
DQ
BYTE
WRITE REGISTER
B,DQP B
B
BW
BW
B
C
D
DQ A, DQP
BYTE
A
DQ A, DQP
BYTE
A
A
WRITE DRIVER
WRITE REGISTER
BWE
INPUT
REGISTERS
GW
ENABLE
REGISTER
PIPELINED
ENABLE
CE
CE
CE
1
2
3
OE
SLEEP
ZZ
CONTROL
Logic Block Diagram – CY7C1367C
ADDRESS
REGISTER
A0, A1,
A
2
A[1:0]
MODE
ADV
Q1
BURST
CLK
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQ
BYTE
WRITE DRIVER
B , DQP B
DQ B, DQP
BYTE
WRITE REGISTER
B
OUTPUT
BUFFERS
BW
B
OUTPUT
REGISTERS
DQ s,
DQP
DQP
SENSE
AMPS
MEMORY
ARRAY
A
DQ A, DQP
BYTE
A
B
E
DQ
A , DQP A
BYTE
WRITE REGISTER
BW
A
WRITE DRIVER
BWE
GW
INPUT
REGISTERS
ENABLE
REGISTER
CE
CE
1
PIPELINED
ENABLE
2
3
CE
OE
SLEEP
CONTROL
ZZ
Document Number: 38-05542 Rev. *N
Page 2 of 32
CY7C1366C
CY7C1367C
Contents
Pin Configurations ...........................................................4
Pin Definitions ..................................................................6
Functional Overview ........................................................7
Single Read Accesses ................................................7
Single Write Accesses Initiated by ADSP ...................8
Single Write Accesses Initiated by ADSC ...................8
Burst Sequences .........................................................8
Sleep Mode .................................................................8
Interleaved Burst Address Table .................................8
Linear Burst Address Table .........................................8
ZZ Mode Electrical Characteristics ..............................8
Partial Truth Table for Read/Write ..................................9
Partial Truth Table for Read/Write ..................................9
IEEE 1149.1 Serial Boundary Scan (JTAG) ..................10
Disabling the JTAG Feature ......................................10
Test Access Port (TAP) .............................................10
PERFORMING A TAP RESET ..................................10
TAP REGISTERS ......................................................10
TAP Instruction Set ...................................................11
TAP Controller State Diagram .......................................12
TAP Controller Block Diagram ......................................13
TAP Timing ......................................................................13
TAP AC Switching Characteristics ...............................14
3.3 V TAP AC Test Conditions .......................................14
3.3 V TAP AC Output Load Equivalent .........................14
2.5 V TAP AC Test Conditions .......................................14
2.5 V TAP AC Output Load Equivalent .........................14
TAP DC Electrical Characteristics
Identification Register Definitions ................................16
Scan Register Sizes .......................................................16
Identification Codes .......................................................16
Boundary Scan Order ....................................................17
Maximum Ratings ...........................................................18
Operating Range .............................................................18
Neutron Soft Error Immunity .........................................18
Electrical Characteristics ...............................................18
Capacitance ....................................................................19
Thermal Resistance ........................................................19
AC Test Loads and Waveforms .....................................20
Switching Characteristics ..............................................21
Switching Waveforms ....................................................22
Ordering Information ......................................................26
Ordering Code Definitions .........................................26
Package Diagrams ..........................................................27
Acronyms ........................................................................28
Document Conventions .................................................28
Units of Measure .......................................................28
Document History Page .................................................29
Sales, Solutions, and Legal Information ......................32
Worldwide Sales and Design Support .......................32
Products ....................................................................32
PSoC® Solutions ......................................................32
Cypress Developer Community .................................32
Technical Support .....................................................32
and Operating Conditions .............................................15
Document Number: 38-05542 Rev. *N
Page 3 of 32
CY7C1366C
CY7C1367C
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout (3 Chip Enables)
DQPC
1
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
VDDQ
VSSQ
NC
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQC
2
DQC
VDDQ
VSSQ
DQC
3
4
5
6
DQC
7
NC
DQC
8
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
DQC
9
10
11
9
VSSQ
VDDQ
DQC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
12
DQC
13
NC
14
VDD
15
NC
VDD
ZZ
CY7C1367C
(512K × 18)
CY7C1366C
(256K × 36)
NC
16
VDD
ZZ
VSS
17
DQD
18
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
DQD
19
20
21
VDDQ
VSSQ
DQD
22
DQD
23
DQD
24
DQD
25
26
27
NC
VSSQ
VDDQ
DQD
DQD
29
VSSQ
VDDQ
NC
NC
NC
VSSQ
VDDQ
NC
NC
NC
28
DQPD
30
Document Number: 38-05542 Rev. *N
Page 4 of 32
CY7C1366C
CY7C1367C
Pin Configurations (continued)
Figure 2. 119-ball BGA (14 × 22 × 2.4 mm) pinout (2 Chip Enable with JTAG)
CY7C1366C (256K × 36)
1
2
3
4
5
6
7
A
VDDQ
A
A
A
A
VDDQ
ADSP
ADSC
VDD
B
C
NC/288M
NC/144M
CE2
A
A
A
A
A
A
A
NC/576M
NC/1G
D
E
F
DQC
DQC
VDDQ
DQPC
DQC
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQPB
DQB
DQB
DQB
CE1
DQC
DQB
VDDQ
OE
G
H
J
DQC
DQC
VDDQ
DQD
DQC
DQC
VDD
BWC
VSS
NC
BWB
VSS
NC
DQB
DQB
VDD
DQA
DQB
DQB
VDDQ
DQA
ADV
GW
VDD
K
DQD
VSS
CLK
NC
VSS
L
M
N
DQD
VDDQ
DQD
DQD
DQD
DQD
DQA
DQA
DQA
DQA
VDDQ
DQA
BWD
VSS
VSS
BWA
VSS
VSS
BWE
A1
DQD
NC
DQPD
A
VSS
A0
VSS
NC
DQPA
A
DQA
NC
P
R
MODE
VDD
T
NC
NC/72M
TMS
A
A
A
NC/36M
NC
ZZ
U
VDDQ
TDI
TCK
TDO
VDDQ
Document Number: 38-05542 Rev. *N
Page 5 of 32
CY7C1366C
CY7C1367C
Pin Definitions
Name
I/O
Description
Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK
A0, A1, A
Input-
[2]
synchronous if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1:A0 are fed to the
two-bit counter.
BWA,BWB,
Input-
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled
BWC,BWD synchronous on the rising edge of CLK.
GW
Input-
Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write
synchronous is conducted (All bytes are written, regardless of the values on BWX and BWE).
BWE
CLK
CE1
Input- Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted
synchronous LOW to conduct a byte write.
Input-
clock
Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
Input-
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
synchronous and CE3[2] to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a
new external address is loaded.
CE2
Input-
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE3[2] to select/deselect the device. CE2 is sampled only when a new external address is loaded.
[2]
CE3
Input- Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE to select/deselect the device.
CE [2] is assumed
3
Not connected for BGA. Where referenced,
2
active throughout this document for BGA.
CE3 is sampled only when a new external address is loaded.
OE
Input-
Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
asynchronous the I/O pins behave as outputs. When deasserted HIGH, DQ pins are tristated, and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
Input-
Advance input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
synchronous automatically increments the address in a burst cycle.
ADSP
Input- Address strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted
synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH.
ADSC
ZZ
Input-
Address strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted
synchronous LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
Input-
ZZ “sleep” input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep”
asynchronous condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ
pin has an internal pull-down.
I/O-
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
DQs,
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX
are placed in a tristate condition.
DQPs
VDD
Power supply Power supply inputs to the core of the device.
VSS
Ground
Ground for the core of the device.
VSSQ
VDDQ
I/O ground Ground for the I/O circuitry.
I/O power Power supply for the I/O circuitry.
supply
Note
2. CE is for 100-pin TQFP. 119-ball BGA is offered only in 2 Chip Enable.
3
Document Number: 38-05542 Rev. *N
Page 6 of 32
CY7C1366C
CY7C1367C
Pin Definitions (continued)
Name
MODE
I/O
Description
Input-
static
Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence. This is a strap pin and should remain static during device operation.
Mode pin has an internal pull-up.
TDO
TDI
JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is
output
not being used, this pin should be disconnected. This pin is not available on TQFP packages.
synchronous
JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being
input
used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages.
synchronous
TMS
JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being
input
used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages.
synchronous
TCK
NC
JTAG-
clock
Clock input to the JTAG circuitry. If the JTAG feature is not being used, this pin must be connected
to VSS. This pin is not available on TQFP packages.
–
No connects. Not internally connected to the die.18M, 36M, 72M, 144M, 288M, 576M, and 1G are
address expansion pins and are not internally connected to the die.
output tristate control.
is ignored if
is
CE1
selection and
HIGH.
ADSP
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) chip selects are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is
HIGH. The address presented to the address inputs is stored into
the address advancement logic and the address register while
being presented to the memory core. The corresponding data is
allowed to propagate to the input of the output registers. At the
rising edge of the next clock the data is allowed to propagate
through the output register and on the data bus within tco if OE
is active LOW. The only exception occurs when the SRAM is
emerging from a deselected state to a selected state, its outputs
are always tristated during the first cycle of the access. After the
first cycle of the access, the outputs are controlled by the OE
signal. Consecutive single read cycles are supported.
The CY7C1366C/CY7C1367C supports secondary cache in
systems using either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486™ processors.
The linear burst sequence is suited for processors that use a
linear burst sequence. The burst order is user selectable, and is
determined by sampling the MODE input. Accesses can be
initiated with either the processor address strobe (ADSP) or the
controller address strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BWX) inputs. A global write enable
(GW) overrides all byte write inputs and writes data to all four
bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
The CY7C1366C/CY7C1367C is a double-cycle deselect part.
Once the SRAM is deselected at clock rise by the chip select and
either ADSP or ADSC signals, its output will tristate immediately
after the next clock rise.
[3]
Synchronous chip selects CE1, CE2, CE3
and an
asynchronous output enable (OE) provide for easy bank
Note
3. CE is for 100-pin TQFP. 119-ball BGA is offered only in 2 Chip Enable.
3
Document Number: 38-05542 Rev. *N
Page 7 of 32
CY7C1366C
CY7C1367C
Single Write Accesses Initiated by ADSP
Burst Sequences
This access is initiated when both of the following conditions are
satisfied at clock rise: (1) ADSP is asserted LOW, and (2) chip
select is asserted active. The address presented is loaded into
the address register and the address advancement logic while
being delivered to the memory core. The write signals (GW,
BWE, and BWX) and ADV inputs are ignored during this first
cycle.
The CY7C1366C/CY7C1367C provides a two-bit wraparound
counter, fed by A[1:0], that implements either an interleaved or
linear burst sequence. The interleaved burst sequence is
designed specifically to support Intel Pentium applications. The
linear burst sequence is designed to support processors that
follow a linear burst sequence. The burst sequence is user
selectable through the MODE input. Both read and write burst
operations are supported.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQx inputs is written into the
corresponding address location in the memory core. If GW is
Asserting ADV LOW at clock rise automatically increments the
burst counter to the next address in the burst sequence. Both
read and write burst operations are supported.
HIGH, then the write operation is controlled by BWE and
BWX
Sleep Mode
signals. The CY7C1366C/CY7C1367C provides byte write
capability that is described in the Write Cycle Description table.
Asserting the byte write enable input (BWE) with the selected
byte write input will selectively write to only the desired bytes.
Bytes not selected during a byte write operation remain
unaltered. A synchronous self-timed write mechanism is
provided to simplify the write operations.
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation ‘sleep’ mode. Two clock
cycles are required to enter into or exit from this ‘sleep’ mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the ‘sleep’ mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the ‘sleep’ mode. CEs,
ADSP, and ADSC must remain inactive for the duration of tZZREC
after the ZZ input returns LOW.
Because the CY7C1366C/CY7C1367C is a common I/O device,
the output enable (OE) must be deasserted HIGH before
presenting data to the DQ inputs. Doing so tristates the output
drivers. As a safety precaution, DQ are automatically tristated
whenever a write cycle is detected, regardless of the state of OE.
Interleaved Burst Address Table
(MODE = Floating or VDD
)
Single Write Accesses Initiated by ADSC
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
ADSC write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted
HIGH, (3) chip select is asserted active, and (4) the appropriate
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
combination of the write inputs (GW, BWE, and
) are
BWX
asserted active to conduct a write to the desired byte(s). ADSC
triggered write accesses require a single clock cycle to complete.
The address presented is loaded into the address register and
the address advancement logic while being delivered to the
memory core. The ADV input is ignored during this cycle. If a
global write is conducted, the data presented to the DQX is
written into the corresponding address location in the memory
core. If a byte write is conducted, only the selected bytes are
written. Bytes not selected during a byte write operation remain
unaltered. A synchronous self-timed write mechanism is
provided to simplify the write operations.
Linear Burst Address Table
(MODE = GND)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
Because the CY7C1366C/CY7C1367C is a common I/O device,
the output enable (OE) must be deasserted HIGH before
presenting data to the DQX inputs. Doing so tristates the output
drivers. As a safety precaution, DQX are automatically tristated
whenever a write cycle is detected, regardless of the state of OE.
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
Min
Max
50
Unit
mA
ns
ZZ > VDD– 0.2 V
–
tZZS
ZZ > VDD – 0.2 V
ZZ < 0.2 V
–
2tCYC
–
2tCYC
–
tZZREC
tZZI
ns
ZZ active to sleep current
This parameter is sampled
2tCYC
–
ns
tRZZI
ZZ inactive to exit sleep current This parameter is sampled
0
ns
Document Number: 38-05542 Rev. *N
Page 8 of 32
CY7C1366C
CY7C1367C
Partial Truth Table for Read/Write
The Partial Truth Table for Read/Write for CY7C1366C follows. [4, 5]
Function (CY7C1366C)
GW
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
BWE
H
L
BWD
X
H
H
H
H
H
H
H
H
L
BWC
X
H
H
H
H
L
BWB
BWA
X
H
L
Read
Read
X
H
H
L
Write byte A – (DQA and DQPA)
Write byte B – (DQB and DQPB)
Write bytes B, A
L
L
H
L
L
L
Write byte C – (DQC and DQPC)
Write bytes C, A
L
H
H
L
H
L
L
L
Write bytes C, B
L
L
H
L
Write bytes C, B, A
Write byte D – (DQD and DQPD)
Write bytes D, A
L
L
L
L
H
H
H
H
L
H
H
L
H
L
L
L
Write bytes D, B
L
L
H
L
Write bytes D, B, A
Write bytes D, C
L
L
L
L
L
H
H
L
H
L
Write bytes D, C, A
Write bytes D, C, B
Write all bytes
L
L
L
L
L
L
H
L
L
L
L
L
Write all bytes
X
X
X
X
X
Partial Truth Table for Read/Write
The Partial Truth Table for Read/Write for CY7C1367C follows. [4, 5]
Function (CY7C1367C)
GW
H
BWE
BWB
X
BWA
X
Read
Read
H
L
L
L
L
X
H
H
H
Write byte A – (DQA and DQPA)
Write byte B – (DQB and DQPB)
Write all bytes
H
H
L
H
L
H
H
L
L
Write all bytes
L
X
X
Notes
4. All voltages referenced to V (GND).
SS
5. This part has a voltage regulator internally; t
be initiated.
is the time that the power needs to be supplied above V
initially before a read or write operation can
POWER
DD(minimum)
Document Number: 38-05542 Rev. *N
Page 9 of 32
CY7C1366C
CY7C1367C
Performing a TAP Reset
IEEE 1149.1 Serial Boundary Scan (JTAG)
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
The CY7C1366C incorporates a serial boundary scan test
access port (TAP) in the BGA package only. The TQFP package
does not offer this functionality. This part operates in accordance
with IEEE Standard 1149.1-1900, but does not have the set of
functions required for full 1149.1 compliance. These functions
from the IEEE specification are excluded because their inclusion
places an added delay in the critical speed path of the SRAM.
Note that the TAP controller functions in a manner that does not
conflict with the operation of other devices using 1149.1 fully
compliant TAPs. The TAP operates using JEDEC-standard 3.3 V
or 2.5 V I/O logic levels.
At power up, the TAP is reset internally to ensure that TDO
comes up in a high Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
enable data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
The CY7C1366C contains a TAP controller, instruction register,
boundary scan register, bypass register, and ID register.
Instruction Register
Disabling the JTAG Feature
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 13. Upon power-up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as described
in the previous section.
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device comes
up in a reset state which does not interfere with the operation of
the device.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to enable
fault isolation of the board-level serial test data path.
Test Access Port (TAP)
Bypass Register
Test Clock (TCK)
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This enables data to be shifted through the
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
SRAM with minimal delay. The bypass register is set LOW (VSS
when the BYPASS instruction is executed.
)
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used. The ball is pulled up
internally, resulting in a logic HIGH level.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
Test Data-In (TDI)
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information about
loading the instruction register, see the TAP Controller State
Diagram on page 12. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
The Boundary Scan Order on page 17 show the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI and the LSB is connected to TDO.
Test Data-Out (TDO)
Identification (ID) Register
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine (see Identification Codes on page 16).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 16.
Document Number: 38-05542 Rev. *N
Page 10 of 32
CY7C1366C
CY7C1367C
controller is in a Shift-DR state. It also places all SRAM outputs
into a high Z state.
TAP Instruction Set
Overview
SAMPLE/PRELOAD
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Identification
Codes on page 16. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in detail in this section.
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
The TAP controller used in this SRAM is not fully compliant to the
1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O buffers.
The SRAM does not implement the 1149.1 commands EXTEST
or INTEST or the PRELOAD portion of SAMPLE/PRELOAD;
rather, it performs a capture of the I/O ring when these
instructions are executed.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction once it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK# captured in the boundary scan register.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is to be
executed whenever the instruction register is loaded with all 0s.
EXTEST is not implemented in this SRAM TAP controller, and
therefore this device is not compliant to 1149.1. The TAP
controller does recognize an all-0 instruction.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD enables an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between the
two instructions. Unlike the SAMPLE/PRELOAD instruction,
EXTEST places the SRAM outputs in a high Z state.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required - that is, while data captured
is shifted out, the preloaded data can be shifted in.
IDCODE
BYPASS
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO balls. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
The IDCODE instruction is loaded into the instruction register
upon power up or whenever the TAP controller is given a test
logic reset state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO balls when the TAP
Document Number: 38-05542 Rev. *N
Page 11 of 32
CY7C1366C
CY7C1367C
TAP Controller State Diagram
TEST-LOGIC
1
RESET
0
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
1
1
EXIT1-DR
EXIT1-IR
0
0
PAUSE-DR
0
PAUSE-IR
1
0
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
0
1
0
The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
Document Number: 38-05542 Rev. *N
Page 12 of 32
CY7C1366C
CY7C1367C
TAP Controller Block Diagram
0
0
Bypass Register
2
1
Selection
Circuitry
Selection
Circuitry
Instruction Register
31 30 29
Identification Register
TDI
TDO
.
.
.
2
1
0
x
.
.
.
.
. 2 1
0
Boundary Scan Register
TAP CONTROLLER
TCK
TM S
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TM SS
TDIS
TM SH
Test M ode Select
(TM S)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
Document Number: 38-05542 Rev. *N
Page 13 of 32
CY7C1366C
CY7C1367C
TAP AC Switching Characteristics
Over the Operating Range
Parameter [6, 7]
Clock
Description
Min
Max
Unit
tTCYC
TCK clock cycle time
TCK clock frequency
TCK clock HIGH time
TCK clock LOW time
50
–
–
20
–
ns
MHz
ns
tTF
tTH
20
20
tTL
–
ns
Output Times
tTDOV
tTDOX
Setup Times
tTMSS
tTDIS
TCK clock LOW to TDO valid
TCK clock LOW to TDO invalid
–
0
10
–
ns
ns
TMS setup to TCK clock rise
TDI setup to TCK clock rise
Capture setup to TCK rise
5
5
5
–
–
–
ns
ns
ns
tCS
Hold Times
tTMSH
tTDIH
TMS hold after TCK clock rise
TDI hold after clock rise
5
5
5
–
–
–
ns
ns
ns
tCH
Capture hold after clock rise
3.3 V TAP AC Test Conditions
2.5 V TAP AC Test Conditions
Input pulse levels ...............................................VSS to 3.3 V
Input rise and fall times ...................................................1 ns
Input timing reference levels ......................................... 1.5 V
Output reference levels ................................................ 1.5 V
Test load termination supply voltage ............................ 1.5 V
Input pulse levels ...............................................VSS to 2.5 V
Input rise and fall time ....................................................1 ns
Input timing reference levels ....................................... 1.25 V
Output reference levels .............................................. 1.25 V
Test load termination supply voltage .......................... 1.25 V
3.3 V TAP AC Output Load Equivalent
2.5 V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
50Ω
TDO
TDO
ZO= 50Ω
20pF
ZO= 50Ω
20pF
Notes
6.
7. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.
t
and t refer to the setup and hold time requirements of latching data from the boundary scan register.
CH
CS
R
F
Document Number: 38-05542 Rev. *N
Page 14 of 32
CY7C1366C
CY7C1367C
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.3 V ± 0.165 V unless otherwise noted)
Parameter [8]
Description
Conditions
VDDQ = 3.3 V
Min
2.4
2.0
2.9
2.1
–
Max
Unit
V
VOH1
Output HIGH voltage
IOH = –4.0 mA
IOH = –1.0 mA
IOH = –100 µA
–
VDDQ = 2.5 V
VDDQ = 3.3 V
VDDQ = 2.5 V
VDDQ = 3.3 V
VDDQ = 2.5 V
VDDQ = 3.3 V
VDDQ = 2.5 V
VDDQ = 3.3 V
VDDQ = 2.5 V
VDDQ = 3.3 V
VDDQ = 2.5 V
–
V
VOH2
VOL1
VOL2
VIH
Output HIGH voltage
Output LOW voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Input load current
–
V
–
0.4
V
IOL = 8.0 mA
IOL = 8.0 mA
IOL = 100 µA
V
–
0.4
V
–
0.2
V
–
0.2
V
2.0
1.7
–0.5
–0.3
–5
VDD + 0.3
VDD + 0.3
0.7
V
V
VIL
V
0.7
V
IX
GND < VIN < VDDQ
5
µA
Notes
8. All voltages referenced to V (GND).
SS
Document Number: 38-05542 Rev. *N
Page 15 of 32
CY7C1366C
CY7C1367C
Identification Register Definitions
CY7C1366C
(256K × 36)
Instruction Field
Description
Revision number (31:29)
Device depth (28:24) [9]
000
01011
Describes the version number.
Reserved for Internal Use
Device width (23:18) 119-ball BGA
Cypress device ID (17:12)
101110
100110
00000110100
1
Defines memory type and architecture
Defines width and density
Cypress JEDEC ID code (11:1)
ID register presence indicator (0)
Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size (× 36)
Instruction
3
1
Bypass
ID
32
71
Boundary scan order (119-ball BGA package)
Identification Codes
Instruction
EXTEST
Code
Description
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM outputs to high Z state.
IDCODE
001
010
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
SAMPLE Z
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM output drivers to a high Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does
not affect SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Note
9. Bit #24 is “1” in the Register Definitions for both 2.5 V and 3.3 V versions of this device.
Document Number: 38-05542 Rev. *N
Page 16 of 32
CY7C1366C
CY7C1367C
Boundary Scan Order
119-ball BGA
CY7C1366C (256K × 36)
Bit #
1
Ball ID
Signal Name
CLK
GW
BWE
OE
Bit #
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
Ball ID
P4
Signal Name
A0
K4
H4
M4
F4
B4
A4
G4
C3
B3
D6
H7
G6
E6
D7
E7
F6
G7
H6
T7
K7
L6
2
N4
A1
3
R6
A
4
T5
A
5
ADSC
ADSP
ADV
A
T3
A
6
R2
A
7
R3
MODE
DQPD
DQD
DQD
DQD
DQD
DQD
DQD
DQD
DQD
Internal
DQC
DQC
DQC
DQC
DQC
DQC
DQC
DQC
DQPC
A
8
P2
9
A
P1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
DQPB
DQB
DQB
DQB
DQB
DQB
DQB
DQB
DQB
ZZ
L2
K1
N2
N1
M2
L1
K2
Internal
H1
G2
E2
DQA
DQA
DQA
DQA
DQA
DQA
DQA
DQA
DQPA
A
D1
N6
P7
N7
M6
L7
H2
G1
F2
E1
D2
K6
P6
T4
A3
C5
B5
A5
C6
A6
B6
C2
A2
A
E4
CE1
A
B2
CE2
A
L3
BWD
BWC
BWB
BWA
Internal
A
G3
G5
L5
A
A
A
Internal
A
Document Number: 38-05542 Rev. *N
Page 17 of 32
CY7C1366C
CY7C1367C
Maximum Ratings
Operating Range
Ambient
Temperature
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Range
Commercial 0 °C to +70 °C
VDD
VDDQ
3.3 V– 5% / 2.5 V – 5% to
Storage temperature ................................ –65 °C to +150 °C
+ 10%
VDD
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Supply voltage on VDD relative to GND .......–0.5 V to +4.6 V
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
Neutron Soft Error Immunity
Test
Parameter Description
Conditions
Typ Max* Unit
DC voltage applied to outputs
in tristate ...........................................–0.5 V to VDDQ + 0.5 V
LSBU
LMBU
SEL
Logical
single-bit
upsets
25 °C
25 °C
85 °C
361 394 FIT/
Mb
DC input voltage .................................–0.5 V to VDD + 0.5 V
Current into outputs (LOW) ........................................ 20 mA
Logical
multi-bit
upsets
0
0
0.01 FIT/
Mb
Static discharge voltage
(per MIL-STD-883, method 3015) ..........................> 2001 V
Latch-up current ....................................................> 200 mA
Single event
latch-up
0.1
FIT/
Dev
* No LMBU or SEL events occurred during testing; this column represents a
2
statistical , 95% confidence limit calculation. For more details refer to
Application Note AN54908 “Accelerated Neutron SER Testing and Calculation of
Terrestrial Failure Rates”.
Electrical Characteristics
Over the Operating Range
Parameter [10, 11]
Description
Power supply voltage
I/O supply voltage
Test Conditions
Min
3.135
3.135
2.375
2.4
Max
3.6
Unit
V
VDD
VDDQ
for 3.3 V I/O
for 2.5 V I/O
VDD
2.625
–
V
V
VOH
VOL
VIH
VIL
IX
Output HIGH voltage
Output LOW voltage
Input HIGH voltage [10]
Input LOW voltage [10]
for 3.3 V I/O, IOH =4.0 mA
for 2.5 V I/O, IOH =1.0 mA
for 3.3 V I/O, IOL=8.0 mA
for 2.5 V I/O, IOL= 1.0 mA
for 3.3 V I/O
V
2.0
–
V
–
0.4
V
–
0.4
V
2.0
VDD + 0.3
VDD + 0.3
0.8
V
for 2.5 V I/O
1.7
V
for 3.3 V I/O
–0.3
–0.3
–5
V
for 2.5 V I/O
0.7
V
Input leakage current except ZZ GND VI VDDQ
and MODE
5
µA
Input current of MODE
Input = VSS
–30
–
–
5
µA
µA
µA
µA
µA
Input = VDD
Input current of ZZ
Input = VSS
–5
–
–
Input = VDD
30
5
IOZ
Output leakage current
GND VI VDDQ, output disabled
–5
Notes
10. Overshoot: V
< V + 1.5 V (Pulse width less than t
/2), undershoot: V
> –2 V (Pulse width less than t
/2).
IH(AC)
DD
CYC
IL(AC)
CYC
11. T
: Assumes a linear ramp from 0 V to V
within 200 ms. During this time V < V and V
V
.
Power-up
DD(min)
IH
DD
DDQ
DD
Document Number: 38-05542 Rev. *N
Page 18 of 32
CY7C1366C
CY7C1367C
Electrical Characteristics (continued)
Over the Operating Range
Parameter [10, 11]
Description
Test Conditions
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
Min
Max
Unit
IDD
VDD operating supply current
6 ns cycle,
166 MHz
–
180
mA
ISB1
ISB2
ISB3
ISB4
Automatic CE power-down
current – TTL inputs
VDD = Max, device deselected, 6 ns cycle,
–
–
–
–
110
40
mA
mA
mA
mA
VIN VIH or VIN VIL
f = fMAX = 1/tCYC
166 MHz
Automatic CE power-down
current – CMOS inputs
VDD = Max, device deselected, 6 ns cycle,
VIN 0.3 V or VIN > VDDQ – 0.3 V, 166 MHz
f = 0
Automatic CE power-down
current – CMOS inputs
VDD = Max, device deselected, or 6 ns cycle,
VIN 0.3 V or VIN > VDDQ – 0.3 V, 166 MHz
f = fMAX = 1/tCYC
100
40
Automatic CE power-down
current – TTL inputs
VDD = Max, device deselected, 6 ns cycle,
VIN VIH or VIN VIL,
f = 0
166 MHz
Capacitance
100-pin TQFP 119-ball BGA
Parameter [12]
Description
Test Conditions
TA = 25 °C, f = 1 MHz,
Unit
Max
Max
CIN
Input capacitance
5
5
5
5
5
7
pF
pF
pF
VDD = 3.3 V, VDDQ = 2.5 V
CCLK
CI/O
Clock input capacitance
Input/output capacitance
Thermal Resistance
100-pin TQFP 119-ball BGA
Parameter [12]
Description
Test Conditions
Unit
Package
Package
JA
Thermal resistance
(junction to ambient)
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
29.41
34.1
°C/W
JC
Thermal resistance
(junction to case)
6.31
14.0
°C/W
Note
12. Tested initially and after any design or process change that may affect these parameters
Document Number: 38-05542 Rev. *N
Page 19 of 32
CY7C1366C
CY7C1367C
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317
3.3 V
OUTPUT
ALL INPUT PULSES
90%
VDDQ
OUTPUT
90%
10%
Z = 50
0
10%
R = 50
L
GND
5 pF
R = 351
1ns
1ns
V = 1.5 V
T
INCLUDING
JIG AND
SCOPE
(c)
(a)
2.5 V I/O Test Load
(b)
R = 1667
2.5 V
OUTPUT
R = 50
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50
0
10%
L
5 pF
R =1538
1ns
1ns
V = 1.25 V
T
INCLUDING
JIG AND
SCOPE
(c)
(a)
(b)
Document Number: 38-05542 Rev. *N
Page 20 of 32
CY7C1366C
CY7C1367C
Switching Characteristics
Over the Operating Range
-166
Parameter [13, 14]
Description
VDD(typical) to the first access [15]
Unit
Min
Max
tPOWER
Clock
tCYC
1
–
ms
Clock cycle time
Clock HIGH
6.0
2.4
2.4
–
–
–
ns
ns
ns
tCH
tCL
Clock LOW
Output Times
tCO
Data output valid after CLK rise
Data output hold after CLK rise
Clock to low Z [16, 17, 18]
–
1.25
1.25
1.25
–
3.5
–
ns
ns
ns
ns
ns
ns
ns
tDOH
tCLZ
–
tCHZ
Clock to high Z [16, 17, 18]
3.5
3.5
–
tOEV
OE LOW to output valid
tOELZ
tOEHZ
Setup Times
tAS
OE LOW to output low Z [16, 17, 18]
OE HIGH to output high Z [16, 17, 18]
0
–
3.5
Address setup before CLK rise
ADSC, ADSP setup before CLK rise
ADV setup before CLK rise
1.5
1.5
1.5
1.5
1.5
1.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tADS
tADVS
tWES
GW, BWE, BWX setup before CLK rise
Data input setup before CLK rise
Chip enable setup before CLK rise
tDS
tCES
Hold Times
tAH
Address hold after CLK rise
ADSP, ADSC hold after CLK rise
ADV hold after CLK rise
0.5
0.5
0.5
0.5
0.5
0.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tADH
tADVH
tWEH
GW, BWE, BWX hold after CLK rise
Data input hold after CLK rise
Chip enable hold after CLK rise
tDH
tCEH
Notes
13. Timing reference level is 1.5 V when V
= 3.3 V and is 1.25 V when V
= 2.5 V.
DDQ
DDQ
14. Test conditions shown in (a) of Figure 3 on page 20 unless otherwise noted.
15. This part has a voltage regulator internally; t
is the time that the power needs to be supplied above V
initially before a read or write operation can
POWER
DD(minimum)
be initiated.
16. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of Figure 3 on page 20. Transition is measured ±200 mV from steady-state voltage.
CHZ CLZ OELZ
OEHZ
17. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same data
CLZ
OEHZ
OELZ
CHZ
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high Z prior to low Z under the same system conditions.
18. This parameter is sampled and not 100% tested.
Document Number: 38-05542 Rev. *N
Page 21 of 32
CY7C1366C
CY7C1367C
Switching Waveforms
Figure 4. Read Cycle Timing [19]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
Burst continued with
ADDRESS
t
t
WEH
WES
new base address
GW, BWE,BW
X
Deselect
cycle
t
t
CEH
CES
CE
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
OEV
CO
t
t
CHZ
t
t
t
OELZ
OEHZ
DOH
CLZ
t
Q(A2)
Q(A2
+
1)
Q(A2
+
2)
Q(A2
+
3)
Q(A2)
Q(A2
+
1)
Q(A3)
Q(A1)
Data Out (DQ)
High-Z
CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note
19. In this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
Document Number: 38-05542 Rev. *N
Page 22 of 32
CY7C1366C
CY7C1367C
Switching Waveforms (continued)
Figure 5. Write Cycle Timing [20, 21]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
ADSC extends burst
t
t
ADH
ADS
t
t
ADH
ADS
t
t
AH
AS
A1
A2
A3
ADDRESS
BWE,
Byte write signals are ignored for first cycle when
ADSP initiates burst
t
t
WEH
WES
BW
X
t
t
WEH
WES
GW
CE
t
t
CEH
CES
t
t
ADVH
ADVS
ADV
OE
ADV suspends burst
t
t
DH
DS
D(A2)
D(A2
+
1)
D(A2
+
1)
D(A2
+
2)
D(A2
+
3)
D(A3)
D(A3
+
1)
D(A3
+
2)
D(A1)
High-Z
Data in (D)
t
OEHZ
Data Out (Q)
BURST READ
BURST WRITE
Single WRITE
Extended BURST WRITE
DON’T CARE
UNDEFINED
Notes
20. In this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
21.
Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW LOW.
X
Document Number: 38-05542 Rev. *N
Page 23 of 32
CY7C1366C
CY7C1367C
Switching Waveforms (continued)
Figure 6. Read/Write Cycle Timing [22, 23, 24]
t
CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t
t
AH
AS
A1
A2
A3
A4
A5
A6
ADDRESS
t
t
WEH
WES
BWE, BW
X
t
t
CEH
CES
CE
ADV
OE
t
t
DH
t
CO
DS
t
OELZ
Data In (D)
High-Z
D(A3)
D(A5)
D(A6)
t
t
OEHZ
CLZ
Data Out (Q)
Q(A1)
Back-to-Back READs
Q(A2)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
High-Z
BURST READ
Back-to-Back
WRITEs
Single WRITE
DON’T CARE
UNDEFINED
Notes
22. In this diagram, when CE is LOW: CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH: CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
23. The data bus (Q) remains in high Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
24. GW is HIGH.
Document Number: 38-05542 Rev. *N
Page 24 of 32
CY7C1366C
CY7C1367C
Switching Waveforms (continued)
Figure 7. ZZ Mode Timing [25, 26]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes
25. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
26. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 38-05542 Rev. *N
Page 25 of 32
CY7C1366C
CY7C1367C
Ordering Information
The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your
local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary
page at http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices
Speed
(MHz)
Package
Diagram
Operating
Range
Part and Package Type
Ordering Code
166 CY7C1366C-166AXC
CY7C1367C-166AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
Ordering Code Definitions
CY
7
C 13XX C - 166 A X C
Temperature Range:
C = Commercial
Pb-free
Package Type:
A = 100-pin TQFP
Speed Grade: 166 MHz
Process Technology: C 90 nm
Part Identifier: 13XX = 1366 or 1367
1366 = DCD, 256K × 36 (9Mb)
1367 = DCD, 512K × 18 (9Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05542 Rev. *N
Page 26 of 32
CY7C1366C
CY7C1367C
Package Diagrams
Figure 8. 100-pin TQFP (16 × 22 × 1.6 mm) A100RA Package Outline, 51-85050
ș 2
ș
1
ș
DIMENSIONS
MIN. NOM. MAX.
1.60
NOTE:
SYMBOL
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. BODY LENGTH DIMENSION DOES NOT
INCLUDE MOLD PROTRUSION/END FLASH.
MOLD PROTRUSION/END FLASH SHALL
A
0.05
0.15
A1
A2
D
1.35 1.40 1.45
15.80 16.00 16.20
13.90 14.00 14.10
21.80 22.00 22.20
19.90 20.00 20.10
NOT EXCEED 0.0098 in (0.25 mm) PER SIDE.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC
D1
E
E1
BODY SIZE INCLUDING MOLD MISMATCH.
3. JEDEC SPECIFICATION NO. REF: MS-026.
0.08
0.08
0°
R
R
ș
0.20
0.20
7°
1
2
ș 1
ș 2
c
0°
11° 12° 13°
0.20
0.22 0.30 0.38
0.45 0.60 0.75
1.00 REF
b
L
L1
L 2
L 3
e
0.25 BSC
0.20
0.65 TYP
51-85050 *G
Document Number: 38-05542 Rev. *N
Page 27 of 32
CY7C1366C
CY7C1367C
Acronyms
Document Conventions
Units of Measure
Acronym
Description
BGA
CE
Ball Grid Array
Chip Enable
Symbol
°C
Unit of Measure
degree Celsius
megahertz
microampere
milliampere
millimeter
millisecond
millivolt
MHz
µA
mA
mm
ms
mV
nm
ns
CMOS
EIA
Complementary Metal Oxide Semiconductor
Electronic Industries Alliance
Input/Output
I/O
JEDEC
JTAG
LMBU
LSB
Joint Electron Devices Engineering Council
Joint Test Action Group
Logical Multi-Bit Upsets
Least Significant Bit
nanometer
nanosecond
ohm
LSBU
MSB
OE
Logical Single-Bit Upsets
Most Significant Bit
%
percent
Output Enable
pF
V
picofarad
volt
SEL
Single Event Latch-up
Static Random Access Memory
Test Access Port
SRAM
TAP
W
watt
TCK
TMS
TDI
Test Clock
Test Mode Select
Test Data-In
TDO
TQFP
TTL
Test Data-Out
Thin Quad Flat Pack
Transistor-Transistor Logic
Document Number: 38-05542 Rev. *N
Page 28 of 32
CY7C1366C
CY7C1367C
Document History Page
Document Title: CY7C1366C/CY7C1367C, 9-Mbit (256K × 36/512K × 18) Pipelined DCD Sync SRAM
Document Number: 38-05542
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
241690
278969
RKF
RKF
07/12/2004 New data sheet.
*A
10/18/2004 Updated Boundary Scan Order (Changed to match the B rev of these devices).
Updated Boundary Scan order (Changed to match the B rev of these devices).
*B
332059
PCI
03/11/2005 Updated Features (Changed frequency from 225 MHz to 250 MHz).
Updated Selection Guide (Changed frequency from 225 MHz to 250 MHz;
unshaded 200 MHz and 166 MHz frequency related information).
Updated Pin Configurations (Address expansion pins/balls in the pinouts for
all packages are modified as per JEDEC standard).
Updated Pin Definitions (Added Address Expansion pins).
Updated Functional Overview (Added ZZ Mode Electrical Characteristics).
Updated Identification Register Definitions (Splitted Device Width (23:18) into
two rows; retained the same values for 165-ball FBGA; Changed Device Width
(23:18) for 119-ball BGA from 000110 to 101110).
Updated Electrical Characteristics (Changed frequency from 225 MHz to
250 MHz; unshaded 200 MHz and 166 MHz frequency related information;
Updated Test Conditions of VOL, VOH parameters; changed maximum value of
ISB1 parameter from 50 mA to 130 mA, 120 mA, and 110 mA for 250 MHz,
200 MHz, and 166 MHz; changed maximum value of ISB3 parameter from
50 mA to 120 mA, 110 mA, and 100 mA for 250 MHz, 200 MHz, and 166 MHz).
Updated Thermal Resistance (Changed value of JA and JC parameters
from 25 C/W and 9 C/W to 29.41 C/W and 6.31 C/W respectively for 100-pin
TQFP Package; changed value of JA andJC parameters from 25 C/W and
6 C/W to 34.1 C/W and 14.0 C/W respectively for 119-ball BGA Package;
changed value of JA and JC parameters from 27 C/W and 6 C/W to
16.8 C/W and 3.0 C/W respectively for 165-ball FBGA Package).
Updated Switching Characteristics (Changed frequency from 225 MHz to
250 MHz, unshaded 200 MHz and 166 MHz frequency related information;
replaced minimum value of tCYC parameter from 4.4 ns to 4.0 ns for 250 MHz
frequency).
Updated Ordering Information (Updated part numbers (Added lead-free
information for 100-pin TQFP, 119-ball BGA and 165-ball FBGA packages)).
*C
*D
377095
408298
PCI
06/10/2005 Updated Electrical Characteristics (Updated Note 11 (Modified Test Condition
from VIH < VDD to VIH VDD); changed maximum value of ISB2 parameter from
30 mA to 40 mA).
RXU
11/16/2005 Changed address of Cypress Semiconductor Corporation from “3901 North
First Street” to “198 Champion Court”.
Changed status from Preliminary to Final.
Updated Electrical Characteristics (Changed “Input Load Current except ZZ
and MODE” to “Input Leakage Current except ZZ and MODE” in the description
of IX parameter).
Updated Ordering Information (Updated part numbers; replaced Package
Name column with Package Diagram in the Ordering Information table).
*E
*F
501793
VKN
VKN
09/13/2006 Updated TAP AC Switching Characteristics (Changed minimum value of tTH
and tTL parameters from 25 ns to 20 ns; changed maximum value of tTDOV
parameter from 5 ns to 10 ns).
Updated Maximum Ratings (Added the Maximum Rating for Supply Voltage
on VDDQ Relative to GND).
Updated Ordering Information (Updated part numbers).
2756940
08/27/2009 Added Neutron Soft Error Immunity.
Updated Ordering Information (Updated part numbers; and modified the
disclaimer for the Ordering information).
Document Number: 38-05542 Rev. *N
Page 29 of 32
CY7C1366C
CY7C1367C
Document History Page (continued)
Document Title: CY7C1366C/CY7C1367C, 9-Mbit (256K × 36/512K × 18) Pipelined DCD Sync SRAM
Document Number: 38-05542
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
*G
3046851
NJY
10/04/2010 Updated Ordering Information:
No change in part numbers.
Added Ordering Code Definitions.
Updated Package Diagrams:
spec 51-85050 – Changed revision from *B to *C.
spec 51-85115 – Changed revision from *B to *C.
spec 51-85180 – Changed revision from *B to *C.
Added Acronyms and Units of Measure.
Minor edits.
Updated to new template.
Completing Sunset Review.
*H
*I
3370121
3613540
PRIT
PRIT
09/13/2011 Updated Package Diagrams
spec 51-85050 – Changed revision from *C to *D.
Completing Sunset Review.
05/10/2012 Updated Features (Removed 250 MHz, 200 MHz frequencies related
information, removed 165-ball FBGA Package related information).
Updated Functional Description (Removed the Note “For best-practices
recommendations, refer to the Cypress application note System Design
Guidelines on www.cypress.com.” and its reference).
Updated Selection Guide (Removed 250 MHz, 200 MHz frequencies related
information).
Updated Pin Configurations (Updated Figure 2(Removed CY7C1367Crelated
information), removed 165-ball FBGA Package related information).
Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Removed CY7C1367C
related information).
Updated Identification Register Definitions (Removed CY7C1367C related
information).
Updated Scan Register Sizes (Removed “Bit Size (× 18)” column).
Updated Boundary Scan Order (Removed CY7C1367C related information).
Removed Boundary Scan Order (Corresponding to 165-ball FBGA Package).
Updated Operating Range (Removed Industrial Temperature Range).
Updated Electrical Characteristics (Removed 250 MHz, 200 MHz frequencies
related information).
Updated Capacitance (Removed 165-ball FBGA Package related information).
Updated Thermal Resistance (Removed 165-ball FBGA Package related
information).
Updated Switching Characteristics (Removed 250 MHz, 200 MHz frequencies
related information).
Updated Package Diagrams (Removed 165-ball FBGA Package related
information (spec 51-85180 *C)).
*J
3755966
4539022
PRIT
PRIT
09/26/2012 Updated Package Diagrams:
spec 51-85115 – Changed revision from *C to *D.
Completing Sunset Review.
*K
10/15/2014 Updated Ordering Information (Updated part numbers).
Updated Package Diagrams:
spec 51-85050 – Changed revision from *D to *E.
Removed spec 51-85115 *D.
Updated to new template.
Completing Sunset Review.
*L
4575272
PRIT
11/20/2014 Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Document Number: 38-05542 Rev. *N
Page 30 of 32
CY7C1366C
CY7C1367C
Document History Page (continued)
Document Title: CY7C1366C/CY7C1367C, 9-Mbit (256K × 36/512K × 18) Pipelined DCD Sync SRAM
Document Number: 38-05542
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
*M
5515297
PRIT
11/09/2016 Updated Package Diagrams:
spec 51-85050 – Changed revision from *E to *F.
Updated to new template.
Completing Sunset Review.
*N
6028297
RMES
01/12/2018 Updated Package Diagrams:
spec 51-85050 – Changed revision from *F to *G.
Updated to new template.
Completing Sunset Review.
Document Number: 38-05542 Rev. *N
Page 31 of 32
CY7C1366C
CY7C1367C
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
Arm® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Automotive
Cypress Developer Community
Clocks & Buffers
Interface
Community | Projects | Video | Blogs | Training | Components
Technical Support
Internet of Things
Memory
cypress.com/support
cypress.com/memory
cypress.com/mcu
Microcontrollers
PSoC
cypress.com/psoc
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2004-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-05542 Rev. *N
Revised January 12, 2018
Page 32 of 32
i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation.
相关型号：
CY7C1366C-166AXIT
Cache SRAM, 256KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, PLASTIC, MS-026, TQFP-100
CYPRESS
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