CY7C1354CV25-166BZCT [CYPRESS]
ZBT SRAM, 256KX36, 3.5ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165;
| 型号： | CY7C1354CV25-166BZCT |
| 厂家： | 
CYPRESS |
| 描述： | ZBT SRAM, 256KX36, 3.5ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165 时钟 静态存储器 内存集成电路 |
| 文件： | 总35页 (文件大小：603K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1354CV25
CY7C1356CV25
9-Mbit (256K × 36/512K × 18)
Pipelined SRAM with NoBL™ Architecture
9-Mbit (256K
× 36/512K × 18) Pipelined SRAM with NoBL™ Architecture
Features
Functional Description
■ Pin-compatible with and functionally equivalent to ZBT™
■ Supports 250 MHz bus operations with zero wait states
■ Available speed grades are 250, 200, and 166 MHz
The
CY7C1354CV25/CY7C1356CV25[1]
are
2.5 V,
256K × 36/512K × 18 synchronous pipelined burst SRAMs with
No Bus Latency™ (NoBL logic, respectively. They are
designed to support unlimited true back-to-back read/write
operations
with
no
wait
states.
The
■ Internally self-timed output buffer control to eliminate the need
to use asynchronous OE
CY7C1354CV25/CY7C1356CV25 are equipped with the
advanced (NoBL) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
in systems that require frequent write/read transitions. The
CY7C1354CV25/CY7C1356CV25 are pin-compatible with and
functionally equivalent to ZBT devices.
■ Fully registered (inputs and outputs) for pipelined operation
■ Byte write capability
■ Single 2.5 V power supply (VDD
)
■ Fast clock-to-output times
❐ 2.8 ns (for 250-MHz device)
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
■ Clock enable (CEN) pin to suspend operation
■ Synchronous self-timed writes
■ Available in Pb-free 100-pin TQFP package, Pb-free and
non Pb-free 119-ball BGA package and 165-ball FBGA
package
Write operations are controlled by the byte write selects
(BWa–BWd for CY7C1354CV25 and BWa–BWb for
CY7C1356CV25) and a write enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
■ IEEE 1149.1 JTAG-compatible boundary scan
■ Burst capability – linear or interleaved burst order
■ “ZZ” sleep mode option and stop clock option
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated during
the data portion of a write sequence.
For a complete list of related documentation, click here.
Selection Guide
Description
Maximum access time
250 MHz
2.8
200 MHz
3.2
166 MHz Unit
3.5
180
40
ns
Maximum operating current
250
220
mA
mA
Maximum CMOS standby current
40
40
Note
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document Number: 38-05537 Rev. *R
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 9, 2018
CY7C1354CV25
CY7C1356CV25
Logic Block Diagram – CY7C1354CV25
ADDRESS
REGISTER 0
A0, A1, A
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
ADV/LD
C
CLK
CEN
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
O
U
T
P
O
U
T
P
S
E
N
S
D
A
T
U
T
U
T
ADV/LD
A
E
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
R
E
G
I
MEMORY
ARRAY
B
U
F
S
T
E
E
R
I
DQs
WRITE
DRIVERS
BW
BW
a
DQP
DQP
DQP
DQP
a
b
c
d
A
M
P
b
BW
BW
c
S
T
E
R
S
F
d
E
R
S
S
WE
E
E
N
G
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
READ LOGIC
CE1
CE2
CE3
SLEEP
CONTROL
ZZ
Document Number: 38-05537 Rev. *R
Page 2 of 35
CY7C1354CV25
CY7C1356CV25
Logic Block Diagram – CY7C1356CV25
ADDRESS
REGISTER 0
A0, A1, A
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
ADV/LD
C
CLK
CEN
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
O
U
T
P
O
U
T
P
S
E
N
S
D
A
T
U
T
U
T
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
A
R
E
G
I
MEMORY
ARRAY
E
B
U
F
DQs
DQP
DQP
WRITE
DRIVERS
BW
BW
a
S
T
E
E
R
I
A
M
P
a
F
b
S
T
E
R
S
b
E
R
S
S
N
G
WE
E
E
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
READ LOGIC
CE1
CE2
CE3
Sleep
Control
ZZ
Document Number: 38-05537 Rev. *R
Page 3 of 35
CY7C1354CV25
CY7C1356CV25
Contents
Pin Configurations ...........................................................5
Pin Definitions ..................................................................8
Functional Overview ........................................................9
Single Read Accesses ................................................9
Burst Read Accesses ..................................................9
Single Write Accesses .................................................9
Burst Write Accesses ................................................10
Sleep Mode ...............................................................10
Interleaved Burst Address Table ...............................10
Linear Burst Address Table .......................................10
ZZ Mode Electrical Characteristics ............................10
Truth Table ......................................................................11
Partial Truth Table for Read/Write ................................12
Partial Truth Table for Read/Write ................................12
IEEE 1149.1 Serial Boundary Scan (JTAG) ..................13
Disabling the JTAG Feature ......................................13
Test Access Port (TAP) .............................................13
PERFORMING A TAP RESET ..................................13
TAP REGISTERS ......................................................13
TAP Instruction Set ...................................................14
TAP Controller State Diagram .......................................15
TAP Controller Block Diagram ......................................16
TAP Timing ......................................................................16
TAP AC Switching Characteristics ...............................17
2.5 V TAP AC Test Conditions .......................................17
2.5 V TAP AC Output Load Equivalent .........................17
TAP DC Electrical Characteristics
Identification Register Definitions ................................18
Scan Register Sizes .......................................................18
Instruction Codes ...........................................................18
Boundary Scan Exit Order .............................................19
Boundary Scan Exit Order .............................................20
Maximum Ratings ...........................................................21
Operating Range .............................................................21
Electrical Characteristics ...............................................21
Capacitance ....................................................................22
Thermal Resistance ........................................................22
AC Test Loads and Waveforms .....................................22
Switching Characteristics ..............................................23
Switching Waveforms ....................................................24
Ordering Information ......................................................27
Ordering Code Definitions .........................................27
Package Diagrams ..........................................................28
Acronyms ........................................................................31
Document Conventions .................................................31
Units of Measure .......................................................31
Document History Page .................................................32
Sales, Solutions, and Legal Information ......................35
Worldwide Sales and Design Support .......................35
Products ....................................................................35
PSoC® Solutions ......................................................35
Cypress Developer Community .................................35
Technical Support .....................................................35
and Operating Conditions .............................................18
Document Number: 38-05537 Rev. *R
Page 4 of 35
CY7C1354CV25
CY7C1356CV25
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
DQPc
DQc
DQc
1
2
3
4
5
6
7
8
NC
NC
NC
DDQ
1
2
3
4
5
6
7
8
A
NC
NC
78
DQPb
DQb
DQb
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
80
79
V
V
DDQ
V
V
V
NC
DQPa
DQa
DQa
DDQ
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
SS
V
V
V
SS
SS
SS
DQc
DQc
NC
NC
DQb
DQb
DQb
DQb
DQb
DQc
DQc
9
DQb
9
V
V
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
SS
V
V
DDQ
DDQ
V
V
DQa
DQa
V
NC
DDQ
DDQ
DQc
DQc
NC
DQb
DQb
DQb
DQb
NC
V
SS
CY7C1354CV25
(256K × 36)
SS
V
V
DD
NC
DD
CY7C1356CV25
(512K × 18)
NC
V
NC
V
ZZ
DD
DD
V
V
SS
SS
ZZ
DQa
DQa
DQd
DQb
DQa
DQa
DQd
DQb
DDQ
V
V
DDQ
V
V
V
DQa
DQa
NC
NC
V
V
DDQ
DDQ
V
V
SS
V
SS
SS
SS
DQd
DQd
DQd
DQd
DQa
DQa
DQb
DQb
DQa DQPb
DQa
NC
V
SS
V
V
SS
SS
SS
V
V
DDQ
DDQ
V
DDQ
DDQ
DQd
DQd
DQPd
DQa
DQa
DQPa
NC
NC
NC
NC
NC
NC
Document Number: 38-05537 Rev. *R
Page 5 of 35
CY7C1354CV25
CY7C1356CV25
Pin Configurations (continued)
Figure 2. 119-ball BGA (14 × 22 × 2.4 mm) pinout
CY7C1354CV25 (256K × 36)
1
2
3
4
5
6
7
VDDQ
A
A
NC/18M
A
A
VDDQ
A
NC/576M
NC/1G
DQc
CE2
A
A
A
ADV/LD
VDD
A
A
CE3
A
NC
NC
B
C
D
DQPc
VSS
NC
VSS
DQPb
DQb
DQc
VDDQ
DQc
DQc
DQc
DQc
DQc
VDD
VSS
VSS
CE1
VSS
VSS
DQb
DQb
DQb
DQb
VDD
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
E
F
OE
A
G
H
J
BWc
VSS
NC
BWb
VSS
NC
DQc
WE
VDD
VDDQ
DQd
DQd
VDDQ
DQd
DQd
DQd
DQd
DQd
DQd
DQPd
VSS
BWd
VSS
CLK
NC
VSS
BWa
VSS
VSS
VSS
DQa
DQa
DQa
DQa
DQPa
K
L
M
N
P
CEN
A1
VSS
VSS
MODE
A
A0
NC/144M
NC
A
VDD
A
A
NC/288M
ZZ
R
T
NC
A
NC/72M
TMS
NC/36M
NC
VDDQ
TDI
TCK
TDO
VDDQ
U
CY7C1356CV25 (512K × 18)
1
2
3
4
5
6
7
VDDQ
A
A
NC/18M
A
A
VDDQ
A
B
C
D
E
F
NC/576M
NC/1G
DQb
CE2
A
A
A
NC
NC
CE3
A
ADV/LD
VDD
A
A
NC
DQb
NC
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQPa
NC
NC
NC
DQa
VDDQ
CE1
VDDQ
DQa
OE
A
NC
DQb
VDDQ
DQb
NC
VDD
VSS
VSS
NC
NC
DQa
VDD
DQa
NC
VDDQ
G
H
J
BWb
VSS
NC
WE
VDD
NC
DQb
DQb
NC
VSS
VSS
VSS
VSS
VSS
MODE
A
CLK
NC
VSS
NC
DQa
NC
DQa
NC
A
DQa
NC
K
L
BWa
VSS
VDDQ
DQb
DQb
NC
VDDQ
NC
M
N
P
R
T
CEN
A1
VSS
VSS
NC
A
NC
DQPb
A
A0
DQa
NC/144M
NC/72M
VDDQ
VDD
NC/36M
TCK
NC/288M
ZZ
A
A
TMS
TDI
TDO
NC
VDDQ
U
Document Number: 38-05537 Rev. *R
Page 6 of 35
CY7C1354CV25
CY7C1356CV25
Pin Configurations (continued)
Figure 3. 165-ball FBGA (13 × 15 × 1.4 mm) pinout
CY7C1354CV25 (256K × 36)
1
2
A
3
4
5
6
7
8
9
A
10
A
11
NC
NC/576M
NC/1G
DQPc
ADV/LD
A
B
C
D
CE1
BWc
BWd
VSS
VDD
BWb
BWa
VSS
VSS
CE3
CLK
VSS
VSS
CEN
WE
A
CE2
VDDQ
VDDQ
OE
VSS
VDD
NC/18M
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
A
NC
DQc
VSS
VSS
NC
DQb
DQPb
DQb
DQc
DQc
DQc
DQc
NC
DQc
DQc
DQc
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
DQb
DQb
DQb
NC
DQb
DQb
DQb
ZZ
E
F
G
H
J
NC
DQd
DQd
DQd
DQd
DQd
DQd
VDDQ
VDDQ
VDDQ
VDDQ
DQa
DQa
DQa
DQa
DQa
DQa
VDDQ
VDDQ
VDDQ
VDDQ
A
K
L
DQd
DQd
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC
A1
VSS
NC
VDD
VSS
A
DQa
NC
A
DQa
DQPa
M
N
P
DQPd
NC/144M NC/72M
MODE NC/36M
TDI
TDO
NC/288M
A
A
TMS
A0
TCK
A
A
A
A
R
CY7C1356CV25 (512K × 18)
1
NC/576M
NC/1G
NC
2
A
A
3
4
5
NC
6
CE3
7
8
9
A
10
A
11
A
A
B
C
D
CE1
BWb
NC
CEN
ADV/LD
CE2
VDDQ
VDDQ
BWa
VSS
VSS
CLK
VSS
VSS
NC/18M
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
A
WE
VSS
VSS
OE
VSS
VDD
NC
VSS
VDD
NC
NC
DQPa
DQa
NC
DQb
NC
NC
DQb
DQb
DQb
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
NC
NC
DQa
DQa
DQa
ZZ
E
F
NC
NC
G
H
J
NC
NC
NC
DQb
DQb
DQb
NC
VDDQ
VDDQ
VDDQ
VDDQ
DQa
DQa
DQa
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
A
NC
K
L
NC
NC
DQb
NC
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC
A1
VSS
NC
VDD
VSS
A
DQa
NC
A
NC
NC
M
N
P
DQPb
NC/144M NC/72M
MODE NC/36M
TDI
TDO
NC/288M
A
A
TMS
A0
TCK
A
A
A
A
R
Document Number: 38-05537 Rev. *R
Page 7 of 35
CY7C1354CV25
CY7C1356CV25
Pin Definitions
Pin Name
I/O Type
Pin Description
A0, A1, A
Input-
synchronous
Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK.
BWa, BWb,
Input-
Byte write select inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
BWc, BWd synchronous the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb, BWc controls DQc
and DQPc, BWd controls DQd and DQPd.
WE
Input-
Write enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
synchronous must be asserted LOW to initiate a write sequence.
ADV/LD
Input- Advance/load input used to advance the on-chip address counter or load a new address. When
synchronous HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address
can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in
order to load a new address.
CLK
CE1
CE2
CE3
OE
Input-
clock
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
Input-
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
synchronous and CE3 to select/deselect the device.
Input-
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE3 to select/deselect the device.
Input-
Chip enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE2 to select/deselect the device.
Input-
Output enable, active LOW. Combined with the synchronous logic block inside the device to control
asynchronous the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted
HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write
sequence, during the first clock when emerging from a deselected state and when the device has been
deselected.
CEN
DQS
Input-
Clock enable input, active LOW. When asserted LOW the clock signal is recognized by the SRAM.
synchronous When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device,
CEN can be used to extend the previous cycle when required.
I/O-
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by
addresses during the previous clock rise of the read cycle. The direction of the pins is controlled by OE
and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH,
DQa–DQd are placed in a tri-state condition. The outputs are automatically tri-stated during the data
portion of a write sequence, during the first clock when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE.
DQPX
MODE
TDO
TDI
I/O-
Bidirectional data parity I/O lines. Functionally, these signals are identical to DQ[a:d]. During write
synchronous sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled by BWc, and
DQPd is controlled by BWd.
Input strap pin Mode input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled
LOW selects the linear burst order. MODE should not change states during operation. When left floating
MODE will default HIGH, to an interleaved burst order.
JTAG serial Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
output
synchronous
JTAG serial Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK.
input
synchronous
TMS
Test mode This pin controls the test access port state machine. Sampled on the rising edge of TCK.
select
synchronous
Document Number: 38-05537 Rev. *R
Page 8 of 35
CY7C1354CV25
CY7C1356CV25
Pin Definitions (continued)
Pin Name
TCK
I/O Type
Pin Description
JTAG-clock Clock input to the JTAG circuitry.
VDD
Power supply Power supply inputs to the core of the device.
VDDQ
I/O power Power supply for the I/O circuitry.
supply
VSS
NC
Ground
Ground for the device. Should be connected to ground of the system.
No connects. This pin is not connected to the die.
–
–
NC/18M,
NC/36M,
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M 288M,
576M, and 1G densities.
ZZ
Input-
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with
asynchronous data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an
internal pull-down.
requested data is allowed to propagate through the output
Functional Overview
register and onto the data bus within 2.8 ns (250-MHz device)
provided OE is active LOW. After the first clock of the read
access the output buffers are controlled by OE and the internal
control logic. OE must be driven LOW in order for the device to
drive out the requested data. During the second clock, a
subsequent operation (read/write/deselect) can be initiated.
Deselecting the device is also pipelined. Therefore, when the
SRAM is deselected at clock rise by one of the chip enable
signals, its output will tri-state following the next clock rise.
The
CY7C1354CV25/CY7C1356CV25
are
synchronous-pipelined burst NoBL SRAMs designed specifically
to eliminate wait states during write/read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with the
clock enable input signal (CEN). If CEN is HIGH, the clock signal
is not recognized and all internal states are maintained. All
synchronous operations are qualified with CEN. All data outputs
pass through output registers controlled by the rising edge of the
clock. Maximum access delay from the clock rise (tCO) is 2.8 ns
(250-MHz device).
Burst Read Accesses
The CY7C1354CV25/CY7C1356CV25 have an on-chip burst
counter that allows the user the ability to supply a single address
and conduct up to four reads without reasserting the address
inputs. ADV/LD must be driven LOW in order to load a new
address into the SRAM, as described in Single Read Accesses.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst mode,
a HIGH selects an interleaved burst sequence. Both burst
counters use A0 and A1 in the burst sequence, and will wrap
around when incremented sufficiently. A HIGH input on ADV/LD
will increment the internal burst counter regardless of the state
of chip enables inputs or WE. WE is latched at the beginning of
a burst cycle. Therefore, the type of access (read or write) is
maintained throughout the burst sequence.
Accesses can be initiated by asserting all three chip enables
(CE1, CE2, CE3) active at the rising edge of the clock. If clock
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device will be latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BW[d:a] can be used to conduct byte write
operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
should be driven LOW once the device has been deselected in
order to load a new address for the next operation.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, and (3) the write signal WE is
asserted LOW. The address presented to A0–A16 is loaded into
the address register. The write signals are latched into the
control logic block.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, (3) the write enable input signal
WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
address register and presented to the memory core and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the input
of the output register. At the rising edge of the next clock the
On the subsequent clock rise the data lines are automatically
tri-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1354CV25 and DQa,b/DQPa,b for
Document Number: 38-05537 Rev. *R
Page 9 of 35
CY7C1354CV25
CY7C1356CV25
CY7C1356CV25). In addition, the address for the subsequent
access (read/write/deselect) is latched into the address register
(provided the appropriate control signals are asserted).
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
On the next clock rise the data presented to DQ
(DQa,b,c,d/DQPa,b,c,d for CY7C1354CV25 and DQa,b/DQaPnda,bDfQoPr
CY7C1356CV25) (or a subset for byte write operations, see
Write Cycle Description table for details) inputs is latched into the
device and the Write is complete.
The data written during the write operation is controlled by BW
(BWa,b,c,d for CY7C1354CV25 and BWa,b for CY7C1356CV25)
signals. The CY7C1354CV25/CY7C1356CV25 provides byte
write capability that is described in the Write Cycle Description
table. Asserting the write enable input (WE) with the selected
byte write select (BW) input will selectively write to only the
desired bytes. Bytes not selected during a byte write operation
Interleaved Burst Address Table
(MODE = Floating or VDD
)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
will remain unaltered.
A
synchronous self-timed write
mechanism has been provided to simplify the write operations.
Byte write capability has been included in order to greatly simplify
read/modify/write sequences, which can be reduced to simple
byte write operations.
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Because the CY7C1354CV25/CY7C1356CV25 are common I/O
devices, data should not be driven into the device while the
outputs are active. The output enable (OE) can be deasserted
HIGH before presenting data to the DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1354CV25 and DQa,b/DQPa,b for
CY7C1356CV25) inputs. Doing so will tri-state the output drivers.
As a safety precaution, DQ and DQP (DQa,b,c,d/DQPa,b,c,d for
CY7C1354CV25 and DQa,b/DQPa,b for CY7C1356CV25) are
automatically tri-stated during the data portion of a write cycle,
regardless of the state of OE.
Linear Burst Address Table
(MODE = GND)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
Burst Write Accesses
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
The CY7C1354CV25/CY7C1356CV25 has an on-chip burst
counter that allows the user the ability to supply a single address
and conduct up to four write operations without reasserting the
address inputs. ADV/LD must be driven LOW in order to load the
initial address, as described in Single Write Accesses. When
ADV/LD is driven HIGH on the subsequent clock rise, the chip
enables (CE1, CE2, and CE3) and WE inputs are ignored and the
burst counter is incremented. The correct BW (BWa,b,c,d for
CY7C1354CV25 and BWa,b for CY7C1356CV25) inputs must be
driven in each cycle of the burst write in order to write the correct
bytes of data.
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
Min
Max
50
Unit
mA
ns
ZZ VDD 0.2 V
–
tZZS
ZZ VDD 0.2 V
ZZ 0.2 V
–
2tCYC
–
2tCYC
–
tZZREC
tZZI
ns
ZZ active to sleep current
This parameter is sampled
2tCYC
–
ns
tRZZI
ZZ Inactive to exit sleep current This parameter is sampled
0
ns
Document Number: 38-05537 Rev. *R
Page 10 of 35
CY7C1354CV25
CY7C1356CV25
Truth Table
The truth table for CY7C1354CV25/CY7C1356CV25 follows. [2, 3, 4, 5, 6, 7, 8]
Operation
Address used CE ZZ ADV/LD WE BWx OE CEN CLK
DQ
Deselect cycle
None
None
H
X
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
X
X
H
X
H
X
L
X
X
X
X
X
X
L
X
X
L
L
L
L
L
L
L
L
L
L
L
H
X
L–H
L–H
Tri-state
Tri-state
Continue deselect cycle
Read cycle (begin burst)
Read cycle (continue burst)
NOP/dummy read (begin burst)
Dummy read (continue burst)
Write cycle (begin burst)
Write cycle (continue burst)
NOP/write abort (begin burst)
Write abort (continue burst)
Ignore clock edge (stall)
Sleep mode
External
Next
L–H Data out (Q)
L–H Data out (Q)
X
L
H
L
L
External
Next
H
H
X
X
X
X
X
X
L–H
L–H
Tri-state
Tri-state
X
L
H
L
External
Next
L–H Data in (D)
L–H Data in (D)
X
L
H
L
X
L
L
None
H
H
X
X
L–H
L–H
L–H
X
Tri-state
Tri-state
–
Next
X
X
X
H
X
X
X
X
X
Current
None
Tri-state
Notes
2. X = “Don’t Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = Valid signifies
that the desired byte write selects are asserted, see Write Cycle Description table for details.
3. Write is defined by WE and BW . See Write Cycle Description table for details.
X
4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
5. The DQ and DQP pins are controlled by the current cycle and the OE signal.
6. CEN = H inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP = tri-state when OE is
X
inactive or when the device is deselected, and DQs = data when OE is active.
Document Number: 38-05537 Rev. *R
Page 11 of 35
CY7C1354CV25
CY7C1356CV25
Partial Truth Table for Read/Write
The partial truth table for Read/Write for CY7C1354CV25 follows. [9, 10, 11, 12]
Function (CY7C1354CV25)
BWd
X
H
H
H
H
H
H
H
H
L
BWc
X
H
H
H
H
L
BWb
X
H
H
L
BWa
X
H
L
WE
Read
H
Write– no bytes written
Write byte a–(DQa and DQPa)
Write byte b – (DQb and DQPb)
Write bytes b, a
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
Write byte c –(DQc and DQPc)
Write bytes c, a
H
H
L
H
L
L
Write bytes c, b
L
H
L
Write bytes c, b, a
L
L
Write byte d –(DQd and DQPd)
Write bytes d, a
H
H
H
H
L
H
H
L
H
L
L
Write bytes d, b
L
H
L
Write bytes d, b, a
L
L
Write bytes d, c
L
H
H
L
H
L
Write bytes d, c, a
L
L
Write bytes d, c, b
L
L
H
L
Write all bytes
L
L
L
Partial Truth Table for Read/Write
The partial truth table for Read/Write for CY7C1356CV25 follows. [9, 10, 11, 12]
Function (CY7C1356CV25)
WE
H
L
BWb
BWa
x
Read
x
H
H
L
Write – no bytes written
Write byte a (DQa and DQPa)
Write byte b – (DQb and DQPb)
Write both bytes
H
L
L
L
H
L
L
L
Notes
9. X = “Don’t Care”, H = Logic HIGH, L = Logic LOW, CE stands for all chip enables active. BWx = L signifies at least one byte write select is active, BWx = valid signifies
that the desired byte write selects are asserted, see Write Cycle Description table for details.
10. Write is defined by WE and BW . See Write Cycle Description table for details.
X
11. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
12. Table only lists a partial listing of the byte write combinations. Any combination of BW is valid. Appropriate write will be done based on which byte write is active.
X
Document Number: 38-05537 Rev. *R
Page 12 of 35
CY7C1354CV25
CY7C1356CV25
Performing a TAP Reset
IEEE 1149.1 Serial Boundary Scan (JTAG)
A RESET is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
The CY7C1354CV25/CY7C1356CV25 incorporates a serial
boundary scan test access port (TAP) in the BGA package only.
The TQFP package does not offer this functionality. This part
operates in accordance with IEEE Standard 1149.1-1900, but
doesn’t have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note the TAP controller
functions in a manner that does not conflict with the operation of
other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 2.5 V I/O logic levels.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a high Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
The CY7C1354CV25/CY7C1356CV25 contains
a
TAP
controller, instruction register, boundary scan register, bypass
register, and ID register.
Instruction Register
Disabling the JTAG Feature
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 16. Upon power-up, the instruction register is loaded with
the IDCODE instruction.
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the operation
of the device.
It is also loaded with the IDCODE instruction if the controller is
placed in a reset state as described in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
Test Access Port (TAP)
Bypass Register
Test Clock (TCK)
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
SRAM with minimal delay. The bypass register is set LOW (VSS
when the BYPASS instruction is executed.
)
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to leave
this ball unconnected if the TAP is not used.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The ball is pulled up internally, resulting in a logic HIGH level.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used to
capture the contents of the I/O ring.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see TAP Controller State
Diagram on page 15. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) of any register.
The Boundary Scan Exit Order on page 19 and Boundary Scan
Exit Order on page 20 show the order in which the bits are
connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI,
and the LSB is connected to TDO.
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current state
of the TAP state machine (see Instruction Codes on page 18).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the Identification Register Definitions on
page 18.
Document Number: 38-05537 Rev. *R
Page 13 of 35
CY7C1354CV25
CY7C1356CV25
during the Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This will not harm the device, but
there is no guarantee as to the value that will be captured.
Repeatable results may not be possible.
TAP Instruction Set
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the Instruction
Codes table. Three of these instructions are listed as
RESERVED and should not be used. The other five instructions
are described in detail below.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or slow)
the clock during a SAMPLE/PRELOAD instruction. If this is an
issue, it is still possible to capture all other signals and simply
ignore the value of the CK and CK# captured in the boundary
scan register.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO balls. To execute
the instruction once it is shifted in, the TAP controller needs to be
moved into the Update-IR state.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells prior
to the selection of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required — that is, while data captured
is shifted out, the preloaded data can be shifted in.
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
BYPASS
SAMPLE Z
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
The SAMPLE Z instruction causes the boundary scan register to
be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a high Z state until the next command is given
during the “Update IR” state.
EXTEST
SAMPLE/PRELOAD
The EXTEST instruction enables the preloaded data to be driven
out through the system output pins. This instruction also selects
the boundary scan register to be connected for serial access
between the TDI and TDO in the shift-DR controller state.
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
Reserved
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 38-05537 Rev. *R
Page 14 of 35
CY7C1354CV25
CY7C1356CV25
TAP Controller State Diagram
The TAP Controller State Diagram follows. [13]
TEST-LOGIC
1
RESET
0
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
1
1
EXIT1-DR
EXIT1-IR
0
0
PAUSE-DR
0
PAUSE-IR
0
1
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
0
1
0
Note
13. The 0/1 next to each state represents the value of TMS at the rising edge of the TCK.
Document Number: 38-05537 Rev. *R
Page 15 of 35
CY7C1354CV25
CY7C1356CV25
TAP Controller Block Diagram
0
0
Bypass Register
2
1
Selection
Circuitry
Instruction Register
31 30 29 .
S
election
TDI
TDO
Circuitr
y
.
.
2
1
0
Identification Register
x
.
.
.
.
. 2 1 0
Boundary Scan Register
TAP CONTROLLER
TCK
TMS
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
Document Number: 38-05537 Rev. *R
Page 16 of 35
CY7C1354CV25
CY7C1356CV25
TAP AC Switching Characteristics
Over the Operating Range
Parameter [14, 15]
Clock
Description
Min
Max
Unit
tTCYC
TCK clock cycle time
TCK clock frequency
TCK clock HIGH time
TCK clock LOW time
50
–
–
20
–
ns
MHz
ns
tTF
tTH
20
20
tTL
–
ns
Output Times
tTDOV
TCK clock LOW to TDO valid
TCK clock LOW to TDO invalid
–
0
10
–
ns
ns
tTDOX
Set-up Times
tTMSS
TMS set-up to TCK clock rise
TDI set-up to TCK clock rise
Capture set-up to TCK rise
5
5
5
–
–
–
ns
ns
ns
tTDIS
tCS
Hold Times
tTMSH
tTDIH
TMS hold after TCK clock rise
TDI hold after clock rise
5
5
5
–
–
–
ns
ns
ns
tCH
Capture hold after clock rise
2.5 V TAP AC Test Conditions
2.5 V TAP AC Output Load Equivalent
1.25V
Input pulse levels ...............................................VSS to 2.5 V
Input rise and fall time ....................................................1 ns
Input timing reference levels ....................................... 1.25 V
Output reference levels .............................................. 1.25 V
Test load termination supply voltage ..........................1.25 V
50Ω
TDO
ZO= 50Ω
20pF
Notes
14. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
15. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1 ns.
R
F
Document Number: 38-05537 Rev. *R
Page 17 of 35
CY7C1354CV25
CY7C1356CV25
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 2.5 V ± 0.125 V unless otherwise noted)
Parameter [16]
Description
Output HIGH voltage
Output HIGH voltage
Output LOW voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage
Input Load current
Test Conditions
IOH = –1.0 mA, VDDQ = 2.5 V
IOH = –100 µA, VDDQ = 2.5 V
IOL = 8.0 mA, VDDQ = 2.5 V
Min
2.0
2.1
–
Max
Unit
V
VOH1
VOH2
VOL1
VOL2
VIH
–
–
0.4
V
V
IOL = 100 µA
VDDQ = 2.5 V
–
0.2
V
VDDQ = 2.5 V
VDDQ = 2.5 V
1.7
–0.3
–5
VDD + 0.3
0.7
V
VIL
V
IX
GND < VIN < VDDQ
5
µA
Identification Register Definitions
Instruction Field
Revision number (31:29)
Cypress device ID (28:12)
Cypress JEDEC ID (11:1)
ID register presence (0)
CY7C1354CV25
CY7C1356CV25
000
01011001000010110 Reserved for future use.
Description
000
01011001000100110
00000110100
1
Reserved for version number.
00000110100
1
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size (× 36)
Bit Size (× 18)
Instruction
Bypass
ID
3
3
1
1
32
69
69
32
69
69
Boundary scan order (119-ball BGA package)
Boundary scan order (165-ball FBGA package)
Instruction Codes
Instruction
EXTEST
Code
Description
000
Captures the input/output ring contents. Places the boundary scan register between the TDI
and TDO. Forces all SRAM outputs to high Z state.
IDCODE
001
010
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
Captures the input/output contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a high Z state.
RESERVED
011
100
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
Captures the input/output ring contents. Places the boundary scan register between TDI and
TDO. Does not affect the SRAM operation.
RESERVED
RESERVED
BYPASS
101
110
111
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Note
16. All voltages referenced to V (GND).
SS
Document Number: 38-05537 Rev. *R
Page 18 of 35
CY7C1354CV25
CY7C1356CV25
Boundary Scan Exit Order (continued)
Boundary Scan Exit Order
(256K × 36)
(256K × 36)
Bit #
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
119-ball ID
165-ball ID
Bit #
1
119-ball ID
K4
H4
M4
F4
165-ball ID
B6
L2
K1
N2
N1
M2
L1
K2
J2
2
B7
M2
M1
L1
K1
J1
3
A7
4
B8
5
B4
G4
C3
B3
D6
H7
G6
E6
D7
E7
F6
A8
6
A9
K2
7
B10
A10
C11
E10
F10
G10
D10
D11
E11
F11
G11
H11
J10
K10
L10
M10
J11
K11
L11
M11
N11
R11
R10
P10
R9
Not Bonded (Preset to 1) Not Bonded (Preset to 1)
8
H1
G2
E2
D1
H2
G1
F2
E1
D2
C2
A2
E4
B2
L3
G2
F2
E2
D2
G1
F1
E1
D1
C1
B2
A2
A3
B3
B4
A4
A5
B5
A6
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
G7
H6
T7
K7
L6
N6
P7
N7
M6
L7
G3
G5
L5
B6
K6
P6
T4
A3
C5
B5
A5
C6
A6
P4
N4
R6
T5
P9
R8
P8
R6
P6
R4
P4
T3
R3
R2
R3
P2
P1
P3
R1
N1
L2
Document Number: 38-05537 Rev. *R
Page 19 of 35
CY7C1354CV25
CY7C1356CV25
Boundary Scan Exit Order (continued)
Boundary Scan Exit Order
(512K × 18)
(512K × 18)
Bit #
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
69
69
68
69
66
67
68
69
119-ball ID
165-ball ID
Bit #
1
119-ball ID
165-ball ID
B6
T3
R2
R3
R3
P3
R1
K4
H4
M4
F4
B4
G4
C3
B3
T2
2
B7
3
A7
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
4
B8
5
A8
6
A9
7
B10
A10
A11
P2
N1
M2
L1
N1
M1
L1
K1
J1
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
K2
Not Bonded (Preset to 1) Not Bonded (Preset to 1)
D6
E7
F6
G7
H6
T7
K7
L6
C11
D11
E11
F11
G11
H11
J10
K10
L10
M10
H1
G2
E2
D1
G2
F2
E2
D2
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
N6
P7
C2
A2
E4
B2
B2
A2
A3
B3
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
Not Bonded (Preset to 0) Not Bonded (Preset to 0)
G3
Not Bonded (Preset to 0)
T6
A3
C5
B5
A5
C6
A6
P4
N4
R6
T5
R11
R10
P10
R9
P9
Not Bonded (Preset to 0)
A4
L5
B5
B6
A6
B6
A6
B6
A6
R8
P8
L5
B5
B6
A6
R6
P6
G3
Not Bonded (Preset to 0)
Not Bonded (Preset to 0)
A4
B5
A6
R4
P4
L5
B6
Document Number: 38-05537 Rev. *R
Page 20 of 35
CY7C1354CV25
CY7C1356CV25
DC input voltage ................................. –0.5 V to VDD + 0.5 V
Current into outputs (LOW) ........................................ 20 mA
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Static discharge voltage
(per MIL-STD-883, method 3015) ......................... > 2001 V
Storage temperature ................................ –65 °C to +150 °C
Latch-up current ................................................... > 200 mA
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Operating Range
Supply voltage on VDD relative to GND .......–0.5 V to +3.6 V
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
DC to outputs in tri-state ...................–0.5 V to VDDQ + 0.5 V
Range
Commercial
Industrial
Ambient Temperature
0 °C to +70 °C
VDD/VDDQ
2.5 V ±5%
–40 °C to +85 °C
Electrical Characteristics
Over the Operating Range
Parameter [17, 18]
Description
Power supply voltage
I/O supply voltage
Test Conditions
Min
2.375
2.375
2.0
Max
Unit
VDD
VDDQ
VOH
VOL
VIH
2.625
V
V
for 2.5 V I/O
VDD
Output HIGH voltage
Output LOW voltage
Input HIGH voltage
Input LOW voltage [17]
for 2.5 V I/O, IOH = 1.0 mA
for 2.5 V I/O, IOL= 1.0 mA
for 2.5 V I/O
–
V
–
0.4
V
1.7
VDD + 0.3 V
V
VIL
for 2.5 V I/O
–0.3
–5
0.7
5
V
IX
Input leakage current except ZZ GND VI VDDQ
and MODE
A
Input current of MODE
Input = VSS
Input = VDD
Input = VSS
Input = VDD
–30
–
–
5
A
A
A
A
A
mA
Input current of ZZ
–5
–
–
30
5
IOZ
IDD
Output leakage current
VDD operating supply
GND VI VDDQ, output disabled
–5
–
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
4-ns cycle,
250 MHz
250
5-ns cycle,
200 MHz
–
–
–
–
–
–
220
180
130
120
110
40
mA
mA
mA
mA
mA
mA
6-ns cycle,
166 MHz
ISB1
Automatic CE power-down
current — TTL inputs
Max VDD, device deselected,
VIN VIH or VIN VIL,
f = fMAX = 1/tCYC
4-ns cycle,
250 MHz
5-ns cycle,
200 MHz
6-ns cycle,
166 MHz
ISB2
Automatic CE power-down
current — CMOS inputs
Max VDD, device deselected,
VIN 0.3 V or VIN > VDDQ 0.3 V, grades
f = 0
All speed
Notes
17. Overshoot: V
< V + 1.5 V (Pulse width less than t
/2), undershoot: V
> –2 V (Pulse width less than t
/2).
IH(AC)
DD
CYC
IL(AC)
CYC
18. T
: Assumes a linear ramp from 0 V to V
within 200 ms. During this time V < V and V
V
.
Power-up
(min)
IH
DD
DDQ
DD
DD
Document Number: 38-05537 Rev. *R
Page 21 of 35
CY7C1354CV25
CY7C1356CV25
Electrical Characteristics (continued)
Over the Operating Range
Parameter [17, 18]
Description
Test Conditions
Min
Max
Unit
ISB3
Automatic CE power-down
current — CMOS inputs
Max VDD, device deselected,
VIN 0.3 V or VIN > VDDQ 0.3 V, 250 MHz
f = fMAX = 1/tCYC
4-ns cycle,
–
120
mA
5-ns cycle,
200 MHz
–
–
–
110
100
40
mA
mA
mA
6-ns cycle,
166 MHz
ISB4
Automatic CE power-down
current — TTL inputs
Max VDD, device deselected,
VIN VIH or VIN VIL, f = 0
All speed
grades
Capacitance
100-pin TQFP 119-ball BGA 165-ballFBGA
Parameter [19]
Description
Test Conditions
Unit
Max
Max
Max
CIN
Input capacitance
TA = 25 °C, f = 1 MHz,
VDD = 2.5 V, VDDQ = 2.5 V
5
5
5
5
5
7
5
5
7
pF
pF
pF
CCLK
CI/O
Clock input capacitance
Input/output capacitance
Thermal Resistance
100-pin TQFP 119-ball BGA 165-ballFBGA
Parameter [19]
Description
Test Conditions
Unit
Package
Package
Package
JA
Thermal resistance
(junction to ambient)
Test
conditions
follow
29.41
34.1
16.8
°C/W
standard test methods and
procedures for measuring
thermal impedance, per
EIA/JESD51.
JC
Thermal resistance
(junction to case)
6.13
14
3.0
°C/W
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms
2.5 V I/O Test Load
R = 1667
2.5 V
OUTPUT
OUTPUT
ALL INPUT PULSES
90%
VDDQ
90%
10%
Z = 50
0
R = 50
10%
L
GND
5 pF
INCLUDING
R = 1538
1 ns
1 ns
VT = 1.25 V
(a)
JIG AND
SCOPE
(b)
(c)
Note
19. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05537 Rev. *R
Page 22 of 35
CY7C1354CV25
CY7C1356CV25
Switching Characteristics
Over the Operating Range
-250
-200
-166
Unit
Parameter [20, 21]
Description
Min
Max
Min
Max
Min
Max
[22]
tPower
VCC(typical)tothefirstaccessreador
write
1
–
1
–
1
–
ms
Clock
tCYC
Clock cycle time
Maximum operating frequency
Clock HIGH
4.0
–
–
250
–
5
–
–
200
–
6
–
–
166
–
ns
MHz
ns
FMAX
tCH
1.8
1.8
2.0
2.0
2.4
2.4
tCL
Clock LOW
–
–
–
ns
Output Times
tCO
Data output valid after CLK rise
OE LOW to output valid
–
–
2.8
2.8
–
–
–
3.2
3.2
–
–
–
3.5
3.5
–
ns
ns
ns
ns
ns
ns
ns
tEOV
tDOH
Data output hold after CLK rise
Clock to high Z [23, 24, 25]
Clock to low Z [23, 24, 25]
OE HIGH to output high Z [23, 24, 25]
OE LOW to output low Z [23, 24, 25]
1.25
1.25
1.25
–
1.5
1.5
1.5
–
1.5
1.5
1.5
–
tCHZ
2.8
–
3.2
–
3.5
–
tCLZ
tEOHZ
tEOLZ
Set-up Times
tAS
2.8
–
3.2
–
3.5
–
0
0
0
Address set-up before CLK rise
Data input set-up before CLK rise
CEN set-up before CLK rise
WE, BWx set-up before CLK rise
ADV/LD set-up before CLK rise
Chip select set-up
1.4
1.4
1.4
1.4
1.4
1.4
–
–
–
–
–
–
1.5
1.5
1.5
1.5
1.5
1.5
–
–
–
–
–
–
1.5
1.5
1.5
1.5
1.5
1.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tDS
tCENS
tWES
tALS
tCES
Hold Times
tAH
Address hold after CLK rise
Data input hold after CLK rise
CEN hold after CLK rise
0.4
0.4
0.4
0.4
0.4
0.4
–
–
–
–
–
–
0.5
0.5
0.5
0.5
0.5
0.5
–
–
–
–
–
–
0.5
0.5
0.5
0.5
0.5
0.5
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
tDH
tCENH
tWEH
WE, BWx hold after CLK rise
ADV/LD hold after CLK rise
Chip select hold after CLK rise
tALH
tCEH
Notes
20. Timing reference level is when V
= 2.5 V.
DDQ
21. Test conditions shown in (a) of Figure 4 on page 22 unless otherwise noted.
22. This part has a voltage regulator internally; t is the time power needs to be supplied above V minimum initially, before a Read or Write operation can be initiated.
power
DD
23. t
, t
, t
, and t
are specified with AC test conditions shown in (b) of Figure 4 on page 22. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ EOLZ
EOHZ
24. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same data
CLZ
EOHZ
EOLZ
CHZ
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high Z prior to low Z under the same system conditions.
25. This parameter is sampled and not 100% tested.
Document Number: 38-05537 Rev. *R
Page 23 of 35
CY7C1354CV25
CY7C1356CV25
Switching Waveforms
Figure 5. Read/Write Timing [26, 27, 28]
1
2
3
4
5
6
7
8
9
10
t
CYC
t
CLK
t
t
t
CENS CENH
CL
CH
CEN
t
t
CES
CEH
CE
ADV/LD
WE
BW
X
A1
A2
A4
CO
A3
A5
A6
A7
ADDRESS
t
t
t
t
DS
DH
t
t
t
DOH
OEV
CLZ
CHZ
t
t
AS
AH
Data
D(A1)
D(A2)
D(A2+1)
Q(A3)
Q(A4)
Q(A4+1)
D(A5)
Q(A6)
In-Out (DQ)
t
OEHZ
t
DOH
t
OELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
READ
Q(A3)
READ
Q(A4)
BURST
READ
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
D(A2+1)
Q(A4+1)
DON’T CARE
UNDEFINED
Notes
26. For this waveform ZZ is tied LOW.
27. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
28. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document Number: 38-05537 Rev. *R
Page 24 of 35
CY7C1354CV25
CY7C1356CV25
Switching Waveforms (continued)
Figure 6. NOP, STALL and DESELECT CYCLES [29, 30, 31]
1
2
3
4
5
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BW
X
A1
A2
A3
A4
A5
ADDRESS
t
CHZ
D(A4)
D(A1)
Q(A2)
Q(A3)
Q(A5)
Data
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
Notes
29. For this waveform ZZ is tied LOW.
30. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH, CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
31. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
Document Number: 38-05537 Rev. *R
Page 25 of 35
CY7C1354CV25
CY7C1356CV25
Switching Waveforms (continued)
Figure 7. ZZ Mode Timing [32, 33]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
Notes
32. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
33. I/Os are in high Z when exiting ZZ sleep mode.
Document Number: 38-05537 Rev. *R
Page 26 of 35
CY7C1354CV25
CY7C1356CV25
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The below table contains only the
list of parts that are currently available.For a complete listing of all options, visit the Cypress website at www.cypress.com and refer
to the product summary page at http://www.cypress.com/products or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
Package
Diagram
Operating
Range
Part and Package Type
Ordering Code
166 CY7C1354CV25-166AXC
CY7C1356CV25-166AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
CY7C1354CV25-166BZC
51-85180 165-ball FBGA (13 × 15 × 1.4 mm)
200 CY7C1354CV25-200AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
Ordering Code Definitions
CY
7
C
135X
C
V25 - XXX XX X
C
Temperature Range: C = Commercial
Pb-free
Package Type: XX = A or BZ
A = 100-pin TQFP
BZ = 165-ball FBGA
Speed Grade: XXX = 166 MHz or 200 MHz
V25 = 2.5 V
Process Technology 90 nm
135X = 1354 or 1356
1354 = PL, 256Kb × 36 (9Mb)
1356 = PL, 512Kb × 18 (9Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05537 Rev. *R
Page 27 of 35
CY7C1354CV25
CY7C1356CV25
Package Diagrams
Figure 8. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
ș 2
ș
1
ș
DIMENSIONS
MIN. NOM. MAX.
1.60
NOTE:
SYMBOL
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. BODY LENGTH DIMENSION DOES NOT
INCLUDE MOLD PROTRUSION/END FLASH.
MOLD PROTRUSION/END FLASH SHALL
A
0.05
0.15
A1
A2
D
1.35 1.40 1.45
15.80 16.00 16.20
13.90 14.00 14.10
21.80 22.00 22.20
19.90 20.00 20.10
NOT EXCEED 0.0098 in (0.25 mm) PER SIDE.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC
D1
E
E1
BODY SIZE INCLUDING MOLD MISMATCH.
3. JEDEC SPECIFICATION NO. REF: MS-026.
0.08
0.08
0°
R
R
ș
0.20
0.20
7°
1
2
ș 1
ș 2
c
0°
11° 12° 13°
0.20
0.22 0.30 0.38
0.45 0.60 0.75
1.00 REF
b
L
L1
L 2
L 3
e
0.25 BSC
0.20
0.65 TYP
51-85050 *G
Document Number: 38-05537 Rev. *R
Page 28 of 35
CY7C1354CV25
CY7C1356CV25
Package Diagrams (continued)
Figure 9. 119-ball PBGA (14 × 22 × 2.4 mm) BG119 Package Outline, 51-85115
51-85115 *D
Document Number: 38-05537 Rev. *R
Page 29 of 35
CY7C1354CV25
CY7C1356CV25
Package Diagrams (continued)
Figure 10. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180
51-85180 *G
Document Number: 38-05537 Rev. *R
Page 30 of 35
CY7C1354CV25
CY7C1356CV25
Acronyms
Document Conventions
Units of Measure
Acronym
Description
BGA
CE
Ball Grid Array
Symbol
°C
Unit of Measure
Chip Enable
Clock Enable
degree Celsius
megahertz
microampere
milliampere
millimeter
millisecond
millivolt
MHz
µA
mA
mm
ms
mV
ns
CEN
CMOS
EIA
Complementary Metal Oxide Semiconductor
Electronic Industries Alliance
Fine-Pitch Ball Grid Array
Input/Output
FBGA
I/O
JEDEC
JTAG
LSB
Joint Electron Devices Engineering Council
Joint Test Action Group
Least Significant Bit
Most Significant Bit
nanosecond
ohm
%
percent
MSB
NoBL
OE
pF
V
picofarad
volt
No Bus Latency
Output Enable
W
watt
SRAM
TAP
Static Random Access Memory
Test Access Port
TCK
TDI
Test Clock
Test Data-In
TDO
TMS
TQFP
TTL
Test Data-Out
Test mode select
Thin Quad Flat Pack
Transistor-Transistor Logic
Write Enable
WE
Document Number: 38-05537 Rev. *R
Page 31 of 35
CY7C1354CV25
CY7C1356CV25
Document History Page
Document Title: CY7C1354CV25/CY7C1356CV25, 9-Mbit (256K × 36/512K × 18) Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05537
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
**
242032
278969
RKF
RKF
07/13/2004 New data sheet.
*A
10/18/2004 Updated Boundary Scan Exit Order (To match the B Rev of these devices).
Updated Boundary Scan Exit Order (To match the B Rev of these devices).
*B
*C
284929
323636
RKF / VBL 11/01/2004 Updated Functional Overview:
Updated ZZ Mode Electrical Characteristics:
Changed maximum value of IDDZZ parameter from 35 mA to 50 mA.
Added Electrical Characteristics.
Updated Ordering Information:
Updated part numbers.
PCI
02/22/2005 Replaced “225 MHz” with “250 MHz” in all instances across the document.
Updated Pin Definitions:
Modified address expansion as per JEDEC Standard in all instances across
the document.
Updated Thermal Resistance:
Changed value of JA parameter corresponding to 100-pin TQFP Package
from 25 °C/W to 29.41 °C/W.
Changed value of JC parameter corresponding to 100-pin TQFP Package
from 9 °C/W to 6.13 °C/W.
Changed value of JA parameter corresponding to 119-ball BGA Packagefrom
25 °C/W to 34.1 °C/W.
Changed value of JC parameter corresponding to 119-ball BGA Packagefrom
6 °C/W to 14.0 °C/W.
Changed value of JA parameter corresponding to 165-ball FBGA Package
from 27 °C/W to 16.8 °C/W.
Changed value of JC parameter corresponding to 165-ball FBGA Package
from 6 °C/W to 3.0 °C/W.
Updated Switching Characteristics:
Changedminimumvalue of tCYC parameter from4.4 ns to4.0nscorresponding
to 250 MHz frequency.
Updated Ordering Information:
No change in part numbers.
Removed comment “Lead-free BGX package will be available in 2005.” below
the table.
*D
332879
PCI
03/13/2005 Updated Selection Guide:
Unshaded 200 MHz and 166 MHz speed bins related information.
Updated Pin Definitions:
Added Address Expansion pins.
Updated IEEE 1149.1 Serial Boundary Scan (JTAG):
Updated TAP Instruction Set:
Removed “EXTEST OUTPUT BUS TRI-STATE”.
Updated Electrical Characteristics:
Unshaded 200 MHz and 166 MHz speed bins related information.
Updated details in “Test Conditions” column corresponding to VOL and VOH
parameters.
Updated Switching Characteristics:
Unshaded 200 MHz and 166 MHz speed bins related information.
Updated Ordering Information:
Updated part numbers.
Document Number: 38-05537 Rev. *R
Page 32 of 35
CY7C1354CV25
CY7C1356CV25
Document History Page (continued)
Document Title: CY7C1354CV25/CY7C1356CV25, 9-Mbit (256K × 36/512K × 18) Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05537
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
*E
357258
PCI
05/05/2005 Changed status from Preliminary to Final.
Updated Selection Guide:
Unshaded 250 MHz speed bin related information.
Updated Electrical Characteristics:
Changed maximum value of ISB2 parameter from 35 mA to 40 mA.
Unshaded 250 MHz speed bin related information.
Updated Switching Characteristics:
Unshaded 250 MHz speed bin related information.
Updated Ordering Information:
Updated part numbers.
*F
377095
408298
PCI
06/10/2005 Updated Electrical Characteristics:
Updated Note 18 (Replaced “VDDQ < VDD” with “VDDQ VDD”).
*G
RXU
11/16/2005 Changed address of Cypress Semiconductor Corporation in page 1 from “3901
North First Street” to “198 Champion Court”.
Replaced “three-state” with “tri-state” in all instances across the document.
Updated Electrical Characteristics:
Replaced “Input Load” with “Input Leakage Current except ZZ and MODE” in
“Description” column corresponding to IX parameter.
Updated Ordering Information:
Updated part numbers.
Removed “Package Name” column.
Added “Package Diagram” column.
*H
501793
VKN
09/13/2006 Updated Switching Characteristics:
Changed minimum value of tTH, and tTL parameters from 25 ns to 20 ns.
Changed maximum value of tTDOV parameter from 5 ns to 10 ns.
Updated Maximum Ratings:
Added “Supply Voltage on VDDQ Relative to GND” and its rating.
Updated Ordering Information:
Updated part numbers.
*I
2898958
3033272
NJY
NJY
03/25/2010 Updated Ordering Information:
Updated part numbers.
Updated Package Diagrams:
spec 51-85050 – Changed revision from *B to *C.
spec 51-85115 – Changed revision from *B to *C.
spec 51-85180 – Changed revision from *A to *C.
*J
09/19/2010 Updated Ordering Information:
No change in part numbers.
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Minor edits.
Updated to new template.
Completing Sunset Review.
*K
*L
3052726
3385314
NJY
10/08/2010 Updated Ordering Information:
Updated part numbers.
PRIT
09/29/2011 Updated Package Diagrams:
spec 51-85050 – Changed revision from *C to *D.
Completing Sunset Review.
*M
3754566
PRIT
09/25/2012 Updated Package Diagrams (spec 51-85115 (Changed revision from *C to *D),
spec 51-85180 (Changed revision from *C to *F)).
Completing Sunset Review.
Document Number: 38-05537 Rev. *R
Page 33 of 35
CY7C1354CV25
CY7C1356CV25
Document History Page (continued)
Document Title: CY7C1354CV25/CY7C1356CV25, 9-Mbit (256K × 36/512K × 18) Pipelined SRAM with NoBL™ Architecture
Document Number: 38-05537
Orig. of
Change
Submission
Date
Rev.
ECN No.
Description of Change
*N
4537527
PRIT
10/14/2014 Updated Package Diagrams:
spec 51-85050 – Changed revision from *D to *E.
Updated to new template.
Completing Sunset Review.
*O
*P
4571917
4974141
PRIT
PRIT
11/18/2014 Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
10/19/2015 Updated Package Diagrams:
spec 51-85180 – Changed revision from *F to *G.
Updated to new template.
Completing Sunset Review.
*Q
*R
5509821
6021076
PRIT
11/04/2016 Updated Package Diagrams:
spec 51-85050 – Changed revision from *E to *F.
Updated to new template.
Completing Sunset Review.
RMES
01/09/2018 Updated Package Diagrams:
spec 51-85050 – Changed revision from *F to *G.
Updated to new template.
Completing Sunset Review.
Document Number: 38-05537 Rev. *R
Page 34 of 35
CY7C1354CV25
CY7C1356CV25
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
®
Products
PSoC Solutions
Arm® Cortex® Microcontrollers
cypress.com/arm
cypress.com/automotive
cypress.com/clocks
cypress.com/interface
cypress.com/iot
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
Automotive
Cypress Developer Community
Clocks & Buffers
Interface
Community | Projects | Video | Blogs | Training | Components
Technical Support
Internet of Things
Memory
cypress.com/support
cypress.com/memory
cypress.com/mcu
Microcontrollers
PSoC
cypress.com/psoc
Power Management ICs
Touch Sensing
USB Controllers
Wireless Connectivity
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2004-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-05537 Rev. *R
Revised January 9, 2018
Page 35 of 35
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc.
相关型号：
CY7C1354CV25-167BGXC
9-Mbit ( 256K x 36/512K x 18 ) Pipelined SRAM with NoBL-TM Architecture
CYPRESS
CY7C1354CV25-167BGXI
9-Mbit ( 256K x 36/512K x 18 ) Pipelined SRAM with NoBL-TM Architecture
CYPRESS
CY7C1354CV25-167BZXC
9-Mbit ( 256K x 36/512K x 18 ) Pipelined SRAM with NoBL-TM Architecture
CYPRESS
©2020 ICPDF网 联系我们和版权申明