CY7C1354CV25-167AXC [CYPRESS]
9-Mbit ( 256K x 36/512K x 18 ) Pipelined SRAM with NoBL-TM Architecture; 9兆位（ 256K ×36 / 512K ×18 ）流水线SRAM与NOBL -TM架构
| 型号： | CY7C1354CV25-167AXC |
| 厂家： | 
CYPRESS |
| 描述： | 9-Mbit ( 256K x 36/512K x 18 ) Pipelined SRAM with NoBL-TM Architecture |
| 文件： | 总25页 (文件大小：338K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1354CV25
CY7C1356CV25
PRELIMINARY
9-Mbit (256K x 36/512K x 18) Pipelined SRAM
with NoBL™ Architecture
Features
Functional Description
• Pin-compatible with and functionally equivalent to
ZBT™
The CY7C1354CV25 and CY7C1356CV25 are 2.5V, 256K x
36 and 512K x 18 Synchronous pipelined burst SRAMs with
No Bus Latency™ (NoBL™) logic, respectively. They are
designed to support unlimited true back-to-back Read/Write
operations with no wait states. The CY7C1354CV25 and
CY7C1356CV25 are equipped with the advanced (NoBL) logic
required to enable consecutive Read/Write operations with
data being transferred on every clock cycle. This feature
dramatically improves the throughput of data in systems that
require frequent Write/Read transitions. The CY7C1354CV25
and CY7C1356CV25 are pin-compatible with and functionally
equivalent to ZBT devices.
• Supports 225-MHz bus operations with zero wait states
— Available speed grades are 225, 200, and 167 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• Single 2.5V power supply
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle.
• Fast clock-to-output times
— 2.8 ns (for 225-MHz device)
— 3.2ns (for 200-MHz device)
— 3.5 ns (for 167-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
Write operations are controlled by the Byte Write Selects
(BWa–BWd for CY7C1354CV25 and BWa–BWb for
CY7C1356CV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
• Available in lead-free 100 TQFP, 119 BGA, and 165 fBGA
packages
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
• IEEE 1149.1 JTAG Boundary Scan
• Burst capability–linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
Logic Block Diagram–CY7C1354CV25 (256K x 36)
ADDRESS
REGISTER 0
A0, A1, A
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
C
ADV/LD
C
CLK
CEN
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
O
O
S
U
D
A
T
U
T
P
T
P
E
N
S
U
T
U
T
ADV/LD
A
E
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
R
E
G
I
MEMORY
ARRAY
B
U
F
S
T
E
E
R
I
DQs
DQP
DQP
DQP
DQP
WRITE
DRIVERS
BW
BW
a
a
b
c
d
A
M
P
b
BW
BW
c
S
T
E
R
S
F
d
E
R
S
S
WE
E
E
N
G
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
READ LOGIC
CE1
CE2
CE3
SLEEP
CONTROL
ZZ
Cypress Semiconductor Corporation
Document #: 38-05537 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised November 1, 2004
CY7C1354CV25
CY7C1356CV25
PRELIMINARY
Logic Block Diagram–CY7C1356CV25 (512K x 18)
ADDRESS
REGISTER 0
A0, A1, A
A1
A0
A1'
A0'
D1
D0
Q1
Q0
BURST
LOGIC
MODE
C
ADV/LD
C
CLK
CEN
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
O
U
T
P
O
U
T
P
S
E
N
S
D
A
T
U
T
U
T
ADV/LD
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
A
R
E
G
I
MEMORY
ARRAY
E
B
U
F
DQs
DQP
DQP
WRITE
DRIVERS
BW
BW
a
S
T
E
E
R
I
A
M
P
a
F
b
S
T
E
R
S
b
E
R
S
S
N
G
WE
E
E
INPUT
REGISTER 1
INPUT
REGISTER 0
E
E
OE
READ LOGIC
CE1
CE2
CE3
Sleep
Control
ZZ
Selection Guide
CY7C1354CV25-225
CY7C1356CV25-225
CY7C1354CV25-200
CY7C1356CV25-200
CY7C1354CV25-167
CY7C1356CV25-167
Unit
ns
Maximum Access Time
2.8
250
35
3.2
220
35
3.5
180
35
Maximum Operating Current
Maximum CMOS Standby Current
mA
mA
Shaded areas contain advance information.Please contact your local Cypress sales representative for availability of these parts.
Note:
1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Document #: 38-05537 Rev. *B
Page 2 of 25
CY7C1354CV25
CY7C1356CV25
PRELIMINARY
Pin Configurations
100-pin TQFP Packages
DQPc
DQc
DQc
1
2
3
4
5
6
7
8
NC
NC
NC
DDQ
1
2
3
4
5
6
7
8
A
NC
NC
78
DQPb
DQb
DQb
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
80
79
V
V
DDQ
VDDQ
VSS
V
V
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DDQ
SS
V
V
SS
SS
DQc
DQc
NC
NC
DQb
NC
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
DQPa
DQa
DQa
DQc
DQc
9
DQb
9
V
V
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
V
V
DDQ
DDQ
V
DQa
DQa
DDQ
DQc
DQc
NC
DQb
DQb
NC
V
CY7C1354CV25
(256K × 36)
SS
V
V
DD
DD
NC
CY7C1356CV25
(512K × 18)
NC
VDD
ZZ
DQa
DQa
NC
V
DD
V
V
SS
SS
ZZ
DQd
DQb
DQb
DQa
DQa
DQd
V
V
DDQ
DDQ
VDDQ
VSS
DQa
DQa
V
DDQ
V
V
SS
SS
V
SS
DQd
DQd
DQd
DQd
DQb
DQb
DQa DQPb
DQa
DQa
NC
DQa
VSS
VDDQ
DQa
DQa
DQPa
NC
NC
V
SS
V
V
SS
SS
V
V
DDQ
DQd
DDQ
V
DDQ
NC
NC
NC
NC
NC
NC
DQd
DQPd
Document #: 38-05537 Rev. *B
Page 3 of 25
CY7C1354CV25
CY7C1356CV25
PRELIMINARY
Pin Configurations (continued)
119-ball BGA Pinout
CY7C1354CV25 (256K × 36) – 14 × 22 BGA
1
2
3
4
5
6
7
VDDQ
A
A
E(18)
A
A
VDDQ
A
NC
NC
CE2
A
A
A
ADV/LD
VDD
A
A
CE3
A
NC
NC
B
C
D
DQc
DQPc
VSS
NC
VSS
DQPb
DQb
DQc
VDDQ
DQc
DQc
DQc
DQc
DQc
VDD
VSS
VSS
CE1
VSS
VSS
DQb
DQb
DQb
DQb
VDD
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
E
F
OE
A
G
H
J
BWc
VSS
NC
BWb
VSS
NC
DQc
WE
VDD
VDDQ
DQd
DQd
VDDQ
DQd
DQd
DQd
DQd
DQd
DQd
DQPd
VSS
BWd
VSS
CLK
NC
VSS
BWa
VSS
VSS
VSS
DQa
DQa
DQa
DQa
DQPa
K
L
M
N
P
CEN
A1
VSS
VSS
MODE
A
A0
NC
NC
A
VDD
A
A
NC
ZZ
R
T
NC
A
E(72)
TMS
E(36)
NC
VDDQ
TDI
TCK
TDO
VDDQ
U
CY7C1356CV25 (512K x 18)–14 x 22 BGA
1
2
3
4
5
6
7
VDDQ
A
A
E(18)
A
A
VDDQ
A
B
C
D
E
F
NC
NC
CE2
A
A
A
NC
NC
CE3
A
ADV/LD
VDD
A
A
DQb
NC
NC
DQb
NC
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQPa
NC
NC
DQa
VDDQ
CE1
VDDQ
DQa
OE
A
NC
DQb
VDDQ
DQb
NC
VDD
VSS
VSS
NC
NC
DQa
VDD
DQa
NC
VDDQ
G
H
J
BWb
VSS
NC
WE
VDD
NC
DQb
VDDQ
DQb
NC
DQb
NC
VSS
VSS
VSS
VSS
VSS
MODE
A
CLK
NC
VSS
NC
DQa
NC
DQa
NC
A
DQa
NC
K
L
BWa
VSS
DQb
NC
VDDQ
NC
M
N
P
R
T
CEN
A1
VSS
VSS
NC
A
DQPb
A
A0
DQa
NC
NC
VDD
E(36)
TCK
E(72)
VDDQ
A
A
ZZ
TMS
TDI
TDO
NC
VDDQ
U
Document #: 38-05537 Rev. *B
Page 4 of 25
CY7C1354CV25
CY7C1356CV25
PRELIMINARY
Pin Configurations (continued)
165-Ball fBGA Pinout
CY7C1354CV25 (256K × 36) – 13 × 15 fBGA
1
2
A
3
4
5
6
7
8
9
A
10
A
11
NC
E(288)
ADV/LD
A
B
C
D
CE1
BWc
BWd
VSS
VDD
BWb
BWa
VSS
VSS
CE3
CLK
VSS
VSS
CEN
WE
NC
A
CE2
VDDQ
VDDQ
OE
VSS
VDD
E(18)
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
E(144)
DQPb
DQb
A
DQPc
DQc
NC
DQc
VSS
VSS
NC
DQb
DQc
DQc
DQc
NC
DQc
DQc
DQc
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
DQb
DQb
DQb
NC
DQb
DQb
DQb
ZZ
E
F
G
H
J
NC
DQd
DQd
DQd
DQd
DQd
DQd
VDDQ
VDDQ
VDDQ
VDDQ
DQa
DQa
DQa
DQa
DQa
DQa
VDDQ
VDDQ
VDDQ
VDDQ
A
K
L
DQd
DQPd
NC
DQd
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC
A1
VSS
NC
VDD
VSS
A
DQa
NC
A
DQa
DQPa
NC
M
N
P
E(72)
TDI
TDO
MODE
E(36)
A
A
TMS
A0
TCK
A
A
A
A
R
CY7C1356CV25 (512K × 18) – 13 × 15 fBGA
1
E(288)
NC
2
A
A
3
4
5
NC
6
CE3
7
8
9
A
10
A
11
A
A
B
C
D
CE1
BWb
NC
CEN
ADV/LD
CE2
VDDQ
VDDQ
BWa
VSS
VSS
CLK
VSS
VSS
E(18)
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
E(144)
DQPa
DQa
WE
VSS
VSS
OE
VSS
VDD
A
NC
NC
VSS
VDD
NC
NC
DQb
NC
NC
NC
DQb
DQb
DQb
NC
VDDQ
VDDQ
VDDQ
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
NC
NC
DQa
DQa
DQa
ZZ
E
F
NC
NC
G
H
J
NC
NC
NC
DQb
DQb
DQb
NC
VDDQ
VDDQ
VDDQ
VDDQ
DQa
DQa
DQa
NC
NC
VDDQ
VDDQ
VDDQ
VDDQ
A
NC
K
L
NC
NC
DQb
DQPb
NC
NC
NC
VDDQ
VDDQ
A
VDD
VSS
A
VSS
NC
VSS
NC
A1
VSS
NC
VDD
VSS
A
DQa
NC
A
NC
NC
NC
M
N
P
E(72)
TDI
TDO
MODE
E(36)
A
A
TMS
A0
TCK
A
A
A
A
R
Document #: 38-05537 Rev. *B
Page 5 of 25
CY7C1354CV25
CY7C1356CV25
PRELIMINARY
Pin Definitions
Pin Name
I/O Type
Pin Description
A0
A1
A
Input-
Synchronous
Address Inputs used to select one of the address locations. Sampled at the rising edge of
the CLK.
BWa,
BWb,
BWc,
BWd,
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BWa controls DQa and DQPa, BWb controls DQb and DQPb,
BWc controls DQc and DQPc, BWd controls DQd and DQPd.
Input-
Synchronous
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
WE
Input-
Synchronous
Advance/Load Input used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD should
be driven LOW in order to load a new address.
ADV/LD
CLK
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select/deselect the device.
CE1
CE2
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous
CE1 and CE3 to select/deselect the device.
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device.
CE3
OE
Input-
Output Enable, active LOW. Combined with the synchronous logic block inside the device to
Asynchronous control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs.
When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked
during the data portion of a Write sequence, during the first clock when emerging from a
deselected state and when the device has been deselected.
Input-
Synchronous
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the
SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
CEN
DQS
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by addresses during the previous clock rise of the Read cycle. The direction of the pins
is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave
as outputs. When HIGH, DQa–DQd are placed in a three-state condition. The outputs are
automatically three-stated during the data portion of a write sequence, during the first clock when
emerging from a deselected state, and when the device is deselected, regardless of the state of
OE.
DQPX
I/O-
Synchronous
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[a:d]. During
write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc is controlled
by BWc, and DQPd is controlled by BWd.
MODE
Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Pulled LOW selects the linear burst order. MODE should not change states during operation.
When left floating MODE will default HIGH, to an interleaved burst order.
TDO
TDI
JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.
Synchronous
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.
Synchronous
TMS
Test Mode Select This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
Synchronous
TCK
VDD
VDDQ
VSS
JTAG-Clock
Clock input to the JTAG circuitry.
Power Supply Power supply inputs to the core of the device.
I/O Power Supply Power supply for the I/O circuitry.
Ground
Ground for the device. Should be connected to ground of the system.
Document #: 38-05537 Rev. *B
Page 6 of 25
CY7C1354CV25
CY7C1356CV25
PRELIMINARY
Pin Definitions (continued)
Pin Name
I/O Type
Pin Description
No connects. This pin is not connected to the die.
NC
–
–
E(18,36,
72, 144,
288)
These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M
and 288M densities.
ZZ
Input-
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
Asynchronous with data integrity preserved. During normal operation, this pin can be connected to VSS or left floating.
Burst Read Accesses
Functional Overview
The CY7C1354CV25 and CY7C1356CV25 have an on-chip
burst counter that allows the user the ability to supply a single
address and conduct up to four Reads without reasserting the
address inputs. ADV/LD must be driven LOW in order to load
a new address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and will wrap around when incremented suffi-
ciently. A HIGH input on ADV/LD will increment the internal
burst counter regardless of the state of chip enables inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.
The
CY7C1354CV25
and
CY7C1356CV25
are
synchronous-pipelined Burst NoBL SRAMs designed specifi-
cally to eliminate wait states during Write/Read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with
the Clock Enable input signal (CEN). If CEN is HIGH, the clock
signal is not recognized and all internal states are maintained.
All synchronous operations are qualified with CEN. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise
(tCO) is 2.8 ns (225-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a Read or Write operation, depending on
the status of the Write Enable (WE). BW[d:a] can be used to
conduct Byte Write operations.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the Write signal WE
is asserted LOW. The address presented to A0∠A16 is loaded
into the Address Register. The write signals are latched into
the Control Logic block.
Write operations are qualified by the Write Enable (WE). All
Writes are simplified with on-chip synchronous self-timed
Write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1354CV25 and DQa,b/DQPa,b
for CY7C1356CV25). In addition, the address for the subse-
quent access (Read/Write/Deselect) is latched into the
address register (provided the appropriate control signals are
asserted).
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the address register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus within 2.8 ns
(225-MHz device) provided OE is active LOW. After the first
clock of the read access the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. During the
second clock, a subsequent operation (Read/Write/Deselect)
can be initiated. Deselecting the device is also pipelined.
Therefore, when the SRAM is deselected at clock rise by one
of the chip enable signals, its output will three-state following
the next clock rise.
On the next clock rise the data presented to DQ
and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1354CV25 and DQa,b/DQPa,b
for CY7C1356CV25) (or a subset for byte write operations,
see Write Cycle Description table for details) inputs is latched
into the device and the Write is complete.
The data written during the Write operation is controlled by BW
(BWa,b,c,d
for
CY7C1354CV25
and
BWa,b
for
CY7C1356CV25) signals. The CY7C1354CV25/56CV25
provides Byte Write capability that is described in the Write
Cycle Description table. Asserting the Write Enable input (WE)
with the selected Byte Write Select (BW) input will selectively
write to only the desired bytes. Bytes not selected during a
Byte Write operation will remain unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
Write operations. Byte Write capability has been included in
order to greatly simplify Read/Modify/Write sequences, which
can be reduced to simple Byte Write operations.
Because the CY7C1354CV25 and CY7C1356CV25 are
common I/O devices, data should not be driven into the device
while the outputs are active. The Output Enable (OE) can be
Document #: 38-05537 Rev. *B
Page 7 of 25
CY7C1354CV25
CY7C1356CV25
PRELIMINARY
deasserted HIGH before presenting data to the DQ and DQP
(DQa,b,c,d/DQPa,b,c,d for CY7C1354CV25 and DQa,b/DQPa,b
for CY7C1356CV25) inputs. Doing so will three-state the
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive for
the duration of tZZREC after the ZZ input returns LOW.
output drivers. As a safety precaution, DQ and DQP (DQa,b,c,d
/
DQPa,b,c,d for CY7C1354CV25 and DQa,b/DQPa,b for
CY7C1356CV25) are automatically three-stated during the
data portion of a write cycle, regardless of the state of OE.
Interleaved Burst Address Table
(MODE = Floating or VDD
)
First
Address
Second
Address
Third
Address
Fourth
Address
Burst Write Accesses
The CY7C1354CV25/56CV25 has an on-chip burst counter
that allows the user the ability to supply a single address and
conduct up to four WRITE operations without reasserting the
address inputs. ADV/LD must be driven LOW in order to load
the initial address, as described in the Single Write Access
section above. When ADV/LD is driven HIGH on the subse-
quent clock rise, the chip enables (CE1, CE2, and CE3) and
WE inputs are ignored and the burst counter is incremented.
The correct BW (BWa,b,c,d for CY7C1354CV25 and BWa,b for
CY7C1356CV25) inputs must be driven in each cycle of the
burst write in order to write the correct bytes of data.
A1,A0
00
01
10
11
A1,A0
01
00
11
10
A1,A0
10
11
00
01
A1,A0
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
Second
Address
Third
Address
Fourth
Address
A1,A0
00
01
10
11
A1,A0
01
10
11
00
A1,A0
10
11
00
01
A1,A0
11
00
01
10
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
Test Conditions
ZZ > VDD − 0.2V
ZZ > VDD − 0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Min.
Max
Unit
50
mA
tZZS
2tCYC
ns
ns
ns
ns
tZZREC
tZZI
2tCYC
0
ZZ active to sleep current
2tCYC
tRZZI
ZZ Inactive to exit sleep current
Truth Table[2, 3, 4, 5, 6, 7, 8]
Address
Used
Operation
CE ZZ ADV/LD WE BWx
OE
CEN CLK
L-H
DQ
Deselect Cycle
None
H
X
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
X
X
H
X
H
X
L
X
X
X
X
X
X
L
X
X
L
L
L
L
L
L
L
L
L
L
L
Three-State
Three-State
Data Out (Q)
Data Out (Q)
Three-State
Three-State
Data In (D)
Data In (D)
Three-State
Three-State
–
Continue Deselect Cycle
None
L-H
Read Cycle (Begin Burst)
Read Cycle (Continue Burst)
NOP/Dummy Read (Begin Burst)
Dummy Read (Continue Burst)
Write Cycle (Begin Burst)
External
Next
L-H
X
L
H
L
L
L-H
External
Next
H
H
X
X
X
X
X
X
L-H
X
L
H
L
L-H
External
Next
L-H
Write Cycle (Continue Burst)
NOP/WRITE ABORT (Begin Burst)
WRITE ABORT (Continue Burst)
IGNORE CLOCK EDGE (Stall)
X
L
H
L
X
L
L
L-H
None
H
H
X
X
L-H
Next
X
X
X
H
X
X
X
X
X
L-H
Current
None
H
X
L-H
X
SLEEP MODE
Three-State
Notes:
2. X = “Don’t Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx =
Valid signifies that the desired Byte Write Selects are asserted, see Write Cycle Description table for details.
3. Write is defined by WE and BW . See Write Cycle Description table for details.
X
4. When a write cycle is detected, all I/Os are three-stated, even during Byte Writes.
5. The DQ and DQP pins are controlled by the current cycle and the OE signal.
6. CEN = H inserts wait states.
7. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP = Three-state when
X
OE is inactive or when the device is deselected, and DQs = data when OE is active.
Document #: 38-05537 Rev. *B
Page 8 of 25
CY7C1354CV25
CY7C1356CV25
PRELIMINARY
Partial Write Cycle Description[2, 3, 4, 9]
Function (CY7C1354CV25)
Read
BWd
BWc
X
H
H
H
H
L
BWb
X
H
H
L
BWa
X
H
L
WE
H
L
X
H
H
H
H
H
H
H
H
L
Write –No bytes written
Write Byte a– (DQa and DQPa)
Write Byte b – (DQb and DQPb)
Write Bytes b, a
L
L
H
L
L
L
Write Byte c – (DQc and DQPc)
Write Bytes c, a
L
H
H
L
H
L
L
L
Write Bytes c, b
L
L
H
L
Write Bytes c, b, a
L
L
L
Write Byte d – (DQd and DQPd)
Write Bytes d, a
L
H
H
H
H
L
H
H
L
H
L
L
L
Write Bytes d, b
L
L
H
L
Write Bytes d, b, a
L
L
L
Write Bytes d, c
L
L
H
H
L
H
L
Write Bytes d, c, a
L
L
L
Write Bytes d, c, b
L
L
L
H
L
Write All Bytes
L
L
L
L
Partial Write Cycle Description[2, 3, 4, 9]
Function (CY7C1356CV25)
Read
WE
H
L
BWb
BWa
x
H
H
L
x
H
L
Write – No Bytes Written
Write Byte a − (DQa and DQPa)
Write Byte b – (DQb and DQPb)
Write Both Bytes
L
L
H
L
L
L
The CY7C1354CV25/CY7C1356CV25 contains
controller, instruction register, boundary scan register, bypass
register, and ID register.
a
TAP
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1354CV25/CY7C1356CV25 incorporates a serial
boundary scan test access port (TAP) in the BGA package
only. The TQFP package does not offer this functionality. This
part operates in accordance with IEEE Standard 1149.1-1900,
but doesn’t have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note the TAP controller
functions in a manner that does not conflict with the operation
of other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 2.5V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied
LOW(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may alter-
nately be connected to VDD through a pull-up resistor. TDO
should be left unconnected. Upon power-up, the device will
come up in a reset state which will not interfere with the
operation of the device.
Note:
9. Table only lists a partial listing of the byte write combinations. Any combination of BW is valid. Appropriate write will be done based on which byte write is active.
X
Document #: 38-05537 Rev. *B
Page 9 of 25
CY7C1354CV25
CY7C1356CV25
PRELIMINARY
TAP Controller State Diagram[10]
TAP Controller Block Diagram
0
TEST-LOGIC
1
RESET
0
Bypass Register
2
1
0
1
1
1
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
0
Selection
Circuitry
Instruction Register
31 30 29
Identification Register
Selection
0
0
TDI
TDO
Circuitr
y
1
1
.
.
.
2
1
0
CAPTURE-DR
CAPTURE-IR
0
0
x
.
.
.
.
. 2 1 0
SHIFT-DR
0
SHIFT-IR
0
Boundary Scan Register
TAP CONTROLLER
1
1
1
1
EXIT1-DR
EXIT1-IR
0
0
TCK
TMS
PAUSE-DR
0
PAUSE-IR
0
1
1
0
0
EXIT2-DR
1
EXIT2-IR
1
Performing a TAP Reset
UPDATE-DR
UPDATE-IR
A RESET is performed by forcing TMS HIGH (VDD) for five
rising edges of TCK. This RESET does not affect the operation
of the SRAM and may be performed while the SRAM is
operating.
1
0
1
0
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High-Z state.
Test Access Port (TAP)
Test Clock (TCK)
TAP Registers
The test clock is used only with the TAP controller. All inputs
are captured on the rising edge of TCK. All outputs are driven
from the falling edge of TCK.
Registers are connected between the TDI and TDO balls and
allow data to be scanned into and out of the SRAM test
circuitry. Only one register can be selected at a time through
the instruction register. Data is serially loaded into the TDI ball
on the rising edge of TCK. Data is output on the TDO ball on
the falling edge of TCK.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. It is allowable to
leave this ball unconnected if the TAP is not used. The ball is
pulled up internally, resulting in a logic HIGH level.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the
TDI and TDO balls as shown in the Tap Controller Block
Diagram. Upon power-up, the instruction register is loaded
with the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state as
described in the previous section.
Test Data-In (TDI)
The TDI ball is used to serially input information into the
registers and can be connected to the input of any of the
registers. The register between TDI and TDO is chosen by the
instruction that is loaded into the TAP instruction register. For
information on loading the instruction register, see Figure . TDI
is internally pulled up and can be unconnected if the TAP is
unused in an application. TDI is connected to the most signif-
icant bit (MSB) of any register. (See Tap Controller Block
Diagram.)
When the TAP controller is in the Capture-IR state, the two
least significant bits are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test data path.
Bypass Register
Test Data-Out (TDO)
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This allows data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW
(VSS) when the BYPASS instruction is executed.
The TDO output ball is used to serially clock data-out from the
registers. The output is active depending upon the current
state of the TAP state machine. The output changes on the
falling edge of TCK. TDO is connected to the least significant
bit (LSB) of any register. (See Tap Controller State Diagram.)
Note:
10. The 0/1 next to each state represents the value of TMS at the rising edge of the TCK.
Document #: 38-05537 Rev. *B
Page 10 of 25
CY7C1354CV25
CY7C1356CV25
PRELIMINARY
Boundary Scan Register
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because
there is a large difference in the clock frequencies, it is
possible that during the Capture-DR state, an input or output
will undergo a transition. The TAP may then try to capture a
signal while in transition (metastable state). This will not harm
the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible.
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR
state and is then placed between the TDI and TDO balls when
the controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
To guarantee that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture set-up plus
hold times (tCS and tCH). The SRAM clock input might not be
captured correctly if there is no way in a design to stop (or
slow) the clock during a SAMPLE/PRELOAD instruction. If this
is an issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK# captured in the
boundary scan register.
The Boundary Scan Order tables show the order in which the
bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected
to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired
into the SRAM and can be shifted out when the TAP controller
is in the Shift-DR state. The ID register has a vendor code and
other information described in the Identification Register
Definitions table.
Once the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the
boundary scan register between the TDI and TDO pins.
PRELOAD allows an initial data pattern to be placed at the
latched parallel outputs of the boundary scan register cells
prior to the selection of another boundary scan test operation.
TAP Instruction Set
The shifting of data for the SAMPLE and PRELOAD phases
can occur concurrently when required - that is, while data
captured is shifted out, the preloaded data can be shifted in.
Overview
Eight different instructions are possible with the three bit
instruction register. All combinations are listed in the
Instruction Codes table. Three of these instructions are listed
as RESERVED and should not be used. The other five instruc-
tions are described in detail below.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO pins. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction once it is shifted in, the TAP
controller needs to be moved into the Update-IR state.
EXTEST
The EXTEST instruction enables the preloaded data to be
driven out through the system output pins. This instruction also
selects the boundary scan register to be connected for serial
access between the TDI and TDO in the shift-DR controller
state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and allows
the IDCODE to be shifted out of the device when the TAP
controller enters the Shift-DR state.
EXTEST OUTPUT BUS TRI-STATE
The IDCODE instruction is loaded into the instruction register
upon power-up or whenever the TAP controller is given a test
logic reset state.
IEEE Standard 1149.1 mandates that the TAP controller be
able to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #85
(for 119-BGA package), bit #89 (for 165-FBGA package).
When this scan cell, called the “extest output bus tristate”, is
latched into the preload register during the “Update-DR” state
in the TAP controller, it will directly control the state of the
output (Q-bus) pins, when the EXTEST is entered as the
current instruction. When HIGH, it will enable the output
buffers to drive the output bus. When LOW, this bit will place
the output bus into a High-Z condition.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO pins when the TAP
controller is in a Shift-DR state. The SAMPLE Z command puts
the output bus into a High-Z state until the next command is
given during the “Update IR” state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and output pins is
captured in the boundary scan register.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that
cell, during the “Shift-DR” state. During “Update-DR,” the value
loaded into that shift-register cell will latch into the preload
register. When the EXTEST instruction is entered, this bit will
directly control the output Q-bus pins. Note that this bit is
Document #: 38-05537 Rev. *B
Page 11 of 25
CY7C1354CV25
CY7C1356CV25
PRELIMINARY
pre-set HIGH to enable the output when the device is
powered-up, and also when the TAP controller is in the
“Test-Logic-Reset” state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
TAP Timing
1
2
3
4
5
6
Test Clock
(TCK)
t
t
t
CYC
TH
TL
t
t
t
t
TMSS
TDIS
TMSH
Test Mode Select
(TMS)
TDIH
Test Data-In
(TDI)
t
TDOV
t
TDOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
TAP AC Switching Characteristics Over the Operating Range[11, 12]
Parameter
Clock
tTCYC
tTF
Description
Min.
Max.
Unit
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
50
ns
MHz
ns
20
tTH
25
25
tTL
ns
Output Times
tTDOV TCK Clock LOW to TDO Valid
tTDOX TCK Clock LOW to TDO Invalid
Set-up Times
tTMSS TMS Set-up to TCK Clock Rise
tTDIS
5
ns
ns
0
5
5
5
ns
ns
TDI Set-up to TCK Clock Rise
Capture Set-up to TCK Rise
tCS
Hold Times
tTMSH
tTDIH
TMS hold after TCK Clock Rise
TDI Hold after Clock Rise
5
5
5
ns
ns
ns
tCH
Capture Hold after Clock Rise
Notes:
11. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register.
CS
CH
12. Test conditions are specified using the load in TAP AC test Conditions. t /t = 1ns.
R
F
Document #: 38-05537 Rev. *B
Page 12 of 25
CY7C1354CV25
CY7C1356CV25
PRELIMINARY
2.5V TAP AC Test Conditions
2.5V TAP AC Output Load Equivalent
1.25V
Input pulse levels ........................................ VSS to 2.5V
Input rise and fall time .................................................... 1 ns
Input timing reference levels ........................................1.25V
Output reference levels ................................................1.25V
Test load termination supply voltage.............................1.25V
50Ω
TDO
ZO= 50Ω
20pF
TAP DC Electrical Characteristics And Operating Conditions
(0°C < TA < +70°C; Vdd = 2.5V ±0.125V unless otherwise noted)[13]
Parameter
VOH1
Description
Test Conditions
Min.
Max.
Unit
2.0
V
Output HIGH Voltage IOH = -1.0 mA, VDDQ = 2.5V
Output HIGH Voltage IOH = -100 µA,VDDQ = 2.5V
Output LOW Voltage IOL = 8.0 mA, VDDQ = 2.5V
Output LOW Voltage IOL = 100 µA
Input HIGH Voltage
2.1
V
V
VOH2
VOL1
VOL2
VIH
0.4
0.2
VDDQ = 2.5V
V
VDDQ = 2.5V
VDDQ = 2.5V
1.7
-0.3
-5
VDD + 0.3
V
0.7
5
V
VIL
Input LOW Voltage
µA
IX
Input Load Current
GND < VIN < VDDQ
Identification Register Definitions
Instruction Field
Revision Number (31:29)
Cypress Device ID (28:12)
Cypress JEDEC ID (11:1)
ID Register Presence (0)
CY7C1354CV25
000
01011001000100110 01011001000010110 Reserved for future use.
CY7C1356CV25
Description
000
Reserved for version number.
00000110100
1
00000110100
1
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
69
69
Boundary Scan Order (119-ball BGA package)
Boundary Scan Order (165-ball fBGA package)
Identification Codes
Instruction
EXTEST
Code
Description
000 Captures the Input/Output ring contents. Places the boundary scan register between the TDI and
TDO. Forces all SRAM outputs to High-Z state.
IDCODE
001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This
operation does not affect SRAM operation.
SAMPLE Z
RESERVED
010 Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scanregister between TDI and TDO.
Does not affect the SRAM operation.
Note:
13. All voltages referenced to VSS (GND).
Document #: 38-05537 Rev. *B
Page 13 of 25
CY7C1354CV25
CY7C1356CV25
PRELIMINARY
Identification Codes (continued)
Instruction
RESERVED
Code
Description
101 Do Not Use: This instruction is reserved for future use.
RESERVED
BYPASS
110
111
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
Boundary Scan Exit Order (×36) (continued)
Boundary Scan Exit Order (×36)
Bit #
42
43
44
45
46
47
48
49
50
51
119-Ball ID
165-Ball ID
Bit #
1
119-Ball ID
K4
H4
M4
F4
165-Ball ID
B6
P2
P1
L2
N1
L2
K2
J2
2
B7
3
A7
K1
N2
N1
M2
L1
4
B8
M2
M1
L1
K1
J1
5
B4
G4
C3
B3
D6
H7
G6
E6
D7
E7
F6
A8
6
A9
7
B10
A10
C11
E10
F10
G10
D10
D11
E11
F11
G11
H11
J10
K10
L10
M10
J11
K11
L11
M11
N11
R11
R10
P10
R9
8
K2
9
Not Bonded
(Preset to 1)
Not Bonded
(Preset to 1)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
H1
G2
E2
D1
H2
G1
F2
E1
D2
C2
A2
E4
B2
L3
G2
F2
E2
D2
G1
F1
E1
D1
C1
B2
A2
A3
B3
B4
A4
A5
B5
A6
G7
H6
T7
K7
L6
N6
P7
N7
M6
L7
G3
G5
L5
K6
P6
T4
B6
A3
C5
B5
A5
C6
A6
P4
N4
R6
T5
Boundary Scan Exit Order (×18)
Bit #
119-Ball ID
165-Ball ID
B6
P9
1
2
3
4
5
6
7
8
9
K4
H4
M4
F4
B4
G4
C3
B3
T2
R8
B7
P8
A7
R6
B8
P6
A8
R4
A9
P4
B10
A10
A11
T3
R3
R2
R3
P3
R1
Document #: 38-05537 Rev. *B
Page 14 of 25
CY7C1354CV25
CY7C1356CV25
PRELIMINARY
Boundary Scan Exit Order (×18) (continued)
Boundary Scan Exit Order (×18) (continued)
Bit #
119-Ball ID
165-Ball ID
Bit #
48
119-Ball ID
165-Ball ID
10
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
M2
L1
L1
K1
J1
49
11
12
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
50
K2
51
Not Bonded
(Preset to 1)
Not Bonded
(Preset to 1)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
52
53
54
55
56
H1
G2
E2
D1
G2
F2
E2
D2
13
14
15
16
17
18
19
20
21
22
23
D6
E7
F6
G7
H6
T7
K7
L6
C11
D11
E11
F11
G11
H11
J10
K10
L10
M10
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
57
58
59
60
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
N6
P7
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
24
25
26
27
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
61
62
63
64
65
C2
A2
E4
B2
B2
A2
A3
B3
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
66
67
G3
Not Bonded
(Preset to 0)
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
T6
A3
C5
B5
A5
C6
A6
P4
N4
R6
T5
T3
R2
R3
R11
R10
P10
R9
P9
Not Bonded
(Preset to 0
A4
68
69
69
69
68
69
66
L5
B6
B6
B6
L5
B6
G3
B5
A6
A6
A6
B5
A6
R8
P8
R6
P6
Not Bonded
(Preset to 0)
R4
P4
67
Not Bonded
(Preset to 0
A4
R3
P3
68
69
L5
B6
B5
A6
R1
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
43
44
45
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
Not Bonded
(Preset to 0)
46
47
P2
N1
N1
M1
Document #: 38-05537 Rev. *B
Page 15 of 25
CY7C1354CV25
CY7C1356CV25
PRELIMINARY
Current into Outputs (LOW)......................................... 20 mA
Maximum Ratings
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-up Current.................................................... > 200 mA
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
VDD /VDDQ
Supply Voltage on VDD Relative to GND........ –0.5V to +3.6V
DC to Outputs in Three-State.............. –0.5V to VDDQ + 0.5V
DC Input Voltage....................................–0.5V to VDD + 0.5V
2.5V +_ 5%
–40°C to +85°C
Electrical Characteristics Over the Operating Range[14, 15]
Parameter
VDD
Description
Test Conditions
Min.
2.375
2.375
2.0
Max.
Unit
V
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
2.625
VDD
VDDQ
VOH
VOL
VIH
VIL
V
VDD = Min., IOH = −1.0 mA
V
VDD = Min., IOL= 1.0 mA
0.4
V
VDDQ = 2.5V
1.7
–0.3
–5
VDD + 0.3V
V
Input LOW Voltage[14] VDDQ = 2.5V
0.7
5
V
IX
Input Load
GND ≤ VI ≤ VDDQ
µA
µA
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
Input Current of MODE Input = VSS
Input = VDD
–30
5
Input Current of ZZ
Input = VSS
Input = VDD
–5
–5
30
5
IOZ
IDD
Output Leakage Current GND ≤ VI ≤ VDD, Output Disabled
VDD Operating Supply VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
4.4-ns cycle, 225 MHz
250
220
180
130
120
110
5-ns cycle, 200 MHz
6-ns cycle, 167 MHz
ISB1
Automatic CE
Power-down
Current—TTL Inputs
Max. VDD, Device Deselected, 4.4-ns cycle, 225 MHz
VIN ≥ VIH or VIN ≤ VIL, f = fMAX =
5-ns cycle, 200 MHz
6-ns cycle, 167 MHz
1/tCYC
ISB2
Automatic CE
Power-down
Current—CMOS Inputs f = 0
Max. VDD, Device Deselected, All speed grades
VIN ≤ 0.3V or VIN > VDDQ − 0.3V,
35
mA
ISB3
Automatic CE
Power-down
Current—CMOS Inputs f = fMAX = 1/tCYC
Max. VDD, Device Deselected, 4.4-ns cycle, 225 MHz
120
110
100
mA
mA
mA
VIN ≤ 0.3V or VIN > VDDQ − 0.3V,
5-ns cycle, 200 MHz
6-ns cycle, 167 MHz
ISB4
Automatic CE
Power-down
Current—TTL Inputs
Max. VDD, Device Deselected, All speed grades
VIN ≥ VIH or VIN ≤ VIL, f = 0
40
mA
Shaded areas contain advance information.
Thermal Resistance[16]
Parameters
ΘJA
Description
Test Conditions
BGA Typ.
fBGA Typ.
TQFP Typ.
Unit
Thermal Resistance
(Junction to Ambient)
Test conditions follow standard
test methods and procedures
for measuring thermal
25
27
25
°C/W
ΘJC
Thermal Resistance
(Junction to Case)
6
6
9
°C/W
impedance, per EIA / JESD51.
Notes:
14. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than t
/2), undershoot: V (AC)> –2V (Pulse width less than t
/2).
CYC
IL
CYC
15. T
: Assumes a linear ramp from 0V to V
(min.) within 200 ms. During this time V < V and V
< V
.
Power-up
IH
DD
DDQ
DD
DD
16. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05537 Rev. *B
Page 16 of 25
CY7C1354CV25
CY7C1356CV25
PRELIMINARY
Capacitance[16]
Parameter
Description
Test Conditions
BGA Max.
fBGA Max.
TQFP Max.
Unit
pF
CIN
Input Capacitance
TA = 25°C, f = 1 MHz,
DD = 2.5V, VDDQ = 2.5V
5
5
7
5
5
7
5
5
5
V
CCLK
CI/O
Clock Input Capacitance
Input/Output Capacitance
pF
pF
AC Test Loads and Waveforms
2.5V I/O Test Load
R = 1667Ω
2.5V
OUTPUT
OUTPUT
ALL INPUT PULSES
90%
VDDQ
GND
90%
10%
Z = 50Ω
0
10%
R = 50Ω
L
5 pF
INCLUDING
R =1538Ω
≤ 1ns
≤ 1ns
V = 1.25V
T
JIG AND
SCOPE
(a)
(b)
(c)
Switching Characteristics Over the Operating Range [18, 19]
-225
Max.
-200
-167
Parameter
Description
Min.
Min.
Max.
Min.
Max.
Unit
[17]
tPower
VCC (typical) to the First Access Read or
Write
1
1
1
ms
Clock
tCYC
Clock Cycle Time
Maximum Operating Frequency
Clock HIGH
4.4
5
6
ns
MHz
ns
FMAX
tCH
225
200
167
1.8
1.8
2.0
2.0
2.4
2.4
tCL
Clock LOW
ns
Output Times
tCO
Data Output Valid after CLK Rise
OE LOW to Output Valid
2.8
2.8
3.2
3.2
3.5
3.5
ns
ns
ns
ns
ns
ns
ns
tEOV
tDOH
Data Output Hold after CLK Rise
Clock to High-Z[20, 21, 22]
Clock to Low-Z[20, 21, 22]
1.25
1.25
1.25
1.5
1.5
1.5
1.5
1.5
1.5
tCHZ
2.8
2.8
3.2
3.2
3.5
3.5
tCLZ
HIGH to Output High-Z[20, 21, 22]
OE LOW to Output Low-Z[20, 21, 22]
tEOHZ
tEOLZ
Set-up Times
tAS
OE
0
0
0
Address Set-up before CLK Rise
Data Input Set-up before CLK Rise
1.4
1.4
1.4
1.4
1.4
1.4
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
tDS
tCENS
tWES
CEN Set-up before CLK Rise
WE, BWx Set-up before CLK Rise
tALS
ADV/LD Set-up before CLK Rise
Chip Select Set-up
tCES
Shaded areas contain advance information.
Notes:
17. This part has a voltage regulator internally; t
is the time power needs to be supplied above V minimum initially, before a Read or Write operation can be
DD
power
initiated.
18. Timing reference level is when V
= 2.5V.
DDQ
19. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
20. t , t , t , and t are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ CLZ EOLZ
EOHZ
21. At any given voltage and temperature, t
is less than t
and t
is less than t
to eliminate bus contention between SRAMs when sharing the same
CLZ
EOHZ
EOLZ
CHZ
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
22. This parameter is sampled and not 100% tested.
Document #: 38-05537 Rev. *B
Page 17 of 25
CY7C1354CV25
CY7C1356CV25
PRELIMINARY
Switching Characteristics Over the Operating Range (continued)[18, 19]
-225
-200
-167
Parameter
Hold Times
tAH
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Address Hold after CLK Rise
Data Input Hold after CLK Rise
0.4
0.4
0.4
0.4
0.4
0.4
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tDH
tCENH
CEN Hold after CLK Rise
tWEH
WE, BWx Hold after CLK Rise
tALH
ADV/LD Hold after CLK Rise
tCEH
Chip Select Hold after CLK Rise
Switching Waveforms
Read/Write Timing[23,24,25]
1
2
3
4
5
6
7
8
9
10
t
CYC
t
CLK
t
t
t
CENS CENH
CL
CH
CEN
t
t
CES
CEH
CE
ADV/LD
WE
BW
X
A1
A2
A4
CO
A3
A5
A6
A7
ADDRESS
t
t
t
t
DS
DH
t
t
t
DOH
OEV
CLZ
CHZ
t
t
AS
AH
Data
D(A1)
D(A2)
D(A2+1)
Q(A3)
Q(A4)
OEHZ
Q(A4+1)
D(A5)
Q(A6
-Out (DQ)
t
t
DOH
t
OELZ
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
READ
Q(A3)
READ
Q(A4)
BURST
READ
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DESELECT
D(A2+1)
Q(A4+1)
DON’T CARE
UNDEFINED
Notes:
23. For this waveform ZZ is tied low.
24. When CE is LOW, CE is LOW, CE is HIGH and CE is LOW. When CE is HIGH,CE is HIGH or CE is LOW or CE is HIGH.
1
2
3
1
2
3
25. Order of the Burst sequence is determined by the status of the MODE (0=Linear, 1=Interleaved).Burst operations are optional.
Document #: 38-05537 Rev. *B
Page 18 of 25
CY7C1354CV25
CY7C1356CV25
PRELIMINARY
Switching Waveforms (continued)
NOP, STALL and DESELECT CYCLES[23,24,26]
1
2
3
4
5
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BW
X
A1
A2
A3
A4
A5
ADDRESS
t
CHZ
D(A4)
D(A1)
Q(A2)
Q(A3)
Q(A5)
Data
In-Out (DQ)
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
DON’T CARE
UNDEFINED
ZZ Mode Timing[27,28]
CLK
t
t
ZZ
ZZREC
ZZ
t
ZZI
I
SUPPLY
I
DDZZ
t
RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
26. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle
27. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device.
28. I/Os are in High-Z when exiting ZZ sleep mode.
Document #: 38-05537 Rev. *B
Page 19 of 25
CY7C1354CV25
CY7C1356CV25
PRELIMINARY
Ordering Information
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Package Type
225
CY7C1354CV25-225AXC
CY7C1356CV25-225AXC
CY7C1354CV25-225AXI
CY7C1356CV25-225AXI
CY7C1354CV25-225BGC
CY7C1356CV25-225BGC
CY7C1354CV25-225BGI
CY7C1356CV25-225BGI
CY7C1354CV25-225BZC
CY7C1356CV25-225BZC
CY7C1354CV25-225BZI
CY7C1356CV25-225BZI
CY7C1354CV25-225BGXC
CY7C1356CV25-225BGXC
CY7C1354CV25-225BGXI
CY7C1356CV25-225BGXI
CY7C1354CV25-225BZXC
CY7C1356CV25-225BZXC
CY7C1354CV25-225BZXI
CY7C1356CV25-225BZXI
CY7C1354CV25-200AXC
CY7C1356CV25-200AXC
CY7C1354CV25-200AXI
CY7C1356CV25-200AXI
CY7C1354CV25-200BGC
CY7C1356CV25-200BGC
CY7C1354CV25-200BGI
CY7C1356CV25-200BGI
CY7C1354CV25-200BZC
CY7C1356CV25-200BZC
CY7C1354CV25-200BZI
CY7C1356CV25-200BZI
CY7C1354CV25-200BGXC
CY7C1356CV25-200BGXC
CY7C1354CV25-200BGXI
CY7C1356CV25-200BGXI
CY7C1354CV25-200BZXC
CY7C1356CV25-200BZXC
CY7C1354CV25-200BZXI
CY7C1356CV25-200BZXI
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x
1.4 mm)
Commercial
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x
1.4 mm)
Industrial
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
Commercial
Industrial
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial
BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial
BG119 Lead-Free 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Commercial
BG119 Lead-Free 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
Industrial
Commercial
Industrial
BB165D Lead-Free 165-ball Fine Pitch Ball Grid Array (13 x
15 x 1.4 mm)
BB165D Lead-Free 165-ball Fine Pitch Ball Grid Array (13 x
15 x 1.4 mm)
200
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x
1.4 mm)
Commercial
Industrial
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x
1.4 mm)
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
Commercial
Industrial
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial
BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial
BG119 Lead-Free 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Commercial
BG119 Lead-Free 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
Industrial
Commercial
Industrial
BB165D Lead-Free 165-ball Fine Pitch Ball Grid Array (13 x
15 x 1.4 mm)
BB165D Lead-Free 165-ball Fine Pitch Ball Grid Array (13 x
15 x 1.4 mm)
Document #: 38-05537 Rev. *B
Page 20 of 25
CY7C1354CV25
CY7C1356CV25
PRELIMINARY
Ordering Information (continued)
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Package Type
167
CY7C1354CV25-167AXC
CY7C1356CV25-167AXC
CY7C1354CV25-167AXI
CY7C1356CV25-167AXI
CY7C1354CV25-167BGC
CY7C1356CV25-167BGC
CY7C1354CV25-167BGI
CY7C1356CV25-167BGI
CY7C1354CV25-167BZC
CY7C1356CV25-167BZC
CY7C1354CV25-167BZI
CY7C1356CV25-167BZI
CY7C1354CV25-167BGXC
CY7C1356CV25-167BGXC
CY7C1354CV25-167BGXI
CY7C1356CV25-167BGXI
CY7C1354CV25-167BZXC
CY7C1356CV25-167BZXC
CY7C1354CV25-167BZXI
CY7C1356CV25-167BZXI
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x
1.4 mm)
Commercial
A101
Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x
1.4 mm)
Industrial
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
Commercial
Industrial
BG119 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Commercial
BB165D 165-ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Industrial
BG119 Lead-Free 119-ball Ball Grid Array (14 x 22 x 2.4 mm) Commercial
BG119 Lead-Free 119-ball Ball Grid Array (14 x 22 x 2.4 mm)
Industrial
Commercial
Industrial
BB165D Lead-Free 165-ball Fine Pitch Ball Grid Array (13 x
15 x 1.4 mm)
BB165D Lead-Free 165-ball Fine Pitch Ball Grid Array (13 x
15 x 1.4 mm)
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Lead-free BGX package will be
available in 2005.
Document #: 38-05537 Rev. *B
Page 21 of 25
CY7C1354CV25
CY7C1356CV25
PRELIMINARY
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
DIMENSIONS ARE IN MILLIMETERS.
ꢁ6.00 0.20
ꢁ4.00 0.ꢁ0
ꢁ.40 0.05
ꢁ00
ꢀꢁ
ꢀ0
ꢁ
0.30 0.0ꢀ
0.65
TYP.
ꢁ2° ꢁ°
(ꢀX)
SEE DETAIL
A
30
5ꢁ
3ꢁ
50
0.20 MAX.
ꢁ.60 MAX.
R 0.0ꢀ MIN.
0.20 MAX.
0° MIN.
STAND-OFF
0.05 MIN.
0.ꢁ5 MAX.
SEATING PLANE
0.25
GAUGE PLANE
R 0.0ꢀ MIN.
0.20 MAX.
0°-7°
0.60 0.ꢁ5
0.20 MIN.
ꢁ.00 REF.
51-85050-*A
DETAIL
A
Document #: 38-05537 Rev. *B
Page 22 of 25
CY7C1354CV25
CY7C1356CV25
PRELIMINARY
Package Diagrams (continued)
119-Lead BGA (14 x 22 x 2.4mm) BG119
51-85115-*B
Document #: 38-05537 Rev. *B
Page 23 of 25
CY7C1354CV25
CY7C1356CV25
PRELIMINARY
Package Diagrams (continued)
165 FBGA 13 x 15 x 1.40 MM BB165D
51-85180-**
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device
Technology. All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05537 Rev. *B
Page 24 of 25
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1354CV25
CY7C1356CV25
PRELIMINARY
Document History Page
Document Title: CY7C1354CV25/CY7C1356CV25 9-Mbit (256K x 36/512K x 18) Pipelined SRAM
with NoBL™ Architecture
Document Number: 38-05537
Orig. of
REV.
**
ECN No. Issue Date Change
Description of Change
242032
278969
284929
See ECN
See ECN
See ECN
RKF
RKF
New data sheet
*A
Changed Boundary Scan order to match the B Rev of these devices
*B
RKF
VBL
Included DC Characteristics Table
Changed ISB1 and ISB3 from DC Characteristic table as follows:
ISB1: 225 MHz -> 130 mA, 200 MHz -> 120 mA, 167 MHz -> 110 mA
ISB3: 225 MHz -> 120 mA, 200 MHz -> 110 mA, 167 MHz -> 100 mA
Changed IDDZZ to 50mA.
Added BG and BZ pkg lead-free part numbers to ordering info section.
Document #: 38-05537 Rev. *B
Page 25 of 25
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