CY7C1346L-166AC_技术文档

fax id: 1112

PRELIMINARY

CY7C1346

64K x 36 Synchronous-Pipelined Cache RAM

Features

Functional Description

• Low (1.65 mW) standby power (f=0, L version)

The CY7C1346 is a 3.3V 64K by 36 synchronous-pipelined

cache SRAM designed to support zero wait state secondary

cache with minimal glue logic.

• Supports 100-MHz bus for Pentium® and PowerPC™

operations with zero wait states

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. Max-

imum access delay from the clock rise is 3.5 ns (166-MHz

device). A 2-bit on-chip wraparound burst counter captures the

first address in a burst sequence and automatically increments

the address for the rest of the burst access.

• Fully registered inputs and outputs for pipelined

operation

• 64K x 36 common I/O architecture

• Single 3.3V power supply

• Fast clock-to-output times

— 3.5 ns (for 166-MHz device)

— 4.0 ns (for 133-MHz device)

— 4.5 ns (for 117-MHz device)

— 5.5 ns (for 100-MHz device)

The CY7C1346 supports either the interleaved burst se-

quence used by the Intel Pentium processor or a linear burst

sequence used by processors such as the PowerPC. The burst

sequence is selected through the MODE pin. Accesses can be

initiated by asserting either the processor address strobe

(ADSP) or the controller address strobe (ADSC) at clock rise.

Address advancement through the burst sequence is con-

trolled by the ADV input.

• User-selectable burst counter supporting Intel®

Pentium interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

Byte write operations are qualified with the four Byte Write

Select (BW

) inputs. A Global Write Enable (GW) overrides

[3:0]

• Asynchronous output enable

the byte write inputs and writes data to all four bytes. All writes

are conducted with on-chip synchronous self-timed write cir-

cuitry.

• JEDEC-standard 100-pin TQFP pinout

• “ZZ” Sleep Mode option and Stop Clock option

Three synchronous chip selects (CE , CE , CE ) and an asyn-

1

2

3

chronous output enable (OE) provide for easy bank selection

and output three-state control. In order to provide proper data

during depth expansion, OE is masked during the first clock of

a read cycle when emerging from a deselected state.

Logic Block Diagram

2

(A ,A )

0

1

Q

0

CLK

ADV

ADSC

BURST

COUNTER

CE

CLR

Q

1

ADSP

Q

14

16

ADDRESS

REGISTER

CE

D

64K 36

X

A

[15:0]

16

14

MEMORY

ARRAY

GW

BWE

DDQ[31:24],DP[3]

Q

BW

BYTEWRITE

3

REGISTERS

DQ[23:16],DP[2]

D

Q

BW

2

BYTEWRITE

REGISTERS

DQ[15:8],DP[1]

BW

BYTEWRITE

1

REGISTERS

D

DQ[7:0],DP[0]

BYTEWRITE

BW

0

REGISTERS

36

CE

1

2

CE

D

ENABLE

REGISTER

Q

CE

3

CLK

D

Q

OUTPUT

REGISTERS

CLK

INPUT

REGISTERS

CLK

ENABLE DELAY

REGISTER

CLK

OE

ZZ

SLEEP

CONTROL

DQ

DP

[31:0]

[3:0]

Intel and Pentium are registered trademarks of Intel Corporation.

PowerPC is a trademark of IBM Corporation.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

August 24, 1998

PRELIMINARY

CY7C1346

Pin Configuration

100-Lead TQFP

DP₂

DQ₁₆

DQ₁₇

V_DDQ

V_SSQ

DQ₁₈

DQ₁₉

DQ₂₀

DQ₂₁

V_SSQ

V_DDQ

DQ₂₂

DQ₂₃

NC

DP₁

1

2

3

4

5

6

7

8

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

DQ₁₅

DQ₁₄

V_DDQ

V_SSQ

DQ₁₃

DQ₁₂

DQ₁₁

DQ₁₀

V_SSQ

V_DDQ

DQ₉

DQ₈

V_SS

BYTE2

BYTE1

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

V_DD

NC

V_SS

NC

V_DD

ZZ

DQ₂₄

DQ₂₅

V_DDQ

V_SSQ

DQ₂₆

DQ₂₇

DQ₂₈

DQ₂₉

V_SSQ

V_DDQ

DQ₃₀

DQ₃₁

DP₃

DQ₇

DQ₆

V_DDQ

V_SSQ

DQ₅

DQ₄

DQ₃

DQ₂

V_SSQ

V_DDQ

DQ₁

DQ₀

DP₀

BYTE3

BYTE0

Selection Guide

7C1346-166 7C1346-133 7C1346-117 7C1346-100

Maximum Access Time (ns)

3.5

420

2.0

4.0

375

2.0

4.5

350

2.0

5.5

325

2.0

Maximum Operating Current (mA)

Maximum Standby Current (mA)

2

PRELIMINARY

CY7C1346

Pin Definitions

Pin Number

Name

I/O

Description

Address Inputs used to select one of the 64K address locations. Sampled at the

rising edge of the CLK if ADSP or ADSC is active LOW, and CE , CE , and CE

3

49–44,81,82,

99, 100,

A

Input-

[15:0]

Synchronous

1

2

32–37

are sampled active. A and A feed the 2-bit counter.

0 1

96–93

BW

Input-

Synchronous

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes

to the SRAM. Sampled on the rising edge of CLK.

[3:0]

88

GW

Input-

Synchronous

Global Write Enable Input, active LOW. When asserted LOW on the rising edge of

CLK, a global write is conducted (ALL bytes are written, regardless of the values

on BW

and BWE).

[1:0]

87

89

98

BWE

CLK

Input-

Synchronous

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This

signal must be asserted LOW to conduct a byte write.

Input-Clock

Clock input. Used to capture all synchronous inputs to the device. Also used to

increment the burst counter when ADV is asserted LOW, during a burst operation.

CE

Input-

Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in

1

conjunction with CE and CE to select/deselect the device. ADSP is ignored if

2 3

CE is HIGH.

1

97

92

86

CE

Input-

Synchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in

conjunction with CE and CE to select/deselect the device.

2

3

1

3

Input-

Synchronous

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in

conjunction with CE and CE to select/deselect the device.

1

2

OE

Input-

Output Enable, asynchronous input, active LOW. Controls the direction of the I/O

Asynchronous pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins

are three-stated, and act as input data pins. OE is masked during the first clock of

a read cycle when emerging from a deselected state.

83

84

ADV

Input-

Synchronous

Advance Input signal, sampled on the rising edge of CLK. When asserted, it auto-

matically increments the address in a burst cycle.

ADSP

Input-

Synchronous

Address Strobe from Processor, sampled on the rising edge of CLK. When assert-

ed LOW, A

is captured in the address registers. A and A are also loaded into

[15:0] 0 1

the burst counter. When ADSP and ADSC are both asserted, only ADSP is recog-

nized. ASDP is ignored when CE is deasserted HIGH.

1

85

64

ADSC

ZZ

Input-

Synchronous

Address Strobe from Controller, sampled on the rising edge of CLK. When assert-

ed LOW, A

is captured in the address registers. A and A are also loaded into

[15:0] 0 1

the burst counter. When ADSP and ADSC are both asserted, only ADSP is recog-

nized.

Input-

ZZ “sleep” Input. This active HIGH input places the device in a non-time critical

Asynchronous “sleep” condition with data integrity preserved.

30–28,

DQ

DP

,

I/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that

is triggered by the rising edge of CLK. As outputs, they deliver the data contained

in the memory location specified by A during the previous clock rise of the

[31:0]

[3:0]

25–22, 19,

18, 13, 12,

9–6, 3–1,

80–78,

75–72, 69,

68, 63, 62,

59–56, 53–51

[15:0]

read cycle. The direction of the pins is controlled by OE. When OE is asserted

LOW, the pins behave as outputs. When HIGH, DQ

a three-state condition.

and DP

are placed in

[31:0]

[3:0]

15, 41, 65, 91

V

Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power

supply.

DD

17, 40, 67, 90

V

Ground

Ground for the core of the device. Should be connected to ground of the system.

Power supply for the I/O circuitry. Should be connected to a 3.3V power supply.

SS

4, 11, 20, 27,

54, 61, 70, 77

I/O Power

Supply

DDQ

5, 10, 21, 26,

55, 60, 71, 76

V

I/O Ground

Ground for the I/O circuitry. Should be connected to ground of the system.

Selects burst order. When tied to GND selects linear burst sequence. When tied

SSQ

31

MODE

Input-

Static

to V

or left floating selects interleaved burst sequence. This is a strap pin and

DDQ

should remain static during device operation.

14, 16, 38, 39, NC

42, 43, 50, 66

-

No Connects

3

PRELIMINARY

CY7C1346

GW is HIGH, then the write operation is controlled by BWE and

Introduction

BW

signals. The CY7C1346 provides byte write capability

[3:0]

Functional Overview

that is described in the Write Cycle Descriptions table. Assert-

ing the Byte Write Enable input (BWE) with the selected Byte

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock. Max-

Write (BW

) input will selectively write to only the desired

[3:0]

bytes. Bytes not selected during a byte write operation will

remain unaltered. A synchronous self-timed write mechanism

has been provided to simplify the write operations.

imum access delay from the clock rise (t ) is 3.5 ns (166-MHz

CO

device). A two-bit on-chip wraparound burst counter captures

the first address in a burst sequence and automatically incre-

ments the address for the rest of the burst access.

Because the CY7C1346 is a common I/O device, the Output

Enable (OE) must be deasserted HIGH before presenting data

to the DQ –DQ and DP inputs. Doing so will three-state the

0

31

The CY7C1346 supports secondary cache in systems utilizing

either a linear or interleaved burst sequence. The interleaved

burst order supports Pentium and i486 processors. The linear

burst sequence is suited for processors that utilize a linear

burst sequence. The burst order is user selectable, and is de-

termined by sampling the MODE input. Accesses can be initi-

ated with either the processor address strobe (ADSP) or the

controller address strobe (ADSC). Address advancement

through the burst sequence is controlled by the ADV input.

output drivers. As a safety precaution, DQ –DQ and DPs are

0

31

automatically three-stated whenever a write cycle is detected,

regardless of the state of OE.

Single Write Accesses Initiated by ADSC

ADSC write accesses are initiated when the following condi-

tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is

deasserted HIGH, (3) CE , CE , CE are all asserted active,

1

2

3

and (4) the appropriate combination of the write inputs (GW,

Byte write operations are qualified with the Byte Write Enable

BWE, and BW ) are asserted active to conduct a write to

[3:0]

(BWE) and Byte Write Select (BW

) inputs. A Global Write

[3:0]

the desired byte(s). ADSC triggered write accesses require a

single clock cycle to complete. The address presented to

Enable (GW) overrides all byte write inputs and writes data to

all four bytes. All writes are simplified with on-chip synchro-

nous self-timed write circuitry.

A –A is loaded into the address register and the address

0

15

advancement logic while being delivered to the RAM core. The

ADV input is ignored during this cycle. If a global write is con-

Three synchronous chip selects (CE , CE , CE ) and an asyn-

1

2

3

chronous output enable (OE) provide for easy bank selection

ducted, the data presented to the DQ –DQ and DPs are

0 31

and output three-state control. ADSP is ignored if CE is

HIGH.

written into the corresponding address location in the RAM

core. If a byte write is conducted, only the selected bytes are

written. Bytes not selected during a byte write operation will

remain unaltered. A synchronous self-timed write mechanism

has been provided to simplify the write operations.

1

Single Read Accesses

This access is initiated when the following conditions are sat-

isfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)

Because the CY7C1346 is a common I/O device, the Output

Enable (OE) must be deasserted HIGH before presenting data

CE , CE , CE are all asserted active, and (3) the write signals

1

2

3

(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE

1

to the DQ –DQ and DP inputs. Doing so will three-state the

0 31

is HIGH. The address presented to the address inputs

output drivers. As a safety precaution, DQ –DQ and DPs are

0

31

(A –A ) is stored into the address advancement logic and the

0

15

automatically three-stated whenever a write cycle is detected,

Address Register while being presented to the memory core.

The corresponding data is allowed to propagate to the input of

the Output Registers. At the rising edge of the next clock the

data is allowed to propagate through the output register and

onto the data bus within 3.5 ns (166-MHz device) if OE is active

LOW. The only exception occurs when the SRAM is emerging

from a deselected state to a selected state, its outputs are

always three-stated during the first cycle of the access. After

the first cycle of the access, the outputs are controlled by the

OE signal. Consecutive single read cycles are supported.

Once the SRAM is deselected at clock rise by the chip select

and either ADSP or ADSC signals, its output will three-state

immediately.

regardless of the state of OE.

Burst Sequences

The CY7C1346 provides a two-bit wraparound counter, fed by

A and A , that implements either an interleaved or linear burst

0

1

sequence. The interleaved burst sequence is designed specif-

ically to support Intel Pentium applications. The linear burst

sequence is designed to support processors that follow a lin-

ear burst sequence. The burst sequence is user selectable

through the MODE input.

Asserting ADV LOW at clock rise will automatically increment

the burst counter to the next address in the burst sequence.

Both read and write burst operations are supported.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions

are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)

Interleaved Burst Sequence

First

Second

Address

Third

Address

Fourth

Address

CE , CE , CE are all asserted active. The address presented

1

2

3

Address

to A –A is loaded into the address register and the address

0

15

advancement logic while being delivered to the RAM core. The

Ax+1, Ax

write signals (GW, BWE, and BW

nored during this first cycle.

) and ADV inputs are ig-

[0:3]

00

01

10

11

01

00

11

10

11

00

01

11

10

01

00

ADSP triggered write accesses require two clock cycles to

complete. If GW is asserted LOW on the second clock rise, the

data presented to the DQ –DQ and DP inputs are written

0

31

into the corresponding address location in the RAM core. If

4

PRELIMINARY

CY7C1346

Sleep Mode

Linear Burst Sequence

The ZZ input pin is an asynchronous input. Asserting ZZ plac-

es the SRAM in a power conservation “sleep” mode. Two clock

cycles are required to enter into or exit from this “sleep” mode.

While in this mode, data integrity is guaranteed. Accesses

pending when entering the “sleep” mode are not considered

valid nor is the completion of the operation guaranteed. The

device must be deselected prior to entering the “sleep” mode.

First

Second

Third

Fourth

Address

Ax+1, Ax

00

01

10

11

01

10

11

00

10

11

00

01

11

00

01

10

CE , CE , CE , ADSP, and ADSC must remain inactive for the

1

2

3

duration of t

after the ZZ input returns LOW.

ZZREC

Cycle Description Table^{[1, 2, 3]}

ADD

Cycle Description

Used

CE CE

CE

X

L

ZZ ADSP ADSP ADV WE

OE CLK

DQ

1

3

2

Deselected Cycle, Power-down

Snooze Mode, Power-down

Read Cycle, Begin Burst

None

H

L

X

H

X

L

H

L

X

L

X

L

X

L

X

L

X

L

L-H High-Z

None

L

X

L

None

L

H

X

L

None

X

L

X

H

X

L

None

X

L

X

High-Z

Q

External

Read Cycle, Begin Burst

L

H

X

L

L-H High-Z

Write Cycle, Begin Burst

L

H

X

H

X

H

X

H

X

L-H

D

Q

Read Cycle, Begin Burst

L

H

L

Read Cycle, Begin Burst

L

H

L

L-H High-Z

L-H

L-H High-Z

L-H

L-H High-Z

Read Cycle, Continue Burst

Write Cycle, Continue Burst

Read Cycle, Suspend Burst

Write Cycle, Suspend Burst

X

H

X

H

X

H

X

H

X

H

Q

H

L

Q

H

X

L

L-H

D

Q

L

Current

H

L

H

L

L-H High-Z

L-H

L-H High-Z

Q

H

X

L-H

D

Write Cycle, Suspend Burst

L

Note:

1. X=Don't Care, 1=Logic HIGH, 0=Logic LOW.

2. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWS_[3:0].Writes may occur only on subsequent clocks

after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE

is a don't care for the remainder of the write cycle.

3. OE is asynchronous and is not sampled with the clock rise. During a read cycle DQ=High-Z when OE is inactive, and DQ=data when OE is active

5

PRELIMINARY

CY7C1346

Write Cycle Descriptions^{[1, 2, 3, 4]}

Function

GW

1

BWE

1

BW

X

1

BW

X

1

BW

X

1

BW

X

1

3

2

1

0

Read

1

0

Write Byte 0, DP

Write Byte 1, DP

1

0

1

0

1

0

1

0

1

Write Bytes 1, 0, DP , DP

1

0

1

0

1

Write Byte 2, DP

1

0

1

0

1

2

Write Bytes 2, 0, DP , DP

1

0

1

0

1

0

2

0

1

Write Bytes 2, 1, DP , DP

1

0

1

0

1

2

Write Bytes 2, 1, 0, DP , DP , DP

1

0

1

0

2

1

0

Write Byte 3, DP

1

0

1

3

Write Bytes 3, 0, DP , DP

1

0

1

0

3

0

Write Bytes 3, 1, DP , DP

1

0

1

0

1

3

Write Bytes 3, 1, 0, DP , DP , DP

1

0

1

0

3

1

Write Bytes 3, 2, DP , DP

1

0

1

3

2

Write Bytes 3, 2, 0, DP , DP , DP

1

0

1

0

3

2

0

1

Write Bytes 3, 2, 1, DP , DP , DP

1

0

1

3

2

Write All Bytes

1

0

X

Current into Outputs (LOW)......................................... 20 mA

Maximum Ratings

Static Discharge Voltage .......................................... >2001V

(per MIL-STD-883, Method 3015)

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Latch-Up Current.................................................... >200 mA

Storage Temperature ..................................... −65°C to +150°C

Ambient Temperature with

Power Applied.................................................. −55°C to +125°C

Operating Range

Ambient

Supply Voltage on V Relative to GND.........−0.5V to +4.6V

[6]

DD

Range

Com’l

Temperature

V

DD

DC Voltage Applied to Outputs

[5]

0°C to +70°C

3.3V −5%/+10%

in High Z State .....................................−0.5V to V

+ 0.5V

DDQ

[5]

DC Input Voltage ..................................−0.5V to V

DDQ

Notes:

4. When a write cycle is detected, all I/Os are three-stated, even during byte writes.

5. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.

6.

T_Ais the “instant on” case temperature.

6

PRELIMINARY

CY7C1346

Electrical Characteristics Over the Operating Range

Parameter

Description

Test Conditions

Min.

3.135

2.4

Max.

3.6

Unit

V

Power Supply Voltage

I/O Supply Voltage

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

CC

3.6

V

DDQ

V

= Min., I = −4.0 mA

V

OH

DD

OH

V

= Min., I = 8.0 mA

0.4

V

OL

V

2.0

–0.3

−5

V

+ 0.3V

DDQ

V

IH

IL

[7]

V

Input LOW Voltage

0.8

5

V

I

Input Load Current

GND ≤ V ≤ V

µA

X

I

DDQ

except ZZ and MODE

Input Current of MODE Input = V

Input = V

–30

–5

µA

SS

5

DDQ

SS

Input Current of ZZ

Input = V

30

5

DDQ

I

Output Leakage

Current

GND ≤ V ≤ V

Output Disabled

−5

OZ

I

DDQ,

V

Operating Supply

V

f = f

= Max., I

= 0 mA,

6-ns cycle, 166 MHz

7.5-ns cycle, 133 MHz

8.5-ns cycle, 117 MHz

10-ns cycle, 100 MHz

6-ns cycle, 166 MHz

7.5-ns cycle, 133 MHz

8.5-ns cycle, 117 MHz

10-ns cycle, 100 MHz

420

375

350

325

35

mA

µA

CC

DD

OUT

CYC

Current

= 1/t

MAX

I

Automatic CS

Power-Down

Current—TTL Inputs

Max. V , Device Deselected,

DD

V

f = f

SB1

≥ V or V ≤ V

IN

IH

IN

IL

30

= 1/t

MAX CYC

25

I

Automatic CS

Power-Down

Current—CMOS Inputs f = 0

Max. V , Device Deselected,

V

2.5

500

SB2

DD

≤ 0.3V or V > V

– 0.3V,

IN

DDQ

L Version

Automatic CS

Power-Down

Current—CMOS Inputs f = f

Max. V , Device Deselected, or 6-ns cycle, 166 MHz

V

10

18

mA

SB3

DD

≤ 0.3V or V > V

– 0.3V

IN

CYC

DDQ

7.5-ns cycle, 133 MHz

8.5-ns cycle, 117 MHz

10-ns cycle, 100 MHz

= 1/t

MAX

I

Automatic CS

Max. V , Device Deselected,

DD

SB4

Power-Down

V

≥ V or V ≤ V , f = 0

IN IH IN IL

Current—TTL Inputs

ZZ Mode Electrical Characteristics

Parameter

Description

Test Conditions

ZZ > V − 0.2V

Min

Max

Unit

I

Snooze mode

3

mA

CCZZ

DD

standby current

I

(L Version)

Snooze mode

standby current

ZZ > V − 0.2V

800

µA

ns

CCZZ

DD

t

Deviceoperationto

ZZ

ZZ > V − 0.2V

2t

CYC

ZZS

DD

t

ZZ recovery time

ZZ < 0.2V

2t

CYC

ZZREC

7

PRELIMINARY

CY7C1346

Capacitance^[7]

Parameter

Description

Test Conditions

T = 25°C, f = 1 MHz,

Max.

Unit

pF

C

Input Capacitance

6

8

IN

A

V

= 3.3V,

DD

Clock Input Capacitance

Input/Output Capacitance

pF

CLK

I/O

= 3.3V

DDQ

pF

AC Test Loads and Waveforms

R=317

Ω

3.3V

OUTPUT

[8]

OUTPUT

ALL INPUT PULSES

Z =50

Ω

0

3.0V

R =50

Ω

L

5 pF

R=351

Ω

GND

V = 1.5V

L

INCLUDING

JIG AND

SCOPE

(a)

(b)

Notes:

7. Tested initially and after any design or process changes that may affect these parameters.

8. Input waveform should have a slew rate of 1V/ns.

8

PRELIMINARY

CY7C1346

[9,10,11]

Switching Characteristics Over the Operating Range

-166

-133

-117

-100

Parameter

Description

Clock Cycle Time

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Unit

t

6

7.5

1.9

2.5

0.5

8.5

2.5

0.5

10

3.5

2.5

0.5

ns

CYC

CH

t

Clock HIGH

1.7

2.0

0.5

Clock LOW

CL

Address Set-Up Before CLK Rise

Address Hold After CLK Rise

Data Output Valid After CLK Rise

Data Output Hold After CLK Rise

ADSP, ADSC Set-Up Before CLK Rise

ADSP, ADSC Hold After CLK Rise

AS

AH

3.5

4

4.5

5.5

ns

CO

1.5

2.0

0.5

2.0

2.5

0.5

2.5

2.0

2.5

0.5

2.5

2.0

2.5

0.5

2.5

DOH

ADS

ADH

WES

BWE, GW, BW[1:0] Set-Up Before CLK

Rise

t

BWE, GW, BW[1:0] Hold After CLK

Rise

0.5

ns

WEH

t

ADV Set-Up Before CLK Rise

ADV Hold After CLK Rise

2.0

0.5

2.0

0.5

2.0

0.5

2.5

0.5

2.5

0.5

2.5

0.5

2.5

0.5

2.5

0.5

2.5

0.5

2.5

0.5

2.5

0.5

2.5

0.5

ns

ADVS

ADVH

DS

Data Input Set-Up Before CLK Rise

Data Input Hold After CLK Rise

Chip Select Set-Up

DH

CES

CEH

CHZ

CLZ

Chip Select Hold After CLK Rise

[10, 11]

Clock to High-Z

3.5

[10, 11]

Clock to Low-Z

0

[10, 11]

OE HIGH to Output High-Z

3.5

6

EOHZ

EOLZ

EOV

[10,11]

OE LOW to Output Low-Z

[10]

OE LOW to Output Valid

3.5

Notes:

9. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output

loading of the specified I_OL/I_OHand load capacitance. Shown in (a) and (b) of AC test loads.

10. t_CHZ, t_CLZ, t_EOV, t_EOLZ, and t_EOHZare specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from

steady-state voltage.

11. At any given voltage and temperature, t_EOHZis less than t_EOLZand t_CHZis less than t_CLZ

.

9

PRELIMINARY

CY7C1346

Switching Waveforms

Write Cycle Timing

Single Write

Burst Write

Pipelined Write

t

Unselected

CH

t

CYC

CLK

t

ADH

t

ADS

t

ADSP ignored with CE inactive

CL

1

ADSP

ADSC

ADV

t

ADS

t

ADVS

t

ADH

t

AS

ADVH

WD3

ADD

GW

WE

WD1

WD2

t

AH

t

WH

t

WH

t

WS

t

WS

t

CES

CEH

CE masks ADSP

1

CE

1

t

CEH

CES

Unselected with CE

2

CE

2

3

t

CES

t

CEH

OE

t

DH

t

DS

High-Z

Data-

In

3a

2a

2d

1a

2b

2c

WE is the combination of BWE & BW to define

x

a write cycle (see Write Cycle Descriptions table).

= UNDEFINED

= DON’T CARE

10

PRELIMINARY

CY7C1346

Switching Waveforms (continued)

Read Cycle Timing

Burst Read

Single Read

Unselected

t

CYC

CH

Pipelined Read

CLK

t

ADH

ADS

t

ADSP ignored with CE inactive

CL

1

ADSP

t

ADS

ADSC initiated read

ADSC

ADV

t

ADVS

t

Suspend Burst

ADH

t

ADVH

AS

ADD

GW

WE

RD3

RD1

RD2

t

AH

t

WS

t

WS

t

WH

t

CES

CEH

t

WH

CE masks ADSP

1

CE

1

2

Unselected with CE

2

t

CES

t

CEH

CE

OE

3

CES

t

DOE

t

CEH

t

EOHZ

t

DOH

t

CO

Data-

Out

2c

1a

3a

2d

2a

2b

t

CLZ

t

CHZ

WE is the combination of BWE & BW to define

x

a write cycle (see Write Cycle Descriptions table).

= DON’T CARE

= UNDEFINED

11

PRELIMINARY

CY7C1346

Switching Waveforms (continued)

Read/Write Cycle Timing

Single Read

Single Write

Unselected

Burst Read

t

CYC

t

CH

Pipelined Read

CLK

t

ADH

ADS

t

ADSP ignored with CE inactive

CL

1

ADSP

ADSC

ADV

t

ADS

t

ADVS

ADH

t

AS

t

ADVH

ADD

RD1

WD2

RD3

t

AH

GW

WE

t

WS

t

WS

WH

t

CES

t

CEH

WH

CE masks ADSP

1

CE

1

2

t

CES

t

CEH

CE

3

t

DOE

CES

t

CEH

OE

t

EOHZ

t

DS

t

DH

DOH

See Note.

2a

t

EOLZ

3b

Out

3c

Out

3a

Out

3d

Data-

In/Out

1a

2a

In

Out

t

CO

WE is the combination of BWE & BW to define

t

x

CHZ

a write cycle (see Write Cycle Descriptions table).

= UNDEFINED

= DON’T CARE

Note: Write data forwarded to outputs on read immediately

following a write.

12

PRELIMINARY

CY7C1346

Switching Waveforms (continued)

Pipeline Timing

t

CYC

CL

CH

CLK

t

AS

C

E

F

G

H

B

D

A

ADD

t

ADH

ADS

ADSP

ADSC

ADV

t

CEH

CES

CE

1

CE

t

WES

WEH

WE

ADSP ignored

with CE HIGH

1

OE

t

CLZ

Data

D (E)

D (F)

D (H)

D(C)

Q(A)

D (G)

Q(B)

Q(C)

Q(D)

In/Out

CDV

t

DOH

t

CHZ

Device originally

deselected

WE is the combination of BWE, BWS

, and GW to define a write cycle (see Write Cycle Descriptions table).

[1:0]

CE is the combination of CE and CE . All chip selects need to be active in order to select

2

3

the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X,

Qx stands for Data-out X

= UNDEFINED

= DON’T CARE

13

PRELIMINARY

CY7C1346

Switching Waveforms (continued)

[12,13]

ZZ Mode Timing

CLK

ADSP

ADSC

HIGH

CE

1

2

LOW

CE

HIGH

CE

ZZ

3

t

ZZS

I

CC

I

(active)

CC

t

ZZREC

I

CCZZ

I/Os

Three-state

Notes:

12. Device must be deselected when entering ZZ mode. See Cycle Description for all possible signal conditions to deselect the device.

13. I/Os are in three-state when exiting ZZ sleep mode.

14

PRELIMINARY

CY7C1346

Ordering Information

Speed

Package

Name

Operating

Range

(MHz)

166

133

117

100

Ordering Code

Package Type

CY7C1346–166AC

CY7C1346L–166AC

CY7C1346–133AC

CY7C1346L–133AC

CY7C1346–117AC

CY7C1346L–117AC

CY7C1346–100AC

CY7C1346L–100AC

A101

100-Lead Thin Quad Flat Pack

Commercial

Document #: 38-00726

Package Diagram

100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101

51-85050-A

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.


型号：	CY7C1346L-166AC
厂家：	CYPRESS
描述：	Cache SRAM, 64KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 静态存储器
文件：	总15页 (文件大小：482K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY7C1346L-166AC [CYPRESS]

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